1 /***************************************************************************//**
2 * \file cy_ble_clk.c
3 * \version 3.70
4 *
5 * \brief
6 * This driver provides the source code for API BLE ECO clock.
7 *
8 ********************************************************************************
9 * \copyright
10 * Copyright 2017-2020 Cypress Semiconductor Corporation
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the "License");
14 * you may not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * http://www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an "AS IS" BASIS,
21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 *******************************************************************************/
25
26 #include "cy_device.h"
27
28 #if defined (CY_IP_MXBLESS) && defined (CY_IP_MXS40IOSS)
29
30 #include "cy_syslib.h"
31 #include "cy_gpio.h"
32 #include "cy_syspm.h"
33 #include "cy_ble_clk.h"
34 #include "cy_sysclk.h"
35
36 /* C binding of definitions if building with C++ compiler */
37 #ifdef __cplusplus
38 extern "C" {
39 #endif /* __cplusplus */
40
41 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 10.4', 1, \
42 'Checked manually. Type cast to uint8_t made intentionally.')
43
44 CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 10.8', 3, \
45 'Checked manually. Type cast to uint8_t made intentionally.')
46
47 /*******************************************************************************
48 * Internal functions
49 *******************************************************************************/
50
51 #if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE)))
52 static cy_en_ble_eco_status_t Cy_BLE_HAL_RcbRegRead(uint16_t addr, uint16_t *data);
53 static cy_en_ble_eco_status_t Cy_BLE_HAL_RcbRegWrite(uint16_t addr, uint16_t data);
54 static cy_en_ble_eco_status_t Cy_BLE_HAL_EcoSetTrim(uint32_t trim, uint32_t startUpTime);
55 static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq_t bleEcoFreq,
56 cy_en_ble_eco_sys_clk_div_t sysClkDiv);
57 #endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */
58
59
60 /*******************************************************************************
61 * Internal Defines
62 *******************************************************************************/
63
64 /** \cond INTERNAL */
65
66 #define CY_BLE_PORT2_CFG_VAL (0x66666666u)
67 #define CY_BLE_PORT3_CFG_VAL (0x66EEE666u)
68 #define CY_BLE_PORT4_CFG_VAL (0x6666E666u)
69
70 #define CY_BLE_PORT_CFG_OUT_VAL (0xFFFF0000u)
71
72 #define CY_BLE_PORT2_HSIOM_SEL0 (0x1C1C1C1Cu)
73 #define CY_BLE_PORT2_HSIOM_SEL1 (0x1C1C1C1Cu)
74 #define CY_BLE_PORT3_HSIOM_SEL0 (0x1A1A1A1Cu)
75 #define CY_BLE_PORT3_HSIOM_SEL1 (0x00001A1Au)
76 #define CY_BLE_PORT4_HSIOM_SEL0 (0x1C001A1Au)
77 #define CY_BLE_PORT4_HSIOM_SEL1 (0x00000000u)
78
79 #define CY_BLE_GPIO_PRT2 (&((GPIO_Type*)(cy_device->gpioBase))->PRT[2])
80 #define CY_BLE_GPIO_PRT3 (&((GPIO_Type*)(cy_device->gpioBase))->PRT[3])
81 #define CY_BLE_GPIO_PRT4 (&((GPIO_Type*)(cy_device->gpioBase))->PRT[4])
82 #define CY_BLE_GPIO_VDD_ACTIVE (((GPIO_Type*)(cy_device->gpioBase))->VDD_ACTIVE)
83
84 #define CY_BLE_DEFAULT_OSC_STARTUP_DELAY_LF (25u)
85 #define CY_BLE_DEFAULT_CAP_TRIM_VALUE (32u)
86 #define CY_BLE_DEFAULT_ECO_FREQ (CY_BLE_BLESS_ECO_FREQ_32MHZ)
87 #define CY_BLE_DEFAULT_ECO_DIV (CY_BLE_SYS_ECO_CLK_DIV_4)
88
89 #define CY_BLE_DEFAULT_HVLDO_STARTUP_DELAY (6UL)
90 #define CY_BLE_DEFAULT_ISOLATE_DEASSERT_DELAY (0UL)
91 #define CY_BLE_DEFAULT_ACT_TO_SWITCH_DELAY (0UL)
92 #define CY_BLE_DEFAULT_HVLDO_DISABLE_DELAY (1UL)
93 #define CY_BLE_DEFAULT_ACT_STARTUP_DELAY (10UL)
94 #define CY_BLE_DEFAULT_DIG_LDO_STARTUP_DELAY (0UL)
95 #define CY_BLE_DEFAULT_XTAL_DISABLE_DELAY (1UL)
96 #define CY_BLE_DEFAULT_DIG_LDO_DISABLE_DELAY (0UL)
97 #define CY_BLE_DEFAULT_VDDR_STABLE_DELAY (1UL)
98 #define CY_BLE_DEFAULT_RCB_CTRL_LEAD (0x2UL)
99 #define CY_BLE_DEFAULT_RCB_CTRL_LAG (0x2UL)
100 #define CY_BLE_DEFAULT_RCB_CTRL_DIV (0x1UL) /* LL 8 MHz / 2 */
101 #define CY_BLE_DEFAULT_RCB_CTRL_FREQ (4000000UL) /* Default RCB clock is 4 MHz */
102 #define CY_BLE_DEFAULT_ECO_CLK_FREQ_32MHZ (32000000UL)
103 #define CY_BLE_DEFAULT_ECO_CLK_FREQ_16MHZ (16000000UL)
104 #define CY_BLE_MXD_RADIO_CLK_BUF_EN_VAL (CY_BLE_PMU_MODE_TRANSITION_REG_CLK_ANA_DIG_EN_BIT | \
105 CY_BLE_PMU_MODE_TRANSITION_REG_RST_ACT_N_BIT)
106 #define CY_BLE_MXD_RADIO_DIG_CLK_OUT_EN_VAL (CY_BLE_PMU_PMU_CTRL_REG_CLK_CMOS_SEL_BIT)
107
108 /* Radio registers */
109 #define CY_BLE_RCB_FIFO_WR_BIT_MASK (0x8000UL)
110 #define CY_BLE_RCB_FIFO_WR_BIT_SHIFT (16U)
111
112 #define CY_BLE_PMU_MODE_TRANSITION_REG (0x1e02U)
113 #define CY_BLE_PMU_MODE_TRANSITION_REG_CLK_ANA_DIG_EN_BIT (uint16_t)(1UL << 12U)
114 #define CY_BLE_PMU_MODE_TRANSITION_REG_RST_ACT_N_BIT (uint16_t)(1UL << 11U)
115
116 #define CY_BLE_PMU_PMU_CTRL_REG (0x1e03u)
117 #define CY_BLE_PMU_PMU_CTRL_REG_CLK_CMOS_SEL_BIT (uint16_t)(1UL << 10U)
118
119 #define CY_BLE_RF_DCXO_CFG_REG (0x1e08U)
120 #define CY_BLE_RF_DCXO_CFG_REG_DCXO_CAP_SHIFT (1U)
121 #define CY_BLE_RF_DCXO_CFG_REG_DCXO_CAP_MASK (0xffUL)
122 #define CY_BLE_RF_DCXO_CFG_REG_VALUE (0x1001U)
123
124 #define CY_BLE_RF_DCXO_CFG2_REG (0x1e0fU)
125 #define CY_BLE_RF_DCXO_CFG2_REG_VALUE (0x6837U)
126
127 #define CY_BLE_RF_DCXO_BUF_CFG_REG (0x1e09U)
128 #define CY_BLE_RF_DCXO_BUF_CFG_REG_XTAL_32M_SEL_BIT (uint16_t)(1UL << 6U)
129 #define CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_SHIFT (4U)
130 #define CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_MASK (0x03UL)
131 #define CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_SHIFT (0U)
132 #define CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_MASK (0x0fUL)
133
134 #define CY_BLE_RF_LDO_CFG_REG (0x1e07u)
135 #define CY_BLE_RF_LDO_CFG_REG_LDO10_CFG_SHIFT (11U)
136 #define CY_BLE_RF_LDO_CFG_REG_LDO10_CFG_MASK (0x03UL)
137 #define CY_BLE_RF_LDO_CFG_REG_LDO_ACT_CFG_SHIFT (7U)
138 #define CY_BLE_RF_LDO_CFG_REG_LDO_ACT_CFG_MASK (0x15UL)
139 #define CY_BLE_RF_LDO_CFG_REG_LDO_IF_CFG_SHIFT (5U)
140 #define CY_BLE_RF_LDO_CFG_REG_LDO_IF_CFG_MASK (0x03UL)
141
142 #define CY_BLE_RF_LDO_EN_REG (0x1e06U)
143 #define CY_BLE_RF_LDO_EN_REG_LDO_RF_CFG_SHIFT (6U)
144 #define CY_BLE_RF_LDO_EN_REG_LDO_RF_CFG_MASK (0x03UL)
145
146 #define CY_BLE_DELAY_TIME (1U) /* in us */
147 #define CY_BLE_RCB_TIMEOUT (1000U / CY_BLE_DELAY_TIME) /* 1ms */
148 #define CY_BLE_VIO_TIMEOUT (2000U / CY_BLE_DELAY_TIME) /* 2ms */
149 #define CY_BLE_ACT_TIMEOUT (950000U / CY_BLE_DELAY_TIME) /* 950ms */
150 #define CY_BLE_RCB_RETRIES (10U)
151
152
153 /* Range for inputs parameters */
154 #define CY_BLE_ECO_XTAL_START_UP_TIME_MAX ((uint32_t) (4593.75 / 31.25))
155 #define CY_BLE_ECO_XTAL_START_UP_TIME_MIN ((uint32_t) (400 / 31.25))
156
157 #define CY_BLE_ECO_CLOAD_MIN ((uint32_t) ((7.5 - 7.5)/0.075))
158 #define CY_BLE_ECO_CLOAD_MAX ((uint32_t) ((26.325 - 7.5)/0.075))
159
160 #define CY_BLE_ECO_SET_TRIM_DELAY_COEF (32U)
161 #define CY_BLE_ECO_LDO_ENABLE_DELAY (64U)
162 /** \endcond */
163
164
165 /*******************************************************************************
166 * Function Name: Cy_BLE_EcoConfigure
167 ****************************************************************************//**
168 *
169 * This API configures and enables the BLE ECO clock.
170 *
171 * If Cy_BLE_Enable() API is called by the application, the stack enables
172 * the BLE ECO clock automatically with the following default parameters:
173 *
174 * Parameter | Value
175 * -------------------- | -----------
176 * ECO Frequency | CY_BLE_DEFAULT_ECO_FREQ
177 * Divider | CY_BLE_DEFAULT_ECO_DIV
178 * Startup time | CY_BLE_DEFAULT_OSC_STARTUP_DELAY_LF
179 * Load cap | CY_BLE_DEFAULT_CAP_TRIM_VALUE
180 *
181 * If there is a need to start the BLE ECO with non-default parameters, call the
182 * Cy_BLE_EcoConfigure() function with the custom configuration each time before calling
183 * the Cy_BLE_Enable() function.
184 *
185 * This clock is stopped in Deep Sleep and Hibernate power modes.
186 *
187 * \param freq - Operating frequency of the crystal, type of
188 * \ref cy_en_ble_eco_freq_t.
189 *
190 * \param sysClkDiv - System divider for ECO clock, type of
191 * \ref cy_en_ble_eco_sys_clk_div_t.
192 *
193 * \param cLoad - ECO crystal load capacitance in multiple of 0.075pF
194 * (pF_from_user valid range: 7.5...26.625pF)
195 * cLoad = ((pF_from_user - 7.5)/0.075)
196 *
197 * \param xtalStartUpTime - ECO crystal startup time in multiple of 31.25us
198 * (startup_time_from_user valid range: 400...4593.75us)
199 * xtalStartUpTime = startup_time_from_user/31.25
200 *
201 * \param voltageReg - BLE Voltage regulator, type of
202 * \ref cy_en_ble_eco_voltage_reg_t.
203 *
204 * \return
205 * \ref cy_en_ble_eco_status_t : The return value indicates if the function
206 * succeeded or failed. The possible error codes:
207 *
208 * Error Codes | Description
209 * -------------------- | -----------
210 * CY_BLE_ECO_SUCCESS | The function completed successfully.
211 * CY_BLE_ECO_BAD_PARAM | The wrong input parameter.
212 * CY_BLE_ECO_RCB_CONTROL_LL | The RCB Control is with BLE Link Layer.
213 * CY_BLE_ECO_ALREADY_STARTED | The BLE ECO clock is already started.
214 * CY_BLE_ECO_HARDWARE_ERROR | The RCB or BLE ECO operation failed.
215 *
216 * For the PSoC 64 devices, there are possible situations when the function returns
217 * the PRA error status code. This is because for PSoC 64 devices, the function
218 * uses the PRA driver to change the frequency value on the protected side.
219 * Refer to \ref cy_en_pra_status_t for more details.
220 *
221 * \funcusage
222 * \snippet bleclk/snippet/main.c BLE ECO clock API: Cy_BLE_EcoConfigure()
223 *
224 * \sideeffect
225 * The I/O pins will be automatically unfrozen coming out of Hibernate when
226 * the BLE ECO is in use.
227 *
228 * \note Limitation: Do not call this API if the BLE is executed with LPM.
229 * There is a risk that when the Cy_BLE_EcoConfigure() function is called on
230 * one core, the BLE is in Deep Sleep mode on the other core. It will cause
231 * a fault hard exception.
232 *
233 *******************************************************************************/
Cy_BLE_EcoConfigure(cy_en_ble_eco_freq_t freq,cy_en_ble_eco_sys_clk_div_t sysClkDiv,uint32_t cLoad,uint32_t xtalStartUpTime,cy_en_ble_eco_voltage_reg_t voltageReg)234 cy_en_ble_eco_status_t Cy_BLE_EcoConfigure(cy_en_ble_eco_freq_t freq, cy_en_ble_eco_sys_clk_div_t sysClkDiv,
235 uint32_t cLoad, uint32_t xtalStartUpTime, cy_en_ble_eco_voltage_reg_t voltageReg)
236 {
237 cy_en_ble_eco_status_t status = CY_BLE_ECO_SUCCESS;
238
239 #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE)))
240 cy_stc_pra_ble_eco_config_t ecoConfigParams;
241 ecoConfigParams.freq = freq;
242 ecoConfigParams.sysClkDiv = sysClkDiv;
243 ecoConfigParams.cLoad = cLoad;
244 ecoConfigParams.xtalStartUpTime = xtalStartUpTime;
245 ecoConfigParams.voltageReg = voltageReg;
246
247 status = (cy_en_ble_eco_status_t)CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_SECURE_ONLY,
248 CY_PRA_BLE_CLK_FUNC_ECO_CONFIGURE,
249 &ecoConfigParams);
250 #else
251 uint32_t temp = 0UL;
252
253 if( (freq > CY_BLE_BLESS_ECO_FREQ_32MHZ) || (sysClkDiv > CY_BLE_SYS_ECO_CLK_DIV_8) ||
254 (xtalStartUpTime > CY_BLE_ECO_XTAL_START_UP_TIME_MAX) || (xtalStartUpTime < CY_BLE_ECO_XTAL_START_UP_TIME_MIN) ||
255 (cLoad > CY_BLE_ECO_CLOAD_MAX))
256 {
257 status = CY_BLE_ECO_BAD_PARAM;
258 }
259 else
260 {
261 /* Unfreeze IO after Hibernate */
262 if(Cy_SysPm_GetIoFreezeStatus())
263 {
264 Cy_SysPm_IoUnfreeze();
265 }
266
267 if(Cy_BLE_EcoIsEnabled())
268 {
269 status = CY_BLE_ECO_ALREADY_STARTED;
270 }
271 else
272 {
273 /* HAL Initialization */
274 Cy_BLE_HAL_Init();
275
276 /* BLESS MT Delays configuration */
277 BLE_BLESS_MT_DELAY_CFG =
278 (uint32_t)(CY_BLE_DEFAULT_HVLDO_STARTUP_DELAY << BLE_BLESS_MT_DELAY_CFG_HVLDO_STARTUP_DELAY_Pos) |
279 (uint32_t)(CY_BLE_DEFAULT_ISOLATE_DEASSERT_DELAY << BLE_BLESS_MT_DELAY_CFG_ISOLATE_DEASSERT_DELAY_Pos) |
280 (uint32_t)(CY_BLE_DEFAULT_ACT_TO_SWITCH_DELAY << BLE_BLESS_MT_DELAY_CFG_ACT_TO_SWITCH_DELAY_Pos) |
281 (uint32_t)(CY_BLE_DEFAULT_HVLDO_DISABLE_DELAY << BLE_BLESS_MT_DELAY_CFG_HVLDO_DISABLE_DELAY_Pos);
282
283 BLE_BLESS_MT_DELAY_CFG2 =
284 (uint32_t)(xtalStartUpTime << BLE_BLESS_MT_DELAY_CFG2_OSC_STARTUP_DELAY_LF_Pos) |
285 (uint32_t)(CY_BLE_DEFAULT_ACT_STARTUP_DELAY << BLE_BLESS_MT_DELAY_CFG2_ACT_STARTUP_DELAY_Pos) |
286 (uint32_t)(CY_BLE_DEFAULT_DIG_LDO_STARTUP_DELAY << BLE_BLESS_MT_DELAY_CFG2_DIG_LDO_STARTUP_DELAY_Pos);
287
288 BLE_BLESS_MT_DELAY_CFG3 =
289 (uint32_t)(CY_BLE_DEFAULT_XTAL_DISABLE_DELAY << BLE_BLESS_MT_DELAY_CFG3_XTAL_DISABLE_DELAY_Pos) |
290 (uint32_t)(CY_BLE_DEFAULT_DIG_LDO_DISABLE_DELAY << BLE_BLESS_MT_DELAY_CFG3_DIG_LDO_DISABLE_DELAY_Pos) |
291 (uint32_t)(CY_BLE_DEFAULT_VDDR_STABLE_DELAY << BLE_BLESS_MT_DELAY_CFG3_VDDR_STABLE_DELAY_Pos);
292
293 /* RCB Initialization
294 * Check if the RCB Control is with LL.
295 */
296 if((BLE_RCB_RCBLL_CTRL & BLE_RCB_RCBLL_CTRL_RCBLL_CTRL_Msk) != 0U)
297 {
298 status = CY_BLE_ECO_RCB_CONTROL_LL;
299 }
300 else
301 {
302 uint32_t rcbDivider = 0UL;
303
304 /* If clock source for RCB is PeriClk */
305 if((BLE_BLESS_LL_CLK_EN & BLE_BLESS_LL_CLK_EN_SEL_RCB_CLK_Msk) == 0U)
306 {
307 uint32_t periClkFreqHz = Cy_SysClk_ClkPeriGetFrequency();
308
309 if(periClkFreqHz > CY_BLE_DEFAULT_RCB_CTRL_FREQ)
310 {
311 rcbDivider = (periClkFreqHz / CY_BLE_DEFAULT_RCB_CTRL_FREQ) - 1U;
312 }
313 }
314 else
315 {
316 rcbDivider = CY_BLE_DEFAULT_RCB_CTRL_DIV;
317 }
318
319 /* Configure default RCB Parameters. */
320 BLE_RCB_CTRL |= (BLE_RCB_CTRL_ENABLED_Msk |
321 BLE_RCB_CTRL_RX_CLK_EDGE_Msk |
322 (CY_BLE_DEFAULT_RCB_CTRL_LEAD << BLE_RCB_CTRL_LEAD_Pos) |
323 (CY_BLE_DEFAULT_RCB_CTRL_LAG << BLE_RCB_CTRL_LAG_Pos) |
324 ((rcbDivider > 0U) ? ((rcbDivider << BLE_RCB_CTRL_DIV_Pos) |
325 BLE_RCB_CTRL_DIV_ENABLED_Msk) : 0U));
326
327 /* If user uses SIMO Buck, enable Buck2 in hardware mode for BLE */
328 #if (defined (SRSS_BUCKCTL_PRESENT) && (SRSS_BUCKCTL_PRESENT == 1u))
329 if((Cy_SysPm_SimoBuckIsEnabled()) && (voltageReg == CY_BLE_ECO_VOLTAGE_REG_AUTO))
330 {
331 Cy_SysPm_BuckSetVoltage2(CY_SYSPM_BUCK_OUT2_VOLTAGE_1_3V, true);
332 Cy_SysPm_BuckSetVoltage2HwControl(true);
333 }
334 else /* Configure BLE LDO if SIMO Buck2 is not enabled */
335 {
336 BLE_BLESS_MISC_EN_CTRL |= (BLE_BLESS_MISC_EN_CTRL_ACT_REG_EN_CTRL_Msk |
337 BLE_BLESS_MISC_EN_CTRL_BUCK_EN_CTRL_Msk);
338 }
339 #else
340 BLE_BLESS_MISC_EN_CTRL |= (BLE_BLESS_MISC_EN_CTRL_ACT_REG_EN_CTRL_Msk |
341 BLE_BLESS_MISC_EN_CTRL_BUCK_EN_CTRL_Msk);
342 #endif
343
344 /* Enable the VIO supply and LDO in standby mode for slow ramp */
345 temp = BLE_BLESS_MT_CFG;
346 temp |= BLE_BLESS_MT_CFG_HVLDO_BYPASS_Msk |
347 BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_BYPASS_Msk |
348 BLE_BLESS_MT_CFG_HVLDO_EN_Msk |
349 BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_EN_Msk;
350 BLE_BLESS_MT_CFG = temp;
351 Cy_SysLib_DelayUs(CY_BLE_ECO_LDO_ENABLE_DELAY);
352
353 if((BLE_BLESS_MT_VIO_CTRL & BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Msk) == 0U)
354 {
355 /* Enable LDO */
356 BLE_BLESS_MT_VIO_CTRL = BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Msk;
357
358 /* Wait for 64us after turning HVLDO ON */
359 Cy_SysLib_DelayUs(CY_BLE_ECO_LDO_ENABLE_DELAY);
360
361 /* Enable LDO Delayed */
362 BLE_BLESS_MT_VIO_CTRL = BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_Msk |
363 BLE_BLESS_MT_VIO_CTRL_SRSS_SWITCH_EN_DLY_Msk;
364 /* Wait for 64us */
365 Cy_SysLib_DelayUs(CY_BLE_ECO_LDO_ENABLE_DELAY);
366 }
367
368 /* Disable override mode and let hardware take control of HVLDO */
369 temp &= ~(BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_BYPASS_Msk |
370 BLE_BLESS_MT_CFG_OVERRIDE_HVLDO_EN_Msk);
371 BLE_BLESS_MT_CFG = temp;
372
373 /* Wait for the VIO stable key write operation to complete */
374 {
375 uint32_t timeout = CY_BLE_VIO_TIMEOUT;
376 while(((CY_BLE_GPIO_VDD_ACTIVE & 0x10U) == 0U) && (timeout > 0U))
377 {
378 timeout--;
379 Cy_SysLib_DelayUs(CY_BLE_DELAY_TIME);
380 }
381 if(timeout == 0U)
382 {
383 status = CY_BLE_ECO_HARDWARE_ERROR;
384 }
385 }
386
387
388 if(status == CY_BLE_ECO_SUCCESS)
389 {
390 uint32_t timeout = CY_BLE_ACT_TIMEOUT;
391
392 /* Clear the BLERD_ACTIVE_INTR */
393 BLE_BLESS_INTR_STAT |= BLE_BLESS_INTR_STAT_BLERD_ACTIVE_INTR_Msk;
394
395
396 #if (defined (SRSS_BUCKCTL_PRESENT) && (SRSS_BUCKCTL_PRESENT == 1u))
397 if((!Cy_SysPm_SimoBuckOutputIsEnabled(CY_SYSPM_BUCK_VRF)) || (voltageReg == CY_BLE_ECO_VOLTAGE_REG_BLESSLDO))
398 {
399 temp |= BLE_BLESS_MT_CFG_ACT_LDO_NOT_BUCK_Msk;
400 }
401 #else
402 temp |= BLE_BLESS_MT_CFG_ACT_LDO_NOT_BUCK_Msk;
403 #endif
404 /* Enable Radio */
405 temp |= BLE_BLESS_MT_CFG_ENABLE_BLERD_Msk;
406
407 /* Disable ECO in DeepSleep mode */
408 temp &= ~BLE_BLESS_MT_CFG_DPSLP_ECO_ON_Msk;
409 BLE_BLESS_MT_CFG = temp;
410
411 /* Wait for BLESS in ACTIVE state */
412 while(((BLE_BLESS_MT_STATUS & BLE_BLESS_MT_STATUS_BLESS_STATE_Msk) == 0U) && (timeout > 0U))
413 {
414 timeout--;
415 Cy_SysLib_DelayUs(CY_BLE_DELAY_TIME);
416 }
417 if(timeout == 0U)
418 {
419 status = CY_BLE_ECO_HARDWARE_ERROR;
420 }
421 }
422
423 if(status == CY_BLE_ECO_SUCCESS)
424 {
425 /* Enable and configure radio clock */
426 status = Cy_BLE_HAL_MxdRadioEnableClocks(freq, sysClkDiv);
427 }
428
429 if(status == CY_BLE_ECO_SUCCESS)
430 {
431 /* Set Load capacitance */
432 status = Cy_BLE_HAL_EcoSetTrim(cLoad, xtalStartUpTime);
433 }
434 }
435 }
436 }
437 #endif /* ((CY_CPU_CORTEX_M4) && (!defined(CY_DEVICE_SECURE))) */
438
439 return(status);
440 }
441
442
443 /*******************************************************************************
444 * Function Name: Cy_BLE_EcoReset
445 ****************************************************************************//**
446 *
447 * This API resets and disables the BLE ECO clock.
448 *
449 * \return
450 * None
451 *
452 *******************************************************************************/
Cy_BLE_EcoReset(void)453 void Cy_BLE_EcoReset(void)
454 {
455 /* Initiate Soft Reset */
456 #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE)))
457 CY_PRA_FUNCTION_CALL_VOID_VOID(CY_PRA_MSG_TYPE_SECURE_ONLY, CY_PRA_BLE_CLK_FUNC_ECO_RESET);
458 #else
459 BLE_BLESS_LL_CLK_EN |= BLE_BLESS_LL_CLK_EN_BLESS_RESET_Msk;
460 cy_BleEcoClockFreqHz = 0UL; /* Reset the BLE ECO frequency */
461 #endif
462 }
463
464
465 /*******************************************************************************
466 * Function Name: Cy_BLE_EcoStart
467 ****************************************************************************//**
468 *
469 * This API configure and enables the BLE ECO clock.
470 *
471 * This API is used as the PSoC Creator wrapper function. This function is not
472 * recommended for new designs. Please use Cy_BLE_EcoConfigure()
473 * instead of this function.
474 *
475 * \param config
476 * The pointer to the configuration structure cy_stc_ble_eco_config_t.
477 *
478 * \return
479 * \ref cy_en_ble_eco_status_t : The return value indicates if the function
480 * succeeded or failed. The possible error codes:
481 *
482 * Error Codes | Description
483 * -------------------- | -----------
484 * CY_BLE_ECO_SUCCESS | The function completed successfully.
485 * CY_BLE_ECO_BAD_PARAM | The wrong input parameter.
486 * CY_BLE_ECO_RCB_CONTROL_LL | The RCB Control is with BLE Link Layer.
487 * CY_BLE_ECO_ALREADY_STARTED | The BLE ECO clock is already started.
488 * CY_BLE_ECO_HARDWARE_ERROR | The RCB or BLE ECO operation failed.
489 *
490 * \sideeffect
491 * The I/O pins will be automatically unfrozen coming out of Hibernate when
492 * the BLE ECO is in use.
493 *
494 * \note Limitation: Do not call this API if the BLE is executed with LPM.
495 * There is a risk that when the Cy_BLE_EcoStart() function is called on one
496 * core, the BLE is in Deep Sleep mode on the other core. It will cause
497 * a fault hard exception.
498 *
499 *******************************************************************************/
Cy_BLE_EcoStart(const cy_stc_ble_eco_config_t * config)500 cy_en_ble_eco_status_t Cy_BLE_EcoStart(const cy_stc_ble_eco_config_t *config)
501 {
502 cy_en_ble_eco_status_t retValue = CY_BLE_ECO_BAD_PARAM;
503 if(config != NULL)
504 {
505 /* Configure BLE ECO clock */
506 retValue = Cy_BLE_EcoConfigure(config->ecoFreq, config->ecoSysDiv, (uint32_t) config->loadCap,
507 (uint32_t) config->ecoXtalStartUpTime, CY_BLE_ECO_VOLTAGE_REG_AUTO);
508 }
509 return (retValue);
510 }
511
512
513 /*******************************************************************************
514 * Function Name: Cy_BLE_EcoStop
515 ****************************************************************************//**
516 *
517 * This API stops BLE ECO clock.
518 *
519 * This API is used as the PSoC Creator wrapper function. This function is not
520 * recommended for new designs. Please use Cy_BLE_EcoReset() instead of this
521 * function.
522 *
523 * \return
524 * None
525 *
526 *******************************************************************************/
Cy_BLE_EcoStop(void)527 void Cy_BLE_EcoStop(void)
528 {
529 Cy_BLE_EcoReset();
530 }
531
532
533 /*******************************************************************************
534 * Function Name: Cy_BLE_HAL_Init
535 ****************************************************************************//**
536 *
537 * Initializes the BLESS port.
538 *
539 * \return
540 * None
541 *
542 *******************************************************************************/
Cy_BLE_HAL_Init(void)543 void Cy_BLE_HAL_Init(void)
544 {
545 /* Configures pins for BLESS */
546 const cy_stc_gpio_prt_config_t port2_cfg =
547 {
548 0UL, /* out */
549 0UL, /* ntrMask */
550 0UL, /* intrCfg */
551 CY_BLE_PORT2_CFG_VAL, /* cfg */
552 0UL, /* cfgIn */
553 CY_BLE_PORT_CFG_OUT_VAL, /* cfgOut */
554 0UL, /* cfgSIO */
555 CY_BLE_PORT2_HSIOM_SEL0, /* sel0Active */
556 CY_BLE_PORT2_HSIOM_SEL1 /* sel1Active */
557 };
558
559 const cy_stc_gpio_prt_config_t port3_cfg =
560 {
561 0UL, /* out */
562 0UL, /* ntrMask */
563 0UL, /* intrCfg */
564 CY_BLE_PORT3_CFG_VAL, /* cfg */
565 0UL, /* cfgIn */
566 CY_BLE_PORT_CFG_OUT_VAL, /* cfgOut */
567 0UL, /* cfgSIO */
568 CY_BLE_PORT3_HSIOM_SEL0, /* sel0Active */
569 CY_BLE_PORT3_HSIOM_SEL1 /* sel1Active */
570 };
571
572 const cy_stc_gpio_prt_config_t port4_cfg =
573 {
574 0UL, /* out */
575 0UL, /* ntrMask */
576 0UL, /* intrCfg */
577 CY_BLE_PORT4_CFG_VAL, /* cfg */
578 0UL, /* cfgIn */
579 CY_BLE_PORT_CFG_OUT_VAL, /* cfgOut */
580 0UL, /* cfgSIO */
581 CY_BLE_PORT4_HSIOM_SEL0, /* sel0Active */
582 CY_BLE_PORT4_HSIOM_SEL1 /* sel1Active */
583 };
584
585 (void)Cy_GPIO_Port_Init(CY_BLE_GPIO_PRT2, &port2_cfg);
586 (void)Cy_GPIO_Port_Init(CY_BLE_GPIO_PRT3, &port3_cfg);
587 (void)Cy_GPIO_Port_Init(CY_BLE_GPIO_PRT4, &port4_cfg);
588
589 }
590
591
592 #if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE)))
593 /*******************************************************************************
594 * Function Name: Cy_BLE_HAL_RcbRegRead
595 ****************************************************************************//**
596 *
597 * Reads Radio register.
598 *
599 * \param addr : Register address.
600 * \param *data: Register data (output parameter).
601 *
602 * \return
603 * \ref cy_en_ble_eco_status_t : Return value indicates if the function succeeded or
604 * failed. The following are possible error codes:
605 *
606 * Error Codes | Description
607 * -------------------- | -----------
608 * CY_BLE_ECO_SUCCESS | On successful operation.
609 * CY_BLE_ECO_HARDWARE_ERROR | If RCB operation failed
610 *
611 *******************************************************************************/
Cy_BLE_HAL_RcbRegRead(uint16_t addr,uint16_t * data)612 static cy_en_ble_eco_status_t Cy_BLE_HAL_RcbRegRead(uint16_t addr, uint16_t *data)
613 {
614 cy_en_ble_eco_status_t status = CY_BLE_ECO_HARDWARE_ERROR;
615 uint32_t timeout = CY_BLE_RCB_TIMEOUT;
616 uint32_t temp = (uint32_t)((CY_BLE_RCB_FIFO_WR_BIT_MASK | addr) << CY_BLE_RCB_FIFO_WR_BIT_SHIFT);
617
618 /* Write Address to the RCB */
619 BLE_RCB_TX_FIFO_WR = temp;
620
621 /* Wait for Data. */
622 while(((BLE_RCB_INTR & BLE_RCB_INTR_RCB_DONE_Msk) == 0U) && (timeout > 0U))
623 {
624 timeout--;
625 Cy_SysLib_DelayUs(CY_BLE_DELAY_TIME);
626 }
627
628 if(timeout > 0U)
629 {
630 BLE_RCB_INTR |= BLE_RCB_INTR_RCB_DONE_Msk;
631 *data = (uint16_t)BLE_RCB_RX_FIFO_RD;
632 status = CY_BLE_ECO_SUCCESS;
633 }
634
635 return(status);
636 }
637
638
639 /*******************************************************************************
640 * Function Name: Cy_BLE_HAL_RcbRegWrite
641 ****************************************************************************//**
642 *
643 * Writes Radio register.
644 *
645 * \param addr: Register address.
646 * \param data: Register data.
647 *
648 * \return
649 * \ref cy_en_ble_eco_status_t : Return value indicates if the function succeeded or
650 * failed. The following are possible error codes:
651 *
652 * Error Codes | Description
653 * -------------------- | -----------
654 * CY_BLE_ECO_SUCCESS | On successful operation.
655 * CY_BLE_ECO_HARDWARE_ERROR | If RCB operation failed
656 *
657 *******************************************************************************/
Cy_BLE_HAL_RcbRegWrite(uint16_t addr,uint16_t data)658 static cy_en_ble_eco_status_t Cy_BLE_HAL_RcbRegWrite(uint16_t addr, uint16_t data)
659 {
660 cy_en_ble_eco_status_t status = CY_BLE_ECO_HARDWARE_ERROR;
661 uint32_t timeout = CY_BLE_RCB_TIMEOUT;
662 uint32_t temp = ((uint32_t)((~CY_BLE_RCB_FIFO_WR_BIT_MASK & addr) << CY_BLE_RCB_FIFO_WR_BIT_SHIFT)) | data;
663
664 BLE_RCB_TX_FIFO_WR = temp;
665
666 /* Wait for RCB done. */
667 while(((BLE_RCB_INTR & BLE_RCB_INTR_RCB_DONE_Msk) == 0U) && (timeout > 0U))
668 {
669 timeout--;
670 Cy_SysLib_DelayUs(CY_BLE_DELAY_TIME);
671 }
672
673 if(timeout > 0U)
674 {
675 BLE_RCB_INTR |= BLE_RCB_INTR_RCB_DONE_Msk;
676 status = CY_BLE_ECO_SUCCESS;
677 }
678
679 return(status);
680 }
681
682
683 /*******************************************************************************
684 * Function Name: Cy_BLE_HAL_EcoSetTrim
685 ****************************************************************************//**
686 *
687 * Sets ECO trim value.
688 *
689 * \param trim : Trim value.
690 * \param startUpTime : Start up time delay.
691 *
692 * \return
693 * \ref cy_en_ble_eco_status_t : Return value indicates if the function succeeded or
694 * failed. The following are possible error codes:
695 *
696 * Error Codes | Description
697 * -------------------- | -----------
698 * CY_BLE_ECO_SUCCESS | On successful operation.
699 * CY_BLE_ECO_HARDWARE_ERROR | If RCB operation failed
700 *
701 *******************************************************************************/
Cy_BLE_HAL_EcoSetTrim(uint32_t trim,uint32_t startUpTime)702 static cy_en_ble_eco_status_t Cy_BLE_HAL_EcoSetTrim(uint32_t trim, uint32_t startUpTime)
703 {
704 uint16_t reg = CY_BLE_RF_DCXO_CFG_REG_VALUE;
705 cy_en_ble_eco_status_t status;
706
707 /* Load the new CAP TRIM value */
708 reg |= (uint16_t)((uint16_t)trim << CY_BLE_RF_DCXO_CFG_REG_DCXO_CAP_SHIFT);
709
710 /* Write the new value to the register */
711 status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_RF_DCXO_CFG_REG, reg);
712
713 if(status == CY_BLE_ECO_SUCCESS)
714 {
715 /* Write the new value to the CFG2 register */
716 status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_RF_DCXO_CFG2_REG, CY_BLE_RF_DCXO_CFG2_REG_VALUE);
717 }
718
719 Cy_SysLib_DelayUs((uint16_t)startUpTime * CY_BLE_ECO_SET_TRIM_DELAY_COEF);
720
721 return(status);
722 }
723
724
725 /*******************************************************************************
726 * Function Name: Cy_BLE_HAL_MxdRadioEnableClocks
727 ****************************************************************************//**
728 *
729 * Enables and configures radio clock.
730 *
731 * \param bleEcoFreq : ECO Frequency.
732 * \param sysClkDiv : System divider for ECO clock.
733 *
734 * \return
735 * \ref cy_en_ble_eco_status_t : Return value indicates if the function succeeded or
736 * failed. The following are possible error codes:
737 *
738 * Error Codes | Description
739 * -------------------- | -----------
740 * CY_BLE_ECO_SUCCESS | On successful operation.
741 * CY_BLE_ECO_HARDWARE_ERROR | If RCB operation failed
742 *
743 *******************************************************************************/
Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq_t bleEcoFreq,cy_en_ble_eco_sys_clk_div_t sysClkDiv)744 static cy_en_ble_eco_status_t Cy_BLE_HAL_MxdRadioEnableClocks(cy_en_ble_eco_freq_t bleEcoFreq,
745 cy_en_ble_eco_sys_clk_div_t sysClkDiv)
746 {
747 uint16_t temp;
748 uint32_t retries = CY_BLE_RCB_RETRIES;
749 cy_en_ble_eco_status_t status;
750
751 /* De-assert active domain reset and enable clock buffer in MXD Radio */
752 do
753 {
754 status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_PMU_MODE_TRANSITION_REG, CY_BLE_MXD_RADIO_CLK_BUF_EN_VAL);
755 if(status == CY_BLE_ECO_SUCCESS)
756 {
757 status = Cy_BLE_HAL_RcbRegRead(CY_BLE_PMU_MODE_TRANSITION_REG, &temp);
758 }
759 if(retries > 0U)
760 {
761 retries--;
762 }
763 else
764 {
765 status = CY_BLE_ECO_HARDWARE_ERROR;
766 }
767 }
768 while((status == CY_BLE_ECO_SUCCESS) && (temp != CY_BLE_MXD_RADIO_CLK_BUF_EN_VAL));
769
770 /* Check if ECO clock output is enabled
771 * In MXD_VER2, ECO clock is stopped on overwriting this bit */
772 if(status == CY_BLE_ECO_SUCCESS)
773 {
774 retries = CY_BLE_RCB_RETRIES;
775 status = Cy_BLE_HAL_RcbRegRead(CY_BLE_PMU_PMU_CTRL_REG, &temp);
776 if((status == CY_BLE_ECO_SUCCESS) && ((temp & CY_BLE_MXD_RADIO_DIG_CLK_OUT_EN_VAL) == 0U))
777 {
778 /* Enable digital ECO clock output from MXD Radio to BLESS */
779 do
780 {
781 status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_PMU_PMU_CTRL_REG, CY_BLE_MXD_RADIO_DIG_CLK_OUT_EN_VAL);
782 if(status == CY_BLE_ECO_SUCCESS)
783 {
784 status = Cy_BLE_HAL_RcbRegRead(CY_BLE_PMU_PMU_CTRL_REG, &temp);
785 }
786 if(retries > 0U)
787 {
788 retries--;
789 }
790 else
791 {
792 status = CY_BLE_ECO_HARDWARE_ERROR;
793 }
794 }
795 while((status == CY_BLE_ECO_SUCCESS) && (temp != CY_BLE_MXD_RADIO_DIG_CLK_OUT_EN_VAL));
796 }
797 }
798
799 /* Configure ECO clock frequency and clock divider in MXD Radio */
800 if(status == CY_BLE_ECO_SUCCESS)
801 {
802 /* Read the MXD Radio register */
803 status = Cy_BLE_HAL_RcbRegRead(CY_BLE_RF_DCXO_BUF_CFG_REG, &temp);
804 }
805 if(status == CY_BLE_ECO_SUCCESS)
806 {
807 uint16_t blerdDivider;
808 uint16_t ecoSysDivider;
809 uint16_t blellDivider = 0U;
810
811 /* Clear clock divider and select amp buffer output bits */
812 temp &= CY_LO16(~((CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_MASK << CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_SHIFT) |
813 (CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_MASK << CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_SHIFT)));
814
815 /* Total ECO divider consist of divider located on BLERD and BLESS divider
816 * Set BLERD divider to maximum value taking in to account that 8 MHz is required for BLELL.
817 * BLELL clock frequency is set to 8 MHz irrespective of the crystal value.
818 */
819 if(bleEcoFreq == CY_BLE_BLESS_ECO_FREQ_32MHZ)
820 {
821 if(sysClkDiv >= CY_BLE_SYS_ECO_CLK_DIV_4)
822 {
823 blerdDivider = (uint16_t)CY_BLE_MXD_RADIO_CLK_DIV_4;
824 }
825 else
826 {
827 blerdDivider = (uint16_t)sysClkDiv;
828 blellDivider = (uint16_t)CY_BLE_MXD_RADIO_CLK_DIV_4 - blerdDivider;
829 }
830 temp |= CY_BLE_RF_DCXO_BUF_CFG_REG_XTAL_32M_SEL_BIT;
831 temp |= ((uint16_t)CY_BLE_MXD_RADIO_CLK_BUF_AMP_32M_LARGE << (uint16_t)CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_SHIFT);
832
833 /* Update cy_BleEcoClockFreqHz for the proper Cy_SysLib_Delay functionality */
834 cy_BleEcoClockFreqHz = CY_BLE_DEFAULT_ECO_CLK_FREQ_32MHZ / (1UL << (uint16_t)sysClkDiv);
835 }
836 else
837 {
838 if(sysClkDiv >= CY_BLE_SYS_ECO_CLK_DIV_2)
839 {
840 blerdDivider = (uint16_t)CY_BLE_MXD_RADIO_CLK_DIV_2;
841 }
842 else
843 {
844 blerdDivider = (uint16_t)sysClkDiv;
845 blellDivider = (uint16_t)CY_BLE_MXD_RADIO_CLK_DIV_2 - blerdDivider;
846 }
847 temp &= (uint16_t) ~CY_BLE_RF_DCXO_BUF_CFG_REG_XTAL_32M_SEL_BIT;
848 temp |= (uint16_t)((uint32_t)CY_BLE_MXD_RADIO_CLK_BUF_AMP_16M_LARGE << CY_BLE_RF_DCXO_BUF_CFG_REG_BUF_AMP_SEL_SHIFT);
849
850 /* Update cy_BleEcoClockFreqHz for the proper Cy_SysLib_Delay functionality */
851 cy_BleEcoClockFreqHz = CY_BLE_DEFAULT_ECO_CLK_FREQ_16MHZ / (1UL << (uint16_t)sysClkDiv);
852 }
853
854 temp |= (uint16_t)(blerdDivider << CY_BLE_RF_DCXO_BUF_CFG_REG_CLK_DIV_SHIFT);
855
856 /* Write the MXD Radio register */
857 status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_RF_DCXO_BUF_CFG_REG, temp);
858
859 /* Reduce BLESS divider by BLERD divider value */
860 ecoSysDivider = (uint16_t)sysClkDiv - blerdDivider;
861 temp = (uint16_t)(ecoSysDivider & BLE_BLESS_XTAL_CLK_DIV_CONFIG_SYSCLK_DIV_Msk);
862 temp |= (uint16_t)(blellDivider << BLE_BLESS_XTAL_CLK_DIV_CONFIG_LLCLK_DIV_Pos);
863
864 /* Set clock divider */
865 BLE_BLESS_XTAL_CLK_DIV_CONFIG = temp;
866 }
867
868 /* Update RADIO LDO trim values */
869 if((Cy_SysLib_GetDeviceRevision() != CY_SYSLIB_DEVICE_REV_0A) && (SFLASH->RADIO_LDO_TRIMS != 0U))
870 {
871 if(status == CY_BLE_ECO_SUCCESS)
872 {
873 status = Cy_BLE_HAL_RcbRegRead(CY_BLE_RF_LDO_CFG_REG, &temp);
874 }
875
876 if(status == CY_BLE_ECO_SUCCESS)
877 {
878 /* Update LDO_IF value */
879 temp &= (uint16_t)~((uint16_t) ((uint16_t)CY_BLE_RF_LDO_CFG_REG_LDO_IF_CFG_MASK << CY_BLE_RF_LDO_CFG_REG_LDO_IF_CFG_SHIFT));
880 temp |= (uint16_t)(((SFLASH->RADIO_LDO_TRIMS & SFLASH_RADIO_LDO_TRIMS_LDO_IF_Msk) >>
881 SFLASH_RADIO_LDO_TRIMS_LDO_IF_Pos) << CY_BLE_RF_LDO_CFG_REG_LDO_IF_CFG_SHIFT);
882
883 /* Update LDO_ACT value */
884 temp &= (uint16_t)~((uint16_t) ((uint16_t)CY_BLE_RF_LDO_CFG_REG_LDO_ACT_CFG_MASK << CY_BLE_RF_LDO_CFG_REG_LDO_ACT_CFG_SHIFT));
885 temp |= (uint16_t)(((SFLASH->RADIO_LDO_TRIMS & SFLASH_RADIO_LDO_TRIMS_LDO_ACT_Msk) >>
886 SFLASH_RADIO_LDO_TRIMS_LDO_ACT_Pos) << CY_BLE_RF_LDO_CFG_REG_LDO_ACT_CFG_SHIFT);
887
888 /* Update LDO_DIG value */
889 temp &= (uint16_t)~((uint16_t) ((uint16_t)CY_BLE_RF_LDO_CFG_REG_LDO10_CFG_MASK << CY_BLE_RF_LDO_CFG_REG_LDO10_CFG_SHIFT));
890 temp |= (uint16_t)(((SFLASH->RADIO_LDO_TRIMS & SFLASH_RADIO_LDO_TRIMS_LDO_DIG_Msk) >>
891 SFLASH_RADIO_LDO_TRIMS_LDO_DIG_Pos) << CY_BLE_RF_LDO_CFG_REG_LDO10_CFG_SHIFT);
892
893 status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_RF_LDO_CFG_REG, temp);
894 }
895
896 if(status == CY_BLE_ECO_SUCCESS)
897 {
898 status = Cy_BLE_HAL_RcbRegRead(CY_BLE_RF_LDO_EN_REG, &temp);
899 }
900
901 if(status == CY_BLE_ECO_SUCCESS)
902 {
903 /* Update LDO_LNA value */
904 temp &= (uint16_t)~(CY_BLE_RF_LDO_EN_REG_LDO_RF_CFG_MASK << CY_BLE_RF_LDO_EN_REG_LDO_RF_CFG_SHIFT);
905 temp |= (uint16_t)(((SFLASH->RADIO_LDO_TRIMS & SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Msk) >>
906 SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Pos) << CY_BLE_RF_LDO_EN_REG_LDO_RF_CFG_SHIFT);
907
908 status = Cy_BLE_HAL_RcbRegWrite(CY_BLE_RF_LDO_EN_REG, temp);
909 }
910 }
911 return(status);
912 }
913 #endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */
914
915 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 10.8')
916
917 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 10.4')
918
919 #ifdef __cplusplus
920 }
921 #endif /* __cplusplus */
922 #endif /* defined(CY_IP_MXBLESS) */
923
924
925 /* [] END OF FILE */
926
