1 /***************************************************************************//** 2 * \file cyip_sdhc.h 3 * 4 * \brief 5 * SDHC IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_SDHC_H_ 28 #define _CYIP_SDHC_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * SDHC 34 *******************************************************************************/ 35 36 #define SDHC_WRAP_SECTION_SIZE 0x00000020UL 37 #define SDHC_CORE_SECTION_SIZE 0x00001000UL 38 #define SDHC_SECTION_SIZE 0x00010000UL 39 40 /** 41 * \brief MMIO at SDHC wrapper level (SDHC_WRAP) 42 */ 43 typedef struct { 44 __IOM uint32_t CTL; /*!< 0x00000000 Top level wrapper control */ 45 __IM uint32_t RESERVED[7]; 46 } SDHC_WRAP_Type; /*!< Size = 32 (0x20) */ 47 48 /** 49 * \brief MMIO for Synopsys Mobile Storage Host Controller IP (SDHC_CORE) 50 */ 51 typedef struct { 52 __IOM uint32_t SDMASA_R; /*!< 0x00000000 SDMA System Address register */ 53 __IOM uint16_t BLOCKSIZE_R; /*!< 0x00000004 Block Size register */ 54 __IOM uint16_t BLOCKCOUNT_R; /*!< 0x00000006 16-bit Block Count register */ 55 __IOM uint32_t ARGUMENT_R; /*!< 0x00000008 Argument register */ 56 __IOM uint16_t XFER_MODE_R; /*!< 0x0000000C Transfer Mode register */ 57 __IOM uint16_t CMD_R; /*!< 0x0000000E Command register */ 58 __IM uint32_t RESP01_R; /*!< 0x00000010 Response Register 0/1 */ 59 __IM uint32_t RESP23_R; /*!< 0x00000014 Response Register 2/3 */ 60 __IM uint32_t RESP45_R; /*!< 0x00000018 Response Register 4/5 */ 61 __IM uint32_t RESP67_R; /*!< 0x0000001C Response Register 6/7 */ 62 __IOM uint32_t BUF_DATA_R; /*!< 0x00000020 Buffer Data Port Register */ 63 __IM uint32_t PSTATE_REG; /*!< 0x00000024 Present State Register */ 64 __IOM uint8_t HOST_CTRL1_R; /*!< 0x00000028 Host Control 1 Register */ 65 __IOM uint8_t PWR_CTRL_R; /*!< 0x00000029 Power Control Register */ 66 __IOM uint8_t BGAP_CTRL_R; /*!< 0x0000002A Block Gap Control Register */ 67 __IOM uint8_t WUP_CTRL_R; /*!< 0x0000002B Wakeup Control Register */ 68 __IOM uint16_t CLK_CTRL_R; /*!< 0x0000002C Clock Control Register */ 69 __IOM uint8_t TOUT_CTRL_R; /*!< 0x0000002E Timeout Control Register */ 70 __IOM uint8_t SW_RST_R; /*!< 0x0000002F Software Reset Register */ 71 __IOM uint16_t NORMAL_INT_STAT_R; /*!< 0x00000030 Normal Interrupt Status Register */ 72 __IOM uint16_t ERROR_INT_STAT_R; /*!< 0x00000032 Error Interrupt Status Register */ 73 __IOM uint16_t NORMAL_INT_STAT_EN_R; /*!< 0x00000034 Normal Interrupt Status Enable Register */ 74 __IOM uint16_t ERROR_INT_STAT_EN_R; /*!< 0x00000036 Error Interrupt Status Enable Register */ 75 __IOM uint16_t NORMAL_INT_SIGNAL_EN_R; /*!< 0x00000038 Normal Interrupt Signal Enable Register */ 76 __IOM uint16_t ERROR_INT_SIGNAL_EN_R; /*!< 0x0000003A Error Interrupt Signal Enable Register */ 77 __IM uint16_t AUTO_CMD_STAT_R; /*!< 0x0000003C Auto CMD Status Register */ 78 __IOM uint16_t HOST_CTRL2_R; /*!< 0x0000003E Host Control 2 Register */ 79 __IM uint32_t CAPABILITIES1_R; /*!< 0x00000040 Capabilities 1 Register - 0 to 31 */ 80 __IM uint32_t CAPABILITIES2_R; /*!< 0x00000044 Capabilities Register - 32 to 63 */ 81 __IM uint32_t CURR_CAPABILITIES1_R; /*!< 0x00000048 Current Capabilities Register - 0 to 31 */ 82 __IM uint32_t CURR_CAPABILITIES2_R; /*!< 0x0000004C Maximum Current Capabilities Register - 32 to 63 */ 83 __OM uint16_t FORCE_AUTO_CMD_STAT_R; /*!< 0x00000050 Force Event Register for Auto CMD Error Status register */ 84 __IOM uint16_t FORCE_ERROR_INT_STAT_R; /*!< 0x00000052 Force Event Register for Error Interrupt Status */ 85 __IM uint8_t ADMA_ERR_STAT_R; /*!< 0x00000054 ADMA Error Status Register */ 86 __IM uint8_t RESERVED[3]; 87 __IOM uint32_t ADMA_SA_LOW_R; /*!< 0x00000058 ADMA System Address Register - Low */ 88 __IM uint32_t RESERVED1[7]; 89 __IOM uint32_t ADMA_ID_LOW_R; /*!< 0x00000078 ADMA3 Integrated Descriptor Address Register - Low */ 90 __IM uint16_t RESERVED2[65]; 91 __IM uint16_t HOST_CNTRL_VERS_R; /*!< 0x000000FE Host Controller Version */ 92 __IM uint32_t RESERVED3[32]; 93 __IM uint32_t CQVER; /*!< 0x00000180 Command Queuing Version register */ 94 __IM uint32_t CQCAP; /*!< 0x00000184 Command Queuing Capabilities register */ 95 __IOM uint32_t CQCFG; /*!< 0x00000188 Command Queuing Configuration register */ 96 __IOM uint32_t CQCTL; /*!< 0x0000018C Command Queuing Control register */ 97 __IOM uint32_t CQIS; /*!< 0x00000190 Command Queuing Interrupt Status register */ 98 __IOM uint32_t CQISE; /*!< 0x00000194 Command Queuing Interrupt Status Enable register */ 99 __IOM uint32_t CQISGE; /*!< 0x00000198 Command Queuing Interrupt signal enable register */ 100 __IOM uint32_t CQIC; /*!< 0x0000019C Command Queuing Interrupt Coalescing register */ 101 __IOM uint32_t CQTDLBA; /*!< 0x000001A0 Command Queuing Task Descriptor List Base Address register */ 102 __IM uint32_t RESERVED4; 103 __IOM uint32_t CQTDBR; /*!< 0x000001A8 Command Queuing DoorBell register */ 104 __IOM uint32_t CQTCN; /*!< 0x000001AC Command Queuing TaskClear Notification register */ 105 __IM uint32_t CQDQS; /*!< 0x000001B0 Device queue status register */ 106 __IM uint32_t CQDPT; /*!< 0x000001B4 Device pending tasks register */ 107 __IOM uint32_t CQTCLR; /*!< 0x000001B8 Command Queuing DoorBell register */ 108 __IM uint32_t RESERVED5; 109 __IOM uint32_t CQSSC1; /*!< 0x000001C0 CQ Send Status Configuration 1 register */ 110 __IOM uint32_t CQSSC2; /*!< 0x000001C4 CQ Send Status Configuration 2 register */ 111 __IM uint32_t CQCRDCT; /*!< 0x000001C8 Command response for direct command register */ 112 __IM uint32_t RESERVED6; 113 __IOM uint32_t CQRMEM; /*!< 0x000001D0 Command response mode error mask register */ 114 __IM uint32_t CQTERRI; /*!< 0x000001D4 CQ Task Error Information register */ 115 __IM uint32_t CQCRI; /*!< 0x000001D8 CQ Command response index */ 116 __IM uint32_t CQCRA; /*!< 0x000001DC CQ Command response argument register */ 117 __IM uint32_t RESERVED7[200]; 118 __IM uint32_t MSHC_VER_ID_R; /*!< 0x00000500 MSHC version */ 119 __IM uint32_t MSHC_VER_TYPE_R; /*!< 0x00000504 MSHC version type */ 120 __IOM uint8_t MSHC_CTRL_R; /*!< 0x00000508 MSHC Control register */ 121 __IM uint8_t RESERVED8[7]; 122 __IOM uint8_t MBIU_CTRL_R; /*!< 0x00000510 MBIU Control register */ 123 __IM uint8_t RESERVED9[27]; 124 __IOM uint16_t EMMC_CTRL_R; /*!< 0x0000052C eMMC Control register */ 125 __IOM uint16_t BOOT_CTRL_R; /*!< 0x0000052E eMMC Boot Control register */ 126 __IM uint32_t GP_IN_R; /*!< 0x00000530 General Purpose Input register */ 127 __IOM uint32_t GP_OUT_R; /*!< 0x00000534 General Purpose Output register */ 128 __IM uint32_t RESERVED10[690]; 129 } SDHC_CORE_Type; /*!< Size = 4096 (0x1000) */ 130 131 /** 132 * \brief SD/eMMC Host Controller (SDHC) 133 */ 134 typedef struct { 135 SDHC_WRAP_Type WRAP; /*!< 0x00000000 MMIO at SDHC wrapper level */ 136 __IM uint32_t RESERVED[1016]; 137 SDHC_CORE_Type CORE; /*!< 0x00001000 MMIO for Synopsys Mobile Storage Host Controller IP */ 138 } SDHC_Type; /*!< Size = 8192 (0x2000) */ 139 140 141 /* SDHC_WRAP.CTL */ 142 #define SDHC_WRAP_CTL_ENABLE_Pos 31UL 143 #define SDHC_WRAP_CTL_ENABLE_Msk 0x80000000UL 144 145 146 /* SDHC_CORE.SDMASA_R */ 147 #define SDHC_CORE_SDMASA_R_BLOCKCNT_SDMASA_Pos 0UL 148 #define SDHC_CORE_SDMASA_R_BLOCKCNT_SDMASA_Msk 0xFFFFFFFFUL 149 /* SDHC_CORE.BLOCKSIZE_R */ 150 #define SDHC_CORE_BLOCKSIZE_R_XFER_BLOCK_SIZE_Pos 0UL 151 #define SDHC_CORE_BLOCKSIZE_R_XFER_BLOCK_SIZE_Msk 0xFFFUL 152 #define SDHC_CORE_BLOCKSIZE_R_SDMA_BUF_BDARY_Pos 12UL 153 #define SDHC_CORE_BLOCKSIZE_R_SDMA_BUF_BDARY_Msk 0x7000UL 154 /* SDHC_CORE.BLOCKCOUNT_R */ 155 #define SDHC_CORE_BLOCKCOUNT_R_BLOCK_CNT_Pos 0UL 156 #define SDHC_CORE_BLOCKCOUNT_R_BLOCK_CNT_Msk 0xFFFFUL 157 /* SDHC_CORE.ARGUMENT_R */ 158 #define SDHC_CORE_ARGUMENT_R_ARGUMENT_Pos 0UL 159 #define SDHC_CORE_ARGUMENT_R_ARGUMENT_Msk 0xFFFFFFFFUL 160 /* SDHC_CORE.XFER_MODE_R */ 161 #define SDHC_CORE_XFER_MODE_R_DMA_ENABLE_Pos 0UL 162 #define SDHC_CORE_XFER_MODE_R_DMA_ENABLE_Msk 0x1UL 163 #define SDHC_CORE_XFER_MODE_R_BLOCK_COUNT_ENABLE_Pos 1UL 164 #define SDHC_CORE_XFER_MODE_R_BLOCK_COUNT_ENABLE_Msk 0x2UL 165 #define SDHC_CORE_XFER_MODE_R_AUTO_CMD_ENABLE_Pos 2UL 166 #define SDHC_CORE_XFER_MODE_R_AUTO_CMD_ENABLE_Msk 0xCUL 167 #define SDHC_CORE_XFER_MODE_R_DATA_XFER_DIR_Pos 4UL 168 #define SDHC_CORE_XFER_MODE_R_DATA_XFER_DIR_Msk 0x10UL 169 #define SDHC_CORE_XFER_MODE_R_MULTI_BLK_SEL_Pos 5UL 170 #define SDHC_CORE_XFER_MODE_R_MULTI_BLK_SEL_Msk 0x20UL 171 #define SDHC_CORE_XFER_MODE_R_RESP_TYPE_Pos 6UL 172 #define SDHC_CORE_XFER_MODE_R_RESP_TYPE_Msk 0x40UL 173 #define SDHC_CORE_XFER_MODE_R_RESP_ERR_CHK_ENABLE_Pos 7UL 174 #define SDHC_CORE_XFER_MODE_R_RESP_ERR_CHK_ENABLE_Msk 0x80UL 175 #define SDHC_CORE_XFER_MODE_R_RESP_INT_DISABLE_Pos 8UL 176 #define SDHC_CORE_XFER_MODE_R_RESP_INT_DISABLE_Msk 0x100UL 177 /* SDHC_CORE.CMD_R */ 178 #define SDHC_CORE_CMD_R_RESP_TYPE_SELECT_Pos 0UL 179 #define SDHC_CORE_CMD_R_RESP_TYPE_SELECT_Msk 0x3UL 180 #define SDHC_CORE_CMD_R_SUB_CMD_FLAG_Pos 2UL 181 #define SDHC_CORE_CMD_R_SUB_CMD_FLAG_Msk 0x4UL 182 #define SDHC_CORE_CMD_R_CMD_CRC_CHK_ENABLE_Pos 3UL 183 #define SDHC_CORE_CMD_R_CMD_CRC_CHK_ENABLE_Msk 0x8UL 184 #define SDHC_CORE_CMD_R_CMD_IDX_CHK_ENABLE_Pos 4UL 185 #define SDHC_CORE_CMD_R_CMD_IDX_CHK_ENABLE_Msk 0x10UL 186 #define SDHC_CORE_CMD_R_DATA_PRESENT_SEL_Pos 5UL 187 #define SDHC_CORE_CMD_R_DATA_PRESENT_SEL_Msk 0x20UL 188 #define SDHC_CORE_CMD_R_CMD_TYPE_Pos 6UL 189 #define SDHC_CORE_CMD_R_CMD_TYPE_Msk 0xC0UL 190 #define SDHC_CORE_CMD_R_CMD_INDEX_Pos 8UL 191 #define SDHC_CORE_CMD_R_CMD_INDEX_Msk 0x3F00UL 192 /* SDHC_CORE.RESP01_R */ 193 #define SDHC_CORE_RESP01_R_RESP01_Pos 0UL 194 #define SDHC_CORE_RESP01_R_RESP01_Msk 0xFFFFFFFFUL 195 /* SDHC_CORE.RESP23_R */ 196 #define SDHC_CORE_RESP23_R_RESP23_Pos 0UL 197 #define SDHC_CORE_RESP23_R_RESP23_Msk 0xFFFFFFFFUL 198 /* SDHC_CORE.RESP45_R */ 199 #define SDHC_CORE_RESP45_R_RESP45_Pos 0UL 200 #define SDHC_CORE_RESP45_R_RESP45_Msk 0xFFFFFFFFUL 201 /* SDHC_CORE.RESP67_R */ 202 #define SDHC_CORE_RESP67_R_RESP67_Pos 0UL 203 #define SDHC_CORE_RESP67_R_RESP67_Msk 0xFFFFFFFFUL 204 /* SDHC_CORE.BUF_DATA_R */ 205 #define SDHC_CORE_BUF_DATA_R_BUF_DATA_Pos 0UL 206 #define SDHC_CORE_BUF_DATA_R_BUF_DATA_Msk 0xFFFFFFFFUL 207 /* SDHC_CORE.PSTATE_REG */ 208 #define SDHC_CORE_PSTATE_REG_CMD_INHIBIT_Pos 0UL 209 #define SDHC_CORE_PSTATE_REG_CMD_INHIBIT_Msk 0x1UL 210 #define SDHC_CORE_PSTATE_REG_CMD_INHIBIT_DAT_Pos 1UL 211 #define SDHC_CORE_PSTATE_REG_CMD_INHIBIT_DAT_Msk 0x2UL 212 #define SDHC_CORE_PSTATE_REG_DAT_LINE_ACTIVE_Pos 2UL 213 #define SDHC_CORE_PSTATE_REG_DAT_LINE_ACTIVE_Msk 0x4UL 214 #define SDHC_CORE_PSTATE_REG_DAT_7_4_Pos 4UL 215 #define SDHC_CORE_PSTATE_REG_DAT_7_4_Msk 0xF0UL 216 #define SDHC_CORE_PSTATE_REG_WR_XFER_ACTIVE_Pos 8UL 217 #define SDHC_CORE_PSTATE_REG_WR_XFER_ACTIVE_Msk 0x100UL 218 #define SDHC_CORE_PSTATE_REG_RD_XFER_ACTIVE_Pos 9UL 219 #define SDHC_CORE_PSTATE_REG_RD_XFER_ACTIVE_Msk 0x200UL 220 #define SDHC_CORE_PSTATE_REG_BUF_WR_ENABLE_Pos 10UL 221 #define SDHC_CORE_PSTATE_REG_BUF_WR_ENABLE_Msk 0x400UL 222 #define SDHC_CORE_PSTATE_REG_BUF_RD_ENABLE_Pos 11UL 223 #define SDHC_CORE_PSTATE_REG_BUF_RD_ENABLE_Msk 0x800UL 224 #define SDHC_CORE_PSTATE_REG_CARD_INSERTED_Pos 16UL 225 #define SDHC_CORE_PSTATE_REG_CARD_INSERTED_Msk 0x10000UL 226 #define SDHC_CORE_PSTATE_REG_CARD_STABLE_Pos 17UL 227 #define SDHC_CORE_PSTATE_REG_CARD_STABLE_Msk 0x20000UL 228 #define SDHC_CORE_PSTATE_REG_CARD_DETECT_PIN_LEVEL_Pos 18UL 229 #define SDHC_CORE_PSTATE_REG_CARD_DETECT_PIN_LEVEL_Msk 0x40000UL 230 #define SDHC_CORE_PSTATE_REG_WR_PROTECT_SW_LVL_Pos 19UL 231 #define SDHC_CORE_PSTATE_REG_WR_PROTECT_SW_LVL_Msk 0x80000UL 232 #define SDHC_CORE_PSTATE_REG_DAT_3_0_Pos 20UL 233 #define SDHC_CORE_PSTATE_REG_DAT_3_0_Msk 0xF00000UL 234 #define SDHC_CORE_PSTATE_REG_CMD_LINE_LVL_Pos 24UL 235 #define SDHC_CORE_PSTATE_REG_CMD_LINE_LVL_Msk 0x1000000UL 236 #define SDHC_CORE_PSTATE_REG_HOST_REG_VOL_Pos 25UL 237 #define SDHC_CORE_PSTATE_REG_HOST_REG_VOL_Msk 0x2000000UL 238 #define SDHC_CORE_PSTATE_REG_CMD_ISSU_ERR_Pos 27UL 239 #define SDHC_CORE_PSTATE_REG_CMD_ISSU_ERR_Msk 0x8000000UL 240 #define SDHC_CORE_PSTATE_REG_SUB_CMD_STAT_Pos 28UL 241 #define SDHC_CORE_PSTATE_REG_SUB_CMD_STAT_Msk 0x10000000UL 242 /* SDHC_CORE.HOST_CTRL1_R */ 243 #define SDHC_CORE_HOST_CTRL1_R_LED_CTRL_Pos 0UL 244 #define SDHC_CORE_HOST_CTRL1_R_LED_CTRL_Msk 0x1UL 245 #define SDHC_CORE_HOST_CTRL1_R_DAT_XFER_WIDTH_Pos 1UL 246 #define SDHC_CORE_HOST_CTRL1_R_DAT_XFER_WIDTH_Msk 0x2UL 247 #define SDHC_CORE_HOST_CTRL1_R_HIGH_SPEED_EN_Pos 2UL 248 #define SDHC_CORE_HOST_CTRL1_R_HIGH_SPEED_EN_Msk 0x4UL 249 #define SDHC_CORE_HOST_CTRL1_R_DMA_SEL_Pos 3UL 250 #define SDHC_CORE_HOST_CTRL1_R_DMA_SEL_Msk 0x18UL 251 #define SDHC_CORE_HOST_CTRL1_R_EXT_DAT_XFER_Pos 5UL 252 #define SDHC_CORE_HOST_CTRL1_R_EXT_DAT_XFER_Msk 0x20UL 253 #define SDHC_CORE_HOST_CTRL1_R_CARD_DETECT_TEST_LVL_Pos 6UL 254 #define SDHC_CORE_HOST_CTRL1_R_CARD_DETECT_TEST_LVL_Msk 0x40UL 255 #define SDHC_CORE_HOST_CTRL1_R_CARD_DETECT_SIG_SEL_Pos 7UL 256 #define SDHC_CORE_HOST_CTRL1_R_CARD_DETECT_SIG_SEL_Msk 0x80UL 257 /* SDHC_CORE.PWR_CTRL_R */ 258 #define SDHC_CORE_PWR_CTRL_R_SD_BUS_PWR_VDD1_Pos 0UL 259 #define SDHC_CORE_PWR_CTRL_R_SD_BUS_PWR_VDD1_Msk 0x1UL 260 #define SDHC_CORE_PWR_CTRL_R_SD_BUS_VOL_VDD1_Pos 1UL 261 #define SDHC_CORE_PWR_CTRL_R_SD_BUS_VOL_VDD1_Msk 0xEUL 262 /* SDHC_CORE.BGAP_CTRL_R */ 263 #define SDHC_CORE_BGAP_CTRL_R_STOP_BG_REQ_Pos 0UL 264 #define SDHC_CORE_BGAP_CTRL_R_STOP_BG_REQ_Msk 0x1UL 265 #define SDHC_CORE_BGAP_CTRL_R_CONTINUE_REQ_Pos 1UL 266 #define SDHC_CORE_BGAP_CTRL_R_CONTINUE_REQ_Msk 0x2UL 267 #define SDHC_CORE_BGAP_CTRL_R_RD_WAIT_CTRL_Pos 2UL 268 #define SDHC_CORE_BGAP_CTRL_R_RD_WAIT_CTRL_Msk 0x4UL 269 #define SDHC_CORE_BGAP_CTRL_R_INT_AT_BGAP_Pos 3UL 270 #define SDHC_CORE_BGAP_CTRL_R_INT_AT_BGAP_Msk 0x8UL 271 /* SDHC_CORE.WUP_CTRL_R */ 272 #define SDHC_CORE_WUP_CTRL_R_WUP_CARD_INT_Pos 0UL 273 #define SDHC_CORE_WUP_CTRL_R_WUP_CARD_INT_Msk 0x1UL 274 #define SDHC_CORE_WUP_CTRL_R_WUP_CARD_INSERT_Pos 1UL 275 #define SDHC_CORE_WUP_CTRL_R_WUP_CARD_INSERT_Msk 0x2UL 276 #define SDHC_CORE_WUP_CTRL_R_WUP_CARD_REMOVAL_Pos 2UL 277 #define SDHC_CORE_WUP_CTRL_R_WUP_CARD_REMOVAL_Msk 0x4UL 278 /* SDHC_CORE.CLK_CTRL_R */ 279 #define SDHC_CORE_CLK_CTRL_R_INTERNAL_CLK_EN_Pos 0UL 280 #define SDHC_CORE_CLK_CTRL_R_INTERNAL_CLK_EN_Msk 0x1UL 281 #define SDHC_CORE_CLK_CTRL_R_INTERNAL_CLK_STABLE_Pos 1UL 282 #define SDHC_CORE_CLK_CTRL_R_INTERNAL_CLK_STABLE_Msk 0x2UL 283 #define SDHC_CORE_CLK_CTRL_R_SD_CLK_EN_Pos 2UL 284 #define SDHC_CORE_CLK_CTRL_R_SD_CLK_EN_Msk 0x4UL 285 #define SDHC_CORE_CLK_CTRL_R_PLL_ENABLE_Pos 3UL 286 #define SDHC_CORE_CLK_CTRL_R_PLL_ENABLE_Msk 0x8UL 287 #define SDHC_CORE_CLK_CTRL_R_CLK_GEN_SELECT_Pos 5UL 288 #define SDHC_CORE_CLK_CTRL_R_CLK_GEN_SELECT_Msk 0x20UL 289 #define SDHC_CORE_CLK_CTRL_R_UPPER_FREQ_SEL_Pos 6UL 290 #define SDHC_CORE_CLK_CTRL_R_UPPER_FREQ_SEL_Msk 0xC0UL 291 #define SDHC_CORE_CLK_CTRL_R_FREQ_SEL_Pos 8UL 292 #define SDHC_CORE_CLK_CTRL_R_FREQ_SEL_Msk 0xFF00UL 293 /* SDHC_CORE.TOUT_CTRL_R */ 294 #define SDHC_CORE_TOUT_CTRL_R_TOUT_CNT_Pos 0UL 295 #define SDHC_CORE_TOUT_CTRL_R_TOUT_CNT_Msk 0xFUL 296 /* SDHC_CORE.SW_RST_R */ 297 #define SDHC_CORE_SW_RST_R_SW_RST_ALL_Pos 0UL 298 #define SDHC_CORE_SW_RST_R_SW_RST_ALL_Msk 0x1UL 299 #define SDHC_CORE_SW_RST_R_SW_RST_CMD_Pos 1UL 300 #define SDHC_CORE_SW_RST_R_SW_RST_CMD_Msk 0x2UL 301 #define SDHC_CORE_SW_RST_R_SW_RST_DAT_Pos 2UL 302 #define SDHC_CORE_SW_RST_R_SW_RST_DAT_Msk 0x4UL 303 /* SDHC_CORE.NORMAL_INT_STAT_R */ 304 #define SDHC_CORE_NORMAL_INT_STAT_R_CMD_COMPLETE_Pos 0UL 305 #define SDHC_CORE_NORMAL_INT_STAT_R_CMD_COMPLETE_Msk 0x1UL 306 #define SDHC_CORE_NORMAL_INT_STAT_R_XFER_COMPLETE_Pos 1UL 307 #define SDHC_CORE_NORMAL_INT_STAT_R_XFER_COMPLETE_Msk 0x2UL 308 #define SDHC_CORE_NORMAL_INT_STAT_R_BGAP_EVENT_Pos 2UL 309 #define SDHC_CORE_NORMAL_INT_STAT_R_BGAP_EVENT_Msk 0x4UL 310 #define SDHC_CORE_NORMAL_INT_STAT_R_DMA_INTERRUPT_Pos 3UL 311 #define SDHC_CORE_NORMAL_INT_STAT_R_DMA_INTERRUPT_Msk 0x8UL 312 #define SDHC_CORE_NORMAL_INT_STAT_R_BUF_WR_READY_Pos 4UL 313 #define SDHC_CORE_NORMAL_INT_STAT_R_BUF_WR_READY_Msk 0x10UL 314 #define SDHC_CORE_NORMAL_INT_STAT_R_BUF_RD_READY_Pos 5UL 315 #define SDHC_CORE_NORMAL_INT_STAT_R_BUF_RD_READY_Msk 0x20UL 316 #define SDHC_CORE_NORMAL_INT_STAT_R_CARD_INSERTION_Pos 6UL 317 #define SDHC_CORE_NORMAL_INT_STAT_R_CARD_INSERTION_Msk 0x40UL 318 #define SDHC_CORE_NORMAL_INT_STAT_R_CARD_REMOVAL_Pos 7UL 319 #define SDHC_CORE_NORMAL_INT_STAT_R_CARD_REMOVAL_Msk 0x80UL 320 #define SDHC_CORE_NORMAL_INT_STAT_R_CARD_INTERRUPT_Pos 8UL 321 #define SDHC_CORE_NORMAL_INT_STAT_R_CARD_INTERRUPT_Msk 0x100UL 322 #define SDHC_CORE_NORMAL_INT_STAT_R_FX_EVENT_Pos 13UL 323 #define SDHC_CORE_NORMAL_INT_STAT_R_FX_EVENT_Msk 0x2000UL 324 #define SDHC_CORE_NORMAL_INT_STAT_R_CQE_EVENT_Pos 14UL 325 #define SDHC_CORE_NORMAL_INT_STAT_R_CQE_EVENT_Msk 0x4000UL 326 #define SDHC_CORE_NORMAL_INT_STAT_R_ERR_INTERRUPT_Pos 15UL 327 #define SDHC_CORE_NORMAL_INT_STAT_R_ERR_INTERRUPT_Msk 0x8000UL 328 /* SDHC_CORE.ERROR_INT_STAT_R */ 329 #define SDHC_CORE_ERROR_INT_STAT_R_CMD_TOUT_ERR_Pos 0UL 330 #define SDHC_CORE_ERROR_INT_STAT_R_CMD_TOUT_ERR_Msk 0x1UL 331 #define SDHC_CORE_ERROR_INT_STAT_R_CMD_CRC_ERR_Pos 1UL 332 #define SDHC_CORE_ERROR_INT_STAT_R_CMD_CRC_ERR_Msk 0x2UL 333 #define SDHC_CORE_ERROR_INT_STAT_R_CMD_END_BIT_ERR_Pos 2UL 334 #define SDHC_CORE_ERROR_INT_STAT_R_CMD_END_BIT_ERR_Msk 0x4UL 335 #define SDHC_CORE_ERROR_INT_STAT_R_CMD_IDX_ERR_Pos 3UL 336 #define SDHC_CORE_ERROR_INT_STAT_R_CMD_IDX_ERR_Msk 0x8UL 337 #define SDHC_CORE_ERROR_INT_STAT_R_DATA_TOUT_ERR_Pos 4UL 338 #define SDHC_CORE_ERROR_INT_STAT_R_DATA_TOUT_ERR_Msk 0x10UL 339 #define SDHC_CORE_ERROR_INT_STAT_R_DATA_CRC_ERR_Pos 5UL 340 #define SDHC_CORE_ERROR_INT_STAT_R_DATA_CRC_ERR_Msk 0x20UL 341 #define SDHC_CORE_ERROR_INT_STAT_R_DATA_END_BIT_ERR_Pos 6UL 342 #define SDHC_CORE_ERROR_INT_STAT_R_DATA_END_BIT_ERR_Msk 0x40UL 343 #define SDHC_CORE_ERROR_INT_STAT_R_CUR_LMT_ERR_Pos 7UL 344 #define SDHC_CORE_ERROR_INT_STAT_R_CUR_LMT_ERR_Msk 0x80UL 345 #define SDHC_CORE_ERROR_INT_STAT_R_AUTO_CMD_ERR_Pos 8UL 346 #define SDHC_CORE_ERROR_INT_STAT_R_AUTO_CMD_ERR_Msk 0x100UL 347 #define SDHC_CORE_ERROR_INT_STAT_R_ADMA_ERR_Pos 9UL 348 #define SDHC_CORE_ERROR_INT_STAT_R_ADMA_ERR_Msk 0x200UL 349 #define SDHC_CORE_ERROR_INT_STAT_R_TUNING_ERR_Pos 10UL 350 #define SDHC_CORE_ERROR_INT_STAT_R_TUNING_ERR_Msk 0x400UL 351 #define SDHC_CORE_ERROR_INT_STAT_R_RESP_ERR_Pos 11UL 352 #define SDHC_CORE_ERROR_INT_STAT_R_RESP_ERR_Msk 0x800UL 353 #define SDHC_CORE_ERROR_INT_STAT_R_BOOT_ACK_ERR_Pos 12UL 354 #define SDHC_CORE_ERROR_INT_STAT_R_BOOT_ACK_ERR_Msk 0x1000UL 355 /* SDHC_CORE.NORMAL_INT_STAT_EN_R */ 356 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_CMD_COMPLETE_STAT_EN_Pos 0UL 357 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_CMD_COMPLETE_STAT_EN_Msk 0x1UL 358 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_XFER_COMPLETE_STAT_EN_Pos 1UL 359 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_XFER_COMPLETE_STAT_EN_Msk 0x2UL 360 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_BGAP_EVENT_STAT_EN_Pos 2UL 361 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_BGAP_EVENT_STAT_EN_Msk 0x4UL 362 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_DMA_INTERRUPT_STAT_EN_Pos 3UL 363 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_DMA_INTERRUPT_STAT_EN_Msk 0x8UL 364 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_BUF_WR_READY_STAT_EN_Pos 4UL 365 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_BUF_WR_READY_STAT_EN_Msk 0x10UL 366 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_BUF_RD_READY_STAT_EN_Pos 5UL 367 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_BUF_RD_READY_STAT_EN_Msk 0x20UL 368 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_CARD_INSERTION_STAT_EN_Pos 6UL 369 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_CARD_INSERTION_STAT_EN_Msk 0x40UL 370 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_CARD_REMOVAL_STAT_EN_Pos 7UL 371 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_CARD_REMOVAL_STAT_EN_Msk 0x80UL 372 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_CARD_INTERRUPT_STAT_EN_Pos 8UL 373 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_CARD_INTERRUPT_STAT_EN_Msk 0x100UL 374 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_INT_A_STAT_EN_Pos 9UL 375 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_INT_A_STAT_EN_Msk 0x200UL 376 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_INT_B_STAT_EN_Pos 10UL 377 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_INT_B_STAT_EN_Msk 0x400UL 378 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_INT_C_STAT_EN_Pos 11UL 379 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_INT_C_STAT_EN_Msk 0x800UL 380 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_RE_TUNE_EVENT_STAT_EN_Pos 12UL 381 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_RE_TUNE_EVENT_STAT_EN_Msk 0x1000UL 382 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_FX_EVENT_STAT_EN_Pos 13UL 383 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_FX_EVENT_STAT_EN_Msk 0x2000UL 384 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_CQE_EVENT_STAT_EN_Pos 14UL 385 #define SDHC_CORE_NORMAL_INT_STAT_EN_R_CQE_EVENT_STAT_EN_Msk 0x4000UL 386 /* SDHC_CORE.ERROR_INT_STAT_EN_R */ 387 #define SDHC_CORE_ERROR_INT_STAT_EN_R_CMD_TOUT_ERR_STAT_EN_Pos 0UL 388 #define SDHC_CORE_ERROR_INT_STAT_EN_R_CMD_TOUT_ERR_STAT_EN_Msk 0x1UL 389 #define SDHC_CORE_ERROR_INT_STAT_EN_R_CMD_CRC_ERR_STAT_EN_Pos 1UL 390 #define SDHC_CORE_ERROR_INT_STAT_EN_R_CMD_CRC_ERR_STAT_EN_Msk 0x2UL 391 #define SDHC_CORE_ERROR_INT_STAT_EN_R_CMD_END_BIT_ERR_STAT_EN_Pos 2UL 392 #define SDHC_CORE_ERROR_INT_STAT_EN_R_CMD_END_BIT_ERR_STAT_EN_Msk 0x4UL 393 #define SDHC_CORE_ERROR_INT_STAT_EN_R_CMD_IDX_ERR_STAT_EN_Pos 3UL 394 #define SDHC_CORE_ERROR_INT_STAT_EN_R_CMD_IDX_ERR_STAT_EN_Msk 0x8UL 395 #define SDHC_CORE_ERROR_INT_STAT_EN_R_DATA_TOUT_ERR_STAT_EN_Pos 4UL 396 #define SDHC_CORE_ERROR_INT_STAT_EN_R_DATA_TOUT_ERR_STAT_EN_Msk 0x10UL 397 #define SDHC_CORE_ERROR_INT_STAT_EN_R_DATA_CRC_ERR_STAT_EN_Pos 5UL 398 #define SDHC_CORE_ERROR_INT_STAT_EN_R_DATA_CRC_ERR_STAT_EN_Msk 0x20UL 399 #define SDHC_CORE_ERROR_INT_STAT_EN_R_DATA_END_BIT_ERR_STAT_EN_Pos 6UL 400 #define SDHC_CORE_ERROR_INT_STAT_EN_R_DATA_END_BIT_ERR_STAT_EN_Msk 0x40UL 401 #define SDHC_CORE_ERROR_INT_STAT_EN_R_CUR_LMT_ERR_STAT_EN_Pos 7UL 402 #define SDHC_CORE_ERROR_INT_STAT_EN_R_CUR_LMT_ERR_STAT_EN_Msk 0x80UL 403 #define SDHC_CORE_ERROR_INT_STAT_EN_R_AUTO_CMD_ERR_STAT_EN_Pos 8UL 404 #define SDHC_CORE_ERROR_INT_STAT_EN_R_AUTO_CMD_ERR_STAT_EN_Msk 0x100UL 405 #define SDHC_CORE_ERROR_INT_STAT_EN_R_ADMA_ERR_STAT_EN_Pos 9UL 406 #define SDHC_CORE_ERROR_INT_STAT_EN_R_ADMA_ERR_STAT_EN_Msk 0x200UL 407 #define SDHC_CORE_ERROR_INT_STAT_EN_R_TUNING_ERR_STAT_EN_Pos 10UL 408 #define SDHC_CORE_ERROR_INT_STAT_EN_R_TUNING_ERR_STAT_EN_Msk 0x400UL 409 #define SDHC_CORE_ERROR_INT_STAT_EN_R_RESP_ERR_STAT_EN_Pos 11UL 410 #define SDHC_CORE_ERROR_INT_STAT_EN_R_RESP_ERR_STAT_EN_Msk 0x800UL 411 #define SDHC_CORE_ERROR_INT_STAT_EN_R_BOOT_ACK_ERR_STAT_EN_Pos 12UL 412 #define SDHC_CORE_ERROR_INT_STAT_EN_R_BOOT_ACK_ERR_STAT_EN_Msk 0x1000UL 413 #define SDHC_CORE_ERROR_INT_STAT_EN_R_VENDOR_ERR_STAT_EN1_Pos 13UL 414 #define SDHC_CORE_ERROR_INT_STAT_EN_R_VENDOR_ERR_STAT_EN1_Msk 0x2000UL 415 #define SDHC_CORE_ERROR_INT_STAT_EN_R_VENDOR_ERR_STAT_EN2_Pos 14UL 416 #define SDHC_CORE_ERROR_INT_STAT_EN_R_VENDOR_ERR_STAT_EN2_Msk 0x4000UL 417 #define SDHC_CORE_ERROR_INT_STAT_EN_R_VENDOR_ERR_STAT_EN3_Pos 15UL 418 #define SDHC_CORE_ERROR_INT_STAT_EN_R_VENDOR_ERR_STAT_EN3_Msk 0x8000UL 419 /* SDHC_CORE.NORMAL_INT_SIGNAL_EN_R */ 420 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CMD_COMPLETE_SIGNAL_EN_Pos 0UL 421 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CMD_COMPLETE_SIGNAL_EN_Msk 0x1UL 422 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_XFER_COMPLETE_SIGNAL_EN_Pos 1UL 423 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_XFER_COMPLETE_SIGNAL_EN_Msk 0x2UL 424 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_BGAP_EVENT_SIGNAL_EN_Pos 2UL 425 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_BGAP_EVENT_SIGNAL_EN_Msk 0x4UL 426 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_DMA_INTERRUPT_SIGNAL_EN_Pos 3UL 427 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_DMA_INTERRUPT_SIGNAL_EN_Msk 0x8UL 428 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_BUF_WR_READY_SIGNAL_EN_Pos 4UL 429 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_BUF_WR_READY_SIGNAL_EN_Msk 0x10UL 430 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_BUF_RD_READY_SIGNAL_EN_Pos 5UL 431 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_BUF_RD_READY_SIGNAL_EN_Msk 0x20UL 432 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CARD_INSERTION_SIGNAL_EN_Pos 6UL 433 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CARD_INSERTION_SIGNAL_EN_Msk 0x40UL 434 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CARD_REMOVAL_SIGNAL_EN_Pos 7UL 435 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CARD_REMOVAL_SIGNAL_EN_Msk 0x80UL 436 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CARD_INTERRUPT_SIGNAL_EN_Pos 8UL 437 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CARD_INTERRUPT_SIGNAL_EN_Msk 0x100UL 438 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_INT_A_SIGNAL_EN_Pos 9UL 439 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_INT_A_SIGNAL_EN_Msk 0x200UL 440 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_INT_B_SIGNAL_EN_Pos 10UL 441 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_INT_B_SIGNAL_EN_Msk 0x400UL 442 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_INT_C_SIGNAL_EN_Pos 11UL 443 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_INT_C_SIGNAL_EN_Msk 0x800UL 444 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_RE_TUNE_EVENT_SIGNAL_EN_Pos 12UL 445 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_RE_TUNE_EVENT_SIGNAL_EN_Msk 0x1000UL 446 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_FX_EVENT_SIGNAL_EN_Pos 13UL 447 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_FX_EVENT_SIGNAL_EN_Msk 0x2000UL 448 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CQE_EVENT_SIGNAL_EN_Pos 14UL 449 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R_CQE_EVENT_SIGNAL_EN_Msk 0x4000UL 450 /* SDHC_CORE.ERROR_INT_SIGNAL_EN_R */ 451 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CMD_TOUT_ERR_SIGNAL_EN_Pos 0UL 452 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CMD_TOUT_ERR_SIGNAL_EN_Msk 0x1UL 453 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CMD_CRC_ERR_SIGNAL_EN_Pos 1UL 454 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CMD_CRC_ERR_SIGNAL_EN_Msk 0x2UL 455 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CMD_END_BIT_ERR_SIGNAL_EN_Pos 2UL 456 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CMD_END_BIT_ERR_SIGNAL_EN_Msk 0x4UL 457 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CMD_IDX_ERR_SIGNAL_EN_Pos 3UL 458 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CMD_IDX_ERR_SIGNAL_EN_Msk 0x8UL 459 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_DATA_TOUT_ERR_SIGNAL_EN_Pos 4UL 460 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_DATA_TOUT_ERR_SIGNAL_EN_Msk 0x10UL 461 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_DATA_CRC_ERR_SIGNAL_EN_Pos 5UL 462 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_DATA_CRC_ERR_SIGNAL_EN_Msk 0x20UL 463 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_DATA_END_BIT_ERR_SIGNAL_EN_Pos 6UL 464 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_DATA_END_BIT_ERR_SIGNAL_EN_Msk 0x40UL 465 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CUR_LMT_ERR_SIGNAL_EN_Pos 7UL 466 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_CUR_LMT_ERR_SIGNAL_EN_Msk 0x80UL 467 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_AUTO_CMD_ERR_SIGNAL_EN_Pos 8UL 468 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_AUTO_CMD_ERR_SIGNAL_EN_Msk 0x100UL 469 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_ADMA_ERR_SIGNAL_EN_Pos 9UL 470 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_ADMA_ERR_SIGNAL_EN_Msk 0x200UL 471 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_TUNING_ERR_SIGNAL_EN_Pos 10UL 472 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_TUNING_ERR_SIGNAL_EN_Msk 0x400UL 473 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_RESP_ERR_SIGNAL_EN_Pos 11UL 474 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_RESP_ERR_SIGNAL_EN_Msk 0x800UL 475 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_BOOT_ACK_ERR_SIGNAL_EN_Pos 12UL 476 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_BOOT_ACK_ERR_SIGNAL_EN_Msk 0x1000UL 477 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_VENDOR_ERR_SIGNAL_EN1_Pos 13UL 478 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_VENDOR_ERR_SIGNAL_EN1_Msk 0x2000UL 479 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_VENDOR_ERR_SIGNAL_EN2_Pos 14UL 480 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_VENDOR_ERR_SIGNAL_EN2_Msk 0x4000UL 481 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_VENDOR_ERR_SIGNAL_EN3_Pos 15UL 482 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R_VENDOR_ERR_SIGNAL_EN3_Msk 0x8000UL 483 /* SDHC_CORE.AUTO_CMD_STAT_R */ 484 #define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD12_NOT_EXEC_Pos 0UL 485 #define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD12_NOT_EXEC_Msk 0x1UL 486 #define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_TOUT_ERR_Pos 1UL 487 #define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_TOUT_ERR_Msk 0x2UL 488 #define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_CRC_ERR_Pos 2UL 489 #define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_CRC_ERR_Msk 0x4UL 490 #define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_EBIT_ERR_Pos 3UL 491 #define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_EBIT_ERR_Msk 0x8UL 492 #define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_IDX_ERR_Pos 4UL 493 #define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_IDX_ERR_Msk 0x10UL 494 #define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_RESP_ERR_Pos 5UL 495 #define SDHC_CORE_AUTO_CMD_STAT_R_AUTO_CMD_RESP_ERR_Msk 0x20UL 496 #define SDHC_CORE_AUTO_CMD_STAT_R_CMD_NOT_ISSUED_AUTO_CMD12_Pos 7UL 497 #define SDHC_CORE_AUTO_CMD_STAT_R_CMD_NOT_ISSUED_AUTO_CMD12_Msk 0x80UL 498 /* SDHC_CORE.HOST_CTRL2_R */ 499 #define SDHC_CORE_HOST_CTRL2_R_UHS_MODE_SEL_Pos 0UL 500 #define SDHC_CORE_HOST_CTRL2_R_UHS_MODE_SEL_Msk 0x7UL 501 #define SDHC_CORE_HOST_CTRL2_R_SIGNALING_EN_Pos 3UL 502 #define SDHC_CORE_HOST_CTRL2_R_SIGNALING_EN_Msk 0x8UL 503 #define SDHC_CORE_HOST_CTRL2_R_DRV_STRENGTH_SEL_Pos 4UL 504 #define SDHC_CORE_HOST_CTRL2_R_DRV_STRENGTH_SEL_Msk 0x30UL 505 #define SDHC_CORE_HOST_CTRL2_R_EXEC_TUNING_Pos 6UL 506 #define SDHC_CORE_HOST_CTRL2_R_EXEC_TUNING_Msk 0x40UL 507 #define SDHC_CORE_HOST_CTRL2_R_SAMPLE_CLK_SEL_Pos 7UL 508 #define SDHC_CORE_HOST_CTRL2_R_SAMPLE_CLK_SEL_Msk 0x80UL 509 #define SDHC_CORE_HOST_CTRL2_R_UHS2_IF_ENABLE_Pos 8UL 510 #define SDHC_CORE_HOST_CTRL2_R_UHS2_IF_ENABLE_Msk 0x100UL 511 #define SDHC_CORE_HOST_CTRL2_R_ADMA2_LEN_MODE_Pos 10UL 512 #define SDHC_CORE_HOST_CTRL2_R_ADMA2_LEN_MODE_Msk 0x400UL 513 #define SDHC_CORE_HOST_CTRL2_R_CMD23_ENABLE_Pos 11UL 514 #define SDHC_CORE_HOST_CTRL2_R_CMD23_ENABLE_Msk 0x800UL 515 #define SDHC_CORE_HOST_CTRL2_R_HOST_VER4_ENABLE_Pos 12UL 516 #define SDHC_CORE_HOST_CTRL2_R_HOST_VER4_ENABLE_Msk 0x1000UL 517 #define SDHC_CORE_HOST_CTRL2_R_ADDRESSING_Pos 13UL 518 #define SDHC_CORE_HOST_CTRL2_R_ADDRESSING_Msk 0x2000UL 519 #define SDHC_CORE_HOST_CTRL2_R_ASYNC_INT_ENABLE_Pos 14UL 520 #define SDHC_CORE_HOST_CTRL2_R_ASYNC_INT_ENABLE_Msk 0x4000UL 521 #define SDHC_CORE_HOST_CTRL2_R_PRESET_VAL_ENABLE_Pos 15UL 522 #define SDHC_CORE_HOST_CTRL2_R_PRESET_VAL_ENABLE_Msk 0x8000UL 523 /* SDHC_CORE.CAPABILITIES1_R */ 524 #define SDHC_CORE_CAPABILITIES1_R_TOUT_CLK_FREQ_Pos 0UL 525 #define SDHC_CORE_CAPABILITIES1_R_TOUT_CLK_FREQ_Msk 0x3FUL 526 #define SDHC_CORE_CAPABILITIES1_R_TOUT_CLK_UNIT_Pos 7UL 527 #define SDHC_CORE_CAPABILITIES1_R_TOUT_CLK_UNIT_Msk 0x80UL 528 #define SDHC_CORE_CAPABILITIES1_R_BASE_CLK_FREQ_Pos 8UL 529 #define SDHC_CORE_CAPABILITIES1_R_BASE_CLK_FREQ_Msk 0xFF00UL 530 #define SDHC_CORE_CAPABILITIES1_R_MAX_BLK_LEN_Pos 16UL 531 #define SDHC_CORE_CAPABILITIES1_R_MAX_BLK_LEN_Msk 0x30000UL 532 #define SDHC_CORE_CAPABILITIES1_R_EMBEDDED_8_BIT_Pos 18UL 533 #define SDHC_CORE_CAPABILITIES1_R_EMBEDDED_8_BIT_Msk 0x40000UL 534 #define SDHC_CORE_CAPABILITIES1_R_ADMA2_SUPPORT_Pos 19UL 535 #define SDHC_CORE_CAPABILITIES1_R_ADMA2_SUPPORT_Msk 0x80000UL 536 #define SDHC_CORE_CAPABILITIES1_R_HIGH_SPEED_SUPPORT_Pos 21UL 537 #define SDHC_CORE_CAPABILITIES1_R_HIGH_SPEED_SUPPORT_Msk 0x200000UL 538 #define SDHC_CORE_CAPABILITIES1_R_SDMA_SUPPORT_Pos 22UL 539 #define SDHC_CORE_CAPABILITIES1_R_SDMA_SUPPORT_Msk 0x400000UL 540 #define SDHC_CORE_CAPABILITIES1_R_SUS_RES_SUPPORT_Pos 23UL 541 #define SDHC_CORE_CAPABILITIES1_R_SUS_RES_SUPPORT_Msk 0x800000UL 542 #define SDHC_CORE_CAPABILITIES1_R_VOLT_33_Pos 24UL 543 #define SDHC_CORE_CAPABILITIES1_R_VOLT_33_Msk 0x1000000UL 544 #define SDHC_CORE_CAPABILITIES1_R_VOLT_30_Pos 25UL 545 #define SDHC_CORE_CAPABILITIES1_R_VOLT_30_Msk 0x2000000UL 546 #define SDHC_CORE_CAPABILITIES1_R_VOLT_18_Pos 26UL 547 #define SDHC_CORE_CAPABILITIES1_R_VOLT_18_Msk 0x4000000UL 548 #define SDHC_CORE_CAPABILITIES1_R_SYS_ADDR_64_V4_Pos 27UL 549 #define SDHC_CORE_CAPABILITIES1_R_SYS_ADDR_64_V4_Msk 0x8000000UL 550 #define SDHC_CORE_CAPABILITIES1_R_SYS_ADDR_64_V3_Pos 28UL 551 #define SDHC_CORE_CAPABILITIES1_R_SYS_ADDR_64_V3_Msk 0x10000000UL 552 #define SDHC_CORE_CAPABILITIES1_R_ASYNC_INT_SUPPORT_Pos 29UL 553 #define SDHC_CORE_CAPABILITIES1_R_ASYNC_INT_SUPPORT_Msk 0x20000000UL 554 #define SDHC_CORE_CAPABILITIES1_R_SLOT_TYPE_R_Pos 30UL 555 #define SDHC_CORE_CAPABILITIES1_R_SLOT_TYPE_R_Msk 0xC0000000UL 556 /* SDHC_CORE.CAPABILITIES2_R */ 557 #define SDHC_CORE_CAPABILITIES2_R_SDR50_SUPPORT_Pos 0UL 558 #define SDHC_CORE_CAPABILITIES2_R_SDR50_SUPPORT_Msk 0x1UL 559 #define SDHC_CORE_CAPABILITIES2_R_SDR104_SUPPORT_Pos 1UL 560 #define SDHC_CORE_CAPABILITIES2_R_SDR104_SUPPORT_Msk 0x2UL 561 #define SDHC_CORE_CAPABILITIES2_R_DDR50_SUPPORT_Pos 2UL 562 #define SDHC_CORE_CAPABILITIES2_R_DDR50_SUPPORT_Msk 0x4UL 563 #define SDHC_CORE_CAPABILITIES2_R_UHS2_SUPPORT_Pos 3UL 564 #define SDHC_CORE_CAPABILITIES2_R_UHS2_SUPPORT_Msk 0x8UL 565 #define SDHC_CORE_CAPABILITIES2_R_DRV_TYPEA_Pos 4UL 566 #define SDHC_CORE_CAPABILITIES2_R_DRV_TYPEA_Msk 0x10UL 567 #define SDHC_CORE_CAPABILITIES2_R_DRV_TYPEC_Pos 5UL 568 #define SDHC_CORE_CAPABILITIES2_R_DRV_TYPEC_Msk 0x20UL 569 #define SDHC_CORE_CAPABILITIES2_R_DRV_TYPED_Pos 6UL 570 #define SDHC_CORE_CAPABILITIES2_R_DRV_TYPED_Msk 0x40UL 571 #define SDHC_CORE_CAPABILITIES2_R_RETUNE_CNT_Pos 8UL 572 #define SDHC_CORE_CAPABILITIES2_R_RETUNE_CNT_Msk 0xF00UL 573 #define SDHC_CORE_CAPABILITIES2_R_USE_TUNING_SDR50_Pos 13UL 574 #define SDHC_CORE_CAPABILITIES2_R_USE_TUNING_SDR50_Msk 0x2000UL 575 #define SDHC_CORE_CAPABILITIES2_R_RE_TUNING_MODES_Pos 14UL 576 #define SDHC_CORE_CAPABILITIES2_R_RE_TUNING_MODES_Msk 0xC000UL 577 #define SDHC_CORE_CAPABILITIES2_R_CLK_MUL_Pos 16UL 578 #define SDHC_CORE_CAPABILITIES2_R_CLK_MUL_Msk 0xFF0000UL 579 #define SDHC_CORE_CAPABILITIES2_R_ADMA3_SUPPORT_Pos 27UL 580 #define SDHC_CORE_CAPABILITIES2_R_ADMA3_SUPPORT_Msk 0x8000000UL 581 #define SDHC_CORE_CAPABILITIES2_R_VDD2_18V_SUPPORT_Pos 28UL 582 #define SDHC_CORE_CAPABILITIES2_R_VDD2_18V_SUPPORT_Msk 0x10000000UL 583 /* SDHC_CORE.CURR_CAPABILITIES1_R */ 584 #define SDHC_CORE_CURR_CAPABILITIES1_R_MAX_CUR_33V_Pos 0UL 585 #define SDHC_CORE_CURR_CAPABILITIES1_R_MAX_CUR_33V_Msk 0xFFUL 586 #define SDHC_CORE_CURR_CAPABILITIES1_R_MAX_CUR_30V_Pos 8UL 587 #define SDHC_CORE_CURR_CAPABILITIES1_R_MAX_CUR_30V_Msk 0xFF00UL 588 #define SDHC_CORE_CURR_CAPABILITIES1_R_MAX_CUR_18V_Pos 16UL 589 #define SDHC_CORE_CURR_CAPABILITIES1_R_MAX_CUR_18V_Msk 0xFF0000UL 590 /* SDHC_CORE.CURR_CAPABILITIES2_R */ 591 #define SDHC_CORE_CURR_CAPABILITIES2_R_MAX_CUR_VDD2_18V_Pos 0UL 592 #define SDHC_CORE_CURR_CAPABILITIES2_R_MAX_CUR_VDD2_18V_Msk 0xFFUL 593 /* SDHC_CORE.FORCE_AUTO_CMD_STAT_R */ 594 #define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD12_NOT_EXEC_Pos 0UL 595 #define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD12_NOT_EXEC_Msk 0x1UL 596 #define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_TOUT_ERR_Pos 1UL 597 #define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_TOUT_ERR_Msk 0x2UL 598 #define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_CRC_ERR_Pos 2UL 599 #define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_CRC_ERR_Msk 0x4UL 600 #define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_EBIT_ERR_Pos 3UL 601 #define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_EBIT_ERR_Msk 0x8UL 602 #define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_IDX_ERR_Pos 4UL 603 #define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_IDX_ERR_Msk 0x10UL 604 #define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_RESP_ERR_Pos 5UL 605 #define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_AUTO_CMD_RESP_ERR_Msk 0x20UL 606 #define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_Pos 7UL 607 #define SDHC_CORE_FORCE_AUTO_CMD_STAT_R_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_Msk 0x80UL 608 /* SDHC_CORE.FORCE_ERROR_INT_STAT_R */ 609 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CMD_TOUT_ERR_Pos 0UL 610 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CMD_TOUT_ERR_Msk 0x1UL 611 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CMD_CRC_ERR_Pos 1UL 612 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CMD_CRC_ERR_Msk 0x2UL 613 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CMD_END_BIT_ERR_Pos 2UL 614 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CMD_END_BIT_ERR_Msk 0x4UL 615 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CMD_IDX_ERR_Pos 3UL 616 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CMD_IDX_ERR_Msk 0x8UL 617 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_DATA_TOUT_ERR_Pos 4UL 618 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_DATA_TOUT_ERR_Msk 0x10UL 619 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_DATA_CRC_ERR_Pos 5UL 620 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_DATA_CRC_ERR_Msk 0x20UL 621 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_DATA_END_BIT_ERR_Pos 6UL 622 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_DATA_END_BIT_ERR_Msk 0x40UL 623 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CUR_LMT_ERR_Pos 7UL 624 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_CUR_LMT_ERR_Msk 0x80UL 625 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_AUTO_CMD_ERR_Pos 8UL 626 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_AUTO_CMD_ERR_Msk 0x100UL 627 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_ADMA_ERR_Pos 9UL 628 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_ADMA_ERR_Msk 0x200UL 629 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_TUNING_ERR_Pos 10UL 630 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_TUNING_ERR_Msk 0x400UL 631 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_RESP_ERR_Pos 11UL 632 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_RESP_ERR_Msk 0x800UL 633 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_BOOT_ACK_ERR_Pos 12UL 634 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_BOOT_ACK_ERR_Msk 0x1000UL 635 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_VENDOR_ERR1_Pos 13UL 636 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_VENDOR_ERR1_Msk 0x2000UL 637 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_VENDOR_ERR2_Pos 14UL 638 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_VENDOR_ERR2_Msk 0x4000UL 639 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_VENDOR_ERR3_Pos 15UL 640 #define SDHC_CORE_FORCE_ERROR_INT_STAT_R_FORCE_VENDOR_ERR3_Msk 0x8000UL 641 /* SDHC_CORE.ADMA_ERR_STAT_R */ 642 #define SDHC_CORE_ADMA_ERR_STAT_R_ADMA_ERR_STATES_Pos 0UL 643 #define SDHC_CORE_ADMA_ERR_STAT_R_ADMA_ERR_STATES_Msk 0x3UL 644 #define SDHC_CORE_ADMA_ERR_STAT_R_ADMA_LEN_ERR_Pos 2UL 645 #define SDHC_CORE_ADMA_ERR_STAT_R_ADMA_LEN_ERR_Msk 0x4UL 646 /* SDHC_CORE.ADMA_SA_LOW_R */ 647 #define SDHC_CORE_ADMA_SA_LOW_R_ADMA_SA_LOW_Pos 0UL 648 #define SDHC_CORE_ADMA_SA_LOW_R_ADMA_SA_LOW_Msk 0xFFFFFFFFUL 649 /* SDHC_CORE.ADMA_ID_LOW_R */ 650 #define SDHC_CORE_ADMA_ID_LOW_R_ADMA_ID_LOW_Pos 0UL 651 #define SDHC_CORE_ADMA_ID_LOW_R_ADMA_ID_LOW_Msk 0xFFFFFFFFUL 652 /* SDHC_CORE.HOST_CNTRL_VERS_R */ 653 #define SDHC_CORE_HOST_CNTRL_VERS_R_SPEC_VERSION_NUM_Pos 0UL 654 #define SDHC_CORE_HOST_CNTRL_VERS_R_SPEC_VERSION_NUM_Msk 0xFFUL 655 #define SDHC_CORE_HOST_CNTRL_VERS_R_VENDOR_VERSION_NUM_Pos 8UL 656 #define SDHC_CORE_HOST_CNTRL_VERS_R_VENDOR_VERSION_NUM_Msk 0xFF00UL 657 /* SDHC_CORE.CQVER */ 658 #define SDHC_CORE_CQVER_EMMC_VER_SUFFIX_Pos 0UL 659 #define SDHC_CORE_CQVER_EMMC_VER_SUFFIX_Msk 0xFUL 660 #define SDHC_CORE_CQVER_EMMC_VER_MINOR_Pos 4UL 661 #define SDHC_CORE_CQVER_EMMC_VER_MINOR_Msk 0xF0UL 662 #define SDHC_CORE_CQVER_EMMC_VER_MAJOR_Pos 8UL 663 #define SDHC_CORE_CQVER_EMMC_VER_MAJOR_Msk 0xF00UL 664 /* SDHC_CORE.CQCAP */ 665 #define SDHC_CORE_CQCAP_ITCFVAL_Pos 0UL 666 #define SDHC_CORE_CQCAP_ITCFVAL_Msk 0x3FFUL 667 #define SDHC_CORE_CQCAP_ITCFMUL_Pos 12UL 668 #define SDHC_CORE_CQCAP_ITCFMUL_Msk 0xF000UL 669 #define SDHC_CORE_CQCAP_CRYPTO_SUPPORT_Pos 28UL 670 #define SDHC_CORE_CQCAP_CRYPTO_SUPPORT_Msk 0x10000000UL 671 /* SDHC_CORE.CQCFG */ 672 #define SDHC_CORE_CQCFG_CQ_EN_Pos 0UL 673 #define SDHC_CORE_CQCFG_CQ_EN_Msk 0x1UL 674 #define SDHC_CORE_CQCFG_CR_GENERAL_EN_Pos 1UL 675 #define SDHC_CORE_CQCFG_CR_GENERAL_EN_Msk 0x2UL 676 #define SDHC_CORE_CQCFG_TASK_DESC_SIZE_Pos 8UL 677 #define SDHC_CORE_CQCFG_TASK_DESC_SIZE_Msk 0x100UL 678 #define SDHC_CORE_CQCFG_DCMD_EN_Pos 12UL 679 #define SDHC_CORE_CQCFG_DCMD_EN_Msk 0x1000UL 680 /* SDHC_CORE.CQCTL */ 681 #define SDHC_CORE_CQCTL_HALT_Pos 0UL 682 #define SDHC_CORE_CQCTL_HALT_Msk 0x1UL 683 #define SDHC_CORE_CQCTL_CLR_ALL_TASKS_Pos 8UL 684 #define SDHC_CORE_CQCTL_CLR_ALL_TASKS_Msk 0x100UL 685 /* SDHC_CORE.CQIS */ 686 #define SDHC_CORE_CQIS_HAC_Pos 0UL 687 #define SDHC_CORE_CQIS_HAC_Msk 0x1UL 688 #define SDHC_CORE_CQIS_TCC_Pos 1UL 689 #define SDHC_CORE_CQIS_TCC_Msk 0x2UL 690 #define SDHC_CORE_CQIS_RED_Pos 2UL 691 #define SDHC_CORE_CQIS_RED_Msk 0x4UL 692 #define SDHC_CORE_CQIS_TCL_Pos 3UL 693 #define SDHC_CORE_CQIS_TCL_Msk 0x8UL 694 #define SDHC_CORE_CQIS_GCE_Pos 4UL 695 #define SDHC_CORE_CQIS_GCE_Msk 0x10UL 696 #define SDHC_CORE_CQIS_ICCE_Pos 5UL 697 #define SDHC_CORE_CQIS_ICCE_Msk 0x20UL 698 /* SDHC_CORE.CQISE */ 699 #define SDHC_CORE_CQISE_HAC_STE_Pos 0UL 700 #define SDHC_CORE_CQISE_HAC_STE_Msk 0x1UL 701 #define SDHC_CORE_CQISE_TCC_STE_Pos 1UL 702 #define SDHC_CORE_CQISE_TCC_STE_Msk 0x2UL 703 #define SDHC_CORE_CQISE_RED_STE_Pos 2UL 704 #define SDHC_CORE_CQISE_RED_STE_Msk 0x4UL 705 #define SDHC_CORE_CQISE_TCL_STE_Pos 3UL 706 #define SDHC_CORE_CQISE_TCL_STE_Msk 0x8UL 707 #define SDHC_CORE_CQISE_GCE_STE_Pos 4UL 708 #define SDHC_CORE_CQISE_GCE_STE_Msk 0x10UL 709 #define SDHC_CORE_CQISE_ICCE_STE_Pos 5UL 710 #define SDHC_CORE_CQISE_ICCE_STE_Msk 0x20UL 711 /* SDHC_CORE.CQISGE */ 712 #define SDHC_CORE_CQISGE_HAC_SGE_Pos 0UL 713 #define SDHC_CORE_CQISGE_HAC_SGE_Msk 0x1UL 714 #define SDHC_CORE_CQISGE_TCC_SGE_Pos 1UL 715 #define SDHC_CORE_CQISGE_TCC_SGE_Msk 0x2UL 716 #define SDHC_CORE_CQISGE_RED_SGE_Pos 2UL 717 #define SDHC_CORE_CQISGE_RED_SGE_Msk 0x4UL 718 #define SDHC_CORE_CQISGE_TCL_SGE_Pos 3UL 719 #define SDHC_CORE_CQISGE_TCL_SGE_Msk 0x8UL 720 #define SDHC_CORE_CQISGE_GCE_SGE_Pos 4UL 721 #define SDHC_CORE_CQISGE_GCE_SGE_Msk 0x10UL 722 #define SDHC_CORE_CQISGE_ICCE_SGE_Pos 5UL 723 #define SDHC_CORE_CQISGE_ICCE_SGE_Msk 0x20UL 724 /* SDHC_CORE.CQIC */ 725 #define SDHC_CORE_CQIC_TOUT_VAL_Pos 0UL 726 #define SDHC_CORE_CQIC_TOUT_VAL_Msk 0x7FUL 727 #define SDHC_CORE_CQIC_TOUT_VAL_WEN_Pos 7UL 728 #define SDHC_CORE_CQIC_TOUT_VAL_WEN_Msk 0x80UL 729 #define SDHC_CORE_CQIC_INTC_TH_Pos 8UL 730 #define SDHC_CORE_CQIC_INTC_TH_Msk 0x1F00UL 731 #define SDHC_CORE_CQIC_INTC_TH_WEN_Pos 15UL 732 #define SDHC_CORE_CQIC_INTC_TH_WEN_Msk 0x8000UL 733 #define SDHC_CORE_CQIC_INTC_RST_Pos 16UL 734 #define SDHC_CORE_CQIC_INTC_RST_Msk 0x10000UL 735 #define SDHC_CORE_CQIC_INTC_STAT_Pos 20UL 736 #define SDHC_CORE_CQIC_INTC_STAT_Msk 0x100000UL 737 #define SDHC_CORE_CQIC_INTC_EN_Pos 31UL 738 #define SDHC_CORE_CQIC_INTC_EN_Msk 0x80000000UL 739 /* SDHC_CORE.CQTDLBA */ 740 #define SDHC_CORE_CQTDLBA_TDLBA_Pos 0UL 741 #define SDHC_CORE_CQTDLBA_TDLBA_Msk 0xFFFFFFFFUL 742 /* SDHC_CORE.CQTDBR */ 743 #define SDHC_CORE_CQTDBR_DBR_Pos 0UL 744 #define SDHC_CORE_CQTDBR_DBR_Msk 0xFFFFFFFFUL 745 /* SDHC_CORE.CQTCN */ 746 #define SDHC_CORE_CQTCN_TCN_Pos 0UL 747 #define SDHC_CORE_CQTCN_TCN_Msk 0xFFFFFFFFUL 748 /* SDHC_CORE.CQDQS */ 749 #define SDHC_CORE_CQDQS_DQS_Pos 0UL 750 #define SDHC_CORE_CQDQS_DQS_Msk 0xFFFFFFFFUL 751 /* SDHC_CORE.CQDPT */ 752 #define SDHC_CORE_CQDPT_DPT_Pos 0UL 753 #define SDHC_CORE_CQDPT_DPT_Msk 0xFFFFFFFFUL 754 /* SDHC_CORE.CQTCLR */ 755 #define SDHC_CORE_CQTCLR_TCLR_Pos 0UL 756 #define SDHC_CORE_CQTCLR_TCLR_Msk 0xFFFFFFFFUL 757 /* SDHC_CORE.CQSSC1 */ 758 #define SDHC_CORE_CQSSC1_SQSCMD_IDLE_TMR_Pos 0UL 759 #define SDHC_CORE_CQSSC1_SQSCMD_IDLE_TMR_Msk 0xFFFFUL 760 #define SDHC_CORE_CQSSC1_SQSCMD_BLK_CNT_Pos 16UL 761 #define SDHC_CORE_CQSSC1_SQSCMD_BLK_CNT_Msk 0xF0000UL 762 /* SDHC_CORE.CQSSC2 */ 763 #define SDHC_CORE_CQSSC2_SQSCMD_RCA_Pos 0UL 764 #define SDHC_CORE_CQSSC2_SQSCMD_RCA_Msk 0xFFFFUL 765 /* SDHC_CORE.CQCRDCT */ 766 #define SDHC_CORE_CQCRDCT_DCMD_RESP_Pos 0UL 767 #define SDHC_CORE_CQCRDCT_DCMD_RESP_Msk 0xFFFFFFFFUL 768 /* SDHC_CORE.CQRMEM */ 769 #define SDHC_CORE_CQRMEM_RESP_ERR_MASK_Pos 0UL 770 #define SDHC_CORE_CQRMEM_RESP_ERR_MASK_Msk 0xFFFFFFFFUL 771 /* SDHC_CORE.CQTERRI */ 772 #define SDHC_CORE_CQTERRI_RESP_ERR_CMD_INDX_Pos 0UL 773 #define SDHC_CORE_CQTERRI_RESP_ERR_CMD_INDX_Msk 0x3FUL 774 #define SDHC_CORE_CQTERRI_RESP_ERR_TASKID_Pos 8UL 775 #define SDHC_CORE_CQTERRI_RESP_ERR_TASKID_Msk 0x1F00UL 776 #define SDHC_CORE_CQTERRI_RESP_ERR_FIELDS_VALID_Pos 15UL 777 #define SDHC_CORE_CQTERRI_RESP_ERR_FIELDS_VALID_Msk 0x8000UL 778 #define SDHC_CORE_CQTERRI_TRANS_ERR_CMD_INDX_Pos 16UL 779 #define SDHC_CORE_CQTERRI_TRANS_ERR_CMD_INDX_Msk 0x3F0000UL 780 #define SDHC_CORE_CQTERRI_TRANS_ERR_TASKID_Pos 24UL 781 #define SDHC_CORE_CQTERRI_TRANS_ERR_TASKID_Msk 0x1F000000UL 782 #define SDHC_CORE_CQTERRI_TRANS_ERR_FIELDS_VALID_Pos 31UL 783 #define SDHC_CORE_CQTERRI_TRANS_ERR_FIELDS_VALID_Msk 0x80000000UL 784 /* SDHC_CORE.CQCRI */ 785 #define SDHC_CORE_CQCRI_CMD_RESP_INDX_Pos 0UL 786 #define SDHC_CORE_CQCRI_CMD_RESP_INDX_Msk 0x3FUL 787 /* SDHC_CORE.CQCRA */ 788 #define SDHC_CORE_CQCRA_CMD_RESP_ARG_Pos 0UL 789 #define SDHC_CORE_CQCRA_CMD_RESP_ARG_Msk 0xFFFFFFFFUL 790 /* SDHC_CORE.MSHC_VER_ID_R */ 791 #define SDHC_CORE_MSHC_VER_ID_R_MSHC_VER_ID_Pos 0UL 792 #define SDHC_CORE_MSHC_VER_ID_R_MSHC_VER_ID_Msk 0xFFFFFFFFUL 793 /* SDHC_CORE.MSHC_VER_TYPE_R */ 794 #define SDHC_CORE_MSHC_VER_TYPE_R_MSHC_VER_TYPE_Pos 0UL 795 #define SDHC_CORE_MSHC_VER_TYPE_R_MSHC_VER_TYPE_Msk 0xFFFFFFFFUL 796 /* SDHC_CORE.MSHC_CTRL_R */ 797 #define SDHC_CORE_MSHC_CTRL_R_CMD_CONFLICT_CHECK_Pos 0UL 798 #define SDHC_CORE_MSHC_CTRL_R_CMD_CONFLICT_CHECK_Msk 0x1UL 799 #define SDHC_CORE_MSHC_CTRL_R_SW_CG_DIS_Pos 4UL 800 #define SDHC_CORE_MSHC_CTRL_R_SW_CG_DIS_Msk 0x10UL 801 /* SDHC_CORE.MBIU_CTRL_R */ 802 #define SDHC_CORE_MBIU_CTRL_R_UNDEFL_INCR_EN_Pos 0UL 803 #define SDHC_CORE_MBIU_CTRL_R_UNDEFL_INCR_EN_Msk 0x1UL 804 #define SDHC_CORE_MBIU_CTRL_R_BURST_INCR4_EN_Pos 1UL 805 #define SDHC_CORE_MBIU_CTRL_R_BURST_INCR4_EN_Msk 0x2UL 806 #define SDHC_CORE_MBIU_CTRL_R_BURST_INCR8_EN_Pos 2UL 807 #define SDHC_CORE_MBIU_CTRL_R_BURST_INCR8_EN_Msk 0x4UL 808 #define SDHC_CORE_MBIU_CTRL_R_BURST_INCR16_EN_Pos 3UL 809 #define SDHC_CORE_MBIU_CTRL_R_BURST_INCR16_EN_Msk 0x8UL 810 /* SDHC_CORE.EMMC_CTRL_R */ 811 #define SDHC_CORE_EMMC_CTRL_R_CARD_IS_EMMC_Pos 0UL 812 #define SDHC_CORE_EMMC_CTRL_R_CARD_IS_EMMC_Msk 0x1UL 813 #define SDHC_CORE_EMMC_CTRL_R_DISABLE_DATA_CRC_CHK_Pos 1UL 814 #define SDHC_CORE_EMMC_CTRL_R_DISABLE_DATA_CRC_CHK_Msk 0x2UL 815 #define SDHC_CORE_EMMC_CTRL_R_EMMC_RST_N_Pos 2UL 816 #define SDHC_CORE_EMMC_CTRL_R_EMMC_RST_N_Msk 0x4UL 817 #define SDHC_CORE_EMMC_CTRL_R_EMMC_RST_N_OE_Pos 3UL 818 #define SDHC_CORE_EMMC_CTRL_R_EMMC_RST_N_OE_Msk 0x8UL 819 #define SDHC_CORE_EMMC_CTRL_R_CQE_ALGO_SEL_Pos 9UL 820 #define SDHC_CORE_EMMC_CTRL_R_CQE_ALGO_SEL_Msk 0x200UL 821 #define SDHC_CORE_EMMC_CTRL_R_CQE_PREFETCH_DISABLE_Pos 10UL 822 #define SDHC_CORE_EMMC_CTRL_R_CQE_PREFETCH_DISABLE_Msk 0x400UL 823 /* SDHC_CORE.BOOT_CTRL_R */ 824 #define SDHC_CORE_BOOT_CTRL_R_MAN_BOOT_EN_Pos 0UL 825 #define SDHC_CORE_BOOT_CTRL_R_MAN_BOOT_EN_Msk 0x1UL 826 #define SDHC_CORE_BOOT_CTRL_R_VALIDATE_BOOT_Pos 7UL 827 #define SDHC_CORE_BOOT_CTRL_R_VALIDATE_BOOT_Msk 0x80UL 828 #define SDHC_CORE_BOOT_CTRL_R_BOOT_ACK_ENABLE_Pos 8UL 829 #define SDHC_CORE_BOOT_CTRL_R_BOOT_ACK_ENABLE_Msk 0x100UL 830 #define SDHC_CORE_BOOT_CTRL_R_BOOT_TOUT_CNT_Pos 12UL 831 #define SDHC_CORE_BOOT_CTRL_R_BOOT_TOUT_CNT_Msk 0xF000UL 832 /* SDHC_CORE.GP_IN_R */ 833 #define SDHC_CORE_GP_IN_R_GP_IN_Pos 0UL 834 #define SDHC_CORE_GP_IN_R_GP_IN_Msk 0x1UL 835 /* SDHC_CORE.GP_OUT_R */ 836 #define SDHC_CORE_GP_OUT_R_CARD_DETECT_EN_Pos 0UL 837 #define SDHC_CORE_GP_OUT_R_CARD_DETECT_EN_Msk 0x1UL 838 #define SDHC_CORE_GP_OUT_R_CARD_MECH_WRITE_PROT_EN_Pos 1UL 839 #define SDHC_CORE_GP_OUT_R_CARD_MECH_WRITE_PROT_EN_Msk 0x2UL 840 #define SDHC_CORE_GP_OUT_R_LED_CTRL_OE_Pos 2UL 841 #define SDHC_CORE_GP_OUT_R_LED_CTRL_OE_Msk 0x4UL 842 #define SDHC_CORE_GP_OUT_R_CARD_CLOCK_OE_Pos 3UL 843 #define SDHC_CORE_GP_OUT_R_CARD_CLOCK_OE_Msk 0x8UL 844 #define SDHC_CORE_GP_OUT_R_CARD_IF_PWR_EN_OE_Pos 4UL 845 #define SDHC_CORE_GP_OUT_R_CARD_IF_PWR_EN_OE_Msk 0x10UL 846 #define SDHC_CORE_GP_OUT_R_IO_VOLT_SEL_OE_Pos 5UL 847 #define SDHC_CORE_GP_OUT_R_IO_VOLT_SEL_OE_Msk 0x20UL 848 #define SDHC_CORE_GP_OUT_R_CARD_CLOCK_OUT_DLY_Pos 6UL 849 #define SDHC_CORE_GP_OUT_R_CARD_CLOCK_OUT_DLY_Msk 0xC0UL 850 #define SDHC_CORE_GP_OUT_R_CARD_CLOCK_IN_DLY_Pos 8UL 851 #define SDHC_CORE_GP_OUT_R_CARD_CLOCK_IN_DLY_Msk 0x300UL 852 853 854 #endif /* _CYIP_SDHC_H_ */ 855 856 857 /* [] END OF FILE */ 858
