1 /***************************************************************************//**
2 * \file cyip_peri_pclk_v3.h
3 *
4 * \brief
5 * PERI_PCLK IP definitions
6 *
7 ********************************************************************************
8 * \copyright
9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
10 * an affiliate of Cypress Semiconductor Corporation.
11 *
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 *     http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *******************************************************************************/
26 
27 #ifndef _CYIP_PERI_PCLK_V3_H_
28 #define _CYIP_PERI_PCLK_V3_H_
29 
30 #include "cyip_headers.h"
31 
32 /*******************************************************************************
33 *                                  PERI_PCLK
34 *******************************************************************************/
35 
36 #define PERI_PCLK_GR_SECTION_SIZE               0x00002000UL
37 #define PERI_PCLK_SECTION_SIZE                  0x00020000UL
38 
39 /**
40   * \brief PERI clock domains (PERI_PCLK_GR)
41   */
42 typedef struct {
43   __IOM uint32_t DIV_CMD;                       /*!< 0x00000000 Divider command */
44    __IM uint32_t RESERVED[767];
45   __IOM uint32_t CLOCK_CTL[256];                /*!< 0x00000C00 Clock control */
46   __IOM uint32_t DIV_8_CTL[256];                /*!< 0x00001000 Divider control (for 8.0 divider) */
47   __IOM uint32_t DIV_16_CTL[256];               /*!< 0x00001400 Divider control (for 16.0 divider) */
48   __IOM uint32_t DIV_16_5_CTL[256];             /*!< 0x00001800 Divider control (for 16.5 divider) */
49   __IOM uint32_t DIV_24_5_CTL[255];             /*!< 0x00001C00 Divider control (for 24.5 divider) */
50    __IM uint32_t RESERVED1;
51 } PERI_PCLK_GR_Type;                            /*!< Size = 8192 (0x2000) */
52 
53 /**
54   * \brief Peripheral PCLK groups (PERI_PCLK)
55   */
56 typedef struct {
57         PERI_PCLK_GR_Type GR[16];               /*!< 0x00000000 PERI clock domains */
58 } PERI_PCLK_Type;                               /*!< Size = 131072 (0x20000) */
59 
60 
61 /* PERI_PCLK_GR.DIV_CMD */
62 #define PERI_PCLK_GR_DIV_CMD_DIV_SEL_Pos        0UL
63 #define PERI_PCLK_GR_DIV_CMD_DIV_SEL_Msk        0xFFUL
64 #define PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Pos       8UL
65 #define PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Msk       0x300UL
66 #define PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Pos     16UL
67 #define PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Msk     0xFF0000UL
68 #define PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Pos    24UL
69 #define PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Msk    0x3000000UL
70 #define PERI_PCLK_GR_DIV_CMD_DISABLE_Pos        30UL
71 #define PERI_PCLK_GR_DIV_CMD_DISABLE_Msk        0x40000000UL
72 #define PERI_PCLK_GR_DIV_CMD_ENABLE_Pos         31UL
73 #define PERI_PCLK_GR_DIV_CMD_ENABLE_Msk         0x80000000UL
74 /* PERI_PCLK_GR.CLOCK_CTL */
75 #define PERI_PCLK_GR_CLOCK_CTL_DIV_SEL_Pos      0UL
76 #define PERI_PCLK_GR_CLOCK_CTL_DIV_SEL_Msk      0xFFUL
77 #define PERI_PCLK_GR_CLOCK_CTL_TYPE_SEL_Pos     8UL
78 #define PERI_PCLK_GR_CLOCK_CTL_TYPE_SEL_Msk     0x300UL
79 /* PERI_PCLK_GR.DIV_8_CTL */
80 #define PERI_PCLK_GR_DIV_8_CTL_EN_Pos           0UL
81 #define PERI_PCLK_GR_DIV_8_CTL_EN_Msk           0x1UL
82 #define PERI_PCLK_GR_DIV_8_CTL_INT8_DIV_Pos     8UL
83 #define PERI_PCLK_GR_DIV_8_CTL_INT8_DIV_Msk     0xFF00UL
84 /* PERI_PCLK_GR.DIV_16_CTL */
85 #define PERI_PCLK_GR_DIV_16_CTL_EN_Pos          0UL
86 #define PERI_PCLK_GR_DIV_16_CTL_EN_Msk          0x1UL
87 #define PERI_PCLK_GR_DIV_16_CTL_INT16_DIV_Pos   8UL
88 #define PERI_PCLK_GR_DIV_16_CTL_INT16_DIV_Msk   0xFFFF00UL
89 /* PERI_PCLK_GR.DIV_16_5_CTL */
90 #define PERI_PCLK_GR_DIV_16_5_CTL_EN_Pos        0UL
91 #define PERI_PCLK_GR_DIV_16_5_CTL_EN_Msk        0x1UL
92 #define PERI_PCLK_GR_DIV_16_5_CTL_FRAC5_DIV_Pos 3UL
93 #define PERI_PCLK_GR_DIV_16_5_CTL_FRAC5_DIV_Msk 0xF8UL
94 #define PERI_PCLK_GR_DIV_16_5_CTL_INT16_DIV_Pos 8UL
95 #define PERI_PCLK_GR_DIV_16_5_CTL_INT16_DIV_Msk 0xFFFF00UL
96 /* PERI_PCLK_GR.DIV_24_5_CTL */
97 #define PERI_PCLK_GR_DIV_24_5_CTL_EN_Pos        0UL
98 #define PERI_PCLK_GR_DIV_24_5_CTL_EN_Msk        0x1UL
99 #define PERI_PCLK_GR_DIV_24_5_CTL_FRAC5_DIV_Pos 3UL
100 #define PERI_PCLK_GR_DIV_24_5_CTL_FRAC5_DIV_Msk 0xF8UL
101 #define PERI_PCLK_GR_DIV_24_5_CTL_INT24_DIV_Pos 8UL
102 #define PERI_PCLK_GR_DIV_24_5_CTL_INT24_DIV_Msk 0xFFFFFF00UL
103 
104 
105 #endif /* _CYIP_PERI_PCLK_V3_H_ */
106 
107 
108 /* [] END OF FILE */
109