1 /***************************************************************************//** 2 * \file cyip_peri.h 3 * 4 * \brief 5 * PERI IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_PERI_H_ 28 #define _CYIP_PERI_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * PERI 34 *******************************************************************************/ 35 36 #define PERI_GR_SECTION_SIZE 0x00000040UL 37 #define PERI_TR_GR_SECTION_SIZE 0x00000400UL 38 #define PERI_TR_1TO1_GR_SECTION_SIZE 0x00000400UL 39 #define PERI_SECTION_SIZE 0x00010000UL 40 41 /** 42 * \brief Peripheral group structure (PERI_GR) 43 */ 44 typedef struct { 45 __IOM uint32_t CLOCK_CTL; /*!< 0x00000000 Clock control */ 46 __IM uint32_t RESERVED[3]; 47 __IOM uint32_t SL_CTL; /*!< 0x00000010 Slave control */ 48 __IOM uint32_t SL_CTL2; /*!< 0x00000014 Slave control2 */ 49 __IM uint32_t SL_CTL3; /*!< 0x00000018 Slave control3 */ 50 __IM uint32_t RESERVED1; 51 __IOM uint32_t SL_WOUND; /*!< 0x00000020 Slave wounding */ 52 __IM uint32_t RESERVED2[7]; 53 } PERI_GR_Type; /*!< Size = 64 (0x40) */ 54 55 /** 56 * \brief Trigger group (PERI_TR_GR) 57 */ 58 typedef struct { 59 __IOM uint32_t TR_CTL[256]; /*!< 0x00000000 Trigger control register */ 60 } PERI_TR_GR_Type; /*!< Size = 1024 (0x400) */ 61 62 /** 63 * \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR) 64 */ 65 typedef struct { 66 __IOM uint32_t TR_CTL[256]; /*!< 0x00000000 Trigger control register */ 67 } PERI_TR_1TO1_GR_Type; /*!< Size = 1024 (0x400) */ 68 69 /** 70 * \brief Peripheral interconnect (PERI) 71 */ 72 typedef struct { 73 __IM uint32_t RESERVED[128]; 74 __IOM uint32_t TIMEOUT_CTL; /*!< 0x00000200 Timeout control */ 75 __IM uint32_t RESERVED1[895]; 76 __IM uint32_t AHB_ERROR_STATUS1[16]; /*!< 0x00001000 AHB error status1 */ 77 __IM uint32_t AHB_ERROR_STATUS2[16]; /*!< 0x00001040 AHB error status2 */ 78 __IM uint32_t AHB_ERROR_STATUS3[16]; /*!< 0x00001080 AHB error status3 */ 79 __IOM uint32_t INTR_AHB_ERROR; /*!< 0x000010C0 Interrupt AHB error */ 80 __IOM uint32_t INTR_AHB_ERROR_SET; /*!< 0x000010C4 Interrupt AHB error set */ 81 __IOM uint32_t INTR_AHB_ERROR_MASK; /*!< 0x000010C8 Interrupt AHB error mask */ 82 __IM uint32_t INTR_AHB_ERROR_MASKED; /*!< 0x000010CC Interrupt AHB error masked */ 83 __IM uint32_t RESERVED2[972]; 84 __IOM uint32_t TR_CMD; /*!< 0x00002000 Trigger command */ 85 __IOM uint32_t INFRA_CLK_FORCE; /*!< 0x00002004 Infrastructure clock force enable */ 86 __IM uint32_t RESERVED3[2046]; 87 PERI_GR_Type GR[16]; /*!< 0x00004000 Peripheral group structure */ 88 __IM uint32_t RESERVED4[3840]; 89 PERI_TR_GR_Type TR_GR[16]; /*!< 0x00008000 Trigger group */ 90 PERI_TR_1TO1_GR_Type TR_1TO1_GR[16]; /*!< 0x0000C000 Trigger 1-to-1 group */ 91 } PERI_Type; /*!< Size = 65536 (0x10000) */ 92 93 94 /* PERI_GR.CLOCK_CTL */ 95 #define PERI_GR_CLOCK_CTL_INT8_DIV_Pos 8UL 96 #define PERI_GR_CLOCK_CTL_INT8_DIV_Msk 0xFF00UL 97 /* PERI_GR.SL_CTL */ 98 #define PERI_GR_SL_CTL_ENABLED_Pos 0UL 99 #define PERI_GR_SL_CTL_ENABLED_Msk 0xFFFFFFFFUL 100 /* PERI_GR.SL_CTL2 */ 101 #define PERI_GR_SL_CTL2_RST_Pos 0UL 102 #define PERI_GR_SL_CTL2_RST_Msk 0xFFFFFFFFUL 103 /* PERI_GR.SL_CTL3 */ 104 #define PERI_GR_SL_CTL3_SS_POWERSTATE_Pos 0UL 105 #define PERI_GR_SL_CTL3_SS_POWERSTATE_Msk 0xFFFFFFFFUL 106 /* PERI_GR.SL_WOUND */ 107 #define PERI_GR_SL_WOUND_DISABLED_Pos 0UL 108 #define PERI_GR_SL_WOUND_DISABLED_Msk 0xFFFFFFFFUL 109 110 111 /* PERI_TR_GR.TR_CTL */ 112 #define PERI_TR_GR_TR_CTL_TR_SEL_Pos 0UL 113 #define PERI_TR_GR_TR_CTL_TR_SEL_Msk 0xFFUL 114 #define PERI_TR_GR_TR_CTL_TR_INV_Pos 8UL 115 #define PERI_TR_GR_TR_CTL_TR_INV_Msk 0x100UL 116 #define PERI_TR_GR_TR_CTL_TR_EDGE_Pos 9UL 117 #define PERI_TR_GR_TR_CTL_TR_EDGE_Msk 0x200UL 118 #define PERI_TR_GR_TR_CTL_DBG_FREEZE_EN_Pos 12UL 119 #define PERI_TR_GR_TR_CTL_DBG_FREEZE_EN_Msk 0x1000UL 120 121 122 /* PERI_TR_1TO1_GR.TR_CTL */ 123 #define PERI_TR_1TO1_GR_TR_CTL_TR_SEL_Pos 0UL 124 #define PERI_TR_1TO1_GR_TR_CTL_TR_SEL_Msk 0x1UL 125 #define PERI_TR_1TO1_GR_TR_CTL_TR_INV_Pos 8UL 126 #define PERI_TR_1TO1_GR_TR_CTL_TR_INV_Msk 0x100UL 127 #define PERI_TR_1TO1_GR_TR_CTL_TR_EDGE_Pos 9UL 128 #define PERI_TR_1TO1_GR_TR_CTL_TR_EDGE_Msk 0x200UL 129 #define PERI_TR_1TO1_GR_TR_CTL_DBG_FREEZE_EN_Pos 12UL 130 #define PERI_TR_1TO1_GR_TR_CTL_DBG_FREEZE_EN_Msk 0x1000UL 131 132 133 /* PERI.TIMEOUT_CTL */ 134 #define PERI_TIMEOUT_CTL_TIMEOUT_Pos 0UL 135 #define PERI_TIMEOUT_CTL_TIMEOUT_Msk 0xFFFFUL 136 #define PERI_TIMEOUT_CTL_HWRST_DISABLE_Pos 31UL 137 #define PERI_TIMEOUT_CTL_HWRST_DISABLE_Msk 0x80000000UL 138 /* PERI.AHB_ERROR_STATUS1 */ 139 #define PERI_AHB_ERROR_STATUS1_ADDR_Pos 0UL 140 #define PERI_AHB_ERROR_STATUS1_ADDR_Msk 0xFFFFFFFFUL 141 /* PERI.AHB_ERROR_STATUS2 */ 142 #define PERI_AHB_ERROR_STATUS2_P_Pos 0UL 143 #define PERI_AHB_ERROR_STATUS2_P_Msk 0x1UL 144 #define PERI_AHB_ERROR_STATUS2_NS_Pos 1UL 145 #define PERI_AHB_ERROR_STATUS2_NS_Msk 0x2UL 146 #define PERI_AHB_ERROR_STATUS2_W_Pos 2UL 147 #define PERI_AHB_ERROR_STATUS2_W_Msk 0x4UL 148 #define PERI_AHB_ERROR_STATUS2_PC_Pos 4UL 149 #define PERI_AHB_ERROR_STATUS2_PC_Msk 0xF0UL 150 #define PERI_AHB_ERROR_STATUS2_MS_Pos 8UL 151 #define PERI_AHB_ERROR_STATUS2_MS_Msk 0xFFFF00UL 152 #define PERI_AHB_ERROR_STATUS2_TYPE_Pos 30UL 153 #define PERI_AHB_ERROR_STATUS2_TYPE_Msk 0xC0000000UL 154 /* PERI.AHB_ERROR_STATUS3 */ 155 #define PERI_AHB_ERROR_STATUS3_SLAVE_NO_Pos 0UL 156 #define PERI_AHB_ERROR_STATUS3_SLAVE_NO_Msk 0x1FUL 157 /* PERI.INTR_AHB_ERROR */ 158 #define PERI_INTR_AHB_ERROR_AHB_ERROR_VIO_Pos 0UL 159 #define PERI_INTR_AHB_ERROR_AHB_ERROR_VIO_Msk 0xFFFFUL 160 #define PERI_INTR_AHB_ERROR_TIMEOUT_VIO_Pos 17UL 161 #define PERI_INTR_AHB_ERROR_TIMEOUT_VIO_Msk 0xFFFE0000UL 162 /* PERI.INTR_AHB_ERROR_SET */ 163 #define PERI_INTR_AHB_ERROR_SET_AHB_ERROR_VIO_Pos 0UL 164 #define PERI_INTR_AHB_ERROR_SET_AHB_ERROR_VIO_Msk 0xFFFFUL 165 #define PERI_INTR_AHB_ERROR_SET_TIMEOUT_VIO_Pos 17UL 166 #define PERI_INTR_AHB_ERROR_SET_TIMEOUT_VIO_Msk 0xFFFE0000UL 167 /* PERI.INTR_AHB_ERROR_MASK */ 168 #define PERI_INTR_AHB_ERROR_MASK_AHB_ERROR_VIO_Pos 0UL 169 #define PERI_INTR_AHB_ERROR_MASK_AHB_ERROR_VIO_Msk 0xFFFFUL 170 #define PERI_INTR_AHB_ERROR_MASK_TIMEOUT_VIO_Pos 17UL 171 #define PERI_INTR_AHB_ERROR_MASK_TIMEOUT_VIO_Msk 0xFFFE0000UL 172 /* PERI.INTR_AHB_ERROR_MASKED */ 173 #define PERI_INTR_AHB_ERROR_MASKED_AHB_ERROR_VIO_Pos 0UL 174 #define PERI_INTR_AHB_ERROR_MASKED_AHB_ERROR_VIO_Msk 0xFFFFUL 175 #define PERI_INTR_AHB_ERROR_MASKED_TIMEOUT_VIO_Pos 17UL 176 #define PERI_INTR_AHB_ERROR_MASKED_TIMEOUT_VIO_Msk 0xFFFE0000UL 177 /* PERI.TR_CMD */ 178 #define PERI_TR_CMD_TR_SEL_Pos 0UL 179 #define PERI_TR_CMD_TR_SEL_Msk 0xFFUL 180 #define PERI_TR_CMD_GROUP_SEL_Pos 8UL 181 #define PERI_TR_CMD_GROUP_SEL_Msk 0x1F00UL 182 #define PERI_TR_CMD_TR_EDGE_Pos 29UL 183 #define PERI_TR_CMD_TR_EDGE_Msk 0x20000000UL 184 #define PERI_TR_CMD_OUT_SEL_Pos 30UL 185 #define PERI_TR_CMD_OUT_SEL_Msk 0x40000000UL 186 #define PERI_TR_CMD_ACTIVATE_Pos 31UL 187 #define PERI_TR_CMD_ACTIVATE_Msk 0x80000000UL 188 /* PERI.INFRA_CLK_FORCE */ 189 #define PERI_INFRA_CLK_FORCE_ENABLED_Pos 0UL 190 #define PERI_INFRA_CLK_FORCE_ENABLED_Msk 0x1UL 191 192 193 #endif /* _CYIP_PERI_H_ */ 194 195 196 /* [] END OF FILE */ 197
