1 /***************************************************************************//** 2 * \file cyip_btss.h 3 * 4 * \brief 5 * BTSS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_BTSS_H_ 28 #define _CYIP_BTSS_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * BTSS 34 *******************************************************************************/ 35 36 #define BTSS_DATA_RAM_IPC_SECTION_SIZE 0x000186A0UL 37 #define BTSS_SECTION_SIZE 0x01000000UL 38 39 /** 40 * \brief N/A (BTSS_DATA_RAM_IPC) 41 */ 42 typedef struct { 43 __IM uint32_t RESERVED[131072]; 44 __IOM uint32_t MXIPC_0_ACQUIRE; /*!< 0x00080000 N/A */ 45 __IOM uint32_t MXIPC_0_RELEASE; /*!< 0x00080004 N/A */ 46 __IOM uint32_t MXIPC_0_NOTIFY; /*!< 0x00080008 N/A */ 47 __IOM uint32_t MXIPC_0_DATA0; /*!< 0x0008000C N/A */ 48 __IOM uint32_t MXIPC_0_DATA1; /*!< 0x00080010 N/A */ 49 __IM uint32_t RESERVED1[2]; 50 __IM uint32_t MXIPC_0_LOCK_STATUS; /*!< 0x0008001C N/A */ 51 __IOM uint32_t MXIPC_1_ACQUIRE; /*!< 0x00080020 N/A */ 52 __IOM uint32_t MXIPC_1_RELEASE; /*!< 0x00080024 N/A */ 53 __IOM uint32_t MXIPC_1_NOTIFY; /*!< 0x00080028 N/A */ 54 __IOM uint32_t MXIPC_1_DATA0; /*!< 0x0008002C N/A */ 55 __IOM uint32_t MXIPC_1_DATA1; /*!< 0x00080030 N/A */ 56 __IM uint32_t RESERVED2[2]; 57 __IM uint32_t MXIPC_1_LOCK_STATUS; /*!< 0x0008003C N/A */ 58 __IOM uint32_t MXIPC_2_ACQUIRE; /*!< 0x00080040 N/A */ 59 __IOM uint32_t MXIPC_2_RELEASE; /*!< 0x00080044 N/A */ 60 __IOM uint32_t MXIPC_2_NOTIFY; /*!< 0x00080048 N/A */ 61 __IOM uint32_t MXIPC_2_DATA0; /*!< 0x0008004C N/A */ 62 __IOM uint32_t MXIPC_2_DATA1; /*!< 0x00080050 N/A */ 63 __IM uint32_t RESERVED3[2]; 64 __IM uint32_t MXIPC_2_LOCK_STATUS; /*!< 0x0008005C N/A */ 65 __IOM uint32_t MXIPC_3_ACQUIRE; /*!< 0x00080060 N/A */ 66 __IOM uint32_t MXIPC_3_RELEASE; /*!< 0x00080064 N/A */ 67 __IOM uint32_t MXIPC_3_NOTIFY; /*!< 0x00080068 N/A */ 68 __IOM uint32_t MXIPC_3_DATA0; /*!< 0x0008006C N/A */ 69 __IOM uint32_t MXIPC_3_DATA1; /*!< 0x00080070 N/A */ 70 __IM uint32_t RESERVED4[2]; 71 __IM uint32_t MXIPC_3_LOCK_STATUS; /*!< 0x0008007C N/A */ 72 __IM uint32_t RESERVED5[992]; 73 __IOM uint32_t MXIPC_INTR_0; /*!< 0x00081000 N/A */ 74 __IOM uint32_t MXIPC_INTR_0_SET; /*!< 0x00081004 N/A */ 75 __IOM uint32_t MXIPC_INTR_0_MASK; /*!< 0x00081008 N/A */ 76 __IM uint32_t MXIPC_INTR_0_MASKED; /*!< 0x0008100C N/A */ 77 __IM uint32_t RESERVED6[4]; 78 __IOM uint32_t MXIPC_INTR_1; /*!< 0x00081020 N/A */ 79 __IOM uint32_t MXIPC_INTR_1_SET; /*!< 0x00081024 N/A */ 80 __IOM uint32_t MXIPC_INTR_1_MASK; /*!< 0x00081028 N/A */ 81 __IM uint32_t MXIPC_INTR_1_MASKED; /*!< 0x0008102C N/A */ 82 } BTSS_DATA_RAM_IPC_Type; /*!< Size = 528432 (0x81030) */ 83 84 /** 85 * \brief MXS40BLE52SS IP (BTSS) 86 */ 87 typedef struct { 88 __IM uint32_t RESERVED[1572864]; 89 BTSS_DATA_RAM_IPC_Type DATA_RAM_IPC; /*!< 0x00600000 N/A */ 90 } BTSS_Type; /*!< Size = 6391456 (0x6186A0) */ 91 92 93 /* BTSS_DATA_RAM_IPC.MXIPC_0_ACQUIRE */ 94 #define BTSS_DATA_RAM_IPC_MXIPC_0_ACQUIRE_MXIPC_0_ACQUIRE_P_Pos 0UL 95 #define BTSS_DATA_RAM_IPC_MXIPC_0_ACQUIRE_MXIPC_0_ACQUIRE_P_Msk 0x1UL 96 #define BTSS_DATA_RAM_IPC_MXIPC_0_ACQUIRE_MXIPC_0_ACQUIRE_NS_Pos 1UL 97 #define BTSS_DATA_RAM_IPC_MXIPC_0_ACQUIRE_MXIPC_0_ACQUIRE_NS_Msk 0x2UL 98 #define BTSS_DATA_RAM_IPC_MXIPC_0_ACQUIRE_MXIPC_0_ACQUIRE_PC_Pos 4UL 99 #define BTSS_DATA_RAM_IPC_MXIPC_0_ACQUIRE_MXIPC_0_ACQUIRE_PC_Msk 0xF0UL 100 #define BTSS_DATA_RAM_IPC_MXIPC_0_ACQUIRE_MXIPC_0_ACQUIRE_MS_Pos 8UL 101 #define BTSS_DATA_RAM_IPC_MXIPC_0_ACQUIRE_MXIPC_0_ACQUIRE_MS_Msk 0xFF00UL 102 #define BTSS_DATA_RAM_IPC_MXIPC_0_ACQUIRE_MXIPC_0_ACQUIRE_SUCCESS_Pos 31UL 103 #define BTSS_DATA_RAM_IPC_MXIPC_0_ACQUIRE_MXIPC_0_ACQUIRE_SUCCESS_Msk 0x80000000UL 104 /* BTSS_DATA_RAM_IPC.MXIPC_0_RELEASE */ 105 #define BTSS_DATA_RAM_IPC_MXIPC_0_RELEASE_MXIPC_0_RELEASE_Pos 0UL 106 #define BTSS_DATA_RAM_IPC_MXIPC_0_RELEASE_MXIPC_0_RELEASE_Msk 0xFFFFFFFFUL 107 /* BTSS_DATA_RAM_IPC.MXIPC_0_NOTIFY */ 108 #define BTSS_DATA_RAM_IPC_MXIPC_0_NOTIFY_MXIPC_0_NOTIFY_Pos 0UL 109 #define BTSS_DATA_RAM_IPC_MXIPC_0_NOTIFY_MXIPC_0_NOTIFY_Msk 0xFFFFFFFFUL 110 /* BTSS_DATA_RAM_IPC.MXIPC_0_DATA0 */ 111 #define BTSS_DATA_RAM_IPC_MXIPC_0_DATA0_MXIPC_0_DATA0_Pos 0UL 112 #define BTSS_DATA_RAM_IPC_MXIPC_0_DATA0_MXIPC_0_DATA0_Msk 0xFFFFFFFFUL 113 /* BTSS_DATA_RAM_IPC.MXIPC_0_DATA1 */ 114 #define BTSS_DATA_RAM_IPC_MXIPC_0_DATA1_MXIPC_0_DATA1_Pos 0UL 115 #define BTSS_DATA_RAM_IPC_MXIPC_0_DATA1_MXIPC_0_DATA1_Msk 0xFFFFFFFFUL 116 /* BTSS_DATA_RAM_IPC.MXIPC_0_LOCK_STATUS */ 117 #define BTSS_DATA_RAM_IPC_MXIPC_0_LOCK_STATUS_MXIPC_0_LOCK_STATUS_P_Pos 0UL 118 #define BTSS_DATA_RAM_IPC_MXIPC_0_LOCK_STATUS_MXIPC_0_LOCK_STATUS_P_Msk 0x1UL 119 #define BTSS_DATA_RAM_IPC_MXIPC_0_LOCK_STATUS_MXIPC_0_LOCK_STATUS_NS_Pos 1UL 120 #define BTSS_DATA_RAM_IPC_MXIPC_0_LOCK_STATUS_MXIPC_0_LOCK_STATUS_NS_Msk 0x2UL 121 #define BTSS_DATA_RAM_IPC_MXIPC_0_LOCK_STATUS_MXIPC_0_LOCK_STATUS_PC_Pos 4UL 122 #define BTSS_DATA_RAM_IPC_MXIPC_0_LOCK_STATUS_MXIPC_0_LOCK_STATUS_PC_Msk 0xF0UL 123 #define BTSS_DATA_RAM_IPC_MXIPC_0_LOCK_STATUS_MXIPC_0_LOCK_STATUS_MS_Pos 8UL 124 #define BTSS_DATA_RAM_IPC_MXIPC_0_LOCK_STATUS_MXIPC_0_LOCK_STATUS_MS_Msk 0xFF00UL 125 #define BTSS_DATA_RAM_IPC_MXIPC_0_LOCK_STATUS_MXIPC_0_LOCK_STATUS_ACQUIRED_Pos 31UL 126 #define BTSS_DATA_RAM_IPC_MXIPC_0_LOCK_STATUS_MXIPC_0_LOCK_STATUS_ACQUIRED_Msk 0x80000000UL 127 /* BTSS_DATA_RAM_IPC.MXIPC_1_ACQUIRE */ 128 #define BTSS_DATA_RAM_IPC_MXIPC_1_ACQUIRE_MXIPC_1_ACQUIRE_P_Pos 0UL 129 #define BTSS_DATA_RAM_IPC_MXIPC_1_ACQUIRE_MXIPC_1_ACQUIRE_P_Msk 0x1UL 130 #define BTSS_DATA_RAM_IPC_MXIPC_1_ACQUIRE_MXIPC_1_ACQUIRE_NS_Pos 1UL 131 #define BTSS_DATA_RAM_IPC_MXIPC_1_ACQUIRE_MXIPC_1_ACQUIRE_NS_Msk 0x2UL 132 #define BTSS_DATA_RAM_IPC_MXIPC_1_ACQUIRE_MXIPC_1_ACQUIRE_PC_Pos 4UL 133 #define BTSS_DATA_RAM_IPC_MXIPC_1_ACQUIRE_MXIPC_1_ACQUIRE_PC_Msk 0xF0UL 134 #define BTSS_DATA_RAM_IPC_MXIPC_1_ACQUIRE_MXIPC_1_ACQUIRE_MS_Pos 8UL 135 #define BTSS_DATA_RAM_IPC_MXIPC_1_ACQUIRE_MXIPC_1_ACQUIRE_MS_Msk 0xFF00UL 136 #define BTSS_DATA_RAM_IPC_MXIPC_1_ACQUIRE_MXIPC_1_ACQUIRE_SUCCESS_Pos 31UL 137 #define BTSS_DATA_RAM_IPC_MXIPC_1_ACQUIRE_MXIPC_1_ACQUIRE_SUCCESS_Msk 0x80000000UL 138 /* BTSS_DATA_RAM_IPC.MXIPC_1_RELEASE */ 139 #define BTSS_DATA_RAM_IPC_MXIPC_1_RELEASE_MXIPC_1_RELEASE_Pos 0UL 140 #define BTSS_DATA_RAM_IPC_MXIPC_1_RELEASE_MXIPC_1_RELEASE_Msk 0xFFFFFFFFUL 141 /* BTSS_DATA_RAM_IPC.MXIPC_1_NOTIFY */ 142 #define BTSS_DATA_RAM_IPC_MXIPC_1_NOTIFY_MXIPC_1_NOTIFY_Pos 0UL 143 #define BTSS_DATA_RAM_IPC_MXIPC_1_NOTIFY_MXIPC_1_NOTIFY_Msk 0xFFFFFFFFUL 144 /* BTSS_DATA_RAM_IPC.MXIPC_1_DATA0 */ 145 #define BTSS_DATA_RAM_IPC_MXIPC_1_DATA0_MXIPC_1_DATA0_Pos 0UL 146 #define BTSS_DATA_RAM_IPC_MXIPC_1_DATA0_MXIPC_1_DATA0_Msk 0xFFFFFFFFUL 147 /* BTSS_DATA_RAM_IPC.MXIPC_1_DATA1 */ 148 #define BTSS_DATA_RAM_IPC_MXIPC_1_DATA1_MXIPC_1_DATA1_Pos 0UL 149 #define BTSS_DATA_RAM_IPC_MXIPC_1_DATA1_MXIPC_1_DATA1_Msk 0xFFFFFFFFUL 150 /* BTSS_DATA_RAM_IPC.MXIPC_1_LOCK_STATUS */ 151 #define BTSS_DATA_RAM_IPC_MXIPC_1_LOCK_STATUS_MXIPC_1_LOCK_STATUS_P_Pos 0UL 152 #define BTSS_DATA_RAM_IPC_MXIPC_1_LOCK_STATUS_MXIPC_1_LOCK_STATUS_P_Msk 0x1UL 153 #define BTSS_DATA_RAM_IPC_MXIPC_1_LOCK_STATUS_MXIPC_1_LOCK_STATUS_NS_Pos 1UL 154 #define BTSS_DATA_RAM_IPC_MXIPC_1_LOCK_STATUS_MXIPC_1_LOCK_STATUS_NS_Msk 0x2UL 155 #define BTSS_DATA_RAM_IPC_MXIPC_1_LOCK_STATUS_MXIPC_1_LOCK_STATUS_PC_Pos 4UL 156 #define BTSS_DATA_RAM_IPC_MXIPC_1_LOCK_STATUS_MXIPC_1_LOCK_STATUS_PC_Msk 0xF0UL 157 #define BTSS_DATA_RAM_IPC_MXIPC_1_LOCK_STATUS_MXIPC_1_LOCK_STATUS_MS_Pos 8UL 158 #define BTSS_DATA_RAM_IPC_MXIPC_1_LOCK_STATUS_MXIPC_1_LOCK_STATUS_MS_Msk 0xFF00UL 159 #define BTSS_DATA_RAM_IPC_MXIPC_1_LOCK_STATUS_MXIPC_1_LOCK_STATUS_ACQUIRED_Pos 31UL 160 #define BTSS_DATA_RAM_IPC_MXIPC_1_LOCK_STATUS_MXIPC_1_LOCK_STATUS_ACQUIRED_Msk 0x80000000UL 161 /* BTSS_DATA_RAM_IPC.MXIPC_2_ACQUIRE */ 162 #define BTSS_DATA_RAM_IPC_MXIPC_2_ACQUIRE_MXIPC_2_ACQUIRE_P_Pos 0UL 163 #define BTSS_DATA_RAM_IPC_MXIPC_2_ACQUIRE_MXIPC_2_ACQUIRE_P_Msk 0x1UL 164 #define BTSS_DATA_RAM_IPC_MXIPC_2_ACQUIRE_MXIPC_2_ACQUIRE_NS_Pos 1UL 165 #define BTSS_DATA_RAM_IPC_MXIPC_2_ACQUIRE_MXIPC_2_ACQUIRE_NS_Msk 0x2UL 166 #define BTSS_DATA_RAM_IPC_MXIPC_2_ACQUIRE_MXIPC_2_ACQUIRE_PC_Pos 4UL 167 #define BTSS_DATA_RAM_IPC_MXIPC_2_ACQUIRE_MXIPC_2_ACQUIRE_PC_Msk 0xF0UL 168 #define BTSS_DATA_RAM_IPC_MXIPC_2_ACQUIRE_MXIPC_2_ACQUIRE_MS_Pos 8UL 169 #define BTSS_DATA_RAM_IPC_MXIPC_2_ACQUIRE_MXIPC_2_ACQUIRE_MS_Msk 0xFF00UL 170 #define BTSS_DATA_RAM_IPC_MXIPC_2_ACQUIRE_MXIPC_2_ACQUIRE_SUCCESS_Pos 31UL 171 #define BTSS_DATA_RAM_IPC_MXIPC_2_ACQUIRE_MXIPC_2_ACQUIRE_SUCCESS_Msk 0x80000000UL 172 /* BTSS_DATA_RAM_IPC.MXIPC_2_RELEASE */ 173 #define BTSS_DATA_RAM_IPC_MXIPC_2_RELEASE_MXIPC_2_RELEASE_Pos 0UL 174 #define BTSS_DATA_RAM_IPC_MXIPC_2_RELEASE_MXIPC_2_RELEASE_Msk 0xFFFFFFFFUL 175 /* BTSS_DATA_RAM_IPC.MXIPC_2_NOTIFY */ 176 #define BTSS_DATA_RAM_IPC_MXIPC_2_NOTIFY_MXIPC_2_NOTIFY_Pos 0UL 177 #define BTSS_DATA_RAM_IPC_MXIPC_2_NOTIFY_MXIPC_2_NOTIFY_Msk 0xFFFFFFFFUL 178 /* BTSS_DATA_RAM_IPC.MXIPC_2_DATA0 */ 179 #define BTSS_DATA_RAM_IPC_MXIPC_2_DATA0_MXIPC_2_DATA0_Pos 0UL 180 #define BTSS_DATA_RAM_IPC_MXIPC_2_DATA0_MXIPC_2_DATA0_Msk 0xFFFFFFFFUL 181 /* BTSS_DATA_RAM_IPC.MXIPC_2_DATA1 */ 182 #define BTSS_DATA_RAM_IPC_MXIPC_2_DATA1_MXIPC_2_DATA1_Pos 0UL 183 #define BTSS_DATA_RAM_IPC_MXIPC_2_DATA1_MXIPC_2_DATA1_Msk 0xFFFFFFFFUL 184 /* BTSS_DATA_RAM_IPC.MXIPC_2_LOCK_STATUS */ 185 #define BTSS_DATA_RAM_IPC_MXIPC_2_LOCK_STATUS_MXIPC_2_LOCK_STATUS_P_Pos 0UL 186 #define BTSS_DATA_RAM_IPC_MXIPC_2_LOCK_STATUS_MXIPC_2_LOCK_STATUS_P_Msk 0x1UL 187 #define BTSS_DATA_RAM_IPC_MXIPC_2_LOCK_STATUS_MXIPC_2_LOCK_STATUS_NS_Pos 1UL 188 #define BTSS_DATA_RAM_IPC_MXIPC_2_LOCK_STATUS_MXIPC_2_LOCK_STATUS_NS_Msk 0x2UL 189 #define BTSS_DATA_RAM_IPC_MXIPC_2_LOCK_STATUS_MXIPC_2_LOCK_STATUS_PC_Pos 4UL 190 #define BTSS_DATA_RAM_IPC_MXIPC_2_LOCK_STATUS_MXIPC_2_LOCK_STATUS_PC_Msk 0xF0UL 191 #define BTSS_DATA_RAM_IPC_MXIPC_2_LOCK_STATUS_MXIPC_2_LOCK_STATUS_MS_Pos 8UL 192 #define BTSS_DATA_RAM_IPC_MXIPC_2_LOCK_STATUS_MXIPC_2_LOCK_STATUS_MS_Msk 0xFF00UL 193 #define BTSS_DATA_RAM_IPC_MXIPC_2_LOCK_STATUS_MXIPC_2_LOCK_STATUS_ACQUIRED_Pos 31UL 194 #define BTSS_DATA_RAM_IPC_MXIPC_2_LOCK_STATUS_MXIPC_2_LOCK_STATUS_ACQUIRED_Msk 0x80000000UL 195 /* BTSS_DATA_RAM_IPC.MXIPC_3_ACQUIRE */ 196 #define BTSS_DATA_RAM_IPC_MXIPC_3_ACQUIRE_MXIPC_3_ACQUIRE_P_Pos 0UL 197 #define BTSS_DATA_RAM_IPC_MXIPC_3_ACQUIRE_MXIPC_3_ACQUIRE_P_Msk 0x1UL 198 #define BTSS_DATA_RAM_IPC_MXIPC_3_ACQUIRE_MXIPC_3_ACQUIRE_NS_Pos 1UL 199 #define BTSS_DATA_RAM_IPC_MXIPC_3_ACQUIRE_MXIPC_3_ACQUIRE_NS_Msk 0x2UL 200 #define BTSS_DATA_RAM_IPC_MXIPC_3_ACQUIRE_MXIPC_3_ACQUIRE_PC_Pos 4UL 201 #define BTSS_DATA_RAM_IPC_MXIPC_3_ACQUIRE_MXIPC_3_ACQUIRE_PC_Msk 0xF0UL 202 #define BTSS_DATA_RAM_IPC_MXIPC_3_ACQUIRE_MXIPC_3_ACQUIRE_MS_Pos 8UL 203 #define BTSS_DATA_RAM_IPC_MXIPC_3_ACQUIRE_MXIPC_3_ACQUIRE_MS_Msk 0xFF00UL 204 #define BTSS_DATA_RAM_IPC_MXIPC_3_ACQUIRE_MXIPC_3_ACQUIRE_SUCCESS_Pos 31UL 205 #define BTSS_DATA_RAM_IPC_MXIPC_3_ACQUIRE_MXIPC_3_ACQUIRE_SUCCESS_Msk 0x80000000UL 206 /* BTSS_DATA_RAM_IPC.MXIPC_3_RELEASE */ 207 #define BTSS_DATA_RAM_IPC_MXIPC_3_RELEASE_MXIPC_3_RELEASE_Pos 0UL 208 #define BTSS_DATA_RAM_IPC_MXIPC_3_RELEASE_MXIPC_3_RELEASE_Msk 0xFFFFFFFFUL 209 /* BTSS_DATA_RAM_IPC.MXIPC_3_NOTIFY */ 210 #define BTSS_DATA_RAM_IPC_MXIPC_3_NOTIFY_MXIPC_3_NOTIFY_Pos 0UL 211 #define BTSS_DATA_RAM_IPC_MXIPC_3_NOTIFY_MXIPC_3_NOTIFY_Msk 0xFFFFFFFFUL 212 /* BTSS_DATA_RAM_IPC.MXIPC_3_DATA0 */ 213 #define BTSS_DATA_RAM_IPC_MXIPC_3_DATA0_MXIPC_3_DATA0_Pos 0UL 214 #define BTSS_DATA_RAM_IPC_MXIPC_3_DATA0_MXIPC_3_DATA0_Msk 0xFFFFFFFFUL 215 /* BTSS_DATA_RAM_IPC.MXIPC_3_DATA1 */ 216 #define BTSS_DATA_RAM_IPC_MXIPC_3_DATA1_MXIPC_3_DATA1_Pos 0UL 217 #define BTSS_DATA_RAM_IPC_MXIPC_3_DATA1_MXIPC_3_DATA1_Msk 0xFFFFFFFFUL 218 /* BTSS_DATA_RAM_IPC.MXIPC_3_LOCK_STATUS */ 219 #define BTSS_DATA_RAM_IPC_MXIPC_3_LOCK_STATUS_MXIPC_3_LOCK_STATUS_P_Pos 0UL 220 #define BTSS_DATA_RAM_IPC_MXIPC_3_LOCK_STATUS_MXIPC_3_LOCK_STATUS_P_Msk 0x1UL 221 #define BTSS_DATA_RAM_IPC_MXIPC_3_LOCK_STATUS_MXIPC_3_LOCK_STATUS_NS_Pos 1UL 222 #define BTSS_DATA_RAM_IPC_MXIPC_3_LOCK_STATUS_MXIPC_3_LOCK_STATUS_NS_Msk 0x2UL 223 #define BTSS_DATA_RAM_IPC_MXIPC_3_LOCK_STATUS_MXIPC_3_LOCK_STATUS_PC_Pos 4UL 224 #define BTSS_DATA_RAM_IPC_MXIPC_3_LOCK_STATUS_MXIPC_3_LOCK_STATUS_PC_Msk 0xF0UL 225 #define BTSS_DATA_RAM_IPC_MXIPC_3_LOCK_STATUS_MXIPC_3_LOCK_STATUS_MS_Pos 8UL 226 #define BTSS_DATA_RAM_IPC_MXIPC_3_LOCK_STATUS_MXIPC_3_LOCK_STATUS_MS_Msk 0xFF00UL 227 #define BTSS_DATA_RAM_IPC_MXIPC_3_LOCK_STATUS_MXIPC_3_LOCK_STATUS_ACQUIRED_Pos 31UL 228 #define BTSS_DATA_RAM_IPC_MXIPC_3_LOCK_STATUS_MXIPC_3_LOCK_STATUS_ACQUIRED_Msk 0x80000000UL 229 /* BTSS_DATA_RAM_IPC.MXIPC_INTR_0 */ 230 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_0_MXIPC_INTR_0_MXIPC_INTR_0_RELEASE________Pos 0UL 231 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_0_MXIPC_INTR_0_MXIPC_INTR_0_RELEASE________Msk 0xFFFFUL 232 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_0_MXIPC_INTR_0_MXIPC_INTR_0_NOTIFY_Pos 16UL 233 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_0_MXIPC_INTR_0_MXIPC_INTR_0_NOTIFY_Msk 0xFFFF0000UL 234 /* BTSS_DATA_RAM_IPC.MXIPC_INTR_0_SET */ 235 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_0_SET_MXIPC_INTR_0_SET_MXIPC_INTR_0_SET_RELEASE________Pos 0UL 236 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_0_SET_MXIPC_INTR_0_SET_MXIPC_INTR_0_SET_RELEASE________Msk 0xFFFFUL 237 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_0_SET_MXIPC_INTR_0_SET_MXIPC_INTR_0_SET_NOTIFY_Pos 16UL 238 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_0_SET_MXIPC_INTR_0_SET_MXIPC_INTR_0_SET_NOTIFY_Msk 0xFFFF0000UL 239 /* BTSS_DATA_RAM_IPC.MXIPC_INTR_0_MASK */ 240 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_0_MASK_MXIPC_INTR_0_MASK_MXIPC_INTR_0_MASK_RELEASE________Pos 0UL 241 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_0_MASK_MXIPC_INTR_0_MASK_MXIPC_INTR_0_MASK_RELEASE________Msk 0xFFFFUL 242 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_0_MASK_MXIPC_INTR_0_MASK_MXIPC_INTR_0_MASK_NOTIFY_Pos 16UL 243 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_0_MASK_MXIPC_INTR_0_MASK_MXIPC_INTR_0_MASK_NOTIFY_Msk 0xFFFF0000UL 244 /* BTSS_DATA_RAM_IPC.MXIPC_INTR_0_MASKED */ 245 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_0_MASKED_MXIPC_INTR_0_MASKED_MXIPC_INTR_0_MASKED_RELEASE________Pos 0UL 246 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_0_MASKED_MXIPC_INTR_0_MASKED_MXIPC_INTR_0_MASKED_RELEASE________Msk 0xFFFFUL 247 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_0_MASKED_MXIPC_INTR_0_MASKED_MXIPC_INTR_0_MASKED_NOTIFY_Pos 16UL 248 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_0_MASKED_MXIPC_INTR_0_MASKED_MXIPC_INTR_0_MASKED_NOTIFY_Msk 0xFFFF0000UL 249 /* BTSS_DATA_RAM_IPC.MXIPC_INTR_1 */ 250 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_1_MXIPC_INTR_1_MXIPC_INTR_1_RELEASE________Pos 0UL 251 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_1_MXIPC_INTR_1_MXIPC_INTR_1_RELEASE________Msk 0xFFFFUL 252 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_1_MXIPC_INTR_1_MXIPC_INTR_1_NOTIFY_Pos 16UL 253 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_1_MXIPC_INTR_1_MXIPC_INTR_1_NOTIFY_Msk 0xFFFF0000UL 254 /* BTSS_DATA_RAM_IPC.MXIPC_INTR_1_SET */ 255 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_1_SET_MXIPC_INTR_1_SET_MXIPC_INTR_1_SET_RELEASE________Pos 0UL 256 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_1_SET_MXIPC_INTR_1_SET_MXIPC_INTR_1_SET_RELEASE________Msk 0xFFFFUL 257 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_1_SET_MXIPC_INTR_1_SET_MXIPC_INTR_1_SET_NOTIFY_Pos 16UL 258 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_1_SET_MXIPC_INTR_1_SET_MXIPC_INTR_1_SET_NOTIFY_Msk 0xFFFF0000UL 259 /* BTSS_DATA_RAM_IPC.MXIPC_INTR_1_MASK */ 260 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_1_MASK_MXIPC_INTR_1_MASK_MXIPC_INTR_1_MASK_RELEASE________Pos 0UL 261 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_1_MASK_MXIPC_INTR_1_MASK_MXIPC_INTR_1_MASK_RELEASE________Msk 0xFFFFUL 262 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_1_MASK_MXIPC_INTR_1_MASK_MXIPC_INTR_1_MASK_NOTIFY_Pos 16UL 263 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_1_MASK_MXIPC_INTR_1_MASK_MXIPC_INTR_1_MASK_NOTIFY_Msk 0xFFFF0000UL 264 /* BTSS_DATA_RAM_IPC.MXIPC_INTR_1_MASKED */ 265 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_1_MASKED_MXIPC_INTR_1_MASKED_MXIPC_INTR_1_MASKED_RELEASE________Pos 0UL 266 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_1_MASKED_MXIPC_INTR_1_MASKED_MXIPC_INTR_1_MASKED_RELEASE________Msk 0xFFFFUL 267 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_1_MASKED_MXIPC_INTR_1_MASKED_MXIPC_INTR_1_MASKED_NOTIFY_Pos 16UL 268 #define BTSS_DATA_RAM_IPC_MXIPC_INTR_1_MASKED_MXIPC_INTR_1_MASKED_MXIPC_INTR_1_MASKED_NOTIFY_Msk 0xFFFF0000UL 269 270 271 #endif /* _CYIP_BTSS_H_ */ 272 273 274 /* [] END OF FILE */ 275
