1<?xml version="1.0" encoding="utf-8"?>
2<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
3  <vendor>Cypress Semiconductor</vendor>
4  <vendorID>Cypress</vendorID>
5  <name>tviibe1m</name>
6  <series>TVIIBE1M</series>
7  <version>1.0</version>
8  <description>TVIIBE1M</description>
9  <licenseText>(c) (2016-2021), Cypress Semiconductor Corporation (an Infineon company)\n
10    or an affiliate of Cypress Semiconductor Corporation.\n
11\n
12    SPDX-License-Identifier: Apache-2.0\n
13\n
14    Licensed under the Apache License, Version 2.0 (the "License");\n
15    you may not use this file except in compliance with the License.\n
16    You may obtain a copy of the License at\n
17\n
18      http://www.apache.org/licenses/LICENSE-2.0\n
19\n
20    Unless required by applicable law or agreed to in writing, software\n
21    distributed under the License is distributed on an "AS IS" BASIS,\n
22    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
23    See the License for the specific language governing permissions and\n
24    limitations under the License.</licenseText>
25  <cpu>
26    <name>CM4</name>
27    <revision>r0p1</revision>
28    <endian>little</endian>
29    <mpuPresent>true</mpuPresent>
30    <fpuPresent>true</fpuPresent>
31    <vtorPresent>1</vtorPresent>
32    <nvicPrioBits>3</nvicPrioBits>
33    <vendorSystickConfig>0</vendorSystickConfig>
34  </cpu>
35  <addressUnitBits>8</addressUnitBits>
36  <width>32</width>
37  <resetValue>0x00000000</resetValue>
38  <resetMask>0xFFFFFFFF</resetMask>
39  <peripherals>
40    <peripheral>
41      <name>PERI</name>
42      <description>Peripheral interconnect</description>
43      <baseAddress>0x40000000</baseAddress>
44      <addressBlock>
45        <offset>0</offset>
46        <size>65536</size>
47        <usage>registers</usage>
48      </addressBlock>
49      <registers>
50        <register>
51          <name>TIMEOUT_CTL</name>
52          <description>Timeout control</description>
53          <addressOffset>0x200</addressOffset>
54          <size>32</size>
55          <access>read-write</access>
56          <resetValue>0xFFFF</resetValue>
57          <resetMask>0xFFFF</resetMask>
58          <fields>
59            <field>
60              <name>TIMEOUT</name>
61              <description>This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)).
62'0x0000'-'0xfffe': Number of clock cycles.
63'0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated.</description>
64              <bitRange>[15:0]</bitRange>
65              <access>read-write</access>
66            </field>
67          </fields>
68        </register>
69        <register>
70          <name>TR_CMD</name>
71          <description>Trigger command</description>
72          <addressOffset>0x220</addressOffset>
73          <size>32</size>
74          <access>read-write</access>
75          <resetValue>0x0</resetValue>
76          <resetMask>0xE0001FFF</resetMask>
77          <fields>
78            <field>
79              <name>TR_SEL</name>
80              <description>Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present, the trigger activation has no effect.</description>
81              <bitRange>[7:0]</bitRange>
82              <access>read-write</access>
83            </field>
84            <field>
85              <name>GROUP_SEL</name>
86              <description>Specifies the trigger group:
87'0'-'15': trigger multiplexer groups.
88'16'-'31': trigger 1-to-1 groups.</description>
89              <bitRange>[12:8]</bitRange>
90              <access>read-write</access>
91            </field>
92            <field>
93              <name>TR_EDGE</name>
94              <description>Specifies if the activated  trigger is treated as a level sensitive or edge sensitive  trigger.
95'0': level sensitive. The trigger reflects TR_CMD.ACTIVATE.
96'1': edge sensitive trigger. The trigger is activated for two clk_peri cycles.</description>
97              <bitRange>[29:29]</bitRange>
98              <access>read-write</access>
99            </field>
100            <field>
101              <name>OUT_SEL</name>
102              <description>Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL  field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only.
103'0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer.
104'1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer.
105
106Note: this field is not used for trigger 1-to-1 groups.</description>
107              <bitRange>[30:30]</bitRange>
108              <access>read-write</access>
109            </field>
110            <field>
111              <name>ACTIVATE</name>
112              <description>SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL, TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles.
113
114Note: when ACTIVATE is '1', SW should not modify the other register fields.
115SW MUST NOT set ACTIVATE bit to '1' while updating the other register bits simultaneously. At first the SW MUST update the other register bits as needed, and then set ACTIVATE to '1' with a new register write.</description>
116              <bitRange>[31:31]</bitRange>
117              <access>read-write</access>
118            </field>
119          </fields>
120        </register>
121        <register>
122          <name>DIV_CMD</name>
123          <description>Divider command</description>
124          <addressOffset>0x400</addressOffset>
125          <size>32</size>
126          <access>read-write</access>
127          <resetValue>0x3FF03FF</resetValue>
128          <resetMask>0xC3FF03FF</resetMask>
129          <fields>
130            <field>
131              <name>DIV_SEL</name>
132              <description>(TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed.
133
134If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated.</description>
135              <bitRange>[7:0]</bitRange>
136              <access>read-write</access>
137            </field>
138            <field>
139              <name>TYPE_SEL</name>
140              <description>Specifies the divider type of the divider on which the command is performed:
1410: 8.0 (integer) clock dividers.
1421: 16.0 (integer) clock dividers.
1432: 16.5 (fractional) clock dividers.
1443: 24.5 (fractional) clock dividers.</description>
145              <bitRange>[9:8]</bitRange>
146              <access>read-write</access>
147            </field>
148            <field>
149              <name>PA_DIV_SEL</name>
150              <description>(PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times.
151
152If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference.</description>
153              <bitRange>[23:16]</bitRange>
154              <access>read-write</access>
155            </field>
156            <field>
157              <name>PA_TYPE_SEL</name>
158              <description>Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:
1590: 8.0 (integer) clock dividers.
1601: 16.0 (integer) clock dividers.
1612: 16.5 (fractional) clock dividers.
1623: 24.5 (fractional) clock dividers.</description>
163              <bitRange>[25:24]</bitRange>
164              <access>read-write</access>
165            </field>
166            <field>
167              <name>DISABLE</name>
168              <description>Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'.
169
170The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled.
171
172The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately.</description>
173              <bitRange>[30:30]</bitRange>
174              <access>read-write</access>
175            </field>
176            <field>
177              <name>ENABLE</name>
178              <description>Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps:
1790: Disable the divider using the DIV_CMD.DISABLE field.
1801: Configure the divider's DIV_XXX_CTL register.
1812: Enable the divider using the DIV_CMD_ENABLE field.
182
183The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_peri' (typical usage) or to ANY enabled divider.
184
185The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider.
186
187The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_peri'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_peri' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process.</description>
188              <bitRange>[31:31]</bitRange>
189              <access>read-write</access>
190            </field>
191          </fields>
192        </register>
193        <register>
194          <dim>256</dim>
195          <dimIncrement>4</dimIncrement>
196          <name>CLOCK_CTL[%s]</name>
197          <description>Clock control</description>
198          <addressOffset>0xC00</addressOffset>
199          <size>32</size>
200          <access>read-write</access>
201          <resetValue>0x3FF</resetValue>
202          <resetMask>0x3FF</resetMask>
203          <fields>
204            <field>
205              <name>DIV_SEL</name>
206              <description>Specifies one of the dividers of the divider type specified by TYPE_SEL.
207
208If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated.
209
210When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.</description>
211              <bitRange>[7:0]</bitRange>
212              <access>read-write</access>
213            </field>
214            <field>
215              <name>TYPE_SEL</name>
216              <description>Specifies divider type:
2170: 8.0 (integer) clock dividers.
2181: 16.0 (integer) clock dividers.
2192: 16.5 (fractional) clock dividers.
2203: 24.5 (fractional) clock dividers.</description>
221              <bitRange>[9:8]</bitRange>
222              <access>read-write</access>
223            </field>
224          </fields>
225        </register>
226        <register>
227          <dim>256</dim>
228          <dimIncrement>4</dimIncrement>
229          <name>DIV_8_CTL[%s]</name>
230          <description>Divider control (for 8.0 divider)</description>
231          <addressOffset>0x1000</addressOffset>
232          <size>32</size>
233          <access>read-write</access>
234          <resetValue>0x0</resetValue>
235          <resetMask>0xFF01</resetMask>
236          <fields>
237            <field>
238              <name>EN</name>
239              <description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
240
241Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
242              <bitRange>[0:0]</bitRange>
243              <access>read-only</access>
244            </field>
245            <field>
246              <name>INT8_DIV</name>
247              <description>Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division.
248
249For the generation of a divided clock, the integer division range is restricted to [2, 256].
250
251For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50  percent duty cycle analog divided clock has no restrictions.
252
253Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
254              <bitRange>[15:8]</bitRange>
255              <access>read-write</access>
256            </field>
257          </fields>
258        </register>
259        <register>
260          <dim>256</dim>
261          <dimIncrement>4</dimIncrement>
262          <name>DIV_16_CTL[%s]</name>
263          <description>Divider control (for 16.0 divider)</description>
264          <addressOffset>0x1400</addressOffset>
265          <size>32</size>
266          <access>read-write</access>
267          <resetValue>0x0</resetValue>
268          <resetMask>0xFFFF01</resetMask>
269          <fields>
270            <field>
271              <name>EN</name>
272              <description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
273
274Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
275              <bitRange>[0:0]</bitRange>
276              <access>read-only</access>
277            </field>
278            <field>
279              <name>INT16_DIV</name>
280              <description>Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division.
281
282For the generation of a divided clock, the integer division range is restricted to [2, 65,536].
283
284For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50  percent duty cycle analog divided clock has no restrictions.
285
286Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
287              <bitRange>[23:8]</bitRange>
288              <access>read-write</access>
289            </field>
290          </fields>
291        </register>
292        <register>
293          <dim>256</dim>
294          <dimIncrement>4</dimIncrement>
295          <name>DIV_16_5_CTL[%s]</name>
296          <description>Divider control (for 16.5 divider)</description>
297          <addressOffset>0x1800</addressOffset>
298          <size>32</size>
299          <access>read-write</access>
300          <resetValue>0x0</resetValue>
301          <resetMask>0xFFFFF9</resetMask>
302          <fields>
303            <field>
304              <name>EN</name>
305              <description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
306
307Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
308              <bitRange>[0:0]</bitRange>
309              <access>read-only</access>
310            </field>
311            <field>
312              <name>FRAC5_DIV</name>
313              <description>Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods.
314
315Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
316              <bitRange>[7:3]</bitRange>
317              <access>read-write</access>
318            </field>
319            <field>
320              <name>INT16_DIV</name>
321              <description>Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments.
322
323For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32].
324
325For the generation of a 50/50 percent duty cycle divided clock, the  division range is restricted to [2, 65,536].
326
327Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
328              <bitRange>[23:8]</bitRange>
329              <access>read-write</access>
330            </field>
331          </fields>
332        </register>
333        <register>
334          <dim>255</dim>
335          <dimIncrement>4</dimIncrement>
336          <name>DIV_24_5_CTL[%s]</name>
337          <description>Divider control (for 24.5 divider)</description>
338          <addressOffset>0x1C00</addressOffset>
339          <size>32</size>
340          <access>read-write</access>
341          <resetValue>0x0</resetValue>
342          <resetMask>0xFFFFFFF9</resetMask>
343          <fields>
344            <field>
345              <name>EN</name>
346              <description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
347
348Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
349              <bitRange>[0:0]</bitRange>
350              <access>read-only</access>
351            </field>
352            <field>
353              <name>FRAC5_DIV</name>
354              <description>Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods.
355
356Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
357              <bitRange>[7:3]</bitRange>
358              <access>read-write</access>
359            </field>
360            <field>
361              <name>INT24_DIV</name>
362              <description>Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments.
363
364For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32].
365
366For the generation of a 50/50 percent duty cycle divided clock, the  division range is restricted to [2, 16,777,216].
367
368Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
369              <bitRange>[31:8]</bitRange>
370              <access>read-write</access>
371            </field>
372          </fields>
373        </register>
374        <register>
375          <name>ECC_CTL</name>
376          <description>ECC control</description>
377          <addressOffset>0x2000</addressOffset>
378          <size>32</size>
379          <access>read-write</access>
380          <resetValue>0x10000</resetValue>
381          <resetMask>0xFF0507FF</resetMask>
382          <fields>
383            <field>
384              <name>WORD_ADDR</name>
385              <description>Specifies the word address where the parity is injected.
386- On a 32-bit write access to this SRAM address and when ECC_INJ_EN bit is '1', the parity (PARITY) is injected.</description>
387              <bitRange>[10:0]</bitRange>
388              <access>read-write</access>
389            </field>
390            <field>
391              <name>ECC_EN</name>
392              <description>Enable ECC checking:
393'0': Disabled.
394'1': Enabled.</description>
395              <bitRange>[16:16]</bitRange>
396              <access>read-write</access>
397            </field>
398            <field>
399              <name>ECC_INJ_EN</name>
400              <description>Enable error injection for PERI protection structure SRAM.
401When '1', the parity (PARITY) is used when a write is done to the WORD_ADDR word address of the SRAM.</description>
402              <bitRange>[18:18]</bitRange>
403              <access>read-write</access>
404            </field>
405            <field>
406              <name>PARITY</name>
407              <description>ECC parity to use for ECC error injection at address WORD_ADDR.</description>
408              <bitRange>[31:24]</bitRange>
409              <access>read-write</access>
410            </field>
411          </fields>
412        </register>
413        <cluster>
414          <dim>10</dim>
415          <dimIncrement>32</dimIncrement>
416          <name>GR[%s]</name>
417          <description>Peripheral group structure</description>
418          <addressOffset>0x00004000</addressOffset>
419          <register>
420            <name>CLOCK_CTL</name>
421            <description>Clock control</description>
422            <addressOffset>0x0</addressOffset>
423            <size>32</size>
424            <access>read-write</access>
425            <resetValue>0x0</resetValue>
426            <resetMask>0xFF00</resetMask>
427            <fields>
428              <field>
429                <name>INT8_DIV</name>
430                <description>Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256].
431
432Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
433                <bitRange>[15:8]</bitRange>
434                <access>read-write</access>
435              </field>
436            </fields>
437          </register>
438          <register>
439            <name>SL_CTL</name>
440            <description>Slave control</description>
441            <addressOffset>0x10</addressOffset>
442            <size>32</size>
443            <access>read-write</access>
444            <resetValue>0xFFFF</resetValue>
445            <resetMask>0xFFFFFFFF</resetMask>
446            <fields>
447              <field>
448                <name>ENABLED_0</name>
449                <description>Peripheral group, slave 0 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated.
450
451Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.</description>
452                <bitRange>[0:0]</bitRange>
453                <access>read-write</access>
454              </field>
455              <field>
456                <name>ENABLED_1</name>
457                <description>Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated.
458
459Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.</description>
460                <bitRange>[1:1]</bitRange>
461                <access>read-write</access>
462              </field>
463              <field>
464                <name>ENABLED_2</name>
465                <description>N/A</description>
466                <bitRange>[2:2]</bitRange>
467                <access>read-write</access>
468              </field>
469              <field>
470                <name>ENABLED_3</name>
471                <description>N/A</description>
472                <bitRange>[3:3]</bitRange>
473                <access>read-write</access>
474              </field>
475              <field>
476                <name>ENABLED_4</name>
477                <description>N/A</description>
478                <bitRange>[4:4]</bitRange>
479                <access>read-write</access>
480              </field>
481              <field>
482                <name>ENABLED_5</name>
483                <description>N/A</description>
484                <bitRange>[5:5]</bitRange>
485                <access>read-write</access>
486              </field>
487              <field>
488                <name>ENABLED_6</name>
489                <description>N/A</description>
490                <bitRange>[6:6]</bitRange>
491                <access>read-write</access>
492              </field>
493              <field>
494                <name>ENABLED_7</name>
495                <description>N/A</description>
496                <bitRange>[7:7]</bitRange>
497                <access>read-write</access>
498              </field>
499              <field>
500                <name>ENABLED_8</name>
501                <description>N/A</description>
502                <bitRange>[8:8]</bitRange>
503                <access>read-write</access>
504              </field>
505              <field>
506                <name>ENABLED_9</name>
507                <description>N/A</description>
508                <bitRange>[9:9]</bitRange>
509                <access>read-write</access>
510              </field>
511              <field>
512                <name>ENABLED_10</name>
513                <description>N/A</description>
514                <bitRange>[10:10]</bitRange>
515                <access>read-write</access>
516              </field>
517              <field>
518                <name>ENABLED_11</name>
519                <description>N/A</description>
520                <bitRange>[11:11]</bitRange>
521                <access>read-write</access>
522              </field>
523              <field>
524                <name>ENABLED_12</name>
525                <description>N/A</description>
526                <bitRange>[12:12]</bitRange>
527                <access>read-write</access>
528              </field>
529              <field>
530                <name>ENABLED_13</name>
531                <description>N/A</description>
532                <bitRange>[13:13]</bitRange>
533                <access>read-write</access>
534              </field>
535              <field>
536                <name>ENABLED_14</name>
537                <description>N/A</description>
538                <bitRange>[14:14]</bitRange>
539                <access>read-write</access>
540              </field>
541              <field>
542                <name>ENABLED_15</name>
543                <description>N/A</description>
544                <bitRange>[15:15]</bitRange>
545                <access>read-write</access>
546              </field>
547              <field>
548                <name>DISABLED_0</name>
549                <description>Peripheral group, slave 0 permanent disable. Setting this bit to 1 has the same effect as setting ENABLED_0 to 0.  However, once set to 1, this bit cannot be changed back to 0 anymore.</description>
550                <bitRange>[16:16]</bitRange>
551                <access>read-write</access>
552              </field>
553              <field>
554                <name>DISABLED_1</name>
555                <description>N/A</description>
556                <bitRange>[17:17]</bitRange>
557                <access>read-write</access>
558              </field>
559              <field>
560                <name>DISABLED_2</name>
561                <description>N/A</description>
562                <bitRange>[18:18]</bitRange>
563                <access>read-write</access>
564              </field>
565              <field>
566                <name>DISABLED_3</name>
567                <description>N/A</description>
568                <bitRange>[19:19]</bitRange>
569                <access>read-write</access>
570              </field>
571              <field>
572                <name>DISABLED_4</name>
573                <description>N/A</description>
574                <bitRange>[20:20]</bitRange>
575                <access>read-write</access>
576              </field>
577              <field>
578                <name>DISABLED_5</name>
579                <description>N/A</description>
580                <bitRange>[21:21]</bitRange>
581                <access>read-write</access>
582              </field>
583              <field>
584                <name>DISABLED_6</name>
585                <description>N/A</description>
586                <bitRange>[22:22]</bitRange>
587                <access>read-write</access>
588              </field>
589              <field>
590                <name>DISABLED_7</name>
591                <description>N/A</description>
592                <bitRange>[23:23]</bitRange>
593                <access>read-write</access>
594              </field>
595              <field>
596                <name>DISABLED_8</name>
597                <description>N/A</description>
598                <bitRange>[24:24]</bitRange>
599                <access>read-write</access>
600              </field>
601              <field>
602                <name>DISABLED_9</name>
603                <description>N/A</description>
604                <bitRange>[25:25]</bitRange>
605                <access>read-write</access>
606              </field>
607              <field>
608                <name>DISABLED_10</name>
609                <description>N/A</description>
610                <bitRange>[26:26]</bitRange>
611                <access>read-write</access>
612              </field>
613              <field>
614                <name>DISABLED_11</name>
615                <description>N/A</description>
616                <bitRange>[27:27]</bitRange>
617                <access>read-write</access>
618              </field>
619              <field>
620                <name>DISABLED_12</name>
621                <description>N/A</description>
622                <bitRange>[28:28]</bitRange>
623                <access>read-write</access>
624              </field>
625              <field>
626                <name>DISABLED_13</name>
627                <description>N/A</description>
628                <bitRange>[29:29]</bitRange>
629                <access>read-write</access>
630              </field>
631              <field>
632                <name>DISABLED_14</name>
633                <description>N/A</description>
634                <bitRange>[30:30]</bitRange>
635                <access>read-write</access>
636              </field>
637              <field>
638                <name>DISABLED_15</name>
639                <description>N/A</description>
640                <bitRange>[31:31]</bitRange>
641                <access>read-write</access>
642              </field>
643            </fields>
644          </register>
645        </cluster>
646        <cluster>
647          <dim>11</dim>
648          <dimIncrement>1024</dimIncrement>
649          <name>TR_GR[%s]</name>
650          <description>Trigger group</description>
651          <addressOffset>0x00008000</addressOffset>
652          <register>
653            <dim>256</dim>
654            <dimIncrement>4</dimIncrement>
655            <name>TR_CTL[%s]</name>
656            <description>Trigger control register</description>
657            <addressOffset>0x0</addressOffset>
658            <size>32</size>
659            <access>read-write</access>
660            <resetValue>0x0</resetValue>
661            <resetMask>0x13FF</resetMask>
662            <fields>
663              <field>
664                <name>TR_SEL</name>
665                <description>Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.</description>
666                <bitRange>[7:0]</bitRange>
667                <access>read-write</access>
668              </field>
669              <field>
670                <name>TR_INV</name>
671                <description>Specifies if the output trigger is inverted.</description>
672                <bitRange>[8:8]</bitRange>
673                <access>read-write</access>
674              </field>
675              <field>
676                <name>TR_EDGE</name>
677                <description>Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive  trigger.
678'0': level sensitive.
679'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.</description>
680                <bitRange>[9:9]</bitRange>
681                <access>read-write</access>
682              </field>
683              <field>
684                <name>DBG_FREEZE_EN</name>
685                <description>Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation.</description>
686                <bitRange>[12:12]</bitRange>
687                <access>read-write</access>
688              </field>
689            </fields>
690          </register>
691        </cluster>
692        <cluster>
693          <dim>9</dim>
694          <dimIncrement>1024</dimIncrement>
695          <name>TR_1TO1_GR[%s]</name>
696          <description>Trigger 1-to-1 group</description>
697          <addressOffset>0x0000C000</addressOffset>
698          <register>
699            <dim>256</dim>
700            <dimIncrement>4</dimIncrement>
701            <name>TR_CTL[%s]</name>
702            <description>Trigger control register</description>
703            <addressOffset>0x0</addressOffset>
704            <size>32</size>
705            <access>read-write</access>
706            <resetValue>0x0</resetValue>
707            <resetMask>0x1301</resetMask>
708            <fields>
709              <field>
710                <name>TR_SEL</name>
711                <description>Specifies input trigger:
712'0'': constant signal level '0'.
713'1': input trigger.</description>
714                <bitRange>[0:0]</bitRange>
715                <access>read-write</access>
716              </field>
717              <field>
718                <name>TR_INV</name>
719                <description>Specifies if the output trigger is inverted.</description>
720                <bitRange>[8:8]</bitRange>
721                <access>read-write</access>
722              </field>
723              <field>
724                <name>TR_EDGE</name>
725                <description>Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive  trigger.
726'0': level sensitive.
727'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.</description>
728                <bitRange>[9:9]</bitRange>
729                <access>read-write</access>
730              </field>
731              <field>
732                <name>DBG_FREEZE_EN</name>
733                <description>Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation.</description>
734                <bitRange>[12:12]</bitRange>
735                <access>read-write</access>
736              </field>
737            </fields>
738          </register>
739        </cluster>
740      </registers>
741    </peripheral>
742    <peripheral>
743      <name>PERI_MS</name>
744      <description>Peripheral interconnect, master interface</description>
745      <baseAddress>0x40010000</baseAddress>
746      <addressBlock>
747        <offset>0</offset>
748        <size>65536</size>
749        <usage>registers</usage>
750      </addressBlock>
751      <registers>
752        <cluster>
753          <dim>16</dim>
754          <dimIncrement>64</dimIncrement>
755          <name>PPU_PR[%s]</name>
756          <description>Programmable protection structure pair</description>
757          <addressOffset>0x00000000</addressOffset>
758          <register>
759            <name>SL_ADDR</name>
760            <description>Slave region, base address</description>
761            <addressOffset>0x0</addressOffset>
762            <size>32</size>
763            <access>read-write</access>
764            <resetValue>0x0</resetValue>
765            <resetMask>0x0</resetMask>
766            <fields>
767              <field>
768                <name>ADDR30</name>
769                <description>This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's.</description>
770                <bitRange>[31:2]</bitRange>
771                <access>read-write</access>
772              </field>
773            </fields>
774          </register>
775          <register>
776            <name>SL_SIZE</name>
777            <description>Slave region, size</description>
778            <addressOffset>0x4</addressOffset>
779            <size>32</size>
780            <access>read-write</access>
781            <resetValue>0x0</resetValue>
782            <resetMask>0x80000000</resetMask>
783            <fields>
784              <field>
785                <name>REGION_SIZE</name>
786                <description>This field specifies the size of the slave region:
787'0': Undefined.
788'1': 4 B region (this is the smallest region size).
789'2': 8 B region
790'3': 16 B region
791'4': 32 B region
792'5': 64 B region
793'6': 128 B region
794'7': 256 B region
795'8': 512 B region
796'9': 1 KB region
797'10': 2 KB region
798'11': 4 KB region
799'12': 8 KB region
800'13': 16 KB region
801'14': 32 KB region
802'15': 64 KB region
803'16': 128 KB region
804'17': 256 KB region
805'18': 512 KB region
806'19': 1 MB region
807'20': 2 MB region
808'21': 4 MB region
809'22': 8 MB region
810'23': 16 MB region
811'24': 32 MB region
812'25': 64 MB region
813'26': 128 MB region
814'27': 256 MB region
815'28': 512 MB region
816'29': 1 GB region
817'30': 2 GB region
818'31': 4 GB region</description>
819                <bitRange>[28:24]</bitRange>
820                <access>read-write</access>
821              </field>
822              <field>
823                <name>VALID</name>
824                <description>Slave region enable:
825'0': Disabled. A disabled region will never result in a match on the transfer address.
826'1': Enabled.</description>
827                <bitRange>[31:31]</bitRange>
828                <access>read-write</access>
829              </field>
830            </fields>
831          </register>
832          <register>
833            <name>SL_ATT0</name>
834            <description>Slave attributes 0</description>
835            <addressOffset>0x10</addressOffset>
836            <size>32</size>
837            <access>read-write</access>
838            <resetValue>0x1F1F1F1F</resetValue>
839            <resetMask>0x1F1F1F1F</resetMask>
840            <fields>
841              <field>
842                <name>PC0_UR</name>
843                <description>Protection context 0, user read enable:
844'0': Disabled (user, read accesses are NOT allowed).
845'1': Enabled (user, read accesses are allowed).</description>
846                <bitRange>[0:0]</bitRange>
847                <access>read-only</access>
848              </field>
849              <field>
850                <name>PC0_UW</name>
851                <description>Protection context 0, user write enable:
852'0': Disabled (user, write accesses are NOT allowed).
853'1': Enabled (user, write accesses are allowed).</description>
854                <bitRange>[1:1]</bitRange>
855                <access>read-only</access>
856              </field>
857              <field>
858                <name>PC0_PR</name>
859                <description>Protection context 0, privileged read enable:
860'0': Disabled (privileged, read accesses are NOT allowed).
861'1': Enabled (privileged, read accesses are allowed).</description>
862                <bitRange>[2:2]</bitRange>
863                <access>read-only</access>
864              </field>
865              <field>
866                <name>PC0_PW</name>
867                <description>Protection context 0, privileged write enable:
868'0': Disabled (privileged, write accesses are NOT allowed).
869'1': Enabled (privileged, write accesses are allowed).</description>
870                <bitRange>[3:3]</bitRange>
871                <access>read-only</access>
872              </field>
873              <field>
874                <name>PC0_NS</name>
875                <description>Protection context 0, non-secure:
876'0': Secure (secure accesses allowed, non-secure access NOT allowed).
877'1': Non-secure (both secure and non-secure accesses allowed).</description>
878                <bitRange>[4:4]</bitRange>
879                <access>read-only</access>
880              </field>
881              <field>
882                <name>PC1_UR</name>
883                <description>Protection context 1, user read enable.</description>
884                <bitRange>[8:8]</bitRange>
885                <access>read-write</access>
886              </field>
887              <field>
888                <name>PC1_UW</name>
889                <description>Protection context 1, user write enable.</description>
890                <bitRange>[9:9]</bitRange>
891                <access>read-write</access>
892              </field>
893              <field>
894                <name>PC1_PR</name>
895                <description>Protection context 1, privileged read enable.</description>
896                <bitRange>[10:10]</bitRange>
897                <access>read-write</access>
898              </field>
899              <field>
900                <name>PC1_PW</name>
901                <description>Protection context 1, privileged write enable.</description>
902                <bitRange>[11:11]</bitRange>
903                <access>read-write</access>
904              </field>
905              <field>
906                <name>PC1_NS</name>
907                <description>Protection context 1, non-secure.</description>
908                <bitRange>[12:12]</bitRange>
909                <access>read-write</access>
910              </field>
911              <field>
912                <name>PC2_UR</name>
913                <description>Protection context 2, user read enable.</description>
914                <bitRange>[16:16]</bitRange>
915                <access>read-write</access>
916              </field>
917              <field>
918                <name>PC2_UW</name>
919                <description>Protection context 2, user write enable.</description>
920                <bitRange>[17:17]</bitRange>
921                <access>read-write</access>
922              </field>
923              <field>
924                <name>PC2_PR</name>
925                <description>Protection context 2, privileged read enable.</description>
926                <bitRange>[18:18]</bitRange>
927                <access>read-write</access>
928              </field>
929              <field>
930                <name>PC2_PW</name>
931                <description>Protection context 2, privileged write enable.</description>
932                <bitRange>[19:19]</bitRange>
933                <access>read-write</access>
934              </field>
935              <field>
936                <name>PC2_NS</name>
937                <description>Protection context 2, non-secure.</description>
938                <bitRange>[20:20]</bitRange>
939                <access>read-write</access>
940              </field>
941              <field>
942                <name>PC3_UR</name>
943                <description>Protection context 3, user read enable.</description>
944                <bitRange>[24:24]</bitRange>
945                <access>read-write</access>
946              </field>
947              <field>
948                <name>PC3_UW</name>
949                <description>Protection context 3, user write enable.</description>
950                <bitRange>[25:25]</bitRange>
951                <access>read-write</access>
952              </field>
953              <field>
954                <name>PC3_PR</name>
955                <description>Protection context 3, privileged read enable.</description>
956                <bitRange>[26:26]</bitRange>
957                <access>read-write</access>
958              </field>
959              <field>
960                <name>PC3_PW</name>
961                <description>Protection context 3, privileged write enable.</description>
962                <bitRange>[27:27]</bitRange>
963                <access>read-write</access>
964              </field>
965              <field>
966                <name>PC3_NS</name>
967                <description>Protection context 3, non-secure.</description>
968                <bitRange>[28:28]</bitRange>
969                <access>read-write</access>
970              </field>
971            </fields>
972          </register>
973          <register>
974            <name>SL_ATT1</name>
975            <description>Slave attributes 1</description>
976            <addressOffset>0x14</addressOffset>
977            <size>32</size>
978            <access>read-write</access>
979            <resetValue>0x1F1F1F1F</resetValue>
980            <resetMask>0x1F1F1F1F</resetMask>
981            <fields>
982              <field>
983                <name>PC4_UR</name>
984                <description>Protection context 4, user read enable.</description>
985                <bitRange>[0:0]</bitRange>
986                <access>read-write</access>
987              </field>
988              <field>
989                <name>PC4_UW</name>
990                <description>Protection context 4, user write enable.</description>
991                <bitRange>[1:1]</bitRange>
992                <access>read-write</access>
993              </field>
994              <field>
995                <name>PC4_PR</name>
996                <description>Protection context 4, privileged read enable.</description>
997                <bitRange>[2:2]</bitRange>
998                <access>read-write</access>
999              </field>
1000              <field>
1001                <name>PC4_PW</name>
1002                <description>Protection context 4, privileged write enable.</description>
1003                <bitRange>[3:3]</bitRange>
1004                <access>read-write</access>
1005              </field>
1006              <field>
1007                <name>PC4_NS</name>
1008                <description>Protection context 4, non-secure.</description>
1009                <bitRange>[4:4]</bitRange>
1010                <access>read-write</access>
1011              </field>
1012              <field>
1013                <name>PC5_UR</name>
1014                <description>Protection context 5, user read enable.</description>
1015                <bitRange>[8:8]</bitRange>
1016                <access>read-write</access>
1017              </field>
1018              <field>
1019                <name>PC5_UW</name>
1020                <description>Protection context 5, user write enable.</description>
1021                <bitRange>[9:9]</bitRange>
1022                <access>read-write</access>
1023              </field>
1024              <field>
1025                <name>PC5_PR</name>
1026                <description>Protection context 5, privileged read enable.</description>
1027                <bitRange>[10:10]</bitRange>
1028                <access>read-write</access>
1029              </field>
1030              <field>
1031                <name>PC5_PW</name>
1032                <description>Protection context 5, privileged write enable.</description>
1033                <bitRange>[11:11]</bitRange>
1034                <access>read-write</access>
1035              </field>
1036              <field>
1037                <name>PC5_NS</name>
1038                <description>Protection context 5, non-secure.</description>
1039                <bitRange>[12:12]</bitRange>
1040                <access>read-write</access>
1041              </field>
1042              <field>
1043                <name>PC6_UR</name>
1044                <description>Protection context 6, user read enable.</description>
1045                <bitRange>[16:16]</bitRange>
1046                <access>read-write</access>
1047              </field>
1048              <field>
1049                <name>PC6_UW</name>
1050                <description>Protection context 6, user write enable.</description>
1051                <bitRange>[17:17]</bitRange>
1052                <access>read-write</access>
1053              </field>
1054              <field>
1055                <name>PC6_PR</name>
1056                <description>Protection context 6, privileged read enable.</description>
1057                <bitRange>[18:18]</bitRange>
1058                <access>read-write</access>
1059              </field>
1060              <field>
1061                <name>PC6_PW</name>
1062                <description>Protection context 6, privileged write enable.</description>
1063                <bitRange>[19:19]</bitRange>
1064                <access>read-write</access>
1065              </field>
1066              <field>
1067                <name>PC6_NS</name>
1068                <description>Protection context 6, non-secure.</description>
1069                <bitRange>[20:20]</bitRange>
1070                <access>read-write</access>
1071              </field>
1072              <field>
1073                <name>PC7_UR</name>
1074                <description>Protection context 7, user read enable.</description>
1075                <bitRange>[24:24]</bitRange>
1076                <access>read-write</access>
1077              </field>
1078              <field>
1079                <name>PC7_UW</name>
1080                <description>Protection context 7, user write enable.</description>
1081                <bitRange>[25:25]</bitRange>
1082                <access>read-write</access>
1083              </field>
1084              <field>
1085                <name>PC7_PR</name>
1086                <description>Protection context 7, privileged read enable.</description>
1087                <bitRange>[26:26]</bitRange>
1088                <access>read-write</access>
1089              </field>
1090              <field>
1091                <name>PC7_PW</name>
1092                <description>Protection context 7, privileged write enable.</description>
1093                <bitRange>[27:27]</bitRange>
1094                <access>read-write</access>
1095              </field>
1096              <field>
1097                <name>PC7_NS</name>
1098                <description>Protection context 7, non-secure.</description>
1099                <bitRange>[28:28]</bitRange>
1100                <access>read-write</access>
1101              </field>
1102            </fields>
1103          </register>
1104          <register>
1105            <name>SL_ATT2</name>
1106            <description>Slave attributes 2</description>
1107            <addressOffset>0x18</addressOffset>
1108            <size>32</size>
1109            <access>read-write</access>
1110            <resetValue>0x1F1F1F1F</resetValue>
1111            <resetMask>0x1F1F1F1F</resetMask>
1112            <fields>
1113              <field>
1114                <name>PC8_UR</name>
1115                <description>Protection context 8, user read enable.</description>
1116                <bitRange>[0:0]</bitRange>
1117                <access>read-write</access>
1118              </field>
1119              <field>
1120                <name>PC8_UW</name>
1121                <description>Protection context 8, user write enable.</description>
1122                <bitRange>[1:1]</bitRange>
1123                <access>read-write</access>
1124              </field>
1125              <field>
1126                <name>PC8_PR</name>
1127                <description>Protection context 8, privileged read enable.</description>
1128                <bitRange>[2:2]</bitRange>
1129                <access>read-write</access>
1130              </field>
1131              <field>
1132                <name>PC8_PW</name>
1133                <description>Protection context 8, privileged write enable.</description>
1134                <bitRange>[3:3]</bitRange>
1135                <access>read-write</access>
1136              </field>
1137              <field>
1138                <name>PC8_NS</name>
1139                <description>Protection context 8, non-secure.</description>
1140                <bitRange>[4:4]</bitRange>
1141                <access>read-write</access>
1142              </field>
1143              <field>
1144                <name>PC9_UR</name>
1145                <description>Protection context 9, user read enable.</description>
1146                <bitRange>[8:8]</bitRange>
1147                <access>read-write</access>
1148              </field>
1149              <field>
1150                <name>PC9_UW</name>
1151                <description>Protection context 9, user write enable.</description>
1152                <bitRange>[9:9]</bitRange>
1153                <access>read-write</access>
1154              </field>
1155              <field>
1156                <name>PC9_PR</name>
1157                <description>Protection context 9, privileged read enable.</description>
1158                <bitRange>[10:10]</bitRange>
1159                <access>read-write</access>
1160              </field>
1161              <field>
1162                <name>PC9_PW</name>
1163                <description>Protection context 9, privileged write enable.</description>
1164                <bitRange>[11:11]</bitRange>
1165                <access>read-write</access>
1166              </field>
1167              <field>
1168                <name>PC9_NS</name>
1169                <description>Protection context 9, non-secure.</description>
1170                <bitRange>[12:12]</bitRange>
1171                <access>read-write</access>
1172              </field>
1173              <field>
1174                <name>PC10_UR</name>
1175                <description>Protection context 10, user read enable.</description>
1176                <bitRange>[16:16]</bitRange>
1177                <access>read-write</access>
1178              </field>
1179              <field>
1180                <name>PC10_UW</name>
1181                <description>Protection context 10, user write enable.</description>
1182                <bitRange>[17:17]</bitRange>
1183                <access>read-write</access>
1184              </field>
1185              <field>
1186                <name>PC10_PR</name>
1187                <description>Protection context 10, privileged read enable.</description>
1188                <bitRange>[18:18]</bitRange>
1189                <access>read-write</access>
1190              </field>
1191              <field>
1192                <name>PC10_PW</name>
1193                <description>Protection context 10, privileged write enable.</description>
1194                <bitRange>[19:19]</bitRange>
1195                <access>read-write</access>
1196              </field>
1197              <field>
1198                <name>PC10_NS</name>
1199                <description>Protection context 10, non-secure.</description>
1200                <bitRange>[20:20]</bitRange>
1201                <access>read-write</access>
1202              </field>
1203              <field>
1204                <name>PC11_UR</name>
1205                <description>Protection context 11, user read enable.</description>
1206                <bitRange>[24:24]</bitRange>
1207                <access>read-write</access>
1208              </field>
1209              <field>
1210                <name>PC11_UW</name>
1211                <description>Protection context 11, user write enable.</description>
1212                <bitRange>[25:25]</bitRange>
1213                <access>read-write</access>
1214              </field>
1215              <field>
1216                <name>PC11_PR</name>
1217                <description>Protection context 11, privileged read enable.</description>
1218                <bitRange>[26:26]</bitRange>
1219                <access>read-write</access>
1220              </field>
1221              <field>
1222                <name>PC11_PW</name>
1223                <description>Protection context 11, privileged write enable.</description>
1224                <bitRange>[27:27]</bitRange>
1225                <access>read-write</access>
1226              </field>
1227              <field>
1228                <name>PC11_NS</name>
1229                <description>Protection context 11, non-secure.</description>
1230                <bitRange>[28:28]</bitRange>
1231                <access>read-write</access>
1232              </field>
1233            </fields>
1234          </register>
1235          <register>
1236            <name>SL_ATT3</name>
1237            <description>Slave attributes 3</description>
1238            <addressOffset>0x1C</addressOffset>
1239            <size>32</size>
1240            <access>read-write</access>
1241            <resetValue>0x1F1F1F1F</resetValue>
1242            <resetMask>0x1F1F1F1F</resetMask>
1243            <fields>
1244              <field>
1245                <name>PC12_UR</name>
1246                <description>Protection context 12, user read enable.</description>
1247                <bitRange>[0:0]</bitRange>
1248                <access>read-write</access>
1249              </field>
1250              <field>
1251                <name>PC12_UW</name>
1252                <description>Protection context 12, user write enable.</description>
1253                <bitRange>[1:1]</bitRange>
1254                <access>read-write</access>
1255              </field>
1256              <field>
1257                <name>PC12_PR</name>
1258                <description>Protection context 12, privileged read enable.</description>
1259                <bitRange>[2:2]</bitRange>
1260                <access>read-write</access>
1261              </field>
1262              <field>
1263                <name>PC12_PW</name>
1264                <description>Protection context 12, privileged write enable.</description>
1265                <bitRange>[3:3]</bitRange>
1266                <access>read-write</access>
1267              </field>
1268              <field>
1269                <name>PC12_NS</name>
1270                <description>Protection context 12, non-secure.</description>
1271                <bitRange>[4:4]</bitRange>
1272                <access>read-write</access>
1273              </field>
1274              <field>
1275                <name>PC13_UR</name>
1276                <description>Protection context 13, user read enable.</description>
1277                <bitRange>[8:8]</bitRange>
1278                <access>read-write</access>
1279              </field>
1280              <field>
1281                <name>PC13_UW</name>
1282                <description>Protection context 13, user write enable.</description>
1283                <bitRange>[9:9]</bitRange>
1284                <access>read-write</access>
1285              </field>
1286              <field>
1287                <name>PC13_PR</name>
1288                <description>Protection context 13, privileged read enable.</description>
1289                <bitRange>[10:10]</bitRange>
1290                <access>read-write</access>
1291              </field>
1292              <field>
1293                <name>PC13_PW</name>
1294                <description>Protection context 13, privileged write enable.</description>
1295                <bitRange>[11:11]</bitRange>
1296                <access>read-write</access>
1297              </field>
1298              <field>
1299                <name>PC13_NS</name>
1300                <description>Protection context 13, non-secure.</description>
1301                <bitRange>[12:12]</bitRange>
1302                <access>read-write</access>
1303              </field>
1304              <field>
1305                <name>PC14_UR</name>
1306                <description>Protection context 14, user read enable.</description>
1307                <bitRange>[16:16]</bitRange>
1308                <access>read-write</access>
1309              </field>
1310              <field>
1311                <name>PC14_UW</name>
1312                <description>Protection context 14, user write enable.</description>
1313                <bitRange>[17:17]</bitRange>
1314                <access>read-write</access>
1315              </field>
1316              <field>
1317                <name>PC14_PR</name>
1318                <description>Protection context 14, privileged read enable.</description>
1319                <bitRange>[18:18]</bitRange>
1320                <access>read-write</access>
1321              </field>
1322              <field>
1323                <name>PC14_PW</name>
1324                <description>Protection context 14, privileged write enable.</description>
1325                <bitRange>[19:19]</bitRange>
1326                <access>read-write</access>
1327              </field>
1328              <field>
1329                <name>PC14_NS</name>
1330                <description>Protection context 14, non-secure.</description>
1331                <bitRange>[20:20]</bitRange>
1332                <access>read-write</access>
1333              </field>
1334              <field>
1335                <name>PC15_UR</name>
1336                <description>Protection context 15, user read enable.</description>
1337                <bitRange>[24:24]</bitRange>
1338                <access>read-write</access>
1339              </field>
1340              <field>
1341                <name>PC15_UW</name>
1342                <description>Protection context 15, user write enable.</description>
1343                <bitRange>[25:25]</bitRange>
1344                <access>read-write</access>
1345              </field>
1346              <field>
1347                <name>PC15_PR</name>
1348                <description>Protection context 15, privileged read enable.</description>
1349                <bitRange>[26:26]</bitRange>
1350                <access>read-write</access>
1351              </field>
1352              <field>
1353                <name>PC15_PW</name>
1354                <description>Protection context 15, privileged write enable.</description>
1355                <bitRange>[27:27]</bitRange>
1356                <access>read-write</access>
1357              </field>
1358              <field>
1359                <name>PC15_NS</name>
1360                <description>Protection context 15, non-secure.</description>
1361                <bitRange>[28:28]</bitRange>
1362                <access>read-write</access>
1363              </field>
1364            </fields>
1365          </register>
1366          <register>
1367            <name>MS_ADDR</name>
1368            <description>Master region, base address</description>
1369            <addressOffset>0x20</addressOffset>
1370            <size>32</size>
1371            <access>read-only</access>
1372            <resetValue>0x0</resetValue>
1373            <resetMask>0xFFFFFFC0</resetMask>
1374            <fields>
1375              <field>
1376                <name>ADDR26</name>
1377                <description>This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register.</description>
1378                <bitRange>[31:6]</bitRange>
1379                <access>read-only</access>
1380              </field>
1381            </fields>
1382          </register>
1383          <register>
1384            <name>MS_SIZE</name>
1385            <description>Master region, size</description>
1386            <addressOffset>0x24</addressOffset>
1387            <size>32</size>
1388            <access>read-only</access>
1389            <resetValue>0x85000000</resetValue>
1390            <resetMask>0x9F000000</resetMask>
1391            <fields>
1392              <field>
1393                <name>REGION_SIZE</name>
1394                <description>This field specifies the size of the master region:
1395'5': 64 B region
1396
1397The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3.</description>
1398                <bitRange>[28:24]</bitRange>
1399                <access>read-only</access>
1400              </field>
1401              <field>
1402                <name>VALID</name>
1403                <description>Master region enable:
1404'1': Enabled.</description>
1405                <bitRange>[31:31]</bitRange>
1406                <access>read-only</access>
1407              </field>
1408            </fields>
1409          </register>
1410          <register>
1411            <name>MS_ATT0</name>
1412            <description>Master attributes 0</description>
1413            <addressOffset>0x30</addressOffset>
1414            <size>32</size>
1415            <access>read-write</access>
1416            <resetValue>0x1F1F1F1F</resetValue>
1417            <resetMask>0x1F1F1F1F</resetMask>
1418            <fields>
1419              <field>
1420                <name>PC0_UR</name>
1421                <description>Protection context 0, user read enable:
1422'0': Disabled (user, read accesses are NOT allowed).
1423'1': Enabled (user, read accesses are allowed).</description>
1424                <bitRange>[0:0]</bitRange>
1425                <access>read-only</access>
1426              </field>
1427              <field>
1428                <name>PC0_UW</name>
1429                <description>Protection context 0, user write enable:
1430'0': Disabled (user, write accesses are NOT allowed).
1431'1': Enabled (user, write accesses are allowed).</description>
1432                <bitRange>[1:1]</bitRange>
1433                <access>read-only</access>
1434              </field>
1435              <field>
1436                <name>PC0_PR</name>
1437                <description>Protection context 0, privileged read enable:
1438'0': Disabled (privileged, read accesses are NOT allowed).
1439'1': Enabled (privileged, read accesses are allowed).</description>
1440                <bitRange>[2:2]</bitRange>
1441                <access>read-only</access>
1442              </field>
1443              <field>
1444                <name>PC0_PW</name>
1445                <description>Protection context 0, privileged write enable:
1446'0': Disabled (privileged, write accesses are NOT allowed).
1447'1': Enabled (privileged, write accesses are allowed).</description>
1448                <bitRange>[3:3]</bitRange>
1449                <access>read-only</access>
1450              </field>
1451              <field>
1452                <name>PC0_NS</name>
1453                <description>Protection context 0, non-secure:
1454'0': Secure (secure accesses allowed, non-secure access NOT allowed).
1455'1': Non-secure (both secure and non-secure accesses allowed).</description>
1456                <bitRange>[4:4]</bitRange>
1457                <access>read-only</access>
1458              </field>
1459              <field>
1460                <name>PC1_UR</name>
1461                <description>Protection context 1, user read enable.</description>
1462                <bitRange>[8:8]</bitRange>
1463                <access>read-only</access>
1464              </field>
1465              <field>
1466                <name>PC1_UW</name>
1467                <description>Protection context 1, user write enable.</description>
1468                <bitRange>[9:9]</bitRange>
1469                <access>read-write</access>
1470              </field>
1471              <field>
1472                <name>PC1_PR</name>
1473                <description>Protection context 1, privileged read enable.</description>
1474                <bitRange>[10:10]</bitRange>
1475                <access>read-only</access>
1476              </field>
1477              <field>
1478                <name>PC1_PW</name>
1479                <description>Protection context 1, privileged write enable.</description>
1480                <bitRange>[11:11]</bitRange>
1481                <access>read-write</access>
1482              </field>
1483              <field>
1484                <name>PC1_NS</name>
1485                <description>Protection context 1, non-secure.</description>
1486                <bitRange>[12:12]</bitRange>
1487                <access>read-write</access>
1488              </field>
1489              <field>
1490                <name>PC2_UR</name>
1491                <description>Protection context 2, user read enable.</description>
1492                <bitRange>[16:16]</bitRange>
1493                <access>read-only</access>
1494              </field>
1495              <field>
1496                <name>PC2_UW</name>
1497                <description>Protection context 2, user write enable.</description>
1498                <bitRange>[17:17]</bitRange>
1499                <access>read-write</access>
1500              </field>
1501              <field>
1502                <name>PC2_PR</name>
1503                <description>Protection context 2, privileged read enable.</description>
1504                <bitRange>[18:18]</bitRange>
1505                <access>read-only</access>
1506              </field>
1507              <field>
1508                <name>PC2_PW</name>
1509                <description>Protection context 2, privileged write enable.</description>
1510                <bitRange>[19:19]</bitRange>
1511                <access>read-write</access>
1512              </field>
1513              <field>
1514                <name>PC2_NS</name>
1515                <description>Protection context 2, non-secure.</description>
1516                <bitRange>[20:20]</bitRange>
1517                <access>read-write</access>
1518              </field>
1519              <field>
1520                <name>PC3_UR</name>
1521                <description>Protection context 3, user read enable.</description>
1522                <bitRange>[24:24]</bitRange>
1523                <access>read-only</access>
1524              </field>
1525              <field>
1526                <name>PC3_UW</name>
1527                <description>Protection context 3, user write enable.</description>
1528                <bitRange>[25:25]</bitRange>
1529                <access>read-write</access>
1530              </field>
1531              <field>
1532                <name>PC3_PR</name>
1533                <description>Protection context 3, privileged read enable.</description>
1534                <bitRange>[26:26]</bitRange>
1535                <access>read-only</access>
1536              </field>
1537              <field>
1538                <name>PC3_PW</name>
1539                <description>Protection context 3, privileged write enable.</description>
1540                <bitRange>[27:27]</bitRange>
1541                <access>read-write</access>
1542              </field>
1543              <field>
1544                <name>PC3_NS</name>
1545                <description>Protection context 3, non-secure.</description>
1546                <bitRange>[28:28]</bitRange>
1547                <access>read-write</access>
1548              </field>
1549            </fields>
1550          </register>
1551          <register>
1552            <name>MS_ATT1</name>
1553            <description>Master attributes 1</description>
1554            <addressOffset>0x34</addressOffset>
1555            <size>32</size>
1556            <access>read-write</access>
1557            <resetValue>0x1F1F1F1F</resetValue>
1558            <resetMask>0x1F1F1F1F</resetMask>
1559            <fields>
1560              <field>
1561                <name>PC4_UR</name>
1562                <description>Protection context 4, user read enable.</description>
1563                <bitRange>[0:0]</bitRange>
1564                <access>read-only</access>
1565              </field>
1566              <field>
1567                <name>PC4_UW</name>
1568                <description>Protection context 4, user write enable.</description>
1569                <bitRange>[1:1]</bitRange>
1570                <access>read-write</access>
1571              </field>
1572              <field>
1573                <name>PC4_PR</name>
1574                <description>Protection context 4, privileged read enable.</description>
1575                <bitRange>[2:2]</bitRange>
1576                <access>read-only</access>
1577              </field>
1578              <field>
1579                <name>PC4_PW</name>
1580                <description>Protection context 4, privileged write enable.</description>
1581                <bitRange>[3:3]</bitRange>
1582                <access>read-write</access>
1583              </field>
1584              <field>
1585                <name>PC4_NS</name>
1586                <description>Protection context 4, non-secure.</description>
1587                <bitRange>[4:4]</bitRange>
1588                <access>read-write</access>
1589              </field>
1590              <field>
1591                <name>PC5_UR</name>
1592                <description>Protection context 5, user read enable.</description>
1593                <bitRange>[8:8]</bitRange>
1594                <access>read-only</access>
1595              </field>
1596              <field>
1597                <name>PC5_UW</name>
1598                <description>Protection context 5, user write enable.</description>
1599                <bitRange>[9:9]</bitRange>
1600                <access>read-write</access>
1601              </field>
1602              <field>
1603                <name>PC5_PR</name>
1604                <description>Protection context 5, privileged read enable.</description>
1605                <bitRange>[10:10]</bitRange>
1606                <access>read-only</access>
1607              </field>
1608              <field>
1609                <name>PC5_PW</name>
1610                <description>Protection context 5, privileged write enable.</description>
1611                <bitRange>[11:11]</bitRange>
1612                <access>read-write</access>
1613              </field>
1614              <field>
1615                <name>PC5_NS</name>
1616                <description>Protection context 5, non-secure.</description>
1617                <bitRange>[12:12]</bitRange>
1618                <access>read-write</access>
1619              </field>
1620              <field>
1621                <name>PC6_UR</name>
1622                <description>Protection context 6, user read enable.</description>
1623                <bitRange>[16:16]</bitRange>
1624                <access>read-only</access>
1625              </field>
1626              <field>
1627                <name>PC6_UW</name>
1628                <description>Protection context 6, user write enable.</description>
1629                <bitRange>[17:17]</bitRange>
1630                <access>read-write</access>
1631              </field>
1632              <field>
1633                <name>PC6_PR</name>
1634                <description>Protection context 6, privileged read enable.</description>
1635                <bitRange>[18:18]</bitRange>
1636                <access>read-only</access>
1637              </field>
1638              <field>
1639                <name>PC6_PW</name>
1640                <description>Protection context 6, privileged write enable.</description>
1641                <bitRange>[19:19]</bitRange>
1642                <access>read-write</access>
1643              </field>
1644              <field>
1645                <name>PC6_NS</name>
1646                <description>Protection context 6, non-secure.</description>
1647                <bitRange>[20:20]</bitRange>
1648                <access>read-write</access>
1649              </field>
1650              <field>
1651                <name>PC7_UR</name>
1652                <description>Protection context 7, user read enable.</description>
1653                <bitRange>[24:24]</bitRange>
1654                <access>read-only</access>
1655              </field>
1656              <field>
1657                <name>PC7_UW</name>
1658                <description>Protection context 7, user write enable.</description>
1659                <bitRange>[25:25]</bitRange>
1660                <access>read-write</access>
1661              </field>
1662              <field>
1663                <name>PC7_PR</name>
1664                <description>Protection context 7, privileged read enable.</description>
1665                <bitRange>[26:26]</bitRange>
1666                <access>read-only</access>
1667              </field>
1668              <field>
1669                <name>PC7_PW</name>
1670                <description>Protection context 7, privileged write enable.</description>
1671                <bitRange>[27:27]</bitRange>
1672                <access>read-write</access>
1673              </field>
1674              <field>
1675                <name>PC7_NS</name>
1676                <description>Protection context 7, non-secure.</description>
1677                <bitRange>[28:28]</bitRange>
1678                <access>read-write</access>
1679              </field>
1680            </fields>
1681          </register>
1682          <register>
1683            <name>MS_ATT2</name>
1684            <description>Master attributes 2</description>
1685            <addressOffset>0x38</addressOffset>
1686            <size>32</size>
1687            <access>read-write</access>
1688            <resetValue>0x1F1F1F1F</resetValue>
1689            <resetMask>0x1F1F1F1F</resetMask>
1690            <fields>
1691              <field>
1692                <name>PC8_UR</name>
1693                <description>Protection context 8, user read enable.</description>
1694                <bitRange>[0:0]</bitRange>
1695                <access>read-only</access>
1696              </field>
1697              <field>
1698                <name>PC8_UW</name>
1699                <description>Protection context 8, user write enable.</description>
1700                <bitRange>[1:1]</bitRange>
1701                <access>read-write</access>
1702              </field>
1703              <field>
1704                <name>PC8_PR</name>
1705                <description>Protection context 8, privileged read enable.</description>
1706                <bitRange>[2:2]</bitRange>
1707                <access>read-only</access>
1708              </field>
1709              <field>
1710                <name>PC8_PW</name>
1711                <description>Protection context 8, privileged write enable.</description>
1712                <bitRange>[3:3]</bitRange>
1713                <access>read-write</access>
1714              </field>
1715              <field>
1716                <name>PC8_NS</name>
1717                <description>Protection context 8, non-secure.</description>
1718                <bitRange>[4:4]</bitRange>
1719                <access>read-write</access>
1720              </field>
1721              <field>
1722                <name>PC9_UR</name>
1723                <description>Protection context 9, user read enable.</description>
1724                <bitRange>[8:8]</bitRange>
1725                <access>read-only</access>
1726              </field>
1727              <field>
1728                <name>PC9_UW</name>
1729                <description>Protection context 9, user write enable.</description>
1730                <bitRange>[9:9]</bitRange>
1731                <access>read-write</access>
1732              </field>
1733              <field>
1734                <name>PC9_PR</name>
1735                <description>Protection context 9, privileged read enable.</description>
1736                <bitRange>[10:10]</bitRange>
1737                <access>read-only</access>
1738              </field>
1739              <field>
1740                <name>PC9_PW</name>
1741                <description>Protection context 9, privileged write enable.</description>
1742                <bitRange>[11:11]</bitRange>
1743                <access>read-write</access>
1744              </field>
1745              <field>
1746                <name>PC9_NS</name>
1747                <description>Protection context 9, non-secure.</description>
1748                <bitRange>[12:12]</bitRange>
1749                <access>read-write</access>
1750              </field>
1751              <field>
1752                <name>PC10_UR</name>
1753                <description>Protection context 10, user read enable.</description>
1754                <bitRange>[16:16]</bitRange>
1755                <access>read-only</access>
1756              </field>
1757              <field>
1758                <name>PC10_UW</name>
1759                <description>Protection context 10, user write enable.</description>
1760                <bitRange>[17:17]</bitRange>
1761                <access>read-write</access>
1762              </field>
1763              <field>
1764                <name>PC10_PR</name>
1765                <description>Protection context 10, privileged read enable.</description>
1766                <bitRange>[18:18]</bitRange>
1767                <access>read-only</access>
1768              </field>
1769              <field>
1770                <name>PC10_PW</name>
1771                <description>Protection context 10, privileged write enable.</description>
1772                <bitRange>[19:19]</bitRange>
1773                <access>read-write</access>
1774              </field>
1775              <field>
1776                <name>PC10_NS</name>
1777                <description>Protection context 10, non-secure.</description>
1778                <bitRange>[20:20]</bitRange>
1779                <access>read-write</access>
1780              </field>
1781              <field>
1782                <name>PC11_UR</name>
1783                <description>Protection context 11, user read enable.</description>
1784                <bitRange>[24:24]</bitRange>
1785                <access>read-only</access>
1786              </field>
1787              <field>
1788                <name>PC11_UW</name>
1789                <description>Protection context 11, user write enable.</description>
1790                <bitRange>[25:25]</bitRange>
1791                <access>read-write</access>
1792              </field>
1793              <field>
1794                <name>PC11_PR</name>
1795                <description>Protection context 11, privileged read enable.</description>
1796                <bitRange>[26:26]</bitRange>
1797                <access>read-only</access>
1798              </field>
1799              <field>
1800                <name>PC11_PW</name>
1801                <description>Protection context 11, privileged write enable.</description>
1802                <bitRange>[27:27]</bitRange>
1803                <access>read-write</access>
1804              </field>
1805              <field>
1806                <name>PC11_NS</name>
1807                <description>Protection context 11, non-secure.</description>
1808                <bitRange>[28:28]</bitRange>
1809                <access>read-write</access>
1810              </field>
1811            </fields>
1812          </register>
1813          <register>
1814            <name>MS_ATT3</name>
1815            <description>Master attributes 3</description>
1816            <addressOffset>0x3C</addressOffset>
1817            <size>32</size>
1818            <access>read-write</access>
1819            <resetValue>0x1F1F1F1F</resetValue>
1820            <resetMask>0x1F1F1F1F</resetMask>
1821            <fields>
1822              <field>
1823                <name>PC12_UR</name>
1824                <description>Protection context 12, user read enable.</description>
1825                <bitRange>[0:0]</bitRange>
1826                <access>read-only</access>
1827              </field>
1828              <field>
1829                <name>PC12_UW</name>
1830                <description>Protection context 12, user write enable.</description>
1831                <bitRange>[1:1]</bitRange>
1832                <access>read-write</access>
1833              </field>
1834              <field>
1835                <name>PC12_PR</name>
1836                <description>Protection context 12, privileged read enable.</description>
1837                <bitRange>[2:2]</bitRange>
1838                <access>read-only</access>
1839              </field>
1840              <field>
1841                <name>PC12_PW</name>
1842                <description>Protection context 12, privileged write enable.</description>
1843                <bitRange>[3:3]</bitRange>
1844                <access>read-write</access>
1845              </field>
1846              <field>
1847                <name>PC12_NS</name>
1848                <description>Protection context 12, non-secure.</description>
1849                <bitRange>[4:4]</bitRange>
1850                <access>read-write</access>
1851              </field>
1852              <field>
1853                <name>PC13_UR</name>
1854                <description>Protection context 13, user read enable.</description>
1855                <bitRange>[8:8]</bitRange>
1856                <access>read-only</access>
1857              </field>
1858              <field>
1859                <name>PC13_UW</name>
1860                <description>Protection context 13, user write enable.</description>
1861                <bitRange>[9:9]</bitRange>
1862                <access>read-write</access>
1863              </field>
1864              <field>
1865                <name>PC13_PR</name>
1866                <description>Protection context 13, privileged read enable.</description>
1867                <bitRange>[10:10]</bitRange>
1868                <access>read-only</access>
1869              </field>
1870              <field>
1871                <name>PC13_PW</name>
1872                <description>Protection context 13, privileged write enable.</description>
1873                <bitRange>[11:11]</bitRange>
1874                <access>read-write</access>
1875              </field>
1876              <field>
1877                <name>PC13_NS</name>
1878                <description>Protection context 13, non-secure.</description>
1879                <bitRange>[12:12]</bitRange>
1880                <access>read-write</access>
1881              </field>
1882              <field>
1883                <name>PC14_UR</name>
1884                <description>Protection context 14, user read enable.</description>
1885                <bitRange>[16:16]</bitRange>
1886                <access>read-only</access>
1887              </field>
1888              <field>
1889                <name>PC14_UW</name>
1890                <description>Protection context 14, user write enable.</description>
1891                <bitRange>[17:17]</bitRange>
1892                <access>read-write</access>
1893              </field>
1894              <field>
1895                <name>PC14_PR</name>
1896                <description>Protection context 14, privileged read enable.</description>
1897                <bitRange>[18:18]</bitRange>
1898                <access>read-only</access>
1899              </field>
1900              <field>
1901                <name>PC14_PW</name>
1902                <description>Protection context 14, privileged write enable.</description>
1903                <bitRange>[19:19]</bitRange>
1904                <access>read-write</access>
1905              </field>
1906              <field>
1907                <name>PC14_NS</name>
1908                <description>Protection context 14, non-secure.</description>
1909                <bitRange>[20:20]</bitRange>
1910                <access>read-write</access>
1911              </field>
1912              <field>
1913                <name>PC15_UR</name>
1914                <description>Protection context 15, user read enable.</description>
1915                <bitRange>[24:24]</bitRange>
1916                <access>read-only</access>
1917              </field>
1918              <field>
1919                <name>PC15_UW</name>
1920                <description>Protection context 15, user write enable.</description>
1921                <bitRange>[25:25]</bitRange>
1922                <access>read-write</access>
1923              </field>
1924              <field>
1925                <name>PC15_PR</name>
1926                <description>Protection context 15, privileged read enable.</description>
1927                <bitRange>[26:26]</bitRange>
1928                <access>read-only</access>
1929              </field>
1930              <field>
1931                <name>PC15_PW</name>
1932                <description>Protection context 15, privileged write enable.</description>
1933                <bitRange>[27:27]</bitRange>
1934                <access>read-write</access>
1935              </field>
1936              <field>
1937                <name>PC15_NS</name>
1938                <description>Protection context 15, non-secure.</description>
1939                <bitRange>[28:28]</bitRange>
1940                <access>read-write</access>
1941              </field>
1942            </fields>
1943          </register>
1944        </cluster>
1945        <cluster>
1946          <dim>458</dim>
1947          <dimIncrement>64</dimIncrement>
1948          <name>PPU_FX[%s]</name>
1949          <description>Fixed protection structure pair</description>
1950          <addressOffset>0x00000800</addressOffset>
1951          <register>
1952            <name>SL_ADDR</name>
1953            <description>Slave region, base address</description>
1954            <addressOffset>0x0</addressOffset>
1955            <size>32</size>
1956            <access>read-only</access>
1957            <resetValue>0x0</resetValue>
1958            <resetMask>0xFFFFFFFC</resetMask>
1959            <fields>
1960              <field>
1961                <name>ADDR30</name>
1962                <description>This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's.</description>
1963                <bitRange>[31:2]</bitRange>
1964                <access>read-only</access>
1965              </field>
1966            </fields>
1967          </register>
1968          <register>
1969            <name>SL_SIZE</name>
1970            <description>Slave region, size</description>
1971            <addressOffset>0x4</addressOffset>
1972            <size>32</size>
1973            <access>read-only</access>
1974            <resetValue>0x80000000</resetValue>
1975            <resetMask>0x9F000000</resetMask>
1976            <fields>
1977              <field>
1978                <name>REGION_SIZE</name>
1979                <description>This field specifies the size of the slave region:
1980'0': Undefined.
1981'1': 4 B region (this is the smallest region size).
1982'2': 8 B region
1983'3': 16 B region
1984'4': 32 B region
1985'5': 64 B region
1986'6': 128 B region
1987'7': 256 B region
1988'8': 512 B region
1989'9': 1 KB region
1990'10': 2 KB region
1991'11': 4 KB region
1992'12': 8 KB region
1993'13': 16 KB region
1994'14': 32 KB region
1995'15': 64 KB region
1996'16': 128 KB region
1997'17': 256 KB region
1998'18': 512 KB region
1999'19': 1 MB region
2000'20': 2 MB region
2001'21': 4 MB region
2002'22': 8 MB region
2003'23': 16 MB region
2004'24': 32 MB region
2005'25': 64 MB region
2006'26': 128 MB region
2007'27': 256 MB region
2008'28': 512 MB region
2009'29': 1 GB region
2010'30': 2 GB region
2011'31': 4 GB region</description>
2012                <bitRange>[28:24]</bitRange>
2013                <access>read-only</access>
2014              </field>
2015              <field>
2016                <name>VALID</name>
2017                <description>Slave region enable:
2018'0': Disabled. A disabled region will never result in a match on the transfer address.
2019'1': Enabled.</description>
2020                <bitRange>[31:31]</bitRange>
2021                <access>read-only</access>
2022              </field>
2023            </fields>
2024          </register>
2025          <register>
2026            <name>SL_ATT0</name>
2027            <description>Slave attributes 0</description>
2028            <addressOffset>0x10</addressOffset>
2029            <size>32</size>
2030            <access>read-write</access>
2031            <resetValue>0x1F1F1F1F</resetValue>
2032            <resetMask>0x1F1F1F1F</resetMask>
2033            <fields>
2034              <field>
2035                <name>PC0_UR</name>
2036                <description>Protection context 0, user read enable:
2037'0': Disabled (user, read accesses are NOT allowed).
2038'1': Enabled (user, read accesses are allowed).</description>
2039                <bitRange>[0:0]</bitRange>
2040                <access>read-only</access>
2041              </field>
2042              <field>
2043                <name>PC0_UW</name>
2044                <description>Protection context 0, user write enable:
2045'0': Disabled (user, write accesses are NOT allowed).
2046'1': Enabled (user, write accesses are allowed).</description>
2047                <bitRange>[1:1]</bitRange>
2048                <access>read-only</access>
2049              </field>
2050              <field>
2051                <name>PC0_PR</name>
2052                <description>Protection context 0, privileged read enable:
2053'0': Disabled (privileged, read accesses are NOT allowed).
2054'1': Enabled (privileged, read accesses are allowed).</description>
2055                <bitRange>[2:2]</bitRange>
2056                <access>read-only</access>
2057              </field>
2058              <field>
2059                <name>PC0_PW</name>
2060                <description>Protection context 0, privileged write enable:
2061'0': Disabled (privileged, write accesses are NOT allowed).
2062'1': Enabled (privileged, write accesses are allowed).</description>
2063                <bitRange>[3:3]</bitRange>
2064                <access>read-only</access>
2065              </field>
2066              <field>
2067                <name>PC0_NS</name>
2068                <description>Protection context 0, non-secure:
2069'0': Secure (secure accesses allowed, non-secure access NOT allowed).
2070'1': Non-secure (both secure and non-secure accesses allowed).</description>
2071                <bitRange>[4:4]</bitRange>
2072                <access>read-only</access>
2073              </field>
2074              <field>
2075                <name>PC1_UR</name>
2076                <description>Protection context 1, user read enable.</description>
2077                <bitRange>[8:8]</bitRange>
2078                <access>read-write</access>
2079              </field>
2080              <field>
2081                <name>PC1_UW</name>
2082                <description>Protection context 1, user write enable.</description>
2083                <bitRange>[9:9]</bitRange>
2084                <access>read-write</access>
2085              </field>
2086              <field>
2087                <name>PC1_PR</name>
2088                <description>Protection context 1, privileged read enable.</description>
2089                <bitRange>[10:10]</bitRange>
2090                <access>read-write</access>
2091              </field>
2092              <field>
2093                <name>PC1_PW</name>
2094                <description>Protection context 1, privileged write enable.</description>
2095                <bitRange>[11:11]</bitRange>
2096                <access>read-write</access>
2097              </field>
2098              <field>
2099                <name>PC1_NS</name>
2100                <description>Protection context 1, non-secure.</description>
2101                <bitRange>[12:12]</bitRange>
2102                <access>read-write</access>
2103              </field>
2104              <field>
2105                <name>PC2_UR</name>
2106                <description>Protection context 2, user read enable.</description>
2107                <bitRange>[16:16]</bitRange>
2108                <access>read-write</access>
2109              </field>
2110              <field>
2111                <name>PC2_UW</name>
2112                <description>Protection context 2, user write enable.</description>
2113                <bitRange>[17:17]</bitRange>
2114                <access>read-write</access>
2115              </field>
2116              <field>
2117                <name>PC2_PR</name>
2118                <description>Protection context 2, privileged read enable.</description>
2119                <bitRange>[18:18]</bitRange>
2120                <access>read-write</access>
2121              </field>
2122              <field>
2123                <name>PC2_PW</name>
2124                <description>Protection context 2, privileged write enable.</description>
2125                <bitRange>[19:19]</bitRange>
2126                <access>read-write</access>
2127              </field>
2128              <field>
2129                <name>PC2_NS</name>
2130                <description>Protection context 2, non-secure.</description>
2131                <bitRange>[20:20]</bitRange>
2132                <access>read-write</access>
2133              </field>
2134              <field>
2135                <name>PC3_UR</name>
2136                <description>Protection context 3, user read enable.</description>
2137                <bitRange>[24:24]</bitRange>
2138                <access>read-write</access>
2139              </field>
2140              <field>
2141                <name>PC3_UW</name>
2142                <description>Protection context 3, user write enable.</description>
2143                <bitRange>[25:25]</bitRange>
2144                <access>read-write</access>
2145              </field>
2146              <field>
2147                <name>PC3_PR</name>
2148                <description>Protection context 3, privileged read enable.</description>
2149                <bitRange>[26:26]</bitRange>
2150                <access>read-write</access>
2151              </field>
2152              <field>
2153                <name>PC3_PW</name>
2154                <description>Protection context 3, privileged write enable.</description>
2155                <bitRange>[27:27]</bitRange>
2156                <access>read-write</access>
2157              </field>
2158              <field>
2159                <name>PC3_NS</name>
2160                <description>Protection context 3, non-secure.</description>
2161                <bitRange>[28:28]</bitRange>
2162                <access>read-write</access>
2163              </field>
2164            </fields>
2165          </register>
2166          <register>
2167            <name>SL_ATT1</name>
2168            <description>Slave attributes 1</description>
2169            <addressOffset>0x14</addressOffset>
2170            <size>32</size>
2171            <access>read-write</access>
2172            <resetValue>0x1F1F1F1F</resetValue>
2173            <resetMask>0x1F1F1F1F</resetMask>
2174            <fields>
2175              <field>
2176                <name>PC4_UR</name>
2177                <description>Protection context 4, user read enable.</description>
2178                <bitRange>[0:0]</bitRange>
2179                <access>read-write</access>
2180              </field>
2181              <field>
2182                <name>PC4_UW</name>
2183                <description>Protection context 4, user write enable.</description>
2184                <bitRange>[1:1]</bitRange>
2185                <access>read-write</access>
2186              </field>
2187              <field>
2188                <name>PC4_PR</name>
2189                <description>Protection context 4, privileged read enable.</description>
2190                <bitRange>[2:2]</bitRange>
2191                <access>read-write</access>
2192              </field>
2193              <field>
2194                <name>PC4_PW</name>
2195                <description>Protection context 4, privileged write enable.</description>
2196                <bitRange>[3:3]</bitRange>
2197                <access>read-write</access>
2198              </field>
2199              <field>
2200                <name>PC4_NS</name>
2201                <description>Protection context 4, non-secure.</description>
2202                <bitRange>[4:4]</bitRange>
2203                <access>read-write</access>
2204              </field>
2205              <field>
2206                <name>PC5_UR</name>
2207                <description>Protection context 5, user read enable.</description>
2208                <bitRange>[8:8]</bitRange>
2209                <access>read-write</access>
2210              </field>
2211              <field>
2212                <name>PC5_UW</name>
2213                <description>Protection context 5, user write enable.</description>
2214                <bitRange>[9:9]</bitRange>
2215                <access>read-write</access>
2216              </field>
2217              <field>
2218                <name>PC5_PR</name>
2219                <description>Protection context 5, privileged read enable.</description>
2220                <bitRange>[10:10]</bitRange>
2221                <access>read-write</access>
2222              </field>
2223              <field>
2224                <name>PC5_PW</name>
2225                <description>Protection context 5, privileged write enable.</description>
2226                <bitRange>[11:11]</bitRange>
2227                <access>read-write</access>
2228              </field>
2229              <field>
2230                <name>PC5_NS</name>
2231                <description>Protection context 5, non-secure.</description>
2232                <bitRange>[12:12]</bitRange>
2233                <access>read-write</access>
2234              </field>
2235              <field>
2236                <name>PC6_UR</name>
2237                <description>Protection context 6, user read enable.</description>
2238                <bitRange>[16:16]</bitRange>
2239                <access>read-write</access>
2240              </field>
2241              <field>
2242                <name>PC6_UW</name>
2243                <description>Protection context 6, user write enable.</description>
2244                <bitRange>[17:17]</bitRange>
2245                <access>read-write</access>
2246              </field>
2247              <field>
2248                <name>PC6_PR</name>
2249                <description>Protection context 6, privileged read enable.</description>
2250                <bitRange>[18:18]</bitRange>
2251                <access>read-write</access>
2252              </field>
2253              <field>
2254                <name>PC6_PW</name>
2255                <description>Protection context 6, privileged write enable.</description>
2256                <bitRange>[19:19]</bitRange>
2257                <access>read-write</access>
2258              </field>
2259              <field>
2260                <name>PC6_NS</name>
2261                <description>Protection context 6, non-secure.</description>
2262                <bitRange>[20:20]</bitRange>
2263                <access>read-write</access>
2264              </field>
2265              <field>
2266                <name>PC7_UR</name>
2267                <description>Protection context 7, user read enable.</description>
2268                <bitRange>[24:24]</bitRange>
2269                <access>read-write</access>
2270              </field>
2271              <field>
2272                <name>PC7_UW</name>
2273                <description>Protection context 7, user write enable.</description>
2274                <bitRange>[25:25]</bitRange>
2275                <access>read-write</access>
2276              </field>
2277              <field>
2278                <name>PC7_PR</name>
2279                <description>Protection context 7, privileged read enable.</description>
2280                <bitRange>[26:26]</bitRange>
2281                <access>read-write</access>
2282              </field>
2283              <field>
2284                <name>PC7_PW</name>
2285                <description>Protection context 7, privileged write enable.</description>
2286                <bitRange>[27:27]</bitRange>
2287                <access>read-write</access>
2288              </field>
2289              <field>
2290                <name>PC7_NS</name>
2291                <description>Protection context 7, non-secure.</description>
2292                <bitRange>[28:28]</bitRange>
2293                <access>read-write</access>
2294              </field>
2295            </fields>
2296          </register>
2297          <register>
2298            <name>SL_ATT2</name>
2299            <description>Slave attributes 2</description>
2300            <addressOffset>0x18</addressOffset>
2301            <size>32</size>
2302            <access>read-write</access>
2303            <resetValue>0x1F1F1F1F</resetValue>
2304            <resetMask>0x1F1F1F1F</resetMask>
2305            <fields>
2306              <field>
2307                <name>PC8_UR</name>
2308                <description>Protection context 8, user read enable.</description>
2309                <bitRange>[0:0]</bitRange>
2310                <access>read-write</access>
2311              </field>
2312              <field>
2313                <name>PC8_UW</name>
2314                <description>Protection context 8, user write enable.</description>
2315                <bitRange>[1:1]</bitRange>
2316                <access>read-write</access>
2317              </field>
2318              <field>
2319                <name>PC8_PR</name>
2320                <description>Protection context 8, privileged read enable.</description>
2321                <bitRange>[2:2]</bitRange>
2322                <access>read-write</access>
2323              </field>
2324              <field>
2325                <name>PC8_PW</name>
2326                <description>Protection context 8, privileged write enable.</description>
2327                <bitRange>[3:3]</bitRange>
2328                <access>read-write</access>
2329              </field>
2330              <field>
2331                <name>PC8_NS</name>
2332                <description>Protection context 8, non-secure.</description>
2333                <bitRange>[4:4]</bitRange>
2334                <access>read-write</access>
2335              </field>
2336              <field>
2337                <name>PC9_UR</name>
2338                <description>Protection context 9, user read enable.</description>
2339                <bitRange>[8:8]</bitRange>
2340                <access>read-write</access>
2341              </field>
2342              <field>
2343                <name>PC9_UW</name>
2344                <description>Protection context 9, user write enable.</description>
2345                <bitRange>[9:9]</bitRange>
2346                <access>read-write</access>
2347              </field>
2348              <field>
2349                <name>PC9_PR</name>
2350                <description>Protection context 9, privileged read enable.</description>
2351                <bitRange>[10:10]</bitRange>
2352                <access>read-write</access>
2353              </field>
2354              <field>
2355                <name>PC9_PW</name>
2356                <description>Protection context 9, privileged write enable.</description>
2357                <bitRange>[11:11]</bitRange>
2358                <access>read-write</access>
2359              </field>
2360              <field>
2361                <name>PC9_NS</name>
2362                <description>Protection context 9, non-secure.</description>
2363                <bitRange>[12:12]</bitRange>
2364                <access>read-write</access>
2365              </field>
2366              <field>
2367                <name>PC10_UR</name>
2368                <description>Protection context 10, user read enable.</description>
2369                <bitRange>[16:16]</bitRange>
2370                <access>read-write</access>
2371              </field>
2372              <field>
2373                <name>PC10_UW</name>
2374                <description>Protection context 10, user write enable.</description>
2375                <bitRange>[17:17]</bitRange>
2376                <access>read-write</access>
2377              </field>
2378              <field>
2379                <name>PC10_PR</name>
2380                <description>Protection context 10, privileged read enable.</description>
2381                <bitRange>[18:18]</bitRange>
2382                <access>read-write</access>
2383              </field>
2384              <field>
2385                <name>PC10_PW</name>
2386                <description>Protection context 10, privileged write enable.</description>
2387                <bitRange>[19:19]</bitRange>
2388                <access>read-write</access>
2389              </field>
2390              <field>
2391                <name>PC10_NS</name>
2392                <description>Protection context 10, non-secure.</description>
2393                <bitRange>[20:20]</bitRange>
2394                <access>read-write</access>
2395              </field>
2396              <field>
2397                <name>PC11_UR</name>
2398                <description>Protection context 11, user read enable.</description>
2399                <bitRange>[24:24]</bitRange>
2400                <access>read-write</access>
2401              </field>
2402              <field>
2403                <name>PC11_UW</name>
2404                <description>Protection context 11, user write enable.</description>
2405                <bitRange>[25:25]</bitRange>
2406                <access>read-write</access>
2407              </field>
2408              <field>
2409                <name>PC11_PR</name>
2410                <description>Protection context 11, privileged read enable.</description>
2411                <bitRange>[26:26]</bitRange>
2412                <access>read-write</access>
2413              </field>
2414              <field>
2415                <name>PC11_PW</name>
2416                <description>Protection context 11, privileged write enable.</description>
2417                <bitRange>[27:27]</bitRange>
2418                <access>read-write</access>
2419              </field>
2420              <field>
2421                <name>PC11_NS</name>
2422                <description>Protection context 11, non-secure.</description>
2423                <bitRange>[28:28]</bitRange>
2424                <access>read-write</access>
2425              </field>
2426            </fields>
2427          </register>
2428          <register>
2429            <name>SL_ATT3</name>
2430            <description>Slave attributes 3</description>
2431            <addressOffset>0x1C</addressOffset>
2432            <size>32</size>
2433            <access>read-write</access>
2434            <resetValue>0x1F1F1F1F</resetValue>
2435            <resetMask>0x1F1F1F1F</resetMask>
2436            <fields>
2437              <field>
2438                <name>PC12_UR</name>
2439                <description>Protection context 12, user read enable.</description>
2440                <bitRange>[0:0]</bitRange>
2441                <access>read-write</access>
2442              </field>
2443              <field>
2444                <name>PC12_UW</name>
2445                <description>Protection context 12, user write enable.</description>
2446                <bitRange>[1:1]</bitRange>
2447                <access>read-write</access>
2448              </field>
2449              <field>
2450                <name>PC12_PR</name>
2451                <description>Protection context 12, privileged read enable.</description>
2452                <bitRange>[2:2]</bitRange>
2453                <access>read-write</access>
2454              </field>
2455              <field>
2456                <name>PC12_PW</name>
2457                <description>Protection context 12, privileged write enable.</description>
2458                <bitRange>[3:3]</bitRange>
2459                <access>read-write</access>
2460              </field>
2461              <field>
2462                <name>PC12_NS</name>
2463                <description>Protection context 12, non-secure.</description>
2464                <bitRange>[4:4]</bitRange>
2465                <access>read-write</access>
2466              </field>
2467              <field>
2468                <name>PC13_UR</name>
2469                <description>Protection context 13, user read enable.</description>
2470                <bitRange>[8:8]</bitRange>
2471                <access>read-write</access>
2472              </field>
2473              <field>
2474                <name>PC13_UW</name>
2475                <description>Protection context 13, user write enable.</description>
2476                <bitRange>[9:9]</bitRange>
2477                <access>read-write</access>
2478              </field>
2479              <field>
2480                <name>PC13_PR</name>
2481                <description>Protection context 13, privileged read enable.</description>
2482                <bitRange>[10:10]</bitRange>
2483                <access>read-write</access>
2484              </field>
2485              <field>
2486                <name>PC13_PW</name>
2487                <description>Protection context 13, privileged write enable.</description>
2488                <bitRange>[11:11]</bitRange>
2489                <access>read-write</access>
2490              </field>
2491              <field>
2492                <name>PC13_NS</name>
2493                <description>Protection context 13, non-secure.</description>
2494                <bitRange>[12:12]</bitRange>
2495                <access>read-write</access>
2496              </field>
2497              <field>
2498                <name>PC14_UR</name>
2499                <description>Protection context 14, user read enable.</description>
2500                <bitRange>[16:16]</bitRange>
2501                <access>read-write</access>
2502              </field>
2503              <field>
2504                <name>PC14_UW</name>
2505                <description>Protection context 14, user write enable.</description>
2506                <bitRange>[17:17]</bitRange>
2507                <access>read-write</access>
2508              </field>
2509              <field>
2510                <name>PC14_PR</name>
2511                <description>Protection context 14, privileged read enable.</description>
2512                <bitRange>[18:18]</bitRange>
2513                <access>read-write</access>
2514              </field>
2515              <field>
2516                <name>PC14_PW</name>
2517                <description>Protection context 14, privileged write enable.</description>
2518                <bitRange>[19:19]</bitRange>
2519                <access>read-write</access>
2520              </field>
2521              <field>
2522                <name>PC14_NS</name>
2523                <description>Protection context 14, non-secure.</description>
2524                <bitRange>[20:20]</bitRange>
2525                <access>read-write</access>
2526              </field>
2527              <field>
2528                <name>PC15_UR</name>
2529                <description>Protection context 15, user read enable.</description>
2530                <bitRange>[24:24]</bitRange>
2531                <access>read-write</access>
2532              </field>
2533              <field>
2534                <name>PC15_UW</name>
2535                <description>Protection context 15, user write enable.</description>
2536                <bitRange>[25:25]</bitRange>
2537                <access>read-write</access>
2538              </field>
2539              <field>
2540                <name>PC15_PR</name>
2541                <description>Protection context 15, privileged read enable.</description>
2542                <bitRange>[26:26]</bitRange>
2543                <access>read-write</access>
2544              </field>
2545              <field>
2546                <name>PC15_PW</name>
2547                <description>Protection context 15, privileged write enable.</description>
2548                <bitRange>[27:27]</bitRange>
2549                <access>read-write</access>
2550              </field>
2551              <field>
2552                <name>PC15_NS</name>
2553                <description>Protection context 15, non-secure.</description>
2554                <bitRange>[28:28]</bitRange>
2555                <access>read-write</access>
2556              </field>
2557            </fields>
2558          </register>
2559          <register>
2560            <name>MS_ADDR</name>
2561            <description>Master region, base address</description>
2562            <addressOffset>0x20</addressOffset>
2563            <size>32</size>
2564            <access>read-only</access>
2565            <resetValue>0x0</resetValue>
2566            <resetMask>0xFFFFFFC0</resetMask>
2567            <fields>
2568              <field>
2569                <name>ADDR26</name>
2570                <description>This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register.</description>
2571                <bitRange>[31:6]</bitRange>
2572                <access>read-only</access>
2573              </field>
2574            </fields>
2575          </register>
2576          <register>
2577            <name>MS_SIZE</name>
2578            <description>Master region, size</description>
2579            <addressOffset>0x24</addressOffset>
2580            <size>32</size>
2581            <access>read-only</access>
2582            <resetValue>0x85000000</resetValue>
2583            <resetMask>0x9F000000</resetMask>
2584            <fields>
2585              <field>
2586                <name>REGION_SIZE</name>
2587                <description>This field specifies the size of the master region:
2588'5': 64 B region
2589
2590The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3.</description>
2591                <bitRange>[28:24]</bitRange>
2592                <access>read-only</access>
2593              </field>
2594              <field>
2595                <name>VALID</name>
2596                <description>Master region enable:
2597'1': Enabled.</description>
2598                <bitRange>[31:31]</bitRange>
2599                <access>read-only</access>
2600              </field>
2601            </fields>
2602          </register>
2603          <register>
2604            <name>MS_ATT0</name>
2605            <description>Master attributes 0</description>
2606            <addressOffset>0x30</addressOffset>
2607            <size>32</size>
2608            <access>read-write</access>
2609            <resetValue>0x1F1F1F1F</resetValue>
2610            <resetMask>0x1F1F1F1F</resetMask>
2611            <fields>
2612              <field>
2613                <name>PC0_UR</name>
2614                <description>Protection context 0, user read enable:
2615'0': Disabled (user, read accesses are NOT allowed).
2616'1': Enabled (user, read accesses are allowed).</description>
2617                <bitRange>[0:0]</bitRange>
2618                <access>read-only</access>
2619              </field>
2620              <field>
2621                <name>PC0_UW</name>
2622                <description>Protection context 0, user write enable:
2623'0': Disabled (user, write accesses are NOT allowed).
2624'1': Enabled (user, write accesses are allowed).</description>
2625                <bitRange>[1:1]</bitRange>
2626                <access>read-only</access>
2627              </field>
2628              <field>
2629                <name>PC0_PR</name>
2630                <description>Protection context 0, privileged read enable:
2631'0': Disabled (privileged, read accesses are NOT allowed).
2632'1': Enabled (privileged, read accesses are allowed).</description>
2633                <bitRange>[2:2]</bitRange>
2634                <access>read-only</access>
2635              </field>
2636              <field>
2637                <name>PC0_PW</name>
2638                <description>Protection context 0, privileged write enable:
2639'0': Disabled (privileged, write accesses are NOT allowed).
2640'1': Enabled (privileged, write accesses are allowed).</description>
2641                <bitRange>[3:3]</bitRange>
2642                <access>read-only</access>
2643              </field>
2644              <field>
2645                <name>PC0_NS</name>
2646                <description>Protection context 0, non-secure:
2647'0': Secure (secure accesses allowed, non-secure access NOT allowed).
2648'1': Non-secure (both secure and non-secure accesses allowed).</description>
2649                <bitRange>[4:4]</bitRange>
2650                <access>read-only</access>
2651              </field>
2652              <field>
2653                <name>PC1_UR</name>
2654                <description>Protection context 1, user read enable.</description>
2655                <bitRange>[8:8]</bitRange>
2656                <access>read-only</access>
2657              </field>
2658              <field>
2659                <name>PC1_UW</name>
2660                <description>Protection context 1, user write enable.</description>
2661                <bitRange>[9:9]</bitRange>
2662                <access>read-write</access>
2663              </field>
2664              <field>
2665                <name>PC1_PR</name>
2666                <description>Protection context 1, privileged read enable.</description>
2667                <bitRange>[10:10]</bitRange>
2668                <access>read-only</access>
2669              </field>
2670              <field>
2671                <name>PC1_PW</name>
2672                <description>Protection context 1, privileged write enable.</description>
2673                <bitRange>[11:11]</bitRange>
2674                <access>read-write</access>
2675              </field>
2676              <field>
2677                <name>PC1_NS</name>
2678                <description>Protection context 1, non-secure.</description>
2679                <bitRange>[12:12]</bitRange>
2680                <access>read-write</access>
2681              </field>
2682              <field>
2683                <name>PC2_UR</name>
2684                <description>Protection context 2, user read enable.</description>
2685                <bitRange>[16:16]</bitRange>
2686                <access>read-only</access>
2687              </field>
2688              <field>
2689                <name>PC2_UW</name>
2690                <description>Protection context 2, user write enable.</description>
2691                <bitRange>[17:17]</bitRange>
2692                <access>read-write</access>
2693              </field>
2694              <field>
2695                <name>PC2_PR</name>
2696                <description>Protection context 2, privileged read enable.</description>
2697                <bitRange>[18:18]</bitRange>
2698                <access>read-only</access>
2699              </field>
2700              <field>
2701                <name>PC2_PW</name>
2702                <description>Protection context 2, privileged write enable.</description>
2703                <bitRange>[19:19]</bitRange>
2704                <access>read-write</access>
2705              </field>
2706              <field>
2707                <name>PC2_NS</name>
2708                <description>Protection context 2, non-secure.</description>
2709                <bitRange>[20:20]</bitRange>
2710                <access>read-write</access>
2711              </field>
2712              <field>
2713                <name>PC3_UR</name>
2714                <description>Protection context 3, user read enable.</description>
2715                <bitRange>[24:24]</bitRange>
2716                <access>read-only</access>
2717              </field>
2718              <field>
2719                <name>PC3_UW</name>
2720                <description>Protection context 3, user write enable.</description>
2721                <bitRange>[25:25]</bitRange>
2722                <access>read-write</access>
2723              </field>
2724              <field>
2725                <name>PC3_PR</name>
2726                <description>Protection context 3, privileged read enable.</description>
2727                <bitRange>[26:26]</bitRange>
2728                <access>read-only</access>
2729              </field>
2730              <field>
2731                <name>PC3_PW</name>
2732                <description>Protection context 3, privileged write enable.</description>
2733                <bitRange>[27:27]</bitRange>
2734                <access>read-write</access>
2735              </field>
2736              <field>
2737                <name>PC3_NS</name>
2738                <description>Protection context 3, non-secure.</description>
2739                <bitRange>[28:28]</bitRange>
2740                <access>read-write</access>
2741              </field>
2742            </fields>
2743          </register>
2744          <register>
2745            <name>MS_ATT1</name>
2746            <description>Master attributes 1</description>
2747            <addressOffset>0x34</addressOffset>
2748            <size>32</size>
2749            <access>read-write</access>
2750            <resetValue>0x1F1F1F1F</resetValue>
2751            <resetMask>0x1F1F1F1F</resetMask>
2752            <fields>
2753              <field>
2754                <name>PC4_UR</name>
2755                <description>Protection context 4, user read enable.</description>
2756                <bitRange>[0:0]</bitRange>
2757                <access>read-only</access>
2758              </field>
2759              <field>
2760                <name>PC4_UW</name>
2761                <description>Protection context 4, user write enable.</description>
2762                <bitRange>[1:1]</bitRange>
2763                <access>read-write</access>
2764              </field>
2765              <field>
2766                <name>PC4_PR</name>
2767                <description>Protection context 4, privileged read enable.</description>
2768                <bitRange>[2:2]</bitRange>
2769                <access>read-only</access>
2770              </field>
2771              <field>
2772                <name>PC4_PW</name>
2773                <description>Protection context 4, privileged write enable.</description>
2774                <bitRange>[3:3]</bitRange>
2775                <access>read-write</access>
2776              </field>
2777              <field>
2778                <name>PC4_NS</name>
2779                <description>Protection context 4, non-secure.</description>
2780                <bitRange>[4:4]</bitRange>
2781                <access>read-write</access>
2782              </field>
2783              <field>
2784                <name>PC5_UR</name>
2785                <description>Protection context 5, user read enable.</description>
2786                <bitRange>[8:8]</bitRange>
2787                <access>read-only</access>
2788              </field>
2789              <field>
2790                <name>PC5_UW</name>
2791                <description>Protection context 5, user write enable.</description>
2792                <bitRange>[9:9]</bitRange>
2793                <access>read-write</access>
2794              </field>
2795              <field>
2796                <name>PC5_PR</name>
2797                <description>Protection context 5, privileged read enable.</description>
2798                <bitRange>[10:10]</bitRange>
2799                <access>read-only</access>
2800              </field>
2801              <field>
2802                <name>PC5_PW</name>
2803                <description>Protection context 5, privileged write enable.</description>
2804                <bitRange>[11:11]</bitRange>
2805                <access>read-write</access>
2806              </field>
2807              <field>
2808                <name>PC5_NS</name>
2809                <description>Protection context 5, non-secure.</description>
2810                <bitRange>[12:12]</bitRange>
2811                <access>read-write</access>
2812              </field>
2813              <field>
2814                <name>PC6_UR</name>
2815                <description>Protection context 6, user read enable.</description>
2816                <bitRange>[16:16]</bitRange>
2817                <access>read-only</access>
2818              </field>
2819              <field>
2820                <name>PC6_UW</name>
2821                <description>Protection context 6, user write enable.</description>
2822                <bitRange>[17:17]</bitRange>
2823                <access>read-write</access>
2824              </field>
2825              <field>
2826                <name>PC6_PR</name>
2827                <description>Protection context 6, privileged read enable.</description>
2828                <bitRange>[18:18]</bitRange>
2829                <access>read-only</access>
2830              </field>
2831              <field>
2832                <name>PC6_PW</name>
2833                <description>Protection context 6, privileged write enable.</description>
2834                <bitRange>[19:19]</bitRange>
2835                <access>read-write</access>
2836              </field>
2837              <field>
2838                <name>PC6_NS</name>
2839                <description>Protection context 6, non-secure.</description>
2840                <bitRange>[20:20]</bitRange>
2841                <access>read-write</access>
2842              </field>
2843              <field>
2844                <name>PC7_UR</name>
2845                <description>Protection context 7, user read enable.</description>
2846                <bitRange>[24:24]</bitRange>
2847                <access>read-only</access>
2848              </field>
2849              <field>
2850                <name>PC7_UW</name>
2851                <description>Protection context 7, user write enable.</description>
2852                <bitRange>[25:25]</bitRange>
2853                <access>read-write</access>
2854              </field>
2855              <field>
2856                <name>PC7_PR</name>
2857                <description>Protection context 7, privileged read enable.</description>
2858                <bitRange>[26:26]</bitRange>
2859                <access>read-only</access>
2860              </field>
2861              <field>
2862                <name>PC7_PW</name>
2863                <description>Protection context 7, privileged write enable.</description>
2864                <bitRange>[27:27]</bitRange>
2865                <access>read-write</access>
2866              </field>
2867              <field>
2868                <name>PC7_NS</name>
2869                <description>Protection context 7, non-secure.</description>
2870                <bitRange>[28:28]</bitRange>
2871                <access>read-write</access>
2872              </field>
2873            </fields>
2874          </register>
2875          <register>
2876            <name>MS_ATT2</name>
2877            <description>Master attributes 2</description>
2878            <addressOffset>0x38</addressOffset>
2879            <size>32</size>
2880            <access>read-write</access>
2881            <resetValue>0x1F1F1F1F</resetValue>
2882            <resetMask>0x1F1F1F1F</resetMask>
2883            <fields>
2884              <field>
2885                <name>PC8_UR</name>
2886                <description>Protection context 8, user read enable.</description>
2887                <bitRange>[0:0]</bitRange>
2888                <access>read-only</access>
2889              </field>
2890              <field>
2891                <name>PC8_UW</name>
2892                <description>Protection context 8, user write enable.</description>
2893                <bitRange>[1:1]</bitRange>
2894                <access>read-write</access>
2895              </field>
2896              <field>
2897                <name>PC8_PR</name>
2898                <description>Protection context 8, privileged read enable.</description>
2899                <bitRange>[2:2]</bitRange>
2900                <access>read-only</access>
2901              </field>
2902              <field>
2903                <name>PC8_PW</name>
2904                <description>Protection context 8, privileged write enable.</description>
2905                <bitRange>[3:3]</bitRange>
2906                <access>read-write</access>
2907              </field>
2908              <field>
2909                <name>PC8_NS</name>
2910                <description>Protection context 8, non-secure.</description>
2911                <bitRange>[4:4]</bitRange>
2912                <access>read-write</access>
2913              </field>
2914              <field>
2915                <name>PC9_UR</name>
2916                <description>Protection context 9, user read enable.</description>
2917                <bitRange>[8:8]</bitRange>
2918                <access>read-only</access>
2919              </field>
2920              <field>
2921                <name>PC9_UW</name>
2922                <description>Protection context 9, user write enable.</description>
2923                <bitRange>[9:9]</bitRange>
2924                <access>read-write</access>
2925              </field>
2926              <field>
2927                <name>PC9_PR</name>
2928                <description>Protection context 9, privileged read enable.</description>
2929                <bitRange>[10:10]</bitRange>
2930                <access>read-only</access>
2931              </field>
2932              <field>
2933                <name>PC9_PW</name>
2934                <description>Protection context 9, privileged write enable.</description>
2935                <bitRange>[11:11]</bitRange>
2936                <access>read-write</access>
2937              </field>
2938              <field>
2939                <name>PC9_NS</name>
2940                <description>Protection context 9, non-secure.</description>
2941                <bitRange>[12:12]</bitRange>
2942                <access>read-write</access>
2943              </field>
2944              <field>
2945                <name>PC10_UR</name>
2946                <description>Protection context 10, user read enable.</description>
2947                <bitRange>[16:16]</bitRange>
2948                <access>read-only</access>
2949              </field>
2950              <field>
2951                <name>PC10_UW</name>
2952                <description>Protection context 10, user write enable.</description>
2953                <bitRange>[17:17]</bitRange>
2954                <access>read-write</access>
2955              </field>
2956              <field>
2957                <name>PC10_PR</name>
2958                <description>Protection context 10, privileged read enable.</description>
2959                <bitRange>[18:18]</bitRange>
2960                <access>read-only</access>
2961              </field>
2962              <field>
2963                <name>PC10_PW</name>
2964                <description>Protection context 10, privileged write enable.</description>
2965                <bitRange>[19:19]</bitRange>
2966                <access>read-write</access>
2967              </field>
2968              <field>
2969                <name>PC10_NS</name>
2970                <description>Protection context 10, non-secure.</description>
2971                <bitRange>[20:20]</bitRange>
2972                <access>read-write</access>
2973              </field>
2974              <field>
2975                <name>PC11_UR</name>
2976                <description>Protection context 11, user read enable.</description>
2977                <bitRange>[24:24]</bitRange>
2978                <access>read-only</access>
2979              </field>
2980              <field>
2981                <name>PC11_UW</name>
2982                <description>Protection context 11, user write enable.</description>
2983                <bitRange>[25:25]</bitRange>
2984                <access>read-write</access>
2985              </field>
2986              <field>
2987                <name>PC11_PR</name>
2988                <description>Protection context 11, privileged read enable.</description>
2989                <bitRange>[26:26]</bitRange>
2990                <access>read-only</access>
2991              </field>
2992              <field>
2993                <name>PC11_PW</name>
2994                <description>Protection context 11, privileged write enable.</description>
2995                <bitRange>[27:27]</bitRange>
2996                <access>read-write</access>
2997              </field>
2998              <field>
2999                <name>PC11_NS</name>
3000                <description>Protection context 11, non-secure.</description>
3001                <bitRange>[28:28]</bitRange>
3002                <access>read-write</access>
3003              </field>
3004            </fields>
3005          </register>
3006          <register>
3007            <name>MS_ATT3</name>
3008            <description>Master attributes 3</description>
3009            <addressOffset>0x3C</addressOffset>
3010            <size>32</size>
3011            <access>read-write</access>
3012            <resetValue>0x1F1F1F1F</resetValue>
3013            <resetMask>0x1F1F1F1F</resetMask>
3014            <fields>
3015              <field>
3016                <name>PC12_UR</name>
3017                <description>Protection context 12, user read enable.</description>
3018                <bitRange>[0:0]</bitRange>
3019                <access>read-only</access>
3020              </field>
3021              <field>
3022                <name>PC12_UW</name>
3023                <description>Protection context 12, user write enable.</description>
3024                <bitRange>[1:1]</bitRange>
3025                <access>read-write</access>
3026              </field>
3027              <field>
3028                <name>PC12_PR</name>
3029                <description>Protection context 12, privileged read enable.</description>
3030                <bitRange>[2:2]</bitRange>
3031                <access>read-only</access>
3032              </field>
3033              <field>
3034                <name>PC12_PW</name>
3035                <description>Protection context 12, privileged write enable.</description>
3036                <bitRange>[3:3]</bitRange>
3037                <access>read-write</access>
3038              </field>
3039              <field>
3040                <name>PC12_NS</name>
3041                <description>Protection context 12, non-secure.</description>
3042                <bitRange>[4:4]</bitRange>
3043                <access>read-write</access>
3044              </field>
3045              <field>
3046                <name>PC13_UR</name>
3047                <description>Protection context 13, user read enable.</description>
3048                <bitRange>[8:8]</bitRange>
3049                <access>read-only</access>
3050              </field>
3051              <field>
3052                <name>PC13_UW</name>
3053                <description>Protection context 13, user write enable.</description>
3054                <bitRange>[9:9]</bitRange>
3055                <access>read-write</access>
3056              </field>
3057              <field>
3058                <name>PC13_PR</name>
3059                <description>Protection context 13, privileged read enable.</description>
3060                <bitRange>[10:10]</bitRange>
3061                <access>read-only</access>
3062              </field>
3063              <field>
3064                <name>PC13_PW</name>
3065                <description>Protection context 13, privileged write enable.</description>
3066                <bitRange>[11:11]</bitRange>
3067                <access>read-write</access>
3068              </field>
3069              <field>
3070                <name>PC13_NS</name>
3071                <description>Protection context 13, non-secure.</description>
3072                <bitRange>[12:12]</bitRange>
3073                <access>read-write</access>
3074              </field>
3075              <field>
3076                <name>PC14_UR</name>
3077                <description>Protection context 14, user read enable.</description>
3078                <bitRange>[16:16]</bitRange>
3079                <access>read-only</access>
3080              </field>
3081              <field>
3082                <name>PC14_UW</name>
3083                <description>Protection context 14, user write enable.</description>
3084                <bitRange>[17:17]</bitRange>
3085                <access>read-write</access>
3086              </field>
3087              <field>
3088                <name>PC14_PR</name>
3089                <description>Protection context 14, privileged read enable.</description>
3090                <bitRange>[18:18]</bitRange>
3091                <access>read-only</access>
3092              </field>
3093              <field>
3094                <name>PC14_PW</name>
3095                <description>Protection context 14, privileged write enable.</description>
3096                <bitRange>[19:19]</bitRange>
3097                <access>read-write</access>
3098              </field>
3099              <field>
3100                <name>PC14_NS</name>
3101                <description>Protection context 14, non-secure.</description>
3102                <bitRange>[20:20]</bitRange>
3103                <access>read-write</access>
3104              </field>
3105              <field>
3106                <name>PC15_UR</name>
3107                <description>Protection context 15, user read enable.</description>
3108                <bitRange>[24:24]</bitRange>
3109                <access>read-only</access>
3110              </field>
3111              <field>
3112                <name>PC15_UW</name>
3113                <description>Protection context 15, user write enable.</description>
3114                <bitRange>[25:25]</bitRange>
3115                <access>read-write</access>
3116              </field>
3117              <field>
3118                <name>PC15_PR</name>
3119                <description>Protection context 15, privileged read enable.</description>
3120                <bitRange>[26:26]</bitRange>
3121                <access>read-only</access>
3122              </field>
3123              <field>
3124                <name>PC15_PW</name>
3125                <description>Protection context 15, privileged write enable.</description>
3126                <bitRange>[27:27]</bitRange>
3127                <access>read-write</access>
3128              </field>
3129              <field>
3130                <name>PC15_NS</name>
3131                <description>Protection context 15, non-secure.</description>
3132                <bitRange>[28:28]</bitRange>
3133                <access>read-write</access>
3134              </field>
3135            </fields>
3136          </register>
3137        </cluster>
3138      </registers>
3139    </peripheral>
3140    <peripheral>
3141      <name>CRYPTO</name>
3142      <description>Cryptography component</description>
3143      <baseAddress>0x40100000</baseAddress>
3144      <addressBlock>
3145        <offset>0</offset>
3146        <size>65536</size>
3147        <usage>registers</usage>
3148      </addressBlock>
3149      <registers>
3150        <register>
3151          <name>CTL</name>
3152          <description>Control</description>
3153          <addressOffset>0x0</addressOffset>
3154          <size>32</size>
3155          <access>read-write</access>
3156          <resetValue>0x10002</resetValue>
3157          <resetMask>0x800300F3</resetMask>
3158          <fields>
3159            <field>
3160              <name>P</name>
3161              <description>User/privileged access control:
3162'0': user mode.
3163'1': privileged mode.
3164
3165This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data.
3166
3167All IP master transactions use the P field for the user/privileged access control ('hprot[1]').</description>
3168              <bitRange>[0:0]</bitRange>
3169              <access>read-write</access>
3170            </field>
3171            <field>
3172              <name>NS</name>
3173              <description>Secure/on-secure access control:
3174'0': secure.
3175'1': non-secure.
3176
3177This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data.
3178
3179All IP master transactions use the NS field for the secure/non-secure access control ('hprot[4]').</description>
3180              <bitRange>[1:1]</bitRange>
3181              <access>read-write</access>
3182            </field>
3183            <field>
3184              <name>PC</name>
3185              <description>Protection context.
3186
3187This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data.
3188
3189All IP master transactions use the PC field for the protection context. There is one exception: the LOAD_DEV_KEY instruction IP master transactions are always performed with protection context '0'.</description>
3190              <bitRange>[7:4]</bitRange>
3191              <access>read-write</access>
3192            </field>
3193            <field>
3194              <name>ECC_EN</name>
3195              <description>Enable ECC checking:
3196'0': Disabled.
3197'1': Enabled.</description>
3198              <bitRange>[16:16]</bitRange>
3199              <access>read-write</access>
3200            </field>
3201            <field>
3202              <name>ECC_INJ_EN</name>
3203              <description>Enable parity injection for SRAM.
3204When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM.</description>
3205              <bitRange>[17:17]</bitRange>
3206              <access>read-write</access>
3207            </field>
3208            <field>
3209              <name>ENABLED</name>
3210              <description>IP enable:
3211'0': Disabled. All non-retention registers (command and status registers, instruct FIFO, internal component state machines) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled.
3212'1': Enabled. When the  IP is enabled, the IP register buffer is set to '0'.</description>
3213              <bitRange>[31:31]</bitRange>
3214              <access>read-write</access>
3215              <enumeratedValues>
3216                <enumeratedValue>
3217                  <name>DISABLED</name>
3218                  <description>N/A</description>
3219                  <value>0</value>
3220                </enumeratedValue>
3221                <enumeratedValue>
3222                  <name>ENABLED</name>
3223                  <description>N/A</description>
3224                  <value>1</value>
3225                </enumeratedValue>
3226              </enumeratedValues>
3227            </field>
3228          </fields>
3229        </register>
3230        <register>
3231          <name>RAM_PWR_CTL</name>
3232          <description>SRAM power control</description>
3233          <addressOffset>0x8</addressOffset>
3234          <size>32</size>
3235          <access>read-write</access>
3236          <resetValue>0x3</resetValue>
3237          <resetMask>0x3</resetMask>
3238          <fields>
3239            <field>
3240              <name>PWR_MODE</name>
3241              <description>Set power mode for memory buffer SRAM.</description>
3242              <bitRange>[1:0]</bitRange>
3243              <access>read-write</access>
3244              <enumeratedValues>
3245                <enumeratedValue>
3246                  <name>OFF</name>
3247                  <description>See CM4_PWR_CTL</description>
3248                  <value>0</value>
3249                </enumeratedValue>
3250                <enumeratedValue>
3251                  <name>RSVD</name>
3252                  <description>undefined</description>
3253                  <value>1</value>
3254                </enumeratedValue>
3255                <enumeratedValue>
3256                  <name>RETAINED</name>
3257                  <description>See CM4_PWR_CTL</description>
3258                  <value>2</value>
3259                </enumeratedValue>
3260                <enumeratedValue>
3261                  <name>ENABLED</name>
3262                  <description>See CM4_PWR_CTL</description>
3263                  <value>3</value>
3264                </enumeratedValue>
3265              </enumeratedValues>
3266            </field>
3267          </fields>
3268        </register>
3269        <register>
3270          <name>RAM_PWR_DELAY_CTL</name>
3271          <description>SRAM power delay control</description>
3272          <addressOffset>0xC</addressOffset>
3273          <size>32</size>
3274          <access>read-write</access>
3275          <resetValue>0x96</resetValue>
3276          <resetMask>0x3FF</resetMask>
3277          <fields>
3278            <field>
3279              <name>UP</name>
3280              <description>Number clock cycles delay needed after power domain power up</description>
3281              <bitRange>[9:0]</bitRange>
3282              <access>read-write</access>
3283            </field>
3284          </fields>
3285        </register>
3286        <register>
3287          <name>ECC_CTL</name>
3288          <description>ECC control</description>
3289          <addressOffset>0x10</addressOffset>
3290          <size>32</size>
3291          <access>read-write</access>
3292          <resetValue>0x0</resetValue>
3293          <resetMask>0xFE001FFF</resetMask>
3294          <fields>
3295            <field>
3296              <name>WORD_ADDR</name>
3297              <description>Specifies the word address where the parity is injected.
3298- On a 32-bit write access to this SRAM address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected.</description>
3299              <bitRange>[12:0]</bitRange>
3300              <access>read-write</access>
3301            </field>
3302            <field>
3303              <name>PARITY</name>
3304              <description>ECC parity to use for ECC error injection at address WORD_ADDR.</description>
3305              <bitRange>[31:25]</bitRange>
3306              <access>read-write</access>
3307            </field>
3308          </fields>
3309        </register>
3310        <register>
3311          <name>ERROR_STATUS0</name>
3312          <description>Error status 0</description>
3313          <addressOffset>0x20</addressOffset>
3314          <size>32</size>
3315          <access>read-only</access>
3316          <resetValue>0x0</resetValue>
3317          <resetMask>0x0</resetMask>
3318          <fields>
3319            <field>
3320              <name>DATA32</name>
3321              <description>Specifies error description information.
3322- For INSTR_OPC_ERROR/ INSTR_CC_ERROR/ INSTR_DEV_KEY_ERROR:
3323  - Violating instruction (from instruction FIFO).
3324- For BUS_ERROR:
3325  - Violating transfer, address.</description>
3326              <bitRange>[31:0]</bitRange>
3327              <access>read-only</access>
3328            </field>
3329          </fields>
3330        </register>
3331        <register>
3332          <name>ERROR_STATUS1</name>
3333          <description>Error status 1</description>
3334          <addressOffset>0x24</addressOffset>
3335          <size>32</size>
3336          <access>read-write</access>
3337          <resetValue>0x0</resetValue>
3338          <resetMask>0x80000000</resetMask>
3339          <fields>
3340            <field>
3341              <name>DATA24</name>
3342              <description>Specifies error description information.
3343- For BUS_ERROR:
3344  - Violating transfer, read attribute (DATA[0]).
3345  - Violating transfer, size attribute (DATA[5:4]). '0': 8-bit transfer, '1': 16 bits transfer, '2': 32-bit transfer.</description>
3346              <bitRange>[23:0]</bitRange>
3347              <access>read-only</access>
3348            </field>
3349            <field>
3350              <name>IDX</name>
3351              <description>Error source:
3352'0': INSTR_OPC_ERROR (instruction FIFO decoder error).
3353'1': INSTR_CC_ERROR (instruction FIFO decoder, VU CC error).
3354'2': BUS_ERROR (bus master interface AHB-Lite bus error).
3355'3': TR_AP_DETECT_ERROR.
3356'4': TR_RC_DETECT_ERROR.
3357'5': INSTR_DEV_KEY_ERROR.
3358'6'-'7': Undefined.</description>
3359              <bitRange>[26:24]</bitRange>
3360              <access>read-only</access>
3361            </field>
3362            <field>
3363              <name>VALID</name>
3364              <description>Specifies if ERROR_STATUS0 and ERROR_STATUS1 specify valid error information. No new error information is captured as long as VALID is '1'; i.e. the error information of the first detected error is NOT overwritten.</description>
3365              <bitRange>[31:31]</bitRange>
3366              <access>read-write</access>
3367            </field>
3368          </fields>
3369        </register>
3370        <register>
3371          <name>INTR</name>
3372          <description>Interrupt register</description>
3373          <addressOffset>0x100</addressOffset>
3374          <size>32</size>
3375          <access>read-write</access>
3376          <resetValue>0x0</resetValue>
3377          <resetMask>0x3F001F</resetMask>
3378          <fields>
3379            <field>
3380              <name>INSTR_FF_LEVEL</name>
3381              <description>This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO event is activated.</description>
3382              <bitRange>[0:0]</bitRange>
3383              <access>read-write</access>
3384            </field>
3385            <field>
3386              <name>INSTR_FF_OVERFLOW</name>
3387              <description>This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO overflows (an attempt is made to write to a full FIFO).</description>
3388              <bitRange>[1:1]</bitRange>
3389              <access>read-write</access>
3390            </field>
3391            <field>
3392              <name>TR_INITIALIZED</name>
3393              <description>This interrupt cause is activated (HW sets the field to '1') when the true random number generator is initialized.</description>
3394              <bitRange>[2:2]</bitRange>
3395              <access>read-write</access>
3396            </field>
3397            <field>
3398              <name>TR_DATA_AVAILABLE</name>
3399              <description>This interrupt cause is activated (HW sets the field to '1') when the true random number generator has generated a data value of the specified bit size.</description>
3400              <bitRange>[3:3]</bitRange>
3401              <access>read-write</access>
3402            </field>
3403            <field>
3404              <name>PR_DATA_AVAILABLE</name>
3405              <description>This interrupt cause is activated (HW sets the field to '1') when the pseudo random number generator has generated a data value.</description>
3406              <bitRange>[4:4]</bitRange>
3407              <access>read-write</access>
3408            </field>
3409            <field>
3410              <name>INSTR_OPC_ERROR</name>
3411              <description>This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined operation code (opcode).
3412
3413When the interrupt cause is activated, HW sets INSTR_FF_CTL.CLEAR to '1'.</description>
3414              <bitRange>[16:16]</bitRange>
3415              <access>read-write</access>
3416            </field>
3417            <field>
3418              <name>INSTR_CC_ERROR</name>
3419              <description>This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined condition code. This error is only generated for VU instructions.
3420
3421When the interrupt cause is activated, HW sets INSTR_FF_CTL.CLEAR to '1'.</description>
3422              <bitRange>[17:17]</bitRange>
3423              <access>read-write</access>
3424            </field>
3425            <field>
3426              <name>BUS_ERROR</name>
3427              <description>This interrupt cause is activated (HW sets the field to '1') when a AHB-Lite bus error is observed on the AHB-Lite master interface.
3428
3429When the interrupt cause is activated, HW sets INSTR_FF_CTL.CLEAR to '1'.</description>
3430              <bitRange>[18:18]</bitRange>
3431              <access>read-write</access>
3432            </field>
3433            <field>
3434              <name>TR_AP_DETECT_ERROR</name>
3435              <description>This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a repetition of a specific bit value.</description>
3436              <bitRange>[19:19]</bitRange>
3437              <access>read-write</access>
3438            </field>
3439            <field>
3440              <name>TR_RC_DETECT_ERROR</name>
3441              <description>This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a disproportionate occurrence of a specific bit value.</description>
3442              <bitRange>[20:20]</bitRange>
3443              <access>read-write</access>
3444            </field>
3445            <field>
3446              <name>INSTR_DEV_KEY_ERROR</name>
3447              <description>This interrupt cause is activated (HW sets the field to '1') when the LOAD_DEV_KEY instruction tries to load a device key whose DEV_KEY_ADDR_CTL.VALID or DEV_KEY_CTL.ALLOWED is set to '0'.</description>
3448              <bitRange>[21:21]</bitRange>
3449              <access>read-write</access>
3450            </field>
3451          </fields>
3452        </register>
3453        <register>
3454          <name>INTR_SET</name>
3455          <description>Interrupt set register</description>
3456          <addressOffset>0x104</addressOffset>
3457          <size>32</size>
3458          <access>read-write</access>
3459          <resetValue>0x0</resetValue>
3460          <resetMask>0x3F001F</resetMask>
3461          <fields>
3462            <field>
3463              <name>INSTR_FF_LEVEL</name>
3464              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3465              <bitRange>[0:0]</bitRange>
3466              <access>read-write</access>
3467            </field>
3468            <field>
3469              <name>INSTR_FF_OVERFLOW</name>
3470              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3471              <bitRange>[1:1]</bitRange>
3472              <access>read-write</access>
3473            </field>
3474            <field>
3475              <name>TR_INITIALIZED</name>
3476              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3477              <bitRange>[2:2]</bitRange>
3478              <access>read-write</access>
3479            </field>
3480            <field>
3481              <name>TR_DATA_AVAILABLE</name>
3482              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3483              <bitRange>[3:3]</bitRange>
3484              <access>read-write</access>
3485            </field>
3486            <field>
3487              <name>PR_DATA_AVAILABLE</name>
3488              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3489              <bitRange>[4:4]</bitRange>
3490              <access>read-write</access>
3491            </field>
3492            <field>
3493              <name>INSTR_OPC_ERROR</name>
3494              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3495              <bitRange>[16:16]</bitRange>
3496              <access>read-write</access>
3497            </field>
3498            <field>
3499              <name>INSTR_CC_ERROR</name>
3500              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3501              <bitRange>[17:17]</bitRange>
3502              <access>read-write</access>
3503            </field>
3504            <field>
3505              <name>BUS_ERROR</name>
3506              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3507              <bitRange>[18:18]</bitRange>
3508              <access>read-write</access>
3509            </field>
3510            <field>
3511              <name>TR_AP_DETECT_ERROR</name>
3512              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3513              <bitRange>[19:19]</bitRange>
3514              <access>read-write</access>
3515            </field>
3516            <field>
3517              <name>TR_RC_DETECT_ERROR</name>
3518              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3519              <bitRange>[20:20]</bitRange>
3520              <access>read-write</access>
3521            </field>
3522            <field>
3523              <name>INSTR_DEV_KEY_ERROR</name>
3524              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3525              <bitRange>[21:21]</bitRange>
3526              <access>read-write</access>
3527            </field>
3528          </fields>
3529        </register>
3530        <register>
3531          <name>INTR_MASK</name>
3532          <description>Interrupt mask register</description>
3533          <addressOffset>0x108</addressOffset>
3534          <size>32</size>
3535          <access>read-write</access>
3536          <resetValue>0x0</resetValue>
3537          <resetMask>0x3F001F</resetMask>
3538          <fields>
3539            <field>
3540              <name>INSTR_FF_LEVEL</name>
3541              <description>Mask bit for corresponding field in interrupt request register.</description>
3542              <bitRange>[0:0]</bitRange>
3543              <access>read-write</access>
3544            </field>
3545            <field>
3546              <name>INSTR_FF_OVERFLOW</name>
3547              <description>Mask bit for corresponding field in interrupt request register.</description>
3548              <bitRange>[1:1]</bitRange>
3549              <access>read-write</access>
3550            </field>
3551            <field>
3552              <name>TR_INITIALIZED</name>
3553              <description>Mask bit for corresponding field in interrupt request register.</description>
3554              <bitRange>[2:2]</bitRange>
3555              <access>read-write</access>
3556            </field>
3557            <field>
3558              <name>TR_DATA_AVAILABLE</name>
3559              <description>Mask bit for corresponding field in interrupt request register.</description>
3560              <bitRange>[3:3]</bitRange>
3561              <access>read-write</access>
3562            </field>
3563            <field>
3564              <name>PR_DATA_AVAILABLE</name>
3565              <description>Mask bit for corresponding field in interrupt request register.</description>
3566              <bitRange>[4:4]</bitRange>
3567              <access>read-write</access>
3568            </field>
3569            <field>
3570              <name>INSTR_OPC_ERROR</name>
3571              <description>Mask bit for corresponding field in interrupt request register.</description>
3572              <bitRange>[16:16]</bitRange>
3573              <access>read-write</access>
3574            </field>
3575            <field>
3576              <name>INSTR_CC_ERROR</name>
3577              <description>Mask bit for corresponding field in interrupt request register.</description>
3578              <bitRange>[17:17]</bitRange>
3579              <access>read-write</access>
3580            </field>
3581            <field>
3582              <name>BUS_ERROR</name>
3583              <description>Mask bit for corresponding field in interrupt request register.</description>
3584              <bitRange>[18:18]</bitRange>
3585              <access>read-write</access>
3586            </field>
3587            <field>
3588              <name>TR_AP_DETECT_ERROR</name>
3589              <description>Mask bit for corresponding field in interrupt request register.</description>
3590              <bitRange>[19:19]</bitRange>
3591              <access>read-write</access>
3592            </field>
3593            <field>
3594              <name>TR_RC_DETECT_ERROR</name>
3595              <description>Mask bit for corresponding field in interrupt request register.</description>
3596              <bitRange>[20:20]</bitRange>
3597              <access>read-write</access>
3598            </field>
3599            <field>
3600              <name>INSTR_DEV_KEY_ERROR</name>
3601              <description>Mask bit for corresponding field in interrupt request register.</description>
3602              <bitRange>[21:21]</bitRange>
3603              <access>read-write</access>
3604            </field>
3605          </fields>
3606        </register>
3607        <register>
3608          <name>INTR_MASKED</name>
3609          <description>Interrupt masked register</description>
3610          <addressOffset>0x10C</addressOffset>
3611          <size>32</size>
3612          <access>read-only</access>
3613          <resetValue>0x0</resetValue>
3614          <resetMask>0x3F001F</resetMask>
3615          <fields>
3616            <field>
3617              <name>INSTR_FF_LEVEL</name>
3618              <description>Logical and of corresponding request and mask bits.</description>
3619              <bitRange>[0:0]</bitRange>
3620              <access>read-only</access>
3621            </field>
3622            <field>
3623              <name>INSTR_FF_OVERFLOW</name>
3624              <description>Logical and of corresponding request and mask bits.</description>
3625              <bitRange>[1:1]</bitRange>
3626              <access>read-only</access>
3627            </field>
3628            <field>
3629              <name>TR_INITIALIZED</name>
3630              <description>Logical and of corresponding request and mask bits.</description>
3631              <bitRange>[2:2]</bitRange>
3632              <access>read-only</access>
3633            </field>
3634            <field>
3635              <name>TR_DATA_AVAILABLE</name>
3636              <description>Logical and of corresponding request and mask bits.</description>
3637              <bitRange>[3:3]</bitRange>
3638              <access>read-only</access>
3639            </field>
3640            <field>
3641              <name>PR_DATA_AVAILABLE</name>
3642              <description>Logical and of corresponding request and mask bits.</description>
3643              <bitRange>[4:4]</bitRange>
3644              <access>read-only</access>
3645            </field>
3646            <field>
3647              <name>INSTR_OPC_ERROR</name>
3648              <description>Logical and of corresponding request and mask bits.</description>
3649              <bitRange>[16:16]</bitRange>
3650              <access>read-only</access>
3651            </field>
3652            <field>
3653              <name>INSTR_CC_ERROR</name>
3654              <description>Logical and of corresponding request and mask bits.</description>
3655              <bitRange>[17:17]</bitRange>
3656              <access>read-only</access>
3657            </field>
3658            <field>
3659              <name>BUS_ERROR</name>
3660              <description>Logical and of corresponding request and mask bits.</description>
3661              <bitRange>[18:18]</bitRange>
3662              <access>read-only</access>
3663            </field>
3664            <field>
3665              <name>TR_AP_DETECT_ERROR</name>
3666              <description>Logical and of corresponding request and mask bits.</description>
3667              <bitRange>[19:19]</bitRange>
3668              <access>read-only</access>
3669            </field>
3670            <field>
3671              <name>TR_RC_DETECT_ERROR</name>
3672              <description>Logical and of corresponding request and mask bits.</description>
3673              <bitRange>[20:20]</bitRange>
3674              <access>read-only</access>
3675            </field>
3676            <field>
3677              <name>INSTR_DEV_KEY_ERROR</name>
3678              <description>Logical and of corresponding request and mask bits.</description>
3679              <bitRange>[21:21]</bitRange>
3680              <access>read-only</access>
3681            </field>
3682          </fields>
3683        </register>
3684        <register>
3685          <name>PR_LFSR_CTL0</name>
3686          <description>Pseudo random LFSR control 0</description>
3687          <addressOffset>0x200</addressOffset>
3688          <size>32</size>
3689          <access>read-write</access>
3690          <resetValue>0xD8959BC9</resetValue>
3691          <resetMask>0xFFFFFFFF</resetMask>
3692          <fields>
3693            <field>
3694              <name>LFSR32</name>
3695              <description>State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. This register needs to be initialized by SW. The initialization value should be different from '0'.
3696
3697The three PR_LFSR_CTL registers represents the state of a 32-bit, 31-bit and 29-bit LFSR. Individually, these LFSRs generate a pseudo random bit sequence that repeats itself after (2^32)-1, (2^31)-1 and (2^29)-1 bits. The numbers (2^32)-1, (2^31)-1 and (2^29)-1 are relatively prime (their greatest common denominator is '1'). The three bit sequence are combined (XOR'd) into a single bitstream to create a pseudo random bit sequence that repeats itself after ((2^32)-1) * ((2^31)-1) * ((2*29)-1) bits.
3698
3699The following polynomials are used:
3700- 32-bit irreducible polynomial: x^32+x^30+x^26+x^25+1.
3701- 31-bit irreducible polynomial: x^31+x^28+1.
3702- 29-bit irreducible polynomial: x^29+x^27+1.</description>
3703              <bitRange>[31:0]</bitRange>
3704              <access>read-write</access>
3705            </field>
3706          </fields>
3707        </register>
3708        <register>
3709          <name>PR_LFSR_CTL1</name>
3710          <description>Pseudo random LFSR control 1</description>
3711          <addressOffset>0x204</addressOffset>
3712          <size>32</size>
3713          <access>read-write</access>
3714          <resetValue>0x2BB911F8</resetValue>
3715          <resetMask>0x7FFFFFFF</resetMask>
3716          <fields>
3717            <field>
3718              <name>LFSR31</name>
3719              <description>State of a 31-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0.</description>
3720              <bitRange>[30:0]</bitRange>
3721              <access>read-write</access>
3722            </field>
3723          </fields>
3724        </register>
3725        <register>
3726          <name>PR_LFSR_CTL2</name>
3727          <description>Pseudo random LFSR control 2</description>
3728          <addressOffset>0x208</addressOffset>
3729          <size>32</size>
3730          <access>read-write</access>
3731          <resetValue>0x60C31B7</resetValue>
3732          <resetMask>0x1FFFFFFF</resetMask>
3733          <fields>
3734            <field>
3735              <name>LFSR29</name>
3736              <description>State of a 29-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0.</description>
3737              <bitRange>[28:0]</bitRange>
3738              <access>read-write</access>
3739            </field>
3740          </fields>
3741        </register>
3742        <register>
3743          <name>PR_MAX_CTL</name>
3744          <description>Pseudo random maximum control</description>
3745          <addressOffset>0x20C</addressOffset>
3746          <size>32</size>
3747          <access>read-write</access>
3748          <resetValue>0xFFFFFFFF</resetValue>
3749          <resetMask>0xFFFFFFFF</resetMask>
3750          <fields>
3751            <field>
3752              <name>DATA32</name>
3753              <description>Maximum value of to be generated random number</description>
3754              <bitRange>[31:0]</bitRange>
3755              <access>read-write</access>
3756            </field>
3757          </fields>
3758        </register>
3759        <register>
3760          <name>PR_CMD</name>
3761          <description>Pseudo random command</description>
3762          <addressOffset>0x210</addressOffset>
3763          <size>32</size>
3764          <access>read-write</access>
3765          <resetValue>0x0</resetValue>
3766          <resetMask>0x1</resetMask>
3767          <fields>
3768            <field>
3769              <name>START</name>
3770              <description>Pseudo random command. On a generated number, HW sets this field to '0' and sets INTR.PR_DATA_AVAILABLE to '1.</description>
3771              <bitRange>[0:0]</bitRange>
3772              <access>read-write</access>
3773            </field>
3774          </fields>
3775        </register>
3776        <register>
3777          <name>PR_RESULT</name>
3778          <description>Pseudo random result</description>
3779          <addressOffset>0x218</addressOffset>
3780          <size>32</size>
3781          <access>read-write</access>
3782          <resetValue>0x0</resetValue>
3783          <resetMask>0xFFFFFFFF</resetMask>
3784          <fields>
3785            <field>
3786              <name>DATA32</name>
3787              <description>Result of a pseudo random number generation operation. The resulting value DATA is in the range [0, PR_MAX_CTL.DATA32]. The PR_DATA_AVAILABLE interrupt cause is activated when the number is generated.
3788
3789Note that SW can write this field. This functionality can be used prevent information leakage.</description>
3790              <bitRange>[31:0]</bitRange>
3791              <access>read-write</access>
3792            </field>
3793          </fields>
3794        </register>
3795        <register>
3796          <name>TR_CTL0</name>
3797          <description>True random control 0</description>
3798          <addressOffset>0x280</addressOffset>
3799          <size>32</size>
3800          <access>read-write</access>
3801          <resetValue>0x30000</resetValue>
3802          <resetMask>0x31FFFFFF</resetMask>
3803          <fields>
3804            <field>
3805              <name>SAMPLE_CLOCK_DIV</name>
3806              <description>Specifies the clock divider that is used to sample oscillator data. This clock divider is wrt. 'clk_sys'.
3807'0': sample clock is 'clk_sys'.
3808'1': sample clock is 'clk_sys'/2.
3809...
3810'255': sample clock is 'clk_sys'/256.</description>
3811              <bitRange>[7:0]</bitRange>
3812              <access>read-write</access>
3813            </field>
3814            <field>
3815              <name>RED_CLOCK_DIV</name>
3816              <description>Specifies the clock divider that is used to produce reduced bits.
3817'0': 1 reduced bit is produced for each sample.
3818'1': 1 reduced bit is produced for each 2 samples.
3819...
3820'255': 1 reduced bit is produced for each 256 samples.
3821
3822The reduced bits are considered random bits and shifted into TR_RESULT0.DATA32.</description>
3823              <bitRange>[15:8]</bitRange>
3824              <access>read-write</access>
3825            </field>
3826            <field>
3827              <name>INIT_DELAY</name>
3828              <description>Specifies an initialization delay: number of removed/dropped samples before reduced bits are generated. This field should be programmed in the range [1, 255]. After starting the oscillators, at least the first 2 samples should be removed/dropped to clear the state of internal synchronizers. In addition, it is advised to drop at least the second 2 samples from the oscillators (to circumvent the semi-predictable oscillator startup behavior). This result in the default field value of '3'. Field encoding is as follows:
3829'0': 1 sample is dropped.
3830'1': 2 samples are dropped.
3831...
3832'255': 256 samples are dropped.
3833
3834The TR_INITIALIZED interrupt cause is set to '1', when the initialization delay is passed.</description>
3835              <bitRange>[23:16]</bitRange>
3836              <access>read-write</access>
3837            </field>
3838            <field>
3839              <name>VON_NEUMANN_CORR</name>
3840              <description>Specifies if the 'von Neumann corrector' is disabled or enabled:
3841'0': disabled.
3842'1': enabled.
3843The 'von Neumann corrector' post-processes the reduced bits to remove a '0' or '1' bias. The corrector operates on reduced bit pairs ('oldest bit, newest bit'):
3844'00': no bit is produced.
3845'01': '0' bit is produced (oldest bit).
3846'10': '1' bit is produced (oldest bit).
3847'11': no bit is produced.
3848Note that the corrector produces bits at a random pace and at a frequency that is 1/4 of the reduced bit frequency (reduced bits are processed in pairs, and half of the pairs do NOT produce a bit).</description>
3849              <bitRange>[24:24]</bitRange>
3850              <access>read-write</access>
3851            </field>
3852            <field>
3853              <name>STOP_ON_AP_DETECT</name>
3854              <description>Specifies if TRNG functionality is stopped on an adaptive proportion test detection (when HW sets INTR.TR_AP_DETECT to '1'):
3855'0': Functionality is NOT stopped.
3856'1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW).</description>
3857              <bitRange>[28:28]</bitRange>
3858              <access>read-write</access>
3859            </field>
3860            <field>
3861              <name>STOP_ON_RC_DETECT</name>
3862              <description>Specifies if TRNG functionality is stopped on a repetition count test detection (when HW sets INTR.TR_RC_DETECT to '1'):
3863'0': Functionality is NOT stopped.
3864'1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW).</description>
3865              <bitRange>[29:29]</bitRange>
3866              <access>read-write</access>
3867            </field>
3868          </fields>
3869        </register>
3870        <register>
3871          <name>TR_CTL1</name>
3872          <description>True random control 1</description>
3873          <addressOffset>0x284</addressOffset>
3874          <size>32</size>
3875          <access>read-write</access>
3876          <resetValue>0x0</resetValue>
3877          <resetMask>0x3F</resetMask>
3878          <fields>
3879            <field>
3880              <name>RO11_EN</name>
3881              <description>FW sets this field to '1' to enable the ring oscillator with 11 inverters.</description>
3882              <bitRange>[0:0]</bitRange>
3883              <access>read-write</access>
3884            </field>
3885            <field>
3886              <name>RO15_EN</name>
3887              <description>FW sets this field to '1' to enable the ring oscillator with 15 inverters.</description>
3888              <bitRange>[1:1]</bitRange>
3889              <access>read-write</access>
3890            </field>
3891            <field>
3892              <name>GARO15_EN</name>
3893              <description>FW sets this field to '1' to enable the fixed Galois ring oscillator with 15 inverters.</description>
3894              <bitRange>[2:2]</bitRange>
3895              <access>read-write</access>
3896            </field>
3897            <field>
3898              <name>GARO31_EN</name>
3899              <description>FW sets this field to '1' to enable the programmable Galois ring oscillator with up to 31 inverters. The TR_GARO_CTL register specifies the programmable polynomial.</description>
3900              <bitRange>[3:3]</bitRange>
3901              <access>read-write</access>
3902            </field>
3903            <field>
3904              <name>FIRO15_EN</name>
3905              <description>FW sets this field to '1' to enable the fixed Fibonacci ring oscillator with 15 inverters.</description>
3906              <bitRange>[4:4]</bitRange>
3907              <access>read-write</access>
3908            </field>
3909            <field>
3910              <name>FIRO31_EN</name>
3911              <description>FW sets this field to '1' to enable the programmable Fibonacci ring oscillator with up to 31 inverters. The TR_FIRO_CTL register specifies the programmable polynomial.</description>
3912              <bitRange>[5:5]</bitRange>
3913              <access>read-write</access>
3914            </field>
3915          </fields>
3916        </register>
3917        <register>
3918          <name>TR_CTL2</name>
3919          <description>True random control 2</description>
3920          <addressOffset>0x288</addressOffset>
3921          <size>32</size>
3922          <access>read-write</access>
3923          <resetValue>0x0</resetValue>
3924          <resetMask>0x3F</resetMask>
3925          <fields>
3926            <field>
3927              <name>SIZE</name>
3928              <description>Bit size of generated random number in TR_RESULT. Legal range is in [0, 32].</description>
3929              <bitRange>[5:0]</bitRange>
3930              <access>read-write</access>
3931            </field>
3932          </fields>
3933        </register>
3934        <register>
3935          <name>TR_STATUS</name>
3936          <description>True random status</description>
3937          <addressOffset>0x28C</addressOffset>
3938          <size>32</size>
3939          <access>read-only</access>
3940          <resetValue>0x0</resetValue>
3941          <resetMask>0x1</resetMask>
3942          <fields>
3943            <field>
3944              <name>INITIALIZED</name>
3945              <description>Reflects the state of the true random number generator:
3946'0': Not initialized (TR_CTL0.INIT_DELAY has NOT passed).
3947'1': Initialized (TR_CTL0.INIT_DELAY has passed).</description>
3948              <bitRange>[0:0]</bitRange>
3949              <access>read-only</access>
3950            </field>
3951          </fields>
3952        </register>
3953        <register>
3954          <name>TR_CMD</name>
3955          <description>True random command</description>
3956          <addressOffset>0x290</addressOffset>
3957          <size>32</size>
3958          <access>read-write</access>
3959          <resetValue>0x0</resetValue>
3960          <resetMask>0x1</resetMask>
3961          <fields>
3962            <field>
3963              <name>START</name>
3964              <description>True random command. On completion of the command, HW sets this field to '0' and sets INTR.TR_DATA_AVAILABLE to '1 when:
3965- A random number is generated in TR_RESULT.
3966- All ring oscillators are off (per TR_CTL1).
3967- A repetition count (RC) or adaptive proportion (AP) error is detected during the random number generation (INTR.TR_RC/AP_DETECT_ERROR).
3968
3969Note: On completion of the command, SW should check TR_CTL1 and INTR.TR_RC/AP_DETECT_ERROR to ensure that no unexpected error occurred during random number generation.</description>
3970              <bitRange>[0:0]</bitRange>
3971              <access>read-write</access>
3972            </field>
3973          </fields>
3974        </register>
3975        <register>
3976          <name>TR_RESULT</name>
3977          <description>True random result</description>
3978          <addressOffset>0x298</addressOffset>
3979          <size>32</size>
3980          <access>read-write</access>
3981          <resetValue>0x0</resetValue>
3982          <resetMask>0xFFFFFFFF</resetMask>
3983          <fields>
3984            <field>
3985              <name>DATA32</name>
3986              <description>Generated true random number. HW generates the number in the least significant bit positions (TR_CTL2.SIZE) of this field. The TR_DATA_AVAILABLE interrupt cause is activated when the number is generated.
3987
3988Note that SW can write this field. This functionality can be used prevent information leakage.</description>
3989              <bitRange>[31:0]</bitRange>
3990              <access>read-write</access>
3991            </field>
3992          </fields>
3993        </register>
3994        <register>
3995          <name>TR_GARO_CTL</name>
3996          <description>True random GARO control</description>
3997          <addressOffset>0x2A0</addressOffset>
3998          <size>32</size>
3999          <access>read-write</access>
4000          <resetValue>0x0</resetValue>
4001          <resetMask>0x7FFFFFFF</resetMask>
4002          <fields>
4003            <field>
4004              <name>POLYNOMIAL31</name>
4005              <description>Polynomial for programmable Galois ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's.</description>
4006              <bitRange>[30:0]</bitRange>
4007              <access>read-write</access>
4008            </field>
4009          </fields>
4010        </register>
4011        <register>
4012          <name>TR_FIRO_CTL</name>
4013          <description>True random FIRO control</description>
4014          <addressOffset>0x2A4</addressOffset>
4015          <size>32</size>
4016          <access>read-write</access>
4017          <resetValue>0x0</resetValue>
4018          <resetMask>0x7FFFFFFF</resetMask>
4019          <fields>
4020            <field>
4021              <name>POLYNOMIAL31</name>
4022              <description>Polynomial for programmable Fibonacci ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's.</description>
4023              <bitRange>[30:0]</bitRange>
4024              <access>read-write</access>
4025            </field>
4026          </fields>
4027        </register>
4028        <register>
4029          <name>TR_MON_CTL</name>
4030          <description>True random monitor control</description>
4031          <addressOffset>0x2C0</addressOffset>
4032          <size>32</size>
4033          <access>read-write</access>
4034          <resetValue>0x2</resetValue>
4035          <resetMask>0x3</resetMask>
4036          <fields>
4037            <field>
4038              <name>BITSTREAM_SEL</name>
4039              <description>Selection of the bitstream:
4040'0': DAS bitstream.
4041'1': RED bitstream.
4042'2': TR bitstream.
4043'3': Undefined.</description>
4044              <bitRange>[1:0]</bitRange>
4045              <access>read-write</access>
4046            </field>
4047          </fields>
4048        </register>
4049        <register>
4050          <name>TR_MON_CMD</name>
4051          <description>True random monitor command</description>
4052          <addressOffset>0x2C8</addressOffset>
4053          <size>32</size>
4054          <access>read-write</access>
4055          <resetValue>0x0</resetValue>
4056          <resetMask>0x3</resetMask>
4057          <fields>
4058            <field>
4059              <name>START_AP</name>
4060              <description>Adaptive proportion (AP) test enable:
4061'0': Stopped.
4062'1': Started.
4063
4064On a AP detection, HW sets this field to '0' and sets INTR.TR_AP_DETECT to '1.</description>
4065              <bitRange>[0:0]</bitRange>
4066              <access>read-write</access>
4067            </field>
4068            <field>
4069              <name>START_RC</name>
4070              <description>Repetition count (RC) test enable:
4071'0': Disabled.
4072'1': Enabled.
4073
4074On a RC detection, HW sets this field to '0' and sets INTR.TR_RC_DETECT to '1.</description>
4075              <bitRange>[1:1]</bitRange>
4076              <access>read-write</access>
4077            </field>
4078          </fields>
4079        </register>
4080        <register>
4081          <name>TR_MON_RC_CTL</name>
4082          <description>True random monitor RC control</description>
4083          <addressOffset>0x2D0</addressOffset>
4084          <size>32</size>
4085          <access>read-write</access>
4086          <resetValue>0xFF</resetValue>
4087          <resetMask>0xFF</resetMask>
4088          <fields>
4089            <field>
4090              <name>CUTOFF_COUNT8</name>
4091              <description>Cutoff count (legal range is [1, 255]):
4092'0': Illegal.
4093'1': 1 repetition.
4094...
4095'255': 255 repetitions.</description>
4096              <bitRange>[7:0]</bitRange>
4097              <access>read-write</access>
4098            </field>
4099          </fields>
4100        </register>
4101        <register>
4102          <name>TR_MON_RC_STATUS0</name>
4103          <description>True random monitor RC status 0</description>
4104          <addressOffset>0x2D8</addressOffset>
4105          <size>32</size>
4106          <access>read-only</access>
4107          <resetValue>0x0</resetValue>
4108          <resetMask>0x1</resetMask>
4109          <fields>
4110            <field>
4111              <name>BIT</name>
4112              <description>Current active bit value:
4113'0': '0'.
4114'1': '1'.
4115
4116This field is only valid when TR_MON_RC_STATUS1.REP_COUNT is NOT equal to '0'.</description>
4117              <bitRange>[0:0]</bitRange>
4118              <access>read-only</access>
4119            </field>
4120          </fields>
4121        </register>
4122        <register>
4123          <name>TR_MON_RC_STATUS1</name>
4124          <description>True random monitor RC status 1</description>
4125          <addressOffset>0x2DC</addressOffset>
4126          <size>32</size>
4127          <access>read-only</access>
4128          <resetValue>0x0</resetValue>
4129          <resetMask>0xFF</resetMask>
4130          <fields>
4131            <field>
4132              <name>REP_COUNT</name>
4133              <description>Number of repetitions of the current active bit counter:
4134'0': 0 repetitions.
4135...
4136'255': 255 repetitions.</description>
4137              <bitRange>[7:0]</bitRange>
4138              <access>read-only</access>
4139            </field>
4140          </fields>
4141        </register>
4142        <register>
4143          <name>TR_MON_AP_CTL</name>
4144          <description>True random monitor AP control</description>
4145          <addressOffset>0x2E0</addressOffset>
4146          <size>32</size>
4147          <access>read-write</access>
4148          <resetValue>0xFFFFFFFF</resetValue>
4149          <resetMask>0xFFFFFFFF</resetMask>
4150          <fields>
4151            <field>
4152              <name>CUTOFF_COUNT16</name>
4153              <description>Cutoff count (legal range is [1, 65535]).
4154'0': Illegal.
4155'1': 1 occurrence.
4156...
4157'65535': 65535 occurrences.</description>
4158              <bitRange>[15:0]</bitRange>
4159              <access>read-write</access>
4160            </field>
4161            <field>
4162              <name>WINDOW_SIZE</name>
4163              <description>Window size (minus 1) :
4164'0': 1 bit.
4165...
4166'65535': 65536 bits.</description>
4167              <bitRange>[31:16]</bitRange>
4168              <access>read-write</access>
4169            </field>
4170          </fields>
4171        </register>
4172        <register>
4173          <name>TR_MON_AP_STATUS0</name>
4174          <description>True random monitor AP status 0</description>
4175          <addressOffset>0x2E8</addressOffset>
4176          <size>32</size>
4177          <access>read-only</access>
4178          <resetValue>0x0</resetValue>
4179          <resetMask>0x1</resetMask>
4180          <fields>
4181            <field>
4182              <name>BIT</name>
4183              <description>Current active bit value:
4184'0': '0'.
4185'1': '1'.
4186
4187This field is only valid when TR_MON_AP_STATUS1.OCC_COUNT is NOT equal to '0'.</description>
4188              <bitRange>[0:0]</bitRange>
4189              <access>read-only</access>
4190            </field>
4191          </fields>
4192        </register>
4193        <register>
4194          <name>TR_MON_AP_STATUS1</name>
4195          <description>True random monitor AP status 1</description>
4196          <addressOffset>0x2EC</addressOffset>
4197          <size>32</size>
4198          <access>read-only</access>
4199          <resetValue>0x0</resetValue>
4200          <resetMask>0xFFFFFFFF</resetMask>
4201          <fields>
4202            <field>
4203              <name>OCC_COUNT</name>
4204              <description>Number of occurrences of the current active bit counter:
4205'0': 0 occurrences
4206...
4207'65535': 65535 occurrences</description>
4208              <bitRange>[15:0]</bitRange>
4209              <access>read-only</access>
4210            </field>
4211            <field>
4212              <name>WINDOW_INDEX</name>
4213              <description>Counter to keep track of the current index in the window (counts from '0' to TR_MON_AP_CTL.WINDOW_SIZE to '0').</description>
4214              <bitRange>[31:16]</bitRange>
4215              <access>read-only</access>
4216            </field>
4217          </fields>
4218        </register>
4219        <register>
4220          <name>STATUS</name>
4221          <description>Status</description>
4222          <addressOffset>0x1004</addressOffset>
4223          <size>32</size>
4224          <access>read-only</access>
4225          <resetValue>0x0</resetValue>
4226          <resetMask>0x80000000</resetMask>
4227          <fields>
4228            <field>
4229              <name>BUSY</name>
4230              <description>Reflects the state of the IP:
4231'0': Idle/no busy.
4232'1': Busy:
4233  - Instruction is pending in the instruction FIFO.
4234  - Instruction is busy in a IP component (e.g. SHA1, SHA2, SHA3, DES, TDES, AES, CHACHA, ...).
4235  - Store FIFO is busy.
4236  - TR or PR command is busy.</description>
4237              <bitRange>[31:31]</bitRange>
4238              <access>read-only</access>
4239            </field>
4240          </fields>
4241        </register>
4242        <register>
4243          <name>INSTR_FF_CTL</name>
4244          <description>Instruction FIFO control</description>
4245          <addressOffset>0x1040</addressOffset>
4246          <size>32</size>
4247          <access>read-write</access>
4248          <resetValue>0x20000</resetValue>
4249          <resetMask>0x30007</resetMask>
4250          <fields>
4251            <field>
4252              <name>EVENT_LEVEL</name>
4253              <description>Event level. When the number of entries in the instruction FIFO is less than the amount of this field, an event is generated:
4254- 'event' = INSTR_FF_STATUS.USED &lt; EVENT_LEVEL.</description>
4255              <bitRange>[2:0]</bitRange>
4256              <access>read-write</access>
4257            </field>
4258            <field>
4259              <name>CLEAR</name>
4260              <description>When '1', the instruction FIFO is cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.
4261
4262HW sets this field to '1' on when a INSTR_OPC_ERROR, INSTR_CC_ERROR or BUS_ERROR interrupt cause is activated.</description>
4263              <bitRange>[16:16]</bitRange>
4264              <access>read-write</access>
4265            </field>
4266            <field>
4267              <name>BLOCK</name>
4268              <description>This field specifies the behavior when an instruction is written to a full FIFO (INSTR_FIFO_WR MMIO register):
4269'0': The write is ignored/dropped and the INTR.INSTR_FF_OVERFLOW interrupt cause is set to '1'.
4270'1': The write is blocked, resulting in AHB-Lite wait states and the INTR.INSTR_FF_OVERFLOW interrupt cause is set to '1' (this cause may be masked out). The instruction is written to the FIFO as soon as a FIFO entry becomes available. The maximum time is roughly the time of the execution of the slowest/longest instruction. Note that this setting may 'lock up' /stall the CPU. When the CPU is 'locked up'/stalled it can not respond to any system interrupts. As a result, the interrupt latency is increased. Note that this may not be an issue if the associated CPU is only performing cryptography functionality, e.g. the CM0+ during boot time.</description>
4271              <bitRange>[17:17]</bitRange>
4272              <access>read-write</access>
4273            </field>
4274          </fields>
4275        </register>
4276        <register>
4277          <name>INSTR_FF_STATUS</name>
4278          <description>Instruction FIFO status</description>
4279          <addressOffset>0x1044</addressOffset>
4280          <size>32</size>
4281          <access>read-only</access>
4282          <resetValue>0x0</resetValue>
4283          <resetMask>0x1000F</resetMask>
4284          <fields>
4285            <field>
4286              <name>USED</name>
4287              <description>Number of instructions in the instruction FIFO. The value of this field ranges from 0 to 8.</description>
4288              <bitRange>[3:0]</bitRange>
4289              <access>read-only</access>
4290            </field>
4291            <field>
4292              <name>EVENT</name>
4293              <description>Instruction FIFO  event.</description>
4294              <bitRange>[16:16]</bitRange>
4295              <access>read-only</access>
4296            </field>
4297          </fields>
4298        </register>
4299        <register>
4300          <name>INSTR_FF_WR</name>
4301          <description>Instruction FIFO write</description>
4302          <addressOffset>0x1048</addressOffset>
4303          <size>32</size>
4304          <access>write-only</access>
4305          <resetValue>0x0</resetValue>
4306          <resetMask>0xFFFFFFFF</resetMask>
4307          <fields>
4308            <field>
4309              <name>DATA32</name>
4310              <description>Instruction or instruction operand data that is written to the instruction FIFO.</description>
4311              <bitRange>[31:0]</bitRange>
4312              <access>write-only</access>
4313            </field>
4314          </fields>
4315        </register>
4316        <register>
4317          <name>LOAD0_FF_STATUS</name>
4318          <description>Load 0 FIFO status</description>
4319          <addressOffset>0x10C0</addressOffset>
4320          <size>32</size>
4321          <access>read-only</access>
4322          <resetValue>0x0</resetValue>
4323          <resetMask>0x8000001F</resetMask>
4324          <fields>
4325            <field>
4326              <name>USED5</name>
4327              <description>Number of Bytes in the FIFO. The value of this field is in the range [0, 19].</description>
4328              <bitRange>[4:0]</bitRange>
4329              <access>read-only</access>
4330            </field>
4331            <field>
4332              <name>BUSY</name>
4333              <description>Reflects the state of the FIFO:
4334'0': FIFO load engine is idle and a new FIFO instruction can be accepted.
4335'1': FIFO load engine is busy and NO new FIFO instruction can be accepted.</description>
4336              <bitRange>[31:31]</bitRange>
4337              <access>read-only</access>
4338            </field>
4339          </fields>
4340        </register>
4341        <register>
4342          <name>LOAD1_FF_STATUS</name>
4343          <description>Load 1 FIFO status</description>
4344          <addressOffset>0x10D0</addressOffset>
4345          <size>32</size>
4346          <access>read-only</access>
4347          <resetValue>0x0</resetValue>
4348          <resetMask>0x8000001F</resetMask>
4349          <fields>
4350            <field>
4351              <name>USED5</name>
4352              <description>See LOAD1_FF_STATUS.USED.</description>
4353              <bitRange>[4:0]</bitRange>
4354              <access>read-only</access>
4355            </field>
4356            <field>
4357              <name>BUSY</name>
4358              <description>See LOAD1_FF_STATUS.BUSY.</description>
4359              <bitRange>[31:31]</bitRange>
4360              <access>read-only</access>
4361            </field>
4362          </fields>
4363        </register>
4364        <register>
4365          <name>STORE_FF_STATUS</name>
4366          <description>Store FIFO status</description>
4367          <addressOffset>0x10F0</addressOffset>
4368          <size>32</size>
4369          <access>read-only</access>
4370          <resetValue>0x0</resetValue>
4371          <resetMask>0x8000001F</resetMask>
4372          <fields>
4373            <field>
4374              <name>USED5</name>
4375              <description>Number of Bytes in the FIFO. The value of this field is in the range [0, 16].</description>
4376              <bitRange>[4:0]</bitRange>
4377              <access>read-only</access>
4378            </field>
4379            <field>
4380              <name>BUSY</name>
4381              <description>Reflects the state of the FIFO:
4382'0': FIFO store engine is idle and a new FIFO instruction can be accepted (USED is '0').
4383'1': FIFO store engine is busy and NO new FIFO instruction can be accepted.</description>
4384              <bitRange>[31:31]</bitRange>
4385              <access>read-only</access>
4386            </field>
4387          </fields>
4388        </register>
4389        <register>
4390          <name>AES_CTL</name>
4391          <description>AES control</description>
4392          <addressOffset>0x1100</addressOffset>
4393          <size>32</size>
4394          <access>read-write</access>
4395          <resetValue>0x0</resetValue>
4396          <resetMask>0x3</resetMask>
4397          <fields>
4398            <field>
4399              <name>KEY_SIZE</name>
4400              <description>AES key size:
4401'0': 128-bit key, 10 rounds AES (inverse) cipher operation.
4402'1': 192-bit key, 12 rounds AES (inverse) cipher operation.
4403'2': 256-bit key, 14 rounds AES (inverse) cipher operation.
4404'3': Undefined</description>
4405              <bitRange>[1:0]</bitRange>
4406              <access>read-write</access>
4407              <enumeratedValues>
4408                <enumeratedValue>
4409                  <name>AES128</name>
4410                  <description>N/A</description>
4411                  <value>0</value>
4412                </enumeratedValue>
4413                <enumeratedValue>
4414                  <name>AES192</name>
4415                  <description>N/A</description>
4416                  <value>1</value>
4417                </enumeratedValue>
4418                <enumeratedValue>
4419                  <name>AES256</name>
4420                  <description>N/A</description>
4421                  <value>2</value>
4422                </enumeratedValue>
4423              </enumeratedValues>
4424            </field>
4425          </fields>
4426        </register>
4427        <register>
4428          <name>RESULT</name>
4429          <description>Result</description>
4430          <addressOffset>0x1180</addressOffset>
4431          <size>32</size>
4432          <access>read-write</access>
4433          <resetValue>0x0</resetValue>
4434          <resetMask>0xFFFFFFFF</resetMask>
4435          <fields>
4436            <field>
4437              <name>DATA</name>
4438              <description>BLOCK_CMP operation (DATA[0]):
4439'0': source 0 equals source 1.
4440'1': source 0 does NOT equal source 1.
4441
4442CRC operation (DATA[31:0]). State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value.
4443
4444The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's.
4445
4446Note that SW can write this field. This functionality can be used prevent information leakage.</description>
4447              <bitRange>[31:0]</bitRange>
4448              <access>read-write</access>
4449            </field>
4450          </fields>
4451        </register>
4452        <register>
4453          <name>CRC_CTL</name>
4454          <description>CRC control</description>
4455          <addressOffset>0x1400</addressOffset>
4456          <size>32</size>
4457          <access>read-write</access>
4458          <resetValue>0x0</resetValue>
4459          <resetMask>0x101</resetMask>
4460          <fields>
4461            <field>
4462              <name>DATA_REVERSE</name>
4463              <description>Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):
4464'0': Most significant bit (bit 1) first.
4465'1': Least significant bit (bit 0) first.</description>
4466              <bitRange>[0:0]</bitRange>
4467              <access>read-write</access>
4468            </field>
4469            <field>
4470              <name>REM_REVERSE</name>
4471              <description>Specifies whether the remainder is bit reversed (reversal is performed after XORing):
4472'0': No.
4473'1': Yes.</description>
4474              <bitRange>[8:8]</bitRange>
4475              <access>read-write</access>
4476            </field>
4477          </fields>
4478        </register>
4479        <register>
4480          <name>CRC_DATA_CTL</name>
4481          <description>CRC data control</description>
4482          <addressOffset>0x1410</addressOffset>
4483          <size>32</size>
4484          <access>read-write</access>
4485          <resetValue>0x0</resetValue>
4486          <resetMask>0xFF</resetMask>
4487          <fields>
4488            <field>
4489              <name>DATA_XOR</name>
4490              <description>Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal.</description>
4491              <bitRange>[7:0]</bitRange>
4492              <access>read-write</access>
4493            </field>
4494          </fields>
4495        </register>
4496        <register>
4497          <name>CRC_POL_CTL</name>
4498          <description>CRC polynomial control</description>
4499          <addressOffset>0x1420</addressOffset>
4500          <size>32</size>
4501          <access>read-write</access>
4502          <resetValue>0x0</resetValue>
4503          <resetMask>0xFFFFFFFF</resetMask>
4504          <fields>
4505            <field>
4506              <name>POLYNOMIAL</name>
4507              <description>CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials:
4508- CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1).
4509- CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions).
4510- CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions).</description>
4511              <bitRange>[31:0]</bitRange>
4512              <access>read-write</access>
4513            </field>
4514          </fields>
4515        </register>
4516        <register>
4517          <name>CRC_REM_CTL</name>
4518          <description>CRC remainder control</description>
4519          <addressOffset>0x1440</addressOffset>
4520          <size>32</size>
4521          <access>read-write</access>
4522          <resetValue>0x0</resetValue>
4523          <resetMask>0xFFFFFFFF</resetMask>
4524          <fields>
4525            <field>
4526              <name>REM_XOR</name>
4527              <description>Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal.</description>
4528              <bitRange>[31:0]</bitRange>
4529              <access>read-write</access>
4530            </field>
4531          </fields>
4532        </register>
4533        <register>
4534          <name>CRC_REM_RESULT</name>
4535          <description>CRC remainder result</description>
4536          <addressOffset>0x1448</addressOffset>
4537          <size>32</size>
4538          <access>read-only</access>
4539          <resetValue>0x0</resetValue>
4540          <resetMask>0xFFFFFFFF</resetMask>
4541          <fields>
4542            <field>
4543              <name>REM</name>
4544              <description>Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:
4545'0': the more significant bits (bit 31 and down) contain the remainder.
4546'1': the less significant bits (bit 0 and up) contain the remainder.
4547
4548Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_REM_CTL0.REM_REVERSE and CRC_REM_CTL1.REM_XOR.</description>
4549              <bitRange>[31:0]</bitRange>
4550              <access>read-only</access>
4551            </field>
4552          </fields>
4553        </register>
4554        <register>
4555          <name>VU_CTL0</name>
4556          <description>Vector unit control 0</description>
4557          <addressOffset>0x1480</addressOffset>
4558          <size>32</size>
4559          <access>read-write</access>
4560          <resetValue>0x0</resetValue>
4561          <resetMask>0x1</resetMask>
4562          <fields>
4563            <field>
4564              <name>ALWAYS_EXECUTE</name>
4565              <description>Specifies if a conditional instruction is executed or not, when its condition code evaluates to false/'0'.
4566'0': The instruction is NOT executed. As a result, the instruction may be handled faster than when it is executed.
4567'1': The instruction is executed, but the execution result (including status field information) is not reflected in the IP. The instruction is handled just as fast as when it is executed.
4568
4569Note: a conditional instruction with a condition code that evaluates to false/'0' does not affect the architectural state: VU_STATUS fields, memory or register-file data.
4570
4571Note: Always execution is useful to prevent/complicate differential timing and differential power attacks.</description>
4572              <bitRange>[0:0]</bitRange>
4573              <access>read-write</access>
4574            </field>
4575          </fields>
4576        </register>
4577        <register>
4578          <name>VU_CTL1</name>
4579          <description>Vector unit control 1</description>
4580          <addressOffset>0x1484</addressOffset>
4581          <size>32</size>
4582          <access>read-write</access>
4583          <resetValue>0x0</resetValue>
4584          <resetMask>0xFFFFFF00</resetMask>
4585          <fields>
4586            <field>
4587              <name>ADDR24</name>
4588              <description>Specifies the memory address for the vector unit operand memory region. The register-file registers provide 13-bit word offsets within this memory region. Given ADDR[31:8], VU_VTL2.MASK[14:8] and a 13-bit word offset offset[14:2], a vector operand memory address VU_OPERAND_ADDR[31:0] is calculated as follows:
4589- VU_OPERAND_ADDR[31:15] = ADDR[31:15]
4590- VU_OPERAND_ADDR[14:8] = (ADDR[14:8] &amp; MASK[14:8]) | (offset[14:8] &amp; ~MASK[14:8])
4591- VU_OPERAND_ADDR[7:2] = offset[7:2]
4592- VU_OPERAND_ADDR[1:0] = 0 (always word aligned)
4593
4594The vector unit operand memory region uses either the IP's memory buffer or system memory. For best performance, the IP's memory buffer should be used and ADDR should be set to MEM_BUFF and MASK should specify the IP memory buffer size.
4595
4596If a vector operand memory address is mapped on a memory hole, read accesses return a '0' and write accesses are ignored.</description>
4597              <bitRange>[31:8]</bitRange>
4598              <access>read-write</access>
4599            </field>
4600          </fields>
4601        </register>
4602        <register>
4603          <name>VU_CTL2</name>
4604          <description>Vector unit control 2</description>
4605          <addressOffset>0x1488</addressOffset>
4606          <size>32</size>
4607          <access>read-write</access>
4608          <resetValue>0x7F00</resetValue>
4609          <resetMask>0x7F00</resetMask>
4610          <fields>
4611            <field>
4612              <name>MASK</name>
4613              <description>Specifies the size of  the vector operand memory region. Legal values:
4614'0b0000000': 32 KB memory region (VU_VTL1.ADDR[14:8] ignored).
4615'0b1000000': 16 KB memory region (VU_VTL1.ADDR[13:8] ignored).
4616'0b1100000': 8 KB memory region (VU_VTL1.ADDR[12:8] ignored).
4617'0b1110000': 4 KB memory region (VU_VTL1.ADDR[11:8] ignored).
4618'0b1111000': 2 KB memory region (VU_VTL1.ADDR[10:8] ignored).
4619'0b1111100': 1 KB memory region (VU_VTL1.ADDR[9:8] ignored).
4620'0b1111110': 512 B memory region (VU_VTL1.ADDR[8] ignored).
4621'0b1111111': 256 B memory region.
4622
4623Note: the default specifies a 256 B memory region.</description>
4624              <bitRange>[14:8]</bitRange>
4625              <access>read-write</access>
4626            </field>
4627          </fields>
4628        </register>
4629        <register>
4630          <name>VU_STATUS</name>
4631          <description>Vector unit status</description>
4632          <addressOffset>0x1490</addressOffset>
4633          <size>32</size>
4634          <access>read-only</access>
4635          <resetValue>0x0</resetValue>
4636          <resetMask>0xF</resetMask>
4637          <fields>
4638            <field>
4639              <name>CARRY</name>
4640              <description>STATUS CARRY field.</description>
4641              <bitRange>[0:0]</bitRange>
4642              <access>read-only</access>
4643            </field>
4644            <field>
4645              <name>EVEN</name>
4646              <description>STATUS EVEN field.</description>
4647              <bitRange>[1:1]</bitRange>
4648              <access>read-only</access>
4649            </field>
4650            <field>
4651              <name>ZERO</name>
4652              <description>STATUS ZERO field.</description>
4653              <bitRange>[2:2]</bitRange>
4654              <access>read-only</access>
4655            </field>
4656            <field>
4657              <name>ONE</name>
4658              <description>STATUS ONE field.</description>
4659              <bitRange>[3:3]</bitRange>
4660              <access>read-only</access>
4661            </field>
4662          </fields>
4663        </register>
4664        <register>
4665          <dim>16</dim>
4666          <dimIncrement>4</dimIncrement>
4667          <name>VU_RF_DATA[%s]</name>
4668          <description>Vector unit register-file</description>
4669          <addressOffset>0x14C0</addressOffset>
4670          <size>32</size>
4671          <access>read-only</access>
4672          <resetValue>0x0</resetValue>
4673          <resetMask>0xFFFFFFFF</resetMask>
4674          <fields>
4675            <field>
4676              <name>DATA32</name>
4677              <description>Vector unit register-file data. A register-file register has the following layout:
4678DATA[28:16]: data (typically used as a word offset in vector unit operand memory).
4679DATA[12:0]: bit size minus 1.</description>
4680              <bitRange>[31:0]</bitRange>
4681              <access>read-only</access>
4682            </field>
4683          </fields>
4684        </register>
4685        <register>
4686          <name>DEV_KEY_ADDR0_CTL</name>
4687          <description>Device key address 0 control</description>
4688          <addressOffset>0x2000</addressOffset>
4689          <size>32</size>
4690          <access>read-write</access>
4691          <resetValue>0x0</resetValue>
4692          <resetMask>0x80000000</resetMask>
4693          <fields>
4694            <field>
4695              <name>VALID</name>
4696              <description>Specifies if the address in the associated DEV_KEY_ADDR0 is valid:
4697'0': Address not valid; i.e. no device key specified.
4698'1': Address valid; i.e. device key specified.
4699
4700Note: A LOAD_DEV_KEY instruction requires that the device key's valid field is '1'.</description>
4701              <bitRange>[31:31]</bitRange>
4702              <access>read-write</access>
4703            </field>
4704          </fields>
4705        </register>
4706        <register>
4707          <name>DEV_KEY_ADDR0</name>
4708          <description>Device key address 0</description>
4709          <addressOffset>0x2004</addressOffset>
4710          <size>32</size>
4711          <access>read-write</access>
4712          <resetValue>0x0</resetValue>
4713          <resetMask>0xFFFFFFFF</resetMask>
4714          <fields>
4715            <field>
4716              <name>ADDR32</name>
4717              <description>Specifies the memory address of the device key in memory. A LOAD_DEV_KEY instruction uses this address to load a device key from memory into the IP register buffer blocks 4 and 5.</description>
4718              <bitRange>[31:0]</bitRange>
4719              <access>read-write</access>
4720            </field>
4721          </fields>
4722        </register>
4723        <register>
4724          <name>DEV_KEY_ADDR1_CTL</name>
4725          <description>Device key address 1 control</description>
4726          <addressOffset>0x2020</addressOffset>
4727          <size>32</size>
4728          <access>read-write</access>
4729          <resetValue>0x0</resetValue>
4730          <resetMask>0x80000000</resetMask>
4731          <fields>
4732            <field>
4733              <name>VALID</name>
4734              <description>See DEV_KEY_ADDR0_CTL.</description>
4735              <bitRange>[31:31]</bitRange>
4736              <access>read-write</access>
4737            </field>
4738          </fields>
4739        </register>
4740        <register>
4741          <name>DEV_KEY_ADDR1</name>
4742          <description>Device key address 1 control</description>
4743          <addressOffset>0x2024</addressOffset>
4744          <size>32</size>
4745          <access>read-write</access>
4746          <resetValue>0x0</resetValue>
4747          <resetMask>0xFFFFFFFF</resetMask>
4748          <fields>
4749            <field>
4750              <name>ADDR32</name>
4751              <description>See DEV_KEY_ADDR0.</description>
4752              <bitRange>[31:0]</bitRange>
4753              <access>read-write</access>
4754            </field>
4755          </fields>
4756        </register>
4757        <register>
4758          <name>DEV_KEY_STATUS</name>
4759          <description>Device key status</description>
4760          <addressOffset>0x2080</addressOffset>
4761          <size>32</size>
4762          <access>read-only</access>
4763          <resetValue>0x0</resetValue>
4764          <resetMask>0x1</resetMask>
4765          <fields>
4766            <field>
4767              <name>LOADED</name>
4768              <description>Specifies if a device key is present in the IP register buffer blocks 4 and 5.
4769
4770HW sets this field to '1' on successful completion of a LOAD_DEV_KEY instruction.
4771HW clears this field to '0' when a CLEAR instruction is executed (the CLEAR instruction also sets the IP register buffer to '0').</description>
4772              <bitRange>[0:0]</bitRange>
4773              <access>read-only</access>
4774            </field>
4775          </fields>
4776        </register>
4777        <register>
4778          <name>DEV_KEY_CTL0</name>
4779          <description>Device key control 0</description>
4780          <addressOffset>0x2100</addressOffset>
4781          <size>32</size>
4782          <access>read-write</access>
4783          <resetValue>0x0</resetValue>
4784          <resetMask>0x1</resetMask>
4785          <fields>
4786            <field>
4787              <name>ALLOWED</name>
4788              <description>Specifies if a LOAD_DEV_KEY instruction is allowed to use the device key in memory:
4789'0': Not allowed.
4790'1': Allowed.
4791
4792Note: For successful completion of a LOAD_DEV_KEY instruction, both the associated DEV_KEY_ADDR_CTL.VALID and DEV_KEY_CTL.ALLOWED fields must be '1'. On successful instruction completion, DEV_KEY_STATUS.LOADED is set to '1'. On unsuccessful completion, the instruction FIFO is cleared and the IP is locked; an Active reset or an IP reset (CTL.ENABLED), which reinitializes the IP, is required.
4793
4794Note: A LOAD_DEV_KEY loads the device key from memory with protection context '0'.</description>
4795              <bitRange>[0:0]</bitRange>
4796              <access>read-write</access>
4797            </field>
4798          </fields>
4799        </register>
4800        <register>
4801          <name>DEV_KEY_CTL1</name>
4802          <description>Device key control 1</description>
4803          <addressOffset>0x2120</addressOffset>
4804          <size>32</size>
4805          <access>read-write</access>
4806          <resetValue>0x0</resetValue>
4807          <resetMask>0x1</resetMask>
4808          <fields>
4809            <field>
4810              <name>ALLOWED</name>
4811              <description>See DEV_KEY_CTL0.</description>
4812              <bitRange>[0:0]</bitRange>
4813              <access>read-write</access>
4814            </field>
4815          </fields>
4816        </register>
4817      </registers>
4818    </peripheral>
4819    <peripheral>
4820      <name>CPUSS</name>
4821      <description>CPU subsystem (CPUSS)</description>
4822      <baseAddress>0x40200000</baseAddress>
4823      <addressBlock>
4824        <offset>0</offset>
4825        <size>65536</size>
4826        <usage>registers</usage>
4827      </addressBlock>
4828      <interrupt>
4829        <name>NvicMux0</name>
4830        <description>CPU User Interrupt #0</description>
4831        <value>0</value>
4832      </interrupt>
4833      <interrupt>
4834        <name>NvicMux1</name>
4835        <description>CPU User Interrupt #1</description>
4836        <value>1</value>
4837      </interrupt>
4838      <interrupt>
4839        <name>NvicMux2</name>
4840        <description>CPU User Interrupt #2</description>
4841        <value>2</value>
4842      </interrupt>
4843      <interrupt>
4844        <name>NvicMux3</name>
4845        <description>CPU User Interrupt #3</description>
4846        <value>3</value>
4847      </interrupt>
4848      <interrupt>
4849        <name>NvicMux4</name>
4850        <description>CPU User Interrupt #4</description>
4851        <value>4</value>
4852      </interrupt>
4853      <interrupt>
4854        <name>NvicMux5</name>
4855        <description>CPU User Interrupt #5</description>
4856        <value>5</value>
4857      </interrupt>
4858      <interrupt>
4859        <name>NvicMux6</name>
4860        <description>CPU User Interrupt #6</description>
4861        <value>6</value>
4862      </interrupt>
4863      <interrupt>
4864        <name>NvicMux7</name>
4865        <description>CPU User Interrupt #7</description>
4866        <value>7</value>
4867      </interrupt>
4868      <interrupt>
4869        <name>Internal0</name>
4870        <description>Internal SW Interrupt #0</description>
4871        <value>8</value>
4872      </interrupt>
4873      <interrupt>
4874        <name>Internal1</name>
4875        <description>Internal SW Interrupt #1</description>
4876        <value>9</value>
4877      </interrupt>
4878      <interrupt>
4879        <name>Internal2</name>
4880        <description>Internal SW Interrupt #2</description>
4881        <value>10</value>
4882      </interrupt>
4883      <interrupt>
4884        <name>Internal3</name>
4885        <description>Internal SW Interrupt #3</description>
4886        <value>11</value>
4887      </interrupt>
4888      <interrupt>
4889        <name>Internal4</name>
4890        <description>Internal SW Interrupt #4</description>
4891        <value>12</value>
4892      </interrupt>
4893      <interrupt>
4894        <name>Internal5</name>
4895        <description>Internal SW Interrupt #5</description>
4896        <value>13</value>
4897      </interrupt>
4898      <interrupt>
4899        <name>Internal6</name>
4900        <description>Internal SW Interrupt #6</description>
4901        <value>14</value>
4902      </interrupt>
4903      <interrupt>
4904        <name>Internal7</name>
4905        <description>Internal SW Interrupt #7</description>
4906        <value>15</value>
4907      </interrupt>
4908      <registers>
4909        <register>
4910          <name>IDENTITY</name>
4911          <description>Identity</description>
4912          <addressOffset>0x0</addressOffset>
4913          <size>32</size>
4914          <access>read-only</access>
4915          <resetValue>0x0</resetValue>
4916          <resetMask>0x0</resetMask>
4917          <fields>
4918            <field>
4919              <name>P</name>
4920              <description>This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register.</description>
4921              <bitRange>[0:0]</bitRange>
4922              <access>read-only</access>
4923            </field>
4924            <field>
4925              <name>NS</name>
4926              <description>This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register.</description>
4927              <bitRange>[1:1]</bitRange>
4928              <access>read-only</access>
4929            </field>
4930            <field>
4931              <name>PC</name>
4932              <description>This field specifies the protection context of the transfer that reads the register.</description>
4933              <bitRange>[7:4]</bitRange>
4934              <access>read-only</access>
4935            </field>
4936            <field>
4937              <name>MS</name>
4938              <description>This field specifies the bus master identifier of the transfer that reads the register.</description>
4939              <bitRange>[11:8]</bitRange>
4940              <access>read-only</access>
4941            </field>
4942          </fields>
4943        </register>
4944        <register>
4945          <name>CM4_STATUS</name>
4946          <description>CM4 status</description>
4947          <addressOffset>0x4</addressOffset>
4948          <size>32</size>
4949          <access>read-only</access>
4950          <resetValue>0x13</resetValue>
4951          <resetMask>0x13</resetMask>
4952          <fields>
4953            <field>
4954              <name>SLEEPING</name>
4955              <description>Specifies if the CPU is in Active, Sleep or DeepSleep power mode:
4956- Active power mode: SLEEPING is '0'.
4957- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'.
4958- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.</description>
4959              <bitRange>[0:0]</bitRange>
4960              <access>read-only</access>
4961            </field>
4962            <field>
4963              <name>SLEEPDEEP</name>
4964              <description>Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.</description>
4965              <bitRange>[1:1]</bitRange>
4966              <access>read-only</access>
4967            </field>
4968            <field>
4969              <name>PWR_DONE</name>
4970              <description>After a PWR_MODE change this flag indicates if the new power mode has taken effect or not.
4971Note: this flag can also change as a result of  a change in debug power up req</description>
4972              <bitRange>[4:4]</bitRange>
4973              <access>read-only</access>
4974            </field>
4975          </fields>
4976        </register>
4977        <register>
4978          <name>CM4_CLOCK_CTL</name>
4979          <description>CM4 clock control</description>
4980          <addressOffset>0x8</addressOffset>
4981          <size>32</size>
4982          <access>read-write</access>
4983          <resetValue>0x0</resetValue>
4984          <resetMask>0xFF00</resetMask>
4985          <fields>
4986            <field>
4987              <name>FAST_INT_DIV</name>
4988              <description>Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]).
4989
4990Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
4991              <bitRange>[15:8]</bitRange>
4992              <access>read-write</access>
4993            </field>
4994          </fields>
4995        </register>
4996        <register>
4997          <name>CM4_CTL</name>
4998          <description>CM4 control</description>
4999          <addressOffset>0xC</addressOffset>
5000          <size>32</size>
5001          <access>read-write</access>
5002          <resetValue>0x0</resetValue>
5003          <resetMask>0x9F000000</resetMask>
5004          <fields>
5005            <field>
5006              <name>IOC_MASK</name>
5007              <description>CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition:
5008'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5009'1': the CPU's exception condition activates the CPU's floating point interrupt.
5010
5011Note: the ARM architecture does NOT support FPU exceptions; i.e. there is no precise FPU exception handler. Instead, FPU conditions are captured in the CPU's FPCSR register and the conditions are provided as CPU interface signals. The interface signals are 'masked' with the fields a provide by this register (CM7_0_CTL). The 'masked' signals are reduced/OR-ed into a single CPU floating point interrupt signal. The associated CPU interrupt handler allows for imprecise handling of FPU exception conditions.
5012
5013Note: the CPU's FPCSR exception conditions are 'sticky'. Typically, the CPU FPU interrupt handler will clear the exception condition(s) to '0'.
5014
5015Note: by default, the FPU exception masks are '0'. Therefore, FPU exception conditions will NOT activate the CPU's floating point interrupt.</description>
5016              <bitRange>[24:24]</bitRange>
5017              <access>read-write</access>
5018            </field>
5019            <field>
5020              <name>DZC_MASK</name>
5021              <description>CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition:
5022'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5023'1': the CPU's exception condition activates the CPU's floating point interrupt.</description>
5024              <bitRange>[25:25]</bitRange>
5025              <access>read-write</access>
5026            </field>
5027            <field>
5028              <name>OFC_MASK</name>
5029              <description>CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition:
5030'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5031'1': the CPU's exception condition activates the CPU's floating point interrupt.</description>
5032              <bitRange>[26:26]</bitRange>
5033              <access>read-write</access>
5034            </field>
5035            <field>
5036              <name>UFC_MASK</name>
5037              <description>CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition:
5038'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5039'1': the CPU's exception condition activates the CPU's floating point interrupt.</description>
5040              <bitRange>[27:27]</bitRange>
5041              <access>read-write</access>
5042            </field>
5043            <field>
5044              <name>IXC_MASK</name>
5045              <description>CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition:
5046'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5047'1': the CPU's exception condition activates the CPU's floating point interrupt.
5048
5049Note: the 'inexact' condition is set as a result of rounding. Rounding may occur frequently and is typically not an error condition. To prevent frequent CPU FPU interrupts as a result of rounding, this field is typically set to '0'.</description>
5050              <bitRange>[28:28]</bitRange>
5051              <access>read-write</access>
5052            </field>
5053            <field>
5054              <name>IDC_MASK</name>
5055              <description>CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition:
5056'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5057'1': the CPU's exception condition activates the CPU's floating point interrupt.
5058
5059Note: if the CPU FPCSR.FZ field is set to '1', denormalized inputs are 'flushed to zero'. Dependent on the FPU algorithm, this may or may not occur frequently. To prevent frequent CPU FPU interrupts as a result of denormalized inputs, this field may be set to '0'.</description>
5060              <bitRange>[31:31]</bitRange>
5061              <access>read-write</access>
5062            </field>
5063          </fields>
5064        </register>
5065        <register>
5066          <name>CM4_INT0_STATUS</name>
5067          <description>CM4 interrupt 0 status</description>
5068          <addressOffset>0x100</addressOffset>
5069          <size>32</size>
5070          <access>read-only</access>
5071          <resetValue>0x0</resetValue>
5072          <resetMask>0x80000000</resetMask>
5073          <fields>
5074            <field>
5075              <name>SYSTEM_INT_IDX</name>
5076              <description>Lowest CM4 activated system interrupt index for CPU interrupt 0.
5077
5078See description of CM0_INT0_STATUS.</description>
5079              <bitRange>[9:0]</bitRange>
5080              <access>read-only</access>
5081            </field>
5082            <field>
5083              <name>SYSTEM_INT_VALID</name>
5084              <description>See description of CM0_INT0_STATUS.</description>
5085              <bitRange>[31:31]</bitRange>
5086              <access>read-only</access>
5087            </field>
5088          </fields>
5089        </register>
5090        <register>
5091          <name>CM4_INT1_STATUS</name>
5092          <description>CM4 interrupt 1 status</description>
5093          <addressOffset>0x104</addressOffset>
5094          <size>32</size>
5095          <access>read-only</access>
5096          <resetValue>0x0</resetValue>
5097          <resetMask>0x80000000</resetMask>
5098          <fields>
5099            <field>
5100              <name>SYSTEM_INT_IDX</name>
5101              <description>Lowest CM4 activated system interrupt index for CPU interrupt 1.
5102
5103See description of CM0_INT0_STATUS.</description>
5104              <bitRange>[9:0]</bitRange>
5105              <access>read-only</access>
5106            </field>
5107            <field>
5108              <name>SYSTEM_INT_VALID</name>
5109              <description>See description of CM0_INT0_STATUS.</description>
5110              <bitRange>[31:31]</bitRange>
5111              <access>read-only</access>
5112            </field>
5113          </fields>
5114        </register>
5115        <register>
5116          <name>CM4_INT2_STATUS</name>
5117          <description>CM4 interrupt 2 status</description>
5118          <addressOffset>0x108</addressOffset>
5119          <size>32</size>
5120          <access>read-only</access>
5121          <resetValue>0x0</resetValue>
5122          <resetMask>0x80000000</resetMask>
5123          <fields>
5124            <field>
5125              <name>SYSTEM_INT_IDX</name>
5126              <description>Lowest CM4 activated system interrupt index for CPU interrupt 2.
5127
5128See description of CM0_INT0_STATUS.</description>
5129              <bitRange>[9:0]</bitRange>
5130              <access>read-only</access>
5131            </field>
5132            <field>
5133              <name>SYSTEM_INT_VALID</name>
5134              <description>See description of CM0_INT0_STATUS.</description>
5135              <bitRange>[31:31]</bitRange>
5136              <access>read-only</access>
5137            </field>
5138          </fields>
5139        </register>
5140        <register>
5141          <name>CM4_INT3_STATUS</name>
5142          <description>CM4 interrupt 3 status</description>
5143          <addressOffset>0x10C</addressOffset>
5144          <size>32</size>
5145          <access>read-only</access>
5146          <resetValue>0x0</resetValue>
5147          <resetMask>0x80000000</resetMask>
5148          <fields>
5149            <field>
5150              <name>SYSTEM_INT_IDX</name>
5151              <description>Lowest CM4 activated system interrupt index for CPU interrupt 3.
5152
5153See description of CM0_INT0_STATUS.</description>
5154              <bitRange>[9:0]</bitRange>
5155              <access>read-only</access>
5156            </field>
5157            <field>
5158              <name>SYSTEM_INT_VALID</name>
5159              <description>See description of CM0_INT0_STATUS.</description>
5160              <bitRange>[31:31]</bitRange>
5161              <access>read-only</access>
5162            </field>
5163          </fields>
5164        </register>
5165        <register>
5166          <name>CM4_INT4_STATUS</name>
5167          <description>CM4 interrupt 4 status</description>
5168          <addressOffset>0x110</addressOffset>
5169          <size>32</size>
5170          <access>read-only</access>
5171          <resetValue>0x0</resetValue>
5172          <resetMask>0x80000000</resetMask>
5173          <fields>
5174            <field>
5175              <name>SYSTEM_INT_IDX</name>
5176              <description>Lowest CM4 activated system interrupt index for CPU interrupt 4.
5177
5178See description of CM0_INT0_STATUS.</description>
5179              <bitRange>[9:0]</bitRange>
5180              <access>read-only</access>
5181            </field>
5182            <field>
5183              <name>SYSTEM_INT_VALID</name>
5184              <description>See description of CM0_INT0_STATUS.</description>
5185              <bitRange>[31:31]</bitRange>
5186              <access>read-only</access>
5187            </field>
5188          </fields>
5189        </register>
5190        <register>
5191          <name>CM4_INT5_STATUS</name>
5192          <description>CM4 interrupt 5 status</description>
5193          <addressOffset>0x114</addressOffset>
5194          <size>32</size>
5195          <access>read-only</access>
5196          <resetValue>0x0</resetValue>
5197          <resetMask>0x80000000</resetMask>
5198          <fields>
5199            <field>
5200              <name>SYSTEM_INT_IDX</name>
5201              <description>Lowest CM4 activated system interrupt index for CPU interrupt 5.
5202
5203See description of CM0_INT0_STATUS.</description>
5204              <bitRange>[9:0]</bitRange>
5205              <access>read-only</access>
5206            </field>
5207            <field>
5208              <name>SYSTEM_INT_VALID</name>
5209              <description>See description of CM0_INT0_STATUS.</description>
5210              <bitRange>[31:31]</bitRange>
5211              <access>read-only</access>
5212            </field>
5213          </fields>
5214        </register>
5215        <register>
5216          <name>CM4_INT6_STATUS</name>
5217          <description>CM4 interrupt 6 status</description>
5218          <addressOffset>0x118</addressOffset>
5219          <size>32</size>
5220          <access>read-only</access>
5221          <resetValue>0x0</resetValue>
5222          <resetMask>0x80000000</resetMask>
5223          <fields>
5224            <field>
5225              <name>SYSTEM_INT_IDX</name>
5226              <description>Lowest CM4 activated system interrupt index for CPU interrupt 6.
5227
5228See description of CM0_INT0_STATUS.</description>
5229              <bitRange>[9:0]</bitRange>
5230              <access>read-only</access>
5231            </field>
5232            <field>
5233              <name>SYSTEM_INT_VALID</name>
5234              <description>See description of CM0_INT0_STATUS.</description>
5235              <bitRange>[31:31]</bitRange>
5236              <access>read-only</access>
5237            </field>
5238          </fields>
5239        </register>
5240        <register>
5241          <name>CM4_INT7_STATUS</name>
5242          <description>CM4 interrupt 7 status</description>
5243          <addressOffset>0x11C</addressOffset>
5244          <size>32</size>
5245          <access>read-only</access>
5246          <resetValue>0x0</resetValue>
5247          <resetMask>0x80000000</resetMask>
5248          <fields>
5249            <field>
5250              <name>SYSTEM_INT_IDX</name>
5251              <description>Lowest CM4 activated system interrupt index for CPU interrupt 7.
5252
5253See description of CM0_INT0_STATUS.</description>
5254              <bitRange>[9:0]</bitRange>
5255              <access>read-only</access>
5256            </field>
5257            <field>
5258              <name>SYSTEM_INT_VALID</name>
5259              <description>See description of CM0_INT0_STATUS.</description>
5260              <bitRange>[31:31]</bitRange>
5261              <access>read-only</access>
5262            </field>
5263          </fields>
5264        </register>
5265        <register>
5266          <name>CM4_VECTOR_TABLE_BASE</name>
5267          <description>CM4 vector table base</description>
5268          <addressOffset>0x200</addressOffset>
5269          <size>32</size>
5270          <access>read-write</access>
5271          <resetValue>0x0</resetValue>
5272          <resetMask>0xFFFFFC00</resetMask>
5273          <fields>
5274            <field>
5275              <name>ADDR22</name>
5276              <description>Address of CM4 vector table. This register is used for CM4 warm and cold boot purposes: the CM0+ CPU initializes the CM4_VECTOR_TABLE_BASE register and the CM4 boot code uses the register to initialize the CM4 internal VTOR register.
5277
5278Note: the CM4 vector table is at an address that is a 1024 B multiple.</description>
5279              <bitRange>[31:10]</bitRange>
5280              <access>read-write</access>
5281            </field>
5282          </fields>
5283        </register>
5284        <register>
5285          <dim>4</dim>
5286          <dimIncrement>4</dimIncrement>
5287          <name>CM4_NMI_CTL[%s]</name>
5288          <description>CM4 NMI control</description>
5289          <addressOffset>0x240</addressOffset>
5290          <size>32</size>
5291          <access>read-write</access>
5292          <resetValue>0x3FF</resetValue>
5293          <resetMask>0x3FF</resetMask>
5294          <fields>
5295            <field>
5296              <name>SYSTEM_INT_IDX</name>
5297              <description>System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.</description>
5298              <bitRange>[9:0]</bitRange>
5299              <access>read-write</access>
5300            </field>
5301          </fields>
5302        </register>
5303        <register>
5304          <name>UDB_PWR_CTL</name>
5305          <description>UDB power control</description>
5306          <addressOffset>0x300</addressOffset>
5307          <size>32</size>
5308          <access>read-write</access>
5309          <resetValue>0xFA050001</resetValue>
5310          <resetMask>0xFFFF0003</resetMask>
5311          <fields>
5312            <field>
5313              <name>PWR_MODE</name>
5314              <description>Set Power mode for UDBs</description>
5315              <bitRange>[1:0]</bitRange>
5316              <access>read-write</access>
5317              <enumeratedValues>
5318                <enumeratedValue>
5319                  <name>OFF</name>
5320                  <description>See CM4_PWR_CTL</description>
5321                  <value>0</value>
5322                </enumeratedValue>
5323                <enumeratedValue>
5324                  <name>RESET</name>
5325                  <description>See CM4_PWR_CTL</description>
5326                  <value>1</value>
5327                </enumeratedValue>
5328                <enumeratedValue>
5329                  <name>RETAINED</name>
5330                  <description>See CM4_PWR_CTL</description>
5331                  <value>2</value>
5332                </enumeratedValue>
5333                <enumeratedValue>
5334                  <name>ENABLED</name>
5335                  <description>See CM4_PWR_CTL</description>
5336                  <value>3</value>
5337                </enumeratedValue>
5338              </enumeratedValues>
5339            </field>
5340            <field>
5341              <name>VECTKEYSTAT</name>
5342              <description>Register key (to prevent accidental writes).
5343- Should be written with a 0x05fa key value for the write to take effect.
5344- Always reads as 0xfa05.</description>
5345              <bitRange>[31:16]</bitRange>
5346              <access>read-only</access>
5347            </field>
5348          </fields>
5349        </register>
5350        <register>
5351          <name>UDB_PWR_DELAY_CTL</name>
5352          <description>UDB power control</description>
5353          <addressOffset>0x304</addressOffset>
5354          <size>32</size>
5355          <access>read-write</access>
5356          <resetValue>0x12C</resetValue>
5357          <resetMask>0x3FF</resetMask>
5358          <fields>
5359            <field>
5360              <name>UP</name>
5361              <description>Number clock cycles delay needed after power domain power up</description>
5362              <bitRange>[9:0]</bitRange>
5363              <access>read-write</access>
5364            </field>
5365          </fields>
5366        </register>
5367        <register>
5368          <name>CM0_CTL</name>
5369          <description>CM0+ control</description>
5370          <addressOffset>0x1000</addressOffset>
5371          <size>32</size>
5372          <access>read-write</access>
5373          <resetValue>0xFA050002</resetValue>
5374          <resetMask>0xFFFF0003</resetMask>
5375          <fields>
5376            <field>
5377              <name>SLV_STALL</name>
5378              <description>Processor debug access control:
5379'0': Access.
5380'1': Stall access.
5381
5382This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses.</description>
5383              <bitRange>[0:0]</bitRange>
5384              <access>read-write</access>
5385            </field>
5386            <field>
5387              <name>ENABLED</name>
5388              <description>Processor enable:
5389'0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot.
5390'1': Enabled.
5391Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented).
5392
5393Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details).</description>
5394              <bitRange>[1:1]</bitRange>
5395              <access>read-write</access>
5396            </field>
5397            <field>
5398              <name>VECTKEYSTAT</name>
5399              <description>Register key (to prevent accidental writes).
5400- Should be written with a 0x05fa key value for the write to take effect.
5401- Always reads as 0xfa05.
5402
5403Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.</description>
5404              <bitRange>[31:16]</bitRange>
5405              <access>read-only</access>
5406            </field>
5407          </fields>
5408        </register>
5409        <register>
5410          <name>CM0_STATUS</name>
5411          <description>CM0+ status</description>
5412          <addressOffset>0x1004</addressOffset>
5413          <size>32</size>
5414          <access>read-only</access>
5415          <resetValue>0x0</resetValue>
5416          <resetMask>0x3</resetMask>
5417          <fields>
5418            <field>
5419              <name>SLEEPING</name>
5420              <description>Specifies if the CPU is in Active, Sleep or DeepSleep power mode:
5421- Active power mode: SLEEPING is '0'.
5422- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'.
5423- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.</description>
5424              <bitRange>[0:0]</bitRange>
5425              <access>read-only</access>
5426            </field>
5427            <field>
5428              <name>SLEEPDEEP</name>
5429              <description>Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.</description>
5430              <bitRange>[1:1]</bitRange>
5431              <access>read-only</access>
5432            </field>
5433          </fields>
5434        </register>
5435        <register>
5436          <name>CM0_CLOCK_CTL</name>
5437          <description>CM0+ clock control</description>
5438          <addressOffset>0x1008</addressOffset>
5439          <size>32</size>
5440          <access>read-write</access>
5441          <resetValue>0x0</resetValue>
5442          <resetMask>0xFF00FF00</resetMask>
5443          <fields>
5444            <field>
5445              <name>SLOW_INT_DIV</name>
5446              <description>Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]).
5447
5448Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
5449              <bitRange>[15:8]</bitRange>
5450              <access>read-write</access>
5451            </field>
5452            <field>
5453              <name>PERI_INT_DIV</name>
5454              <description>Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]).
5455
5456Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
5457
5458Note that Fperi &lt;= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'.</description>
5459              <bitRange>[31:24]</bitRange>
5460              <access>read-write</access>
5461            </field>
5462          </fields>
5463        </register>
5464        <register>
5465          <name>CM0_INT0_STATUS</name>
5466          <description>CM0+ interrupt 0 status</description>
5467          <addressOffset>0x1100</addressOffset>
5468          <size>32</size>
5469          <access>read-only</access>
5470          <resetValue>0x0</resetValue>
5471          <resetMask>0x80000000</resetMask>
5472          <fields>
5473            <field>
5474              <name>SYSTEM_INT_IDX</name>
5475              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 0.
5476
5477Multiple system interrupts can be mapped on the same CPU interrupt. The selected system interrupt is the system interrupt with the lowest system interrupt index that has an activated interrupt request at the time of the fetch (system_interrupts[SYSTEM_INT_IDX] is '1').
5478
5479The CPU interrupt handler SW can read SYSTEM_INT_IDX to determine the system interrupt that activated the handler.</description>
5480              <bitRange>[9:0]</bitRange>
5481              <access>read-only</access>
5482            </field>
5483            <field>
5484              <name>SYSTEM_INT_VALID</name>
5485              <description>Valid indication for SYSTEM_INT_IDX. When '0', no system interrupt for CPU interrupt 0 is valid/activated.</description>
5486              <bitRange>[31:31]</bitRange>
5487              <access>read-only</access>
5488            </field>
5489          </fields>
5490        </register>
5491        <register>
5492          <name>CM0_INT1_STATUS</name>
5493          <description>CM0+ interrupt 1 status</description>
5494          <addressOffset>0x1104</addressOffset>
5495          <size>32</size>
5496          <access>read-only</access>
5497          <resetValue>0x0</resetValue>
5498          <resetMask>0x80000000</resetMask>
5499          <fields>
5500            <field>
5501              <name>SYSTEM_INT_IDX</name>
5502              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 1.
5503
5504See description of CM0_INT0_STATUS.</description>
5505              <bitRange>[9:0]</bitRange>
5506              <access>read-only</access>
5507            </field>
5508            <field>
5509              <name>SYSTEM_INT_VALID</name>
5510              <description>See description of CM0_INT0_STATUS.</description>
5511              <bitRange>[31:31]</bitRange>
5512              <access>read-only</access>
5513            </field>
5514          </fields>
5515        </register>
5516        <register>
5517          <name>CM0_INT2_STATUS</name>
5518          <description>CM0+ interrupt 2 status</description>
5519          <addressOffset>0x1108</addressOffset>
5520          <size>32</size>
5521          <access>read-only</access>
5522          <resetValue>0x0</resetValue>
5523          <resetMask>0x80000000</resetMask>
5524          <fields>
5525            <field>
5526              <name>SYSTEM_INT_IDX</name>
5527              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 2.
5528
5529See description of CM0_INT0_STATUS.</description>
5530              <bitRange>[9:0]</bitRange>
5531              <access>read-only</access>
5532            </field>
5533            <field>
5534              <name>SYSTEM_INT_VALID</name>
5535              <description>See description of CM0_INT0_STATUS.</description>
5536              <bitRange>[31:31]</bitRange>
5537              <access>read-only</access>
5538            </field>
5539          </fields>
5540        </register>
5541        <register>
5542          <name>CM0_INT3_STATUS</name>
5543          <description>CM0+ interrupt 3 status</description>
5544          <addressOffset>0x110C</addressOffset>
5545          <size>32</size>
5546          <access>read-only</access>
5547          <resetValue>0x0</resetValue>
5548          <resetMask>0x80000000</resetMask>
5549          <fields>
5550            <field>
5551              <name>SYSTEM_INT_IDX</name>
5552              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 3.
5553
5554See description of CM0_INT0_STATUS.</description>
5555              <bitRange>[9:0]</bitRange>
5556              <access>read-only</access>
5557            </field>
5558            <field>
5559              <name>SYSTEM_INT_VALID</name>
5560              <description>See description of CM0_INT0_STATUS.</description>
5561              <bitRange>[31:31]</bitRange>
5562              <access>read-only</access>
5563            </field>
5564          </fields>
5565        </register>
5566        <register>
5567          <name>CM0_INT4_STATUS</name>
5568          <description>CM0+ interrupt 4 status</description>
5569          <addressOffset>0x1110</addressOffset>
5570          <size>32</size>
5571          <access>read-only</access>
5572          <resetValue>0x0</resetValue>
5573          <resetMask>0x80000000</resetMask>
5574          <fields>
5575            <field>
5576              <name>SYSTEM_INT_IDX</name>
5577              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 4.
5578
5579See description of CM0_INT0_STATUS.</description>
5580              <bitRange>[9:0]</bitRange>
5581              <access>read-only</access>
5582            </field>
5583            <field>
5584              <name>SYSTEM_INT_VALID</name>
5585              <description>See description of CM0_INT0_STATUS.</description>
5586              <bitRange>[31:31]</bitRange>
5587              <access>read-only</access>
5588            </field>
5589          </fields>
5590        </register>
5591        <register>
5592          <name>CM0_INT5_STATUS</name>
5593          <description>CM0+ interrupt 5 status</description>
5594          <addressOffset>0x1114</addressOffset>
5595          <size>32</size>
5596          <access>read-only</access>
5597          <resetValue>0x0</resetValue>
5598          <resetMask>0x80000000</resetMask>
5599          <fields>
5600            <field>
5601              <name>SYSTEM_INT_IDX</name>
5602              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 5.
5603
5604See description of CM0_INT0_STATUS.</description>
5605              <bitRange>[9:0]</bitRange>
5606              <access>read-only</access>
5607            </field>
5608            <field>
5609              <name>SYSTEM_INT_VALID</name>
5610              <description>See description of CM0_INT0_STATUS.</description>
5611              <bitRange>[31:31]</bitRange>
5612              <access>read-only</access>
5613            </field>
5614          </fields>
5615        </register>
5616        <register>
5617          <name>CM0_INT6_STATUS</name>
5618          <description>CM0+ interrupt 6 status</description>
5619          <addressOffset>0x1118</addressOffset>
5620          <size>32</size>
5621          <access>read-only</access>
5622          <resetValue>0x0</resetValue>
5623          <resetMask>0x80000000</resetMask>
5624          <fields>
5625            <field>
5626              <name>SYSTEM_INT_IDX</name>
5627              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 6.
5628
5629See description of CM0_INT0_STATUS.</description>
5630              <bitRange>[9:0]</bitRange>
5631              <access>read-only</access>
5632            </field>
5633            <field>
5634              <name>SYSTEM_INT_VALID</name>
5635              <description>See description of CM0_INT0_STATUS.</description>
5636              <bitRange>[31:31]</bitRange>
5637              <access>read-only</access>
5638            </field>
5639          </fields>
5640        </register>
5641        <register>
5642          <name>CM0_INT7_STATUS</name>
5643          <description>CM0+ interrupt 7 status</description>
5644          <addressOffset>0x111C</addressOffset>
5645          <size>32</size>
5646          <access>read-only</access>
5647          <resetValue>0x0</resetValue>
5648          <resetMask>0x80000000</resetMask>
5649          <fields>
5650            <field>
5651              <name>SYSTEM_INT_IDX</name>
5652              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 7.
5653
5654See description of CM0_INT0_STATUS.</description>
5655              <bitRange>[9:0]</bitRange>
5656              <access>read-only</access>
5657            </field>
5658            <field>
5659              <name>SYSTEM_INT_VALID</name>
5660              <description>See description of CM0_INT0_STATUS.</description>
5661              <bitRange>[31:31]</bitRange>
5662              <access>read-only</access>
5663            </field>
5664          </fields>
5665        </register>
5666        <register>
5667          <name>CM0_VECTOR_TABLE_BASE</name>
5668          <description>CM0+ vector table base</description>
5669          <addressOffset>0x1120</addressOffset>
5670          <size>32</size>
5671          <access>read-write</access>
5672          <resetValue>0x0</resetValue>
5673          <resetMask>0xFFFFFF00</resetMask>
5674          <fields>
5675            <field>
5676              <name>ADDR24</name>
5677              <description>Address of CM0+ vector table. This register is used for CM0+ warm boot purposes: the CM0+ warm boot code uses the register to initialize the CM0+ internal VTOR register.
5678
5679Note: the CM0+ vector table is at an address that is a 256 B multiple.</description>
5680              <bitRange>[31:8]</bitRange>
5681              <access>read-write</access>
5682            </field>
5683          </fields>
5684        </register>
5685        <register>
5686          <dim>4</dim>
5687          <dimIncrement>4</dimIncrement>
5688          <name>CM0_NMI_CTL[%s]</name>
5689          <description>CM0+ NMI control</description>
5690          <addressOffset>0x1140</addressOffset>
5691          <size>32</size>
5692          <access>read-write</access>
5693          <resetValue>0x3FF</resetValue>
5694          <resetMask>0x3FF</resetMask>
5695          <fields>
5696            <field>
5697              <name>SYSTEM_INT_IDX</name>
5698              <description>System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.</description>
5699              <bitRange>[9:0]</bitRange>
5700              <access>read-write</access>
5701            </field>
5702          </fields>
5703        </register>
5704        <register>
5705          <name>CM4_PWR_CTL</name>
5706          <description>CM4 power control</description>
5707          <addressOffset>0x1200</addressOffset>
5708          <size>32</size>
5709          <access>read-write</access>
5710          <resetValue>0xFA050001</resetValue>
5711          <resetMask>0xFFFF0003</resetMask>
5712          <fields>
5713            <field>
5714              <name>PWR_MODE</name>
5715              <description>Power mode.</description>
5716              <bitRange>[1:0]</bitRange>
5717              <access>read-write</access>
5718              <enumeratedValues>
5719                <enumeratedValue>
5720                  <name>OFF</name>
5721                  <description>Switch CM4 off
5722Power off, clock off, isolate, reset and no retain.</description>
5723                  <value>0</value>
5724                </enumeratedValue>
5725                <enumeratedValue>
5726                  <name>RESET</name>
5727                  <description>Reset CM4
5728Clock off, no isolated, no retain and reset.
5729
5730Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot.</description>
5731                  <value>1</value>
5732                </enumeratedValue>
5733                <enumeratedValue>
5734                  <name>RETAINED</name>
5735                  <description>Put CM4 in Retained mode
5736This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached.
5737Power off, clock off, isolate, no reset and retain.</description>
5738                  <value>2</value>
5739                </enumeratedValue>
5740                <enumeratedValue>
5741                  <name>ENABLED</name>
5742                  <description>Switch CM4 on.
5743Power on, clock on, no isolate, no reset and no retain.</description>
5744                  <value>3</value>
5745                </enumeratedValue>
5746              </enumeratedValues>
5747            </field>
5748            <field>
5749              <name>VECTKEYSTAT</name>
5750              <description>Register key (to prevent accidental writes).
5751- Should be written with a 0x05fa key value for the write to take effect.
5752- Always reads as 0xfa05.
5753
5754Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.</description>
5755              <bitRange>[31:16]</bitRange>
5756              <access>read-only</access>
5757            </field>
5758          </fields>
5759        </register>
5760        <register>
5761          <name>CM4_PWR_DELAY_CTL</name>
5762          <description>CM4 power control</description>
5763          <addressOffset>0x1204</addressOffset>
5764          <size>32</size>
5765          <access>read-write</access>
5766          <resetValue>0x12C</resetValue>
5767          <resetMask>0x3FF</resetMask>
5768          <fields>
5769            <field>
5770              <name>UP</name>
5771              <description>Number clock cycles delay needed after power domain power up</description>
5772              <bitRange>[9:0]</bitRange>
5773              <access>read-write</access>
5774            </field>
5775          </fields>
5776        </register>
5777        <register>
5778          <name>RAM0_CTL0</name>
5779          <description>RAM 0 control</description>
5780          <addressOffset>0x1300</addressOffset>
5781          <size>32</size>
5782          <access>read-write</access>
5783          <resetValue>0x30001</resetValue>
5784          <resetMask>0x70303</resetMask>
5785          <fields>
5786            <field>
5787              <name>SLOW_WS</name>
5788              <description>Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.</description>
5789              <bitRange>[1:0]</bitRange>
5790              <access>read-write</access>
5791            </field>
5792            <field>
5793              <name>FAST_WS</name>
5794              <description>Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.</description>
5795              <bitRange>[9:8]</bitRange>
5796              <access>read-write</access>
5797            </field>
5798            <field>
5799              <name>ECC_EN</name>
5800              <description>Enable ECC checking:
5801'0': Disabled.
5802'1': Enabled.</description>
5803              <bitRange>[16:16]</bitRange>
5804              <access>read-write</access>
5805            </field>
5806            <field>
5807              <name>ECC_AUTO_CORRECT</name>
5808              <description>HW ECC autocorrect functionality:
5809'0': Disabled.
5810'1': Enabled. HW automatically writes back SRAM with corrected data when a recoverable ECC error is detected.</description>
5811              <bitRange>[17:17]</bitRange>
5812              <access>read-write</access>
5813            </field>
5814            <field>
5815              <name>ECC_INJ_EN</name>
5816              <description>Enable error injection for system SRAM 0.
5817When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of system SRAM 0.</description>
5818              <bitRange>[18:18]</bitRange>
5819              <access>read-write</access>
5820            </field>
5821          </fields>
5822        </register>
5823        <register>
5824          <name>RAM0_STATUS</name>
5825          <description>RAM 0 status</description>
5826          <addressOffset>0x1304</addressOffset>
5827          <size>32</size>
5828          <access>read-only</access>
5829          <resetValue>0x1</resetValue>
5830          <resetMask>0x1</resetMask>
5831          <fields>
5832            <field>
5833              <name>WB_EMPTY</name>
5834              <description>Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode.
5835'0': Write buffer NOT empty.
5836'1': Write buffer empty.
5837
5838Note: the SRAM controller write buffer is only used when ECC checking is enabled. (RAMi_CTL.ECC_EN is '1').</description>
5839              <bitRange>[0:0]</bitRange>
5840              <access>read-only</access>
5841            </field>
5842          </fields>
5843        </register>
5844        <register>
5845          <dim>16</dim>
5846          <dimIncrement>4</dimIncrement>
5847          <name>RAM0_PWR_MACRO_CTL[%s]</name>
5848          <description>RAM 0 power control</description>
5849          <addressOffset>0x1340</addressOffset>
5850          <size>32</size>
5851          <access>read-write</access>
5852          <resetValue>0xFA050003</resetValue>
5853          <resetMask>0xFFFF0003</resetMask>
5854          <fields>
5855            <field>
5856              <name>PWR_MODE</name>
5857              <description>SRAM Power mode.</description>
5858              <bitRange>[1:0]</bitRange>
5859              <access>read-write</access>
5860              <enumeratedValues>
5861                <enumeratedValue>
5862                  <name>OFF</name>
5863                  <description>Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.</description>
5864                  <value>0</value>
5865                </enumeratedValue>
5866                <enumeratedValue>
5867                  <name>RSVD</name>
5868                  <description>undefined</description>
5869                  <value>1</value>
5870                </enumeratedValue>
5871                <enumeratedValue>
5872                  <name>RETAINED</name>
5873                  <description>Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents.
5874The SRAM contents will be retained in DeepSleep system power mode.</description>
5875                  <value>2</value>
5876                </enumeratedValue>
5877                <enumeratedValue>
5878                  <name>ENABLED</name>
5879                  <description>Enable SRAM for regular operation.
5880The SRAM contents will be retained in DeepSleep system power mode.</description>
5881                  <value>3</value>
5882                </enumeratedValue>
5883              </enumeratedValues>
5884            </field>
5885            <field>
5886              <name>VECTKEYSTAT</name>
5887              <description>Register key (to prevent accidental writes).
5888- Should be written with a 0x05fa key value for the write to take effect.
5889- Always reads as 0xfa05.
5890
5891Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.</description>
5892              <bitRange>[31:16]</bitRange>
5893              <access>read-only</access>
5894            </field>
5895          </fields>
5896        </register>
5897        <register>
5898          <name>RAM1_CTL0</name>
5899          <description>RAM 1 control</description>
5900          <addressOffset>0x1380</addressOffset>
5901          <size>32</size>
5902          <access>read-write</access>
5903          <resetValue>0x30001</resetValue>
5904          <resetMask>0x70303</resetMask>
5905          <fields>
5906            <field>
5907              <name>SLOW_WS</name>
5908              <description>See RAM0_CTL.</description>
5909              <bitRange>[1:0]</bitRange>
5910              <access>read-write</access>
5911            </field>
5912            <field>
5913              <name>FAST_WS</name>
5914              <description>See RAM0_CTL.</description>
5915              <bitRange>[9:8]</bitRange>
5916              <access>read-write</access>
5917            </field>
5918            <field>
5919              <name>ECC_EN</name>
5920              <description>See RAM0_CTL.</description>
5921              <bitRange>[16:16]</bitRange>
5922              <access>read-write</access>
5923            </field>
5924            <field>
5925              <name>ECC_AUTO_CORRECT</name>
5926              <description>See RAM0_CTL.</description>
5927              <bitRange>[17:17]</bitRange>
5928              <access>read-write</access>
5929            </field>
5930            <field>
5931              <name>ECC_INJ_EN</name>
5932              <description>See RAM0_CTL.</description>
5933              <bitRange>[18:18]</bitRange>
5934              <access>read-write</access>
5935            </field>
5936          </fields>
5937        </register>
5938        <register>
5939          <name>RAM1_STATUS</name>
5940          <description>RAM 1 status</description>
5941          <addressOffset>0x1384</addressOffset>
5942          <size>32</size>
5943          <access>read-only</access>
5944          <resetValue>0x1</resetValue>
5945          <resetMask>0x1</resetMask>
5946          <fields>
5947            <field>
5948              <name>WB_EMPTY</name>
5949              <description>See RAM0_STATUS.</description>
5950              <bitRange>[0:0]</bitRange>
5951              <access>read-only</access>
5952            </field>
5953          </fields>
5954        </register>
5955        <register>
5956          <name>RAM1_PWR_CTL</name>
5957          <description>RAM 1 power control</description>
5958          <addressOffset>0x1388</addressOffset>
5959          <size>32</size>
5960          <access>read-write</access>
5961          <resetValue>0xFA050003</resetValue>
5962          <resetMask>0xFFFF0003</resetMask>
5963          <fields>
5964            <field>
5965              <name>PWR_MODE</name>
5966              <description>Power mode.</description>
5967              <bitRange>[1:0]</bitRange>
5968              <access>read-write</access>
5969              <enumeratedValues>
5970                <enumeratedValue>
5971                  <name>OFF</name>
5972                  <description>See RAM0_PWR_MACRO_CTL.</description>
5973                  <value>0</value>
5974                </enumeratedValue>
5975                <enumeratedValue>
5976                  <name>RSVD</name>
5977                  <description>undefined</description>
5978                  <value>1</value>
5979                </enumeratedValue>
5980                <enumeratedValue>
5981                  <name>RETAINED</name>
5982                  <description>See RAM0_PWR_MACRO_CTL.</description>
5983                  <value>2</value>
5984                </enumeratedValue>
5985                <enumeratedValue>
5986                  <name>ENABLED</name>
5987                  <description>See RAM0_PWR_MACRO_CTL.</description>
5988                  <value>3</value>
5989                </enumeratedValue>
5990              </enumeratedValues>
5991            </field>
5992            <field>
5993              <name>VECTKEYSTAT</name>
5994              <description>See RAM0_PWR_MACRO_CTL.</description>
5995              <bitRange>[31:16]</bitRange>
5996              <access>read-only</access>
5997            </field>
5998          </fields>
5999        </register>
6000        <register>
6001          <name>RAM2_CTL0</name>
6002          <description>RAM 2 control</description>
6003          <addressOffset>0x13A0</addressOffset>
6004          <size>32</size>
6005          <access>read-write</access>
6006          <resetValue>0x30001</resetValue>
6007          <resetMask>0x70303</resetMask>
6008          <fields>
6009            <field>
6010              <name>SLOW_WS</name>
6011              <description>See RAM0_CTL.</description>
6012              <bitRange>[1:0]</bitRange>
6013              <access>read-write</access>
6014            </field>
6015            <field>
6016              <name>FAST_WS</name>
6017              <description>See RAM0_CTL.</description>
6018              <bitRange>[9:8]</bitRange>
6019              <access>read-write</access>
6020            </field>
6021            <field>
6022              <name>ECC_EN</name>
6023              <description>See RAM0_CTL.</description>
6024              <bitRange>[16:16]</bitRange>
6025              <access>read-write</access>
6026            </field>
6027            <field>
6028              <name>ECC_AUTO_CORRECT</name>
6029              <description>See RAM0_CTL.</description>
6030              <bitRange>[17:17]</bitRange>
6031              <access>read-write</access>
6032            </field>
6033            <field>
6034              <name>ECC_INJ_EN</name>
6035              <description>See RAM0_CTL.</description>
6036              <bitRange>[18:18]</bitRange>
6037              <access>read-write</access>
6038            </field>
6039          </fields>
6040        </register>
6041        <register>
6042          <name>RAM2_STATUS</name>
6043          <description>RAM 2 status</description>
6044          <addressOffset>0x13A4</addressOffset>
6045          <size>32</size>
6046          <access>read-only</access>
6047          <resetValue>0x1</resetValue>
6048          <resetMask>0x1</resetMask>
6049          <fields>
6050            <field>
6051              <name>WB_EMPTY</name>
6052              <description>See RAM0_STATUS.</description>
6053              <bitRange>[0:0]</bitRange>
6054              <access>read-only</access>
6055            </field>
6056          </fields>
6057        </register>
6058        <register>
6059          <name>RAM2_PWR_CTL</name>
6060          <description>RAM 2 power control</description>
6061          <addressOffset>0x13A8</addressOffset>
6062          <size>32</size>
6063          <access>read-write</access>
6064          <resetValue>0xFA050003</resetValue>
6065          <resetMask>0xFFFF0003</resetMask>
6066          <fields>
6067            <field>
6068              <name>PWR_MODE</name>
6069              <description>Power mode.</description>
6070              <bitRange>[1:0]</bitRange>
6071              <access>read-write</access>
6072              <enumeratedValues>
6073                <enumeratedValue>
6074                  <name>OFF</name>
6075                  <description>See RAM0_PWR_MACRO_CTL.</description>
6076                  <value>0</value>
6077                </enumeratedValue>
6078                <enumeratedValue>
6079                  <name>RSVD</name>
6080                  <description>undefined</description>
6081                  <value>1</value>
6082                </enumeratedValue>
6083                <enumeratedValue>
6084                  <name>RETAINED</name>
6085                  <description>See RAM0_PWR_MACRO_CTL.</description>
6086                  <value>2</value>
6087                </enumeratedValue>
6088                <enumeratedValue>
6089                  <name>ENABLED</name>
6090                  <description>See RAM0_PWR_MACRO_CTL.</description>
6091                  <value>3</value>
6092                </enumeratedValue>
6093              </enumeratedValues>
6094            </field>
6095            <field>
6096              <name>VECTKEYSTAT</name>
6097              <description>See RAM0_PWR_MACRO_CTL.</description>
6098              <bitRange>[31:16]</bitRange>
6099              <access>read-only</access>
6100            </field>
6101          </fields>
6102        </register>
6103        <register>
6104          <name>RAM_PWR_DELAY_CTL</name>
6105          <description>Power up delay used for all SRAM power domains</description>
6106          <addressOffset>0x13C0</addressOffset>
6107          <size>32</size>
6108          <access>read-write</access>
6109          <resetValue>0x96</resetValue>
6110          <resetMask>0x3FF</resetMask>
6111          <fields>
6112            <field>
6113              <name>UP</name>
6114              <description>Number clock cycles (clk_slow) delay needed after power domain power up</description>
6115              <bitRange>[9:0]</bitRange>
6116              <access>read-write</access>
6117            </field>
6118          </fields>
6119        </register>
6120        <register>
6121          <name>ROM_CTL</name>
6122          <description>ROM control</description>
6123          <addressOffset>0x13C4</addressOffset>
6124          <size>32</size>
6125          <access>read-write</access>
6126          <resetValue>0x1</resetValue>
6127          <resetMask>0x303</resetMask>
6128          <fields>
6129            <field>
6130              <name>SLOW_WS</name>
6131              <description>Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
6132
6133Timing paths to and from the memory have a (fixed) minimum duration  that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met.
6134ROM_CTL.SLOW_WS = '0' when clk_hf &lt;=100 MHz.
6135ROM_CTL.SLOW_WS = '1' when 100MHz &lt; clk_hf &lt;=clk_hf_max.
6136Note: clk_hf_max depends on the target device. Refer datasheet.</description>
6137              <bitRange>[1:0]</bitRange>
6138              <access>read-write</access>
6139            </field>
6140            <field>
6141              <name>FAST_WS</name>
6142              <description>Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
6143ROM_CTL.FAST_WS = '0' when clk_hf &lt;= clk_hf_max.</description>
6144              <bitRange>[9:8]</bitRange>
6145              <access>read-write</access>
6146            </field>
6147          </fields>
6148        </register>
6149        <register>
6150          <name>ECC_CTL</name>
6151          <description>ECC control</description>
6152          <addressOffset>0x13C8</addressOffset>
6153          <size>32</size>
6154          <access>read-write</access>
6155          <resetValue>0x0</resetValue>
6156          <resetMask>0xFFFFFFFF</resetMask>
6157          <fields>
6158            <field>
6159              <name>WORD_ADDR</name>
6160              <description>Specifies the word address where an error will be injected.
6161- On a write transfer to this SRAM address and when the corresponding RAM0/RAM1/RAM2_CTL0.ECC_INJ_EN bit is '1', the parity (PARITY) is injected.
6162This field needs to be written with the offset address within the memory, divided by 4.
6163For example, if the RAM1 start address is 0x08010000, and an error is to be injected to address 0x08010040, then this field needs to configured to 0x000010.</description>
6164              <bitRange>[24:0]</bitRange>
6165              <access>read-write</access>
6166            </field>
6167            <field>
6168              <name>PARITY</name>
6169              <description>ECC parity to use for ECC error injection at address WORD_ADDR.</description>
6170              <bitRange>[31:25]</bitRange>
6171              <access>read-write</access>
6172            </field>
6173          </fields>
6174        </register>
6175        <register>
6176          <name>PRODUCT_ID</name>
6177          <description>Product identifier and version (same as CoreSight RomTables)</description>
6178          <addressOffset>0x1400</addressOffset>
6179          <size>32</size>
6180          <access>read-only</access>
6181          <resetValue>0x0</resetValue>
6182          <resetMask>0xFFF</resetMask>
6183          <fields>
6184            <field>
6185              <name>FAMILY_ID</name>
6186              <description>Family ID. Common ID for a product family.</description>
6187              <bitRange>[11:0]</bitRange>
6188              <access>read-only</access>
6189            </field>
6190            <field>
6191              <name>MAJOR_REV</name>
6192              <description>Major Revision, starts with 1, increments with all layer tape-out (implemented with metal ECO-able  tie-off)</description>
6193              <bitRange>[19:16]</bitRange>
6194              <access>read-only</access>
6195            </field>
6196            <field>
6197              <name>MINOR_REV</name>
6198              <description>Minor Revision, starts with 1, increments with metal layer only tape-out (implemented with metal ECO-able  tie-off)</description>
6199              <bitRange>[23:20]</bitRange>
6200              <access>read-only</access>
6201            </field>
6202          </fields>
6203        </register>
6204        <register>
6205          <name>DP_STATUS</name>
6206          <description>Debug port status</description>
6207          <addressOffset>0x1410</addressOffset>
6208          <size>32</size>
6209          <access>read-only</access>
6210          <resetValue>0x4</resetValue>
6211          <resetMask>0x7</resetMask>
6212          <fields>
6213            <field>
6214              <name>SWJ_CONNECTED</name>
6215              <description>Specifies if the SWJ debug port is connected; i.e. debug host interface is active:
6216'0': Not connected/not active.
6217'1': Connected/active.</description>
6218              <bitRange>[0:0]</bitRange>
6219              <access>read-only</access>
6220            </field>
6221            <field>
6222              <name>SWJ_DEBUG_EN</name>
6223              <description>Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on:
6224'0': Disabled.
6225'1': Enabled.</description>
6226              <bitRange>[1:1]</bitRange>
6227              <access>read-only</access>
6228            </field>
6229            <field>
6230              <name>SWJ_JTAG_SEL</name>
6231              <description>Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected).
6232'0': SWD selected.
6233'1': JTAG selected.</description>
6234              <bitRange>[2:2]</bitRange>
6235              <access>read-only</access>
6236            </field>
6237          </fields>
6238        </register>
6239        <register>
6240          <name>AP_CTL</name>
6241          <description>Access port control</description>
6242          <addressOffset>0x1414</addressOffset>
6243          <size>32</size>
6244          <access>read-write</access>
6245          <resetValue>0x0</resetValue>
6246          <resetMask>0x70007</resetMask>
6247          <fields>
6248            <field>
6249              <name>CM0_ENABLE</name>
6250              <description>Enables the CM0 AP interface:
6251'0': Disabled.
6252'1': Enabled.</description>
6253              <bitRange>[0:0]</bitRange>
6254              <access>read-write</access>
6255            </field>
6256            <field>
6257              <name>CM4_ENABLE</name>
6258              <description>Enables the CM4 AP interface:
6259'0': Disabled.
6260'1': Enabled.</description>
6261              <bitRange>[1:1]</bitRange>
6262              <access>read-write</access>
6263            </field>
6264            <field>
6265              <name>SYS_ENABLE</name>
6266              <description>Enables the system AP interface:
6267'0': Disabled.
6268'1': Enabled.</description>
6269              <bitRange>[2:2]</bitRange>
6270              <access>read-write</access>
6271            </field>
6272            <field>
6273              <name>CM0_DISABLE</name>
6274              <description>Disables the CM0 AP interface:
6275'0': Enabled.
6276'1': Disabled.
6277
6278Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'.</description>
6279              <bitRange>[16:16]</bitRange>
6280              <access>read-write</access>
6281            </field>
6282            <field>
6283              <name>CM4_DISABLE</name>
6284              <description>Disables the CM4 AP interface:
6285'0': Enabled.
6286'1': Disabled.
6287
6288Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM4_DISABLE is '0' and CM4_ENABLE is '1'.</description>
6289              <bitRange>[17:17]</bitRange>
6290              <access>read-write</access>
6291            </field>
6292            <field>
6293              <name>SYS_DISABLE</name>
6294              <description>Disables the system AP interface:
6295'0': Enabled.
6296'1': Disabled.
6297
6298Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'.</description>
6299              <bitRange>[18:18]</bitRange>
6300              <access>read-write</access>
6301            </field>
6302          </fields>
6303        </register>
6304        <register>
6305          <name>BUFF_CTL</name>
6306          <description>Buffer control</description>
6307          <addressOffset>0x1500</addressOffset>
6308          <size>32</size>
6309          <access>read-write</access>
6310          <resetValue>0x1</resetValue>
6311          <resetMask>0x1</resetMask>
6312          <fields>
6313            <field>
6314              <name>WRITE_BUFF</name>
6315              <description>Specifies if write transfer can be buffered in the bus infrastructure bridges:
6316'0': Write transfers are not buffered, independent of the transfer's bufferable attribute.
6317'1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write.</description>
6318              <bitRange>[0:0]</bitRange>
6319              <access>read-write</access>
6320            </field>
6321          </fields>
6322        </register>
6323        <register>
6324          <name>SYSTICK_CTL</name>
6325          <description>SysTick timer control</description>
6326          <addressOffset>0x1600</addressOffset>
6327          <size>32</size>
6328          <access>read-write</access>
6329          <resetValue>0x40000147</resetValue>
6330          <resetMask>0xC3FFFFFF</resetMask>
6331          <fields>
6332            <field>
6333              <name>TENMS</name>
6334              <description>Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327.</description>
6335              <bitRange>[23:0]</bitRange>
6336              <access>read-write</access>
6337            </field>
6338            <field>
6339              <name>CLOCK_SOURCE</name>
6340              <description>Specifies an external clock source:
6341'0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise).
6342'1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock.
6343o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected.
6344'3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo').
6345
6346Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used.
6347Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source.</description>
6348              <bitRange>[25:24]</bitRange>
6349              <access>read-write</access>
6350            </field>
6351            <field>
6352              <name>SKEW</name>
6353              <description>Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock:
6354'0': Precise.
6355'1': Imprecise.</description>
6356              <bitRange>[30:30]</bitRange>
6357              <access>read-write</access>
6358            </field>
6359            <field>
6360              <name>NOREF</name>
6361              <description>Specifies if an external clock source is provided:
6362'0': An external clock source is provided.
6363'1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source.</description>
6364              <bitRange>[31:31]</bitRange>
6365              <access>read-write</access>
6366            </field>
6367          </fields>
6368        </register>
6369        <register>
6370          <name>MBIST_STAT</name>
6371          <description>Memory BIST status</description>
6372          <addressOffset>0x1704</addressOffset>
6373          <size>32</size>
6374          <access>read-only</access>
6375          <resetValue>0x0</resetValue>
6376          <resetMask>0x3</resetMask>
6377          <fields>
6378            <field>
6379              <name>SFP_READY</name>
6380              <description>Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0.</description>
6381              <bitRange>[0:0]</bitRange>
6382              <access>read-only</access>
6383            </field>
6384            <field>
6385              <name>SFP_FAIL</name>
6386              <description>Report status of the BIST run, only valid if SFP_READY=1</description>
6387              <bitRange>[1:1]</bitRange>
6388              <access>read-only</access>
6389            </field>
6390          </fields>
6391        </register>
6392        <register>
6393          <name>CAL_SUP_SET</name>
6394          <description>Calibration support set and read</description>
6395          <addressOffset>0x1800</addressOffset>
6396          <size>32</size>
6397          <access>read-write</access>
6398          <resetValue>0x0</resetValue>
6399          <resetMask>0xFFFFFFFF</resetMask>
6400          <fields>
6401            <field>
6402              <name>DATA</name>
6403              <description>Read without side effect, write 1 to set</description>
6404              <bitRange>[31:0]</bitRange>
6405              <access>read-write</access>
6406            </field>
6407          </fields>
6408        </register>
6409        <register>
6410          <name>CAL_SUP_CLR</name>
6411          <description>Calibration support clear and reset</description>
6412          <addressOffset>0x1804</addressOffset>
6413          <size>32</size>
6414          <access>read-write</access>
6415          <resetValue>0x0</resetValue>
6416          <resetMask>0xFFFFFFFF</resetMask>
6417          <fields>
6418            <field>
6419              <name>DATA</name>
6420              <description>Read side effect: when read all bits are cleared, write 1 to clear a specific bit
6421Note: no exception for the debug host, it also causes the read side effect</description>
6422              <bitRange>[31:0]</bitRange>
6423              <access>read-write</access>
6424            </field>
6425          </fields>
6426        </register>
6427        <register>
6428          <name>CM0_PC_CTL</name>
6429          <description>CM0+ protection context control</description>
6430          <addressOffset>0x2000</addressOffset>
6431          <size>32</size>
6432          <access>read-write</access>
6433          <resetValue>0x0</resetValue>
6434          <resetMask>0xF</resetMask>
6435          <fields>
6436            <field>
6437              <name>VALID</name>
6438              <description>Valid fields for the protection context handler CM0_PCi_HANDLER registers:
6439Bit 0: Valid field for CM0_PC0_HANDLER.
6440Bit 1: Valid field for CM0_PC1_HANDLER.
6441Bit 2: Valid field for CM0_PC2_HANDLER.
6442Bit 3: Valid field for CM0_PC3_HANDLER.</description>
6443              <bitRange>[3:0]</bitRange>
6444              <access>read-write</access>
6445            </field>
6446          </fields>
6447        </register>
6448        <register>
6449          <name>CM0_PC0_HANDLER</name>
6450          <description>CM0+ protection context 0 handler</description>
6451          <addressOffset>0x2040</addressOffset>
6452          <size>32</size>
6453          <access>read-write</access>
6454          <resetValue>0x0</resetValue>
6455          <resetMask>0xFFFFFFFF</resetMask>
6456          <fields>
6457            <field>
6458              <name>ADDR</name>
6459              <description>Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt.</description>
6460              <bitRange>[31:0]</bitRange>
6461              <access>read-write</access>
6462            </field>
6463          </fields>
6464        </register>
6465        <register>
6466          <name>CM0_PC1_HANDLER</name>
6467          <description>CM0+ protection context 1 handler</description>
6468          <addressOffset>0x2044</addressOffset>
6469          <size>32</size>
6470          <access>read-write</access>
6471          <resetValue>0x0</resetValue>
6472          <resetMask>0xFFFFFFFF</resetMask>
6473          <fields>
6474            <field>
6475              <name>ADDR</name>
6476              <description>Address of the protection context 1 handler.</description>
6477              <bitRange>[31:0]</bitRange>
6478              <access>read-write</access>
6479            </field>
6480          </fields>
6481        </register>
6482        <register>
6483          <name>CM0_PC2_HANDLER</name>
6484          <description>CM0+ protection context 2 handler</description>
6485          <addressOffset>0x2048</addressOffset>
6486          <size>32</size>
6487          <access>read-write</access>
6488          <resetValue>0x0</resetValue>
6489          <resetMask>0xFFFFFFFF</resetMask>
6490          <fields>
6491            <field>
6492              <name>ADDR</name>
6493              <description>Address of the protection context 2 handler.</description>
6494              <bitRange>[31:0]</bitRange>
6495              <access>read-write</access>
6496            </field>
6497          </fields>
6498        </register>
6499        <register>
6500          <name>CM0_PC3_HANDLER</name>
6501          <description>CM0+ protection context 3 handler</description>
6502          <addressOffset>0x204C</addressOffset>
6503          <size>32</size>
6504          <access>read-write</access>
6505          <resetValue>0x0</resetValue>
6506          <resetMask>0xFFFFFFFF</resetMask>
6507          <fields>
6508            <field>
6509              <name>ADDR</name>
6510              <description>Address of the protection context 3 handler.</description>
6511              <bitRange>[31:0]</bitRange>
6512              <access>read-write</access>
6513            </field>
6514          </fields>
6515        </register>
6516        <register>
6517          <name>PROTECTION</name>
6518          <description>Protection status</description>
6519          <addressOffset>0x20C4</addressOffset>
6520          <size>32</size>
6521          <access>read-write</access>
6522          <resetValue>0x0</resetValue>
6523          <resetMask>0x7</resetMask>
6524          <fields>
6525            <field>
6526              <name>STATE</name>
6527              <description>Protection state:
6528'0': UNKNOWN.
6529'1': VIRGIN.
6530'2': NORMAL.
6531'3': SECURE.
6532'4': DEAD.
6533
6534The following state transitions are allowed (and enforced by HW):
6535- UNKNOWN =&gt; VIRGIN/NORMAL/SECURE/DEAD
6536- NORMAL =&gt; DEAD
6537- SECURE =&gt; DEAD
6538An attempt to make a NOT allowed state transition will NOT affect this register field.</description>
6539              <bitRange>[2:0]</bitRange>
6540              <access>read-write</access>
6541            </field>
6542          </fields>
6543        </register>
6544        <register>
6545          <name>TRIM_ROM_CTL</name>
6546          <description>ROM trim control</description>
6547          <addressOffset>0x2100</addressOffset>
6548          <size>32</size>
6549          <access>read-write</access>
6550          <resetValue>0x0</resetValue>
6551          <resetMask>0xFFFFFFFF</resetMask>
6552          <fields>
6553            <field>
6554              <name>TRIM</name>
6555              <description>N/A</description>
6556              <bitRange>[31:0]</bitRange>
6557              <access>read-write</access>
6558            </field>
6559          </fields>
6560        </register>
6561        <register>
6562          <name>TRIM_RAM_CTL</name>
6563          <description>RAM trim control</description>
6564          <addressOffset>0x2104</addressOffset>
6565          <size>32</size>
6566          <access>read-write</access>
6567          <resetValue>0x0</resetValue>
6568          <resetMask>0xFFFFFFFF</resetMask>
6569          <fields>
6570            <field>
6571              <name>TRIM</name>
6572              <description>N/A</description>
6573              <bitRange>[31:0]</bitRange>
6574              <access>read-write</access>
6575            </field>
6576          </fields>
6577        </register>
6578        <register>
6579          <dim>1023</dim>
6580          <dimIncrement>4</dimIncrement>
6581          <name>CM0_SYSTEM_INT_CTL[%s]</name>
6582          <description>CM0+ system interrupt control</description>
6583          <addressOffset>0x8000</addressOffset>
6584          <size>32</size>
6585          <access>read-write</access>
6586          <resetValue>0x0</resetValue>
6587          <resetMask>0x80000000</resetMask>
6588          <fields>
6589            <field>
6590              <name>CPU_INT_IDX</name>
6591              <description>CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'.
6592
6593Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.</description>
6594              <bitRange>[2:0]</bitRange>
6595              <access>read-write</access>
6596            </field>
6597            <field>
6598              <name>CPU_INT_VALID</name>
6599              <description>Interrupt enable:
6600'0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt.
6601'1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX.
6602
6603Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.</description>
6604              <bitRange>[31:31]</bitRange>
6605              <access>read-write</access>
6606            </field>
6607          </fields>
6608        </register>
6609        <register>
6610          <dim>1023</dim>
6611          <dimIncrement>4</dimIncrement>
6612          <name>CM4_SYSTEM_INT_CTL[%s]</name>
6613          <description>CM4 system interrupt control</description>
6614          <addressOffset>0xA000</addressOffset>
6615          <size>32</size>
6616          <access>read-write</access>
6617          <resetValue>0x0</resetValue>
6618          <resetMask>0x80000000</resetMask>
6619          <fields>
6620            <field>
6621              <name>CPU_INT_IDX</name>
6622              <description>N/A</description>
6623              <bitRange>[2:0]</bitRange>
6624              <access>read-write</access>
6625            </field>
6626            <field>
6627              <name>CPU_INT_VALID</name>
6628              <description>N/A</description>
6629              <bitRange>[31:31]</bitRange>
6630              <access>read-write</access>
6631            </field>
6632          </fields>
6633        </register>
6634      </registers>
6635    </peripheral>
6636    <peripheral>
6637      <name>FAULT</name>
6638      <description>Fault structures</description>
6639      <baseAddress>0x40210000</baseAddress>
6640      <addressBlock>
6641        <offset>0</offset>
6642        <size>65536</size>
6643        <usage>registers</usage>
6644      </addressBlock>
6645      <registers>
6646        <cluster>
6647          <dim>4</dim>
6648          <dimIncrement>256</dimIncrement>
6649          <name>STRUCT[%s]</name>
6650          <description>Fault structure</description>
6651          <addressOffset>0x00000000</addressOffset>
6652          <register>
6653            <name>CTL</name>
6654            <description>Fault control</description>
6655            <addressOffset>0x0</addressOffset>
6656            <size>32</size>
6657            <access>read-write</access>
6658            <resetValue>0x0</resetValue>
6659            <resetMask>0x7</resetMask>
6660            <fields>
6661              <field>
6662                <name>TR_EN</name>
6663                <description>Trigger output enable:
6664'0': Disabled. The trigger output 'tr_fault' is '0'.
6665'1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3).</description>
6666                <bitRange>[0:0]</bitRange>
6667                <access>read-write</access>
6668              </field>
6669              <field>
6670                <name>OUT_EN</name>
6671                <description>IO output signal enable:
6672'0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'.
6673'1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'.</description>
6674                <bitRange>[1:1]</bitRange>
6675                <access>read-write</access>
6676              </field>
6677              <field>
6678                <name>RESET_REQ_EN</name>
6679                <description>Reset request enable:
6680'0': Disabled.
6681'1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis).
6682
6683The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal.</description>
6684                <bitRange>[2:2]</bitRange>
6685                <access>read-write</access>
6686              </field>
6687            </fields>
6688          </register>
6689          <register>
6690            <name>STATUS</name>
6691            <description>Fault status</description>
6692            <addressOffset>0xC</addressOffset>
6693            <size>32</size>
6694            <access>read-write</access>
6695            <resetValue>0x0</resetValue>
6696            <resetMask>0x80000000</resetMask>
6697            <fields>
6698              <field>
6699                <name>IDX</name>
6700                <description>The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below.
6701
6702Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'.</description>
6703                <bitRange>[6:0]</bitRange>
6704                <access>read-write</access>
6705              </field>
6706              <field>
6707                <name>VALID</name>
6708                <description>Valid indication:
6709'0': Invalid.
6710'1': Valid. STATUS.IDX, DATA0, ..., DATA3 specify the fault.
6711
6712Note: Typically, HW sets this field to '1' (on an activated HW fault source that is 'enabled' by the MASK registers) and SW clears this field to '0' (typically by boot code SW (after a warm system reset, when the fault is handled). In this typical use case scenario, the HW source fault data is simultaneously captured into DATA0, ..., DATA3 when the VALID field is set to '1'.
6713
6714An exceptional SW use case scenario is identified as well. In this scenario, SW sets this field to '1' with a fault source index different to one of the defined HW fault sources. SW update is not restricted by the MASK registers). In both use case scenarios, the following holds:
6715- STATUS.IDX, DATA0, ..., DATA3 can only be written when STATUS.VALID is '0'; the fault structure is not in use yet. Writing STATUS.VALID to '1' effectively locks the fault structure (until SW clears STATUS.VALID to '0'). This restriction requires a SW update to sequentially update the DATA registers followed by an update of the STATUS register.
6716
6717Note: For the exceptional SW use case, sequential updates to the DATA and STATUS registers may be 'interrupted' by a HW fault capture. In this case, the SW DATA register updates are overwritten by the HW update (and the STATUS.IDX field will reflect the HW capture)</description>
6718                <bitRange>[31:31]</bitRange>
6719                <access>read-write</access>
6720              </field>
6721            </fields>
6722          </register>
6723          <register>
6724            <dim>4</dim>
6725            <dimIncrement>4</dimIncrement>
6726            <name>DATA[%s]</name>
6727            <description>Fault data</description>
6728            <addressOffset>0x10</addressOffset>
6729            <size>32</size>
6730            <access>read-write</access>
6731            <resetValue>0x0</resetValue>
6732            <resetMask>0x0</resetMask>
6733            <fields>
6734              <field>
6735                <name>DATA</name>
6736                <description>Captured fault source data.
6737
6738Note: the DATA registers can only be written when STATUS.VALID is '0'.
6739
6740Note: the fault source index STATUS.IDX specifies the format of the DATA registers.</description>
6741                <bitRange>[31:0]</bitRange>
6742                <access>read-write</access>
6743              </field>
6744            </fields>
6745          </register>
6746          <register>
6747            <name>PENDING0</name>
6748            <description>Fault pending 0</description>
6749            <addressOffset>0x40</addressOffset>
6750            <size>32</size>
6751            <access>read-only</access>
6752            <resetValue>0x0</resetValue>
6753            <resetMask>0x0</resetMask>
6754            <fields>
6755              <field>
6756                <name>SOURCE</name>
6757                <description>This field specifies the following sources:
6758Bit 0: CM0 MPU.
6759Bit 1: CRYPTO MPU.
6760Bit 2: DW 0 MPU.
6761Bit 3: DW 1 MPU.
6762Bit 4: DMA controller MPU.
6763...
6764Bit 15: DAP MPU.
6765Bit 16: CM4 system bus MPU.
6766Bit 17: CM4 code bus MPU (for non FLASH controller accesses).
6767Bit 18: CM4 code bus MPU (for FLASH controller accesses).</description>
6768                <bitRange>[31:0]</bitRange>
6769                <access>read-only</access>
6770              </field>
6771            </fields>
6772          </register>
6773          <register>
6774            <name>PENDING1</name>
6775            <description>Fault pending 1</description>
6776            <addressOffset>0x44</addressOffset>
6777            <size>32</size>
6778            <access>read-only</access>
6779            <resetValue>0x0</resetValue>
6780            <resetMask>0x0</resetMask>
6781            <fields>
6782              <field>
6783                <name>SOURCE</name>
6784                <description>This field specifies the following sources:
6785Bit 0: Peripheral group 0 PPU.
6786Bit 1: Peripheral group 1 PPU.
6787Bit 2: Peripheral group 2 PPU.
6788Bit 3: Peripheral group 3 PPU.
6789Bit 4: Peripheral group 4 PPU.
6790Bit 5: Peripheral group 5 PPU.
6791Bit 6: Peripheral group 6 PPU.
6792Bit 7: Peripheral group 7 PPU.
6793...
6794Bit 15: Peripheral group 15 PPU.
6795
6796Bit 16 - 31: See STATUS register.</description>
6797                <bitRange>[31:0]</bitRange>
6798                <access>read-only</access>
6799              </field>
6800            </fields>
6801          </register>
6802          <register>
6803            <name>PENDING2</name>
6804            <description>Fault pending 2</description>
6805            <addressOffset>0x48</addressOffset>
6806            <size>32</size>
6807            <access>read-only</access>
6808            <resetValue>0x0</resetValue>
6809            <resetMask>0x0</resetMask>
6810            <fields>
6811              <field>
6812                <name>SOURCE</name>
6813                <description>This field specifies the following sources:
6814Bit 0 - 31: See STATUS register.</description>
6815                <bitRange>[31:0]</bitRange>
6816                <access>read-only</access>
6817              </field>
6818            </fields>
6819          </register>
6820          <register>
6821            <name>MASK0</name>
6822            <description>Fault mask 0</description>
6823            <addressOffset>0x50</addressOffset>
6824            <size>32</size>
6825            <access>read-write</access>
6826            <resetValue>0x0</resetValue>
6827            <resetMask>0xFFFFFFFF</resetMask>
6828            <fields>
6829              <field>
6830                <name>SOURCE</name>
6831                <description>Fault source enables:
6832Bits 31-0: Fault sources 31 to 0.</description>
6833                <bitRange>[31:0]</bitRange>
6834                <access>read-write</access>
6835              </field>
6836            </fields>
6837          </register>
6838          <register>
6839            <name>MASK1</name>
6840            <description>Fault mask 1</description>
6841            <addressOffset>0x54</addressOffset>
6842            <size>32</size>
6843            <access>read-write</access>
6844            <resetValue>0x0</resetValue>
6845            <resetMask>0xFFFFFFFF</resetMask>
6846            <fields>
6847              <field>
6848                <name>SOURCE</name>
6849                <description>Fault source enables:
6850Bits 31-0: Fault sources 63 to 32.</description>
6851                <bitRange>[31:0]</bitRange>
6852                <access>read-write</access>
6853              </field>
6854            </fields>
6855          </register>
6856          <register>
6857            <name>MASK2</name>
6858            <description>Fault mask 2</description>
6859            <addressOffset>0x58</addressOffset>
6860            <size>32</size>
6861            <access>read-write</access>
6862            <resetValue>0x0</resetValue>
6863            <resetMask>0xFFFFFFFF</resetMask>
6864            <fields>
6865              <field>
6866                <name>SOURCE</name>
6867                <description>Fault source enables:
6868Bits 31-0: Fault sources 95 to 64.</description>
6869                <bitRange>[31:0]</bitRange>
6870                <access>read-write</access>
6871              </field>
6872            </fields>
6873          </register>
6874          <register>
6875            <name>INTR</name>
6876            <description>Interrupt</description>
6877            <addressOffset>0xC0</addressOffset>
6878            <size>32</size>
6879            <access>read-write</access>
6880            <resetValue>0x0</resetValue>
6881            <resetMask>0x1</resetMask>
6882            <fields>
6883              <field>
6884                <name>FAULT</name>
6885                <description>This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured:
6886- STATUS.VALID is set to '1'.
6887- STATUS.IDX specifies the fault source index.
6888- DATA0 through DATA3 captures the fault source data.
6889
6890SW writes a '1' to this field to clear the interrupt cause to '0'. SW clear STATUS.VALID to '0' to enable capture of the next fault. Note that when there is an enabled pending fault source, the pending fault source is captured immediately and INTR.FAULT is immediately activated (set to '1').</description>
6891                <bitRange>[0:0]</bitRange>
6892                <access>read-write</access>
6893              </field>
6894            </fields>
6895          </register>
6896          <register>
6897            <name>INTR_SET</name>
6898            <description>Interrupt set</description>
6899            <addressOffset>0xC4</addressOffset>
6900            <size>32</size>
6901            <access>read-write</access>
6902            <resetValue>0x0</resetValue>
6903            <resetMask>0x1</resetMask>
6904            <fields>
6905              <field>
6906                <name>FAULT</name>
6907                <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
6908                <bitRange>[0:0]</bitRange>
6909                <access>read-write</access>
6910              </field>
6911            </fields>
6912          </register>
6913          <register>
6914            <name>INTR_MASK</name>
6915            <description>Interrupt mask</description>
6916            <addressOffset>0xC8</addressOffset>
6917            <size>32</size>
6918            <access>read-write</access>
6919            <resetValue>0x0</resetValue>
6920            <resetMask>0x1</resetMask>
6921            <fields>
6922              <field>
6923                <name>FAULT</name>
6924                <description>Mask bit for corresponding field in the INTR register.</description>
6925                <bitRange>[0:0]</bitRange>
6926                <access>read-write</access>
6927              </field>
6928            </fields>
6929          </register>
6930          <register>
6931            <name>INTR_MASKED</name>
6932            <description>Interrupt masked</description>
6933            <addressOffset>0xCC</addressOffset>
6934            <size>32</size>
6935            <access>read-only</access>
6936            <resetValue>0x0</resetValue>
6937            <resetMask>0x1</resetMask>
6938            <fields>
6939              <field>
6940                <name>FAULT</name>
6941                <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
6942                <bitRange>[0:0]</bitRange>
6943                <access>read-only</access>
6944              </field>
6945            </fields>
6946          </register>
6947        </cluster>
6948      </registers>
6949    </peripheral>
6950    <peripheral>
6951      <name>IPC</name>
6952      <description>IPC</description>
6953      <baseAddress>0x40220000</baseAddress>
6954      <addressBlock>
6955        <offset>0</offset>
6956        <size>65536</size>
6957        <usage>registers</usage>
6958      </addressBlock>
6959      <registers>
6960        <cluster>
6961          <dim>8</dim>
6962          <dimIncrement>32</dimIncrement>
6963          <name>STRUCT[%s]</name>
6964          <description>IPC structure</description>
6965          <addressOffset>0x00000000</addressOffset>
6966          <register>
6967            <name>ACQUIRE</name>
6968            <description>IPC acquire</description>
6969            <addressOffset>0x0</addressOffset>
6970            <size>32</size>
6971            <access>read-only</access>
6972            <resetValue>0x0</resetValue>
6973            <resetMask>0x80000000</resetMask>
6974            <fields>
6975              <field>
6976                <name>P</name>
6977                <description>User/privileged access control:
6978'0': user mode.
6979'1': privileged mode.
6980
6981This field is set with the user/privileged access control of the access that successfully acquired the lock.</description>
6982                <bitRange>[0:0]</bitRange>
6983                <access>read-only</access>
6984              </field>
6985              <field>
6986                <name>NS</name>
6987                <description>Secure/non-secure access control:
6988'0': secure.
6989'1': non-secure.
6990
6991This field is set with the secure/non-secure access control of the access that successfully acquired the lock.</description>
6992                <bitRange>[1:1]</bitRange>
6993                <access>read-only</access>
6994              </field>
6995              <field>
6996                <name>PC</name>
6997                <description>This field specifies the protection context that successfully acquired the lock.</description>
6998                <bitRange>[7:4]</bitRange>
6999                <access>read-only</access>
7000              </field>
7001              <field>
7002                <name>MS</name>
7003                <description>This field specifies the bus master identifier that successfully acquired the lock.</description>
7004                <bitRange>[11:8]</bitRange>
7005                <access>read-only</access>
7006              </field>
7007              <field>
7008                <name>SUCCESS</name>
7009                <description>Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED):
7010'0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access.
7011'1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access.
7012
7013Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).</description>
7014                <bitRange>[31:31]</bitRange>
7015                <access>read-only</access>
7016              </field>
7017            </fields>
7018          </register>
7019          <register>
7020            <name>RELEASE</name>
7021            <description>IPC release</description>
7022            <addressOffset>0x4</addressOffset>
7023            <size>32</size>
7024            <access>write-only</access>
7025            <resetValue>0x0</resetValue>
7026            <resetMask>0xFFFF</resetMask>
7027            <fields>
7028              <field>
7029                <name>INTR_RELEASE</name>
7030                <description>Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'.
7031
7032SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
7033                <bitRange>[15:0]</bitRange>
7034                <access>write-only</access>
7035              </field>
7036            </fields>
7037          </register>
7038          <register>
7039            <name>NOTIFY</name>
7040            <description>IPC notification</description>
7041            <addressOffset>0x8</addressOffset>
7042            <size>32</size>
7043            <access>write-only</access>
7044            <resetValue>0x0</resetValue>
7045            <resetMask>0xFFFF</resetMask>
7046            <fields>
7047              <field>
7048                <name>INTR_NOTIFY</name>
7049                <description>This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'.
7050
7051SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
7052                <bitRange>[15:0]</bitRange>
7053                <access>write-only</access>
7054              </field>
7055            </fields>
7056          </register>
7057          <register>
7058            <name>DATA0</name>
7059            <description>IPC data 0</description>
7060            <addressOffset>0xC</addressOffset>
7061            <size>32</size>
7062            <access>read-write</access>
7063            <resetValue>0x0</resetValue>
7064            <resetMask>0x0</resetMask>
7065            <fields>
7066              <field>
7067                <name>DATA</name>
7068                <description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
7069                <bitRange>[31:0]</bitRange>
7070                <access>read-write</access>
7071              </field>
7072            </fields>
7073          </register>
7074          <register>
7075            <name>DATA1</name>
7076            <description>IPC data 1</description>
7077            <addressOffset>0x10</addressOffset>
7078            <size>32</size>
7079            <access>read-write</access>
7080            <resetValue>0x0</resetValue>
7081            <resetMask>0x0</resetMask>
7082            <fields>
7083              <field>
7084                <name>DATA</name>
7085                <description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
7086                <bitRange>[31:0]</bitRange>
7087                <access>read-write</access>
7088              </field>
7089            </fields>
7090          </register>
7091          <register>
7092            <name>LOCK_STATUS</name>
7093            <description>IPC lock status</description>
7094            <addressOffset>0x1C</addressOffset>
7095            <size>32</size>
7096            <access>read-only</access>
7097            <resetValue>0x0</resetValue>
7098            <resetMask>0x80000000</resetMask>
7099            <fields>
7100              <field>
7101                <name>P</name>
7102                <description>This field specifies the user/privileged access control:
7103'0': user mode.
7104'1': privileged mode.</description>
7105                <bitRange>[0:0]</bitRange>
7106                <access>read-only</access>
7107              </field>
7108              <field>
7109                <name>NS</name>
7110                <description>This field specifies the secure/non-secure access control:
7111'0': secure.
7112'1': non-secure.</description>
7113                <bitRange>[1:1]</bitRange>
7114                <access>read-only</access>
7115              </field>
7116              <field>
7117                <name>PC</name>
7118                <description>This field specifies the protection context that successfully acquired the lock.</description>
7119                <bitRange>[7:4]</bitRange>
7120                <access>read-only</access>
7121              </field>
7122              <field>
7123                <name>MS</name>
7124                <description>This field specifies the bus master identifier that successfully acquired the lock.</description>
7125                <bitRange>[11:8]</bitRange>
7126                <access>read-only</access>
7127              </field>
7128              <field>
7129                <name>ACQUIRED</name>
7130                <description>Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid.</description>
7131                <bitRange>[31:31]</bitRange>
7132                <access>read-only</access>
7133              </field>
7134            </fields>
7135          </register>
7136        </cluster>
7137        <cluster>
7138          <dim>8</dim>
7139          <dimIncrement>32</dimIncrement>
7140          <name>INTR_STRUCT[%s]</name>
7141          <description>IPC interrupt structure</description>
7142          <addressOffset>0x00001000</addressOffset>
7143          <register>
7144            <name>INTR</name>
7145            <description>Interrupt</description>
7146            <addressOffset>0x0</addressOffset>
7147            <size>32</size>
7148            <access>read-write</access>
7149            <resetValue>0x0</resetValue>
7150            <resetMask>0xFFFFFFFF</resetMask>
7151            <fields>
7152              <field>
7153                <name>RELEASE</name>
7154                <description>These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.</description>
7155                <bitRange>[15:0]</bitRange>
7156                <access>read-write</access>
7157              </field>
7158              <field>
7159                <name>NOTIFY</name>
7160                <description>These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.</description>
7161                <bitRange>[31:16]</bitRange>
7162                <access>read-write</access>
7163              </field>
7164            </fields>
7165          </register>
7166          <register>
7167            <name>INTR_SET</name>
7168            <description>Interrupt set</description>
7169            <addressOffset>0x4</addressOffset>
7170            <size>32</size>
7171            <access>read-write</access>
7172            <resetValue>0x0</resetValue>
7173            <resetMask>0xFFFFFFFF</resetMask>
7174            <fields>
7175              <field>
7176                <name>RELEASE</name>
7177                <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
7178                <bitRange>[15:0]</bitRange>
7179                <access>read-write</access>
7180              </field>
7181              <field>
7182                <name>NOTIFY</name>
7183                <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
7184                <bitRange>[31:16]</bitRange>
7185                <access>read-write</access>
7186              </field>
7187            </fields>
7188          </register>
7189          <register>
7190            <name>INTR_MASK</name>
7191            <description>Interrupt mask</description>
7192            <addressOffset>0x8</addressOffset>
7193            <size>32</size>
7194            <access>read-write</access>
7195            <resetValue>0x0</resetValue>
7196            <resetMask>0xFFFFFFFF</resetMask>
7197            <fields>
7198              <field>
7199                <name>RELEASE</name>
7200                <description>Mask bit for corresponding field in the INTR register.</description>
7201                <bitRange>[15:0]</bitRange>
7202                <access>read-write</access>
7203              </field>
7204              <field>
7205                <name>NOTIFY</name>
7206                <description>Mask bit for corresponding field in the INTR register.</description>
7207                <bitRange>[31:16]</bitRange>
7208                <access>read-write</access>
7209              </field>
7210            </fields>
7211          </register>
7212          <register>
7213            <name>INTR_MASKED</name>
7214            <description>Interrupt masked</description>
7215            <addressOffset>0xC</addressOffset>
7216            <size>32</size>
7217            <access>read-only</access>
7218            <resetValue>0x0</resetValue>
7219            <resetMask>0xFFFFFFFF</resetMask>
7220            <fields>
7221              <field>
7222                <name>RELEASE</name>
7223                <description>Logical and of corresponding request and mask bits.</description>
7224                <bitRange>[15:0]</bitRange>
7225                <access>read-only</access>
7226              </field>
7227              <field>
7228                <name>NOTIFY</name>
7229                <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
7230                <bitRange>[31:16]</bitRange>
7231                <access>read-only</access>
7232              </field>
7233            </fields>
7234          </register>
7235        </cluster>
7236      </registers>
7237    </peripheral>
7238    <peripheral>
7239      <name>PROT</name>
7240      <description>Protection</description>
7241      <baseAddress>0x40230000</baseAddress>
7242      <addressBlock>
7243        <offset>0</offset>
7244        <size>65536</size>
7245        <usage>registers</usage>
7246      </addressBlock>
7247      <registers>
7248        <cluster>
7249          <name>SMPU</name>
7250          <description>SMPU</description>
7251          <addressOffset>0x00000000</addressOffset>
7252          <register>
7253            <name>MS0_CTL</name>
7254            <description>Master 0 protection context control</description>
7255            <addressOffset>0x0</addressOffset>
7256            <size>32</size>
7257            <access>read-write</access>
7258            <resetValue>0x303</resetValue>
7259            <resetMask>0xFFFF0303</resetMask>
7260            <fields>
7261              <field>
7262                <name>P</name>
7263                <description>Privileged setting ('0': user mode; '1': privileged mode).
7264
7265Notes:
7266This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute.
7267The default/reset field value provides privileged mode access capabilities.</description>
7268                <bitRange>[0:0]</bitRange>
7269                <access>read-write</access>
7270              </field>
7271              <field>
7272                <name>NS</name>
7273                <description>Security setting ('0': secure mode; '1': non-secure mode).
7274
7275Notes:
7276This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute.
7277Note that the default/reset field value provides non-secure mode access capabilities to all masters.</description>
7278                <bitRange>[1:1]</bitRange>
7279                <access>read-write</access>
7280              </field>
7281              <field>
7282                <name>PRIO</name>
7283                <description>Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority).
7284
7285Notes:
7286The AHB-Lite interconnect performs arbitration on the individual  beats/transfers of a burst (this optimizes latency over locality/bandwidth).
7287The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency).
7288Masters with the same priority setting form a 'priority group'. Within a 'priority group', round robin arbitration is performed.</description>
7289                <bitRange>[9:8]</bitRange>
7290                <access>read-write</access>
7291              </field>
7292              <field>
7293                <name>PC_MASK_0</name>
7294                <description>Protection context mask for protection context '0'. This field is a constant '0':
7295- PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed.</description>
7296                <bitRange>[16:16]</bitRange>
7297                <access>read-only</access>
7298              </field>
7299              <field>
7300                <name>PC_MASK_15_TO_1</name>
7301                <description>Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1':
7302- PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed.
7303- PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'.
7304
7305Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]).</description>
7306                <bitRange>[31:17]</bitRange>
7307                <access>read-write</access>
7308              </field>
7309            </fields>
7310          </register>
7311          <register>
7312            <name>MS1_CTL</name>
7313            <description>Master 1 protection context control</description>
7314            <addressOffset>0x4</addressOffset>
7315            <size>32</size>
7316            <access>read-write</access>
7317            <resetValue>0x303</resetValue>
7318            <resetMask>0xFFFF0303</resetMask>
7319            <fields>
7320              <field>
7321                <name>P</name>
7322                <description>See MS0_CTL.P.</description>
7323                <bitRange>[0:0]</bitRange>
7324                <access>read-write</access>
7325              </field>
7326              <field>
7327                <name>NS</name>
7328                <description>See MS0_CTL.NS.</description>
7329                <bitRange>[1:1]</bitRange>
7330                <access>read-write</access>
7331              </field>
7332              <field>
7333                <name>PRIO</name>
7334                <description>See MS0_CTL.PRIO</description>
7335                <bitRange>[9:8]</bitRange>
7336                <access>read-write</access>
7337              </field>
7338              <field>
7339                <name>PC_MASK_0</name>
7340                <description>See MS0_CTL.PC_MASK_0.</description>
7341                <bitRange>[16:16]</bitRange>
7342                <access>read-only</access>
7343              </field>
7344              <field>
7345                <name>PC_MASK_15_TO_1</name>
7346                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
7347                <bitRange>[31:17]</bitRange>
7348                <access>read-write</access>
7349              </field>
7350            </fields>
7351          </register>
7352          <register>
7353            <name>MS2_CTL</name>
7354            <description>Master 2 protection context control</description>
7355            <addressOffset>0x8</addressOffset>
7356            <size>32</size>
7357            <access>read-write</access>
7358            <resetValue>0x303</resetValue>
7359            <resetMask>0xFFFF0303</resetMask>
7360            <fields>
7361              <field>
7362                <name>P</name>
7363                <description>See MS0_CTL.P.</description>
7364                <bitRange>[0:0]</bitRange>
7365                <access>read-write</access>
7366              </field>
7367              <field>
7368                <name>NS</name>
7369                <description>See MS0_CTL.NS.</description>
7370                <bitRange>[1:1]</bitRange>
7371                <access>read-write</access>
7372              </field>
7373              <field>
7374                <name>PRIO</name>
7375                <description>See MS0_CTL.PRIO</description>
7376                <bitRange>[9:8]</bitRange>
7377                <access>read-write</access>
7378              </field>
7379              <field>
7380                <name>PC_MASK_0</name>
7381                <description>See MS0_CTL.PC_MASK_0.</description>
7382                <bitRange>[16:16]</bitRange>
7383                <access>read-only</access>
7384              </field>
7385              <field>
7386                <name>PC_MASK_15_TO_1</name>
7387                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
7388                <bitRange>[31:17]</bitRange>
7389                <access>read-write</access>
7390              </field>
7391            </fields>
7392          </register>
7393          <register>
7394            <name>MS3_CTL</name>
7395            <description>Master 3 protection context control</description>
7396            <addressOffset>0xC</addressOffset>
7397            <size>32</size>
7398            <access>read-write</access>
7399            <resetValue>0x303</resetValue>
7400            <resetMask>0xFFFF0303</resetMask>
7401            <fields>
7402              <field>
7403                <name>P</name>
7404                <description>See MS0_CTL.P.</description>
7405                <bitRange>[0:0]</bitRange>
7406                <access>read-write</access>
7407              </field>
7408              <field>
7409                <name>NS</name>
7410                <description>See MS0_CTL.NS.</description>
7411                <bitRange>[1:1]</bitRange>
7412                <access>read-write</access>
7413              </field>
7414              <field>
7415                <name>PRIO</name>
7416                <description>See MS0_CTL.PRIO</description>
7417                <bitRange>[9:8]</bitRange>
7418                <access>read-write</access>
7419              </field>
7420              <field>
7421                <name>PC_MASK_0</name>
7422                <description>See MS0_CTL.PC_MASK_0.</description>
7423                <bitRange>[16:16]</bitRange>
7424                <access>read-only</access>
7425              </field>
7426              <field>
7427                <name>PC_MASK_15_TO_1</name>
7428                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
7429                <bitRange>[31:17]</bitRange>
7430                <access>read-write</access>
7431              </field>
7432            </fields>
7433          </register>
7434          <register>
7435            <name>MS4_CTL</name>
7436            <description>Master 4 protection context control</description>
7437            <addressOffset>0x10</addressOffset>
7438            <size>32</size>
7439            <access>read-write</access>
7440            <resetValue>0x303</resetValue>
7441            <resetMask>0xFFFF0303</resetMask>
7442            <fields>
7443              <field>
7444                <name>P</name>
7445                <description>See MS0_CTL.P.</description>
7446                <bitRange>[0:0]</bitRange>
7447                <access>read-write</access>
7448              </field>
7449              <field>
7450                <name>NS</name>
7451                <description>See MS0_CTL.NS.</description>
7452                <bitRange>[1:1]</bitRange>
7453                <access>read-write</access>
7454              </field>
7455              <field>
7456                <name>PRIO</name>
7457                <description>See MS0_CTL.PRIO</description>
7458                <bitRange>[9:8]</bitRange>
7459                <access>read-write</access>
7460              </field>
7461              <field>
7462                <name>PC_MASK_0</name>
7463                <description>See MS0_CTL.PC_MASK_0.</description>
7464                <bitRange>[16:16]</bitRange>
7465                <access>read-only</access>
7466              </field>
7467              <field>
7468                <name>PC_MASK_15_TO_1</name>
7469                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
7470                <bitRange>[31:17]</bitRange>
7471                <access>read-write</access>
7472              </field>
7473            </fields>
7474          </register>
7475          <register>
7476            <name>MS5_CTL</name>
7477            <description>Master 5 protection context control</description>
7478            <addressOffset>0x14</addressOffset>
7479            <size>32</size>
7480            <access>read-write</access>
7481            <resetValue>0x303</resetValue>
7482            <resetMask>0xFFFF0303</resetMask>
7483            <fields>
7484              <field>
7485                <name>P</name>
7486                <description>See MS0_CTL.P.</description>
7487                <bitRange>[0:0]</bitRange>
7488                <access>read-write</access>
7489              </field>
7490              <field>
7491                <name>NS</name>
7492                <description>See MS0_CTL.NS.</description>
7493                <bitRange>[1:1]</bitRange>
7494                <access>read-write</access>
7495              </field>
7496              <field>
7497                <name>PRIO</name>
7498                <description>See MS0_CTL.PRIO</description>
7499                <bitRange>[9:8]</bitRange>
7500                <access>read-write</access>
7501              </field>
7502              <field>
7503                <name>PC_MASK_0</name>
7504                <description>See MS0_CTL.PC_MASK_0.</description>
7505                <bitRange>[16:16]</bitRange>
7506                <access>read-only</access>
7507              </field>
7508              <field>
7509                <name>PC_MASK_15_TO_1</name>
7510                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
7511                <bitRange>[31:17]</bitRange>
7512                <access>read-write</access>
7513              </field>
7514            </fields>
7515          </register>
7516          <register>
7517            <name>MS6_CTL</name>
7518            <description>Master 6 protection context control</description>
7519            <addressOffset>0x18</addressOffset>
7520            <size>32</size>
7521            <access>read-write</access>
7522            <resetValue>0x303</resetValue>
7523            <resetMask>0xFFFF0303</resetMask>
7524            <fields>
7525              <field>
7526                <name>P</name>
7527                <description>See MS0_CTL.P.</description>
7528                <bitRange>[0:0]</bitRange>
7529                <access>read-write</access>
7530              </field>
7531              <field>
7532                <name>NS</name>
7533                <description>See MS0_CTL.NS.</description>
7534                <bitRange>[1:1]</bitRange>
7535                <access>read-write</access>
7536              </field>
7537              <field>
7538                <name>PRIO</name>
7539                <description>See MS0_CTL.PRIO</description>
7540                <bitRange>[9:8]</bitRange>
7541                <access>read-write</access>
7542              </field>
7543              <field>
7544                <name>PC_MASK_0</name>
7545                <description>See MS0_CTL.PC_MASK_0.</description>
7546                <bitRange>[16:16]</bitRange>
7547                <access>read-only</access>
7548              </field>
7549              <field>
7550                <name>PC_MASK_15_TO_1</name>
7551                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
7552                <bitRange>[31:17]</bitRange>
7553                <access>read-write</access>
7554              </field>
7555            </fields>
7556          </register>
7557          <register>
7558            <name>MS7_CTL</name>
7559            <description>Master 7 protection context control</description>
7560            <addressOffset>0x1C</addressOffset>
7561            <size>32</size>
7562            <access>read-write</access>
7563            <resetValue>0x303</resetValue>
7564            <resetMask>0xFFFF0303</resetMask>
7565            <fields>
7566              <field>
7567                <name>P</name>
7568                <description>See MS0_CTL.P.</description>
7569                <bitRange>[0:0]</bitRange>
7570                <access>read-write</access>
7571              </field>
7572              <field>
7573                <name>NS</name>
7574                <description>See MS0_CTL.NS.</description>
7575                <bitRange>[1:1]</bitRange>
7576                <access>read-write</access>
7577              </field>
7578              <field>
7579                <name>PRIO</name>
7580                <description>See MS0_CTL.PRIO</description>
7581                <bitRange>[9:8]</bitRange>
7582                <access>read-write</access>
7583              </field>
7584              <field>
7585                <name>PC_MASK_0</name>
7586                <description>See MS0_CTL.PC_MASK_0.</description>
7587                <bitRange>[16:16]</bitRange>
7588                <access>read-only</access>
7589              </field>
7590              <field>
7591                <name>PC_MASK_15_TO_1</name>
7592                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
7593                <bitRange>[31:17]</bitRange>
7594                <access>read-write</access>
7595              </field>
7596            </fields>
7597          </register>
7598          <register>
7599            <name>MS8_CTL</name>
7600            <description>Master 8 protection context control</description>
7601            <addressOffset>0x20</addressOffset>
7602            <size>32</size>
7603            <access>read-write</access>
7604            <resetValue>0x303</resetValue>
7605            <resetMask>0xFFFF0303</resetMask>
7606            <fields>
7607              <field>
7608                <name>P</name>
7609                <description>See MS0_CTL.P.</description>
7610                <bitRange>[0:0]</bitRange>
7611                <access>read-write</access>
7612              </field>
7613              <field>
7614                <name>NS</name>
7615                <description>See MS0_CTL.NS.</description>
7616                <bitRange>[1:1]</bitRange>
7617                <access>read-write</access>
7618              </field>
7619              <field>
7620                <name>PRIO</name>
7621                <description>See MS0_CTL.PRIO</description>
7622                <bitRange>[9:8]</bitRange>
7623                <access>read-write</access>
7624              </field>
7625              <field>
7626                <name>PC_MASK_0</name>
7627                <description>See MS0_CTL.PC_MASK_0.</description>
7628                <bitRange>[16:16]</bitRange>
7629                <access>read-only</access>
7630              </field>
7631              <field>
7632                <name>PC_MASK_15_TO_1</name>
7633                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
7634                <bitRange>[31:17]</bitRange>
7635                <access>read-write</access>
7636              </field>
7637            </fields>
7638          </register>
7639          <register>
7640            <name>MS9_CTL</name>
7641            <description>Master 9 protection context control</description>
7642            <addressOffset>0x24</addressOffset>
7643            <size>32</size>
7644            <access>read-write</access>
7645            <resetValue>0x303</resetValue>
7646            <resetMask>0xFFFF0303</resetMask>
7647            <fields>
7648              <field>
7649                <name>P</name>
7650                <description>See MS0_CTL.P.</description>
7651                <bitRange>[0:0]</bitRange>
7652                <access>read-write</access>
7653              </field>
7654              <field>
7655                <name>NS</name>
7656                <description>See MS0_CTL.NS.</description>
7657                <bitRange>[1:1]</bitRange>
7658                <access>read-write</access>
7659              </field>
7660              <field>
7661                <name>PRIO</name>
7662                <description>See MS0_CTL.PRIO</description>
7663                <bitRange>[9:8]</bitRange>
7664                <access>read-write</access>
7665              </field>
7666              <field>
7667                <name>PC_MASK_0</name>
7668                <description>See MS0_CTL.PC_MASK_0.</description>
7669                <bitRange>[16:16]</bitRange>
7670                <access>read-only</access>
7671              </field>
7672              <field>
7673                <name>PC_MASK_15_TO_1</name>
7674                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
7675                <bitRange>[31:17]</bitRange>
7676                <access>read-write</access>
7677              </field>
7678            </fields>
7679          </register>
7680          <register>
7681            <name>MS10_CTL</name>
7682            <description>Master 10 protection context control</description>
7683            <addressOffset>0x28</addressOffset>
7684            <size>32</size>
7685            <access>read-write</access>
7686            <resetValue>0x303</resetValue>
7687            <resetMask>0xFFFF0303</resetMask>
7688            <fields>
7689              <field>
7690                <name>P</name>
7691                <description>See MS0_CTL.P.</description>
7692                <bitRange>[0:0]</bitRange>
7693                <access>read-write</access>
7694              </field>
7695              <field>
7696                <name>NS</name>
7697                <description>See MS0_CTL.NS.</description>
7698                <bitRange>[1:1]</bitRange>
7699                <access>read-write</access>
7700              </field>
7701              <field>
7702                <name>PRIO</name>
7703                <description>See MS0_CTL.PRIO</description>
7704                <bitRange>[9:8]</bitRange>
7705                <access>read-write</access>
7706              </field>
7707              <field>
7708                <name>PC_MASK_0</name>
7709                <description>See MS0_CTL.PC_MASK_0.</description>
7710                <bitRange>[16:16]</bitRange>
7711                <access>read-only</access>
7712              </field>
7713              <field>
7714                <name>PC_MASK_15_TO_1</name>
7715                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
7716                <bitRange>[31:17]</bitRange>
7717                <access>read-write</access>
7718              </field>
7719            </fields>
7720          </register>
7721          <register>
7722            <name>MS11_CTL</name>
7723            <description>Master 11 protection context control</description>
7724            <addressOffset>0x2C</addressOffset>
7725            <size>32</size>
7726            <access>read-write</access>
7727            <resetValue>0x303</resetValue>
7728            <resetMask>0xFFFF0303</resetMask>
7729            <fields>
7730              <field>
7731                <name>P</name>
7732                <description>See MS0_CTL.P.</description>
7733                <bitRange>[0:0]</bitRange>
7734                <access>read-write</access>
7735              </field>
7736              <field>
7737                <name>NS</name>
7738                <description>See MS0_CTL.NS.</description>
7739                <bitRange>[1:1]</bitRange>
7740                <access>read-write</access>
7741              </field>
7742              <field>
7743                <name>PRIO</name>
7744                <description>See MS0_CTL.PRIO</description>
7745                <bitRange>[9:8]</bitRange>
7746                <access>read-write</access>
7747              </field>
7748              <field>
7749                <name>PC_MASK_0</name>
7750                <description>See MS0_CTL.PC_MASK_0.</description>
7751                <bitRange>[16:16]</bitRange>
7752                <access>read-only</access>
7753              </field>
7754              <field>
7755                <name>PC_MASK_15_TO_1</name>
7756                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
7757                <bitRange>[31:17]</bitRange>
7758                <access>read-write</access>
7759              </field>
7760            </fields>
7761          </register>
7762          <register>
7763            <name>MS12_CTL</name>
7764            <description>Master 12 protection context control</description>
7765            <addressOffset>0x30</addressOffset>
7766            <size>32</size>
7767            <access>read-write</access>
7768            <resetValue>0x303</resetValue>
7769            <resetMask>0xFFFF0303</resetMask>
7770            <fields>
7771              <field>
7772                <name>P</name>
7773                <description>See MS0_CTL.P.</description>
7774                <bitRange>[0:0]</bitRange>
7775                <access>read-write</access>
7776              </field>
7777              <field>
7778                <name>NS</name>
7779                <description>See MS0_CTL.NS.</description>
7780                <bitRange>[1:1]</bitRange>
7781                <access>read-write</access>
7782              </field>
7783              <field>
7784                <name>PRIO</name>
7785                <description>See MS0_CTL.PRIO</description>
7786                <bitRange>[9:8]</bitRange>
7787                <access>read-write</access>
7788              </field>
7789              <field>
7790                <name>PC_MASK_0</name>
7791                <description>See MS0_CTL.PC_MASK_0.</description>
7792                <bitRange>[16:16]</bitRange>
7793                <access>read-only</access>
7794              </field>
7795              <field>
7796                <name>PC_MASK_15_TO_1</name>
7797                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
7798                <bitRange>[31:17]</bitRange>
7799                <access>read-write</access>
7800              </field>
7801            </fields>
7802          </register>
7803          <register>
7804            <name>MS13_CTL</name>
7805            <description>Master 13 protection context control</description>
7806            <addressOffset>0x34</addressOffset>
7807            <size>32</size>
7808            <access>read-write</access>
7809            <resetValue>0x303</resetValue>
7810            <resetMask>0xFFFF0303</resetMask>
7811            <fields>
7812              <field>
7813                <name>P</name>
7814                <description>See MS0_CTL.P.</description>
7815                <bitRange>[0:0]</bitRange>
7816                <access>read-write</access>
7817              </field>
7818              <field>
7819                <name>NS</name>
7820                <description>See MS0_CTL.NS.</description>
7821                <bitRange>[1:1]</bitRange>
7822                <access>read-write</access>
7823              </field>
7824              <field>
7825                <name>PRIO</name>
7826                <description>See MS0_CTL.PRIO</description>
7827                <bitRange>[9:8]</bitRange>
7828                <access>read-write</access>
7829              </field>
7830              <field>
7831                <name>PC_MASK_0</name>
7832                <description>See MS0_CTL.PC_MASK_0.</description>
7833                <bitRange>[16:16]</bitRange>
7834                <access>read-only</access>
7835              </field>
7836              <field>
7837                <name>PC_MASK_15_TO_1</name>
7838                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
7839                <bitRange>[31:17]</bitRange>
7840                <access>read-write</access>
7841              </field>
7842            </fields>
7843          </register>
7844          <register>
7845            <name>MS14_CTL</name>
7846            <description>Master 14 protection context control</description>
7847            <addressOffset>0x38</addressOffset>
7848            <size>32</size>
7849            <access>read-write</access>
7850            <resetValue>0x303</resetValue>
7851            <resetMask>0xFFFF0303</resetMask>
7852            <fields>
7853              <field>
7854                <name>P</name>
7855                <description>See MS0_CTL.P.</description>
7856                <bitRange>[0:0]</bitRange>
7857                <access>read-write</access>
7858              </field>
7859              <field>
7860                <name>NS</name>
7861                <description>See MS0_CTL.NS.</description>
7862                <bitRange>[1:1]</bitRange>
7863                <access>read-write</access>
7864              </field>
7865              <field>
7866                <name>PRIO</name>
7867                <description>See MS0_CTL.PRIO</description>
7868                <bitRange>[9:8]</bitRange>
7869                <access>read-write</access>
7870              </field>
7871              <field>
7872                <name>PC_MASK_0</name>
7873                <description>See MS0_CTL.PC_MASK_0.</description>
7874                <bitRange>[16:16]</bitRange>
7875                <access>read-only</access>
7876              </field>
7877              <field>
7878                <name>PC_MASK_15_TO_1</name>
7879                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
7880                <bitRange>[31:17]</bitRange>
7881                <access>read-write</access>
7882              </field>
7883            </fields>
7884          </register>
7885          <register>
7886            <name>MS15_CTL</name>
7887            <description>Master 15 protection context control</description>
7888            <addressOffset>0x3C</addressOffset>
7889            <size>32</size>
7890            <access>read-write</access>
7891            <resetValue>0x303</resetValue>
7892            <resetMask>0xFFFF0303</resetMask>
7893            <fields>
7894              <field>
7895                <name>P</name>
7896                <description>See MS0_CTL.P.</description>
7897                <bitRange>[0:0]</bitRange>
7898                <access>read-write</access>
7899              </field>
7900              <field>
7901                <name>NS</name>
7902                <description>See MS0_CTL.NS.</description>
7903                <bitRange>[1:1]</bitRange>
7904                <access>read-write</access>
7905              </field>
7906              <field>
7907                <name>PRIO</name>
7908                <description>See MS0_CTL.PRIO</description>
7909                <bitRange>[9:8]</bitRange>
7910                <access>read-write</access>
7911              </field>
7912              <field>
7913                <name>PC_MASK_0</name>
7914                <description>See MS0_CTL.PC_MASK_0.</description>
7915                <bitRange>[16:16]</bitRange>
7916                <access>read-only</access>
7917              </field>
7918              <field>
7919                <name>PC_MASK_15_TO_1</name>
7920                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
7921                <bitRange>[31:17]</bitRange>
7922                <access>read-write</access>
7923              </field>
7924            </fields>
7925          </register>
7926          <cluster>
7927            <dim>16</dim>
7928            <dimIncrement>64</dimIncrement>
7929            <name>SMPU_STRUCT[%s]</name>
7930            <description>SMPU structure</description>
7931            <addressOffset>0x00002000</addressOffset>
7932            <register>
7933              <name>ADDR0</name>
7934              <description>SMPU region address 0 (slave structure)</description>
7935              <addressOffset>0x0</addressOffset>
7936              <size>32</size>
7937              <access>read-write</access>
7938              <resetValue>0x0</resetValue>
7939              <resetMask>0x0</resetMask>
7940              <fields>
7941                <field>
7942                  <name>SUBREGION_DISABLE</name>
7943                  <description>This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:
7944Bit 0: subregion 0 disable.
7945Bit 1: subregion 1 disable.
7946Bit 2: subregion 2 disable.
7947Bit 3: subregion 3 disable.
7948Bit 4: subregion 4 disable.
7949Bit 5: subregion 5 disable.
7950Bit 6: subregion 6 disable.
7951Bit 7: subregion 7 disable.
7952E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.</description>
7953                  <bitRange>[7:0]</bitRange>
7954                  <access>read-write</access>
7955                </field>
7956                <field>
7957                  <name>ADDR24</name>
7958                  <description>This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.</description>
7959                  <bitRange>[31:8]</bitRange>
7960                  <access>read-write</access>
7961                </field>
7962              </fields>
7963            </register>
7964            <register>
7965              <name>ATT0</name>
7966              <description>SMPU region attributes 0 (slave structure)</description>
7967              <addressOffset>0x4</addressOffset>
7968              <size>32</size>
7969              <access>read-write</access>
7970              <resetValue>0x100</resetValue>
7971              <resetMask>0x80000100</resetMask>
7972              <fields>
7973                <field>
7974                  <name>UR</name>
7975                  <description>User read enable:
7976'0': Disabled (user, read accesses are NOT allowed).
7977'1': Enabled (user, read accesses are allowed).</description>
7978                  <bitRange>[0:0]</bitRange>
7979                  <access>read-write</access>
7980                </field>
7981                <field>
7982                  <name>UW</name>
7983                  <description>User write enable:
7984'0': Disabled (user, write accesses are NOT allowed).
7985'1': Enabled (user, write accesses are allowed).</description>
7986                  <bitRange>[1:1]</bitRange>
7987                  <access>read-write</access>
7988                </field>
7989                <field>
7990                  <name>UX</name>
7991                  <description>User execute enable:
7992'0': Disabled (user, execute accesses are NOT allowed).
7993'1': Enabled (user, execute accesses are allowed).</description>
7994                  <bitRange>[2:2]</bitRange>
7995                  <access>read-write</access>
7996                </field>
7997                <field>
7998                  <name>PR</name>
7999                  <description>Privileged read enable:
8000'0': Disabled (privileged, read accesses are NOT allowed).
8001'1': Enabled (privileged, read accesses are allowed).</description>
8002                  <bitRange>[3:3]</bitRange>
8003                  <access>read-write</access>
8004                </field>
8005                <field>
8006                  <name>PW</name>
8007                  <description>Privileged write enable:
8008'0': Disabled (privileged, write accesses are NOT allowed).
8009'1': Enabled (privileged, write accesses are allowed).</description>
8010                  <bitRange>[4:4]</bitRange>
8011                  <access>read-write</access>
8012                </field>
8013                <field>
8014                  <name>PX</name>
8015                  <description>Privileged execute enable:
8016'0': Disabled (privileged, execute accesses are NOT allowed).
8017'1': Enabled (privileged, execute accesses are allowed).</description>
8018                  <bitRange>[5:5]</bitRange>
8019                  <access>read-write</access>
8020                </field>
8021                <field>
8022                  <name>NS</name>
8023                  <description>Non-secure:
8024'0': Secure (secure accesses allowed, non-secure access NOT allowed).
8025'1': Non-secure (both secure and non-secure accesses allowed).</description>
8026                  <bitRange>[6:6]</bitRange>
8027                  <access>read-write</access>
8028                </field>
8029                <field>
8030                  <name>PC_MASK_0</name>
8031                  <description>This field specifies protection context identifier based access control for protection context '0'.</description>
8032                  <bitRange>[8:8]</bitRange>
8033                  <access>read-only</access>
8034                </field>
8035                <field>
8036                  <name>PC_MASK_15_TO_1</name>
8037                  <description>This field specifies protection context identifier based access control.
8038Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.</description>
8039                  <bitRange>[23:9]</bitRange>
8040                  <access>read-write</access>
8041                </field>
8042                <field>
8043                  <name>REGION_SIZE</name>
8044                  <description>This field specifies the region size:
8045'0'-'6': Undefined.
8046'7': 256 B region
8047'8': 512 B region
8048'9': 1 KB region
8049'10': 2 KB region
8050'11': 4 KB region
8051'12': 8 KB region
8052'13': 16 KB region
8053'14': 32 KB region
8054'15': 64 KB region
8055'16': 128 KB region
8056'17': 256 KB region
8057'18': 512 KB region
8058'19': 1 MB region
8059'20': 2 MB region
8060'21': 4 MB region
8061'22': 8 MB region
8062'23': 16 MB region
8063'24': 32 MB region
8064'25': 64 MB region
8065'26': 128 MB region
8066'27': 256 MB region
8067'28': 512 MB region
8068'39': 1 GB region
8069'30': 2 GB region
8070'31': 4 GB region</description>
8071                  <bitRange>[28:24]</bitRange>
8072                  <access>read-write</access>
8073                </field>
8074                <field>
8075                  <name>PC_MATCH</name>
8076                  <description>This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:
8077'0': PC field participates in 'access evaluation'.
8078'1': PC field participates in 'matching'.
8079
8080'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions.
8081'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes.
8082
8083Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.</description>
8084                  <bitRange>[30:30]</bitRange>
8085                  <access>read-write</access>
8086                </field>
8087                <field>
8088                  <name>ENABLED</name>
8089                  <description>Region enable:
8090'0': Disabled. A disabled region will never result in a match on the bus transfer address.
8091'1': Enabled.
8092
8093Note: a disabled address region performs logic gating to reduce dynamic power consumption.</description>
8094                  <bitRange>[31:31]</bitRange>
8095                  <access>read-write</access>
8096                </field>
8097              </fields>
8098            </register>
8099            <register>
8100              <name>ADDR1</name>
8101              <description>SMPU region address 1 (master structure)</description>
8102              <addressOffset>0x20</addressOffset>
8103              <size>32</size>
8104              <access>read-only</access>
8105              <resetValue>0x0</resetValue>
8106              <resetMask>0xFFFFFFFF</resetMask>
8107              <fields>
8108                <field>
8109                  <name>SUBREGION_DISABLE</name>
8110                  <description>This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:
8111Bit 0: subregion 0 disable.
8112Bit 1: subregion 1 disable.
8113Bit 2: subregion 2 disable.
8114Bit 3: subregion 3 disable.
8115Bit 4: subregion 4 disable.
8116Bit 5: subregion 5 disable.
8117Bit 6: subregion 6 disable.
8118Bit 7: subregion 7 disable.
8119
8120Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
8121
8122Note: this field is read-only.</description>
8123                  <bitRange>[7:0]</bitRange>
8124                  <access>read-only</access>
8125                </field>
8126                <field>
8127                  <name>ADDR24</name>
8128                  <description>This field specifies the most significant bits of the 32-bit address of an address region.
8129
8130'ADDR_DEF1': base address of structure.
8131
8132Note: this field is read-only.</description>
8133                  <bitRange>[31:8]</bitRange>
8134                  <access>read-only</access>
8135                </field>
8136              </fields>
8137            </register>
8138            <register>
8139              <name>ATT1</name>
8140              <description>SMPU region attributes 1 (master structure)</description>
8141              <addressOffset>0x24</addressOffset>
8142              <size>32</size>
8143              <access>read-write</access>
8144              <resetValue>0x7000109</resetValue>
8145              <resetMask>0x9F00012D</resetMask>
8146              <fields>
8147                <field>
8148                  <name>UR</name>
8149                  <description>User read enable:
8150'0': Disabled (user, read accesses are NOT allowed).
8151'1': Enabled (user, read accesses are allowed).
8152
8153Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.</description>
8154                  <bitRange>[0:0]</bitRange>
8155                  <access>read-only</access>
8156                </field>
8157                <field>
8158                  <name>UW</name>
8159                  <description>User write enable:
8160'0': Disabled (user, write accesses are NOT allowed).
8161'1': Enabled (user, write accesses are allowed).</description>
8162                  <bitRange>[1:1]</bitRange>
8163                  <access>read-write</access>
8164                </field>
8165                <field>
8166                  <name>UX</name>
8167                  <description>User execute enable:
8168'0': Disabled (user, execute accesses are NOT allowed).
8169'1': Enabled (user, execute accesses are allowed).
8170
8171Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.</description>
8172                  <bitRange>[2:2]</bitRange>
8173                  <access>read-only</access>
8174                </field>
8175                <field>
8176                  <name>PR</name>
8177                  <description>Privileged read enable:
8178'0': Disabled (privileged, read accesses are NOT allowed).
8179'1': Enabled (privileged, read accesses are allowed).
8180
8181Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.</description>
8182                  <bitRange>[3:3]</bitRange>
8183                  <access>read-only</access>
8184                </field>
8185                <field>
8186                  <name>PW</name>
8187                  <description>Privileged write enable:
8188'0': Disabled (privileged, write accesses are NOT allowed).
8189'1': Enabled (privileged, write accesses are allowed).</description>
8190                  <bitRange>[4:4]</bitRange>
8191                  <access>read-write</access>
8192                </field>
8193                <field>
8194                  <name>PX</name>
8195                  <description>Privileged execute enable:
8196'0': Disabled (privileged, execute accesses are NOT allowed).
8197'1': Enabled (privileged, execute accesses are allowed).
8198
8199Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.</description>
8200                  <bitRange>[5:5]</bitRange>
8201                  <access>read-only</access>
8202                </field>
8203                <field>
8204                  <name>NS</name>
8205                  <description>Non-secure:
8206'0': Secure (secure accesses allowed, non-secure access NOT allowed).
8207'1': Non-secure (both secure and non-secure accesses allowed).</description>
8208                  <bitRange>[6:6]</bitRange>
8209                  <access>read-write</access>
8210                </field>
8211                <field>
8212                  <name>PC_MASK_0</name>
8213                  <description>This field specifies protection context identifier based access control for protection context '0'.</description>
8214                  <bitRange>[8:8]</bitRange>
8215                  <access>read-only</access>
8216                </field>
8217                <field>
8218                  <name>PC_MASK_15_TO_1</name>
8219                  <description>This field specifies protection context identifier based access control.
8220Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.</description>
8221                  <bitRange>[23:9]</bitRange>
8222                  <access>read-write</access>
8223                </field>
8224                <field>
8225                  <name>REGION_SIZE</name>
8226                  <description>This field specifies the region size:
8227'7': 256 B region (8 32 B subregions)
8228
8229Note: this field is read-only.</description>
8230                  <bitRange>[28:24]</bitRange>
8231                  <access>read-only</access>
8232                </field>
8233                <field>
8234                  <name>PC_MATCH</name>
8235                  <description>This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:
8236'0': PC field participates in 'access evaluation'.
8237'1': PC field participates in 'matching'.
8238
8239'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions.
8240'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes.
8241
8242Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.</description>
8243                  <bitRange>[30:30]</bitRange>
8244                  <access>read-write</access>
8245                </field>
8246                <field>
8247                  <name>ENABLED</name>
8248                  <description>Region enable:
8249'0': Disabled. A disabled region will never result in a match on the bus transfer address.
8250'1': Enabled.</description>
8251                  <bitRange>[31:31]</bitRange>
8252                  <access>read-write</access>
8253                </field>
8254              </fields>
8255            </register>
8256          </cluster>
8257        </cluster>
8258        <cluster>
8259          <dim>16</dim>
8260          <dimIncrement>1024</dimIncrement>
8261          <name>MPU[%s]</name>
8262          <description>MPU</description>
8263          <addressOffset>0x00004000</addressOffset>
8264          <register>
8265            <name>MS_CTL</name>
8266            <description>Master control</description>
8267            <addressOffset>0x0</addressOffset>
8268            <size>32</size>
8269            <access>read-write</access>
8270            <resetValue>0x0</resetValue>
8271            <resetMask>0xF000F</resetMask>
8272            <fields>
8273              <field>
8274                <name>PC</name>
8275                <description>Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a write transfer with protection context '0' can change this field (protection context 0 has unrestricted access).
8276
8277The CM0+ MPU MS_CTL register is special: the PC field is modifiable by BOTH HW and SW (for all other masters, the MPU MS_CTL.PC field is modifiable by SW ONLY. For CM0+ PC field HW modifications, the following holds:
8278* On entry of a CM0_PC0/1/2/3_HANDLER exception/interrupt handler:
8279   IF (the new PC is the same as MS_CTL.PC)
8280       PC is not affected; PC_SAVED is not affected.
8281   ELSE IF (CM0_PC_CTL.VALID[MS_CTL.PC])
8282       An AHB-Lite bus error is generated for the exception handler fetch;
8283       PC is not affected; PC_SAVED is not affected.
8284   ELSE
8285       PC = 'new PC'; PC_SAVED = PC (push operation).
8286* On entry of any other exception/interrupt handler:
8287   PC = PC_SAVED; PC_SAVED is not affected (pop operation).
8288
8289Note that the CM0_PC0/1/2/3_HANDLER and CM0_PC_CTL registers are part of repecitve CPUSS MMIO registers.
8290
8291Note: this field is NOT used by the DW controllers, DMA controller, AXI DMA controller, CRYPTO component and VIDEOSS.</description>
8292                <bitRange>[3:0]</bitRange>
8293                <access>read-write</access>
8294              </field>
8295              <field>
8296                <name>PC_SAVED</name>
8297                <description>Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields.
8298
8299Note: this field is ONLY used by the CM0+.</description>
8300                <bitRange>[19:16]</bitRange>
8301                <access>read-write</access>
8302              </field>
8303            </fields>
8304          </register>
8305          <register>
8306            <dim>127</dim>
8307            <dimIncrement>4</dimIncrement>
8308            <name>MS_CTL_READ_MIR[%s]</name>
8309            <description>Master control read mirror</description>
8310            <addressOffset>0x4</addressOffset>
8311            <size>32</size>
8312            <access>read-only</access>
8313            <resetValue>0x0</resetValue>
8314            <resetMask>0xF000F</resetMask>
8315            <fields>
8316              <field>
8317                <name>PC</name>
8318                <description>Read-only mirror of MS_CTL.PC</description>
8319                <bitRange>[3:0]</bitRange>
8320                <access>read-only</access>
8321              </field>
8322              <field>
8323                <name>PC_SAVED</name>
8324                <description>Read-only mirror of MS_CTL.PC_SAVED</description>
8325                <bitRange>[19:16]</bitRange>
8326                <access>read-only</access>
8327              </field>
8328            </fields>
8329          </register>
8330          <cluster>
8331            <dim>8</dim>
8332            <dimIncrement>32</dimIncrement>
8333            <name>MPU_STRUCT[%s]</name>
8334            <description>MPU structure</description>
8335            <addressOffset>0x00000200</addressOffset>
8336            <register>
8337              <name>ADDR</name>
8338              <description>MPU region address</description>
8339              <addressOffset>0x0</addressOffset>
8340              <size>32</size>
8341              <access>read-write</access>
8342              <resetValue>0x0</resetValue>
8343              <resetMask>0x0</resetMask>
8344              <fields>
8345                <field>
8346                  <name>SUBREGION_DISABLE</name>
8347                  <description>This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:
8348Bit 0: subregion 0 disable.
8349Bit 1: subregion 1 disable.
8350Bit 2: subregion 2 disable.
8351Bit 3: subregion 3 disable.
8352Bit 4: subregion 4 disable.
8353Bit 5: subregion 5 disable.
8354Bit 6: subregion 6 disable.
8355Bit 7: subregion 7 disable.
8356E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.</description>
8357                  <bitRange>[7:0]</bitRange>
8358                  <access>read-write</access>
8359                </field>
8360                <field>
8361                  <name>ADDR24</name>
8362                  <description>This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.</description>
8363                  <bitRange>[31:8]</bitRange>
8364                  <access>read-write</access>
8365                </field>
8366              </fields>
8367            </register>
8368            <register>
8369              <name>ATT</name>
8370              <description>MPU region attrributes</description>
8371              <addressOffset>0x4</addressOffset>
8372              <size>32</size>
8373              <access>read-write</access>
8374              <resetValue>0x0</resetValue>
8375              <resetMask>0x80000000</resetMask>
8376              <fields>
8377                <field>
8378                  <name>UR</name>
8379                  <description>User read enable:
8380'0': Disabled (user, read accesses are NOT allowed).
8381'1': Enabled (user, read accesses are allowed).</description>
8382                  <bitRange>[0:0]</bitRange>
8383                  <access>read-write</access>
8384                </field>
8385                <field>
8386                  <name>UW</name>
8387                  <description>User write enable:
8388'0': Disabled (user, write accesses are NOT allowed).
8389'1': Enabled (user, write accesses are allowed).</description>
8390                  <bitRange>[1:1]</bitRange>
8391                  <access>read-write</access>
8392                </field>
8393                <field>
8394                  <name>UX</name>
8395                  <description>User execute enable:
8396'0': Disabled (user, execute accesses are NOT allowed).
8397'1': Enabled (user, execute accesses are allowed).</description>
8398                  <bitRange>[2:2]</bitRange>
8399                  <access>read-write</access>
8400                </field>
8401                <field>
8402                  <name>PR</name>
8403                  <description>Privileged read enable:
8404'0': Disabled (privileged, read accesses are NOT allowed).
8405'1': Enabled (privileged, read accesses are allowed).</description>
8406                  <bitRange>[3:3]</bitRange>
8407                  <access>read-write</access>
8408                </field>
8409                <field>
8410                  <name>PW</name>
8411                  <description>Privileged write enable:
8412'0': Disabled (privileged, write accesses are NOT allowed).
8413'1': Enabled (privileged, write accesses are allowed).</description>
8414                  <bitRange>[4:4]</bitRange>
8415                  <access>read-write</access>
8416                </field>
8417                <field>
8418                  <name>PX</name>
8419                  <description>Privileged execute enable:
8420'0': Disabled (privileged, execute accesses are NOT allowed).
8421'1': Enabled (privileged, execute accesses are allowed).</description>
8422                  <bitRange>[5:5]</bitRange>
8423                  <access>read-write</access>
8424                </field>
8425                <field>
8426                  <name>NS</name>
8427                  <description>Non-secure:
8428'0': Secure (secure accesses allowed, non-secure access NOT allowed).
8429'1': Non-secure (both secure and non-secure accesses allowed).</description>
8430                  <bitRange>[6:6]</bitRange>
8431                  <access>read-write</access>
8432                </field>
8433                <field>
8434                  <name>REGION_SIZE</name>
8435                  <description>This field specifies the region size:
8436'0'-'6': Undefined.
8437'7': 256 B region
8438'8': 512 B region
8439'9': 1 KB region
8440'10': 2 KB region
8441'11': 4 KB region
8442'12': 8 KB region
8443'13': 16 KB region
8444'14': 32 KB region
8445'15': 64 KB region
8446'16': 128 KB region
8447'17': 256 KB region
8448'18': 512 KB region
8449'19': 1 MB region
8450'20': 2 MB region
8451'21': 4 MB region
8452'22': 8 MB region
8453'23': 16 MB region
8454'24': 32 MB region
8455'25': 64 MB region
8456'26': 128 MB region
8457'27': 256 MB region
8458'28': 512 MB region
8459'39': 1 GB region
8460'30': 2 GB region
8461'31': 4 GB region</description>
8462                  <bitRange>[28:24]</bitRange>
8463                  <access>read-write</access>
8464                </field>
8465                <field>
8466                  <name>ENABLED</name>
8467                  <description>Region enable:
8468'0': Disabled. A disabled region will never result in a match on the bus transfer address.
8469'1': Enabled.
8470
8471Note: a disabled address region performs logic gating to reduce dynamic power consumption.</description>
8472                  <bitRange>[31:31]</bitRange>
8473                  <access>read-write</access>
8474                </field>
8475              </fields>
8476            </register>
8477          </cluster>
8478        </cluster>
8479      </registers>
8480    </peripheral>
8481    <peripheral>
8482      <name>FLASHC</name>
8483      <description>Flash controller</description>
8484      <baseAddress>0x40240000</baseAddress>
8485      <addressBlock>
8486        <offset>0</offset>
8487        <size>65536</size>
8488        <usage>registers</usage>
8489      </addressBlock>
8490      <registers>
8491        <register>
8492          <name>FLASH_CTL</name>
8493          <description>Control</description>
8494          <addressOffset>0x0</addressOffset>
8495          <size>32</size>
8496          <access>read-write</access>
8497          <resetValue>0x110000</resetValue>
8498          <resetMask>0x77330F</resetMask>
8499          <fields>
8500            <field>
8501              <name>MAIN_WS</name>
8502              <description>FLASH macro main interface wait states:
8503'0': 0 wait states.
8504...
8505'15': 15 wait states</description>
8506              <bitRange>[3:0]</bitRange>
8507              <access>read-write</access>
8508            </field>
8509            <field>
8510              <name>MAIN_MAP</name>
8511              <description>Specifies mapping of FLASH macro main array.
85120: Mapping A.
85131: Mapping B.
8514
8515This field is only used when MAIN_BANK_MODE is '1' (dual bank mode).</description>
8516              <bitRange>[8:8]</bitRange>
8517              <access>read-write</access>
8518            </field>
8519            <field>
8520              <name>WORK_MAP</name>
8521              <description>Specifies mapping of FLASH macro work array.
85220: Mapping A.
85231: Mapping B.
8524
8525This field is only used when WORK_BANK_MODE is '1' (dual bank mode).</description>
8526              <bitRange>[9:9]</bitRange>
8527              <access>read-write</access>
8528            </field>
8529            <field>
8530              <name>MAIN_BANK_MODE</name>
8531              <description>Specifies bank mode of FLASH macro main array.
85320: Single bank mode.
85331: Dual bank mode.</description>
8534              <bitRange>[12:12]</bitRange>
8535              <access>read-write</access>
8536            </field>
8537            <field>
8538              <name>WORK_BANK_MODE</name>
8539              <description>Specifies bank mode of FLASH macro work array.
85400: Single bank mode.
85411: Dual bank mode.</description>
8542              <bitRange>[13:13]</bitRange>
8543              <access>read-write</access>
8544            </field>
8545            <field>
8546              <name>MAIN_ECC_EN</name>
8547              <description>Enable ECC checking for FLASH main interface:
85480: Disabled. ECC checking/reporting on FLASH main interface is disabled. No correctable or non-correctable faults are reported.
85491: Enabled.</description>
8550              <bitRange>[16:16]</bitRange>
8551              <access>read-write</access>
8552            </field>
8553            <field>
8554              <name>MAIN_ECC_INJ_EN</name>
8555              <description>Enable error injection for FLASH main interface.
8556When'1', the parity (ECC_CTL.PARITY[7:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address.</description>
8557              <bitRange>[17:17]</bitRange>
8558              <access>read-write</access>
8559            </field>
8560            <field>
8561              <name>MAIN_ERR_SILENT</name>
8562              <description>Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error, a FLASH macro main interface internal error, a FLASH macro main interface memory hole access):
85630: Bus transfer has a bus error.
85641: Bus transfer does NOT have a bus error; i.e. the error is 'silent'
8565In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer.
8566
8567This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error.
8568
8569Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro main interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered).
8570
8571Note: fault reporting can be used to identify the error that occurred:
8572- FLASH macro main interface internal error.
8573- FLASH macro main interface non-recoverable ECC error.
8574- FLASH macro main interface recoverable ECC error.
8575- FLASH macro main interface memory hole error.</description>
8576              <bitRange>[18:18]</bitRange>
8577              <access>read-write</access>
8578            </field>
8579            <field>
8580              <name>WORK_ECC_EN</name>
8581              <description>Enable ECC checking for FLASH work interface:
85820: Disabled. ECC checking/reporting on FLASH work interface is disabled. No correctable or non-correctable faults are reported.
85831: Enabled.</description>
8584              <bitRange>[20:20]</bitRange>
8585              <access>read-write</access>
8586            </field>
8587            <field>
8588              <name>WORK_ECC_INJ_EN</name>
8589              <description>Enable error injection for FLASH work interface.
8590When'1', the parity (ECC_CTL.PARITY[6:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address.</description>
8591              <bitRange>[21:21]</bitRange>
8592              <access>read-write</access>
8593            </field>
8594            <field>
8595              <name>WORK_ERR_SILENT</name>
8596              <description>Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error, a FLASH macro work interface internal error, a FLASH macro work interface memory hole access):
85970: Bus transfer has a bus error.
85981: Bus transfer does NOT have a bus error; i.e. the error is 'silent'
8599In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer.
8600
8601This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error.
8602
8603Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro work interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered).
8604
8605Note: fault reporting can be used to identify the error that occurred:
8606- FLASH macro work interface internal error.
8607- FLASH macro work interface non-recoverable ECC error.
8608- FLASH macro work interface recoverable ECC error.
8609- FLASH macro work interface memory hole error.</description>
8610              <bitRange>[22:22]</bitRange>
8611              <access>read-write</access>
8612            </field>
8613          </fields>
8614        </register>
8615        <register>
8616          <name>FLASH_PWR_CTL</name>
8617          <description>Flash power control</description>
8618          <addressOffset>0x4</addressOffset>
8619          <size>32</size>
8620          <access>read-write</access>
8621          <resetValue>0x3</resetValue>
8622          <resetMask>0x3</resetMask>
8623          <fields>
8624            <field>
8625              <name>ENABLE</name>
8626              <description>Controls 'enable' pin of the Flash memory.</description>
8627              <bitRange>[0:0]</bitRange>
8628              <access>read-write</access>
8629            </field>
8630            <field>
8631              <name>ENABLE_HV</name>
8632              <description>Controls 'enable_hv' pin of the Flash memory.</description>
8633              <bitRange>[1:1]</bitRange>
8634              <access>read-write</access>
8635            </field>
8636          </fields>
8637        </register>
8638        <register>
8639          <name>FLASH_CMD</name>
8640          <description>Command</description>
8641          <addressOffset>0x8</addressOffset>
8642          <size>32</size>
8643          <access>read-write</access>
8644          <resetValue>0x0</resetValue>
8645          <resetMask>0x3</resetMask>
8646          <fields>
8647            <field>
8648              <name>INV</name>
8649              <description>Invalidation of ALL caches (for CM0+ and CM4) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state.</description>
8650              <bitRange>[0:0]</bitRange>
8651              <access>read-write</access>
8652            </field>
8653            <field>
8654              <name>BUFF_INV</name>
8655              <description>Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks.
8656
8657Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches.</description>
8658              <bitRange>[1:1]</bitRange>
8659              <access>read-write</access>
8660            </field>
8661          </fields>
8662        </register>
8663        <register>
8664          <name>ECC_CTL</name>
8665          <description>ECC control</description>
8666          <addressOffset>0x2A0</addressOffset>
8667          <size>32</size>
8668          <access>read-write</access>
8669          <resetValue>0x0</resetValue>
8670          <resetMask>0xFFFFFFFF</resetMask>
8671          <fields>
8672            <field>
8673              <name>WORD_ADDR</name>
8674              <description>Specifies the word address where an error will be injected.
8675- For cache SRAM ECC, the word address WORD_ADDR[23:0] is device address A[25:2]. On a FLASH macro refill to this word address and when the corresponding CM0/4_CA_CTL.RAM_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) is injected and stored in the cache.
8676- For FLASH main interface ECC, the word address WORD_ADDR[23:0] is device address A[26:3]. On a FLASH main interface read and when FLASH_CTL.MAIN_ECC_INJ_EN bit is '1', the parity (PARITY[7:0]) replaces the FLASH macro parity (FLASH main interface read path is manipulated).
8677- For FLASH work interface ECC, the word address WORD_ADDR[23:0] is device address A[24:2]. On a FLASH work interface read and when FLASH_CTL.WORK_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) replaces the FLASH macro parity (FLASH work interface read path is manipulated).</description>
8678              <bitRange>[23:0]</bitRange>
8679              <access>read-write</access>
8680            </field>
8681            <field>
8682              <name>PARITY</name>
8683              <description>ECC parity to use for ECC error injection at address WORD_ADDR.
8684- For cache SRAM ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word.
8685- For FLASH main interface ECC, the 8-bit parity PARITY[7:0] is for a 64-bit word.
8686- For FLASH work interface ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word.</description>
8687              <bitRange>[31:24]</bitRange>
8688              <access>read-write</access>
8689            </field>
8690          </fields>
8691        </register>
8692        <register>
8693          <name>FM_SRAM_ECC_CTL0</name>
8694          <description>eCT Flash SRAM ECC control 0</description>
8695          <addressOffset>0x2B0</addressOffset>
8696          <size>32</size>
8697          <access>read-write</access>
8698          <resetValue>0x0</resetValue>
8699          <resetMask>0xFFFFFFFF</resetMask>
8700          <fields>
8701            <field>
8702              <name>ECC_INJ_DATA</name>
8703              <description>32-bit data for ECC error injection test of eCT Flash SRAM ECC logic.</description>
8704              <bitRange>[31:0]</bitRange>
8705              <access>read-write</access>
8706            </field>
8707          </fields>
8708        </register>
8709        <register>
8710          <name>FM_SRAM_ECC_CTL1</name>
8711          <description>eCT Flash SRAM ECC control 1</description>
8712          <addressOffset>0x2B4</addressOffset>
8713          <size>32</size>
8714          <access>read-write</access>
8715          <resetValue>0x0</resetValue>
8716          <resetMask>0x7F</resetMask>
8717          <fields>
8718            <field>
8719              <name>ECC_INJ_PARITY</name>
8720              <description>7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic.</description>
8721              <bitRange>[6:0]</bitRange>
8722              <access>read-write</access>
8723            </field>
8724          </fields>
8725        </register>
8726        <register>
8727          <name>FM_SRAM_ECC_CTL2</name>
8728          <description>eCT Flash SRAM ECC control 2</description>
8729          <addressOffset>0x2B8</addressOffset>
8730          <size>32</size>
8731          <access>read-only</access>
8732          <resetValue>0x0</resetValue>
8733          <resetMask>0xFFFFFFFF</resetMask>
8734          <fields>
8735            <field>
8736              <name>CORRECTED_DATA</name>
8737              <description>32-bit corrected data output of the ECC syndrome logic.</description>
8738              <bitRange>[31:0]</bitRange>
8739              <access>read-only</access>
8740            </field>
8741          </fields>
8742        </register>
8743        <register>
8744          <name>FM_SRAM_ECC_CTL3</name>
8745          <description>eCT Flash SRAM ECC control 3</description>
8746          <addressOffset>0x2BC</addressOffset>
8747          <size>32</size>
8748          <access>read-write</access>
8749          <resetValue>0x1</resetValue>
8750          <resetMask>0x111</resetMask>
8751          <fields>
8752            <field>
8753              <name>ECC_ENABLE</name>
8754              <description>ECC generation/check enable for eCT Flash SRAM memory.</description>
8755              <bitRange>[0:0]</bitRange>
8756              <access>read-write</access>
8757            </field>
8758            <field>
8759              <name>ECC_INJ_EN</name>
8760              <description>eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test:
87611. Write corrupted or uncorrupted 39-bit data to FM_SRAM_ECC_CTL0/1 registers.
87622. Set the ECC_INJ_EN bit to '1'.
87633. Confirm that the bit ECC_TEST_FAIL is '0'. If this is not the case, start over at item 1 because the eCT Flash was not idle.
87644. Check the corrected data in FM_SRAM_ECC_CTL2.
87655. Confirm that fault was reported to fault structure, and check syndrome (only applicable if
8766corrupted data was written in step 1).
87676. If not finished, start over at 1 with different data.</description>
8768              <bitRange>[4:4]</bitRange>
8769              <access>read-write</access>
8770            </field>
8771            <field>
8772              <name>ECC_TEST_FAIL</name>
8773              <description>Status of ECC test.
87741 : ECC test failed because eCT Flash macro is busy and using the SRAM.
87750: ECC was performed.</description>
8776              <bitRange>[8:8]</bitRange>
8777              <access>read-only</access>
8778            </field>
8779          </fields>
8780        </register>
8781        <register>
8782          <name>CM0_CA_CTL0</name>
8783          <description>CM0+ cache control</description>
8784          <addressOffset>0x400</addressOffset>
8785          <size>32</size>
8786          <access>read-write</access>
8787          <resetValue>0xC0000001</resetValue>
8788          <resetMask>0xC7030003</resetMask>
8789          <fields>
8790            <field>
8791              <name>RAM_ECC_EN</name>
8792              <description>Enable ECC checking for cache accesses:
87930: Disabled.
87941: Enabled.</description>
8795              <bitRange>[0:0]</bitRange>
8796              <access>read-write</access>
8797            </field>
8798            <field>
8799              <name>RAM_ECC_INJ_EN</name>
8800              <description>Enable error injection for cache.
8801When '1', the parity (ECC_CTL.PARITY[6:0]) is used when a refill is done from the FLASH macro to the ECC_CTL.WORD_ADDR[23:0] word address.</description>
8802              <bitRange>[1:1]</bitRange>
8803              <access>read-write</access>
8804            </field>
8805            <field>
8806              <name>WAY</name>
8807              <description>Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2.</description>
8808              <bitRange>[17:16]</bitRange>
8809              <access>read-write</access>
8810            </field>
8811            <field>
8812              <name>SET_ADDR</name>
8813              <description>Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2.</description>
8814              <bitRange>[26:24]</bitRange>
8815              <access>read-write</access>
8816            </field>
8817            <field>
8818              <name>PREF_EN</name>
8819              <description>Prefetch enable:
88200: Disabled.
88211: Enabled.
8822
8823Prefetching requires the cache to be enabled; i.e. ENABLED is '1'.</description>
8824              <bitRange>[30:30]</bitRange>
8825              <access>read-write</access>
8826            </field>
8827            <field>
8828              <name>CA_EN</name>
8829              <description>Cache enable:
88300: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way).
88311: Enabled.</description>
8832              <bitRange>[31:31]</bitRange>
8833              <access>read-write</access>
8834            </field>
8835          </fields>
8836        </register>
8837        <register>
8838          <name>CM0_CA_CTL1</name>
8839          <description>CM0+ cache control</description>
8840          <addressOffset>0x404</addressOffset>
8841          <size>32</size>
8842          <access>read-write</access>
8843          <resetValue>0xFA050003</resetValue>
8844          <resetMask>0xFFFF0003</resetMask>
8845          <fields>
8846            <field>
8847              <name>PWR_MODE</name>
8848              <description>Specifies power mode for CM0 cache.
8849The following sequnece should be followed for turning OFF/ON the cache SRAM.
8850Turn OFF sequence:
8851a) Write CM0_CA_CTL0 to disable cache.
8852b) Write CM0_CA_CTL1 to turn OFF cache SRAM.
8853Turn ON sequence:
8854a) Write CM0_CA_CTL1 to turn ON cache SRAM.
8855b) Delay to allow power up of cache SRAM. Delay should be at a minimum of CM0_CA_CTL2.PWRUP_DELAY CLK_SLOW clock cycles.
8856c) Write CM0_CA_CTL0 to enable cache.</description>
8857              <bitRange>[1:0]</bitRange>
8858              <access>read-write</access>
8859              <enumeratedValues>
8860                <enumeratedValue>
8861                  <name>OFF</name>
8862                  <description>Power OFF the CM0 cache SRAM.</description>
8863                  <value>0</value>
8864                </enumeratedValue>
8865                <enumeratedValue>
8866                  <name>RSVD</name>
8867                  <description>Undefined</description>
8868                  <value>1</value>
8869                </enumeratedValue>
8870                <enumeratedValue>
8871                  <name>RETAINED</name>
8872                  <description>Put CM0 cache SRAM in retained mode.</description>
8873                  <value>2</value>
8874                </enumeratedValue>
8875                <enumeratedValue>
8876                  <name>ENABLED</name>
8877                  <description>Enable/Turn ON the CM0 cache SRAM.</description>
8878                  <value>3</value>
8879                </enumeratedValue>
8880              </enumeratedValues>
8881            </field>
8882            <field>
8883              <name>VECTKEYSTAT</name>
8884              <description>Register key (to prevent accidental writes).
8885- Should be written with a 0x05fa key value for the write to take effect.
8886- Always reads as 0xfa05.
8887
8888Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.</description>
8889              <bitRange>[31:16]</bitRange>
8890              <access>read-only</access>
8891            </field>
8892          </fields>
8893        </register>
8894        <register>
8895          <name>CM0_CA_CTL2</name>
8896          <description>CM0+ cache control</description>
8897          <addressOffset>0x408</addressOffset>
8898          <size>32</size>
8899          <access>read-write</access>
8900          <resetValue>0x12C</resetValue>
8901          <resetMask>0x3FF</resetMask>
8902          <fields>
8903            <field>
8904              <name>PWRUP_DELAY</name>
8905              <description>Number clock cycles delay needed after power domain power up</description>
8906              <bitRange>[9:0]</bitRange>
8907              <access>read-write</access>
8908            </field>
8909          </fields>
8910        </register>
8911        <register>
8912          <name>CM0_CA_STATUS0</name>
8913          <description>CM0+ cache status 0</description>
8914          <addressOffset>0x440</addressOffset>
8915          <size>32</size>
8916          <access>read-only</access>
8917          <resetValue>0x0</resetValue>
8918          <resetMask>0xFFFFFFFF</resetMask>
8919          <fields>
8920            <field>
8921              <name>VALID32</name>
8922              <description>Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR.</description>
8923              <bitRange>[31:0]</bitRange>
8924              <access>read-only</access>
8925            </field>
8926          </fields>
8927        </register>
8928        <register>
8929          <name>CM0_CA_STATUS1</name>
8930          <description>CM0+ cache status 1</description>
8931          <addressOffset>0x444</addressOffset>
8932          <size>32</size>
8933          <access>read-only</access>
8934          <resetValue>0x0</resetValue>
8935          <resetMask>0x0</resetMask>
8936          <fields>
8937            <field>
8938              <name>TAG</name>
8939              <description>Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR.</description>
8940              <bitRange>[31:0]</bitRange>
8941              <access>read-only</access>
8942            </field>
8943          </fields>
8944        </register>
8945        <register>
8946          <name>CM0_CA_STATUS2</name>
8947          <description>CM0+ cache status 2</description>
8948          <addressOffset>0x448</addressOffset>
8949          <size>32</size>
8950          <access>read-only</access>
8951          <resetValue>0x0</resetValue>
8952          <resetMask>0x0</resetMask>
8953          <fields>
8954            <field>
8955              <name>LRU</name>
8956              <description>Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y):
8957Bit 5: 0_LRU_1: way 0 less recently used than way 1.
8958Bit 4: 0_LRU_2.
8959Bit 3: 0_LRU_3.
8960Bit 2: 1_LRU_2.
8961Bit 1: 1_LRU_3.
8962Bit 0: 2_LRU_3.</description>
8963              <bitRange>[5:0]</bitRange>
8964              <access>read-only</access>
8965            </field>
8966          </fields>
8967        </register>
8968        <register>
8969          <name>CM0_STATUS</name>
8970          <description>CM0+ interface status</description>
8971          <addressOffset>0x460</addressOffset>
8972          <size>32</size>
8973          <access>read-write</access>
8974          <resetValue>0x0</resetValue>
8975          <resetMask>0x3</resetMask>
8976          <fields>
8977            <field>
8978              <name>MAIN_INTERNAL_ERR</name>
8979              <description>Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access (or debug access via SYS_AP/CM0_AP).
8980
8981SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error.
8982
8983Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT.</description>
8984              <bitRange>[0:0]</bitRange>
8985              <access>read-write</access>
8986            </field>
8987            <field>
8988              <name>WORK_INTERNAL_ERR</name>
8989              <description>See CM0_STATUS.MAIN_INTERNAL_ERROR.</description>
8990              <bitRange>[1:1]</bitRange>
8991              <access>read-write</access>
8992            </field>
8993          </fields>
8994        </register>
8995        <register>
8996          <name>CM4_CA_CTL0</name>
8997          <description>CM4 cache control</description>
8998          <addressOffset>0x480</addressOffset>
8999          <size>32</size>
9000          <access>read-write</access>
9001          <resetValue>0xC0000001</resetValue>
9002          <resetMask>0xC7030003</resetMask>
9003          <fields>
9004            <field>
9005              <name>RAM_ECC_EN</name>
9006              <description>See CM0_CA_CTL.</description>
9007              <bitRange>[0:0]</bitRange>
9008              <access>read-write</access>
9009            </field>
9010            <field>
9011              <name>RAM_ECC_INJ_EN</name>
9012              <description>See CM0_CA_CTL.</description>
9013              <bitRange>[1:1]</bitRange>
9014              <access>read-write</access>
9015            </field>
9016            <field>
9017              <name>WAY</name>
9018              <description>See CM0_CA_CTL.</description>
9019              <bitRange>[17:16]</bitRange>
9020              <access>read-write</access>
9021            </field>
9022            <field>
9023              <name>SET_ADDR</name>
9024              <description>See CM0_CA_CTL.</description>
9025              <bitRange>[26:24]</bitRange>
9026              <access>read-write</access>
9027            </field>
9028            <field>
9029              <name>PREF_EN</name>
9030              <description>See CM0_CA_CTL.</description>
9031              <bitRange>[30:30]</bitRange>
9032              <access>read-write</access>
9033            </field>
9034            <field>
9035              <name>CA_EN</name>
9036              <description>See CM0_CA_CTL.</description>
9037              <bitRange>[31:31]</bitRange>
9038              <access>read-write</access>
9039            </field>
9040          </fields>
9041        </register>
9042        <register>
9043          <name>CM4_CA_CTL1</name>
9044          <description>CM4 cache control</description>
9045          <addressOffset>0x484</addressOffset>
9046          <size>32</size>
9047          <access>read-write</access>
9048          <resetValue>0xFA050003</resetValue>
9049          <resetMask>0xFFFF0003</resetMask>
9050          <fields>
9051            <field>
9052              <name>PWR_MODE</name>
9053              <description>Specifies power mode for CM4 cache. Refer CM0_CA_CTL1 for more details.</description>
9054              <bitRange>[1:0]</bitRange>
9055              <access>read-write</access>
9056              <enumeratedValues>
9057                <enumeratedValue>
9058                  <name>OFF</name>
9059                  <description>See CM0_CA_CTL1</description>
9060                  <value>0</value>
9061                </enumeratedValue>
9062                <enumeratedValue>
9063                  <name>RSVD</name>
9064                  <description>Undefined</description>
9065                  <value>1</value>
9066                </enumeratedValue>
9067                <enumeratedValue>
9068                  <name>RETAINED</name>
9069                  <description>See CM0_CA_CTL1</description>
9070                  <value>2</value>
9071                </enumeratedValue>
9072                <enumeratedValue>
9073                  <name>ENABLED</name>
9074                  <description>See CM0_CA_CTL1</description>
9075                  <value>3</value>
9076                </enumeratedValue>
9077              </enumeratedValues>
9078            </field>
9079            <field>
9080              <name>VECTKEYSTAT</name>
9081              <description>Register key (to prevent accidental writes).
9082- Should be written with a 0x05fa key value for the write to take effect.
9083- Always reads as 0xfa05.
9084
9085Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.</description>
9086              <bitRange>[31:16]</bitRange>
9087              <access>read-only</access>
9088            </field>
9089          </fields>
9090        </register>
9091        <register>
9092          <name>CM4_CA_CTL2</name>
9093          <description>CM4 cache control</description>
9094          <addressOffset>0x488</addressOffset>
9095          <size>32</size>
9096          <access>read-write</access>
9097          <resetValue>0x12C</resetValue>
9098          <resetMask>0x3FF</resetMask>
9099          <fields>
9100            <field>
9101              <name>PWRUP_DELAY</name>
9102              <description>Number clock cycles delay needed after power domain power up</description>
9103              <bitRange>[9:0]</bitRange>
9104              <access>read-write</access>
9105            </field>
9106          </fields>
9107        </register>
9108        <register>
9109          <name>CM4_CA_STATUS0</name>
9110          <description>CM4 cache status 0</description>
9111          <addressOffset>0x4C0</addressOffset>
9112          <size>32</size>
9113          <access>read-only</access>
9114          <resetValue>0x0</resetValue>
9115          <resetMask>0xFFFFFFFF</resetMask>
9116          <fields>
9117            <field>
9118              <name>VALID32</name>
9119              <description>See CM0_CA_STATUS0.</description>
9120              <bitRange>[31:0]</bitRange>
9121              <access>read-only</access>
9122            </field>
9123          </fields>
9124        </register>
9125        <register>
9126          <name>CM4_CA_STATUS1</name>
9127          <description>CM4 cache status 1</description>
9128          <addressOffset>0x4C4</addressOffset>
9129          <size>32</size>
9130          <access>read-only</access>
9131          <resetValue>0x0</resetValue>
9132          <resetMask>0x0</resetMask>
9133          <fields>
9134            <field>
9135              <name>TAG</name>
9136              <description>See CM0_CA_STATUS1.</description>
9137              <bitRange>[31:0]</bitRange>
9138              <access>read-only</access>
9139            </field>
9140          </fields>
9141        </register>
9142        <register>
9143          <name>CM4_CA_STATUS2</name>
9144          <description>CM4 cache status 2</description>
9145          <addressOffset>0x4C8</addressOffset>
9146          <size>32</size>
9147          <access>read-only</access>
9148          <resetValue>0x0</resetValue>
9149          <resetMask>0x0</resetMask>
9150          <fields>
9151            <field>
9152              <name>LRU</name>
9153              <description>See CM0_CA_STATUS2.</description>
9154              <bitRange>[5:0]</bitRange>
9155              <access>read-only</access>
9156            </field>
9157          </fields>
9158        </register>
9159        <register>
9160          <name>CM4_STATUS</name>
9161          <description>CM4 interface status</description>
9162          <addressOffset>0x4E0</addressOffset>
9163          <size>32</size>
9164          <access>read-write</access>
9165          <resetValue>0x0</resetValue>
9166          <resetMask>0x3</resetMask>
9167          <fields>
9168            <field>
9169              <name>MAIN_INTERNAL_ERR</name>
9170              <description>Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM4 access (or debug access via SYS_AP/CM4_AP).
9171
9172SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error.
9173
9174Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT.</description>
9175              <bitRange>[0:0]</bitRange>
9176              <access>read-write</access>
9177            </field>
9178            <field>
9179              <name>WORK_INTERNAL_ERR</name>
9180              <description>See CM4_STATUS.MAIN_INTERNAL_ERROR.</description>
9181              <bitRange>[1:1]</bitRange>
9182              <access>read-write</access>
9183            </field>
9184          </fields>
9185        </register>
9186        <register>
9187          <name>CRYPTO_BUFF_CTL</name>
9188          <description>Cryptography buffer control</description>
9189          <addressOffset>0x500</addressOffset>
9190          <size>32</size>
9191          <access>read-write</access>
9192          <resetValue>0x40000000</resetValue>
9193          <resetMask>0x40000000</resetMask>
9194          <fields>
9195            <field>
9196              <name>PREF_EN</name>
9197              <description>Prefetch enable:
91980: Disabled.
91991: Enabled.
9200A prefetch will be done when there is read 'hit' on the last 32-bit word of the buffer.
9201For eCT work Flash, prefetch will not be done.</description>
9202              <bitRange>[30:30]</bitRange>
9203              <access>read-write</access>
9204            </field>
9205          </fields>
9206        </register>
9207        <register>
9208          <name>DW0_BUFF_CTL</name>
9209          <description>Datawire 0 buffer control</description>
9210          <addressOffset>0x580</addressOffset>
9211          <size>32</size>
9212          <access>read-write</access>
9213          <resetValue>0x40000000</resetValue>
9214          <resetMask>0x40000000</resetMask>
9215          <fields>
9216            <field>
9217              <name>PREF_EN</name>
9218              <description>See CRYPTO_BUFF_CTL.</description>
9219              <bitRange>[30:30]</bitRange>
9220              <access>read-write</access>
9221            </field>
9222          </fields>
9223        </register>
9224        <register>
9225          <name>DW1_BUFF_CTL</name>
9226          <description>Datawire 1 buffer control</description>
9227          <addressOffset>0x600</addressOffset>
9228          <size>32</size>
9229          <access>read-write</access>
9230          <resetValue>0x40000000</resetValue>
9231          <resetMask>0x40000000</resetMask>
9232          <fields>
9233            <field>
9234              <name>PREF_EN</name>
9235              <description>See CRYPTO_BUFF_CTL.</description>
9236              <bitRange>[30:30]</bitRange>
9237              <access>read-write</access>
9238            </field>
9239          </fields>
9240        </register>
9241        <register>
9242          <name>DMAC_BUFF_CTL</name>
9243          <description>DMA controller buffer control</description>
9244          <addressOffset>0x680</addressOffset>
9245          <size>32</size>
9246          <access>read-write</access>
9247          <resetValue>0x40000000</resetValue>
9248          <resetMask>0x40000000</resetMask>
9249          <fields>
9250            <field>
9251              <name>PREF_EN</name>
9252              <description>See CRYPTO_BUFF_CTL.</description>
9253              <bitRange>[30:30]</bitRange>
9254              <access>read-write</access>
9255            </field>
9256          </fields>
9257        </register>
9258        <register>
9259          <name>EXT_MS0_BUFF_CTL</name>
9260          <description>External master 0 buffer control</description>
9261          <addressOffset>0x700</addressOffset>
9262          <size>32</size>
9263          <access>read-write</access>
9264          <resetValue>0x40000000</resetValue>
9265          <resetMask>0x40000000</resetMask>
9266          <fields>
9267            <field>
9268              <name>PREF_EN</name>
9269              <description>See CRYPTO_BUFF_CTL.</description>
9270              <bitRange>[30:30]</bitRange>
9271              <access>read-write</access>
9272            </field>
9273          </fields>
9274        </register>
9275        <register>
9276          <name>EXT_MS1_BUFF_CTL</name>
9277          <description>External master 1 buffer control</description>
9278          <addressOffset>0x780</addressOffset>
9279          <size>32</size>
9280          <access>read-write</access>
9281          <resetValue>0x40000000</resetValue>
9282          <resetMask>0x40000000</resetMask>
9283          <fields>
9284            <field>
9285              <name>PREF_EN</name>
9286              <description>See CRYPTO_BUFF_CTL.</description>
9287              <bitRange>[30:30]</bitRange>
9288              <access>read-write</access>
9289            </field>
9290          </fields>
9291        </register>
9292        <cluster>
9293          <name>FM_CTL_ECT</name>
9294          <description>Flash Macro Registers</description>
9295          <addressOffset>0x0000F000</addressOffset>
9296          <register>
9297            <name>FM_CTL</name>
9298            <description>Flash Macro Control</description>
9299            <addressOffset>0x0</addressOffset>
9300            <size>32</size>
9301            <access>read-write</access>
9302            <resetValue>0x0</resetValue>
9303            <resetMask>0x8000001F</resetMask>
9304            <fields>
9305              <field>
9306                <name>FM_MODE</name>
9307                <description>Flash macro mode selection:
9308d0: Read/Idle - Normal mode, read array enabled
9309d1: Not Used - the 1st analog POR is done by enable/enable_hv
9310d2 - POR FUR Download - Downloads critical Flash initialization data from OTP (BG, rd, redu, etc....)
9311d3 - POR IRAM MMR Download - Downloads from OTP region the MMR / IRAM into to the 8051 RDL shadows
9312d4 - POR SW Download - Downloads from OTP region the SW code into to the 8051 MCU SRAM
9313d5 - POR Code_Work Prepare - Loads the Code and Work Flash MG's to be ready for user mode operation
9314d6 - Not Used
9315d7 - Program 32b (WORK) - Used as program confirm command for  32 (Work) bits program
9316d8 - Program 64b (CODE) - Used as program confirm command for  64 (Code) bits program
9317d9 - Program 256b (CODE) - Used as program confirm command for  256 (Code) bits program
9318d10: Program Page (CODE) - Used as program confirm command for page program for Code flash
9319d11: Not Used
9320d12 - Sector Erase - Erase for all kinds of sectors (Code/Work/SMS)
9321d13 - Blank check Entry (UBC)
9322d14 - Blank Check Read 32bit (WORK) - Blank check mode
9323d15 - Blank check Exit
9324d16 - Not Used
9325d17 - Erase Suspend - Suspend command to the Erase operation
9326d18 - Erase Resume - Resume command to Erase suspended operation
9327d19 - Not Used
9328d20- Not Used
9329d21- Not Used
9330d22- Not Used
9331d23- Not Used
9332d24- Not Used
9333d25- Not Used
9334d26- Not Used
9335d27- Not Used
9336d28- Not Used
9337d29- Not Used
9338d30: Not Used
9339d31: Not Used</description>
9340                <bitRange>[4:0]</bitRange>
9341                <access>read-write</access>
9342              </field>
9343              <field>
9344                <name>EMB_START</name>
9345                <description>'0': not active
9346'1': starts the actual embedded operation</description>
9347                <bitRange>[31:31]</bitRange>
9348                <access>read-write</access>
9349              </field>
9350            </fields>
9351          </register>
9352          <register>
9353            <name>FM_CODE_MARGIN</name>
9354            <description>Flash Macro Margin Mode on Code Flash</description>
9355            <addressOffset>0x4</addressOffset>
9356            <size>32</size>
9357            <access>read-write</access>
9358            <resetValue>0x3943</resetValue>
9359            <resetMask>0xE000FFFF</resetMask>
9360            <fields>
9361              <field>
9362                <name>MARGIN_DCS_TRIM</name>
9363                <description>see above table to set the DCS reference current value to be used during Margin mode. (default set to 5uS = 0x143) which gives a Margin to the Erase side. 7uA would probably be used for Margin to the PGM side</description>
9364                <bitRange>[8:0]</bitRange>
9365                <access>read-write</access>
9366              </field>
9367              <field>
9368                <name>MARGIN_DCS_TRIM_EN</name>
9369                <description>0:  internal device defaults used from Margin reads reference current
93701:  MARGIN_DCS_TRIM configuration is used during Margin read</description>
9371                <bitRange>[9:9]</bitRange>
9372                <access>read-write</access>
9373              </field>
9374              <field>
9375                <name>MARGIN_RDREG_TRIM</name>
9376                <description>rdreg_c trim to be used in Margin mode if enabled by MARGIN_MODE_RDREG_CHNG_EN</description>
9377                <bitRange>[15:10]</bitRange>
9378                <access>read-write</access>
9379              </field>
9380              <field>
9381                <name>MARGIN_PGM_ERS_B</name>
9382                <description>0: ERS Margin is checked
93831: PGM Margin is checked</description>
9384                <bitRange>[29:29]</bitRange>
9385                <access>read-write</access>
9386              </field>
9387              <field>
9388                <name>MARGIN_MODE_RDREG_CHNG_EN</name>
9389                <description>when set will also use the MARGIN_RDREG_TRIM from above. Default is not to use</description>
9390                <bitRange>[30:30]</bitRange>
9391                <access>read-write</access>
9392              </field>
9393              <field>
9394                <name>MARGIN_MODE_EN</name>
9395                <description>when set puts the s40ect Flash IP In Margin mode</description>
9396                <bitRange>[31:31]</bitRange>
9397                <access>read-write</access>
9398              </field>
9399            </fields>
9400          </register>
9401          <register>
9402            <name>FM_ADDR</name>
9403            <description>Flash Macro Address</description>
9404            <addressOffset>0x8</addressOffset>
9405            <size>32</size>
9406            <access>write-only</access>
9407            <resetValue>0x0</resetValue>
9408            <resetMask>0xFFFFFFFF</resetMask>
9409            <fields>
9410              <field>
9411                <name>FM_ADDR</name>
9412                <description>Code or Work Flash Address to be used during write operations (PGM/ERS)</description>
9413                <bitRange>[31:0]</bitRange>
9414                <access>write-only</access>
9415              </field>
9416            </fields>
9417          </register>
9418          <register>
9419            <name>INTR</name>
9420            <description>Interrupt</description>
9421            <addressOffset>0x20</addressOffset>
9422            <size>32</size>
9423            <access>read-write</access>
9424            <resetValue>0x0</resetValue>
9425            <resetMask>0x1</resetMask>
9426            <fields>
9427              <field>
9428                <name>INTR</name>
9429                <description>Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit.</description>
9430                <bitRange>[0:0]</bitRange>
9431                <access>read-write</access>
9432              </field>
9433            </fields>
9434          </register>
9435          <register>
9436            <name>INTR_SET</name>
9437            <description>Interrupt Set</description>
9438            <addressOffset>0x24</addressOffset>
9439            <size>32</size>
9440            <access>read-write</access>
9441            <resetValue>0x0</resetValue>
9442            <resetMask>0x1</resetMask>
9443            <fields>
9444              <field>
9445                <name>INTR_SET</name>
9446                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
9447                <bitRange>[0:0]</bitRange>
9448                <access>read-write</access>
9449              </field>
9450            </fields>
9451          </register>
9452          <register>
9453            <name>INTR_MASK</name>
9454            <description>Interrupt Mask</description>
9455            <addressOffset>0x28</addressOffset>
9456            <size>32</size>
9457            <access>read-write</access>
9458            <resetValue>0x0</resetValue>
9459            <resetMask>0x1</resetMask>
9460            <fields>
9461              <field>
9462                <name>INTR_MASK</name>
9463                <description>Mask for corresponding field in the INTR register</description>
9464                <bitRange>[0:0]</bitRange>
9465                <access>read-write</access>
9466              </field>
9467            </fields>
9468          </register>
9469          <register>
9470            <name>INTR_MASKED</name>
9471            <description>Interrupt Masked</description>
9472            <addressOffset>0x2C</addressOffset>
9473            <size>32</size>
9474            <access>read-only</access>
9475            <resetValue>0x0</resetValue>
9476            <resetMask>0x1</resetMask>
9477            <fields>
9478              <field>
9479                <name>INTR_MASKED</name>
9480                <description>Logical and of corresponding request and mask fields.</description>
9481                <bitRange>[0:0]</bitRange>
9482                <access>read-only</access>
9483              </field>
9484            </fields>
9485          </register>
9486          <register>
9487            <name>ECC_OVERRIDE</name>
9488            <description>ECC Data In override information and control bits</description>
9489            <addressOffset>0x30</addressOffset>
9490            <size>32</size>
9491            <access>write-only</access>
9492            <resetValue>0x0</resetValue>
9493            <resetMask>0xC00000FF</resetMask>
9494            <fields>
9495              <field>
9496                <name>ECC_OVERRIDE_SYNDROME</name>
9497                <description>The override syndrome itself to be used in case one of the enables are set. It will take [7:0] in the case of Code flash and [6:0] in the case of work flash, to bypass the internal generated syndrome</description>
9498                <bitRange>[7:0]</bitRange>
9499                <access>write-only</access>
9500              </field>
9501              <field>
9502                <name>ECC_OVERRIDE_WORK</name>
9503                <description>0: no override. Using internal ECC engine to calculate the ECC of the Work Flash</description>
9504                <bitRange>[30:30]</bitRange>
9505                <access>write-only</access>
9506              </field>
9507              <field>
9508                <name>ECC_OVERRIDE_CODE</name>
9509                <description>0: no override. Using internal ECC engine to calculate the ECC of the Code Flash</description>
9510                <bitRange>[31:31]</bitRange>
9511                <access>write-only</access>
9512              </field>
9513            </fields>
9514          </register>
9515          <register>
9516            <name>FM_DATA</name>
9517            <description>Flash macro data_in[31 to 0] both Code and Work Flash</description>
9518            <addressOffset>0x40</addressOffset>
9519            <size>32</size>
9520            <access>write-only</access>
9521            <resetValue>0x0</resetValue>
9522            <resetMask>0xFFFFFFFF</resetMask>
9523            <fields>
9524              <field>
9525                <name>FM_DATA</name>
9526                <description>Pgm command data in going to the internal write buffer (WBUF).</description>
9527                <bitRange>[31:0]</bitRange>
9528                <access>write-only</access>
9529              </field>
9530            </fields>
9531          </register>
9532          <register>
9533            <name>BOOKMARK</name>
9534            <description>Bookmark register - keeps the current FW HV seq</description>
9535            <addressOffset>0x64</addressOffset>
9536            <size>32</size>
9537            <access>read-write</access>
9538            <resetValue>0x0</resetValue>
9539            <resetMask>0xFFFFFFFF</resetMask>
9540            <fields>
9541              <field>
9542                <name>BOOKMARK</name>
9543                <description>Used by FW. Keeps the Current HV cycle sequence</description>
9544                <bitRange>[31:0]</bitRange>
9545                <access>read-write</access>
9546              </field>
9547            </fields>
9548          </register>
9549          <register>
9550            <name>MAIN_FLASH_SAFETY</name>
9551            <description>Main (Code) Flash Security enable</description>
9552            <addressOffset>0x400</addressOffset>
9553            <size>32</size>
9554            <access>read-write</access>
9555            <resetValue>0x0</resetValue>
9556            <resetMask>0x1</resetMask>
9557            <fields>
9558              <field>
9559                <name>MAINFLASHWRITEENABLE</name>
9560                <description>'0': Main Flash embedded operations are blocked
9561'1': Main Flash embedded operations are enabled</description>
9562                <bitRange>[0:0]</bitRange>
9563                <access>read-write</access>
9564              </field>
9565            </fields>
9566          </register>
9567          <register>
9568            <name>STATUS</name>
9569            <description>Status read from Flash Macro</description>
9570            <addressOffset>0x404</addressOffset>
9571            <size>32</size>
9572            <access>read-only</access>
9573            <resetValue>0x80000000</resetValue>
9574            <resetMask>0xF800007F</resetMask>
9575            <fields>
9576              <field>
9577                <name>PGM_CODE</name>
9578                <description>Indicates if active PGM operation to the Code flash is taking place
95790: not running
95801: running</description>
9581                <bitRange>[0:0]</bitRange>
9582                <access>read-only</access>
9583              </field>
9584              <field>
9585                <name>PGM_WORK</name>
9586                <description>Indicates if active PGM operation to the Work flash is taking place
95870: not running
95881: running</description>
9589                <bitRange>[1:1]</bitRange>
9590                <access>read-only</access>
9591              </field>
9592              <field>
9593                <name>ERASE_CODE</name>
9594                <description>Indicates if active Erase operation to the Code flash is taking place
95950: not running
95961: running</description>
9597                <bitRange>[2:2]</bitRange>
9598                <access>read-only</access>
9599              </field>
9600              <field>
9601                <name>ERASE_WORK</name>
9602                <description>Indicates if active Erase operation to the Work flash is taking place
96030: not running
96041: running</description>
9605                <bitRange>[3:3]</bitRange>
9606                <access>read-only</access>
9607              </field>
9608              <field>
9609                <name>ERS_SUSPEND</name>
9610                <description>Indicates if Erase operation (Code/Work) is currently being suspended
96110: not suspended
96121: suspended</description>
9613                <bitRange>[4:4]</bitRange>
9614                <access>read-only</access>
9615              </field>
9616              <field>
9617                <name>BLANK_CHECK_WORK</name>
9618                <description>Indicates if Blank Check mode is currently running on the work flash
96190: not running
96201: running</description>
9621                <bitRange>[5:5]</bitRange>
9622                <access>read-only</access>
9623              </field>
9624              <field>
9625                <name>BLANK_CHCEK_PASS</name>
9626                <description>Indicates  the Blank check command result is PASS (Blank)
96270: Not Blank
96281: Blank (PASS)</description>
9629                <bitRange>[6:6]</bitRange>
9630                <access>read-only</access>
9631              </field>
9632              <field>
9633                <name>POR_1B_ECC_CORRECTED</name>
9634                <description>Indicates internal ECC found 1b error while downloading info in POR from NVM to VM and fixed it.
9635Valid after 2nd, 3rd and 4th POR phases (FUR, IREM &amp; MMR, SW DOWNLOAD). If Set it is not cleaned till additional POR (rst_hf_ac_t)
96360: No error
96371: 1b ECC Error corrected in POR</description>
9638                <bitRange>[27:27]</bitRange>
9639                <access>read-only</access>
9640              </field>
9641              <field>
9642                <name>POR_2B_ECC_ERROR</name>
9643                <description>Indicates an internal ECC error of 2b while downloading info in POR from NVM to VM.
9644Valid after 2nd, 3rd and 4th POR phases (FUR, IREM &amp; MMR, SW DOWNLOAD). If Set it is not cleaned till additional POR (rst_hf_ac_t)
96450: No error
96461: ECC 2b Error in POR</description>
9647                <bitRange>[28:28]</bitRange>
9648                <access>read-only</access>
9649              </field>
9650              <field>
9651                <name>NATIVE_POR</name>
9652                <description>Indicates a Native Flash state (UV) or sorted one.
9653Valid only after 2nd phase of POR (FUR DOWNLOAD).
9654Comment: not a retained flop, therefore reset (rst_hf_act_n) puts it back to 0. If Set it is not cleaned till additional POR (rst_hf_ac_t)
96550: SORTED DEVICE (Non - Native)
96561: NATIVE</description>
9657                <bitRange>[29:29]</bitRange>
9658                <access>read-only</access>
9659              </field>
9660              <field>
9661                <name>HANG</name>
9662                <description>After embedded operation (pgm/erase) this flag will tell if it was successful or failed
96630: PASS
96641: FAIL</description>
9665                <bitRange>[30:30]</bitRange>
9666                <access>read-only</access>
9667              </field>
9668              <field>
9669                <name>BUSY</name>
9670                <description>Whenever the device is in embedded mode the RDY goes low. Should be the same as c_interrupt pin of the IP (but inverted)
96711: busy in embedded
96720: rdy (high also in erase suspend)</description>
9673                <bitRange>[31:31]</bitRange>
9674                <access>read-only</access>
9675              </field>
9676            </fields>
9677          </register>
9678          <register>
9679            <name>WORK_FLASH_SAFETY</name>
9680            <description>Work Flash Security enable</description>
9681            <addressOffset>0x500</addressOffset>
9682            <size>32</size>
9683            <access>read-write</access>
9684            <resetValue>0x0</resetValue>
9685            <resetMask>0x1</resetMask>
9686            <fields>
9687              <field>
9688                <name>WORKFLASHWRITEENABLE</name>
9689                <description>0: Work Flash embedded operations are blocked
96901: Work Flash embedded operations are enabled</description>
9691                <bitRange>[0:0]</bitRange>
9692                <access>read-write</access>
9693              </field>
9694            </fields>
9695          </register>
9696        </cluster>
9697      </registers>
9698    </peripheral>
9699    <peripheral>
9700      <name>SRSS</name>
9701      <description>SRSS Core Registers (ver2)</description>
9702      <baseAddress>0x40260000</baseAddress>
9703      <addressBlock>
9704        <offset>0</offset>
9705        <size>65536</size>
9706        <usage>registers</usage>
9707      </addressBlock>
9708      <registers>
9709        <register>
9710          <name>PWR_LVD_STATUS</name>
9711          <description>High Voltage / Low Voltage Detector (HVLVD) Status Register</description>
9712          <addressOffset>0x40</addressOffset>
9713          <size>32</size>
9714          <access>read-only</access>
9715          <resetValue>0x0</resetValue>
9716          <resetMask>0x1</resetMask>
9717          <fields>
9718            <field>
9719              <name>HVLVD1_OUT</name>
9720              <description>HVLVD1 output.
97210: below voltage threshold
97221: above voltage threshold</description>
9723              <bitRange>[0:0]</bitRange>
9724              <access>read-only</access>
9725            </field>
9726          </fields>
9727        </register>
9728        <register>
9729          <name>PWR_LVD_STATUS2</name>
9730          <description>High Voltage / Low Voltage Detector (HVLVD) Status Register #2</description>
9731          <addressOffset>0x44</addressOffset>
9732          <size>32</size>
9733          <access>read-only</access>
9734          <resetValue>0x0</resetValue>
9735          <resetMask>0x1</resetMask>
9736          <fields>
9737            <field>
9738              <name>HVLVD2_OUT</name>
9739              <description>HVLVD2 output.
97400: below voltage threshold
97411: above voltage threshold</description>
9742              <bitRange>[0:0]</bitRange>
9743              <access>read-only</access>
9744            </field>
9745          </fields>
9746        </register>
9747        <register>
9748          <dim>16</dim>
9749          <dimIncrement>4</dimIncrement>
9750          <name>CLK_DSI_SELECT[%s]</name>
9751          <description>Clock DSI Select Register</description>
9752          <addressOffset>0x100</addressOffset>
9753          <size>32</size>
9754          <access>read-write</access>
9755          <resetValue>0x0</resetValue>
9756          <resetMask>0x1F</resetMask>
9757          <fields>
9758            <field>
9759              <name>DSI_MUX</name>
9760              <description>Selects a DSI source or low frequency clock for use in a clock path.  The output of this mux can be selected for clock PATH&lt;i&gt; using CLK_PATH_SELECT register.  Using the output of this mux as HFCLK source will result in undefined behavior.  It can be used to clocks to DSI or as reference inputs for the FLL/PLL, subject to the frequency limits of those circuits.  This mux is not glitch free, so do not change the selection while it is an actively selected clock.</description>
9761              <bitRange>[4:0]</bitRange>
9762              <access>read-write</access>
9763              <enumeratedValues>
9764                <enumeratedValue>
9765                  <name>DSI_OUT0</name>
9766                  <description>DSI0 - dsi_out[0]</description>
9767                  <value>0</value>
9768                </enumeratedValue>
9769                <enumeratedValue>
9770                  <name>DSI_OUT1</name>
9771                  <description>DSI1 - dsi_out[1]</description>
9772                  <value>1</value>
9773                </enumeratedValue>
9774                <enumeratedValue>
9775                  <name>DSI_OUT2</name>
9776                  <description>DSI2 - dsi_out[2]</description>
9777                  <value>2</value>
9778                </enumeratedValue>
9779                <enumeratedValue>
9780                  <name>DSI_OUT3</name>
9781                  <description>DSI3 - dsi_out[3]</description>
9782                  <value>3</value>
9783                </enumeratedValue>
9784                <enumeratedValue>
9785                  <name>DSI_OUT4</name>
9786                  <description>DSI4 - dsi_out[4]</description>
9787                  <value>4</value>
9788                </enumeratedValue>
9789                <enumeratedValue>
9790                  <name>DSI_OUT5</name>
9791                  <description>DSI5 - dsi_out[5]</description>
9792                  <value>5</value>
9793                </enumeratedValue>
9794                <enumeratedValue>
9795                  <name>DSI_OUT6</name>
9796                  <description>DSI6 - dsi_out[6]</description>
9797                  <value>6</value>
9798                </enumeratedValue>
9799                <enumeratedValue>
9800                  <name>DSI_OUT7</name>
9801                  <description>DSI7 - dsi_out[7]</description>
9802                  <value>7</value>
9803                </enumeratedValue>
9804                <enumeratedValue>
9805                  <name>DSI_OUT8</name>
9806                  <description>DSI8 - dsi_out[8]</description>
9807                  <value>8</value>
9808                </enumeratedValue>
9809                <enumeratedValue>
9810                  <name>DSI_OUT9</name>
9811                  <description>DSI9 - dsi_out[9]</description>
9812                  <value>9</value>
9813                </enumeratedValue>
9814                <enumeratedValue>
9815                  <name>DSI_OUT10</name>
9816                  <description>DSI10 - dsi_out[10]</description>
9817                  <value>10</value>
9818                </enumeratedValue>
9819                <enumeratedValue>
9820                  <name>DSI_OUT11</name>
9821                  <description>DSI11 - dsi_out[11]</description>
9822                  <value>11</value>
9823                </enumeratedValue>
9824                <enumeratedValue>
9825                  <name>DSI_OUT12</name>
9826                  <description>DSI12 - dsi_out[12]</description>
9827                  <value>12</value>
9828                </enumeratedValue>
9829                <enumeratedValue>
9830                  <name>DSI_OUT13</name>
9831                  <description>DSI13 - dsi_out[13]</description>
9832                  <value>13</value>
9833                </enumeratedValue>
9834                <enumeratedValue>
9835                  <name>DSI_OUT14</name>
9836                  <description>DSI14 - dsi_out[14]</description>
9837                  <value>14</value>
9838                </enumeratedValue>
9839                <enumeratedValue>
9840                  <name>DSI_OUT15</name>
9841                  <description>DSI15 - dsi_out[15]</description>
9842                  <value>15</value>
9843                </enumeratedValue>
9844                <enumeratedValue>
9845                  <name>ILO0</name>
9846                  <description>ILO0 - Internal Low-speed Oscillator #0</description>
9847                  <value>16</value>
9848                </enumeratedValue>
9849                <enumeratedValue>
9850                  <name>WCO</name>
9851                  <description>WCO - Watch-Crystal Oscillator</description>
9852                  <value>17</value>
9853                </enumeratedValue>
9854                <enumeratedValue>
9855                  <name>ALTLF</name>
9856                  <description>ALTLF - Alternate Low-Frequency Clock</description>
9857                  <value>18</value>
9858                </enumeratedValue>
9859                <enumeratedValue>
9860                  <name>PILO</name>
9861                  <description>PILO - Precision Internal Low-speed Oscillator</description>
9862                  <value>19</value>
9863                </enumeratedValue>
9864                <enumeratedValue>
9865                  <name>ILO1</name>
9866                  <description>ILO1 - Internal Low-speed Oscillator #1, if present.</description>
9867                  <value>20</value>
9868                </enumeratedValue>
9869              </enumeratedValues>
9870            </field>
9871          </fields>
9872        </register>
9873        <register>
9874          <name>CLK_OUTPUT_FAST</name>
9875          <description>Fast Clock Output Select Register</description>
9876          <addressOffset>0x140</addressOffset>
9877          <size>32</size>
9878          <access>read-write</access>
9879          <resetValue>0x0</resetValue>
9880          <resetMask>0xFFF0FFF</resetMask>
9881          <fields>
9882            <field>
9883              <name>FAST_SEL0</name>
9884              <description>Select signal for fast clock output #0</description>
9885              <bitRange>[3:0]</bitRange>
9886              <access>read-write</access>
9887              <enumeratedValues>
9888                <enumeratedValue>
9889                  <name>NC</name>
9890                  <description>Disabled - output is 0.  For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0.</description>
9891                  <value>0</value>
9892                </enumeratedValue>
9893                <enumeratedValue>
9894                  <name>ECO</name>
9895                  <description>External Crystal Oscillator (ECO)</description>
9896                  <value>1</value>
9897                </enumeratedValue>
9898                <enumeratedValue>
9899                  <name>EXTCLK</name>
9900                  <description>External clock input (EXTCLK)</description>
9901                  <value>2</value>
9902                </enumeratedValue>
9903                <enumeratedValue>
9904                  <name>ALTHF</name>
9905                  <description>Alternate High-Frequency (ALTHF) clock input to SRSS</description>
9906                  <value>3</value>
9907                </enumeratedValue>
9908                <enumeratedValue>
9909                  <name>TIMERCLK</name>
9910                  <description>Timer clock.  It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse.</description>
9911                  <value>4</value>
9912                </enumeratedValue>
9913                <enumeratedValue>
9914                  <name>PATH_SEL0</name>
9915                  <description>Selects the clock path chosen by PATH_SEL0 field</description>
9916                  <value>5</value>
9917                </enumeratedValue>
9918                <enumeratedValue>
9919                  <name>HFCLK_SEL0</name>
9920                  <description>Selects the output of the HFCLK_SEL0 mux</description>
9921                  <value>6</value>
9922                </enumeratedValue>
9923                <enumeratedValue>
9924                  <name>SLOW_SEL0</name>
9925                  <description>Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0</description>
9926                  <value>7</value>
9927                </enumeratedValue>
9928              </enumeratedValues>
9929            </field>
9930            <field>
9931              <name>PATH_SEL0</name>
9932              <description>Selects a clock path to use in fast clock output #0 logic.
99330: FLL output
99341-15: PLL output on path1-path15 (if available)</description>
9935              <bitRange>[7:4]</bitRange>
9936              <access>read-write</access>
9937            </field>
9938            <field>
9939              <name>HFCLK_SEL0</name>
9940              <description>Selects a HFCLK tree for use in fast clock output #0</description>
9941              <bitRange>[11:8]</bitRange>
9942              <access>read-write</access>
9943            </field>
9944            <field>
9945              <name>FAST_SEL1</name>
9946              <description>Select signal for fast clock output #1</description>
9947              <bitRange>[19:16]</bitRange>
9948              <access>read-write</access>
9949              <enumeratedValues>
9950                <enumeratedValue>
9951                  <name>NC</name>
9952                  <description>Disabled - output is 0.  For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1.</description>
9953                  <value>0</value>
9954                </enumeratedValue>
9955                <enumeratedValue>
9956                  <name>ECO</name>
9957                  <description>External Crystal Oscillator (ECO)</description>
9958                  <value>1</value>
9959                </enumeratedValue>
9960                <enumeratedValue>
9961                  <name>EXTCLK</name>
9962                  <description>External clock input (EXTCLK)</description>
9963                  <value>2</value>
9964                </enumeratedValue>
9965                <enumeratedValue>
9966                  <name>ALTHF</name>
9967                  <description>Alternate High-Frequency (ALTHF) clock input to SRSS</description>
9968                  <value>3</value>
9969                </enumeratedValue>
9970                <enumeratedValue>
9971                  <name>TIMERCLK</name>
9972                  <description>Timer clock.  It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse.</description>
9973                  <value>4</value>
9974                </enumeratedValue>
9975                <enumeratedValue>
9976                  <name>PATH_SEL1</name>
9977                  <description>Selects the clock path chosen by PATH_SEL1 field</description>
9978                  <value>5</value>
9979                </enumeratedValue>
9980                <enumeratedValue>
9981                  <name>HFCLK_SEL1</name>
9982                  <description>Selects the output of the HFCLK_SEL1 mux</description>
9983                  <value>6</value>
9984                </enumeratedValue>
9985                <enumeratedValue>
9986                  <name>SLOW_SEL1</name>
9987                  <description>Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1</description>
9988                  <value>7</value>
9989                </enumeratedValue>
9990              </enumeratedValues>
9991            </field>
9992            <field>
9993              <name>PATH_SEL1</name>
9994              <description>Selects a clock path to use in fast clock output #1 logic.
99950: FLL output
99961-15: PLL output on path1-path15 (if available)</description>
9997              <bitRange>[23:20]</bitRange>
9998              <access>read-write</access>
9999            </field>
10000            <field>
10001              <name>HFCLK_SEL1</name>
10002              <description>Selects a HFCLK tree for use in fast clock output #1 logic</description>
10003              <bitRange>[27:24]</bitRange>
10004              <access>read-write</access>
10005            </field>
10006          </fields>
10007        </register>
10008        <register>
10009          <name>CLK_OUTPUT_SLOW</name>
10010          <description>Slow Clock Output Select Register</description>
10011          <addressOffset>0x144</addressOffset>
10012          <size>32</size>
10013          <access>read-write</access>
10014          <resetValue>0x0</resetValue>
10015          <resetMask>0xFF</resetMask>
10016          <fields>
10017            <field>
10018              <name>SLOW_SEL0</name>
10019              <description>Select signal for slow clock output #0</description>
10020              <bitRange>[3:0]</bitRange>
10021              <access>read-write</access>
10022              <enumeratedValues>
10023                <enumeratedValue>
10024                  <name>NC</name>
10025                  <description>Disabled - output is 0.  For power savings, clocks are blocked before entering any muxes.</description>
10026                  <value>0</value>
10027                </enumeratedValue>
10028                <enumeratedValue>
10029                  <name>ILO0</name>
10030                  <description>Internal Low Speed Oscillator (ILO0)</description>
10031                  <value>1</value>
10032                </enumeratedValue>
10033                <enumeratedValue>
10034                  <name>WCO</name>
10035                  <description>Watch-Crystal Oscillator (WCO)</description>
10036                  <value>2</value>
10037                </enumeratedValue>
10038                <enumeratedValue>
10039                  <name>BAK</name>
10040                  <description>Root of the Backup domain clock tree (BAK)</description>
10041                  <value>3</value>
10042                </enumeratedValue>
10043                <enumeratedValue>
10044                  <name>ALTLF</name>
10045                  <description>Alternate low-frequency clock input to SRSS (ALTLF)</description>
10046                  <value>4</value>
10047                </enumeratedValue>
10048                <enumeratedValue>
10049                  <name>LFCLK</name>
10050                  <description>Root of the low-speed clock tree (LFCLK)</description>
10051                  <value>5</value>
10052                </enumeratedValue>
10053                <enumeratedValue>
10054                  <name>IMO</name>
10055                  <description>Internal Main Oscillator (IMO).  This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
10056                  <value>6</value>
10057                </enumeratedValue>
10058                <enumeratedValue>
10059                  <name>SLPCTRL</name>
10060                  <description>Sleep Controller clock (SLPCTRL).  This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
10061                  <value>7</value>
10062                </enumeratedValue>
10063                <enumeratedValue>
10064                  <name>PILO</name>
10065                  <description>Precision Internal Low Speed Oscillator (PILO)</description>
10066                  <value>8</value>
10067                </enumeratedValue>
10068                <enumeratedValue>
10069                  <name>ILO1</name>
10070                  <description>Internal Low Speed Oscillator (ILO1), if present on the product.</description>
10071                  <value>9</value>
10072                </enumeratedValue>
10073                <enumeratedValue>
10074                  <name>ECO_PRESCALER</name>
10075                  <description>ECO Prescaler (ECO_PRESCALER)</description>
10076                  <value>10</value>
10077                </enumeratedValue>
10078              </enumeratedValues>
10079            </field>
10080            <field>
10081              <name>SLOW_SEL1</name>
10082              <description>Select signal for slow clock output #1</description>
10083              <bitRange>[7:4]</bitRange>
10084              <access>read-write</access>
10085              <enumeratedValues>
10086                <enumeratedValue>
10087                  <name>NC</name>
10088                  <description>Disabled - output is 0.  For power savings, clocks are blocked before entering any muxes.</description>
10089                  <value>0</value>
10090                </enumeratedValue>
10091                <enumeratedValue>
10092                  <name>ILO0</name>
10093                  <description>Internal Low Speed Oscillator (ILO)</description>
10094                  <value>1</value>
10095                </enumeratedValue>
10096                <enumeratedValue>
10097                  <name>WCO</name>
10098                  <description>Watch-Crystal Oscillator (WCO)</description>
10099                  <value>2</value>
10100                </enumeratedValue>
10101                <enumeratedValue>
10102                  <name>BAK</name>
10103                  <description>Root of the Backup domain clock tree (BAK)</description>
10104                  <value>3</value>
10105                </enumeratedValue>
10106                <enumeratedValue>
10107                  <name>ALTLF</name>
10108                  <description>Alternate low-frequency clock input to SRSS (ALTLF)</description>
10109                  <value>4</value>
10110                </enumeratedValue>
10111                <enumeratedValue>
10112                  <name>LFCLK</name>
10113                  <description>Root of the low-speed clock tree (LFCLK)</description>
10114                  <value>5</value>
10115                </enumeratedValue>
10116                <enumeratedValue>
10117                  <name>IMO</name>
10118                  <description>Internal Main Oscillator (IMO).  This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
10119                  <value>6</value>
10120                </enumeratedValue>
10121                <enumeratedValue>
10122                  <name>SLPCTRL</name>
10123                  <description>Sleep Controller clock (SLPCTRL).  This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
10124                  <value>7</value>
10125                </enumeratedValue>
10126                <enumeratedValue>
10127                  <name>PILO</name>
10128                  <description>Precision Internal Low Speed Oscillator (PILO)</description>
10129                  <value>8</value>
10130                </enumeratedValue>
10131                <enumeratedValue>
10132                  <name>ILO1</name>
10133                  <description>Internal Low Speed Oscillator (ILO1), if present on the product.</description>
10134                  <value>9</value>
10135                </enumeratedValue>
10136                <enumeratedValue>
10137                  <name>ECO_PRESCALER</name>
10138                  <description>ECO Prescaler (ECO_PRESCALER)</description>
10139                  <value>10</value>
10140                </enumeratedValue>
10141              </enumeratedValues>
10142            </field>
10143          </fields>
10144        </register>
10145        <register>
10146          <name>CLK_CAL_CNT1</name>
10147          <description>Clock Calibration Counter 1</description>
10148          <addressOffset>0x148</addressOffset>
10149          <size>32</size>
10150          <access>read-write</access>
10151          <resetValue>0x80000000</resetValue>
10152          <resetMask>0x80FFFFFF</resetMask>
10153          <fields>
10154            <field>
10155              <name>CAL_COUNTER1</name>
10156              <description>Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero.  Counting starts internally when this register is written with a nonzero value.  CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done.  Do not write this field unless CAL_COUNTER_DONE==1.  Both clocks must be running or the measurement will not complete.  A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result.</description>
10157              <bitRange>[23:0]</bitRange>
10158              <access>read-write</access>
10159            </field>
10160            <field>
10161              <name>CAL_COUNTER_DONE</name>
10162              <description>Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up</description>
10163              <bitRange>[31:31]</bitRange>
10164              <access>read-only</access>
10165            </field>
10166          </fields>
10167        </register>
10168        <register>
10169          <name>CLK_CAL_CNT2</name>
10170          <description>Clock Calibration Counter 2</description>
10171          <addressOffset>0x14C</addressOffset>
10172          <size>32</size>
10173          <access>read-only</access>
10174          <resetValue>0x0</resetValue>
10175          <resetMask>0xFFFFFF</resetMask>
10176          <fields>
10177            <field>
10178              <name>CAL_COUNTER2</name>
10179              <description>Up-counter clocked on fast clock output  #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW.  Do not read this value unless CAL_COUNTER_DONE==1.  The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER)</description>
10180              <bitRange>[23:0]</bitRange>
10181              <access>read-only</access>
10182            </field>
10183          </fields>
10184        </register>
10185        <register>
10186          <name>SRSS_INTR</name>
10187          <description>SRSS Interrupt Register</description>
10188          <addressOffset>0x200</addressOffset>
10189          <size>32</size>
10190          <access>read-write</access>
10191          <resetValue>0x0</resetValue>
10192          <resetMask>0x26</resetMask>
10193          <fields>
10194            <field>
10195              <name>HVLVD1</name>
10196              <description>Interrupt for low voltage detector HVLVD1</description>
10197              <bitRange>[1:1]</bitRange>
10198              <access>read-write</access>
10199            </field>
10200            <field>
10201              <name>HVLVD2</name>
10202              <description>Interrupt for low voltage detector HVLVD2</description>
10203              <bitRange>[2:2]</bitRange>
10204              <access>read-write</access>
10205            </field>
10206            <field>
10207              <name>CLK_CAL</name>
10208              <description>Clock calibration counter is done.  This field is reset during DEEPSLEEP mode.</description>
10209              <bitRange>[5:5]</bitRange>
10210              <access>read-write</access>
10211            </field>
10212          </fields>
10213        </register>
10214        <register>
10215          <name>SRSS_INTR_SET</name>
10216          <description>SRSS Interrupt Set Register</description>
10217          <addressOffset>0x204</addressOffset>
10218          <size>32</size>
10219          <access>read-write</access>
10220          <resetValue>0x0</resetValue>
10221          <resetMask>0x26</resetMask>
10222          <fields>
10223            <field>
10224              <name>HVLVD1</name>
10225              <description>Set interrupt for low voltage detector HVLVD1</description>
10226              <bitRange>[1:1]</bitRange>
10227              <access>read-write</access>
10228            </field>
10229            <field>
10230              <name>HVLVD2</name>
10231              <description>Set interrupt for low voltage detector HVLVD2</description>
10232              <bitRange>[2:2]</bitRange>
10233              <access>read-write</access>
10234            </field>
10235            <field>
10236              <name>CLK_CAL</name>
10237              <description>Set interrupt for clock calibration counter done.  This field is reset during DEEPSLEEP mode.</description>
10238              <bitRange>[5:5]</bitRange>
10239              <access>read-write</access>
10240            </field>
10241          </fields>
10242        </register>
10243        <register>
10244          <name>SRSS_INTR_MASK</name>
10245          <description>SRSS Interrupt Mask Register</description>
10246          <addressOffset>0x208</addressOffset>
10247          <size>32</size>
10248          <access>read-write</access>
10249          <resetValue>0x0</resetValue>
10250          <resetMask>0x26</resetMask>
10251          <fields>
10252            <field>
10253              <name>HVLVD1</name>
10254              <description>Mask for low voltage detector HVLVD1</description>
10255              <bitRange>[1:1]</bitRange>
10256              <access>read-write</access>
10257            </field>
10258            <field>
10259              <name>HVLVD2</name>
10260              <description>Mask for low voltage detector HVLVD2</description>
10261              <bitRange>[2:2]</bitRange>
10262              <access>read-write</access>
10263            </field>
10264            <field>
10265              <name>CLK_CAL</name>
10266              <description>Mask for clock calibration done</description>
10267              <bitRange>[5:5]</bitRange>
10268              <access>read-write</access>
10269            </field>
10270          </fields>
10271        </register>
10272        <register>
10273          <name>SRSS_INTR_MASKED</name>
10274          <description>SRSS Interrupt Masked Register</description>
10275          <addressOffset>0x20C</addressOffset>
10276          <size>32</size>
10277          <access>read-only</access>
10278          <resetValue>0x0</resetValue>
10279          <resetMask>0x26</resetMask>
10280          <fields>
10281            <field>
10282              <name>HVLVD1</name>
10283              <description>Logical and of corresponding request and mask bits.</description>
10284              <bitRange>[1:1]</bitRange>
10285              <access>read-only</access>
10286            </field>
10287            <field>
10288              <name>HVLVD2</name>
10289              <description>Logical and of corresponding request and mask bits.</description>
10290              <bitRange>[2:2]</bitRange>
10291              <access>read-only</access>
10292            </field>
10293            <field>
10294              <name>CLK_CAL</name>
10295              <description>Logical and of corresponding request and mask bits.</description>
10296              <bitRange>[5:5]</bitRange>
10297              <access>read-only</access>
10298            </field>
10299          </fields>
10300        </register>
10301        <register>
10302          <name>PWR_CTL</name>
10303          <description>Power Mode Control</description>
10304          <addressOffset>0x1000</addressOffset>
10305          <size>32</size>
10306          <access>read-only</access>
10307          <resetValue>0x0</resetValue>
10308          <resetMask>0x33</resetMask>
10309          <fields>
10310            <field>
10311              <name>POWER_MODE</name>
10312              <description>Current power mode of the device.  Note that this field cannot be read in all power modes on actual silicon.</description>
10313              <bitRange>[1:0]</bitRange>
10314              <access>read-only</access>
10315              <enumeratedValues>
10316                <enumeratedValue>
10317                  <name>RESET</name>
10318                  <description>System is resetting.</description>
10319                  <value>0</value>
10320                </enumeratedValue>
10321                <enumeratedValue>
10322                  <name>ACTIVE</name>
10323                  <description>At least one CPU is running.</description>
10324                  <value>1</value>
10325                </enumeratedValue>
10326                <enumeratedValue>
10327                  <name>SLEEP</name>
10328                  <description>No CPUs are running.  Peripherals may be running.</description>
10329                  <value>2</value>
10330                </enumeratedValue>
10331                <enumeratedValue>
10332                  <name>DEEPSLEEP</name>
10333                  <description>Main high-frequency clock is off; low speed clocks are available.  Communication interface clocks may be present.</description>
10334                  <value>3</value>
10335                </enumeratedValue>
10336              </enumeratedValues>
10337            </field>
10338            <field>
10339              <name>DEBUG_SESSION</name>
10340              <description>Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)</description>
10341              <bitRange>[4:4]</bitRange>
10342              <access>read-only</access>
10343              <enumeratedValues>
10344                <enumeratedValue>
10345                  <name>NO_SESSION</name>
10346                  <description>No debug session active</description>
10347                  <value>0</value>
10348                </enumeratedValue>
10349                <enumeratedValue>
10350                  <name>SESSION_ACTIVE</name>
10351                  <description>Debug session is active.  Power modes behave differently to keep the debug session active.</description>
10352                  <value>1</value>
10353                </enumeratedValue>
10354              </enumeratedValues>
10355            </field>
10356            <field>
10357              <name>LPM_READY</name>
10358              <description>Indicates whether certain low power functions are ready.  The low current circuits take longer to startup after XRES, HIBERNATE wakeup, or supply supervision reset than the normal mode circuits.  HIBERNATE mode may be entered regardless of this bit.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.
103590: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready.  If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP.  When low power circuits are ready, device will automatically enter the originally requested mode.
103601: Normal operation.  DEEPSLEEP and low power circuits operate as requested in other registers.</description>
10361              <bitRange>[5:5]</bitRange>
10362              <access>read-only</access>
10363            </field>
10364          </fields>
10365        </register>
10366        <register>
10367          <name>PWR_CTL2</name>
10368          <description>Power Mode Control 2</description>
10369          <addressOffset>0x1004</addressOffset>
10370          <size>32</size>
10371          <access>read-write</access>
10372          <resetValue>0x0</resetValue>
10373          <resetMask>0x9F731117</resetMask>
10374          <fields>
10375            <field>
10376              <name>LINREG_DIS</name>
10377              <description>Explicitly disable the linear Core Regulator.  Write zero for Traveo II devices.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.
103780: Linear Core Regulator is not explicitly disabled.  Hardware disables it automatically for internal sequences, including for DEEPSLEEP, HIBERNATE, and XRES low power modes.
103791: Linear Core Regulator is explicitly disabled.  Only use this for special cases when another source supplies vccd during ACTIVE and SLEEP modes.  This setting is only legal when another source supplies vccd, but there is no special hardware protection for this case.</description>
10380              <bitRange>[0:0]</bitRange>
10381              <access>read-write</access>
10382            </field>
10383            <field>
10384              <name>LINREG_OK</name>
10385              <description>Status of the linear Core Regulator.</description>
10386              <bitRange>[1:1]</bitRange>
10387              <access>read-only</access>
10388            </field>
10389            <field>
10390              <name>LINREG_LPMODE</name>
10391              <description>Control the power mode of the Linear Regulator.  The value in this register is ignored and normal mode is used until LPM_READY==1.
103920: Linear Regulator operates in normal mode.  Internal current consumption is 50uA and load current capability is 50mA to 300mA, depending on the number of regulator modules present in the product.
103931: Linear Regulator operates in low power mode.  Internal current consumption is 5uA and load current capability is 25mA.  Firmware must ensure the current is kept within the limit.</description>
10394              <bitRange>[2:2]</bitRange>
10395              <access>read-write</access>
10396            </field>
10397            <field>
10398              <name>DPSLP_REG_DIS</name>
10399              <description>N/A</description>
10400              <bitRange>[4:4]</bitRange>
10401              <access>read-write</access>
10402            </field>
10403            <field>
10404              <name>RET_REG_DIS</name>
10405              <description>Disable the Retention regulator.  This is only legal when another source supplies vccret, but there is no special hardware protection for this case.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.
104060: Retention Regulator is on.
104071: Retention Regulator is off.</description>
10408              <bitRange>[8:8]</bitRange>
10409              <access>read-write</access>
10410            </field>
10411            <field>
10412              <name>NWELL_REG_DIS</name>
10413              <description>Disable the Nwell regulator.  This is only legal when another source supplies vnwell, but there is no special hardware protection for this case.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.
104140: Nwell Regulator is on.
104151: Nwell Regulator is off.</description>
10416              <bitRange>[12:12]</bitRange>
10417              <access>read-write</access>
10418            </field>
10419            <field>
10420              <name>REFV_DIS</name>
10421              <description>N/A</description>
10422              <bitRange>[16:16]</bitRange>
10423              <access>read-write</access>
10424            </field>
10425            <field>
10426              <name>REFV_OK</name>
10427              <description>Indicates that the normal mode of the voltage reference is ready.</description>
10428              <bitRange>[17:17]</bitRange>
10429              <access>read-only</access>
10430            </field>
10431            <field>
10432              <name>REFVBUF_DIS</name>
10433              <description>Disable the voltage reference buffer.  Firmware should only disable the buffer when there is no connected circuit that is using it.  SRSS circuits that require it are the PLL and ECO.  A particular product may have circuits outside the SRSS that use the buffer.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.</description>
10434              <bitRange>[20:20]</bitRange>
10435              <access>read-write</access>
10436            </field>
10437            <field>
10438              <name>REFVBUF_OK</name>
10439              <description>Indicates that the voltage reference buffer is ready.  Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting REFVBUF_DIS=1.</description>
10440              <bitRange>[21:21]</bitRange>
10441              <access>read-only</access>
10442            </field>
10443            <field>
10444              <name>REFVBUF_LPMODE</name>
10445              <description>Control the power mode of the 800mV voltage reference buffer.  The value in this register is ignored and normal mode is used until LPM_READY==1.
104460: Voltage Reference Buffer operates in normal mode.  They work for vddd ramp rates of 100mV/us or less.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.
104471: Voltage Reference Buffer operates in low power mode.  Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less.</description>
10448              <bitRange>[22:22]</bitRange>
10449              <access>read-write</access>
10450            </field>
10451            <field>
10452              <name>REFI_DIS</name>
10453              <description>N/A</description>
10454              <bitRange>[24:24]</bitRange>
10455              <access>read-write</access>
10456            </field>
10457            <field>
10458              <name>REFI_OK</name>
10459              <description>Indicates that the current reference is ready.  Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting REFI_DIS=1.</description>
10460              <bitRange>[25:25]</bitRange>
10461              <access>read-only</access>
10462            </field>
10463            <field>
10464              <name>REFI_LPMODE</name>
10465              <description>Control the power mode of the reference current generator.  The value in this register is ignored and normal mode is used until LPM_READY==1.
104660: Current reference generator operates in normal mode.  It works for vddd ramp rates of 100mV/us or less.
104671: Current reference generator operates in low power mode.  Response time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less.</description>
10468              <bitRange>[26:26]</bitRange>
10469              <access>read-write</access>
10470            </field>
10471            <field>
10472              <name>PORBOD_LPMODE</name>
10473              <description>Control the power mode of the POR/BOD circuits.  The value in this register is ignored and normal mode is used until LPM_READY==1.
104740: POR/BOD circuits operate in normal mode.  They work for vddd ramp rates of 100mV/us or less.
104751: POR/BOD circuits operate in low power mode.  Response time is reduced to save current, and they work for vddd ramp rates of 10mV/us or less.</description>
10476              <bitRange>[27:27]</bitRange>
10477              <access>read-write</access>
10478            </field>
10479            <field>
10480              <name>BGREF_LPMODE</name>
10481              <description>Current is reduced using a sample&amp;hold feature.  This requires ILO0 to be operating properly.  This register will not set unless CLK_ILO0_CONFIG.ILO0_ENABLE==1.  When changing back to continuous operation, keep ILO0 enabled for at least 5 cycles after clearing this bit to allow for internal synchronization.
10482
104830: Bandgap Reference circuits operate in higher current mode.
104841: Bandgap Reference circuits operate in low power (see above for tradeoffs).</description>
10485              <bitRange>[28:28]</bitRange>
10486              <access>read-write</access>
10487            </field>
10488            <field>
10489              <name>PLL_LS_BYPASS</name>
10490              <description>Bypass level shifter inside the PLL.  Unused, if no PLL is present in the product.
104910: Do not bypass the level shifter.  This setting is ok for all operational modes and vccd target voltage.
104921: Bypass the level shifter.  This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal.  Otherwise, it can result in clock degradation and static current.</description>
10493              <bitRange>[31:31]</bitRange>
10494              <access>read-write</access>
10495            </field>
10496          </fields>
10497        </register>
10498        <register>
10499          <name>PWR_HIBERNATE</name>
10500          <description>HIBERNATE Mode Register</description>
10501          <addressOffset>0x1008</addressOffset>
10502          <size>32</size>
10503          <access>read-write</access>
10504          <resetValue>0x0</resetValue>
10505          <resetMask>0xCFFEFFFF</resetMask>
10506          <fields>
10507            <field>
10508              <name>TOKEN</name>
10509              <description>Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event.  Note that waking up from HIBERNATE using XRES will reset this register.</description>
10510              <bitRange>[7:0]</bitRange>
10511              <access>read-write</access>
10512            </field>
10513            <field>
10514              <name>UNLOCK</name>
10515              <description>This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate.  Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description.</description>
10516              <bitRange>[15:8]</bitRange>
10517              <access>read-write</access>
10518            </field>
10519            <field>
10520              <name>FREEZE</name>
10521              <description>Firmware sets this bit to freeze the configuration, mode and state of all GPIOs and SIOs in the system.  When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command.  This occurs even in the illegal condition where UNLOCK is not set.  If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write.  Supply supervision is disabled during HIBERNATE mode.  HIBERNATE peripherals ignore resets (excluding XRES) while FREEZE==1.</description>
10522              <bitRange>[17:17]</bitRange>
10523              <access>read-write</access>
10524            </field>
10525            <field>
10526              <name>MASK_HIBALARM</name>
10527              <description>When set, HIBERNATE will wakeup for a RTC interrupt</description>
10528              <bitRange>[18:18]</bitRange>
10529              <access>read-write</access>
10530            </field>
10531            <field>
10532              <name>MASK_HIBWDT</name>
10533              <description>When set, HIBERNATE will wakeup for WDT interrupt</description>
10534              <bitRange>[19:19]</bitRange>
10535              <access>read-write</access>
10536            </field>
10537            <field>
10538              <name>POLARITY_HIBPIN</name>
10539              <description>Each bit sets the active polarity of the corresponding wakeup pin.
105400: Pin input of 0 will wakeup the part from HIBERNATE
105411: Pin input of 1 will wakeup the part from HIBERNATE</description>
10542              <bitRange>[23:20]</bitRange>
10543              <access>read-write</access>
10544            </field>
10545            <field>
10546              <name>MASK_HIBPIN</name>
10547              <description>When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting.  Each bit corresponds to one of the wakeup pins.</description>
10548              <bitRange>[27:24]</bitRange>
10549              <access>read-write</access>
10550            </field>
10551            <field>
10552              <name>HIBERNATE_DISABLE</name>
10553              <description>Hibernate disable bit.
105540: Normal operation, HIBERNATE works as described
105551: Further writes to this register are ignored
10556Note: This bit is a write-once bit until the next reset.  Avoid changing any other bits in this register while disabling HIBERNATE mode.  Also, it is recommended to clear the UNLOCK code, if it was previously written..</description>
10557              <bitRange>[30:30]</bitRange>
10558              <access>read-write</access>
10559            </field>
10560            <field>
10561              <name>HIBERNATE</name>
10562              <description>Firmware sets this bit to enter HIBERNATE mode.  The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event.  Both UNLOCK and FREEZE must have been set correctly in a previous write operations.  Otherwise, it will not enter HIBERNATE.  External supplies must have been stable for 250us before entering HIBERNATE mode.</description>
10563              <bitRange>[31:31]</bitRange>
10564              <access>read-write</access>
10565            </field>
10566          </fields>
10567        </register>
10568        <register>
10569          <name>PWR_BUCK_CTL</name>
10570          <description>SIMO Buck Control Register</description>
10571          <addressOffset>0x1010</addressOffset>
10572          <size>32</size>
10573          <access>read-write</access>
10574          <resetValue>0x5</resetValue>
10575          <resetMask>0xC0000007</resetMask>
10576          <fields>
10577            <field>
10578              <name>BUCK_OUT1_SEL</name>
10579              <description>Voltage output selection for vccbuck1 output.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.  When increasing the voltage, it can take up to 200us for the output voltage to settle.  When decreasing the voltage, the settling time depends on the load current.
105800: 0.85V
105811: 0.875V
105822: 0.90V
105833: 0.95V
105844: 1.05V
105855: 1.10V
105866: 1.15V
105877: 1.20V</description>
10588              <bitRange>[2:0]</bitRange>
10589              <access>read-write</access>
10590            </field>
10591            <field>
10592              <name>BUCK_EN</name>
10593              <description>Master enable for buck converter.    This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.</description>
10594              <bitRange>[30:30]</bitRange>
10595              <access>read-write</access>
10596            </field>
10597            <field>
10598              <name>BUCK_OUT1_EN</name>
10599              <description>Enable for vccbuck1 output.  The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1.    This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.  The regulator takes up to 600us to charge the external capacitor.  If there is additional load current while charging, this will increase the startup time.  The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1.</description>
10600              <bitRange>[31:31]</bitRange>
10601              <access>read-write</access>
10602            </field>
10603          </fields>
10604        </register>
10605        <register>
10606          <name>PWR_BUCK_CTL2</name>
10607          <description>SIMO Buck Control Register 2</description>
10608          <addressOffset>0x1014</addressOffset>
10609          <size>32</size>
10610          <access>read-write</access>
10611          <resetValue>0x0</resetValue>
10612          <resetMask>0xC0000007</resetMask>
10613          <fields>
10614            <field>
10615              <name>BUCK_OUT2_SEL</name>
10616              <description>Voltage output selection for vccbuck2 output.  When increasing the voltage, it can take up to 200us for the output voltage to settle.  When decreasing the voltage, the settling time depends on the load current.
106170: 1.15V
106181: 1.20V
106192: 1.25V
106203: 1.30V
106214: 1.35V
106225: 1.40V
106236: 1.45V
106247: 1.50V</description>
10625              <bitRange>[2:0]</bitRange>
10626              <access>read-write</access>
10627            </field>
10628            <field>
10629              <name>BUCK_OUT2_HW_SEL</name>
10630              <description>Hardware control for vccbuck2 output.  When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead.  If the product has supporting hardware, it can directly control the enable signal for vccbuck2.  The same charging time in BUCK_OUT2_EN applies.</description>
10631              <bitRange>[30:30]</bitRange>
10632              <access>read-write</access>
10633            </field>
10634            <field>
10635              <name>BUCK_OUT2_EN</name>
10636              <description>Enable for vccbuck2 output.  The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1.  The regulator takes up to 600us to charge the external capacitor.  If there is additional load current while charging, this will increase the startup time.</description>
10637              <bitRange>[31:31]</bitRange>
10638              <access>read-write</access>
10639            </field>
10640          </fields>
10641        </register>
10642        <register>
10643          <name>PWR_SSV_CTL</name>
10644          <description>Supply Supervision Control Register</description>
10645          <addressOffset>0x1018</addressOffset>
10646          <size>32</size>
10647          <access>read-write</access>
10648          <resetValue>0x8080808</resetValue>
10649          <resetMask>0x9D909D9</resetMask>
10650          <fields>
10651            <field>
10652              <name>BODVDDD_VSEL</name>
10653              <description>Selects the voltage threshold for BOD on vddd.  The BOD does not reliably monitor the supply during the transition.
106540: vddd&lt;2.7V
106551: vddd&lt;3.0V</description>
10656              <bitRange>[0:0]</bitRange>
10657              <access>read-write</access>
10658            </field>
10659            <field>
10660              <name>BODVDDD_ENABLE</name>
10661              <description>Enable for BOD on vddd.  This cannot be disabled during normal operation.</description>
10662              <bitRange>[3:3]</bitRange>
10663              <access>read-write</access>
10664            </field>
10665            <field>
10666              <name>BODVDDA_VSEL</name>
10667              <description>Selects the voltage threshold for BOD on vdda.  Ensure BODVDDA_ENABLE==0 before changing this setting to prevent false triggers.
106680: vdda&lt;2.7V
106691: vdda&lt;3.0V</description>
10670              <bitRange>[4:4]</bitRange>
10671              <access>read-write</access>
10672            </field>
10673            <field>
10674              <name>BODVDDA_ACTION</name>
10675              <description>Action taken when the BOD on vdda triggers.</description>
10676              <bitRange>[7:6]</bitRange>
10677              <access>read-write</access>
10678              <enumeratedValues>
10679                <enumeratedValue>
10680                  <name>NOTHING</name>
10681                  <description>No action</description>
10682                  <value>0</value>
10683                </enumeratedValue>
10684                <enumeratedValue>
10685                  <name>FAULT</name>
10686                  <description>Generate a fault</description>
10687                  <value>1</value>
10688                </enumeratedValue>
10689                <enumeratedValue>
10690                  <name>RESET</name>
10691                  <description>Reset the chip</description>
10692                  <value>2</value>
10693                </enumeratedValue>
10694              </enumeratedValues>
10695            </field>
10696            <field>
10697              <name>BODVDDA_ENABLE</name>
10698              <description>Enable for BOD on vdda.  BODVDDA_ACTION will be triggered when the BOD is disabled.  If no action is desired when disabling, firmware must first write BODVDDA_ACTION=NOTHING in a separate write cycle.</description>
10699              <bitRange>[8:8]</bitRange>
10700              <access>read-write</access>
10701            </field>
10702            <field>
10703              <name>BODVCCD_ENABLE</name>
10704              <description>Enable for BOD on vccd.  This cannot be disabled during normal operation.</description>
10705              <bitRange>[11:11]</bitRange>
10706              <access>read-write</access>
10707            </field>
10708            <field>
10709              <name>OVDVDDD_VSEL</name>
10710              <description>Selects the voltage threshold for OVD on vddd.  The OVD does not reliably monitor the supply during the transition.
107110: vddd&gt;5.5V
107121: vddd&gt;5.0V</description>
10713              <bitRange>[16:16]</bitRange>
10714              <access>read-write</access>
10715            </field>
10716            <field>
10717              <name>OVDVDDD_ENABLE</name>
10718              <description>Enable for OVD on vddd.  This cannot be disabled during normal operation.</description>
10719              <bitRange>[19:19]</bitRange>
10720              <access>read-write</access>
10721            </field>
10722            <field>
10723              <name>OVDVDDA_VSEL</name>
10724              <description>Selects the voltage threshold for OVD on vdda.  Ensure OVDVDDA_ENABLE==0 before changing this setting to prevent false triggers
107250: vddd&gt;5.5V
107261: vddd&gt;5.0V</description>
10727              <bitRange>[20:20]</bitRange>
10728              <access>read-write</access>
10729            </field>
10730            <field>
10731              <name>OVDVDDA_ACTION</name>
10732              <description>Action taken when the OVD on vdda triggers.</description>
10733              <bitRange>[23:22]</bitRange>
10734              <access>read-write</access>
10735              <enumeratedValues>
10736                <enumeratedValue>
10737                  <name>NOTHING</name>
10738                  <description>No action</description>
10739                  <value>0</value>
10740                </enumeratedValue>
10741                <enumeratedValue>
10742                  <name>FAULT</name>
10743                  <description>Generate a fault</description>
10744                  <value>1</value>
10745                </enumeratedValue>
10746                <enumeratedValue>
10747                  <name>RESET</name>
10748                  <description>Reset the chip</description>
10749                  <value>2</value>
10750                </enumeratedValue>
10751              </enumeratedValues>
10752            </field>
10753            <field>
10754              <name>OVDVDDA_ENABLE</name>
10755              <description>Enable for OVD on vdda.</description>
10756              <bitRange>[24:24]</bitRange>
10757              <access>read-write</access>
10758            </field>
10759            <field>
10760              <name>OVDVCCD_ENABLE</name>
10761              <description>Enable for OVD on vccd.  This cannot be disabled during normal operation.</description>
10762              <bitRange>[27:27]</bitRange>
10763              <access>read-write</access>
10764            </field>
10765          </fields>
10766        </register>
10767        <register>
10768          <name>PWR_SSV_STATUS</name>
10769          <description>Supply Supervision Status Register</description>
10770          <addressOffset>0x101C</addressOffset>
10771          <size>32</size>
10772          <access>read-only</access>
10773          <resetValue>0x30505</resetValue>
10774          <resetMask>0x30707</resetMask>
10775          <fields>
10776            <field>
10777              <name>BODVDDD_OK</name>
10778              <description>BOD indicates vddd is ok.  This will always read 1, because a detected brownout will reset the chip.</description>
10779              <bitRange>[0:0]</bitRange>
10780              <access>read-only</access>
10781            </field>
10782            <field>
10783              <name>BODVDDA_OK</name>
10784              <description>BOD indicates vdda is ok.</description>
10785              <bitRange>[1:1]</bitRange>
10786              <access>read-only</access>
10787            </field>
10788            <field>
10789              <name>BODVCCD_OK</name>
10790              <description>BOD indicates vccd is ok.  This will always read 1, because a detected brownout will reset the chip.</description>
10791              <bitRange>[2:2]</bitRange>
10792              <access>read-only</access>
10793            </field>
10794            <field>
10795              <name>OVDVDDD_OK</name>
10796              <description>OVD indicates vddd is ok.  This will always read 1, because a detected over-voltage condition will reset the chip.</description>
10797              <bitRange>[8:8]</bitRange>
10798              <access>read-only</access>
10799            </field>
10800            <field>
10801              <name>OVDVDDA_OK</name>
10802              <description>OVD indicates vdda is ok.</description>
10803              <bitRange>[9:9]</bitRange>
10804              <access>read-only</access>
10805            </field>
10806            <field>
10807              <name>OVDVCCD_OK</name>
10808              <description>OVD indicates vccd is ok.    This will always read 1, because a detected over-over-voltage condition will reset the chip.</description>
10809              <bitRange>[10:10]</bitRange>
10810              <access>read-only</access>
10811            </field>
10812            <field>
10813              <name>OCD_ACT_LINREG_OK</name>
10814              <description>OCD indicates the current drawn from the linear Active Regulator is ok.  This will always read 1, because a detected over-current condition will reset the chip.</description>
10815              <bitRange>[16:16]</bitRange>
10816              <access>read-only</access>
10817            </field>
10818            <field>
10819              <name>OCD_DPSLP_REG_OK</name>
10820              <description>OCD indicates the current drawn from the linear DeepSleep Regulator is ok.    This will always read 1, because a detected over-current condition will reset the chip.</description>
10821              <bitRange>[17:17]</bitRange>
10822              <access>read-only</access>
10823            </field>
10824          </fields>
10825        </register>
10826        <register>
10827          <name>PWR_LVD_CTL</name>
10828          <description>High Voltage / Low Voltage Detector (HVLVD) Configuration Register</description>
10829          <addressOffset>0x1020</addressOffset>
10830          <size>32</size>
10831          <access>read-write</access>
10832          <resetValue>0x0</resetValue>
10833          <resetMask>0x7DFFF</resetMask>
10834          <fields>
10835            <field>
10836              <name>HVLVD1_TRIPSEL</name>
10837              <description>Threshold selection for HVLVD1 for products.  Disable the detector (HVLVD1_EN=0) before changing the threshold.
108380: rise=1.225V (nom), fall=1.2V (nom)
108391: rise=1.425V (nom), fall=1.4V (nom)
108402: rise=1.625V (nom), fall=1.6V (nom)
108413: rise=1.825V (nom), fall=1.8V (nom)
108424: rise=2.025V (nom), fall=2V (nom)
108435: rise=2.125V (nom), fall=2.1V (nom)
108446: rise=2.225V (nom), fall=2.2V (nom)
108457: rise=2.325V (nom), fall=2.3V (nom)
108468: rise=2.425V (nom), fall=2.4V (nom)
108479: rise=2.525V (nom), fall=2.5V (nom)
1084810: rise=2.625V (nom), fall=2.6V (nom)
1084911: rise=2.725V (nom), fall=2.7V (nom)
1085012: rise=2.825V (nom), fall=2.8V (nom)
1085113: rise=2.925V (nom), fall=2.9V (nom)
1085214: rise=3.025V (nom), fall=3.0V (nom)
1085315: rise=3.125V (nom), fall=3.1V (nom)</description>
10854              <bitRange>[3:0]</bitRange>
10855              <access>read-write</access>
10856            </field>
10857            <field>
10858              <name>HVLVD1_SRCSEL</name>
10859              <description>Source selection for HVLVD1</description>
10860              <bitRange>[6:4]</bitRange>
10861              <access>read-write</access>
10862              <enumeratedValues>
10863                <enumeratedValue>
10864                  <name>VDDD</name>
10865                  <description>Select VDDD</description>
10866                  <value>0</value>
10867                </enumeratedValue>
10868                <enumeratedValue>
10869                  <name>AMUXBUSA</name>
10870                  <description>Select AMUXBUSA (VDDD branch)</description>
10871                  <value>1</value>
10872                </enumeratedValue>
10873                <enumeratedValue>
10874                  <name>RSVD</name>
10875                  <description>N/A</description>
10876                  <value>2</value>
10877                </enumeratedValue>
10878                <enumeratedValue>
10879                  <name>VDDIO</name>
10880                  <description>N/A</description>
10881                  <value>3</value>
10882                </enumeratedValue>
10883                <enumeratedValue>
10884                  <name>AMUXBUSB</name>
10885                  <description>Select AMUXBUSB (VDDD branch)</description>
10886                  <value>4</value>
10887                </enumeratedValue>
10888              </enumeratedValues>
10889            </field>
10890            <field>
10891              <name>HVLVD1_EN</name>
10892              <description>Enable HVLVD1 voltage monitor.  HVLVD1 does not function during DEEPSLEEP, but it automatically returns to its configured setting after DEEPSLEEP wakeup.  Do not change other HVLVD1 settings when enabled.</description>
10893              <bitRange>[7:7]</bitRange>
10894              <access>read-write</access>
10895            </field>
10896            <field>
10897              <name>HVLVD1_TRIPSEL_HT</name>
10898              <description>N/A</description>
10899              <bitRange>[12:8]</bitRange>
10900              <access>read-write</access>
10901            </field>
10902            <field>
10903              <name>HVLVD1_DPSLP_EN_HT</name>
10904              <description>Keep HVLVD1 voltage monitor enabled during DEEPSLEEP mode.  This field is only used when HVLVD1_EN_HT==1.</description>
10905              <bitRange>[14:14]</bitRange>
10906              <access>read-write</access>
10907            </field>
10908            <field>
10909              <name>HVLVD1_EN_HT</name>
10910              <description>Enable HVLVD1 voltage monitor.  This detector monitors vddd only.  Do not change other HVLVD1 settings when enabled.</description>
10911              <bitRange>[15:15]</bitRange>
10912              <access>read-write</access>
10913            </field>
10914            <field>
10915              <name>HVLVD1_EDGE_SEL</name>
10916              <description>Sets which edge(s) will trigger an action when the threshold is crossed.</description>
10917              <bitRange>[17:16]</bitRange>
10918              <access>read-write</access>
10919              <enumeratedValues>
10920                <enumeratedValue>
10921                  <name>DISABLE</name>
10922                  <description>Disabled</description>
10923                  <value>0</value>
10924                </enumeratedValue>
10925                <enumeratedValue>
10926                  <name>RISING</name>
10927                  <description>Rising edge</description>
10928                  <value>1</value>
10929                </enumeratedValue>
10930                <enumeratedValue>
10931                  <name>FALLING</name>
10932                  <description>Falling edge</description>
10933                  <value>2</value>
10934                </enumeratedValue>
10935                <enumeratedValue>
10936                  <name>BOTH</name>
10937                  <description>Both rising and falling edges</description>
10938                  <value>3</value>
10939                </enumeratedValue>
10940              </enumeratedValues>
10941            </field>
10942            <field>
10943              <name>HVLVD1_ACTION</name>
10944              <description>Action taken when the threshold is crossed in the programmed directions(s)</description>
10945              <bitRange>[18:18]</bitRange>
10946              <access>read-write</access>
10947              <enumeratedValues>
10948                <enumeratedValue>
10949                  <name>INTERRUPT</name>
10950                  <description>Generate an interrupt</description>
10951                  <value>0</value>
10952                </enumeratedValue>
10953                <enumeratedValue>
10954                  <name>FAULT</name>
10955                  <description>Generate a fault</description>
10956                  <value>1</value>
10957                </enumeratedValue>
10958              </enumeratedValues>
10959            </field>
10960          </fields>
10961        </register>
10962        <register>
10963          <name>PWR_LVD_CTL2</name>
10964          <description>High Voltage / Low Voltage Detector (HVLVD) Configuration Register #2</description>
10965          <addressOffset>0x1024</addressOffset>
10966          <size>32</size>
10967          <access>read-write</access>
10968          <resetValue>0x0</resetValue>
10969          <resetMask>0x7DF00</resetMask>
10970          <fields>
10971            <field>
10972              <name>HVLVD2_TRIPSEL_HT</name>
10973              <description>N/A</description>
10974              <bitRange>[12:8]</bitRange>
10975              <access>read-write</access>
10976            </field>
10977            <field>
10978              <name>HVLVD2_DPSLP_EN_HT</name>
10979              <description>Keep HVLVD2 voltage monitor enabled during DEEPSLEEP mode.  This field is only used when HVLVD1_EN_HT==1.</description>
10980              <bitRange>[14:14]</bitRange>
10981              <access>read-write</access>
10982            </field>
10983            <field>
10984              <name>HVLVD2_EN_HT</name>
10985              <description>Enable HVLVD2 voltage monitor.  This detector monitors vddd only.  Do not change other HVLVD2 settings when enabled.</description>
10986              <bitRange>[15:15]</bitRange>
10987              <access>read-write</access>
10988            </field>
10989            <field>
10990              <name>HVLVD2_EDGE_SEL</name>
10991              <description>Sets which edge(s) will trigger an action when the threshold is crossed.</description>
10992              <bitRange>[17:16]</bitRange>
10993              <access>read-write</access>
10994              <enumeratedValues>
10995                <enumeratedValue>
10996                  <name>DISABLE</name>
10997                  <description>Disabled</description>
10998                  <value>0</value>
10999                </enumeratedValue>
11000                <enumeratedValue>
11001                  <name>RISING</name>
11002                  <description>Rising edge</description>
11003                  <value>1</value>
11004                </enumeratedValue>
11005                <enumeratedValue>
11006                  <name>FALLING</name>
11007                  <description>Falling edge</description>
11008                  <value>2</value>
11009                </enumeratedValue>
11010                <enumeratedValue>
11011                  <name>BOTH</name>
11012                  <description>Both rising and falling edges</description>
11013                  <value>3</value>
11014                </enumeratedValue>
11015              </enumeratedValues>
11016            </field>
11017            <field>
11018              <name>HVLVD2_ACTION</name>
11019              <description>Action taken when the threshold is crossed in the programmed directions(s)</description>
11020              <bitRange>[18:18]</bitRange>
11021              <access>read-write</access>
11022              <enumeratedValues>
11023                <enumeratedValue>
11024                  <name>INTERRUPT</name>
11025                  <description>Generate an interrupt</description>
11026                  <value>0</value>
11027                </enumeratedValue>
11028                <enumeratedValue>
11029                  <name>FAULT</name>
11030                  <description>Generate a fault</description>
11031                  <value>1</value>
11032                </enumeratedValue>
11033              </enumeratedValues>
11034            </field>
11035          </fields>
11036        </register>
11037        <register>
11038          <dim>16</dim>
11039          <dimIncrement>4</dimIncrement>
11040          <name>PWR_HIB_DATA[%s]</name>
11041          <description>HIBERNATE Data Register</description>
11042          <addressOffset>0x1040</addressOffset>
11043          <size>32</size>
11044          <access>read-write</access>
11045          <resetValue>0x0</resetValue>
11046          <resetMask>0xFFFFFFFF</resetMask>
11047          <fields>
11048            <field>
11049              <name>HIB_DATA</name>
11050              <description>Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose.  Note that waking up from HIBERNATE using XRES will reset this register.</description>
11051              <bitRange>[31:0]</bitRange>
11052              <access>read-write</access>
11053            </field>
11054          </fields>
11055        </register>
11056        <register>
11057          <dim>16</dim>
11058          <dimIncrement>4</dimIncrement>
11059          <name>CLK_PATH_SELECT[%s]</name>
11060          <description>Clock Path Select Register</description>
11061          <addressOffset>0x1200</addressOffset>
11062          <size>32</size>
11063          <access>read-write</access>
11064          <resetValue>0x0</resetValue>
11065          <resetMask>0x7</resetMask>
11066          <fields>
11067            <field>
11068              <name>PATH_MUX</name>
11069              <description>Selects a source for clock PATH&lt;i&gt;.  Note that not all products support all clock sources.  Selecting a clock source that is not supported will result in undefined behavior.  It takes four cycles of the originally selected clock to switch away from it.  Do not disable the original clock during this time.</description>
11070              <bitRange>[2:0]</bitRange>
11071              <access>read-write</access>
11072              <enumeratedValues>
11073                <enumeratedValue>
11074                  <name>IMO</name>
11075                  <description>IMO - Internal R/C Oscillator</description>
11076                  <value>0</value>
11077                </enumeratedValue>
11078                <enumeratedValue>
11079                  <name>EXTCLK</name>
11080                  <description>EXTCLK - External Clock Pin</description>
11081                  <value>1</value>
11082                </enumeratedValue>
11083                <enumeratedValue>
11084                  <name>ECO</name>
11085                  <description>ECO - External-Crystal Oscillator</description>
11086                  <value>2</value>
11087                </enumeratedValue>
11088                <enumeratedValue>
11089                  <name>ALTHF</name>
11090                  <description>ALTHF - Alternate High-Frequency clock input (product-specific clock)</description>
11091                  <value>3</value>
11092                </enumeratedValue>
11093                <enumeratedValue>
11094                  <name>DSI_MUX</name>
11095                  <description>DSI_MUX - Output of DSI mux for this path.  Using a DSI source directly as root of HFCLK will result in undefined behavior.</description>
11096                  <value>4</value>
11097                </enumeratedValue>
11098                <enumeratedValue>
11099                  <name>LPECO</name>
11100                  <description>N/A</description>
11101                  <value>5</value>
11102                </enumeratedValue>
11103              </enumeratedValues>
11104            </field>
11105          </fields>
11106        </register>
11107        <register>
11108          <dim>16</dim>
11109          <dimIncrement>4</dimIncrement>
11110          <name>CLK_ROOT_SELECT[%s]</name>
11111          <description>Clock Root Select Register</description>
11112          <addressOffset>0x1240</addressOffset>
11113          <size>32</size>
11114          <access>read-write</access>
11115          <resetValue>0x0</resetValue>
11116          <resetMask>0x8000003F</resetMask>
11117          <fields>
11118            <field>
11119              <name>ROOT_MUX</name>
11120              <description>Selects a clock path as the root of HFCLK&lt;k&gt; and for SRSS DSI input &lt;k&gt;.  Use CLK_PATH_SELECT[i] to configure the desired path.  Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers.  Configure the FLL using CLK_FLL_CONFIG register.  Configure a PLL using the related CLK_PLL_CONFIG[k] register.  Note that not all products support all clock sources.  Selecting a clock source that is not supported will result in undefined behavior.  It takes four cycles of the originally selected clock to switch away from it.  Do not disable the original clock during this time.</description>
11121              <bitRange>[3:0]</bitRange>
11122              <access>read-write</access>
11123              <enumeratedValues>
11124                <enumeratedValue>
11125                  <name>PATH0</name>
11126                  <description>Select PATH0 (can be configured for FLL)</description>
11127                  <value>0</value>
11128                </enumeratedValue>
11129                <enumeratedValue>
11130                  <name>PATH1</name>
11131                  <description>Select PATH1 (can be configured for PLL0, if available in the product)</description>
11132                  <value>1</value>
11133                </enumeratedValue>
11134                <enumeratedValue>
11135                  <name>PATH2</name>
11136                  <description>Select PATH2 (can be configured for PLL1, if available in the product)</description>
11137                  <value>2</value>
11138                </enumeratedValue>
11139                <enumeratedValue>
11140                  <name>PATH3</name>
11141                  <description>Select PATH3 (can be configured for PLL2, if available in the product)</description>
11142                  <value>3</value>
11143                </enumeratedValue>
11144                <enumeratedValue>
11145                  <name>PATH4</name>
11146                  <description>Select PATH4 (can be configured for PLL3, if available in the product)</description>
11147                  <value>4</value>
11148                </enumeratedValue>
11149                <enumeratedValue>
11150                  <name>PATH5</name>
11151                  <description>Select PATH5 (can be configured for PLL4, if available in the product)</description>
11152                  <value>5</value>
11153                </enumeratedValue>
11154                <enumeratedValue>
11155                  <name>PATH6</name>
11156                  <description>Select PATH6 (can be configured for PLL5, if available in the product)</description>
11157                  <value>6</value>
11158                </enumeratedValue>
11159                <enumeratedValue>
11160                  <name>PATH7</name>
11161                  <description>Select PATH7 (can be configured for PLL6, if available in the product)</description>
11162                  <value>7</value>
11163                </enumeratedValue>
11164                <enumeratedValue>
11165                  <name>PATH8</name>
11166                  <description>Select PATH8 (can be configured for PLL7, if available in the product)</description>
11167                  <value>8</value>
11168                </enumeratedValue>
11169                <enumeratedValue>
11170                  <name>PATH9</name>
11171                  <description>Select PATH9 (can be configured for PLL8, if available in the product)</description>
11172                  <value>9</value>
11173                </enumeratedValue>
11174                <enumeratedValue>
11175                  <name>PATH10</name>
11176                  <description>Select PATH10 (can be configured for PLL9, if available in the product)</description>
11177                  <value>10</value>
11178                </enumeratedValue>
11179                <enumeratedValue>
11180                  <name>PATH11</name>
11181                  <description>Select PATH11 (can be configured for PLL10, if available in the product)</description>
11182                  <value>11</value>
11183                </enumeratedValue>
11184                <enumeratedValue>
11185                  <name>PATH12</name>
11186                  <description>Select PATH12 (can be configured for PLL11, if available in the product)</description>
11187                  <value>12</value>
11188                </enumeratedValue>
11189                <enumeratedValue>
11190                  <name>PATH13</name>
11191                  <description>Select PATH13 (can be configured for PLL12, if available in the product)</description>
11192                  <value>13</value>
11193                </enumeratedValue>
11194                <enumeratedValue>
11195                  <name>PATH14</name>
11196                  <description>Select PATH14 (can be configured for PLL13, if available in the product)</description>
11197                  <value>14</value>
11198                </enumeratedValue>
11199                <enumeratedValue>
11200                  <name>PATH15</name>
11201                  <description>Select PATH15 (can be configured for PLL14, if available in the product)</description>
11202                  <value>15</value>
11203                </enumeratedValue>
11204              </enumeratedValues>
11205            </field>
11206            <field>
11207              <name>ROOT_DIV</name>
11208              <description>Selects predivider value for this clock root and DSI input.</description>
11209              <bitRange>[5:4]</bitRange>
11210              <access>read-write</access>
11211              <enumeratedValues>
11212                <enumeratedValue>
11213                  <name>NO_DIV</name>
11214                  <description>Transparent mode, feed through selected clock source w/o dividing.</description>
11215                  <value>0</value>
11216                </enumeratedValue>
11217                <enumeratedValue>
11218                  <name>DIV_BY_2</name>
11219                  <description>Divide selected clock source by 2</description>
11220                  <value>1</value>
11221                </enumeratedValue>
11222                <enumeratedValue>
11223                  <name>DIV_BY_4</name>
11224                  <description>Divide selected clock source by 4</description>
11225                  <value>2</value>
11226                </enumeratedValue>
11227                <enumeratedValue>
11228                  <name>DIV_BY_8</name>
11229                  <description>Divide selected clock source by 8</description>
11230                  <value>3</value>
11231                </enumeratedValue>
11232              </enumeratedValues>
11233            </field>
11234            <field>
11235              <name>ENABLE</name>
11236              <description>Enable for this clock root.  All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.</description>
11237              <bitRange>[31:31]</bitRange>
11238              <access>read-write</access>
11239            </field>
11240          </fields>
11241        </register>
11242        <cluster>
11243          <name>CSV_HF</name>
11244          <description>Clock Supervisor (CSV) registers for Root clocks</description>
11245          <headerStructName>CSV_HF</headerStructName>
11246          <addressOffset>0x00001400</addressOffset>
11247          <cluster>
11248            <dim>3</dim>
11249            <dimIncrement>16</dimIncrement>
11250            <name>CSV[%s]</name>
11251            <description>Active domain Clock Supervisor (CSV) registers</description>
11252            <headerStructName>CSV_HF_CSV</headerStructName>
11253            <addressOffset>0x00000000</addressOffset>
11254            <register>
11255              <name>REF_CTL</name>
11256              <description>Clock Supervision Reference Control</description>
11257              <addressOffset>0x0</addressOffset>
11258              <size>32</size>
11259              <access>read-write</access>
11260              <resetValue>0x0</resetValue>
11261              <resetMask>0xC000FFFF</resetMask>
11262              <fields>
11263                <field>
11264                  <name>STARTUP</name>
11265                  <description>Startup delay time -1 (in reference clock cycles), after enable or DeepSleep wakeup, from reference clock start to monitored clock start.
11266At a minimum (both clocks running): STARTUP &gt;= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency)
11267On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added.</description>
11268                  <bitRange>[15:0]</bitRange>
11269                  <access>read-write</access>
11270                </field>
11271                <field>
11272                  <name>CSV_ACTION</name>
11273                  <description>Specifies the action taken when an anomaly is detected on the monitored clock.  CSV in DeepSleep domain always do a Fault report (which also wakes up the system).</description>
11274                  <bitRange>[30:30]</bitRange>
11275                  <access>read-write</access>
11276                  <enumeratedValues>
11277                    <enumeratedValue>
11278                      <name>FAULT</name>
11279                      <description>Do a Fault report.</description>
11280                      <value>0</value>
11281                    </enumeratedValue>
11282                    <enumeratedValue>
11283                      <name>RESET</name>
11284                      <description>Cause a power reset. This should only be used for clk_hf0.</description>
11285                      <value>1</value>
11286                    </enumeratedValue>
11287                  </enumeratedValues>
11288                </field>
11289                <field>
11290                  <name>CSV_EN</name>
11291                  <description>Enables clock supervision, both frequency and loss.
11292CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes.  When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup.
11293CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode.  It must be reconfigured after Hibernate wakeup.
11294
11295A CSV error detection is reported to the Fault structure, or instead it can generate a power reset.</description>
11296                  <bitRange>[31:31]</bitRange>
11297                  <access>read-write</access>
11298                </field>
11299              </fields>
11300            </register>
11301            <register>
11302              <name>REF_LIMIT</name>
11303              <description>Clock Supervision Reference Limits</description>
11304              <addressOffset>0x4</addressOffset>
11305              <size>32</size>
11306              <access>read-write</access>
11307              <resetValue>0x0</resetValue>
11308              <resetMask>0xFFFFFFFF</resetMask>
11309              <fields>
11310                <field>
11311                  <name>LOWER</name>
11312                  <description>Cycle time lower limit.  Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen.  If a monitored clock event happens before this limit is reached a CSV error is detected.
11313LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER.</description>
11314                  <bitRange>[15:0]</bitRange>
11315                  <access>read-write</access>
11316                </field>
11317                <field>
11318                  <name>UPPER</name>
11319                  <description>Cycle time upper limit.  Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen.  If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected.</description>
11320                  <bitRange>[31:16]</bitRange>
11321                  <access>read-write</access>
11322                </field>
11323              </fields>
11324            </register>
11325            <register>
11326              <name>MON_CTL</name>
11327              <description>Clock Supervision Monitor Control</description>
11328              <addressOffset>0x8</addressOffset>
11329              <size>32</size>
11330              <access>read-write</access>
11331              <resetValue>0x0</resetValue>
11332              <resetMask>0xFFFF</resetMask>
11333              <fields>
11334                <field>
11335                  <name>PERIOD</name>
11336                  <description>Period time.  Set the Period -1, in monitored clock cycles, before the next monitored clock event happens.
11337PERIOD &lt;=  (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency)
11338In case the clocks are asynchronous: PERIOD &lt;=  UPPER / FREQ_RATIO -1
11339Additionally margin must be added for accuracy of both clocks.</description>
11340                  <bitRange>[15:0]</bitRange>
11341                  <access>read-write</access>
11342                </field>
11343              </fields>
11344            </register>
11345          </cluster>
11346        </cluster>
11347        <register>
11348          <name>CLK_SELECT</name>
11349          <description>Clock selection register</description>
11350          <addressOffset>0x1500</addressOffset>
11351          <size>32</size>
11352          <access>read-write</access>
11353          <resetValue>0x0</resetValue>
11354          <resetMask>0xFF07</resetMask>
11355          <fields>
11356            <field>
11357              <name>LFCLK_SEL</name>
11358              <description>Select source for LFCLK.  Note that not all products support all clock sources.  Selecting a clock source that is not supported will result in undefined behavior.  Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.  It takes four cycles of the originally selected clock to switch away from it.  Do not disable the original clock during this time.</description>
11359              <bitRange>[2:0]</bitRange>
11360              <access>read-write</access>
11361              <enumeratedValues>
11362                <enumeratedValue>
11363                  <name>ILO0</name>
11364                  <description>ILO0 - Internal Low-speed Oscillator #0.</description>
11365                  <value>0</value>
11366                </enumeratedValue>
11367                <enumeratedValue>
11368                  <name>WCO</name>
11369                  <description>WCO - Watch-Crystal Oscillator.  Requires Backup domain to be present and properly configured (including external watch crystal, if used).</description>
11370                  <value>1</value>
11371                </enumeratedValue>
11372                <enumeratedValue>
11373                  <name>ALTLF</name>
11374                  <description>ALTLF - Alternate Low-Frequency Clock.  Capability is product-specific</description>
11375                  <value>2</value>
11376                </enumeratedValue>
11377                <enumeratedValue>
11378                  <name>PILO</name>
11379                  <description>PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes.  Does not work in HIBERNATE mode.</description>
11380                  <value>3</value>
11381                </enumeratedValue>
11382                <enumeratedValue>
11383                  <name>ILO1</name>
11384                  <description>ILO1 - Internal Low-speed Oscillator #1, if present.</description>
11385                  <value>4</value>
11386                </enumeratedValue>
11387                <enumeratedValue>
11388                  <name>ECO_PRESCALE</name>
11389                  <description>ECO_PRESCALE - External-Crystal Oscillator after prescaling in CLK_ECO_PRESCALE.  Does not work in DEEPSLEEP or HIBERNATE modes.  Intended for applications that operate in ACTIVE/SLEEP modes only.  This option is only valid when an ECO present in the product.</description>
11390                  <value>5</value>
11391                </enumeratedValue>
11392              </enumeratedValues>
11393            </field>
11394            <field>
11395              <name>PUMP_SEL</name>
11396              <description>N/A</description>
11397              <bitRange>[11:8]</bitRange>
11398              <access>read-write</access>
11399            </field>
11400            <field>
11401              <name>PUMP_DIV</name>
11402              <description>N/A</description>
11403              <bitRange>[14:12]</bitRange>
11404              <access>read-write</access>
11405              <enumeratedValues>
11406                <enumeratedValue>
11407                  <name>NO_DIV</name>
11408                  <description>N/A</description>
11409                  <value>0</value>
11410                </enumeratedValue>
11411                <enumeratedValue>
11412                  <name>DIV_BY_2</name>
11413                  <description>N/A</description>
11414                  <value>1</value>
11415                </enumeratedValue>
11416                <enumeratedValue>
11417                  <name>DIV_BY_4</name>
11418                  <description>N/A</description>
11419                  <value>2</value>
11420                </enumeratedValue>
11421                <enumeratedValue>
11422                  <name>DIV_BY_8</name>
11423                  <description>N/A</description>
11424                  <value>3</value>
11425                </enumeratedValue>
11426                <enumeratedValue>
11427                  <name>DIV_BY_16</name>
11428                  <description>N/A</description>
11429                  <value>4</value>
11430                </enumeratedValue>
11431              </enumeratedValues>
11432            </field>
11433            <field>
11434              <name>PUMP_ENABLE</name>
11435              <description>N/A</description>
11436              <bitRange>[15:15]</bitRange>
11437              <access>read-write</access>
11438            </field>
11439          </fields>
11440        </register>
11441        <register>
11442          <name>CLK_TIMER_CTL</name>
11443          <description>Timer Clock Control Register</description>
11444          <addressOffset>0x1504</addressOffset>
11445          <size>32</size>
11446          <access>read-write</access>
11447          <resetValue>0x70000</resetValue>
11448          <resetMask>0x80FF0301</resetMask>
11449          <fields>
11450            <field>
11451              <name>TIMER_SEL</name>
11452              <description>Select source for TIMERCLK.  The output of this mux can be further divided using TIMER_DIV.  It takes four cycles of the originally selected clock to switch away from it.  Do not disable the original clock during this time.</description>
11453              <bitRange>[0:0]</bitRange>
11454              <access>read-write</access>
11455              <enumeratedValues>
11456                <enumeratedValue>
11457                  <name>IMO</name>
11458                  <description>IMO - Internal Main Oscillator</description>
11459                  <value>0</value>
11460                </enumeratedValue>
11461                <enumeratedValue>
11462                  <name>HF0_DIV</name>
11463                  <description>Select the output of the predivider configured by TIMER_HF0_DIV.</description>
11464                  <value>1</value>
11465                </enumeratedValue>
11466              </enumeratedValues>
11467            </field>
11468            <field>
11469              <name>TIMER_HF0_DIV</name>
11470              <description>Predivider used when HF0_DIV is selected in TIMER_SEL.  If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV).  Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock.</description>
11471              <bitRange>[9:8]</bitRange>
11472              <access>read-write</access>
11473              <enumeratedValues>
11474                <enumeratedValue>
11475                  <name>NO_DIV</name>
11476                  <description>Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle.</description>
11477                  <value>0</value>
11478                </enumeratedValue>
11479                <enumeratedValue>
11480                  <name>DIV_BY_2</name>
11481                  <description>Divide HFCLK0 by 2.</description>
11482                  <value>1</value>
11483                </enumeratedValue>
11484                <enumeratedValue>
11485                  <name>DIV_BY_4</name>
11486                  <description>Divide HFCLK0 by 4.</description>
11487                  <value>2</value>
11488                </enumeratedValue>
11489                <enumeratedValue>
11490                  <name>DIV_BY_8</name>
11491                  <description>Divide HFCLK0 by 8.</description>
11492                  <value>3</value>
11493                </enumeratedValue>
11494              </enumeratedValues>
11495            </field>
11496            <field>
11497              <name>TIMER_DIV</name>
11498              <description>Divide selected timer clock source by (1+TIMER_DIV).  The output of this divider is TIMERCLK  Allows for integer divisions in the range [1, 256].  Do not change this setting while the timer is enabled.</description>
11499              <bitRange>[23:16]</bitRange>
11500              <access>read-write</access>
11501            </field>
11502            <field>
11503              <name>ENABLE</name>
11504              <description>Enable for TIMERCLK.
115050: TIMERCLK is off
115061: TIMERCLK is enabled</description>
11507              <bitRange>[31:31]</bitRange>
11508              <access>read-write</access>
11509            </field>
11510          </fields>
11511        </register>
11512        <register>
11513          <name>CLK_ILO0_CONFIG</name>
11514          <description>ILO0 Configuration</description>
11515          <addressOffset>0x1508</addressOffset>
11516          <size>32</size>
11517          <access>read-write</access>
11518          <resetValue>0x80000000</resetValue>
11519          <resetMask>0xC0000001</resetMask>
11520          <fields>
11521            <field>
11522              <name>ILO0_BACKUP</name>
11523              <description>This register indicates that ILO0 should stay enabled during XRES and HIBERNATE modes.  If backup voltage domain is implemented on the product, this bit also indicates if ILO0 should stay enabled through power-related resets on other supplies, e.g.. BOD on VDDD/VCCD.  Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.  This register is reset when the backup logic resets.
115240: ILO0 turns off during XRES, HIBERNATE, and power-related resets.  ILO0 configuration and trims are reset by these events.
115251: ILO0 stays enabled, as described above.  ILO0 configuration and trims are not reset by these events.</description>
11526              <bitRange>[0:0]</bitRange>
11527              <access>read-write</access>
11528            </field>
11529            <field>
11530              <name>ILO0_MON_ENABLE</name>
11531              <description>N/A</description>
11532              <bitRange>[30:30]</bitRange>
11533              <access>read-write</access>
11534            </field>
11535            <field>
11536              <name>ENABLE</name>
11537              <description>Master enable for ILO.  Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.
11538
11539HT-variant: This register will not clear unless PWR_CTL2.BGREF_LPMODE==0. After enabling, the first ILO0 cycle occurs within 12us and is +/-10 percent accuracy.  Thereafter, ILO0 is +/-5 percent accurate.</description>
11540              <bitRange>[31:31]</bitRange>
11541              <access>read-write</access>
11542            </field>
11543          </fields>
11544        </register>
11545        <register>
11546          <name>CLK_ILO1_CONFIG</name>
11547          <description>ILO1 Configuration</description>
11548          <addressOffset>0x150C</addressOffset>
11549          <size>32</size>
11550          <access>read-write</access>
11551          <resetValue>0x0</resetValue>
11552          <resetMask>0xC0000000</resetMask>
11553          <fields>
11554            <field>
11555              <name>ILO1_MON_ENABLE</name>
11556              <description>N/A</description>
11557              <bitRange>[30:30]</bitRange>
11558              <access>read-write</access>
11559            </field>
11560            <field>
11561              <name>ENABLE</name>
11562              <description>Master enable for ILO1.
11563
11564HT-variant: After enabling, the first ILO1 cycle occurs within 12us and is +/-10 percent accuracy.  Thereafter, ILO1 is +/-5 percent accurate.</description>
11565              <bitRange>[31:31]</bitRange>
11566              <access>read-write</access>
11567            </field>
11568          </fields>
11569        </register>
11570        <register>
11571          <name>CLK_IMO_CONFIG</name>
11572          <description>IMO Configuration</description>
11573          <addressOffset>0x1518</addressOffset>
11574          <size>32</size>
11575          <access>read-write</access>
11576          <resetValue>0x80000000</resetValue>
11577          <resetMask>0x80000000</resetMask>
11578          <fields>
11579            <field>
11580              <name>ENABLE</name>
11581              <description>Master enable for IMO oscillator.  This bit must be high at all times for all functions to work properly.  Hardware will automatically disable the IMO during DEEPSLEEP, HIBERNATE, and XRES.</description>
11582              <bitRange>[31:31]</bitRange>
11583              <access>read-write</access>
11584            </field>
11585          </fields>
11586        </register>
11587        <register>
11588          <name>CLK_ECO_CONFIG</name>
11589          <description>ECO Configuration Register</description>
11590          <addressOffset>0x151C</addressOffset>
11591          <size>32</size>
11592          <access>read-write</access>
11593          <resetValue>0x2</resetValue>
11594          <resetMask>0x98000002</resetMask>
11595          <fields>
11596            <field>
11597              <name>AGC_EN</name>
11598              <description>Automatic Gain Control (AGC) enable.  When set, the oscillation amplitude is controlled to the level selected by CLK_ECO_CONFIG2.ATRIM.  When low, the amplitude is not explicitly controlled and can be as high as the vddd supply.  WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal.</description>
11599              <bitRange>[1:1]</bitRange>
11600              <access>read-write</access>
11601            </field>
11602            <field>
11603              <name>ECO_DIV_DISABLE</name>
11604              <description>ECO prescaler disable command (mutually exclusive with ECO_DIV_ENABLE). SW sets this field to '1' and HW sets this field to '0'.
11605
11606HW sets ECO_DIV_DISABLE field to '0' immediately and HW sets CLK_ECO_PRESCALE.ECO_DIV_EN field to '0' immediately.</description>
11607              <bitRange>[27:27]</bitRange>
11608              <access>read-write</access>
11609            </field>
11610            <field>
11611              <name>ECO_DIV_ENABLE</name>
11612              <description>ECO prescaler enable command (mutually exclusive with ECO_DIV_DISABLE). ECO Prescaler only works in ACTIVE and SLEEP modes.  SW sets this field to '1' to enable the divider and HW sets this field to '0' to indicate that divider enabling has completed. When the divider is enabled, its integer and fractional counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps:
116130: Disable the divider using the ECO_DIV_DISABLE field.
116141: Configure CLK_ECO_PRESCALE registers.
116152: Enable the divider using the ECO_DIV_ENABLE field.
11616
11617HW sets the ECO_DIV_ENABLE field to '0' when the enabling is performed and HW set CLK_ECO_PRESCALER.ENABLED to '1' when the enabling is performed.</description>
11618              <bitRange>[28:28]</bitRange>
11619              <access>read-write</access>
11620            </field>
11621            <field>
11622              <name>ECO_EN</name>
11623              <description>Master enable for ECO oscillator.</description>
11624              <bitRange>[31:31]</bitRange>
11625              <access>read-write</access>
11626            </field>
11627          </fields>
11628        </register>
11629        <register>
11630          <name>CLK_ECO_PRESCALE</name>
11631          <description>ECO Prescaler Configuration Register</description>
11632          <addressOffset>0x1520</addressOffset>
11633          <size>32</size>
11634          <access>read-write</access>
11635          <resetValue>0x0</resetValue>
11636          <resetMask>0x3FFFF01</resetMask>
11637          <fields>
11638            <field>
11639              <name>ECO_DIV_ENABLED</name>
11640              <description>ECO prescaler enabled. HW sets this field to '1' as a result of an CLK_ECO_CONFIG.ECO_DIV_ENABLE command. HW sets this field to '0' as a result on a CLK_ECO_CONFIG.ECO_DIV_DISABLE command.</description>
11641              <bitRange>[0:0]</bitRange>
11642              <access>read-only</access>
11643            </field>
11644            <field>
11645              <name>ECO_FRAC_DIV</name>
11646              <description>8-bit fractional value, sufficient to get prescaler output within the +/-65ppm calibration range.  Do not change this setting when ECO Prescaler is enabled.</description>
11647              <bitRange>[15:8]</bitRange>
11648              <access>read-write</access>
11649            </field>
11650            <field>
11651              <name>ECO_INT_DIV</name>
11652              <description>10-bit integer value allows for ECO frequencies up to 33.55MHz.  Subtract one from the desired divide value when writing this field.  For example, to divide by 1, write ECO_INT_DIV=0.  Do not change this setting when ECO Prescaler is enabled.</description>
11653              <bitRange>[25:16]</bitRange>
11654              <access>read-write</access>
11655            </field>
11656          </fields>
11657        </register>
11658        <register>
11659          <name>CLK_ECO_STATUS</name>
11660          <description>ECO Status Register</description>
11661          <addressOffset>0x1524</addressOffset>
11662          <size>32</size>
11663          <access>read-only</access>
11664          <resetValue>0x0</resetValue>
11665          <resetMask>0x3</resetMask>
11666          <fields>
11667            <field>
11668              <name>ECO_OK</name>
11669              <description>Indicates the ECO internal oscillator circuit has sufficient amplitude.  It may not meet the PPM accuracy or duty cycle spec.</description>
11670              <bitRange>[0:0]</bitRange>
11671              <access>read-only</access>
11672            </field>
11673            <field>
11674              <name>ECO_READY</name>
11675              <description>Indicates the ECO internal oscillator circuit has had enough time to fully stabilize.  This is the output of a counter since ECO was enabled, and it does not check the ECO output.  It is recommended to also confirm ECO_OK==1.</description>
11676              <bitRange>[1:1]</bitRange>
11677              <access>read-only</access>
11678            </field>
11679          </fields>
11680        </register>
11681        <register>
11682          <name>CLK_PILO_CONFIG</name>
11683          <description>Precision ILO Configuration Register</description>
11684          <addressOffset>0x1528</addressOffset>
11685          <size>32</size>
11686          <access>read-write</access>
11687          <resetValue>0x80</resetValue>
11688          <resetMask>0xE00003FF</resetMask>
11689          <fields>
11690            <field>
11691              <name>PILO_FFREQ</name>
11692              <description>Fine frequency trim allowing +/-250ppm accuracy with periodic calibration.  The nominal step size of the LSB is 8Hz.</description>
11693              <bitRange>[9:0]</bitRange>
11694              <access>read-write</access>
11695            </field>
11696            <field>
11697              <name>PILO_CLK_EN</name>
11698              <description>Enable the PILO clock output.  See PILO_EN field for required sequencing.</description>
11699              <bitRange>[29:29]</bitRange>
11700              <access>read-write</access>
11701            </field>
11702            <field>
11703              <name>PILO_RESET_N</name>
11704              <description>Reset the PILO.  See PILO_EN field for required sequencing.</description>
11705              <bitRange>[30:30]</bitRange>
11706              <access>read-write</access>
11707            </field>
11708            <field>
11709              <name>PILO_EN</name>
11710              <description>Enable PILO.  When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1.  When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle.</description>
11711              <bitRange>[31:31]</bitRange>
11712              <access>read-write</access>
11713            </field>
11714          </fields>
11715        </register>
11716        <register>
11717          <name>CLK_FLL_CONFIG</name>
11718          <description>FLL Configuration Register</description>
11719          <addressOffset>0x1530</addressOffset>
11720          <size>32</size>
11721          <access>read-write</access>
11722          <resetValue>0x1000000</resetValue>
11723          <resetMask>0x8103FFFF</resetMask>
11724          <fields>
11725            <field>
11726              <name>FLL_MULT</name>
11727              <description>Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref).
11728
11729Ffll = (FLL_MULT)  * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1)</description>
11730              <bitRange>[17:0]</bitRange>
11731              <access>read-write</access>
11732            </field>
11733            <field>
11734              <name>FLL_OUTPUT_DIV</name>
11735              <description>Control bits for Output divider.  Set the divide value before enabling the FLL, and do not change it while FLL is enabled.
117360: no division
117371: divide by 2</description>
11738              <bitRange>[24:24]</bitRange>
11739              <access>read-write</access>
11740            </field>
11741            <field>
11742              <name>FLL_ENABLE</name>
11743              <description>Master enable for FLL.  The FLL requires firmware sequencing when enabling and disabling.  Hardware handles sequencing automatically when entering/exiting DEEPSLEEP.
11744
11745To enable the FLL, use the following sequence:
117461) Configure FLL and CCO settings.  Do not modify CLK_FLL_CONFIG3.BYPASS_SEL (must be AUTO) or CLK_FLL_CONFIG.FLL_ENABLE (must be 0).
117472) Enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1
117483) Wait until CLK_FLL_STATUS.CCO_READY==1.
117494) Ensure the reference clock has stabilized.
117505) Write FLL_ENABLE=1.
117516) Optionally wait until CLK_FLL_STATUS.LOCKED==1.  The hardware automatically changes to the FLL output when LOCKED==1.
11752
11753To disable the FLL, use the following sequence:
117541) Write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF.
117552) Read CLK_FLL_CONFIG3.BYPASS_SEL to ensure the write completes (read is not optional).
117563) Wait at least ten cycles of either FLL reference clock or FLL output clock, whichever is slower.  It is recommended to use a HW counter (e.g. clock calibration counter, event generator) running on the slower clock.
117574) Disable FLL with FLL_ENABLE=0.
117585) Disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0.
117596) Write CLK_FLL_CONFIG3.BYPASS_SEL=AUTO.
117607) Read CLK_FLL_CONFIG3.BYPASS_SEL to ensure the write completes (read is not optional).
117618) Wait three cycles of FLL reference clock. It is recommended to use a HW counter (e.g. clock calibration counter, event generator) running on the reference clock.
11762
117630: Block is powered off
117641: Block is powered on</description>
11765              <bitRange>[31:31]</bitRange>
11766              <access>read-write</access>
11767            </field>
11768          </fields>
11769        </register>
11770        <register>
11771          <name>CLK_FLL_CONFIG2</name>
11772          <description>FLL Configuration Register 2</description>
11773          <addressOffset>0x1534</addressOffset>
11774          <size>32</size>
11775          <access>read-write</access>
11776          <resetValue>0x20001</resetValue>
11777          <resetMask>0xFFFF1FFF</resetMask>
11778          <fields>
11779            <field>
11780              <name>FLL_REF_DIV</name>
11781              <description>Control bits for reference divider.  Set the divide value before enabling the FLL, and do not change it while FLL is enabled.
117820: illegal (undefined behavior)
117831: divide by 1
11784...
117858191: divide by 8191</description>
11786              <bitRange>[12:0]</bitRange>
11787              <access>read-write</access>
11788            </field>
11789            <field>
11790              <name>LOCK_TOL</name>
11791              <description>Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input.  A high tolerance can be used to lock more quickly or allow less accuracy.  The tolerance is the allowed difference between the count value for the ideal formula and the measured value.
117920: tolerate error of 1 count value
117931: tolerate error of 2 count values
11794...
11795255: tolerate error of 256 count values</description>
11796              <bitRange>[23:16]</bitRange>
11797              <access>read-write</access>
11798            </field>
11799            <field>
11800              <name>UPDATE_TOL</name>
11801              <description>Update tolerance sets the error threshold for when the FLL will update the CCO frequency settings.  The update tolerance is the allowed difference between the count value for the ideal formula and the measured value. UPDATE_TOL should be less than LOCK_TOL.</description>
11802              <bitRange>[31:24]</bitRange>
11803              <access>read-write</access>
11804            </field>
11805          </fields>
11806        </register>
11807        <register>
11808          <name>CLK_FLL_CONFIG3</name>
11809          <description>FLL Configuration Register 3</description>
11810          <addressOffset>0x1538</addressOffset>
11811          <size>32</size>
11812          <access>read-write</access>
11813          <resetValue>0x2800</resetValue>
11814          <resetMask>0x301FFFFF</resetMask>
11815          <fields>
11816            <field>
11817              <name>FLL_LF_IGAIN</name>
11818              <description>FLL Loop Filter Gain Setting #1.  The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN.
118190: 1/256
118201: 1/128
118212: 1/64
118223: 1/32
118234: 1/16
118245: 1/8
118256: 1/4
118267: 1/2
118278: 1.0
118289: 2.0
1182910: 4.0
1183011: 8.0
11831&gt;=12: illegal</description>
11832              <bitRange>[3:0]</bitRange>
11833              <access>read-write</access>
11834            </field>
11835            <field>
11836              <name>FLL_LF_PGAIN</name>
11837              <description>FLL Loop Filter Gain Setting #2.  The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN.
118380: 1/256
118391: 1/128
118402: 1/64
118413: 1/32
118424: 1/16
118435: 1/8
118446: 1/4
118457: 1/2
118468: 1.0
118479: 2.0
1184810: 4.0
1184911: 8.0
11850&gt;=12: illegal</description>
11851              <bitRange>[7:4]</bitRange>
11852              <access>read-write</access>
11853            </field>
11854            <field>
11855              <name>SETTLING_COUNT</name>
11856              <description>Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts.  A delay allows the CCO output to settle and gives a more accurate measurement.  The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case.
118570: no settling time
118581: wait one reference clock cycle
11859...
118608191: wait 8191 reference clock cycles</description>
11861              <bitRange>[20:8]</bitRange>
11862              <access>read-write</access>
11863            </field>
11864            <field>
11865              <name>BYPASS_SEL</name>
11866              <description>Bypass mux located just after FLL output.  This register can be written while the FLL is enabled.  When changing BYPASS_SEL, do not turn off the reference clock or CCO clock for five cycles (whichever is slower).  In case of disabling FLL(FLL_ENABLE=0), additional five cycles are required. Refer to FLL disable sequence for more details in CLK_FLL_CONFIG-&gt;FLL_ENABLE.  Whenever BYPASS_SEL is changed, it is required to read CLK_FLL_CONFIG3 to ensure the change takes effect.</description>
11867              <bitRange>[29:28]</bitRange>
11868              <access>read-write</access>
11869              <enumeratedValues>
11870                <enumeratedValue>
11871                  <name>AUTO</name>
11872                  <description>Automatic using lock indicator.  When unlocked, automatically selects FLL reference input (bypass mode).  When locked, automatically selects FLL output.  This can allow some processing to occur while the FLL is locking, such as after DEEPSLEEP wakeup.  It is incompatible with clock supervision, because the frequency changes based on the lock signal.</description>
11873                  <value>0</value>
11874                </enumeratedValue>
11875                <enumeratedValue>
11876                  <name>LOCKED_OR_NOTHING</name>
11877                  <description>Similar to AUTO, except the clock is gated off when unlocked.  This is compatible with clock supervision, because the supervisors allow no clock during startup (until a timeout occurs), and the clock targets the proper frequency whenever it is running.</description>
11878                  <value>1</value>
11879                </enumeratedValue>
11880                <enumeratedValue>
11881                  <name>FLL_REF</name>
11882                  <description>Select FLL reference input (bypass mode).  Ignores lock indicator</description>
11883                  <value>2</value>
11884                </enumeratedValue>
11885                <enumeratedValue>
11886                  <name>FLL_OUT</name>
11887                  <description>Select FLL output.  Ignores lock indicator.</description>
11888                  <value>3</value>
11889                </enumeratedValue>
11890              </enumeratedValues>
11891            </field>
11892          </fields>
11893        </register>
11894        <register>
11895          <name>CLK_FLL_CONFIG4</name>
11896          <description>FLL Configuration Register 4</description>
11897          <addressOffset>0x153C</addressOffset>
11898          <size>32</size>
11899          <access>read-write</access>
11900          <resetValue>0xFF</resetValue>
11901          <resetMask>0xC1FF07FF</resetMask>
11902          <fields>
11903            <field>
11904              <name>CCO_LIMIT</name>
11905              <description>Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support)</description>
11906              <bitRange>[7:0]</bitRange>
11907              <access>read-write</access>
11908            </field>
11909            <field>
11910              <name>CCO_RANGE</name>
11911              <description>Frequency range of CCO</description>
11912              <bitRange>[10:8]</bitRange>
11913              <access>read-write</access>
11914              <enumeratedValues>
11915                <enumeratedValue>
11916                  <name>RANGE0</name>
11917                  <description>Target frequency is in range [48, 64) MHz</description>
11918                  <value>0</value>
11919                </enumeratedValue>
11920                <enumeratedValue>
11921                  <name>RANGE1</name>
11922                  <description>Target frequency is in range [64, 85) MHz</description>
11923                  <value>1</value>
11924                </enumeratedValue>
11925                <enumeratedValue>
11926                  <name>RANGE2</name>
11927                  <description>Target frequency is in range [85, 113) MHz</description>
11928                  <value>2</value>
11929                </enumeratedValue>
11930                <enumeratedValue>
11931                  <name>RANGE3</name>
11932                  <description>Target frequency is in range [113, 150) MHz</description>
11933                  <value>3</value>
11934                </enumeratedValue>
11935                <enumeratedValue>
11936                  <name>RANGE4</name>
11937                  <description>Target frequency is in range [150, 200] MHz</description>
11938                  <value>4</value>
11939                </enumeratedValue>
11940              </enumeratedValues>
11941            </field>
11942            <field>
11943              <name>CCO_FREQ</name>
11944              <description>CCO frequency code.  This is updated by HW when the FLL is enabled.  It can be manually updated to use the CCO in an open loop configuration.  The meaning of each frequency code depends on the range.</description>
11945              <bitRange>[24:16]</bitRange>
11946              <access>read-write</access>
11947            </field>
11948            <field>
11949              <name>CCO_HW_UPDATE_DIS</name>
11950              <description>Disable CCO frequency update by FLL hardware
119510: Hardware update of CCO settings is allowed.  Use this setting for normal FLL operation.
119521: Hardware update of CCO settings is disabled.  Use this setting for open-loop FLL operation.</description>
11953              <bitRange>[30:30]</bitRange>
11954              <access>read-write</access>
11955            </field>
11956            <field>
11957              <name>CCO_ENABLE</name>
11958              <description>Enable the CCO.  It is required to enable the CCO before using the FLL.
119590: Block is powered off
119601: Block is powered on</description>
11961              <bitRange>[31:31]</bitRange>
11962              <access>read-write</access>
11963            </field>
11964          </fields>
11965        </register>
11966        <register>
11967          <name>CLK_FLL_STATUS</name>
11968          <description>FLL Status Register</description>
11969          <addressOffset>0x1540</addressOffset>
11970          <size>32</size>
11971          <access>read-write</access>
11972          <resetValue>0x0</resetValue>
11973          <resetMask>0x7</resetMask>
11974          <fields>
11975            <field>
11976              <name>LOCKED</name>
11977              <description>FLL Lock Indicator</description>
11978              <bitRange>[0:0]</bitRange>
11979              <access>read-only</access>
11980            </field>
11981            <field>
11982              <name>UNLOCK_OCCURRED</name>
11983              <description>This bit sets whenever the FLL is enabled and goes out of lock.  This bit stays set until cleared by firmware.</description>
11984              <bitRange>[1:1]</bitRange>
11985              <access>read-write</access>
11986            </field>
11987            <field>
11988              <name>CCO_READY</name>
11989              <description>This indicates that the CCO is internally settled and ready to use.</description>
11990              <bitRange>[2:2]</bitRange>
11991              <access>read-only</access>
11992            </field>
11993          </fields>
11994        </register>
11995        <register>
11996          <name>CLK_ECO_CONFIG2</name>
11997          <description>ECO Configuration Register 2</description>
11998          <addressOffset>0x1544</addressOffset>
11999          <size>32</size>
12000          <access>read-write</access>
12001          <resetValue>0x3</resetValue>
12002          <resetMask>0x7FF7</resetMask>
12003          <fields>
12004            <field>
12005              <name>WDTRIM</name>
12006              <description>Watch Dog Trim.  Sets the minimum oscillation amplitude (Vp) for the crystal drive level.  The minimum amplitude detector output is readable in CLK_ECO_STATUS.ECO_OK.
120070x0: Vp &gt; 0.05V
120080x1: Vp &gt; 0.10V
120090x2: Vp &gt; 0.15V
120100x3: Vp &gt; 0.20V
120110x4: Vp &gt; 0.25V
120120x5: Vp &gt; 0.30V
120130x6: Vp &gt; 0.35V
120140x7: Vp &gt; 0.40V</description>
12015              <bitRange>[2:0]</bitRange>
12016              <access>read-write</access>
12017            </field>
12018            <field>
12019              <name>ATRIM</name>
12020              <description>Amplitude trim.  Sets maximum oscillation amplitude (Vp) to set the crystal drive level when ECO_CONFIG.AGC_EN=1.  When AGC_EN=0, most values of this register are unused, except as noted.  WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal.
120210x0: Vp &lt; 0.35V
120220x1: Vp &lt; 0.40V
120230x2: Vp &lt; 0.45V
120240x3: Vp &lt; 0.50V
120250x4: Vp &lt; 0.55V
120260x5: Vp &lt; 0.60V
120270x6: Vp &lt; 0.65V
120280x7: Vp &lt; 0.70V
120290x8: Vp &lt; 0.75V
120300x9: Vp &lt; 0.80V
120310xA: Vp &lt; 0.85V
120320xB: Vp &lt; 0.90V
120330xC: Vp &lt; 0.95V
120340xD: Vp &lt; 1.00V
120350xE: Vp &lt; 1.05V
120360xF: Vp &lt; 1.10V when AGC_EN=1.  When AGC_EN=0, this setting enables maximum swing between vddd and vssd.</description>
12037              <bitRange>[7:4]</bitRange>
12038              <access>read-write</access>
12039            </field>
12040            <field>
12041              <name>FTRIM</name>
12042              <description>Filter Trim - 3rd harmonic oscillation</description>
12043              <bitRange>[9:8]</bitRange>
12044              <access>read-write</access>
12045            </field>
12046            <field>
12047              <name>RTRIM</name>
12048              <description>Feedback resistor Trim</description>
12049              <bitRange>[11:10]</bitRange>
12050              <access>read-write</access>
12051            </field>
12052            <field>
12053              <name>GTRIM</name>
12054              <description>Gain Trim - Startup time.</description>
12055              <bitRange>[14:12]</bitRange>
12056              <access>read-write</access>
12057            </field>
12058          </fields>
12059        </register>
12060        <register>
12061          <dim>15</dim>
12062          <dimIncrement>4</dimIncrement>
12063          <name>CLK_PLL_CONFIG[%s]</name>
12064          <description>PLL Configuration Register</description>
12065          <addressOffset>0x1600</addressOffset>
12066          <size>32</size>
12067          <access>read-write</access>
12068          <resetValue>0x20116</resetValue>
12069          <resetMask>0xBE1F1F7F</resetMask>
12070          <fields>
12071            <field>
12072              <name>FEEDBACK_DIV</name>
12073              <description>Control bits for feedback divider.  Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
120740-21: illegal (undefined behavior)
1207522: divide by 22
12076...
12077112: divide by 112
12078&gt;112: illegal (undefined behavior)</description>
12079              <bitRange>[6:0]</bitRange>
12080              <access>read-write</access>
12081            </field>
12082            <field>
12083              <name>REFERENCE_DIV</name>
12084              <description>Control bits for reference divider.  Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
120850: illegal (undefined behavior)
120861: divide by 1
12087...
1208820: divide by 20
12089others: illegal (undefined behavior)</description>
12090              <bitRange>[12:8]</bitRange>
12091              <access>read-write</access>
12092            </field>
12093            <field>
12094              <name>OUTPUT_DIV</name>
12095              <description>Control bits for Output divider.  Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
120960: illegal (undefined behavior)
120971: illegal (undefined behavior)
120982: divide by 2.  Suitable for direct usage as HFCLK source.
12099...
1210016: divide by 16.  Suitable for direct usage as HFCLK source.
12101&gt;16: illegal (undefined behavior)</description>
12102              <bitRange>[20:16]</bitRange>
12103              <access>read-write</access>
12104            </field>
12105            <field>
12106              <name>LOCK_DELAY</name>
12107              <description>N/A</description>
12108              <bitRange>[26:25]</bitRange>
12109              <access>read-write</access>
12110            </field>
12111            <field>
12112              <name>PLL_LF_MODE</name>
12113              <description>VCO frequency range selection.  Configure this bit according to the targeted VCO frequency.  Do not change this setting while the PLL is enabled.
121140: VCO frequency is [200MHz, 400MHz]
121151: VCO frequency is [170MHz, 200MHz)</description>
12116              <bitRange>[27:27]</bitRange>
12117              <access>read-write</access>
12118            </field>
12119            <field>
12120              <name>BYPASS_SEL</name>
12121              <description>Bypass mux located just after PLL output.  This selection is glitch-free and can be changed while the PLL is running.  When changing BYPASS_SEL, do not turn off the reference clock or PLL clock for five cycles (whichever is slower).</description>
12122              <bitRange>[29:28]</bitRange>
12123              <access>read-write</access>
12124              <enumeratedValues>
12125                <enumeratedValue>
12126                  <name>AUTO</name>
12127                  <description>Automatic using lock indicator.  When unlocked, automatically selects PLL reference input (bypass mode).  When locked, automatically selects PLL output.  If ENABLE=0, automatically selects PLL reference input.</description>
12128                  <value>0</value>
12129                </enumeratedValue>
12130                <enumeratedValue>
12131                  <name>LOCKED_OR_NOTHING</name>
12132                  <description>Similar to AUTO, except the clock is gated off when unlocked.  This is compatible with clock supervision, because the supervisors allow no clock during startup (until a timeout occurs), and the clock targets the proper frequency whenever it is running.  If ENABLE=0, no clock is output.</description>
12133                  <value>1</value>
12134                </enumeratedValue>
12135                <enumeratedValue>
12136                  <name>PLL_REF</name>
12137                  <description>Select PLL reference input (bypass mode).  Ignores lock indicator</description>
12138                  <value>2</value>
12139                </enumeratedValue>
12140                <enumeratedValue>
12141                  <name>PLL_OUT</name>
12142                  <description>Select PLL output.  Ignores lock indicator.  If ENABLE=0, no clock is output.</description>
12143                  <value>3</value>
12144                </enumeratedValue>
12145              </enumeratedValues>
12146            </field>
12147            <field>
12148              <name>ENABLE</name>
12149              <description>Master enable for PLL.  Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1.
12150
12151Fpll = (FEEDBACK_DIV)  * (Fref / REFERENCE_DIV) / (OUTPUT_DIV)
12152
121530: Block is disabled.  When the PLL disables, hardware controls the bypass mux as described in BYPASS_SEL, before disabling the PLL circuit.
121541: Block is enabled</description>
12155              <bitRange>[31:31]</bitRange>
12156              <access>read-write</access>
12157            </field>
12158          </fields>
12159        </register>
12160        <register>
12161          <dim>15</dim>
12162          <dimIncrement>4</dimIncrement>
12163          <name>CLK_PLL_STATUS[%s]</name>
12164          <description>PLL Status Register</description>
12165          <addressOffset>0x1640</addressOffset>
12166          <size>32</size>
12167          <access>read-write</access>
12168          <resetValue>0x0</resetValue>
12169          <resetMask>0x3</resetMask>
12170          <fields>
12171            <field>
12172              <name>LOCKED</name>
12173              <description>PLL Lock Indicator</description>
12174              <bitRange>[0:0]</bitRange>
12175              <access>read-only</access>
12176            </field>
12177            <field>
12178              <name>UNLOCK_OCCURRED</name>
12179              <description>This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.</description>
12180              <bitRange>[1:1]</bitRange>
12181              <access>read-write</access>
12182            </field>
12183          </fields>
12184        </register>
12185        <register>
12186          <name>CSV_REF_SEL</name>
12187          <description>Select CSV Reference clock for Active domain</description>
12188          <addressOffset>0x1700</addressOffset>
12189          <size>32</size>
12190          <access>read-write</access>
12191          <resetValue>0x0</resetValue>
12192          <resetMask>0x7</resetMask>
12193          <fields>
12194            <field>
12195              <name>REF_MUX</name>
12196              <description>Selects a source for clock clk_ref_hf.  Note that not all products support all clock sources.  Selecting a clock source that is not supported will result in undefined behavior.   It takes four cycles of the originally selected clock to switch away from it.  Do not disable the original clock during this time.</description>
12197              <bitRange>[2:0]</bitRange>
12198              <access>read-write</access>
12199              <enumeratedValues>
12200                <enumeratedValue>
12201                  <name>IMO</name>
12202                  <description>IMO - Internal R/C Oscillator</description>
12203                  <value>0</value>
12204                </enumeratedValue>
12205                <enumeratedValue>
12206                  <name>EXTCLK</name>
12207                  <description>EXTCLK - External Clock Pin</description>
12208                  <value>1</value>
12209                </enumeratedValue>
12210                <enumeratedValue>
12211                  <name>ECO</name>
12212                  <description>ECO - External-Crystal Oscillator</description>
12213                  <value>2</value>
12214                </enumeratedValue>
12215                <enumeratedValue>
12216                  <name>ALTHF</name>
12217                  <description>ALTHF - Alternate High-Frequency clock input (product-specific clock)</description>
12218                  <value>3</value>
12219                </enumeratedValue>
12220              </enumeratedValues>
12221            </field>
12222          </fields>
12223        </register>
12224        <cluster>
12225          <name>CSV_REF</name>
12226          <description>CSV registers for the CSV Reference clock</description>
12227          <headerStructName>CSV_REF</headerStructName>
12228          <addressOffset>0x00001710</addressOffset>
12229          <cluster>
12230            <name>CSV</name>
12231            <description>Active domain Clock Supervisor (CSV) registers for CSV Reference clock</description>
12232            <headerStructName>CSV_REF_CSV</headerStructName>
12233            <addressOffset>0x00000000</addressOffset>
12234            <register>
12235              <name>REF_CTL</name>
12236              <description>Clock Supervision Reference Control</description>
12237              <addressOffset>0x0</addressOffset>
12238              <size>32</size>
12239              <access>read-write</access>
12240              <resetValue>0x0</resetValue>
12241              <resetMask>0xC000FFFF</resetMask>
12242              <fields>
12243                <field>
12244                  <name>STARTUP</name>
12245                  <description>Startup delay time -1 (in reference clock cycles), after enable or DeepSleep wakeup, from reference clock start to monitored clock start.
12246At a minimum (both clocks running): STARTUP &gt;= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency)
12247On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added.</description>
12248                  <bitRange>[15:0]</bitRange>
12249                  <access>read-write</access>
12250                </field>
12251                <field>
12252                  <name>CSV_ACTION</name>
12253                  <description>Specifies the action taken when an anomaly is detected on the monitored clock.  CSV in DeepSleep domain always do a Fault report (which also wakes up the system).</description>
12254                  <bitRange>[30:30]</bitRange>
12255                  <access>read-write</access>
12256                  <enumeratedValues>
12257                    <enumeratedValue>
12258                      <name>FAULT</name>
12259                      <description>Do a Fault report.</description>
12260                      <value>0</value>
12261                    </enumeratedValue>
12262                    <enumeratedValue>
12263                      <name>RESET</name>
12264                      <description>Cause a power reset. This should only be used for clk_hf0.</description>
12265                      <value>1</value>
12266                    </enumeratedValue>
12267                  </enumeratedValues>
12268                </field>
12269                <field>
12270                  <name>CSV_EN</name>
12271                  <description>Enables clock supervision, both frequency and loss.
12272CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes.  When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup.
12273CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode.  It must be reconfigured after Hibernate wakeup.
12274
12275A CSV error detection is reported to the Fault structure, or instead it can generate a power reset.</description>
12276                  <bitRange>[31:31]</bitRange>
12277                  <access>read-write</access>
12278                </field>
12279              </fields>
12280            </register>
12281            <register>
12282              <name>REF_LIMIT</name>
12283              <description>Clock Supervision Reference Limits</description>
12284              <addressOffset>0x4</addressOffset>
12285              <size>32</size>
12286              <access>read-write</access>
12287              <resetValue>0x0</resetValue>
12288              <resetMask>0xFFFFFFFF</resetMask>
12289              <fields>
12290                <field>
12291                  <name>LOWER</name>
12292                  <description>Cycle time lower limit.  Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen.  If a monitored clock event happens before this limit is reached a CSV error is detected.
12293LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER.</description>
12294                  <bitRange>[15:0]</bitRange>
12295                  <access>read-write</access>
12296                </field>
12297                <field>
12298                  <name>UPPER</name>
12299                  <description>Cycle time upper limit.  Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen.  If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected.</description>
12300                  <bitRange>[31:16]</bitRange>
12301                  <access>read-write</access>
12302                </field>
12303              </fields>
12304            </register>
12305            <register>
12306              <name>MON_CTL</name>
12307              <description>Clock Supervision Monitor Control</description>
12308              <addressOffset>0x8</addressOffset>
12309              <size>32</size>
12310              <access>read-write</access>
12311              <resetValue>0x0</resetValue>
12312              <resetMask>0xFFFF</resetMask>
12313              <fields>
12314                <field>
12315                  <name>PERIOD</name>
12316                  <description>Period time.  Set the Period -1, in monitored clock cycles, before the next monitored clock event happens.
12317PERIOD &lt;=  (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency)
12318In case the clocks are asynchronous: PERIOD &lt;=  UPPER / FREQ_RATIO -1
12319Additionally margin must be added for accuracy of both clocks.</description>
12320                  <bitRange>[15:0]</bitRange>
12321                  <access>read-write</access>
12322                </field>
12323              </fields>
12324            </register>
12325          </cluster>
12326        </cluster>
12327        <cluster>
12328          <name>CSV_LF</name>
12329          <description>CSV registers for LF clock</description>
12330          <headerStructName>CSV_LF</headerStructName>
12331          <addressOffset>0x00001720</addressOffset>
12332          <cluster>
12333            <name>CSV</name>
12334            <description>LF clock Clock Supervisor registers</description>
12335            <headerStructName>CSV_LF_CSV</headerStructName>
12336            <addressOffset>0x00000000</addressOffset>
12337            <register>
12338              <name>REF_CTL</name>
12339              <description>Clock Supervision Reference Control</description>
12340              <addressOffset>0x0</addressOffset>
12341              <size>32</size>
12342              <access>read-write</access>
12343              <resetValue>0x0</resetValue>
12344              <resetMask>0x800000FF</resetMask>
12345              <fields>
12346                <field>
12347                  <name>STARTUP</name>
12348                  <description>Startup delay time -1 (in reference clock cycles), after enable, from reference clock start to monitored clock start.
12349At a minimum (both clocks running): STARTUP &gt;= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency)
12350On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added.</description>
12351                  <bitRange>[7:0]</bitRange>
12352                  <access>read-write</access>
12353                </field>
12354                <field>
12355                  <name>CSV_EN</name>
12356                  <description>Enables clock supervision, both frequency and loss.
12357CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes.  When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup.
12358CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode.  It must be reconfigured after Hibernate wakeup.
12359CSV in Backup domain: Clock supervision operates during Hibernate mode, can be configured to wake from Hibernate, and continues operating during reboot.
12360
12361A CSV error detection is reported to the Fault structure.</description>
12362                  <bitRange>[31:31]</bitRange>
12363                  <access>read-write</access>
12364                </field>
12365              </fields>
12366            </register>
12367            <register>
12368              <name>REF_LIMIT</name>
12369              <description>Clock Supervision Reference Limits</description>
12370              <addressOffset>0x4</addressOffset>
12371              <size>32</size>
12372              <access>read-write</access>
12373              <resetValue>0x0</resetValue>
12374              <resetMask>0xFF00FF</resetMask>
12375              <fields>
12376                <field>
12377                  <name>LOWER</name>
12378                  <description>Cycle time lower limit.  Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen.  If a monitored clock event happens before this limit is reached a CSV error is detected.
12379LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER.</description>
12380                  <bitRange>[7:0]</bitRange>
12381                  <access>read-write</access>
12382                </field>
12383                <field>
12384                  <name>UPPER</name>
12385                  <description>Cycle time upper limit.  Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen.  If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected.</description>
12386                  <bitRange>[23:16]</bitRange>
12387                  <access>read-write</access>
12388                </field>
12389              </fields>
12390            </register>
12391            <register>
12392              <name>MON_CTL</name>
12393              <description>Clock Supervision Monitor Control</description>
12394              <addressOffset>0x8</addressOffset>
12395              <size>32</size>
12396              <access>read-write</access>
12397              <resetValue>0x0</resetValue>
12398              <resetMask>0xFF</resetMask>
12399              <fields>
12400                <field>
12401                  <name>PERIOD</name>
12402                  <description>Period time.  Set the Period -1, in monitored clock cycles, before the next monitored clock event happens.
12403PERIOD &lt;=  (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency)
12404In case the clocks are asynchronous: PERIOD &lt;=  UPPER / FREQ_RATIO -1
12405Additionally margin must be added for accuracy of both clocks.</description>
12406                  <bitRange>[7:0]</bitRange>
12407                  <access>read-write</access>
12408                </field>
12409              </fields>
12410            </register>
12411          </cluster>
12412        </cluster>
12413        <cluster>
12414          <name>CSV_ILO</name>
12415          <description>CSV registers for HVILO clock</description>
12416          <headerStructName>CSV_ILO</headerStructName>
12417          <addressOffset>0x00001730</addressOffset>
12418          <cluster>
12419            <name>CSV</name>
12420            <description>ILO0 clock DeepSleep domain Clock Supervisor registers</description>
12421            <headerStructName>CSV_ILO_CSV</headerStructName>
12422            <addressOffset>0x00000000</addressOffset>
12423            <register>
12424              <name>REF_CTL</name>
12425              <description>Clock Supervision Reference Control</description>
12426              <addressOffset>0x0</addressOffset>
12427              <size>32</size>
12428              <access>read-write</access>
12429              <resetValue>0x0</resetValue>
12430              <resetMask>0x800000FF</resetMask>
12431              <fields>
12432                <field>
12433                  <name>STARTUP</name>
12434                  <description>Startup delay time -1 (in reference clock cycles), after enable, from reference clock start to monitored clock start.
12435At a minimum (both clocks running): STARTUP &gt;= (PERIOD +3) * FREQ_RATIO - UPPER, with FREQ_RATIO = (Reference frequency / Monitored frequency)
12436On top of that the actual clock startup delay and the margin for accuracy of both clocks must be added.</description>
12437                  <bitRange>[7:0]</bitRange>
12438                  <access>read-write</access>
12439                </field>
12440                <field>
12441                  <name>CSV_EN</name>
12442                  <description>Enables clock supervision, both frequency and loss.
12443CSV in Active domain: Clock supervision is reset during DeepSleep and Hibernate modes.  When enabled it begins operating automatically after a DeepSleep wakeup, but it must be reconfigured after Hibernate wakeup.
12444CSV in DeepSleep domain: Clock supervision is reset during Hibernate mode.  It must be reconfigured after Hibernate wakeup.
12445CSV in Backup domain: Clock supervision operates during Hibernate mode, can be configured to wake from Hibernate, and continues operating during reboot.
12446
12447A CSV error detection is reported to the Fault structure.</description>
12448                  <bitRange>[31:31]</bitRange>
12449                  <access>read-write</access>
12450                </field>
12451              </fields>
12452            </register>
12453            <register>
12454              <name>REF_LIMIT</name>
12455              <description>Clock Supervision Reference Limits</description>
12456              <addressOffset>0x4</addressOffset>
12457              <size>32</size>
12458              <access>read-write</access>
12459              <resetValue>0x0</resetValue>
12460              <resetMask>0xFF00FF</resetMask>
12461              <fields>
12462                <field>
12463                  <name>LOWER</name>
12464                  <description>Cycle time lower limit.  Set the lower limit -1, in reference clock cycles, before the next monitored clock event is allowed to happen.  If a monitored clock event happens before this limit is reached a CSV error is detected.
12465LOWER must be at least 1 less than UPPER. In case the clocks are asynchronous LOWER must be at least 3 less than UPPER.</description>
12466                  <bitRange>[7:0]</bitRange>
12467                  <access>read-write</access>
12468                </field>
12469                <field>
12470                  <name>UPPER</name>
12471                  <description>Cycle time upper limit.  Set the upper limit -1, in reference clock cycles, before (or same time) the next monitored clock event must happen.  If a monitored clock event does not happen before this limit is reached, or does not happen at all (clock loss), a CSV error is detected.</description>
12472                  <bitRange>[23:16]</bitRange>
12473                  <access>read-write</access>
12474                </field>
12475              </fields>
12476            </register>
12477            <register>
12478              <name>MON_CTL</name>
12479              <description>Clock Supervision Monitor Control</description>
12480              <addressOffset>0x8</addressOffset>
12481              <size>32</size>
12482              <access>read-write</access>
12483              <resetValue>0x0</resetValue>
12484              <resetMask>0xFF</resetMask>
12485              <fields>
12486                <field>
12487                  <name>PERIOD</name>
12488                  <description>Period time.  Set the Period -1, in monitored clock cycles, before the next monitored clock event happens.
12489PERIOD &lt;=  (UPPER+1) / FREQ_RATIO -1, with FREQ_RATIO = (Reference frequency / Monitored frequency)
12490In case the clocks are asynchronous: PERIOD &lt;=  UPPER / FREQ_RATIO -1
12491Additionally margin must be added for accuracy of both clocks.</description>
12492                  <bitRange>[7:0]</bitRange>
12493                  <access>read-write</access>
12494                </field>
12495              </fields>
12496            </register>
12497          </cluster>
12498        </cluster>
12499        <register>
12500          <name>RES_CAUSE</name>
12501          <description>Reset Cause Observation Register</description>
12502          <addressOffset>0x1800</addressOffset>
12503          <size>32</size>
12504          <access>read-write</access>
12505          <resetValue>0x40000000</resetValue>
12506          <resetMask>0x71FF01FF</resetMask>
12507          <fields>
12508            <field>
12509              <name>RESET_WDT</name>
12510              <description>A basic WatchDog Timer (WDT) reset has occurred since last power cycle.  ULP products: This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).
12511
12512For products that support high-voltage cause detection, this bit blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.  This bit is not blocked by other HV cause bits.</description>
12513              <bitRange>[0:0]</bitRange>
12514              <access>read-write</access>
12515            </field>
12516            <field>
12517              <name>RESET_ACT_FAULT</name>
12518              <description>Fault logging system requested a reset from its Active logic.  This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).</description>
12519              <bitRange>[1:1]</bitRange>
12520              <access>read-write</access>
12521            </field>
12522            <field>
12523              <name>RESET_DPSLP_FAULT</name>
12524              <description>Fault logging system requested a reset from its DeepSleep logic.  This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).</description>
12525              <bitRange>[2:2]</bitRange>
12526              <access>read-write</access>
12527            </field>
12528            <field>
12529              <name>RESET_TC_DBGRESET</name>
12530              <description>Test controller or debugger asserted reset. Only resets debug domain.  This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).</description>
12531              <bitRange>[3:3]</bitRange>
12532              <access>read-write</access>
12533            </field>
12534            <field>
12535              <name>RESET_SOFT</name>
12536              <description>A CPU requested a system reset through it's SYSRESETREQ.  This can be done via a debugger probe or in firmware.  This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).</description>
12537              <bitRange>[4:4]</bitRange>
12538              <access>read-write</access>
12539            </field>
12540            <field>
12541              <name>RESET_MCWDT0</name>
12542              <description>Multi-Counter Watchdog timer reset #0.  This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).</description>
12543              <bitRange>[5:5]</bitRange>
12544              <access>read-write</access>
12545            </field>
12546            <field>
12547              <name>RESET_MCWDT1</name>
12548              <description>Multi-Counter Watchdog timer reset #1.  This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).</description>
12549              <bitRange>[6:6]</bitRange>
12550              <access>read-write</access>
12551            </field>
12552            <field>
12553              <name>RESET_MCWDT2</name>
12554              <description>Multi-Counter Watchdog timer reset #2.  This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).</description>
12555              <bitRange>[7:7]</bitRange>
12556              <access>read-write</access>
12557            </field>
12558            <field>
12559              <name>RESET_MCWDT3</name>
12560              <description>Multi-Counter Watchdog timer reset #3.  This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).</description>
12561              <bitRange>[8:8]</bitRange>
12562              <access>read-write</access>
12563            </field>
12564            <field>
12565              <name>RESET_XRES</name>
12566              <description>External XRES pin was asserted.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.  This bit is not blocked by other HV cause bits.</description>
12567              <bitRange>[16:16]</bitRange>
12568              <access>read-write</access>
12569            </field>
12570            <field>
12571              <name>RESET_BODVDDD</name>
12572              <description>External VDDD supply crossed brown-out limit.  Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit.  Below this limit it is not possible to reliably retain information in the device.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
12573              <bitRange>[17:17]</bitRange>
12574              <access>read-write</access>
12575            </field>
12576            <field>
12577              <name>RESET_BODVDDA</name>
12578              <description>External VDDA supply crossed the brown-out limit.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
12579              <bitRange>[18:18]</bitRange>
12580              <access>read-write</access>
12581            </field>
12582            <field>
12583              <name>RESET_BODVCCD</name>
12584              <description>Internal VCCD core supply crossed the brown-out limit.  Note that this detector will detect gross issues with the internal core supply, but may not catch all brown-out conditions.  Functional and timing supervision (CSV, WDT) is provided to create fully failsafe internal crash detection.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
12585              <bitRange>[19:19]</bitRange>
12586              <access>read-write</access>
12587            </field>
12588            <field>
12589              <name>RESET_OVDVDDD</name>
12590              <description>Overvoltage detection on the external VDDD supply.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
12591              <bitRange>[20:20]</bitRange>
12592              <access>read-write</access>
12593            </field>
12594            <field>
12595              <name>RESET_OVDVDDA</name>
12596              <description>Overvoltage detection on the external VDDA supply.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
12597              <bitRange>[21:21]</bitRange>
12598              <access>read-write</access>
12599            </field>
12600            <field>
12601              <name>RESET_OVDVCCD</name>
12602              <description>Overvoltage detection on the internal core VCCD supply.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
12603              <bitRange>[22:22]</bitRange>
12604              <access>read-write</access>
12605            </field>
12606            <field>
12607              <name>RESET_OCD_ACT_LINREG</name>
12608              <description>Overcurrent detection on the internal VCCD supply when supplied by the ACTIVE power mode linear regulator.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
12609              <bitRange>[23:23]</bitRange>
12610              <access>read-write</access>
12611            </field>
12612            <field>
12613              <name>RESET_OCD_DPSLP_LINREG</name>
12614              <description>Overcurrent detection on the internal VCCD supply when supplied by the DEEPSLEEP power mode linear regulator.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.</description>
12615              <bitRange>[24:24]</bitRange>
12616              <access>read-write</access>
12617            </field>
12618            <field>
12619              <name>RESET_PXRES</name>
12620              <description>PXRES triggered.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.  This bit is not blocked by other HV cause bits.</description>
12621              <bitRange>[28:28]</bitRange>
12622              <access>read-write</access>
12623            </field>
12624            <field>
12625              <name>RESET_STRUCT_XRES</name>
12626              <description>Structural reset was asserted.  This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD.  Hardware clears this bit during POR.  This bit is not blocked by other HV cause bits.</description>
12627              <bitRange>[29:29]</bitRange>
12628              <access>read-write</access>
12629            </field>
12630            <field>
12631              <name>RESET_PORVDDD</name>
12632              <description>Indicator that a POR occurred.  This is a high-voltage cause bit, and hardware clears the other bits when this one is set.  It does not block further recording of other high-voltage causes.</description>
12633              <bitRange>[30:30]</bitRange>
12634              <access>read-write</access>
12635            </field>
12636          </fields>
12637        </register>
12638        <register>
12639          <name>RES_CAUSE2</name>
12640          <description>Reset Cause Observation Register 2</description>
12641          <addressOffset>0x1804</addressOffset>
12642          <size>32</size>
12643          <access>read-write</access>
12644          <resetValue>0x0</resetValue>
12645          <resetMask>0x1FFFF</resetMask>
12646          <fields>
12647            <field>
12648              <name>RESET_CSV_HF</name>
12649              <description>Clock supervision logic requested a reset due to loss or frequency violation of a high-frequency clock.  Each bit index K corresponds to a HFCLK&lt;K&gt;.  Unimplemented clock bits return zero.</description>
12650              <bitRange>[15:0]</bitRange>
12651              <access>read-write</access>
12652            </field>
12653            <field>
12654              <name>RESET_CSV_REF</name>
12655              <description>Clock supervision logic requested a reset due to loss or frequency violation of the reference clock source that is used to monitor the other HF clock sources.</description>
12656              <bitRange>[16:16]</bitRange>
12657              <access>read-write</access>
12658            </field>
12659          </fields>
12660        </register>
12661        <register>
12662          <name>CLK_TRIM_ILO0_CTL</name>
12663          <description>ILO0 Trim Register</description>
12664          <addressOffset>0x3014</addressOffset>
12665          <size>32</size>
12666          <access>read-write</access>
12667          <resetValue>0x52C</resetValue>
12668          <resetMask>0xF3F</resetMask>
12669          <fields>
12670            <field>
12671              <name>ILO0_FTRIM</name>
12672              <description>ILO0 frequency trims.  LSB step size is 1.5 percent (typical) of the frequency.</description>
12673              <bitRange>[5:0]</bitRange>
12674              <access>read-write</access>
12675            </field>
12676            <field>
12677              <name>ILO0_MONTRIM</name>
12678              <description>ILO0 internal monitor trim.</description>
12679              <bitRange>[11:8]</bitRange>
12680              <access>read-write</access>
12681            </field>
12682          </fields>
12683        </register>
12684        <register>
12685          <name>PWR_TRIM_PWRSYS_CTL</name>
12686          <description>Power System Trim Register</description>
12687          <addressOffset>0x3108</addressOffset>
12688          <size>32</size>
12689          <access>read-write</access>
12690          <resetValue>0x17</resetValue>
12691          <resetMask>0x1F</resetMask>
12692          <fields>
12693            <field>
12694              <name>ACT_REG_TRIM</name>
12695              <description>Trim for the Active-Regulator.  This sets the output voltage level.  This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.  The nominal output voltage is vccd=812.5mV + ACT_REG_TRIM*12.5mV.  The actual output voltage will vary depending on conditions and load.  The following settings are explicitly shown for convenience, and other values may be calculated using the formula:
126965'h07: 900mV (nominal)
126975'h17: 1100mV (nominal)</description>
12698              <bitRange>[4:0]</bitRange>
12699              <access>read-write</access>
12700            </field>
12701            <field>
12702              <name>ACT_REG_BOOST</name>
12703              <description>Controls the tradeoff between output current and internal operating current for the Active Regulator.  The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that.  This may allow a reduction in the internal operating current of the regulator.  The regulator internal operating current depends on the boost setting:
127042'b00: 50uA
127052'b01: 100uA
127062'b10: 150uA
127072'b11: 200uA
12708
12709The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer).  The defaults are set assuming the application consumes the maximum allowed by the chip.
1271050mA chip: 2'b00 (default);
12711100mA chip: 2'b00 (default);
12712150mA chip: 50..100mA app =&gt; 2'b00, 150mA app =&gt; 2'b01 (default);
12713200mA chip: 50mA app =&gt; 2'b00, 100..150mA app =&gt; 2'b01,  200mA app =&gt; 2'b10 (default);
12714250mA chip: 50mA app =&gt; 2'b00, 100..150mA app =&gt; 2'b01,  200..250mA app =&gt; 2'b10 (default);
12715300mA chip: 50mA app =&gt; 2'b00, 100..150mA app =&gt; 2'b01, 200..250mA app =&gt; 2'b10, 300mA app =&gt; 2'b11 (default);
12716
12717This register is only reset by XRES, HIBERNATE wakeup, or supply supervision reset.</description>
12718              <bitRange>[31:30]</bitRange>
12719              <access>read-write</access>
12720            </field>
12721          </fields>
12722        </register>
12723        <register>
12724          <name>CLK_TRIM_PILO_CTL</name>
12725          <description>PILO Trim Register</description>
12726          <addressOffset>0x3114</addressOffset>
12727          <size>32</size>
12728          <access>read-write</access>
12729          <resetValue>0x108500F</resetValue>
12730          <resetMask>0x7DFF703F</resetMask>
12731          <fields>
12732            <field>
12733              <name>PILO_CFREQ</name>
12734              <description>Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration.  The nominal step size of the LSB is 1kHz.</description>
12735              <bitRange>[5:0]</bitRange>
12736              <access>read-write</access>
12737            </field>
12738            <field>
12739              <name>PILO_OSC_TRIM</name>
12740              <description>Trim for current in oscillator block.</description>
12741              <bitRange>[14:12]</bitRange>
12742              <access>read-write</access>
12743            </field>
12744            <field>
12745              <name>PILO_COMP_TRIM</name>
12746              <description>Trim for comparator bias current.</description>
12747              <bitRange>[17:16]</bitRange>
12748              <access>read-write</access>
12749            </field>
12750            <field>
12751              <name>PILO_NBIAS_TRIM</name>
12752              <description>Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier</description>
12753              <bitRange>[19:18]</bitRange>
12754              <access>read-write</access>
12755            </field>
12756            <field>
12757              <name>PILO_RES_TRIM</name>
12758              <description>Trim for beta-multiplier branch current</description>
12759              <bitRange>[24:20]</bitRange>
12760              <access>read-write</access>
12761            </field>
12762            <field>
12763              <name>PILO_ISLOPE_TRIM</name>
12764              <description>Trim for beta-multiplier current slope</description>
12765              <bitRange>[27:26]</bitRange>
12766              <access>read-write</access>
12767            </field>
12768            <field>
12769              <name>PILO_VTDIFF_TRIM</name>
12770              <description>Trim for VT-DIFF output (internal power supply)</description>
12771              <bitRange>[30:28]</bitRange>
12772              <access>read-write</access>
12773            </field>
12774          </fields>
12775        </register>
12776        <register>
12777          <name>CLK_TRIM_PILO_CTL2</name>
12778          <description>PILO Trim Register 2</description>
12779          <addressOffset>0x3118</addressOffset>
12780          <size>32</size>
12781          <access>read-write</access>
12782          <resetValue>0xDA10E0</resetValue>
12783          <resetMask>0xFF1FFF</resetMask>
12784          <fields>
12785            <field>
12786              <name>PILO_VREF_TRIM</name>
12787              <description>Trim for voltage reference</description>
12788              <bitRange>[7:0]</bitRange>
12789              <access>read-write</access>
12790            </field>
12791            <field>
12792              <name>PILO_IREFBM_TRIM</name>
12793              <description>Trim for beta-multiplier current reference</description>
12794              <bitRange>[12:8]</bitRange>
12795              <access>read-write</access>
12796            </field>
12797            <field>
12798              <name>PILO_IREF_TRIM</name>
12799              <description>Trim for current reference</description>
12800              <bitRange>[23:16]</bitRange>
12801              <access>read-write</access>
12802            </field>
12803          </fields>
12804        </register>
12805        <register>
12806          <name>CLK_TRIM_PILO_CTL3</name>
12807          <description>PILO Trim Register 3</description>
12808          <addressOffset>0x311C</addressOffset>
12809          <size>32</size>
12810          <access>read-write</access>
12811          <resetValue>0x4800</resetValue>
12812          <resetMask>0xFFFF</resetMask>
12813          <fields>
12814            <field>
12815              <name>PILO_ENGOPT</name>
12816              <description>Engineering options for PILO circuits
128170: Short vdda to vpwr
128181: Beta:mult current change
128192: Iref generation Ptat current addition
128203: Disable current path in secondary Beta:mult startup circuit
128214: Double oscillator current
128225: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block
128236: Spare
128247: Ptat component increase in Iref
128258: vpwr_rc and vpwr_dig_rc shorting testmode
128269: Switch b/w psub connection for cascode nfet for vref generation
1282710: Switch between sub:threshold and deep:sub:threshold stacks in comparator.
1282815-11: Frequency fine trim.  See AKK-444 for an overview of the trim strategy.</description>
12829              <bitRange>[15:0]</bitRange>
12830              <access>read-write</access>
12831            </field>
12832          </fields>
12833        </register>
12834        <register>
12835          <name>CLK_TRIM_ILO1_CTL</name>
12836          <description>ILO1 Trim Register</description>
12837          <addressOffset>0x3220</addressOffset>
12838          <size>32</size>
12839          <access>read-write</access>
12840          <resetValue>0x52C</resetValue>
12841          <resetMask>0xF3F</resetMask>
12842          <fields>
12843            <field>
12844              <name>ILO1_FTRIM</name>
12845              <description>ILO1 frequency trims.  LSB step size is 1.5 percent (typical) of the frequency.</description>
12846              <bitRange>[5:0]</bitRange>
12847              <access>read-write</access>
12848            </field>
12849            <field>
12850              <name>ILO1_MONTRIM</name>
12851              <description>ILO1 internal monitor trim.</description>
12852              <bitRange>[11:8]</bitRange>
12853              <access>read-write</access>
12854            </field>
12855          </fields>
12856        </register>
12857        <cluster>
12858          <dim>2</dim>
12859          <dimIncrement>256</dimIncrement>
12860          <name>MCWDT[%s]</name>
12861          <description>Multi-Counter Watchdog Timer</description>
12862          <headerStructName>MCWDT</headerStructName>
12863          <addressOffset>0x00008000</addressOffset>
12864          <cluster>
12865            <dim>2</dim>
12866            <dimIncrement>32</dimIncrement>
12867            <name>CTR[%s]</name>
12868            <description>MCWDT Configuration for Subcounter 0 and 1</description>
12869            <headerStructName>MCWDT_CTR</headerStructName>
12870            <addressOffset>0x00000000</addressOffset>
12871            <register>
12872              <name>CTL</name>
12873              <description>MCWDT Subcounter Control Register</description>
12874              <addressOffset>0x0</addressOffset>
12875              <size>32</size>
12876              <access>read-write</access>
12877              <resetValue>0x0</resetValue>
12878              <resetMask>0x80000001</resetMask>
12879              <fields>
12880                <field>
12881                  <name>ENABLED</name>
12882                  <description>Indicates actual state of this subcounter.  May lag ENABLE by up to two clk_lf cycles.</description>
12883                  <bitRange>[0:0]</bitRange>
12884                  <access>read-only</access>
12885                </field>
12886                <field>
12887                  <name>ENABLE</name>
12888                  <description>Enable subcounter.  May take up to 2 clk_lf cycles to take effect.  When ENABLE changes from 1-&gt;0, the counter is cleared.
128890: Counter is disabled (not clocked)
128901: Counter is enabled (counting up)</description>
12891                  <bitRange>[31:31]</bitRange>
12892                  <access>read-write</access>
12893                </field>
12894              </fields>
12895            </register>
12896            <register>
12897              <name>LOWER_LIMIT</name>
12898              <description>MCWDT Subcounter Lower Limit Register</description>
12899              <addressOffset>0x4</addressOffset>
12900              <size>32</size>
12901              <access>read-write</access>
12902              <resetValue>0x0</resetValue>
12903              <resetMask>0xFFFF</resetMask>
12904              <fields>
12905                <field>
12906                  <name>LOWER_LIMIT</name>
12907                  <description>Lower limit for this MCWDT subcounter.  See LOWER_ACTION.</description>
12908                  <bitRange>[15:0]</bitRange>
12909                  <access>read-write</access>
12910                </field>
12911              </fields>
12912            </register>
12913            <register>
12914              <name>UPPER_LIMIT</name>
12915              <description>MCWDT Subcounter Upper Limit Register</description>
12916              <addressOffset>0x8</addressOffset>
12917              <size>32</size>
12918              <access>read-write</access>
12919              <resetValue>0x0</resetValue>
12920              <resetMask>0xFFFF</resetMask>
12921              <fields>
12922                <field>
12923                  <name>UPPER_LIMIT</name>
12924                  <description>Upper limit for this MCWDT subcounter.  See UPPER_ACTION.</description>
12925                  <bitRange>[15:0]</bitRange>
12926                  <access>read-write</access>
12927                </field>
12928              </fields>
12929            </register>
12930            <register>
12931              <name>WARN_LIMIT</name>
12932              <description>MCWDT Subcounter Warn Limit Register</description>
12933              <addressOffset>0xC</addressOffset>
12934              <size>32</size>
12935              <access>read-write</access>
12936              <resetValue>0x0</resetValue>
12937              <resetMask>0xFFFF</resetMask>
12938              <fields>
12939                <field>
12940                  <name>WARN_LIMIT</name>
12941                  <description>Warn limit for this MCWDT subcounter.  See WARN_ACTION.</description>
12942                  <bitRange>[15:0]</bitRange>
12943                  <access>read-write</access>
12944                </field>
12945              </fields>
12946            </register>
12947            <register>
12948              <name>CONFIG</name>
12949              <description>MCWDT Subcounter Configuration Register</description>
12950              <addressOffset>0x10</addressOffset>
12951              <size>32</size>
12952              <access>read-write</access>
12953              <resetValue>0x0</resetValue>
12954              <resetMask>0xD0001133</resetMask>
12955              <fields>
12956                <field>
12957                  <name>LOWER_ACTION</name>
12958                  <description>Action taken if this watchdog is serviced before LOWER_LIMIT is reached.  LOWER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected and/or when the corresponding processor is in SLEEPDEEP.</description>
12959                  <bitRange>[1:0]</bitRange>
12960                  <access>read-write</access>
12961                  <enumeratedValues>
12962                    <enumeratedValue>
12963                      <name>NOTHING</name>
12964                      <description>Do nothing</description>
12965                      <value>0</value>
12966                    </enumeratedValue>
12967                    <enumeratedValue>
12968                      <name>FAULT</name>
12969                      <description>Trigger a fault.  It can take up to 3 clk_lf cycles for the fault to be transferred to the fault manager.
12970For LOWER_LIMIT &gt;= 1: The action is triggered on same edge when it meets this condition.
12971For LOWER_LIMIT == 0: No action is triggered.</description>
12972                      <value>1</value>
12973                    </enumeratedValue>
12974                    <enumeratedValue>
12975                      <name>FAULT_THEN_RESET</name>
12976                      <description>Trigger a fault.  Further, trigger a system-wide reset if the fault is not serviced and the watchdog is not cleared within 6 clk_lf cycles.  It can take up to 3 clk_lf cycles for the fault to be transferred to the fault manager, which gives at least 3 clk_lf cycles for software to respond.
12977For LOWER_LIMIT &gt;= 1: The action is triggered on same edge when it meets this condition.
12978For LOWER_LIMIT == 0: No action is triggered.</description>
12979                      <value>2</value>
12980                    </enumeratedValue>
12981                  </enumeratedValues>
12982                </field>
12983                <field>
12984                  <name>UPPER_ACTION</name>
12985                  <description>Action taken if this watchdog is not serviced before UPPER_LIMIT is reached.  The counter stops counting when UPPER_LIMIT is reached, regardless of UPPER_ACTION setting.  UPPER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected.</description>
12986                  <bitRange>[5:4]</bitRange>
12987                  <access>read-write</access>
12988                  <enumeratedValues>
12989                    <enumeratedValue>
12990                      <name>NOTHING</name>
12991                      <description>Do nothing</description>
12992                      <value>0</value>
12993                    </enumeratedValue>
12994                    <enumeratedValue>
12995                      <name>FAULT</name>
12996                      <description>Trigger a fault.
12997For UPPER_LIMIT &gt;= 2: The action is triggered on same edge when it meets this condition.
12998For UPPER_LIMIT &lt; 2: The action may take up to one extra clk_lf cycle to trigger.</description>
12999                      <value>1</value>
13000                    </enumeratedValue>
13001                    <enumeratedValue>
13002                      <name>FAULT_THEN_RESET</name>
13003                      <description>Trigger a fault.  Further, trigger a system-wide reset if the fault is not serviced and the watchdog is not cleared within 6 clk_lf cycles.  It can take up to 3 clk_lf cycles for the fault to be transferred to the fault manager, which gives at least 3 clk_lf cycles for software to respond.
13004For UPPER_LIMIT &gt;= 2: The action is triggered on same edge when it meets this condition.
13005For UPPER_LIMIT &lt; 2: The action may take up to one extra clk_lf cycle to trigger.</description>
13006                      <value>2</value>
13007                    </enumeratedValue>
13008                  </enumeratedValues>
13009                </field>
13010                <field>
13011                  <name>WARN_ACTION</name>
13012                  <description>Action taken when the count value reaches WARN_LIMIT.  The minimum setting to achieve a periodic interrupt is WARN_LIMIT==1.  A setting of zero will trigger once but not periodically.
13013For WARN_LIMIT &gt;= 2: The action is triggered on same edge when it meets this condition.
13014For WARN_LIMIT == [0,1]  : The action may take up to one extra clk_lf cycle to trigger.</description>
13015                  <bitRange>[8:8]</bitRange>
13016                  <access>read-write</access>
13017                  <enumeratedValues>
13018                    <enumeratedValue>
13019                      <name>NOTHING</name>
13020                      <description>Do nothing</description>
13021                      <value>0</value>
13022                    </enumeratedValue>
13023                    <enumeratedValue>
13024                      <name>INT</name>
13025                      <description>Trigger an interrupt.</description>
13026                      <value>1</value>
13027                    </enumeratedValue>
13028                  </enumeratedValues>
13029                </field>
13030                <field>
13031                  <name>AUTO_SERVICE</name>
13032                  <description>Automatically service when the count value reaches WARN_LIMIT.  This allows creation of a periodic interrupt if this counter is not needed as a watchdog.  This field is ignored when LOWER_ACTION&lt;&gt;NOTHING or when UPPER_ACTION&lt;&gt;NOTHING.</description>
13033                  <bitRange>[12:12]</bitRange>
13034                  <access>read-write</access>
13035                </field>
13036                <field>
13037                  <name>DEBUG_TRIGGER_EN</name>
13038                  <description>Enables the trigger input for this MCWDT to pause the counter during debug mode.  To pause at a breakpoint while debugging, configure the trigger matrix to connect the related CPU halted signal to the trigger input for this MCWDT, and then set this bit.  It takes up to two clk_lf cycles for the trigger signal to be processed.  Triggers that are less than two clk_lf cycles may be missed.  Synchronization errors can accumulate each time it is halted.
130390: Pauses the counter whenever a debug probe is connected.
130401: Pauses the counter whenever a debug probe is connected and the trigger input is high.</description>
13041                  <bitRange>[28:28]</bitRange>
13042                  <access>read-write</access>
13043                </field>
13044                <field>
13045                  <name>SLEEPDEEP_PAUSE</name>
13046                  <description>Pauses/runs this counter when the corresponding processor is in SLEEPDEEP.  Note it may take up to two clk_lf cycles for the counter to pause and up to two clk_lf cycles for it to unpause, due to internal synchronization.  After wakeup, the LOWER_ACTION is ignored until after the first service.  This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period.  After the first service, LOWER_ACTION behaves as configured.
130470: Counter runs normally regardless of processor mode.
130481: Counter pauses when corresponding processor is in SLEEPDEEP.</description>
13049                  <bitRange>[30:30]</bitRange>
13050                  <access>read-write</access>
13051                </field>
13052                <field>
13053                  <name>DEBUG_RUN</name>
13054                  <description>Pauses/runs this counter while a debugger is connected.  Other behaviors are unchanged during debugging, including service, configuration updates and enable/disable.  Note it may take up to two clk_lf cycles for the counter to pause, due to internal synchronization.
13055
13056When (DEBUG_RUN==1 or DEBUG_TRIGGER_EN==0) and the debugger is connected for at least two clk_lf cycles, the LOWER_ACTION is ignored until after the first service after the debugger is disconnected.  After the debugger is disconnected, the LOWER_ACTION is ignored until after the first service.  This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period.  After the first service, LOWER_ACTION behaves as configured.  If the debugger is disconnected before two clk_lf cycles, the LOWER_ACTION may or may not be ignored.
13057
130580: When debugger connected, counter pauses incrementing as configured in DEBUG_TRIGGER_EN.
130591: When debugger connected, counter increments normally, but reset generation is blocked.  To block LOWER_ACTION fault generation, write DEBUG_TRIGGER_EN==0.</description>
13060                  <bitRange>[31:31]</bitRange>
13061                  <access>read-write</access>
13062                </field>
13063              </fields>
13064            </register>
13065            <register>
13066              <name>CNT</name>
13067              <description>MCWDT Subcounter Count Register</description>
13068              <addressOffset>0x14</addressOffset>
13069              <size>32</size>
13070              <access>read-write</access>
13071              <resetValue>0x0</resetValue>
13072              <resetMask>0xFFFF</resetMask>
13073              <fields>
13074                <field>
13075                  <name>CNT</name>
13076                  <description>Current value of subcounter for this MCWDT.  This field may lag the actual count value by up to one clk_lf cycle, due to internal synchronization.  When this subcounter is disabled and unlocked, the count value can be written for verification and debugging purposes.  Software writes are always ignored when the subcounter is enabled. This register retains information during DeepSleep mode if SLEEPDEEP_PAUSE == 1.</description>
13077                  <bitRange>[15:0]</bitRange>
13078                  <access>read-write</access>
13079                </field>
13080              </fields>
13081            </register>
13082          </cluster>
13083          <register>
13084            <name>CPU_SELECT</name>
13085            <description>MCWDT CPU selection register</description>
13086            <addressOffset>0x40</addressOffset>
13087            <size>32</size>
13088            <access>read-write</access>
13089            <resetValue>0x0</resetValue>
13090            <resetMask>0x3</resetMask>
13091            <fields>
13092              <field>
13093                <name>CPU_SEL</name>
13094                <description>Assigns this MCWDT to a CPU.  This selects which CPU SLEEPDEEP signal is used for SLEEPDEEP_PAUSE.</description>
13095                <bitRange>[1:0]</bitRange>
13096                <access>read-write</access>
13097              </field>
13098            </fields>
13099          </register>
13100          <register>
13101            <name>CTR2_CTL</name>
13102            <description>MCWDT Subcounter 2 Control register</description>
13103            <addressOffset>0x80</addressOffset>
13104            <size>32</size>
13105            <access>read-write</access>
13106            <resetValue>0x0</resetValue>
13107            <resetMask>0x80000001</resetMask>
13108            <fields>
13109              <field>
13110                <name>ENABLED</name>
13111                <description>Indicates actual state of this subcounter.  May lag ENABLE by up to two clk_lf cycles.</description>
13112                <bitRange>[0:0]</bitRange>
13113                <access>read-only</access>
13114              </field>
13115              <field>
13116                <name>ENABLE</name>
13117                <description>Enable subcounter.  May take up to 2 clk_lf cycles to take effect.  When ENABLE changes from 1-&gt;0, the counter is cleared.
131180: Counter is disabled (not clocked)
131191: Counter is enabled (counting up)</description>
13120                <bitRange>[31:31]</bitRange>
13121                <access>read-write</access>
13122              </field>
13123            </fields>
13124          </register>
13125          <register>
13126            <name>CTR2_CONFIG</name>
13127            <description>MCWDT Subcounter 2 Configuration register</description>
13128            <addressOffset>0x84</addressOffset>
13129            <size>32</size>
13130            <access>read-write</access>
13131            <resetValue>0x0</resetValue>
13132            <resetMask>0xD01F0001</resetMask>
13133            <fields>
13134              <field>
13135                <name>ACTION</name>
13136                <description>Action taken when the specified BIT toggles.
13137Action will be triggered on the same edge where BITS to observe toggle.</description>
13138                <bitRange>[0:0]</bitRange>
13139                <access>read-write</access>
13140                <enumeratedValues>
13141                  <enumeratedValue>
13142                    <name>NOTHING</name>
13143                    <description>Do nothing</description>
13144                    <value>0</value>
13145                  </enumeratedValue>
13146                  <enumeratedValue>
13147                    <name>INT</name>
13148                    <description>Trigger an interrupt</description>
13149                    <value>1</value>
13150                  </enumeratedValue>
13151                </enumeratedValues>
13152              </field>
13153              <field>
13154                <name>BITS</name>
13155                <description>Bit to observe for a toggle:
131560: Do ACTION after CNT[0] toggles (i.e. every tick)
13157.
1315831: Do ACTION after CNT[31] toggles (i.e. every 2^31 ticks)</description>
13159                <bitRange>[20:16]</bitRange>
13160                <access>read-write</access>
13161              </field>
13162              <field>
13163                <name>DEBUG_TRIGGER_EN</name>
13164                <description>Enables the trigger input for this MCWDT to pause the counter during debug mode.  To pause at a breakpoint while debugging, configure the trigger matrix to connect the related CPU halted signal to the trigger input for this MCWDT, and then set this bit.  It takes up to two clk_lf cycles for the trigger signal to be processed.  Triggers that are less than two clk_lf cycles may be missed.  Synchronization errors can accumulate each time it is halted.
131650: Pauses the counter whenever a debug probe is connected.
131661: Pauses the counter whenever a debug probe is connected and the trigger input is high.</description>
13167                <bitRange>[28:28]</bitRange>
13168                <access>read-write</access>
13169              </field>
13170              <field>
13171                <name>SLEEPDEEP_PAUSE</name>
13172                <description>Pauses/runs this counter when the corresponding processor is in SLEEPDEEP.  Note it may take up to two clk_lf cycles for the counter to pause and up to two clk_lf cycles for it to unpause, due to internal synchronization.
131730: Counter runs normally regardless of processor mode.
131741: Counter pauses when corresponding processor is in SLEEPDEEP.</description>
13175                <bitRange>[30:30]</bitRange>
13176                <access>read-write</access>
13177              </field>
13178              <field>
13179                <name>DEBUG_RUN</name>
13180                <description>Pauses/runs this counter while a debugger is connected.  Other behaviors are unchanged during debugging, including service, configuration updates and enable/disable.  Note it may take up to two clk_lf cycles for the counter to pause and another two cycles to unpause, due to internal synchronization.
131810: When debugger connected, counter pauses incrementing as configured in DEBUG_TRIGGER_EN.
131821: When debugger connected, counter increments normally, but reset generation is blocked.</description>
13183                <bitRange>[31:31]</bitRange>
13184                <access>read-write</access>
13185              </field>
13186            </fields>
13187          </register>
13188          <register>
13189            <name>CTR2_CNT</name>
13190            <description>MCWDT Subcounter 2 Count Register</description>
13191            <addressOffset>0x88</addressOffset>
13192            <size>32</size>
13193            <access>read-write</access>
13194            <resetValue>0x0</resetValue>
13195            <resetMask>0xFFFFFFFF</resetMask>
13196            <fields>
13197              <field>
13198                <name>CNT2</name>
13199                <description>Current value of subcounter 2 for this MCWDT.  This field may lag the actual count value by up to one clk_lf cycle, due to internal synchronization.  When this subcounter is disabled and unlocked, the count value can be written for verification and debugging purposes.  Software writes are always ignored when the subcounter is enabled. This register retains information during DeepSleep mode if SLEEPDEEP_PAUSE == 1.</description>
13200                <bitRange>[31:0]</bitRange>
13201                <access>read-write</access>
13202              </field>
13203            </fields>
13204          </register>
13205          <register>
13206            <name>LOCK</name>
13207            <description>MCWDT Lock Register</description>
13208            <addressOffset>0x90</addressOffset>
13209            <size>32</size>
13210            <access>read-write</access>
13211            <resetValue>0x0</resetValue>
13212            <resetMask>0x3</resetMask>
13213            <fields>
13214              <field>
13215                <name>MCWDT_LOCK</name>
13216                <description>Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions).  Requires at least two different writes to unlock.
13217Note that this field is 2 bits to force multiple writes only.  Each MCWDT has a separate local lock.</description>
13218                <bitRange>[1:0]</bitRange>
13219                <access>read-write</access>
13220                <enumeratedValues>
13221                  <enumeratedValue>
13222                    <name>NO_CHG</name>
13223                    <description>No effect</description>
13224                    <value>0</value>
13225                  </enumeratedValue>
13226                  <enumeratedValue>
13227                    <name>CLR0</name>
13228                    <description>Clears bit 0</description>
13229                    <value>1</value>
13230                  </enumeratedValue>
13231                  <enumeratedValue>
13232                    <name>CLR1</name>
13233                    <description>Clears bit 1</description>
13234                    <value>2</value>
13235                  </enumeratedValue>
13236                  <enumeratedValue>
13237                    <name>SET01</name>
13238                    <description>Sets both bits 0 and 1</description>
13239                    <value>3</value>
13240                  </enumeratedValue>
13241                </enumeratedValues>
13242              </field>
13243            </fields>
13244          </register>
13245          <register>
13246            <name>SERVICE</name>
13247            <description>MCWDT Service Register</description>
13248            <addressOffset>0x94</addressOffset>
13249            <size>32</size>
13250            <access>read-write</access>
13251            <resetValue>0x0</resetValue>
13252            <resetMask>0x3</resetMask>
13253            <fields>
13254              <field>
13255                <name>CTR0_SERVICE</name>
13256                <description>Services subcounter 0.  This resets the count value for subcounter 0 to zero.  This may take up to three clk_lf cycles to take effect.  Hardware clears this bit, after necessary synchronization.  To ensure a pending CTR0_SERVICE write is reflected, firmware should wait until this bit reads low before attempting to write CTR0_SERVICE=1.  If subcounter 0 is disabled, CTR0_SERVICE will not trigger a LOWER_ACTION and will not clear a preloaded count value.</description>
13257                <bitRange>[0:0]</bitRange>
13258                <access>read-write</access>
13259              </field>
13260              <field>
13261                <name>CTR1_SERVICE</name>
13262                <description>Services subcounter 1.  This resets the count value for subcounter 1 to zero.  This may take up to three clk_lf cycles to take effect.  Hardware clears this bit, after necessary synchronization.  To ensure a pending CTR1_SERVICE write is reflected, firmware should wait until this bit reads low before attempting to write CTR1_SERVICE=1.  If subcounter 1 is disabled, CTR1_SERVICE will not trigger a LOWER_ACTION and will not clear a preloaded count value.</description>
13263                <bitRange>[1:1]</bitRange>
13264                <access>read-write</access>
13265              </field>
13266            </fields>
13267          </register>
13268          <register>
13269            <name>INTR</name>
13270            <description>MCWDT Interrupt Register</description>
13271            <addressOffset>0xA0</addressOffset>
13272            <size>32</size>
13273            <access>read-write</access>
13274            <resetValue>0x0</resetValue>
13275            <resetMask>0x7</resetMask>
13276            <fields>
13277              <field>
13278                <name>CTR0_INT</name>
13279                <description>MCWDT Interrupt Request for sub-counter 0.  This bit is set by hardware as configured by this registers.  This bit must be cleared by firmware.</description>
13280                <bitRange>[0:0]</bitRange>
13281                <access>read-write</access>
13282              </field>
13283              <field>
13284                <name>CTR1_INT</name>
13285                <description>MCWDT Interrupt Request for sub-counter 1.  This bit is set by hardware as configured by this registers.  This bit must be cleared by firmware.</description>
13286                <bitRange>[1:1]</bitRange>
13287                <access>read-write</access>
13288              </field>
13289              <field>
13290                <name>CTR2_INT</name>
13291                <description>MCWDT Interrupt Request for sub-counter 2.  This bit is set by hardware as configured by this registers.  This bit must be cleared by firmware.</description>
13292                <bitRange>[2:2]</bitRange>
13293                <access>read-write</access>
13294              </field>
13295            </fields>
13296          </register>
13297          <register>
13298            <name>INTR_SET</name>
13299            <description>MCWDT Interrupt Set Register</description>
13300            <addressOffset>0xA4</addressOffset>
13301            <size>32</size>
13302            <access>read-write</access>
13303            <resetValue>0x0</resetValue>
13304            <resetMask>0x7</resetMask>
13305            <fields>
13306              <field>
13307                <name>CTR0_INT</name>
13308                <description>Set interrupt for MCWDT_INT0</description>
13309                <bitRange>[0:0]</bitRange>
13310                <access>read-write</access>
13311              </field>
13312              <field>
13313                <name>CTR1_INT</name>
13314                <description>Set interrupt for MCWDT_INT1</description>
13315                <bitRange>[1:1]</bitRange>
13316                <access>read-write</access>
13317              </field>
13318              <field>
13319                <name>CTR2_INT</name>
13320                <description>Set interrupt for MCWDT_INT2</description>
13321                <bitRange>[2:2]</bitRange>
13322                <access>read-write</access>
13323              </field>
13324            </fields>
13325          </register>
13326          <register>
13327            <name>INTR_MASK</name>
13328            <description>MCWDT Interrupt Mask Register</description>
13329            <addressOffset>0xA8</addressOffset>
13330            <size>32</size>
13331            <access>read-write</access>
13332            <resetValue>0x0</resetValue>
13333            <resetMask>0x7</resetMask>
13334            <fields>
13335              <field>
13336                <name>CTR0_INT</name>
13337                <description>Mask for sub-counter 0 for warning interrupt</description>
13338                <bitRange>[0:0]</bitRange>
13339                <access>read-write</access>
13340              </field>
13341              <field>
13342                <name>CTR1_INT</name>
13343                <description>Mask for sub-counter 1 for warning interrupt</description>
13344                <bitRange>[1:1]</bitRange>
13345                <access>read-write</access>
13346              </field>
13347              <field>
13348                <name>CTR2_INT</name>
13349                <description>Mask for sub-counter 2</description>
13350                <bitRange>[2:2]</bitRange>
13351                <access>read-write</access>
13352              </field>
13353            </fields>
13354          </register>
13355          <register>
13356            <name>INTR_MASKED</name>
13357            <description>MCWDT Interrupt Masked Register</description>
13358            <addressOffset>0xAC</addressOffset>
13359            <size>32</size>
13360            <access>read-only</access>
13361            <resetValue>0x0</resetValue>
13362            <resetMask>0x7</resetMask>
13363            <fields>
13364              <field>
13365                <name>CTR0_INT</name>
13366                <description>Logical and of corresponding request and mask bits.</description>
13367                <bitRange>[0:0]</bitRange>
13368                <access>read-only</access>
13369              </field>
13370              <field>
13371                <name>CTR1_INT</name>
13372                <description>Logical and of corresponding request and mask bits.</description>
13373                <bitRange>[1:1]</bitRange>
13374                <access>read-only</access>
13375              </field>
13376              <field>
13377                <name>CTR2_INT</name>
13378                <description>Logical and of corresponding request and mask bits.</description>
13379                <bitRange>[2:2]</bitRange>
13380                <access>read-only</access>
13381              </field>
13382            </fields>
13383          </register>
13384        </cluster>
13385        <cluster>
13386          <name>WDT</name>
13387          <description>Watchdog Timer</description>
13388          <headerStructName>WDT</headerStructName>
13389          <addressOffset>0x0000C000</addressOffset>
13390          <register>
13391            <name>CTL</name>
13392            <description>WDT Control Register</description>
13393            <addressOffset>0x0</addressOffset>
13394            <size>32</size>
13395            <access>read-write</access>
13396            <resetValue>0x80000001</resetValue>
13397            <resetMask>0x80000001</resetMask>
13398            <fields>
13399              <field>
13400                <name>ENABLED</name>
13401                <description>Indicates actual state of watchdog.  May lag ENABLE by up to three clk_ilo0 cycles.</description>
13402                <bitRange>[0:0]</bitRange>
13403                <access>read-only</access>
13404              </field>
13405              <field>
13406                <name>ENABLE</name>
13407                <description>Enable watchdog.  May take up to three clk_ilo0 cycles to take effect.  When ENABLE changes from 1-&gt;0, the counter is cleared.  Do not enter DEEPSLEEP or HIBERNATE mode if ENABLE&lt;&gt;ENABLED.  This can be done by waiting until ENABLE==ENABLED whenever ENABLE is changed.
134080: Counter is disabled (not clocked).
134091: Counter is enabled (counting up)</description>
13410                <bitRange>[31:31]</bitRange>
13411                <access>read-write</access>
13412              </field>
13413            </fields>
13414          </register>
13415          <register>
13416            <name>LOWER_LIMIT</name>
13417            <description>WDT Lower Limit Register</description>
13418            <addressOffset>0x4</addressOffset>
13419            <size>32</size>
13420            <access>read-write</access>
13421            <resetValue>0x0</resetValue>
13422            <resetMask>0xFFFFFFFF</resetMask>
13423            <fields>
13424              <field>
13425                <name>LOWER_LIMIT</name>
13426                <description>Lower limit for watchdog.  See LOWER_ACTION.</description>
13427                <bitRange>[31:0]</bitRange>
13428                <access>read-write</access>
13429              </field>
13430            </fields>
13431          </register>
13432          <register>
13433            <name>UPPER_LIMIT</name>
13434            <description>WDT Upper Limit Register</description>
13435            <addressOffset>0x8</addressOffset>
13436            <size>32</size>
13437            <access>read-write</access>
13438            <resetValue>0x8000</resetValue>
13439            <resetMask>0xFFFFFFFF</resetMask>
13440            <fields>
13441              <field>
13442                <name>UPPER_LIMIT</name>
13443                <description>Upper limit for watchdog.  See UPPER_ACTION.</description>
13444                <bitRange>[31:0]</bitRange>
13445                <access>read-write</access>
13446              </field>
13447            </fields>
13448          </register>
13449          <register>
13450            <name>WARN_LIMIT</name>
13451            <description>WDT Warn Limit Register</description>
13452            <addressOffset>0xC</addressOffset>
13453            <size>32</size>
13454            <access>read-write</access>
13455            <resetValue>0x0</resetValue>
13456            <resetMask>0xFFFFFFFF</resetMask>
13457            <fields>
13458              <field>
13459                <name>WARN_LIMIT</name>
13460                <description>Warn limit for watchdog.  See WARN_ACTION.</description>
13461                <bitRange>[31:0]</bitRange>
13462                <access>read-write</access>
13463              </field>
13464            </fields>
13465          </register>
13466          <register>
13467            <name>CONFIG</name>
13468            <description>WDT Configuration Register</description>
13469            <addressOffset>0x10</addressOffset>
13470            <size>32</size>
13471            <access>read-write</access>
13472            <resetValue>0x10</resetValue>
13473            <resetMask>0xF0001111</resetMask>
13474            <fields>
13475              <field>
13476                <name>LOWER_ACTION</name>
13477                <description>Action taken if this watchdog is serviced before LOWER_LIMIT is reached.  LOWER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected and/or when the chip is in DEEPSLEEP/HIBERNATE modes.
13478For LOWER_LIMIT &gt;= 1: The action is triggered on same edge when it meets this condition.
13479For LOWER_LIMIT == 0: No action is triggered.</description>
13480                <bitRange>[0:0]</bitRange>
13481                <access>read-write</access>
13482                <enumeratedValues>
13483                  <enumeratedValue>
13484                    <name>NOTHING</name>
13485                    <description>Do nothing</description>
13486                    <value>0</value>
13487                  </enumeratedValue>
13488                  <enumeratedValue>
13489                    <name>RESET</name>
13490                    <description>Trigger a reset.</description>
13491                    <value>1</value>
13492                  </enumeratedValue>
13493                </enumeratedValues>
13494              </field>
13495              <field>
13496                <name>UPPER_ACTION</name>
13497                <description>Action taken if this watchdog is not serviced before UPPER_LIMIT is reached.  The counter stops counting when UPPER_LIMIT is reached, regardless of UPPER_ACTION setting.   UPPER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected.
13498For UPPER_LIMIT &gt;= 2: The action is triggered on same edge when it meets this condition.
13499For UPPER_LIMIT &lt; 2: The action may take up to one extra clk_ilo0 cycle to trigger.</description>
13500                <bitRange>[4:4]</bitRange>
13501                <access>read-write</access>
13502                <enumeratedValues>
13503                  <enumeratedValue>
13504                    <name>NOTHING</name>
13505                    <description>Do nothing</description>
13506                    <value>0</value>
13507                  </enumeratedValue>
13508                  <enumeratedValue>
13509                    <name>RESET</name>
13510                    <description>Trigger a reset.</description>
13511                    <value>1</value>
13512                  </enumeratedValue>
13513                </enumeratedValues>
13514              </field>
13515              <field>
13516                <name>WARN_ACTION</name>
13517                <description>Action taken when the count value reaches WARN_LIMIT.  The minimum setting to achieve a periodic interrupt is WARN_LIMIT==1.  A setting of zero will trigger once but not periodically.
13518For WARN_LIMIT &gt;= 2: The action is triggered on same edge when it meets this condition.
13519For WARN_LIMIT &lt; 2  : The action may take up to one extra clk_ilo0 cycle to trigger.</description>
13520                <bitRange>[8:8]</bitRange>
13521                <access>read-write</access>
13522                <enumeratedValues>
13523                  <enumeratedValue>
13524                    <name>NOTHING</name>
13525                    <description>Do nothing</description>
13526                    <value>0</value>
13527                  </enumeratedValue>
13528                  <enumeratedValue>
13529                    <name>INT</name>
13530                    <description>Trigger an interrupt.</description>
13531                    <value>1</value>
13532                  </enumeratedValue>
13533                </enumeratedValues>
13534              </field>
13535              <field>
13536                <name>AUTO_SERVICE</name>
13537                <description>Automatically service when the count value reaches WARN_LIMIT.  This allows creation of a periodic interrupt if this counter is not needed as a watchdog.  This field is ignored when LOWER_ACTION&lt;&gt;NOTHING or when UPPER_ACTION&lt;&gt;NOTHING.</description>
13538                <bitRange>[12:12]</bitRange>
13539                <access>read-write</access>
13540              </field>
13541              <field>
13542                <name>DEBUG_TRIGGER_EN</name>
13543                <description>Enables the trigger input for WDT to pause the counter during debug mode.  To pause at a breakpoint while debugging, configure the trigger matrix to connect the related CPU halted signal to the trigger input for this WDT, and then set this bit.  It takes up to two clk_ilo0 cycles for the trigger signal to be processed.  Triggers that are less than two clk_ilo0 cycles may be missed.  Synchronization error can accumulate each time it is halted.
135440: Pauses the counter whenever a debug probe is connected.
135451: Pauses the counter whenever a debug probe is connected and the trigger input is high.</description>
13546                <bitRange>[28:28]</bitRange>
13547                <access>read-write</access>
13548              </field>
13549              <field>
13550                <name>DPSLP_PAUSE</name>
13551                <description>Pauses/runs this counter when the system is in DEEPSLEEP.  Note it may take up to two clk_ilo0 cycles for the counter to pause, due to internal synchronization.  During DEEPSLEEP wakeup, the pause request is removed when clk_hf0 starts clocking, and then it may take up to two clk_ilo0 cycles for the counter to start.  After wakeup, the LOWER_ACTION is ignored until after the first service.  This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period.  After the first service, LOWER_ACTION behaves as configured.
135520: Counter behaves normally during DEEPSLEEP.
135531: Counter pauses during DEEPSLEEP.</description>
13554                <bitRange>[29:29]</bitRange>
13555                <access>read-write</access>
13556              </field>
13557              <field>
13558                <name>HIB_PAUSE</name>
13559                <description>Pauses/runs this counter when the system is in HIBERNATE.  Note it may take up to two clk_ilo0 cycles for the counter to pause, due to internal synchronization.  After wakeup, the LOWER_ACTION is ignored until after the first service.  This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period.  After the first service, LOWER_ACTION behaves as configured.
135600: Counter behaves normally during HIBERNATE.
135611: Counter pauses during HIBERNATE.</description>
13562                <bitRange>[30:30]</bitRange>
13563                <access>read-write</access>
13564              </field>
13565              <field>
13566                <name>DEBUG_RUN</name>
13567                <description>Pauses/runs this counter while a debugger is connected.  Other behaviors are unchanged during debugging, including service, configuration updates and enable/disable.  Note it may take up to two clk_ilo0 cycles for the counter to pause and another two cycles to unpause, due to internal synchronization.  If the debugger is connected for at least two clk_ilo0 cycles, the LOWER_ACTION is ignored until after the first service after the debugger is disconnected.  This prevents an unintentional trigger of the LOWER_ACTION before the firmware realigns the servicing period.  After the first service, LOWER_ACTION behaves as configured.  If the debugger is disconnected before two clk_ilo0 cycles, the LOWER_ACTION may or may not be ignored.
135680: When debugger connected, counter pauses incrementing as configured in DEBUG_TRIGGER_EN.
135691: When debugger connected, counter increments normally, but reset generation is blocked.</description>
13570                <bitRange>[31:31]</bitRange>
13571                <access>read-write</access>
13572              </field>
13573            </fields>
13574          </register>
13575          <register>
13576            <name>CNT</name>
13577            <description>WDT Count Register</description>
13578            <addressOffset>0x14</addressOffset>
13579            <size>32</size>
13580            <access>read-write</access>
13581            <resetValue>0x0</resetValue>
13582            <resetMask>0xFFFFFFFF</resetMask>
13583            <fields>
13584              <field>
13585                <name>CNT</name>
13586                <description>Current value of subcounter for this WDT.  This field may lag the actual count value by up to one clk_ilo0 cycle, due to internal synchronization.  When this subcounter is disabled and unlocked, the count value can be written for verification and debugging purposes.  Software writes are always ignored when the subcounter is enabled. This register retains information during DeepSleep or Hiberbate mode if DPSLP_PAUSE == 1 or HIB_PAUSE == 1.</description>
13587                <bitRange>[31:0]</bitRange>
13588                <access>read-write</access>
13589              </field>
13590            </fields>
13591          </register>
13592          <register>
13593            <name>LOCK</name>
13594            <description>WDT Lock register</description>
13595            <addressOffset>0x40</addressOffset>
13596            <size>32</size>
13597            <access>read-write</access>
13598            <resetValue>0x3</resetValue>
13599            <resetMask>0x3</resetMask>
13600            <fields>
13601              <field>
13602                <name>WDT_LOCK</name>
13603                <description>Prohibits writing control and configuration registers related to this WDT when not equal 0 (as specified in the other register descriptions).  Requires at least two different writes to unlock.
13604Note that this field is 2 bits to force multiple writes only.  This register also locks the clk_ilo0 settings.</description>
13605                <bitRange>[1:0]</bitRange>
13606                <access>read-write</access>
13607                <enumeratedValues>
13608                  <enumeratedValue>
13609                    <name>NO_CHG</name>
13610                    <description>No effect</description>
13611                    <value>0</value>
13612                  </enumeratedValue>
13613                  <enumeratedValue>
13614                    <name>CLR0</name>
13615                    <description>Clears bit 0</description>
13616                    <value>1</value>
13617                  </enumeratedValue>
13618                  <enumeratedValue>
13619                    <name>CLR1</name>
13620                    <description>Clears bit 1</description>
13621                    <value>2</value>
13622                  </enumeratedValue>
13623                  <enumeratedValue>
13624                    <name>SET01</name>
13625                    <description>Sets both bits 0 and 1</description>
13626                    <value>3</value>
13627                  </enumeratedValue>
13628                </enumeratedValues>
13629              </field>
13630            </fields>
13631          </register>
13632          <register>
13633            <name>SERVICE</name>
13634            <description>WDT Service register</description>
13635            <addressOffset>0x44</addressOffset>
13636            <size>32</size>
13637            <access>read-write</access>
13638            <resetValue>0x0</resetValue>
13639            <resetMask>0x1</resetMask>
13640            <fields>
13641              <field>
13642                <name>SERVICE</name>
13643                <description>Services the watchdog.  This resets the count value to zero.  This may take up to three clk_ilo0 cycle to take effect.  Hardware clears this bit, after necessary synchronization.  To ensure a pending SERVICE write is reflected, firmware should wait until this bit reads low before attempting to write SERVICE=1.  If WDT is disabled, SERVICE will not trigger a LOWER_ACTION and will not clear a preloaded count value.</description>
13644                <bitRange>[0:0]</bitRange>
13645                <access>read-write</access>
13646              </field>
13647            </fields>
13648          </register>
13649          <register>
13650            <name>INTR</name>
13651            <description>WDT Interrupt Register</description>
13652            <addressOffset>0x50</addressOffset>
13653            <size>32</size>
13654            <access>read-write</access>
13655            <resetValue>0x0</resetValue>
13656            <resetMask>0x1</resetMask>
13657            <fields>
13658              <field>
13659                <name>WDT</name>
13660                <description>WDT Interrupt Request.  This bit is set as configured by WDT action and limits.  Due to internal synchronization, it takes up to 8 SYSCLK cycles to update after a W1C or reading this register and during this time AHB bus is stalled.</description>
13661                <bitRange>[0:0]</bitRange>
13662                <access>read-write</access>
13663              </field>
13664            </fields>
13665          </register>
13666          <register>
13667            <name>INTR_SET</name>
13668            <description>WDT Interrupt Set Register</description>
13669            <addressOffset>0x54</addressOffset>
13670            <size>32</size>
13671            <access>read-write</access>
13672            <resetValue>0x0</resetValue>
13673            <resetMask>0x1</resetMask>
13674            <fields>
13675              <field>
13676                <name>WDT</name>
13677                <description>Set interrupt.
13678Due to internal synchronization, it takes up to 8 SYSCLK cycles to update after a W1S or reading from this register and during this time AHB bus is stalled.</description>
13679                <bitRange>[0:0]</bitRange>
13680                <access>read-write</access>
13681              </field>
13682            </fields>
13683          </register>
13684          <register>
13685            <name>INTR_MASK</name>
13686            <description>WDT Interrupt Mask Register</description>
13687            <addressOffset>0x58</addressOffset>
13688            <size>32</size>
13689            <access>read-write</access>
13690            <resetValue>0x0</resetValue>
13691            <resetMask>0x1</resetMask>
13692            <fields>
13693              <field>
13694                <name>WDT</name>
13695                <description>Mask for watchdog timer.  Clearing this bit will not forward the interrupt to the CPU.</description>
13696                <bitRange>[0:0]</bitRange>
13697                <access>read-write</access>
13698              </field>
13699            </fields>
13700          </register>
13701          <register>
13702            <name>INTR_MASKED</name>
13703            <description>WDT Interrupt Masked Register</description>
13704            <addressOffset>0x5C</addressOffset>
13705            <size>32</size>
13706            <access>read-only</access>
13707            <resetValue>0x0</resetValue>
13708            <resetMask>0x1</resetMask>
13709            <fields>
13710              <field>
13711                <name>WDT</name>
13712                <description>Logical and of corresponding request and mask bits.
13713Due to internal synchronization, it takes up to 8 SYSCLK cycles to read from this register.  During this time AHB bus is stalled.</description>
13714                <bitRange>[0:0]</bitRange>
13715                <access>read-only</access>
13716              </field>
13717            </fields>
13718          </register>
13719        </cluster>
13720      </registers>
13721    </peripheral>
13722    <peripheral>
13723      <name>BACKUP</name>
13724      <description>SRSS Backup Domain (ver2)</description>
13725      <baseAddress>0x40270000</baseAddress>
13726      <addressBlock>
13727        <offset>0</offset>
13728        <size>65536</size>
13729        <usage>registers</usage>
13730      </addressBlock>
13731      <registers>
13732        <register>
13733          <name>CTL</name>
13734          <description>Control</description>
13735          <addressOffset>0x0</addressOffset>
13736          <size>32</size>
13737          <access>read-write</access>
13738          <resetValue>0x0</resetValue>
13739          <resetMask>0xFF0F3308</resetMask>
13740          <fields>
13741            <field>
13742              <name>WCO_EN</name>
13743              <description>Watch-crystal oscillator (WCO) enable.  If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes.
13744After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs.  Follow the procedure in BACKUP_RTC_RW to access this bit.</description>
13745              <bitRange>[3:3]</bitRange>
13746              <access>read-write</access>
13747            </field>
13748            <field>
13749              <name>CLK_SEL</name>
13750              <description>Clock select for RTC clock</description>
13751              <bitRange>[9:8]</bitRange>
13752              <access>read-write</access>
13753              <enumeratedValues>
13754                <enumeratedValue>
13755                  <name>WCO</name>
13756                  <description>Watch-crystal oscillator input, available in Active, DeepSleep and Hibernate</description>
13757                  <value>0</value>
13758                </enumeratedValue>
13759                <enumeratedValue>
13760                  <name>ALTBAK</name>
13761                  <description>This allows to use the LFCLK selection as an alternate backup domain clock. Note that LFCLK is only available in Active and DeepSleep power modes.
13762Note that LFCLK clock glitches can propagate into the backup logic when the clock is stopped.  For this reason, if the WCO or ILO is intended as the clock source then choose it directly instead of routing through LFCLK.</description>
13763                  <value>1</value>
13764                </enumeratedValue>
13765                <enumeratedValue>
13766                  <name>ILO</name>
13767                  <description>Internal Low frequency Oscillator, available in Active, DeepSleep and Hibernate.
13768For Hibernate operation CLK_ILO_CONFIG. ILO_BACKUP must be set.</description>
13769                  <value>2</value>
13770                </enumeratedValue>
13771                <enumeratedValue>
13772                  <name>RSVD</name>
13773                  <description>N/A</description>
13774                  <value>3</value>
13775                </enumeratedValue>
13776              </enumeratedValues>
13777            </field>
13778            <field>
13779              <name>PRESCALER</name>
13780              <description>N/A</description>
13781              <bitRange>[13:12]</bitRange>
13782              <access>read-write</access>
13783            </field>
13784            <field>
13785              <name>WCO_BYPASS</name>
13786              <description>Configures the WCO for different board-level connections to the WCO pins.  For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal.   In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below.  Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1.
137870: Watch crystal.  Connect a 32.768 kHz watch crystal between WCO input and output pins.
137881: Clock signal, either a square wave or sine wave.  See PRESCALER field for connection information.</description>
13789              <bitRange>[16:16]</bitRange>
13790              <access>read-write</access>
13791            </field>
13792            <field>
13793              <name>VDDBAK_CTL</name>
13794              <description>Controls the behavior of the switch that generates vddbak from vbackup or vddd.
137950: automatically select vddd if its brownout detector says it is valid.  If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup.
137961,2,3: force vddbak and vmax to select vbackup, regardless of its voltage.</description>
13797              <bitRange>[18:17]</bitRange>
13798              <access>read-write</access>
13799            </field>
13800            <field>
13801              <name>VBACKUP_MEAS</name>
13802              <description>Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd.  The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC.</description>
13803              <bitRange>[19:19]</bitRange>
13804              <access>read-write</access>
13805            </field>
13806            <field>
13807              <name>EN_CHARGE_KEY</name>
13808              <description>When set to 3C, the supercap charger circuit is enabled.  Any other code disables the supercap charger.  THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY.  DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY.</description>
13809              <bitRange>[31:24]</bitRange>
13810              <access>read-write</access>
13811            </field>
13812          </fields>
13813        </register>
13814        <register>
13815          <name>RTC_RW</name>
13816          <description>RTC Read Write register</description>
13817          <addressOffset>0x8</addressOffset>
13818          <size>32</size>
13819          <access>read-write</access>
13820          <resetValue>0x0</resetValue>
13821          <resetMask>0x3</resetMask>
13822          <fields>
13823            <field>
13824              <name>READ</name>
13825              <description>Read bit
13826When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running.
13827Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared.</description>
13828              <bitRange>[0:0]</bitRange>
13829              <access>read-write</access>
13830            </field>
13831            <field>
13832              <name>WRITE</name>
13833              <description>Write bit
13834Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set.
13835The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers.
13836Only user RTC registers that were written to will get copied, others will not be affected.
13837When the SECONDS field is updated then TICKS will also be reset (WDT is not affected).
13838When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost.
13839Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY).  Do not set the Write bit at the same time that the Read bit is cleared.</description>
13840              <bitRange>[1:1]</bitRange>
13841              <access>read-write</access>
13842            </field>
13843          </fields>
13844        </register>
13845        <register>
13846          <name>CAL_CTL</name>
13847          <description>Oscillator calibration for absolute frequency</description>
13848          <addressOffset>0xC</addressOffset>
13849          <size>32</size>
13850          <access>read-write</access>
13851          <resetValue>0x0</resetValue>
13852          <resetMask>0xB000007F</resetMask>
13853          <fields>
13854            <field>
13855              <name>CALIB_VAL</name>
13856              <description>Calibration value for absolute frequency (at a fixed temperature).  Each step causes 128 ticks to be added or removed each hour.  Effectively that means that each step is 1.085ppm (= 128/(60*60*32,768)).
13857Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field)
13858
13859Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments.</description>
13860              <bitRange>[5:0]</bitRange>
13861              <access>read-write</access>
13862            </field>
13863            <field>
13864              <name>CALIB_SIGN</name>
13865              <description>Calibration sign:
138660= Negative sign: remove pulses (it takes more clock ticks to count one second)
138671= Positive sign: add pulses (it takes less clock ticks to count one second)</description>
13868              <bitRange>[6:6]</bitRange>
13869              <access>read-write</access>
13870            </field>
13871            <field>
13872              <name>CAL_SEL</name>
13873              <description>Select calibration wave output signal</description>
13874              <bitRange>[29:28]</bitRange>
13875              <access>read-write</access>
13876              <enumeratedValues>
13877                <enumeratedValue>
13878                  <name>CAL512</name>
13879                  <description>512Hz wave, not affected by calibration setting (not supported for 50/60Hz input clock: CTL.PRESCALER!=0)</description>
13880                  <value>0</value>
13881                </enumeratedValue>
13882                <enumeratedValue>
13883                  <name>RSVD</name>
13884                  <description>N/A</description>
13885                  <value>1</value>
13886                </enumeratedValue>
13887                <enumeratedValue>
13888                  <name>CAL2</name>
13889                  <description>2Hz wave, includes the effect of the calibration setting, (not supported for 50/60Hz input clock: CTL.PRESCALER!=0)</description>
13890                  <value>2</value>
13891                </enumeratedValue>
13892                <enumeratedValue>
13893                  <name>CAL1</name>
13894                  <description>1Hz wave, includes the effect of the calibration setting (supported for all input clocks)</description>
13895                  <value>3</value>
13896                </enumeratedValue>
13897              </enumeratedValues>
13898            </field>
13899            <field>
13900              <name>CAL_OUT</name>
13901              <description>Output enable for wave signal for calibration and allow CALIB_VAL to be written.</description>
13902              <bitRange>[31:31]</bitRange>
13903              <access>read-write</access>
13904            </field>
13905          </fields>
13906        </register>
13907        <register>
13908          <name>STATUS</name>
13909          <description>Status</description>
13910          <addressOffset>0x10</addressOffset>
13911          <size>32</size>
13912          <access>read-only</access>
13913          <resetValue>0x0</resetValue>
13914          <resetMask>0x5</resetMask>
13915          <fields>
13916            <field>
13917              <name>RTC_BUSY</name>
13918              <description>Pending RTC write</description>
13919              <bitRange>[0:0]</bitRange>
13920              <access>read-only</access>
13921            </field>
13922            <field>
13923              <name>WCO_OK</name>
13924              <description>Indicates that output has transitioned.</description>
13925              <bitRange>[2:2]</bitRange>
13926              <access>read-only</access>
13927            </field>
13928          </fields>
13929        </register>
13930        <register>
13931          <name>RTC_TIME</name>
13932          <description>Calendar Seconds, Minutes, Hours, Day of Week</description>
13933          <addressOffset>0x14</addressOffset>
13934          <size>32</size>
13935          <access>read-write</access>
13936          <resetValue>0x1000000</resetValue>
13937          <resetMask>0x75F3F3F</resetMask>
13938          <fields>
13939            <field>
13940              <name>RTC_SEC</name>
13941              <description>Calendar seconds, 0-59</description>
13942              <bitRange>[5:0]</bitRange>
13943              <access>read-write</access>
13944            </field>
13945            <field>
13946              <name>RTC_MIN</name>
13947              <description>Calendar minutes, 0-59</description>
13948              <bitRange>[13:8]</bitRange>
13949              <access>read-write</access>
13950            </field>
13951            <field>
13952              <name>RTC_HOUR</name>
13953              <description>Calendar hours, value depending on 12/24HR mode
139540=24HR: [20:16]=0-23
139551=12HR: [20]:0=AM, 1=PM, [19:16]=1-12</description>
13956              <bitRange>[20:16]</bitRange>
13957              <access>read-write</access>
13958            </field>
13959            <field>
13960              <name>CTRL_12HR</name>
13961              <description>Select 12/24HR mode: 1=12HR, 0=24HR</description>
13962              <bitRange>[22:22]</bitRange>
13963              <access>read-write</access>
13964            </field>
13965            <field>
13966              <name>RTC_DAY</name>
13967              <description>Calendar Day of the week, 1-7
13968It is up to the user to define the meaning of the values, but 1=Monday is recommended</description>
13969              <bitRange>[26:24]</bitRange>
13970              <access>read-write</access>
13971            </field>
13972          </fields>
13973        </register>
13974        <register>
13975          <name>RTC_DATE</name>
13976          <description>Calendar Day of Month, Month,  Year</description>
13977          <addressOffset>0x18</addressOffset>
13978          <size>32</size>
13979          <access>read-write</access>
13980          <resetValue>0x101</resetValue>
13981          <resetMask>0x7F0F1F</resetMask>
13982          <fields>
13983            <field>
13984              <name>RTC_DATE</name>
13985              <description>Calendar Day of the Month, 1-31
13986Automatic Leap Year Correction</description>
13987              <bitRange>[4:0]</bitRange>
13988              <access>read-write</access>
13989            </field>
13990            <field>
13991              <name>RTC_MON</name>
13992              <description>Calendar Month, 1-12</description>
13993              <bitRange>[11:8]</bitRange>
13994              <access>read-write</access>
13995            </field>
13996            <field>
13997              <name>RTC_YEAR</name>
13998              <description>Calendar year, 0-99</description>
13999              <bitRange>[22:16]</bitRange>
14000              <access>read-write</access>
14001            </field>
14002          </fields>
14003        </register>
14004        <register>
14005          <name>ALM1_TIME</name>
14006          <description>Alarm 1 Seconds, Minute, Hours, Day of Week</description>
14007          <addressOffset>0x1C</addressOffset>
14008          <size>32</size>
14009          <access>read-write</access>
14010          <resetValue>0x1000000</resetValue>
14011          <resetMask>0x879FBFBF</resetMask>
14012          <fields>
14013            <field>
14014              <name>ALM_SEC</name>
14015              <description>Alarm seconds, 0-59</description>
14016              <bitRange>[5:0]</bitRange>
14017              <access>read-write</access>
14018            </field>
14019            <field>
14020              <name>ALM_SEC_EN</name>
14021              <description>Alarm second enable: 0=ignore, 1=match</description>
14022              <bitRange>[7:7]</bitRange>
14023              <access>read-write</access>
14024            </field>
14025            <field>
14026              <name>ALM_MIN</name>
14027              <description>Alarm minutes, 0-59</description>
14028              <bitRange>[13:8]</bitRange>
14029              <access>read-write</access>
14030            </field>
14031            <field>
14032              <name>ALM_MIN_EN</name>
14033              <description>Alarm minutes enable: 0=ignore, 1=match</description>
14034              <bitRange>[15:15]</bitRange>
14035              <access>read-write</access>
14036            </field>
14037            <field>
14038              <name>ALM_HOUR</name>
14039              <description>Alarm hours, value depending on 12/24HR mode
1404024HR: [4:0]=0-23
1404112HR: [4]:0=AM, 1=PM, [3:0]=1-12</description>
14042              <bitRange>[20:16]</bitRange>
14043              <access>read-write</access>
14044            </field>
14045            <field>
14046              <name>ALM_HOUR_EN</name>
14047              <description>Alarm hour enable: 0=ignore, 1=match</description>
14048              <bitRange>[23:23]</bitRange>
14049              <access>read-write</access>
14050            </field>
14051            <field>
14052              <name>ALM_DAY</name>
14053              <description>Alarm Day of the week, 1-7
14054It is up to the user to define the meaning of the values, but 1=Monday is recommended</description>
14055              <bitRange>[26:24]</bitRange>
14056              <access>read-write</access>
14057            </field>
14058            <field>
14059              <name>ALM_DAY_EN</name>
14060              <description>Alarm Day of the Week enable: 0=ignore, 1=match</description>
14061              <bitRange>[31:31]</bitRange>
14062              <access>read-write</access>
14063            </field>
14064          </fields>
14065        </register>
14066        <register>
14067          <name>ALM1_DATE</name>
14068          <description>Alarm 1 Day of Month, Month</description>
14069          <addressOffset>0x20</addressOffset>
14070          <size>32</size>
14071          <access>read-write</access>
14072          <resetValue>0x101</resetValue>
14073          <resetMask>0x80008F9F</resetMask>
14074          <fields>
14075            <field>
14076              <name>ALM_DATE</name>
14077              <description>Alarm Day of the Month, 1-31
14078Leap Year corrected</description>
14079              <bitRange>[4:0]</bitRange>
14080              <access>read-write</access>
14081            </field>
14082            <field>
14083              <name>ALM_DATE_EN</name>
14084              <description>Alarm Day of the Month enable: 0=ignore, 1=match</description>
14085              <bitRange>[7:7]</bitRange>
14086              <access>read-write</access>
14087            </field>
14088            <field>
14089              <name>ALM_MON</name>
14090              <description>Alarm Month, 1-12</description>
14091              <bitRange>[11:8]</bitRange>
14092              <access>read-write</access>
14093            </field>
14094            <field>
14095              <name>ALM_MON_EN</name>
14096              <description>Alarm Month enable: 0=ignore, 1=match</description>
14097              <bitRange>[15:15]</bitRange>
14098              <access>read-write</access>
14099            </field>
14100            <field>
14101              <name>ALM_EN</name>
14102              <description>Master enable for alarm 1.
141030: Alarm 1 is disabled.  Fields for date and time are ignored.
141041: Alarm 1 is enabled.  Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration.  If none of the date and time fields are enabled, then this alarm triggers once every second.</description>
14105              <bitRange>[31:31]</bitRange>
14106              <access>read-write</access>
14107            </field>
14108          </fields>
14109        </register>
14110        <register>
14111          <name>ALM2_TIME</name>
14112          <description>Alarm 2 Seconds, Minute, Hours, Day of Week</description>
14113          <addressOffset>0x24</addressOffset>
14114          <size>32</size>
14115          <access>read-write</access>
14116          <resetValue>0x1000000</resetValue>
14117          <resetMask>0x879FBFBF</resetMask>
14118          <fields>
14119            <field>
14120              <name>ALM_SEC</name>
14121              <description>Alarm seconds, 0-59</description>
14122              <bitRange>[5:0]</bitRange>
14123              <access>read-write</access>
14124            </field>
14125            <field>
14126              <name>ALM_SEC_EN</name>
14127              <description>Alarm second enable: 0=ignore, 1=match</description>
14128              <bitRange>[7:7]</bitRange>
14129              <access>read-write</access>
14130            </field>
14131            <field>
14132              <name>ALM_MIN</name>
14133              <description>Alarm minutes, 0-59</description>
14134              <bitRange>[13:8]</bitRange>
14135              <access>read-write</access>
14136            </field>
14137            <field>
14138              <name>ALM_MIN_EN</name>
14139              <description>Alarm minutes enable: 0=ignore, 1=match</description>
14140              <bitRange>[15:15]</bitRange>
14141              <access>read-write</access>
14142            </field>
14143            <field>
14144              <name>ALM_HOUR</name>
14145              <description>Alarm hours, value depending on 12/24HR mode
1414624HR: [4:0]=0-23
1414712HR: [4]:0=AM, 1=PM, [3:0]=1-12</description>
14148              <bitRange>[20:16]</bitRange>
14149              <access>read-write</access>
14150            </field>
14151            <field>
14152              <name>ALM_HOUR_EN</name>
14153              <description>Alarm hour enable: 0=ignore, 1=match</description>
14154              <bitRange>[23:23]</bitRange>
14155              <access>read-write</access>
14156            </field>
14157            <field>
14158              <name>ALM_DAY</name>
14159              <description>Alarm Day of the week, 1-7
14160It is up to the user to define the meaning of the values, but 1=Monday is recommended</description>
14161              <bitRange>[26:24]</bitRange>
14162              <access>read-write</access>
14163            </field>
14164            <field>
14165              <name>ALM_DAY_EN</name>
14166              <description>Alarm Day of the Week enable: 0=ignore, 1=match</description>
14167              <bitRange>[31:31]</bitRange>
14168              <access>read-write</access>
14169            </field>
14170          </fields>
14171        </register>
14172        <register>
14173          <name>ALM2_DATE</name>
14174          <description>Alarm 2 Day of Month, Month</description>
14175          <addressOffset>0x28</addressOffset>
14176          <size>32</size>
14177          <access>read-write</access>
14178          <resetValue>0x101</resetValue>
14179          <resetMask>0x80008F9F</resetMask>
14180          <fields>
14181            <field>
14182              <name>ALM_DATE</name>
14183              <description>Alarm Day of the Month, 1-31
14184Leap Year corrected</description>
14185              <bitRange>[4:0]</bitRange>
14186              <access>read-write</access>
14187            </field>
14188            <field>
14189              <name>ALM_DATE_EN</name>
14190              <description>Alarm Day of the Month enable: 0=ignore, 1=match</description>
14191              <bitRange>[7:7]</bitRange>
14192              <access>read-write</access>
14193            </field>
14194            <field>
14195              <name>ALM_MON</name>
14196              <description>Alarm Month, 1-12</description>
14197              <bitRange>[11:8]</bitRange>
14198              <access>read-write</access>
14199            </field>
14200            <field>
14201              <name>ALM_MON_EN</name>
14202              <description>Alarm Month enable: 0=ignore, 1=match</description>
14203              <bitRange>[15:15]</bitRange>
14204              <access>read-write</access>
14205            </field>
14206            <field>
14207              <name>ALM_EN</name>
14208              <description>Master enable for alarm 2.
142090: Alarm 2 is disabled.  Fields for date and time are ignored.
142101: Alarm 2 is enabled.  Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration.  If none of the date and time fields are enabled, then this alarm triggers once every second.</description>
14211              <bitRange>[31:31]</bitRange>
14212              <access>read-write</access>
14213            </field>
14214          </fields>
14215        </register>
14216        <register>
14217          <name>INTR</name>
14218          <description>Interrupt request register</description>
14219          <addressOffset>0x2C</addressOffset>
14220          <size>32</size>
14221          <access>read-write</access>
14222          <resetValue>0x0</resetValue>
14223          <resetMask>0x7</resetMask>
14224          <fields>
14225            <field>
14226              <name>ALARM1</name>
14227              <description>Alarm 1 Interrupt</description>
14228              <bitRange>[0:0]</bitRange>
14229              <access>read-write</access>
14230            </field>
14231            <field>
14232              <name>ALARM2</name>
14233              <description>Alarm 2 Interrupt</description>
14234              <bitRange>[1:1]</bitRange>
14235              <access>read-write</access>
14236            </field>
14237            <field>
14238              <name>CENTURY</name>
14239              <description>Century overflow interrupt</description>
14240              <bitRange>[2:2]</bitRange>
14241              <access>read-write</access>
14242            </field>
14243          </fields>
14244        </register>
14245        <register>
14246          <name>INTR_SET</name>
14247          <description>Interrupt set request register</description>
14248          <addressOffset>0x30</addressOffset>
14249          <size>32</size>
14250          <access>read-write</access>
14251          <resetValue>0x0</resetValue>
14252          <resetMask>0x7</resetMask>
14253          <fields>
14254            <field>
14255              <name>ALARM1</name>
14256              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
14257              <bitRange>[0:0]</bitRange>
14258              <access>read-write</access>
14259            </field>
14260            <field>
14261              <name>ALARM2</name>
14262              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
14263              <bitRange>[1:1]</bitRange>
14264              <access>read-write</access>
14265            </field>
14266            <field>
14267              <name>CENTURY</name>
14268              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
14269              <bitRange>[2:2]</bitRange>
14270              <access>read-write</access>
14271            </field>
14272          </fields>
14273        </register>
14274        <register>
14275          <name>INTR_MASK</name>
14276          <description>Interrupt mask register</description>
14277          <addressOffset>0x34</addressOffset>
14278          <size>32</size>
14279          <access>read-write</access>
14280          <resetValue>0x0</resetValue>
14281          <resetMask>0x7</resetMask>
14282          <fields>
14283            <field>
14284              <name>ALARM1</name>
14285              <description>Mask bit for corresponding bit in interrupt request register.</description>
14286              <bitRange>[0:0]</bitRange>
14287              <access>read-write</access>
14288            </field>
14289            <field>
14290              <name>ALARM2</name>
14291              <description>Mask bit for corresponding bit in interrupt request register.</description>
14292              <bitRange>[1:1]</bitRange>
14293              <access>read-write</access>
14294            </field>
14295            <field>
14296              <name>CENTURY</name>
14297              <description>Mask bit for corresponding bit in interrupt request register.</description>
14298              <bitRange>[2:2]</bitRange>
14299              <access>read-write</access>
14300            </field>
14301          </fields>
14302        </register>
14303        <register>
14304          <name>INTR_MASKED</name>
14305          <description>Interrupt masked request register</description>
14306          <addressOffset>0x38</addressOffset>
14307          <size>32</size>
14308          <access>read-only</access>
14309          <resetValue>0x0</resetValue>
14310          <resetMask>0x7</resetMask>
14311          <fields>
14312            <field>
14313              <name>ALARM1</name>
14314              <description>Logical and of corresponding request and mask bits.</description>
14315              <bitRange>[0:0]</bitRange>
14316              <access>read-only</access>
14317            </field>
14318            <field>
14319              <name>ALARM2</name>
14320              <description>Logical and of corresponding request and mask bits.</description>
14321              <bitRange>[1:1]</bitRange>
14322              <access>read-only</access>
14323            </field>
14324            <field>
14325              <name>CENTURY</name>
14326              <description>Logical and of corresponding request and mask bits.</description>
14327              <bitRange>[2:2]</bitRange>
14328              <access>read-only</access>
14329            </field>
14330          </fields>
14331        </register>
14332        <register>
14333          <name>PMIC_CTL</name>
14334          <description>PMIC control register</description>
14335          <addressOffset>0x44</addressOffset>
14336          <size>32</size>
14337          <access>read-write</access>
14338          <resetValue>0xA0000000</resetValue>
14339          <resetMask>0xE001FF00</resetMask>
14340          <fields>
14341            <field>
14342              <name>UNLOCK</name>
14343              <description>This byte must be set to 0x3A for PMIC to be disabled.  When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN.  Do not change PMIC_EN in the same write cycle as setting/clearing the UNLOCK code; do these in separate write cycles.</description>
14344              <bitRange>[15:8]</bitRange>
14345              <access>read-write</access>
14346            </field>
14347            <field>
14348              <name>POLARITY</name>
14349              <description>N/A</description>
14350              <bitRange>[16:16]</bitRange>
14351              <access>read-write</access>
14352            </field>
14353            <field>
14354              <name>PMIC_EN_OUTEN</name>
14355              <description>Output enable for the output driver in the PMIC_EN pad.
143560: Output pad is tristate for PMIC_EN pin.  This can allow this pin to be used for another purpose. Tristate condition is kept only if the UNLOCK key (0x3A) is present
143571: Output pad is enabled for PMIC_EN pin.</description>
14358              <bitRange>[29:29]</bitRange>
14359              <access>read-write</access>
14360            </field>
14361            <field>
14362              <name>PMIC_ALWAYSEN</name>
14363              <description>Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware.
143640: Normal operation, PMIC_EN and PMIC_OUTEN work as described
143651: PMIC_EN and PMIC_OUTEN are ignored and the output pad is forced enabled.
14366Note: This bit is a write-once bit until the next backup reset.</description>
14367              <bitRange>[30:30]</bitRange>
14368              <access>read-write</access>
14369            </field>
14370            <field>
14371              <name>PMIC_EN</name>
14372              <description>Enable for external PMIC that supplies vddd (if present).  This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0.  When PMIC_EN=0, the system functions normally until vddd is no longer present (OFF w/Backup mode).  Firmware can set this bit, if it does so before vddd is actually removed.  This bit is also set by any RTC alarm or PMIC pin wakeup event regardless of UNLOCK setting.</description>
14373              <bitRange>[31:31]</bitRange>
14374              <access>read-write</access>
14375            </field>
14376          </fields>
14377        </register>
14378        <register>
14379          <name>RESET</name>
14380          <description>Backup reset register</description>
14381          <addressOffset>0x48</addressOffset>
14382          <size>32</size>
14383          <access>read-write</access>
14384          <resetValue>0x0</resetValue>
14385          <resetMask>0x80000000</resetMask>
14386          <fields>
14387            <field>
14388              <name>RESET</name>
14389              <description>Writing 1 to this register resets the backup logic.  Hardware clears it when the reset is complete.  After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers.</description>
14390              <bitRange>[31:31]</bitRange>
14391              <access>read-write</access>
14392            </field>
14393          </fields>
14394        </register>
14395        <register>
14396          <dim>64</dim>
14397          <dimIncrement>4</dimIncrement>
14398          <name>BREG[%s]</name>
14399          <description>Backup register region</description>
14400          <addressOffset>0x1000</addressOffset>
14401          <size>32</size>
14402          <access>read-write</access>
14403          <resetValue>0x0</resetValue>
14404          <resetMask>0xFFFFFFFF</resetMask>
14405          <fields>
14406            <field>
14407              <name>BREG</name>
14408              <description>Backup memory that contains application-specific data.  Memory is retained on vbackup supply.</description>
14409              <bitRange>[31:0]</bitRange>
14410              <access>read-write</access>
14411            </field>
14412          </fields>
14413        </register>
14414      </registers>
14415    </peripheral>
14416    <peripheral>
14417      <name>DW0</name>
14418      <description>Datawire Controller</description>
14419      <headerStructName>DW</headerStructName>
14420      <baseAddress>0x40280000</baseAddress>
14421      <addressBlock>
14422        <offset>0</offset>
14423        <size>65536</size>
14424        <usage>registers</usage>
14425      </addressBlock>
14426      <registers>
14427        <register>
14428          <name>CTL</name>
14429          <description>Control</description>
14430          <addressOffset>0x0</addressOffset>
14431          <size>32</size>
14432          <access>read-write</access>
14433          <resetValue>0x1</resetValue>
14434          <resetMask>0x80000003</resetMask>
14435          <fields>
14436            <field>
14437              <name>ECC_EN</name>
14438              <description>Enable ECC checking:
14439'0': Disabled.
14440'1': Enabled.</description>
14441              <bitRange>[0:0]</bitRange>
14442              <access>read-write</access>
14443            </field>
14444            <field>
14445              <name>ECC_INJ_EN</name>
14446              <description>Enable parity injection for SRAM.
14447When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM.</description>
14448              <bitRange>[1:1]</bitRange>
14449              <access>read-write</access>
14450            </field>
14451            <field>
14452              <name>ENABLED</name>
14453              <description>IP enable:
14454'0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected).
14455'1': Enabled.</description>
14456              <bitRange>[31:31]</bitRange>
14457              <access>read-write</access>
14458            </field>
14459          </fields>
14460        </register>
14461        <register>
14462          <name>STATUS</name>
14463          <description>Status</description>
14464          <addressOffset>0x4</addressOffset>
14465          <size>32</size>
14466          <access>read-only</access>
14467          <resetValue>0x0</resetValue>
14468          <resetMask>0xF0000000</resetMask>
14469          <fields>
14470            <field>
14471              <name>P</name>
14472              <description>Active channel, user/privileged access control:
14473'0': user mode.
14474'1': privileged mode.</description>
14475              <bitRange>[0:0]</bitRange>
14476              <access>read-only</access>
14477            </field>
14478            <field>
14479              <name>NS</name>
14480              <description>Active channel, secure/non-secure access control:
14481'0': secure.
14482'1': non-secure.</description>
14483              <bitRange>[1:1]</bitRange>
14484              <access>read-only</access>
14485            </field>
14486            <field>
14487              <name>B</name>
14488              <description>Active channel, non-bufferable/bufferable access control:
14489'0': non-bufferable
14490'1': bufferable.</description>
14491              <bitRange>[2:2]</bitRange>
14492              <access>read-only</access>
14493            </field>
14494            <field>
14495              <name>PC</name>
14496              <description>Active channel protection context.</description>
14497              <bitRange>[7:4]</bitRange>
14498              <access>read-only</access>
14499            </field>
14500            <field>
14501              <name>PRIO</name>
14502              <description>Active channel priority.</description>
14503              <bitRange>[9:8]</bitRange>
14504              <access>read-only</access>
14505            </field>
14506            <field>
14507              <name>PREEMPTABLE</name>
14508              <description>Active channel preemptable.</description>
14509              <bitRange>[11:11]</bitRange>
14510              <access>read-only</access>
14511            </field>
14512            <field>
14513              <name>CH_IDX</name>
14514              <description>Active channel index.</description>
14515              <bitRange>[24:16]</bitRange>
14516              <access>read-only</access>
14517            </field>
14518            <field>
14519              <name>STATE</name>
14520              <description>State of the DW controller.
14521'0': Default/inactive state.
14522'1': Loading descriptor.
14523'2': Loading data element from source location.
14524'3': Storing data element to destination location.
14525'4': CRC functionality (only used for CRC transfer descriptor type).
14526'5': Update of active control information (e.g. source and destination addresses) and wait for trigger de-activation.
14527'6': Error.</description>
14528              <bitRange>[30:28]</bitRange>
14529              <access>read-only</access>
14530            </field>
14531            <field>
14532              <name>ACTIVE</name>
14533              <description>Active channel present:
14534'0': No.
14535'1': Yes.</description>
14536              <bitRange>[31:31]</bitRange>
14537              <access>read-only</access>
14538            </field>
14539          </fields>
14540        </register>
14541        <register>
14542          <name>ACT_DESCR_CTL</name>
14543          <description>Active descriptor control</description>
14544          <addressOffset>0x20</addressOffset>
14545          <size>32</size>
14546          <access>read-only</access>
14547          <resetValue>0x0</resetValue>
14548          <resetMask>0x0</resetMask>
14549          <fields>
14550            <field>
14551              <name>DATA</name>
14552              <description>N/A</description>
14553              <bitRange>[31:0]</bitRange>
14554              <access>read-only</access>
14555            </field>
14556          </fields>
14557        </register>
14558        <register>
14559          <name>ACT_DESCR_SRC</name>
14560          <description>Active descriptor source</description>
14561          <addressOffset>0x24</addressOffset>
14562          <size>32</size>
14563          <access>read-only</access>
14564          <resetValue>0x0</resetValue>
14565          <resetMask>0x0</resetMask>
14566          <fields>
14567            <field>
14568              <name>DATA</name>
14569              <description>Copy of DESCR_SRC of the currently active descriptor.
14570
14571Base address of source location.</description>
14572              <bitRange>[31:0]</bitRange>
14573              <access>read-only</access>
14574            </field>
14575          </fields>
14576        </register>
14577        <register>
14578          <name>ACT_DESCR_DST</name>
14579          <description>Active descriptor destination</description>
14580          <addressOffset>0x28</addressOffset>
14581          <size>32</size>
14582          <access>read-only</access>
14583          <resetValue>0x0</resetValue>
14584          <resetMask>0x0</resetMask>
14585          <fields>
14586            <field>
14587              <name>DATA</name>
14588              <description>Copy of DESCR_DST of the currently active descriptor.
14589
14590Base address of destination location.
14591
14592Note: For a CRC transfer descriptor, this field should be programmed with the address of the CRC_LFSR_CTL register. The calculated CRC LFSR state is written to this address (through the CRYPTO AHB-Lite master interface) when the input trigger is processed. The write transfer will be submitted to the CPUSS and PERI protection schemes.</description>
14593              <bitRange>[31:0]</bitRange>
14594              <access>read-only</access>
14595            </field>
14596          </fields>
14597        </register>
14598        <register>
14599          <name>ACT_DESCR_X_CTL</name>
14600          <description>Active descriptor X loop control</description>
14601          <addressOffset>0x30</addressOffset>
14602          <size>32</size>
14603          <access>read-only</access>
14604          <resetValue>0x0</resetValue>
14605          <resetMask>0x0</resetMask>
14606          <fields>
14607            <field>
14608              <name>DATA</name>
14609              <description>Copy of DESCR_X_CTL of the currently active descriptor.
14610
14611[11:0] SRC_X_INCR
14612Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures.
14613
14614[23:12] DST_X_INCR
14615Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures.
14616
14617Note: this field is not used for CRC transfer descriptors and must be set to '0'.
14618
14619[31:24] X_COUNT
14620Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations.
14621
14622For a single transfer descriptor type, descriptor will not have X_CTL.</description>
14623              <bitRange>[31:0]</bitRange>
14624              <access>read-only</access>
14625            </field>
14626          </fields>
14627        </register>
14628        <register>
14629          <name>ACT_DESCR_Y_CTL</name>
14630          <description>Active descriptor Y loop control</description>
14631          <addressOffset>0x34</addressOffset>
14632          <size>32</size>
14633          <access>read-only</access>
14634          <resetValue>0x0</resetValue>
14635          <resetMask>0x0</resetMask>
14636          <fields>
14637            <field>
14638              <name>DATA</name>
14639              <description>Copy of DESCR_Y_CTL of the currently active descriptor.
14640
14641[11:0] SRC_Y_INCR
14642Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047].
14643
14644[23:12] DST_Y_INCR
14645Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047].
14646
14647[31:24] Y_COUNT
14648Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations.
14649
14650For single, 1D and CRC transfer descriptor types, descriptor will not have Y_CTL.</description>
14651              <bitRange>[31:0]</bitRange>
14652              <access>read-only</access>
14653            </field>
14654          </fields>
14655        </register>
14656        <register>
14657          <name>ACT_DESCR_NEXT_PTR</name>
14658          <description>Active descriptor next pointer</description>
14659          <addressOffset>0x38</addressOffset>
14660          <size>32</size>
14661          <access>read-only</access>
14662          <resetValue>0x0</resetValue>
14663          <resetMask>0x0</resetMask>
14664          <fields>
14665            <field>
14666              <name>ADDR</name>
14667              <description>Copy of DESCR_NEXT_PTR of the currently active descriptor.
14668
14669[31:2] ADDR
14670Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list.</description>
14671              <bitRange>[31:2]</bitRange>
14672              <access>read-only</access>
14673            </field>
14674          </fields>
14675        </register>
14676        <register>
14677          <name>ACT_SRC</name>
14678          <description>Active source</description>
14679          <addressOffset>0x40</addressOffset>
14680          <size>32</size>
14681          <access>read-only</access>
14682          <resetValue>0x0</resetValue>
14683          <resetMask>0x0</resetMask>
14684          <fields>
14685            <field>
14686              <name>SRC_ADDR</name>
14687              <description>Current address of source location.</description>
14688              <bitRange>[31:0]</bitRange>
14689              <access>read-only</access>
14690            </field>
14691          </fields>
14692        </register>
14693        <register>
14694          <name>ACT_DST</name>
14695          <description>Active destination</description>
14696          <addressOffset>0x44</addressOffset>
14697          <size>32</size>
14698          <access>read-only</access>
14699          <resetValue>0x0</resetValue>
14700          <resetMask>0x0</resetMask>
14701          <fields>
14702            <field>
14703              <name>DST_ADDR</name>
14704              <description>Current address of destination location.</description>
14705              <bitRange>[31:0]</bitRange>
14706              <access>read-only</access>
14707            </field>
14708          </fields>
14709        </register>
14710        <register>
14711          <name>ECC_CTL</name>
14712          <description>ECC control</description>
14713          <addressOffset>0x80</addressOffset>
14714          <size>32</size>
14715          <access>read-write</access>
14716          <resetValue>0x0</resetValue>
14717          <resetMask>0xFE0003FF</resetMask>
14718          <fields>
14719            <field>
14720              <name>WORD_ADDR</name>
14721              <description>Specifies the word address where an error will be injected.
14722- On a write transfer to this SRAM word address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected.</description>
14723              <bitRange>[9:0]</bitRange>
14724              <access>read-write</access>
14725            </field>
14726            <field>
14727              <name>PARITY</name>
14728              <description>ECC parity to use for ECC error injection at address WORD_ADDR.</description>
14729              <bitRange>[31:25]</bitRange>
14730              <access>read-write</access>
14731            </field>
14732          </fields>
14733        </register>
14734        <register>
14735          <name>CRC_CTL</name>
14736          <description>CRC control</description>
14737          <addressOffset>0x100</addressOffset>
14738          <size>32</size>
14739          <access>read-write</access>
14740          <resetValue>0x0</resetValue>
14741          <resetMask>0x101</resetMask>
14742          <fields>
14743            <field>
14744              <name>DATA_REVERSE</name>
14745              <description>Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):
14746'0': Most significant bit (bit 1) first.
14747'1': Least significant bit (bit 0) first.</description>
14748              <bitRange>[0:0]</bitRange>
14749              <access>read-write</access>
14750            </field>
14751            <field>
14752              <name>REM_REVERSE</name>
14753              <description>Specifies whether the remainder is bit reversed (reversal is performed after XORing):
14754'0': No.
14755'1': Yes.</description>
14756              <bitRange>[8:8]</bitRange>
14757              <access>read-write</access>
14758            </field>
14759          </fields>
14760        </register>
14761        <register>
14762          <name>CRC_DATA_CTL</name>
14763          <description>CRC data control</description>
14764          <addressOffset>0x110</addressOffset>
14765          <size>32</size>
14766          <access>read-write</access>
14767          <resetValue>0x0</resetValue>
14768          <resetMask>0xFF</resetMask>
14769          <fields>
14770            <field>
14771              <name>DATA_XOR</name>
14772              <description>Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal.</description>
14773              <bitRange>[7:0]</bitRange>
14774              <access>read-write</access>
14775            </field>
14776          </fields>
14777        </register>
14778        <register>
14779          <name>CRC_POL_CTL</name>
14780          <description>CRC polynomial control</description>
14781          <addressOffset>0x120</addressOffset>
14782          <size>32</size>
14783          <access>read-write</access>
14784          <resetValue>0x0</resetValue>
14785          <resetMask>0xFFFFFFFF</resetMask>
14786          <fields>
14787            <field>
14788              <name>POLYNOMIAL</name>
14789              <description>CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials:
14790- CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1).
14791- CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions).
14792- CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions).</description>
14793              <bitRange>[31:0]</bitRange>
14794              <access>read-write</access>
14795            </field>
14796          </fields>
14797        </register>
14798        <register>
14799          <name>CRC_LFSR_CTL</name>
14800          <description>CRC LFSR control</description>
14801          <addressOffset>0x130</addressOffset>
14802          <size>32</size>
14803          <access>read-write</access>
14804          <resetValue>0x0</resetValue>
14805          <resetMask>0xFFFFFFFF</resetMask>
14806          <fields>
14807            <field>
14808              <name>LFSR32</name>
14809              <description>State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value.
14810
14811The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's.
14812
14813Note that SW can write this field. This functionality can be used prevent information leakage (through either CRC_LFSR_CTL or CRC_REM_RESULT).</description>
14814              <bitRange>[31:0]</bitRange>
14815              <access>read-write</access>
14816            </field>
14817          </fields>
14818        </register>
14819        <register>
14820          <name>CRC_REM_CTL</name>
14821          <description>CRC remainder control</description>
14822          <addressOffset>0x140</addressOffset>
14823          <size>32</size>
14824          <access>read-write</access>
14825          <resetValue>0x0</resetValue>
14826          <resetMask>0xFFFFFFFF</resetMask>
14827          <fields>
14828            <field>
14829              <name>REM_XOR</name>
14830              <description>Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal.</description>
14831              <bitRange>[31:0]</bitRange>
14832              <access>read-write</access>
14833            </field>
14834          </fields>
14835        </register>
14836        <register>
14837          <name>CRC_REM_RESULT</name>
14838          <description>CRC remainder result</description>
14839          <addressOffset>0x148</addressOffset>
14840          <size>32</size>
14841          <access>read-only</access>
14842          <resetValue>0x0</resetValue>
14843          <resetMask>0xFFFFFFFF</resetMask>
14844          <fields>
14845            <field>
14846              <name>REM</name>
14847              <description>Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:
14848'0': the more significant bits (bit 31 and down) contain the remainder.
14849'1': the less significant bits (bit 0 and up) contain the remainder.
14850
14851Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_CTL.REM_REVERSE and CRC_REM_CTL.REM_XOR.</description>
14852              <bitRange>[31:0]</bitRange>
14853              <access>read-only</access>
14854            </field>
14855          </fields>
14856        </register>
14857        <cluster>
14858          <dim>89</dim>
14859          <dimIncrement>64</dimIncrement>
14860          <name>CH_STRUCT[%s]</name>
14861          <description>DW channel structure</description>
14862          <addressOffset>0x00008000</addressOffset>
14863          <register>
14864            <name>CH_CTL</name>
14865            <description>Channel control</description>
14866            <addressOffset>0x0</addressOffset>
14867            <size>32</size>
14868            <access>read-write</access>
14869            <resetValue>0x0</resetValue>
14870            <resetMask>0x80000300</resetMask>
14871            <fields>
14872              <field>
14873                <name>P</name>
14874                <description>User/privileged access control:
14875'0': user mode.
14876'1': privileged mode.
14877
14878This field is set with the user/privileged access control of the transaction that writes this register; i.e.  the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R).
14879
14880All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').</description>
14881                <bitRange>[0:0]</bitRange>
14882                <access>read-write</access>
14883              </field>
14884              <field>
14885                <name>NS</name>
14886                <description>Secure/on-secure access control:
14887'0': secure.
14888'1': non-secure.
14889
14890This field is set with the secure/non-secure access control of the transaction that writes this register; i.e.  the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R).
14891
14892All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').</description>
14893                <bitRange>[1:1]</bitRange>
14894                <access>read-write</access>
14895              </field>
14896              <field>
14897                <name>B</name>
14898                <description>Non-bufferable/bufferable access control:
14899'0': non-bufferable.
14900'1': bufferable.
14901
14902This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data.
14903
14904All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').</description>
14905                <bitRange>[2:2]</bitRange>
14906                <access>read-write</access>
14907              </field>
14908              <field>
14909                <name>PC</name>
14910                <description>Protection context.
14911
14912This field is set with the protection context of the transaction that writes this register;  i.e.  the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R).
14913
14914All transactions for this channel uses the PC field for the protection context.</description>
14915                <bitRange>[7:4]</bitRange>
14916                <access>read-write</access>
14917              </field>
14918              <field>
14919                <name>PRIO</name>
14920                <description>Channel priority:
14921'0': highest priority.
14922'1'
14923'2'
14924'3': lowest priority.
14925
14926Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, round robin arbitration is applied. Round robin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).</description>
14927                <bitRange>[9:8]</bitRange>
14928                <access>read-write</access>
14929              </field>
14930              <field>
14931                <name>PREEMPTABLE</name>
14932                <description>Specifies if the channel is preemptable.
14933'0': Not preemptable.
14934'1': Preemptable. This field allows higher priority pending channels (from a higher priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.</description>
14935                <bitRange>[11:11]</bitRange>
14936                <access>read-write</access>
14937              </field>
14938              <field>
14939                <name>ENABLED</name>
14940                <description>Channel enable:
14941'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed).
14942'1': Enabled.
14943
14944SW sets this field to '1' to enable a specific channel.
14945
14946HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).</description>
14947                <bitRange>[31:31]</bitRange>
14948                <access>read-write</access>
14949              </field>
14950            </fields>
14951          </register>
14952          <register>
14953            <name>CH_STATUS</name>
14954            <description>Channel status</description>
14955            <addressOffset>0x4</addressOffset>
14956            <size>32</size>
14957            <access>read-only</access>
14958            <resetValue>0x0</resetValue>
14959            <resetMask>0x80000000</resetMask>
14960            <fields>
14961              <field>
14962                <name>INTR_CAUSE</name>
14963                <description>Specifies the source of the interrupt cause:
14964'0': No interrupt generated
14965'1': Interrupt based on transfer complettion configuration based on INTR_TYPE
14966'2': Source transfer bus error
14967'3': Destination transfer bus error
14968'4': Source address misalignment
14969'5': Destination address misalignment
14970'6': Current descriptor pointer is null
14971'7': Active channel is disabled
14972'8': Descriptor bus error
14973'9'-'15': Not used.
14974
14975For error related interrupt causes (INTR_CAUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').</description>
14976                <bitRange>[3:0]</bitRange>
14977                <access>read-only</access>
14978              </field>
14979              <field>
14980                <name>PENDING</name>
14981                <description>Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)).</description>
14982                <bitRange>[31:31]</bitRange>
14983                <access>read-only</access>
14984              </field>
14985            </fields>
14986          </register>
14987          <register>
14988            <name>CH_IDX</name>
14989            <description>Channel current indices</description>
14990            <addressOffset>0x8</addressOffset>
14991            <size>32</size>
14992            <access>read-write</access>
14993            <resetValue>0x0</resetValue>
14994            <resetMask>0x0</resetMask>
14995            <fields>
14996              <field>
14997                <name>X_IDX</name>
14998                <description>Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor.
14999
15000Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.
15001
15002Note: SW should set this field to '0' when it updates CH_CURR_PTR.</description>
15003                <bitRange>[7:0]</bitRange>
15004                <access>read-write</access>
15005              </field>
15006              <field>
15007                <name>Y_IDX</name>
15008                <description>Specifies the Y loop index, with X_COUNT taken from the current descriptor.
15009
15010Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.
15011
15012Note: SW should set this field to '0' when it updates CH_CURR_PTR.</description>
15013                <bitRange>[15:8]</bitRange>
15014                <access>read-write</access>
15015              </field>
15016            </fields>
15017          </register>
15018          <register>
15019            <name>CH_CURR_PTR</name>
15020            <description>Channel current descriptor pointer</description>
15021            <addressOffset>0xC</addressOffset>
15022            <size>32</size>
15023            <access>read-write</access>
15024            <resetValue>0x0</resetValue>
15025            <resetMask>0x0</resetMask>
15026            <fields>
15027              <field>
15028                <name>ADDR</name>
15029                <description>Address of current descriptor. When this field is '0', there is no valid descriptor.
15030
15031Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.
15032
15033Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.</description>
15034                <bitRange>[31:2]</bitRange>
15035                <access>read-write</access>
15036              </field>
15037            </fields>
15038          </register>
15039          <register>
15040            <name>INTR</name>
15041            <description>Interrupt</description>
15042            <addressOffset>0x10</addressOffset>
15043            <size>32</size>
15044            <access>read-write</access>
15045            <resetValue>0x0</resetValue>
15046            <resetMask>0x1</resetMask>
15047            <fields>
15048              <field>
15049                <name>CH</name>
15050                <description>Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.</description>
15051                <bitRange>[0:0]</bitRange>
15052                <access>read-write</access>
15053              </field>
15054            </fields>
15055          </register>
15056          <register>
15057            <name>INTR_SET</name>
15058            <description>Interrupt set</description>
15059            <addressOffset>0x14</addressOffset>
15060            <size>32</size>
15061            <access>read-write</access>
15062            <resetValue>0x0</resetValue>
15063            <resetMask>0x1</resetMask>
15064            <fields>
15065              <field>
15066                <name>CH</name>
15067                <description>Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).</description>
15068                <bitRange>[0:0]</bitRange>
15069                <access>read-write</access>
15070              </field>
15071            </fields>
15072          </register>
15073          <register>
15074            <name>INTR_MASK</name>
15075            <description>Interrupt mask</description>
15076            <addressOffset>0x18</addressOffset>
15077            <size>32</size>
15078            <access>read-write</access>
15079            <resetValue>0x0</resetValue>
15080            <resetMask>0x1</resetMask>
15081            <fields>
15082              <field>
15083                <name>CH</name>
15084                <description>Mask for corresponding field in INTR register.</description>
15085                <bitRange>[0:0]</bitRange>
15086                <access>read-write</access>
15087              </field>
15088            </fields>
15089          </register>
15090          <register>
15091            <name>INTR_MASKED</name>
15092            <description>Interrupt masked</description>
15093            <addressOffset>0x1C</addressOffset>
15094            <size>32</size>
15095            <access>read-only</access>
15096            <resetValue>0x0</resetValue>
15097            <resetMask>0x1</resetMask>
15098            <fields>
15099              <field>
15100                <name>CH</name>
15101                <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
15102                <bitRange>[0:0]</bitRange>
15103                <access>read-only</access>
15104              </field>
15105            </fields>
15106          </register>
15107          <register>
15108            <name>SRAM_DATA0</name>
15109            <description>SRAM data 0</description>
15110            <addressOffset>0x20</addressOffset>
15111            <size>32</size>
15112            <access>read-write</access>
15113            <resetValue>0x0</resetValue>
15114            <resetMask>0x0</resetMask>
15115            <fields>
15116              <field>
15117                <name>DATA</name>
15118                <description>N/A</description>
15119                <bitRange>[31:0]</bitRange>
15120                <access>read-write</access>
15121              </field>
15122            </fields>
15123          </register>
15124          <register>
15125            <name>SRAM_DATA1</name>
15126            <description>SRAM data 1</description>
15127            <addressOffset>0x24</addressOffset>
15128            <size>32</size>
15129            <access>read-write</access>
15130            <resetValue>0x0</resetValue>
15131            <resetMask>0x0</resetMask>
15132            <fields>
15133              <field>
15134                <name>DATA</name>
15135                <description>N/A</description>
15136                <bitRange>[31:0]</bitRange>
15137                <access>read-write</access>
15138              </field>
15139            </fields>
15140          </register>
15141          <register>
15142            <name>TR_CMD</name>
15143            <description>Channel software trigger</description>
15144            <addressOffset>0x28</addressOffset>
15145            <size>32</size>
15146            <access>read-write</access>
15147            <resetValue>0x0</resetValue>
15148            <resetMask>0x1</resetMask>
15149            <fields>
15150              <field>
15151                <name>ACTIVATE</name>
15152                <description>Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0.</description>
15153                <bitRange>[0:0]</bitRange>
15154                <access>read-write</access>
15155              </field>
15156            </fields>
15157          </register>
15158        </cluster>
15159      </registers>
15160    </peripheral>
15161    <peripheral derivedFrom="DW0">
15162      <name>DW1</name>
15163      <baseAddress>0x40290000</baseAddress>
15164    </peripheral>
15165    <peripheral>
15166      <name>DMAC</name>
15167      <description>DMAC</description>
15168      <baseAddress>0x402A0000</baseAddress>
15169      <addressBlock>
15170        <offset>0</offset>
15171        <size>65536</size>
15172        <usage>registers</usage>
15173      </addressBlock>
15174      <registers>
15175        <register>
15176          <name>CTL</name>
15177          <description>Control</description>
15178          <addressOffset>0x0</addressOffset>
15179          <size>32</size>
15180          <access>read-write</access>
15181          <resetValue>0x0</resetValue>
15182          <resetMask>0x80000000</resetMask>
15183          <fields>
15184            <field>
15185              <name>ENABLED</name>
15186              <description>IP enable:
15187'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled.
15188'1': Enabled.</description>
15189              <bitRange>[31:31]</bitRange>
15190              <access>read-write</access>
15191              <enumeratedValues>
15192                <enumeratedValue>
15193                  <name>DISABLED</name>
15194                  <description>N/A</description>
15195                  <value>0</value>
15196                </enumeratedValue>
15197                <enumeratedValue>
15198                  <name>ENABLED</name>
15199                  <description>N/A</description>
15200                  <value>1</value>
15201                </enumeratedValue>
15202              </enumeratedValues>
15203            </field>
15204          </fields>
15205        </register>
15206        <register>
15207          <name>ACTIVE</name>
15208          <description>Active channels</description>
15209          <addressOffset>0x8</addressOffset>
15210          <size>32</size>
15211          <access>read-only</access>
15212          <resetValue>0x0</resetValue>
15213          <resetMask>0xFF</resetMask>
15214          <fields>
15215            <field>
15216              <name>ACTIVE</name>
15217              <description>Specifies active channels; i.e. enabled channels whose trigger got activated.</description>
15218              <bitRange>[7:0]</bitRange>
15219              <access>read-only</access>
15220            </field>
15221          </fields>
15222        </register>
15223        <cluster>
15224          <dim>4</dim>
15225          <dimIncrement>256</dimIncrement>
15226          <name>CH[%s]</name>
15227          <description>DMA controller channel</description>
15228          <addressOffset>0x00001000</addressOffset>
15229          <register>
15230            <name>CTL</name>
15231            <description>Channel control</description>
15232            <addressOffset>0x0</addressOffset>
15233            <size>32</size>
15234            <access>read-write</access>
15235            <resetValue>0x2</resetValue>
15236            <resetMask>0x800003F7</resetMask>
15237            <fields>
15238              <field>
15239                <name>P</name>
15240                <description>User/privileged access control:
15241'0': user mode.
15242'1': privileged mode.
15243
15244This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data.
15245
15246All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').</description>
15247                <bitRange>[0:0]</bitRange>
15248                <access>read-write</access>
15249              </field>
15250              <field>
15251                <name>NS</name>
15252                <description>Secure/on-secure access control:
15253'0': secure.
15254'1': non-secure.
15255
15256This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data.
15257
15258All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').</description>
15259                <bitRange>[1:1]</bitRange>
15260                <access>read-write</access>
15261              </field>
15262              <field>
15263                <name>B</name>
15264                <description>Non-bufferable/bufferable access control:
15265'0': non-bufferable.
15266'1': bufferable.
15267
15268This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data.
15269
15270All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').</description>
15271                <bitRange>[2:2]</bitRange>
15272                <access>read-write</access>
15273              </field>
15274              <field>
15275                <name>PC</name>
15276                <description>Protection context.
15277
15278This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data.
15279
15280All transactions for this channel uses the PC field for the protection context.</description>
15281                <bitRange>[7:4]</bitRange>
15282                <access>read-write</access>
15283              </field>
15284              <field>
15285                <name>PRIO</name>
15286                <description>Channel priority:
15287'0': highest priority.
15288'1'
15289'2'
15290'3': lowest priority.
15291
15292Channels with the same priority constitute a priority group and within this priority group, the following 'roundrobin' arbitration is applied.
15293A 'round' consists of a contiguous sequence of channel activations, within this priority group, without any repetition. Within a round, higher priority is given to the lower channel indices. The notion of a round guarantees that within a group, higher channel indices do not yield to lower indices indefinitely.</description>
15294                <bitRange>[9:8]</bitRange>
15295                <access>read-write</access>
15296              </field>
15297              <field>
15298                <name>ENABLED</name>
15299                <description>Channel enable:
15300'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed).
15301'1': Enabled.
15302
15303SW sets this field to '1' to enable a specific channel.
15304
15305HW sets this field to '0' when an error interrupt cause is activated.</description>
15306                <bitRange>[31:31]</bitRange>
15307                <access>read-write</access>
15308              </field>
15309            </fields>
15310          </register>
15311          <register>
15312            <name>IDX</name>
15313            <description>Channel current indices</description>
15314            <addressOffset>0x10</addressOffset>
15315            <size>32</size>
15316            <access>read-only</access>
15317            <resetValue>0x0</resetValue>
15318            <resetMask>0x0</resetMask>
15319            <fields>
15320              <field>
15321                <name>X</name>
15322                <description>Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor.
15323
15324Note: HW sets this field to '0' when it loads a descriptor.</description>
15325                <bitRange>[15:0]</bitRange>
15326                <access>read-only</access>
15327              </field>
15328              <field>
15329                <name>Y</name>
15330                <description>Specifies the Y loop index, with Y_COUNT taken from the current descriptor.
15331
15332Note: HW sets this field to '0' when it loads a descriptor..</description>
15333                <bitRange>[31:16]</bitRange>
15334                <access>read-only</access>
15335              </field>
15336            </fields>
15337          </register>
15338          <register>
15339            <name>SRC</name>
15340            <description>Channel current source address</description>
15341            <addressOffset>0x14</addressOffset>
15342            <size>32</size>
15343            <access>read-only</access>
15344            <resetValue>0x0</resetValue>
15345            <resetMask>0x0</resetMask>
15346            <fields>
15347              <field>
15348                <name>ADDR</name>
15349                <description>Current address of source location.</description>
15350                <bitRange>[31:0]</bitRange>
15351                <access>read-only</access>
15352              </field>
15353            </fields>
15354          </register>
15355          <register>
15356            <name>DST</name>
15357            <description>Channel current destination address</description>
15358            <addressOffset>0x18</addressOffset>
15359            <size>32</size>
15360            <access>read-only</access>
15361            <resetValue>0x0</resetValue>
15362            <resetMask>0x0</resetMask>
15363            <fields>
15364              <field>
15365                <name>ADDR</name>
15366                <description>Current address of destination location.</description>
15367                <bitRange>[31:0]</bitRange>
15368                <access>read-only</access>
15369              </field>
15370            </fields>
15371          </register>
15372          <register>
15373            <name>CURR</name>
15374            <description>Channel current descriptor pointer</description>
15375            <addressOffset>0x20</addressOffset>
15376            <size>32</size>
15377            <access>read-write</access>
15378            <resetValue>0x0</resetValue>
15379            <resetMask>0x0</resetMask>
15380            <fields>
15381              <field>
15382                <name>PTR</name>
15383                <description>Address of current descriptor. When this field is '0', there is no valid descriptor.
15384
15385Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.</description>
15386                <bitRange>[31:2]</bitRange>
15387                <access>read-write</access>
15388              </field>
15389            </fields>
15390          </register>
15391          <register>
15392            <name>TR_CMD</name>
15393            <description>Channle software trigger</description>
15394            <addressOffset>0x28</addressOffset>
15395            <size>32</size>
15396            <access>read-write</access>
15397            <resetValue>0x0</resetValue>
15398            <resetMask>0x1</resetMask>
15399            <fields>
15400              <field>
15401                <name>ACTIVATE</name>
15402                <description>Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0.</description>
15403                <bitRange>[0:0]</bitRange>
15404                <access>read-write</access>
15405              </field>
15406            </fields>
15407          </register>
15408          <register>
15409            <name>DESCR_STATUS</name>
15410            <description>Channel descriptor status</description>
15411            <addressOffset>0x40</addressOffset>
15412            <size>32</size>
15413            <access>read-only</access>
15414            <resetValue>0x0</resetValue>
15415            <resetMask>0x80000000</resetMask>
15416            <fields>
15417              <field>
15418                <name>VALID</name>
15419                <description>Indicates whether the descriptor information present in DESCR_CTL, DESCR_SRC, DESCR_DST, DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE, DESCR_Y_INCR, DESCR_NEXT status registers is valid or not.</description>
15420                <bitRange>[31:31]</bitRange>
15421                <access>read-only</access>
15422              </field>
15423            </fields>
15424          </register>
15425          <register>
15426            <name>DESCR_CTL</name>
15427            <description>Channel descriptor control</description>
15428            <addressOffset>0x60</addressOffset>
15429            <size>32</size>
15430            <access>read-only</access>
15431            <resetValue>0x0</resetValue>
15432            <resetMask>0x0</resetMask>
15433            <fields>
15434              <field>
15435                <name>WAIT_FOR_DEACT</name>
15436                <description>Specifies whether the controller should wait for the input trigger to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller with the agent that generated the trigger. This field is ONLY used at the completion of the transfer as specified by TR_IN. E.g., a TX FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the controller AND received by the agent.  Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW controller performance.
15437'0': Do not wait for trigger de-activation (for pulse sensitive triggers).
15438'1': Wait for up to 4 cycles.
15439'2': Wait for up to 16 cycles.
15440'3': Wait indefinitely. This option may result in controller lockup if the trigger is not de-activated.</description>
15441                <bitRange>[1:0]</bitRange>
15442                <access>read-only</access>
15443              </field>
15444              <field>
15445                <name>INTR_TYPE</name>
15446                <description>Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION):
15447'0': An interrupt is generated after a single transfer.
15448'1': An interrupt is generated after a single 1D transfer or a memory copy transfer
15449- If the descriptor type is 'single', the interrupt is generated after a single transfer.
15450- If the descriptor type is '1D' or '2D', the interrupt is generated after the execution of a 1D transfer.
15451- If the descriptor type is 'memory copy', the interrupt is generated after the execution of a memory copy transfer.
15452- If the descriptor type is 'scatter' the interrupt is generated after the execution of a scatter transfer.
15453'2': An interrupt is generated after the execution of the current descriptor (independent of the value of DESCR_NEXT_PTR.ADDR of the current descriptor).
15454'3': An interrupt is generated after the execution of the current descriptor and the current descriptor's DESCR_NEXT_PTR.ADDR is '0'.</description>
15455                <bitRange>[3:2]</bitRange>
15456                <access>read-only</access>
15457              </field>
15458              <field>
15459                <name>TR_OUT_TYPE</name>
15460                <description>Specifies when an output trigger is generated:
15461'0': An output trigger is generated after a single transfer.
15462'1': An output trigger is generated after a single 1D transfer or a memory copy transfer.
15463- If the descriptor type is 'single', the output trigger is generated after a single transfer.
15464- If the descriptor type is '1D' or '2D', the output trigger is generated after the execution of a 1D transfer.
15465- If the descriptor type is 'memory copy', the output trigger is generated after the execution of a memory copy transfer.
15466- If the descriptor type is 'scatter', the output trigger is generated after the execution of a scatter transfer.
15467'2': An output trigger is generated after the execution of the current descriptor.
15468'3': An output trigger is generated after the execution of a descriptor list: after the execution of the current descriptor AND the current descriptor's DESCR_NEXT_PTR.ADDR is '0'.</description>
15469                <bitRange>[5:4]</bitRange>
15470                <access>read-only</access>
15471              </field>
15472              <field>
15473                <name>TR_IN_TYPE</name>
15474                <description>Specifies the input trigger type (not to be confused with the descriptor type):
15475'0': A trigger results in the execution of a single transfer. The descriptor type can be single, 1D or 2D.
15476'1': A trigger results in the execution of a single 1D transfer.
15477- If the descriptor type is 'single', the trigger results in the execution of a single transfer.
15478- If the descriptor type is '1D' or '2D', the trigger results in the execution of a 1D transfer.
15479- If the descriptor type is 'memory copy', the trigger results in the execution of a memory copy transfer.
15480- If the descriptor type is 'scatter', the trigger results in the execution of an scatter transfer.
15481'2': A trigger results in the execution of the current descriptor.
15482'3': A trigger results in the execution of the current descriptor and continues (without requiring another input trigger) with the execution of the next descriptor using the next descriptor's information.</description>
15483                <bitRange>[7:6]</bitRange>
15484                <access>read-only</access>
15485              </field>
15486              <field>
15487                <name>DATA_PREFETCH</name>
15488                <description>Source data prefetch:
15489'0': No source data prefetch. Source data transfers are only initiated AFTER the input trigger is activated.
15490'1': Source data prefetch. Source data transfers are initiated as soon as the channel is enabled, the current descriptor pointer is NOT '0' and there is space available in the channel's data FIFO. When the input trigger is activated, the trigger can initiate destination data transfers with data that is already in the channel's data FIFO. This effectively shortens the initial delay of the data transfer.
15491
15492Note: data prefetch should be used with care, to ensure that data coherency is guaranteed and that prefetches do not cause undesired side effects.</description>
15493                <bitRange>[8:8]</bitRange>
15494                <access>read-only</access>
15495              </field>
15496              <field>
15497                <name>DATA_SIZE</name>
15498                <description>Specifies the data element size:
15499'0': Byte (8 bits).
15500'1': Halfword (16 bits).
15501'2': Word (32 bits).
15502DATA_SIZE, SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE together determine how data elements are transferred. The following are the 9 legal settings:
15503- DATA is 8 bit, SRC is 8 bit, DST is 8 bit.
15504- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 8 bit.
15505- DATA is 8 bit, SRC is 8 bit, DST is 32 bit (higher 24 bits are made '0').
15506- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 32 bit (higher 24 bits are made '0').
15507- DATA is 16 bit, SRC is 16 bit, DST is 16 bit.
15508- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 16 bit.
15509- DATA is 16 bit, SRC is 16 bit, DST is 32 bit (higher 16 bits are made '0').
15510- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 32 bit (higher 16 bits are made '0').
15511- DATA is 32 bit, SRC is 32 bit, DST is 32 bit.
15512
15513Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '2' for a 'initialization' descriptor type.</description>
15514                <bitRange>[17:16]</bitRange>
15515                <access>read-only</access>
15516              </field>
15517              <field>
15518                <name>CH_DISABLE</name>
15519                <description>Specifies whether the channel is disabled or not after completion of the current descriptor (independent of the value of the DESCR_NEXT_PTR value):
15520'0': Channel is not disabled.
15521'1': Channel is disabled.</description>
15522                <bitRange>[24:24]</bitRange>
15523                <access>read-only</access>
15524              </field>
15525              <field>
15526                <name>SRC_TRANSFER_SIZE</name>
15527                <description>Specifies the bus transfer size to the source location:
15528'0': As specified by DATA_SIZE.
15529'1': Word (32 bits).
15530Distinguishing bus transfer size from data element size allows for source components with data elements that are smaller than their 32-bit bus interface width. E.g., an ADC source has a 32-bit bus transfer size, but only provides a 16-bit data element.
15531
15532Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type.</description>
15533                <bitRange>[26:26]</bitRange>
15534                <access>read-only</access>
15535              </field>
15536              <field>
15537                <name>DST_TRANSFER_SIZE</name>
15538                <description>Specifies the bus transfer size to the destination location:
15539'0': As specified by DATA_SIZE.
15540'1': Word (32 bits).
15541Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width. E.g., a DAC destination has a 32-bit bus transfer size, but only requires a 16-bit data element.
15542
15543Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type.</description>
15544                <bitRange>[27:27]</bitRange>
15545                <access>read-only</access>
15546              </field>
15547              <field>
15548                <name>DESCR_TYPE</name>
15549                <description>Specifies the descriptor type (not to be confused with the trigger type):
15550'0': Single transfer.
15551The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are NOT present. The DESCR_NEXT_PTR is at offset 0x0c.
15552'1': 1D transfer.
15553The DESCR_X_SIZE and DESCR_X_INCR registers are present, the DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A 1D transfer consists out of DESCR_X_SIZE.X_COUNT+1 single transfers. The DESCR_NEXT_PTR is at offset 0x14.
15554'2': 2D transfer.
15555The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are present. A 2D transfer consists of (DESCR_X_SIZE.X_COUNT+1)*(DESCR_Y_SIZE.Y_COUNT+1) single transfers. The DESCR_NEXT_PTR is at offset 0x1c.
15556'3': Memory copy.
15557The DESCR_X_SIZE register is present, the DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A memory copy transfer copies DESCR_X_SIZE.X_COUNT+1 Bytes and may use Byte, halfword and word transfers. The DESCR_NEXT_PTR is at offset 0x10.
15558'4': Scatter transfer. The DESCR_X_SIZE register is present, the DESCR_DST, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present.
15559'5'-'7': Undefined.
15560
15561After the execution of the current descriptor, the DESCR_NEXT_PTR address is copied to the channel's CH_CURR_PTR address and CH_STATUS.X_IDX and CH_STATUS.Y_IDX are set to '0'.</description>
15562                <bitRange>[30:28]</bitRange>
15563                <access>read-only</access>
15564              </field>
15565            </fields>
15566          </register>
15567          <register>
15568            <name>DESCR_SRC</name>
15569            <description>Channel descriptor source</description>
15570            <addressOffset>0x64</addressOffset>
15571            <size>32</size>
15572            <access>read-only</access>
15573            <resetValue>0x0</resetValue>
15574            <resetMask>0x0</resetMask>
15575            <fields>
15576              <field>
15577                <name>ADDR</name>
15578                <description>Base address of source location.</description>
15579                <bitRange>[31:0]</bitRange>
15580                <access>read-only</access>
15581              </field>
15582            </fields>
15583          </register>
15584          <register>
15585            <name>DESCR_DST</name>
15586            <description>Channel descriptor destination</description>
15587            <addressOffset>0x68</addressOffset>
15588            <size>32</size>
15589            <access>read-only</access>
15590            <resetValue>0x0</resetValue>
15591            <resetMask>0x0</resetMask>
15592            <fields>
15593              <field>
15594                <name>ADDR</name>
15595                <description>Base address of destination location.</description>
15596                <bitRange>[31:0]</bitRange>
15597                <access>read-only</access>
15598              </field>
15599            </fields>
15600          </register>
15601          <register>
15602            <name>DESCR_X_SIZE</name>
15603            <description>Channel descriptor X size</description>
15604            <addressOffset>0x6C</addressOffset>
15605            <size>32</size>
15606            <access>read-only</access>
15607            <resetValue>0x0</resetValue>
15608            <resetMask>0x0</resetMask>
15609            <fields>
15610              <field>
15611                <name>X_COUNT</name>
15612                <description>Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations.
15613
15614For the 'memory copy' descriptor type, (X_COUNT + 1) is the number of transferred Bytes. For the 'scatter' descriptor type, ceiling(X_COUNT/2) is the number of (address, write data) initialization pairs processed.</description>
15615                <bitRange>[15:0]</bitRange>
15616                <access>read-only</access>
15617              </field>
15618            </fields>
15619          </register>
15620          <register>
15621            <name>DESCR_X_INCR</name>
15622            <description>Channel descriptor X increment</description>
15623            <addressOffset>0x70</addressOffset>
15624            <size>32</size>
15625            <access>read-only</access>
15626            <resetValue>0x0</resetValue>
15627            <resetMask>0x0</resetMask>
15628            <fields>
15629              <field>
15630                <name>SRC_X</name>
15631                <description>Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures.</description>
15632                <bitRange>[15:0]</bitRange>
15633                <access>read-only</access>
15634              </field>
15635              <field>
15636                <name>DST_X</name>
15637                <description>Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures.</description>
15638                <bitRange>[31:16]</bitRange>
15639                <access>read-only</access>
15640              </field>
15641            </fields>
15642          </register>
15643          <register>
15644            <name>DESCR_Y_SIZE</name>
15645            <description>Channel descriptor Y size</description>
15646            <addressOffset>0x74</addressOffset>
15647            <size>32</size>
15648            <access>read-only</access>
15649            <resetValue>0x0</resetValue>
15650            <resetMask>0x0</resetMask>
15651            <fields>
15652              <field>
15653                <name>Y_COUNT</name>
15654                <description>Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations.</description>
15655                <bitRange>[15:0]</bitRange>
15656                <access>read-only</access>
15657              </field>
15658            </fields>
15659          </register>
15660          <register>
15661            <name>DESCR_Y_INCR</name>
15662            <description>Channel descriptor Y increment</description>
15663            <addressOffset>0x78</addressOffset>
15664            <size>32</size>
15665            <access>read-only</access>
15666            <resetValue>0x0</resetValue>
15667            <resetMask>0x0</resetMask>
15668            <fields>
15669              <field>
15670                <name>SRC_Y</name>
15671                <description>Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767].</description>
15672                <bitRange>[15:0]</bitRange>
15673                <access>read-only</access>
15674              </field>
15675              <field>
15676                <name>DST_Y</name>
15677                <description>Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767].</description>
15678                <bitRange>[31:16]</bitRange>
15679                <access>read-only</access>
15680              </field>
15681            </fields>
15682          </register>
15683          <register>
15684            <name>DESCR_NEXT</name>
15685            <description>Channel descriptor next pointer</description>
15686            <addressOffset>0x7C</addressOffset>
15687            <size>32</size>
15688            <access>read-only</access>
15689            <resetValue>0x0</resetValue>
15690            <resetMask>0x0</resetMask>
15691            <fields>
15692              <field>
15693                <name>PTR</name>
15694                <description>Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list.</description>
15695                <bitRange>[31:2]</bitRange>
15696                <access>read-only</access>
15697              </field>
15698            </fields>
15699          </register>
15700          <register>
15701            <name>INTR</name>
15702            <description>Interrupt</description>
15703            <addressOffset>0x80</addressOffset>
15704            <size>32</size>
15705            <access>read-write</access>
15706            <resetValue>0x0</resetValue>
15707            <resetMask>0xFF</resetMask>
15708            <fields>
15709              <field>
15710                <name>COMPLETION</name>
15711                <description>Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE.</description>
15712                <bitRange>[0:0]</bitRange>
15713                <access>read-write</access>
15714              </field>
15715              <field>
15716                <name>SRC_BUS_ERROR</name>
15717                <description>Activated (set to '1') on a bus error for a load from the source.</description>
15718                <bitRange>[1:1]</bitRange>
15719                <access>read-write</access>
15720              </field>
15721              <field>
15722                <name>DST_BUS_ERROR</name>
15723                <description>Activated (set to '1') on a bus error for a store to the destination.</description>
15724                <bitRange>[2:2]</bitRange>
15725                <access>read-write</access>
15726              </field>
15727              <field>
15728                <name>SRC_MISAL</name>
15729                <description>Activated (set to '1') on a misalignment of the source address.</description>
15730                <bitRange>[3:3]</bitRange>
15731                <access>read-write</access>
15732              </field>
15733              <field>
15734                <name>DST_MISAL</name>
15735                <description>Activated (set to '1') on a misalignment of the destination address.</description>
15736                <bitRange>[4:4]</bitRange>
15737                <access>read-write</access>
15738              </field>
15739              <field>
15740                <name>CURR_PTR_NULL</name>
15741                <description>Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'.</description>
15742                <bitRange>[5:5]</bitRange>
15743                <access>read-write</access>
15744              </field>
15745              <field>
15746                <name>ACTIVE_CH_DISABLED</name>
15747                <description>Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy.</description>
15748                <bitRange>[6:6]</bitRange>
15749                <access>read-write</access>
15750              </field>
15751              <field>
15752                <name>DESCR_BUS_ERROR</name>
15753                <description>Activated (set to '1') on a bus error for a load of the descriptor.</description>
15754                <bitRange>[7:7]</bitRange>
15755                <access>read-write</access>
15756              </field>
15757            </fields>
15758          </register>
15759          <register>
15760            <name>INTR_SET</name>
15761            <description>Interrupt set</description>
15762            <addressOffset>0x84</addressOffset>
15763            <size>32</size>
15764            <access>read-write</access>
15765            <resetValue>0x0</resetValue>
15766            <resetMask>0xFF</resetMask>
15767            <fields>
15768              <field>
15769                <name>COMPLETION</name>
15770                <description>Write this field with '1' to set INTR.COMPLETION field to '1' (a write of '0' has no effect).</description>
15771                <bitRange>[0:0]</bitRange>
15772                <access>read-write</access>
15773              </field>
15774              <field>
15775                <name>SRC_BUS_ERROR</name>
15776                <description>Write this field with '1' to set INTR.SRC_BUS_ERROR field to '1' (a write of '0' has no effect).</description>
15777                <bitRange>[1:1]</bitRange>
15778                <access>read-write</access>
15779              </field>
15780              <field>
15781                <name>DST_BUS_ERROR</name>
15782                <description>Write this field with '1' to set INTR.DST_BUS_ERROR field to '1' (a write of '0' has no effect).</description>
15783                <bitRange>[2:2]</bitRange>
15784                <access>read-write</access>
15785              </field>
15786              <field>
15787                <name>SRC_MISAL</name>
15788                <description>Write this field with '1' to set INTR.SRC_MISAL field to '1' (a write of '0' has no effect).</description>
15789                <bitRange>[3:3]</bitRange>
15790                <access>read-write</access>
15791              </field>
15792              <field>
15793                <name>DST_MISAL</name>
15794                <description>Write this field with '1' to set INTR.DST_MISAL field to '1' (a write of '0' has no effect).</description>
15795                <bitRange>[4:4]</bitRange>
15796                <access>read-write</access>
15797              </field>
15798              <field>
15799                <name>CURR_PTR_NULL</name>
15800                <description>Write this field with '1' to set INTR.CURR_PTR_NULL field to '1' (a write of '0' has no effect).</description>
15801                <bitRange>[5:5]</bitRange>
15802                <access>read-write</access>
15803              </field>
15804              <field>
15805                <name>ACTIVE_CH_DISABLED</name>
15806                <description>Write this field with '1' to set INTR.ACT_CH_DISABLED field to '1' (a write of '0' has no effect).</description>
15807                <bitRange>[6:6]</bitRange>
15808                <access>read-write</access>
15809              </field>
15810              <field>
15811                <name>DESCR_BUS_ERROR</name>
15812                <description>Write this field with '1' to set INTR.DESCR_BUS_ERROR field to '1' (a write of '0' has no effect).</description>
15813                <bitRange>[7:7]</bitRange>
15814                <access>read-write</access>
15815              </field>
15816            </fields>
15817          </register>
15818          <register>
15819            <name>INTR_MASK</name>
15820            <description>Interrupt mask</description>
15821            <addressOffset>0x88</addressOffset>
15822            <size>32</size>
15823            <access>read-write</access>
15824            <resetValue>0x0</resetValue>
15825            <resetMask>0xFF</resetMask>
15826            <fields>
15827              <field>
15828                <name>COMPLETION</name>
15829                <description>Mask for INTR.COMPLETION interrupt.</description>
15830                <bitRange>[0:0]</bitRange>
15831                <access>read-write</access>
15832              </field>
15833              <field>
15834                <name>SRC_BUS_ERROR</name>
15835                <description>Mask for INTR.SRC_BUS_ERROR interrupt.</description>
15836                <bitRange>[1:1]</bitRange>
15837                <access>read-write</access>
15838              </field>
15839              <field>
15840                <name>DST_BUS_ERROR</name>
15841                <description>Mask for INTR.DST_BUS_ERROR interrupt.</description>
15842                <bitRange>[2:2]</bitRange>
15843                <access>read-write</access>
15844              </field>
15845              <field>
15846                <name>SRC_MISAL</name>
15847                <description>Mask for INTR.SRC_MISAL interrupt.</description>
15848                <bitRange>[3:3]</bitRange>
15849                <access>read-write</access>
15850              </field>
15851              <field>
15852                <name>DST_MISAL</name>
15853                <description>Mask for INTR.DST_MISAL interrupt.</description>
15854                <bitRange>[4:4]</bitRange>
15855                <access>read-write</access>
15856              </field>
15857              <field>
15858                <name>CURR_PTR_NULL</name>
15859                <description>Mask for INTR.CURR_PTR_NULL interrupt.</description>
15860                <bitRange>[5:5]</bitRange>
15861                <access>read-write</access>
15862              </field>
15863              <field>
15864                <name>ACTIVE_CH_DISABLED</name>
15865                <description>Mask for INTR.ACTIVE_CH_DISABLED interrupt.</description>
15866                <bitRange>[6:6]</bitRange>
15867                <access>read-write</access>
15868              </field>
15869              <field>
15870                <name>DESCR_BUS_ERROR</name>
15871                <description>Mask for INTR.DESCR_BUS_ERROR interrupt.</description>
15872                <bitRange>[7:7]</bitRange>
15873                <access>read-write</access>
15874              </field>
15875            </fields>
15876          </register>
15877          <register>
15878            <name>INTR_MASKED</name>
15879            <description>Interrupt masked</description>
15880            <addressOffset>0x8C</addressOffset>
15881            <size>32</size>
15882            <access>read-only</access>
15883            <resetValue>0x0</resetValue>
15884            <resetMask>0xFF</resetMask>
15885            <fields>
15886              <field>
15887                <name>COMPLETION</name>
15888                <description>Logical and of corresponding INTR.COMPLETION and INTR_MASK.COMPLETION fields.</description>
15889                <bitRange>[0:0]</bitRange>
15890                <access>read-only</access>
15891              </field>
15892              <field>
15893                <name>SRC_BUS_ERROR</name>
15894                <description>Logical and of corresponding INTR.SRC_BUS_ERROR and INTR_MASK.SRC_BUS_ERROR fields.</description>
15895                <bitRange>[1:1]</bitRange>
15896                <access>read-only</access>
15897              </field>
15898              <field>
15899                <name>DST_BUS_ERROR</name>
15900                <description>Logical and of corresponding INTR.DST_BUS_ERROR and INTR_MASK.DST_BUS_ERROR fields.</description>
15901                <bitRange>[2:2]</bitRange>
15902                <access>read-only</access>
15903              </field>
15904              <field>
15905                <name>SRC_MISAL</name>
15906                <description>Logical and of corresponding INTR.SRC_MISAL and INTR_MASK.SRC_MISAL fields.</description>
15907                <bitRange>[3:3]</bitRange>
15908                <access>read-only</access>
15909              </field>
15910              <field>
15911                <name>DST_MISAL</name>
15912                <description>Logical and of corresponding INTR.DST_MISAL and INTR_MASK.DST_MISAL fields.</description>
15913                <bitRange>[4:4]</bitRange>
15914                <access>read-only</access>
15915              </field>
15916              <field>
15917                <name>CURR_PTR_NULL</name>
15918                <description>Logical and of corresponding INTR.CURR_PTR_NULL and INTR_MASK.CURR_PTR_NULL fields.</description>
15919                <bitRange>[5:5]</bitRange>
15920                <access>read-only</access>
15921              </field>
15922              <field>
15923                <name>ACTIVE_CH_DISABLED</name>
15924                <description>Logical and of corresponding INTR.ACTIVE_CH_DISABLED and INTR_MASK.ACTIVE_CH_DISABLED fields.</description>
15925                <bitRange>[6:6]</bitRange>
15926                <access>read-only</access>
15927              </field>
15928              <field>
15929                <name>DESCR_BUS_ERROR</name>
15930                <description>Logical and of corresponding INTR.DESCR_BUS_ERROR and INTR_MASK.DESCR_BUS_ERROR fields.</description>
15931                <bitRange>[7:7]</bitRange>
15932                <access>read-only</access>
15933              </field>
15934            </fields>
15935          </register>
15936        </cluster>
15937      </registers>
15938    </peripheral>
15939    <peripheral>
15940      <name>EFUSE</name>
15941      <description>EFUSE MXS40 registers</description>
15942      <baseAddress>0x402C0000</baseAddress>
15943      <addressBlock>
15944        <offset>0</offset>
15945        <size>512</size>
15946        <usage>registers</usage>
15947      </addressBlock>
15948      <registers>
15949        <register>
15950          <name>CTL</name>
15951          <description>Control</description>
15952          <addressOffset>0x0</addressOffset>
15953          <size>32</size>
15954          <access>read-write</access>
15955          <resetValue>0x0</resetValue>
15956          <resetMask>0x80000000</resetMask>
15957          <fields>
15958            <field>
15959              <name>ENABLED</name>
15960              <description>IP enable:
15961'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled.
15962'1': Enabled.</description>
15963              <bitRange>[31:31]</bitRange>
15964              <access>read-write</access>
15965            </field>
15966          </fields>
15967        </register>
15968        <register>
15969          <name>TEST</name>
15970          <description>Test</description>
15971          <addressOffset>0x4</addressOffset>
15972          <size>32</size>
15973          <access>read-write</access>
15974          <resetValue>0x1</resetValue>
15975          <resetMask>0x3</resetMask>
15976          <fields>
15977            <field>
15978              <name>MARG_READ</name>
15979              <description>Margin Read</description>
15980              <bitRange>[1:0]</bitRange>
15981              <access>read-write</access>
15982              <enumeratedValues>
15983                <enumeratedValue>
15984                  <name>LOWR</name>
15985                  <description>Low Resistance: -50 percent from nominal</description>
15986                  <value>0</value>
15987                </enumeratedValue>
15988                <enumeratedValue>
15989                  <name>DEFAULTR</name>
15990                  <description>Nominal resistance (Default read condition)</description>
15991                  <value>1</value>
15992                </enumeratedValue>
15993                <enumeratedValue>
15994                  <name>HIGHR</name>
15995                  <description>High Resistance: +50 percent from nominal</description>
15996                  <value>2</value>
15997                </enumeratedValue>
15998                <enumeratedValue>
15999                  <name>HIGHERR</name>
16000                  <description>Higher Resistance: +100 percent from nominal</description>
16001                  <value>3</value>
16002                </enumeratedValue>
16003              </enumeratedValues>
16004            </field>
16005          </fields>
16006        </register>
16007        <register>
16008          <name>CMD</name>
16009          <description>Command</description>
16010          <addressOffset>0x10</addressOffset>
16011          <size>32</size>
16012          <access>read-write</access>
16013          <resetValue>0x1</resetValue>
16014          <resetMask>0x800F1F71</resetMask>
16015          <fields>
16016            <field>
16017              <name>BIT_DATA</name>
16018              <description>Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR, BYTE_ADDR, and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro.</description>
16019              <bitRange>[0:0]</bitRange>
16020              <access>read-write</access>
16021            </field>
16022            <field>
16023              <name>BIT_ADDR</name>
16024              <description>Bit address. This field specifies a bit within a Byte.</description>
16025              <bitRange>[6:4]</bitRange>
16026              <access>read-write</access>
16027            </field>
16028            <field>
16029              <name>BYTE_ADDR</name>
16030              <description>Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B).</description>
16031              <bitRange>[12:8]</bitRange>
16032              <access>read-write</access>
16033            </field>
16034            <field>
16035              <name>MACRO_ADDR</name>
16036              <description>Macro address. This field specifies an eFUSE macro.</description>
16037              <bitRange>[19:16]</bitRange>
16038              <access>read-write</access>
16039            </field>
16040            <field>
16041              <name>START</name>
16042              <description>FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed.
16043
16044Note: it is good practice to verify the result of a program operation by reading back a programmed eFUSE memory location. Programming can only change an eFUSE memory bit from '0' to '1'; i.e. a programming operation is a 'one-off' operation for each eFUSE memory bit: once a bit is changed to '1', it can NEVER be changed back to '0' as a hardware fuse is blown.
16045
16046Programming a memory bit to '1' requires blowing a fuse and requires an eFUSE macro operation. Therefore, this programmiong operation takes time (as specified by the SEQ_PROGRAM_CTL reguisters). Programming amemory bit to '0' does not require an eFUSE macro operation (it is the default eFUSE macro state). Therefore, this programming operation is almost instantaneous.
16047
16048Note: during a program operation, a read operation can not be performed. An AHB-Lite read transfer to the eFUSE memory during a program operation results in an AHB-Lite bus error.</description>
16049              <bitRange>[31:31]</bitRange>
16050              <access>read-write</access>
16051            </field>
16052          </fields>
16053        </register>
16054        <register>
16055          <name>SEQ_DEFAULT</name>
16056          <description>Sequencer Default value</description>
16057          <addressOffset>0x20</addressOffset>
16058          <size>32</size>
16059          <access>read-write</access>
16060          <resetValue>0x1D0000</resetValue>
16061          <resetMask>0x7F0000</resetMask>
16062          <fields>
16063            <field>
16064              <name>STROBE_A</name>
16065              <description>Specifies value of eFUSE control signal strobe_f</description>
16066              <bitRange>[16:16]</bitRange>
16067              <access>read-write</access>
16068            </field>
16069            <field>
16070              <name>STROBE_B</name>
16071              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
16072              <bitRange>[17:17]</bitRange>
16073              <access>read-write</access>
16074            </field>
16075            <field>
16076              <name>STROBE_C</name>
16077              <description>Specifies value of eFUSE control signal strobe_c</description>
16078              <bitRange>[18:18]</bitRange>
16079              <access>read-write</access>
16080            </field>
16081            <field>
16082              <name>STROBE_D</name>
16083              <description>Specifies value of eFUSE control signal strobe_d</description>
16084              <bitRange>[19:19]</bitRange>
16085              <access>read-write</access>
16086            </field>
16087            <field>
16088              <name>STROBE_E</name>
16089              <description>Specifies value of eFUSE control signal strobe_e</description>
16090              <bitRange>[20:20]</bitRange>
16091              <access>read-write</access>
16092            </field>
16093            <field>
16094              <name>STROBE_F</name>
16095              <description>Specifies value of eFUSE control signal strobe_f</description>
16096              <bitRange>[21:21]</bitRange>
16097              <access>read-write</access>
16098            </field>
16099            <field>
16100              <name>STROBE_G</name>
16101              <description>Specifies value of eFUSE control signal strobe_g</description>
16102              <bitRange>[22:22]</bitRange>
16103              <access>read-write</access>
16104            </field>
16105          </fields>
16106        </register>
16107        <register>
16108          <name>SEQ_READ_CTL_0</name>
16109          <description>Sequencer read control 0</description>
16110          <addressOffset>0x40</addressOffset>
16111          <size>32</size>
16112          <access>read-write</access>
16113          <resetValue>0x80560001</resetValue>
16114          <resetMask>0x807F03FF</resetMask>
16115          <fields>
16116            <field>
16117              <name>CYCLES</name>
16118              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
16119              <bitRange>[9:0]</bitRange>
16120              <access>read-write</access>
16121            </field>
16122            <field>
16123              <name>STROBE_A</name>
16124              <description>Specifies value of eFUSE control signal strobe_f</description>
16125              <bitRange>[16:16]</bitRange>
16126              <access>read-write</access>
16127            </field>
16128            <field>
16129              <name>STROBE_B</name>
16130              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
16131              <bitRange>[17:17]</bitRange>
16132              <access>read-write</access>
16133            </field>
16134            <field>
16135              <name>STROBE_C</name>
16136              <description>Specifies value of eFUSE control signal strobe_c</description>
16137              <bitRange>[18:18]</bitRange>
16138              <access>read-write</access>
16139            </field>
16140            <field>
16141              <name>STROBE_D</name>
16142              <description>Specifies value of eFUSE control signal strobe_d</description>
16143              <bitRange>[19:19]</bitRange>
16144              <access>read-write</access>
16145            </field>
16146            <field>
16147              <name>STROBE_E</name>
16148              <description>Specifies value of eFUSE control signal strobe_e</description>
16149              <bitRange>[20:20]</bitRange>
16150              <access>read-write</access>
16151            </field>
16152            <field>
16153              <name>STROBE_F</name>
16154              <description>Specifies value of eFUSE control signal strobe_f</description>
16155              <bitRange>[21:21]</bitRange>
16156              <access>read-write</access>
16157            </field>
16158            <field>
16159              <name>STROBE_G</name>
16160              <description>Specifies value of eFUSE control signal strobe_g</description>
16161              <bitRange>[22:22]</bitRange>
16162              <access>read-write</access>
16163            </field>
16164            <field>
16165              <name>DONE</name>
16166              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
16167              <bitRange>[31:31]</bitRange>
16168              <access>read-write</access>
16169            </field>
16170          </fields>
16171        </register>
16172        <register>
16173          <name>SEQ_READ_CTL_1</name>
16174          <description>Sequencer read control 1</description>
16175          <addressOffset>0x44</addressOffset>
16176          <size>32</size>
16177          <access>read-write</access>
16178          <resetValue>0x540004</resetValue>
16179          <resetMask>0x807F03FF</resetMask>
16180          <fields>
16181            <field>
16182              <name>CYCLES</name>
16183              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
16184              <bitRange>[9:0]</bitRange>
16185              <access>read-write</access>
16186            </field>
16187            <field>
16188              <name>STROBE_A</name>
16189              <description>Specifies value of eFUSE control signal strobe_f</description>
16190              <bitRange>[16:16]</bitRange>
16191              <access>read-write</access>
16192            </field>
16193            <field>
16194              <name>STROBE_B</name>
16195              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
16196              <bitRange>[17:17]</bitRange>
16197              <access>read-write</access>
16198            </field>
16199            <field>
16200              <name>STROBE_C</name>
16201              <description>Specifies value of eFUSE control signal strobe_c</description>
16202              <bitRange>[18:18]</bitRange>
16203              <access>read-write</access>
16204            </field>
16205            <field>
16206              <name>STROBE_D</name>
16207              <description>Specifies value of eFUSE control signal strobe_d</description>
16208              <bitRange>[19:19]</bitRange>
16209              <access>read-write</access>
16210            </field>
16211            <field>
16212              <name>STROBE_E</name>
16213              <description>Specifies value of eFUSE control signal strobe_e</description>
16214              <bitRange>[20:20]</bitRange>
16215              <access>read-write</access>
16216            </field>
16217            <field>
16218              <name>STROBE_F</name>
16219              <description>Specifies value of eFUSE control signal strobe_f</description>
16220              <bitRange>[21:21]</bitRange>
16221              <access>read-write</access>
16222            </field>
16223            <field>
16224              <name>STROBE_G</name>
16225              <description>Specifies value of eFUSE control signal strobe_g</description>
16226              <bitRange>[22:22]</bitRange>
16227              <access>read-write</access>
16228            </field>
16229            <field>
16230              <name>DONE</name>
16231              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
16232              <bitRange>[31:31]</bitRange>
16233              <access>read-write</access>
16234            </field>
16235          </fields>
16236        </register>
16237        <register>
16238          <name>SEQ_READ_CTL_2</name>
16239          <description>Sequencer read control 2</description>
16240          <addressOffset>0x48</addressOffset>
16241          <size>32</size>
16242          <access>read-write</access>
16243          <resetValue>0x560001</resetValue>
16244          <resetMask>0x807F03FF</resetMask>
16245          <fields>
16246            <field>
16247              <name>CYCLES</name>
16248              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
16249              <bitRange>[9:0]</bitRange>
16250              <access>read-write</access>
16251            </field>
16252            <field>
16253              <name>STROBE_A</name>
16254              <description>Specifies value of eFUSE control signal strobe_f</description>
16255              <bitRange>[16:16]</bitRange>
16256              <access>read-write</access>
16257            </field>
16258            <field>
16259              <name>STROBE_B</name>
16260              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
16261              <bitRange>[17:17]</bitRange>
16262              <access>read-write</access>
16263            </field>
16264            <field>
16265              <name>STROBE_C</name>
16266              <description>Specifies value of eFUSE control signal strobe_c</description>
16267              <bitRange>[18:18]</bitRange>
16268              <access>read-write</access>
16269            </field>
16270            <field>
16271              <name>STROBE_D</name>
16272              <description>Specifies value of eFUSE control signal strobe_d</description>
16273              <bitRange>[19:19]</bitRange>
16274              <access>read-write</access>
16275            </field>
16276            <field>
16277              <name>STROBE_E</name>
16278              <description>Specifies value of eFUSE control signal strobe_e</description>
16279              <bitRange>[20:20]</bitRange>
16280              <access>read-write</access>
16281            </field>
16282            <field>
16283              <name>STROBE_F</name>
16284              <description>Specifies value of eFUSE control signal strobe_f</description>
16285              <bitRange>[21:21]</bitRange>
16286              <access>read-write</access>
16287            </field>
16288            <field>
16289              <name>STROBE_G</name>
16290              <description>Specifies value of eFUSE control signal strobe_g</description>
16291              <bitRange>[22:22]</bitRange>
16292              <access>read-write</access>
16293            </field>
16294            <field>
16295              <name>DONE</name>
16296              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
16297              <bitRange>[31:31]</bitRange>
16298              <access>read-write</access>
16299            </field>
16300          </fields>
16301        </register>
16302        <register>
16303          <name>SEQ_READ_CTL_3</name>
16304          <description>Sequencer read control 3</description>
16305          <addressOffset>0x4C</addressOffset>
16306          <size>32</size>
16307          <access>read-write</access>
16308          <resetValue>0x540003</resetValue>
16309          <resetMask>0x807F03FF</resetMask>
16310          <fields>
16311            <field>
16312              <name>CYCLES</name>
16313              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
16314              <bitRange>[9:0]</bitRange>
16315              <access>read-write</access>
16316            </field>
16317            <field>
16318              <name>STROBE_A</name>
16319              <description>Specifies value of eFUSE control signal strobe_f</description>
16320              <bitRange>[16:16]</bitRange>
16321              <access>read-write</access>
16322            </field>
16323            <field>
16324              <name>STROBE_B</name>
16325              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
16326              <bitRange>[17:17]</bitRange>
16327              <access>read-write</access>
16328            </field>
16329            <field>
16330              <name>STROBE_C</name>
16331              <description>Specifies value of eFUSE control signal strobe_c</description>
16332              <bitRange>[18:18]</bitRange>
16333              <access>read-write</access>
16334            </field>
16335            <field>
16336              <name>STROBE_D</name>
16337              <description>Specifies value of eFUSE control signal strobe_d</description>
16338              <bitRange>[19:19]</bitRange>
16339              <access>read-write</access>
16340            </field>
16341            <field>
16342              <name>STROBE_E</name>
16343              <description>Specifies value of eFUSE control signal strobe_e</description>
16344              <bitRange>[20:20]</bitRange>
16345              <access>read-write</access>
16346            </field>
16347            <field>
16348              <name>STROBE_F</name>
16349              <description>Specifies value of eFUSE control signal strobe_f</description>
16350              <bitRange>[21:21]</bitRange>
16351              <access>read-write</access>
16352            </field>
16353            <field>
16354              <name>STROBE_G</name>
16355              <description>Specifies value of eFUSE control signal strobe_g</description>
16356              <bitRange>[22:22]</bitRange>
16357              <access>read-write</access>
16358            </field>
16359            <field>
16360              <name>DONE</name>
16361              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
16362              <bitRange>[31:31]</bitRange>
16363              <access>read-write</access>
16364            </field>
16365          </fields>
16366        </register>
16367        <register>
16368          <name>SEQ_READ_CTL_4</name>
16369          <description>Sequencer read control 4</description>
16370          <addressOffset>0x50</addressOffset>
16371          <size>32</size>
16372          <access>read-write</access>
16373          <resetValue>0x80150001</resetValue>
16374          <resetMask>0x807F03FF</resetMask>
16375          <fields>
16376            <field>
16377              <name>CYCLES</name>
16378              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
16379              <bitRange>[9:0]</bitRange>
16380              <access>read-write</access>
16381            </field>
16382            <field>
16383              <name>STROBE_A</name>
16384              <description>Specifies value of eFUSE control signal strobe_f</description>
16385              <bitRange>[16:16]</bitRange>
16386              <access>read-write</access>
16387            </field>
16388            <field>
16389              <name>STROBE_B</name>
16390              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
16391              <bitRange>[17:17]</bitRange>
16392              <access>read-write</access>
16393            </field>
16394            <field>
16395              <name>STROBE_C</name>
16396              <description>Specifies value of eFUSE control signal strobe_c</description>
16397              <bitRange>[18:18]</bitRange>
16398              <access>read-write</access>
16399            </field>
16400            <field>
16401              <name>STROBE_D</name>
16402              <description>Specifies value of eFUSE control signal strobe_d</description>
16403              <bitRange>[19:19]</bitRange>
16404              <access>read-write</access>
16405            </field>
16406            <field>
16407              <name>STROBE_E</name>
16408              <description>Specifies value of eFUSE control signal strobe_e</description>
16409              <bitRange>[20:20]</bitRange>
16410              <access>read-write</access>
16411            </field>
16412            <field>
16413              <name>STROBE_F</name>
16414              <description>Specifies value of eFUSE control signal strobe_f</description>
16415              <bitRange>[21:21]</bitRange>
16416              <access>read-write</access>
16417            </field>
16418            <field>
16419              <name>STROBE_G</name>
16420              <description>Specifies value of eFUSE control signal strobe_g</description>
16421              <bitRange>[22:22]</bitRange>
16422              <access>read-write</access>
16423            </field>
16424            <field>
16425              <name>DONE</name>
16426              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
16427              <bitRange>[31:31]</bitRange>
16428              <access>read-write</access>
16429            </field>
16430          </fields>
16431        </register>
16432        <register>
16433          <name>SEQ_READ_CTL_5</name>
16434          <description>Sequencer read control 5</description>
16435          <addressOffset>0x54</addressOffset>
16436          <size>32</size>
16437          <access>read-write</access>
16438          <resetValue>0x310004</resetValue>
16439          <resetMask>0x807F03FF</resetMask>
16440          <fields>
16441            <field>
16442              <name>CYCLES</name>
16443              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
16444              <bitRange>[9:0]</bitRange>
16445              <access>read-write</access>
16446            </field>
16447            <field>
16448              <name>STROBE_A</name>
16449              <description>Specifies value of eFUSE control signal strobe_f</description>
16450              <bitRange>[16:16]</bitRange>
16451              <access>read-write</access>
16452            </field>
16453            <field>
16454              <name>STROBE_B</name>
16455              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
16456              <bitRange>[17:17]</bitRange>
16457              <access>read-write</access>
16458            </field>
16459            <field>
16460              <name>STROBE_C</name>
16461              <description>Specifies value of eFUSE control signal strobe_c</description>
16462              <bitRange>[18:18]</bitRange>
16463              <access>read-write</access>
16464            </field>
16465            <field>
16466              <name>STROBE_D</name>
16467              <description>Specifies value of eFUSE control signal strobe_d</description>
16468              <bitRange>[19:19]</bitRange>
16469              <access>read-write</access>
16470            </field>
16471            <field>
16472              <name>STROBE_E</name>
16473              <description>Specifies value of eFUSE control signal strobe_e</description>
16474              <bitRange>[20:20]</bitRange>
16475              <access>read-write</access>
16476            </field>
16477            <field>
16478              <name>STROBE_F</name>
16479              <description>Specifies value of eFUSE control signal strobe_f</description>
16480              <bitRange>[21:21]</bitRange>
16481              <access>read-write</access>
16482            </field>
16483            <field>
16484              <name>STROBE_G</name>
16485              <description>Specifies value of eFUSE control signal strobe_g</description>
16486              <bitRange>[22:22]</bitRange>
16487              <access>read-write</access>
16488            </field>
16489            <field>
16490              <name>DONE</name>
16491              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
16492              <bitRange>[31:31]</bitRange>
16493              <access>read-write</access>
16494            </field>
16495          </fields>
16496        </register>
16497        <register>
16498          <name>SEQ_PROGRAM_CTL_0</name>
16499          <description>Sequencer program control 0</description>
16500          <addressOffset>0x60</addressOffset>
16501          <size>32</size>
16502          <access>read-write</access>
16503          <resetValue>0x200001</resetValue>
16504          <resetMask>0x807F03FF</resetMask>
16505          <fields>
16506            <field>
16507              <name>CYCLES</name>
16508              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
16509              <bitRange>[9:0]</bitRange>
16510              <access>read-write</access>
16511            </field>
16512            <field>
16513              <name>STROBE_A</name>
16514              <description>Specifies value of eFUSE control signal strobe_a</description>
16515              <bitRange>[16:16]</bitRange>
16516              <access>read-write</access>
16517            </field>
16518            <field>
16519              <name>STROBE_B</name>
16520              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
16521              <bitRange>[17:17]</bitRange>
16522              <access>read-write</access>
16523            </field>
16524            <field>
16525              <name>STROBE_C</name>
16526              <description>Specifies value of eFUSE control signal strobe_c</description>
16527              <bitRange>[18:18]</bitRange>
16528              <access>read-write</access>
16529            </field>
16530            <field>
16531              <name>STROBE_D</name>
16532              <description>Specifies value of eFUSE control signal strobe_d</description>
16533              <bitRange>[19:19]</bitRange>
16534              <access>read-write</access>
16535            </field>
16536            <field>
16537              <name>STROBE_E</name>
16538              <description>Specifies value of eFUSE control signal strobe_e</description>
16539              <bitRange>[20:20]</bitRange>
16540              <access>read-write</access>
16541            </field>
16542            <field>
16543              <name>STROBE_F</name>
16544              <description>Specifies value of eFUSE control signal strobe_f</description>
16545              <bitRange>[21:21]</bitRange>
16546              <access>read-write</access>
16547            </field>
16548            <field>
16549              <name>STROBE_G</name>
16550              <description>Specifies value of eFUSE control signal strobe_g</description>
16551              <bitRange>[22:22]</bitRange>
16552              <access>read-write</access>
16553            </field>
16554            <field>
16555              <name>DONE</name>
16556              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
16557              <bitRange>[31:31]</bitRange>
16558              <access>read-write</access>
16559            </field>
16560          </fields>
16561        </register>
16562        <register>
16563          <name>SEQ_PROGRAM_CTL_1</name>
16564          <description>Sequencer program control 1</description>
16565          <addressOffset>0x64</addressOffset>
16566          <size>32</size>
16567          <access>read-write</access>
16568          <resetValue>0x220020</resetValue>
16569          <resetMask>0x807F03FF</resetMask>
16570          <fields>
16571            <field>
16572              <name>CYCLES</name>
16573              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
16574              <bitRange>[9:0]</bitRange>
16575              <access>read-write</access>
16576            </field>
16577            <field>
16578              <name>STROBE_A</name>
16579              <description>Specifies value of eFUSE control signal strobe_a</description>
16580              <bitRange>[16:16]</bitRange>
16581              <access>read-write</access>
16582            </field>
16583            <field>
16584              <name>STROBE_B</name>
16585              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
16586              <bitRange>[17:17]</bitRange>
16587              <access>read-write</access>
16588            </field>
16589            <field>
16590              <name>STROBE_C</name>
16591              <description>Specifies value of eFUSE control signal strobe_c</description>
16592              <bitRange>[18:18]</bitRange>
16593              <access>read-write</access>
16594            </field>
16595            <field>
16596              <name>STROBE_D</name>
16597              <description>Specifies value of eFUSE control signal strobe_d</description>
16598              <bitRange>[19:19]</bitRange>
16599              <access>read-write</access>
16600            </field>
16601            <field>
16602              <name>STROBE_E</name>
16603              <description>Specifies value of eFUSE control signal strobe_e</description>
16604              <bitRange>[20:20]</bitRange>
16605              <access>read-write</access>
16606            </field>
16607            <field>
16608              <name>STROBE_F</name>
16609              <description>Specifies value of eFUSE control signal strobe_f</description>
16610              <bitRange>[21:21]</bitRange>
16611              <access>read-write</access>
16612            </field>
16613            <field>
16614              <name>STROBE_G</name>
16615              <description>Specifies value of eFUSE control signal strobe_g</description>
16616              <bitRange>[22:22]</bitRange>
16617              <access>read-write</access>
16618            </field>
16619            <field>
16620              <name>DONE</name>
16621              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
16622              <bitRange>[31:31]</bitRange>
16623              <access>read-write</access>
16624            </field>
16625          </fields>
16626        </register>
16627        <register>
16628          <name>SEQ_PROGRAM_CTL_2</name>
16629          <description>Sequencer program control 2</description>
16630          <addressOffset>0x68</addressOffset>
16631          <size>32</size>
16632          <access>read-write</access>
16633          <resetValue>0x200001</resetValue>
16634          <resetMask>0x807F03FF</resetMask>
16635          <fields>
16636            <field>
16637              <name>CYCLES</name>
16638              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
16639              <bitRange>[9:0]</bitRange>
16640              <access>read-write</access>
16641            </field>
16642            <field>
16643              <name>STROBE_A</name>
16644              <description>Specifies value of eFUSE control signal strobe_a</description>
16645              <bitRange>[16:16]</bitRange>
16646              <access>read-write</access>
16647            </field>
16648            <field>
16649              <name>STROBE_B</name>
16650              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
16651              <bitRange>[17:17]</bitRange>
16652              <access>read-write</access>
16653            </field>
16654            <field>
16655              <name>STROBE_C</name>
16656              <description>Specifies value of eFUSE control signal strobe_c</description>
16657              <bitRange>[18:18]</bitRange>
16658              <access>read-write</access>
16659            </field>
16660            <field>
16661              <name>STROBE_D</name>
16662              <description>Specifies value of eFUSE control signal strobe_d</description>
16663              <bitRange>[19:19]</bitRange>
16664              <access>read-write</access>
16665            </field>
16666            <field>
16667              <name>STROBE_E</name>
16668              <description>Specifies value of eFUSE control signal strobe_e</description>
16669              <bitRange>[20:20]</bitRange>
16670              <access>read-write</access>
16671            </field>
16672            <field>
16673              <name>STROBE_F</name>
16674              <description>Specifies value of eFUSE control signal strobe_f</description>
16675              <bitRange>[21:21]</bitRange>
16676              <access>read-write</access>
16677            </field>
16678            <field>
16679              <name>STROBE_G</name>
16680              <description>Specifies value of eFUSE control signal strobe_g</description>
16681              <bitRange>[22:22]</bitRange>
16682              <access>read-write</access>
16683            </field>
16684            <field>
16685              <name>DONE</name>
16686              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
16687              <bitRange>[31:31]</bitRange>
16688              <access>read-write</access>
16689            </field>
16690          </fields>
16691        </register>
16692        <register>
16693          <name>SEQ_PROGRAM_CTL_3</name>
16694          <description>Sequencer program control 3</description>
16695          <addressOffset>0x6C</addressOffset>
16696          <size>32</size>
16697          <access>read-write</access>
16698          <resetValue>0x310005</resetValue>
16699          <resetMask>0x807F03FF</resetMask>
16700          <fields>
16701            <field>
16702              <name>CYCLES</name>
16703              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
16704              <bitRange>[9:0]</bitRange>
16705              <access>read-write</access>
16706            </field>
16707            <field>
16708              <name>STROBE_A</name>
16709              <description>Specifies value of eFUSE control signal strobe_a</description>
16710              <bitRange>[16:16]</bitRange>
16711              <access>read-write</access>
16712            </field>
16713            <field>
16714              <name>STROBE_B</name>
16715              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
16716              <bitRange>[17:17]</bitRange>
16717              <access>read-write</access>
16718            </field>
16719            <field>
16720              <name>STROBE_C</name>
16721              <description>Specifies value of eFUSE control signal strobe_c</description>
16722              <bitRange>[18:18]</bitRange>
16723              <access>read-write</access>
16724            </field>
16725            <field>
16726              <name>STROBE_D</name>
16727              <description>Specifies value of eFUSE control signal strobe_d</description>
16728              <bitRange>[19:19]</bitRange>
16729              <access>read-write</access>
16730            </field>
16731            <field>
16732              <name>STROBE_E</name>
16733              <description>Specifies value of eFUSE control signal strobe_e</description>
16734              <bitRange>[20:20]</bitRange>
16735              <access>read-write</access>
16736            </field>
16737            <field>
16738              <name>STROBE_F</name>
16739              <description>Specifies value of eFUSE control signal strobe_f</description>
16740              <bitRange>[21:21]</bitRange>
16741              <access>read-write</access>
16742            </field>
16743            <field>
16744              <name>STROBE_G</name>
16745              <description>Specifies value of eFUSE control signal strobe_g</description>
16746              <bitRange>[22:22]</bitRange>
16747              <access>read-write</access>
16748            </field>
16749            <field>
16750              <name>DONE</name>
16751              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
16752              <bitRange>[31:31]</bitRange>
16753              <access>read-write</access>
16754            </field>
16755          </fields>
16756        </register>
16757        <register>
16758          <name>SEQ_PROGRAM_CTL_4</name>
16759          <description>Sequencer program control 4</description>
16760          <addressOffset>0x70</addressOffset>
16761          <size>32</size>
16762          <access>read-write</access>
16763          <resetValue>0x80350006</resetValue>
16764          <resetMask>0x807F03FF</resetMask>
16765          <fields>
16766            <field>
16767              <name>CYCLES</name>
16768              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
16769              <bitRange>[9:0]</bitRange>
16770              <access>read-write</access>
16771            </field>
16772            <field>
16773              <name>STROBE_A</name>
16774              <description>Specifies value of eFUSE control signal strobe_a</description>
16775              <bitRange>[16:16]</bitRange>
16776              <access>read-write</access>
16777            </field>
16778            <field>
16779              <name>STROBE_B</name>
16780              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
16781              <bitRange>[17:17]</bitRange>
16782              <access>read-write</access>
16783            </field>
16784            <field>
16785              <name>STROBE_C</name>
16786              <description>Specifies value of eFUSE control signal strobe_c</description>
16787              <bitRange>[18:18]</bitRange>
16788              <access>read-write</access>
16789            </field>
16790            <field>
16791              <name>STROBE_D</name>
16792              <description>Specifies value of eFUSE control signal strobe_d</description>
16793              <bitRange>[19:19]</bitRange>
16794              <access>read-write</access>
16795            </field>
16796            <field>
16797              <name>STROBE_E</name>
16798              <description>Specifies value of eFUSE control signal strobe_e</description>
16799              <bitRange>[20:20]</bitRange>
16800              <access>read-write</access>
16801            </field>
16802            <field>
16803              <name>STROBE_F</name>
16804              <description>Specifies value of eFUSE control signal strobe_f</description>
16805              <bitRange>[21:21]</bitRange>
16806              <access>read-write</access>
16807            </field>
16808            <field>
16809              <name>STROBE_G</name>
16810              <description>Specifies value of eFUSE control signal strobe_g</description>
16811              <bitRange>[22:22]</bitRange>
16812              <access>read-write</access>
16813            </field>
16814            <field>
16815              <name>DONE</name>
16816              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
16817              <bitRange>[31:31]</bitRange>
16818              <access>read-write</access>
16819            </field>
16820          </fields>
16821        </register>
16822        <register>
16823          <name>SEQ_PROGRAM_CTL_5</name>
16824          <description>Sequencer program control 5</description>
16825          <addressOffset>0x74</addressOffset>
16826          <size>32</size>
16827          <access>read-write</access>
16828          <resetValue>0x803D0019</resetValue>
16829          <resetMask>0x807F03FF</resetMask>
16830          <fields>
16831            <field>
16832              <name>CYCLES</name>
16833              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
16834              <bitRange>[9:0]</bitRange>
16835              <access>read-write</access>
16836            </field>
16837            <field>
16838              <name>STROBE_A</name>
16839              <description>Specifies value of eFUSE control signal strobe_a</description>
16840              <bitRange>[16:16]</bitRange>
16841              <access>read-write</access>
16842            </field>
16843            <field>
16844              <name>STROBE_B</name>
16845              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
16846              <bitRange>[17:17]</bitRange>
16847              <access>read-write</access>
16848            </field>
16849            <field>
16850              <name>STROBE_C</name>
16851              <description>Specifies value of eFUSE control signal strobe_c</description>
16852              <bitRange>[18:18]</bitRange>
16853              <access>read-write</access>
16854            </field>
16855            <field>
16856              <name>STROBE_D</name>
16857              <description>Specifies value of eFUSE control signal strobe_d</description>
16858              <bitRange>[19:19]</bitRange>
16859              <access>read-write</access>
16860            </field>
16861            <field>
16862              <name>STROBE_E</name>
16863              <description>Specifies value of eFUSE control signal strobe_e</description>
16864              <bitRange>[20:20]</bitRange>
16865              <access>read-write</access>
16866            </field>
16867            <field>
16868              <name>STROBE_F</name>
16869              <description>Specifies value of eFUSE control signal strobe_f</description>
16870              <bitRange>[21:21]</bitRange>
16871              <access>read-write</access>
16872            </field>
16873            <field>
16874              <name>STROBE_G</name>
16875              <description>Specifies value of eFUSE control signal strobe_g</description>
16876              <bitRange>[22:22]</bitRange>
16877              <access>read-write</access>
16878            </field>
16879            <field>
16880              <name>DONE</name>
16881              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
16882              <bitRange>[31:31]</bitRange>
16883              <access>read-write</access>
16884            </field>
16885          </fields>
16886        </register>
16887      </registers>
16888    </peripheral>
16889    <peripheral>
16890      <name>HSIOM</name>
16891      <description>High Speed IO Matrix (HSIOM)</description>
16892      <baseAddress>0x40300000</baseAddress>
16893      <addressBlock>
16894        <offset>0</offset>
16895        <size>16384</size>
16896        <usage>registers</usage>
16897      </addressBlock>
16898      <registers>
16899        <cluster>
16900          <dim>24</dim>
16901          <dimIncrement>16</dimIncrement>
16902          <name>PRT[%s]</name>
16903          <description>HSIOM port registers</description>
16904          <addressOffset>0x00000000</addressOffset>
16905          <register>
16906            <name>PORT_SEL0</name>
16907            <description>Port selection 0</description>
16908            <addressOffset>0x0</addressOffset>
16909            <size>32</size>
16910            <access>read-write</access>
16911            <resetValue>0x0</resetValue>
16912            <resetMask>0x1F1F1F1F</resetMask>
16913            <fields>
16914              <field>
16915                <name>IO0_SEL</name>
16916                <description>Selects connection for IO pin 0 route.</description>
16917                <bitRange>[4:0]</bitRange>
16918                <access>read-write</access>
16919                <enumeratedValues>
16920                  <enumeratedValue>
16921                    <name>GPIO</name>
16922                    <description>GPIO controls 'out'</description>
16923                    <value>0</value>
16924                  </enumeratedValue>
16925                  <enumeratedValue>
16926                    <name>GPIO_DSI</name>
16927                    <description>GPIO controls 'out', DSI controls 'output enable'</description>
16928                    <value>1</value>
16929                  </enumeratedValue>
16930                  <enumeratedValue>
16931                    <name>DSI_DSI</name>
16932                    <description>DSI controls 'out' and 'output enable'</description>
16933                    <value>2</value>
16934                  </enumeratedValue>
16935                  <enumeratedValue>
16936                    <name>DSI_GPIO</name>
16937                    <description>DSI controls 'out', GPIO controls 'output enable'</description>
16938                    <value>3</value>
16939                  </enumeratedValue>
16940                  <enumeratedValue>
16941                    <name>AMUXA</name>
16942                    <description>Analog mux bus A</description>
16943                    <value>4</value>
16944                  </enumeratedValue>
16945                  <enumeratedValue>
16946                    <name>AMUXB</name>
16947                    <description>Analog mux bus B</description>
16948                    <value>5</value>
16949                  </enumeratedValue>
16950                  <enumeratedValue>
16951                    <name>AMUXA_DSI</name>
16952                    <description>Analog mux bus A, DSI control</description>
16953                    <value>6</value>
16954                  </enumeratedValue>
16955                  <enumeratedValue>
16956                    <name>AMUXB_DSI</name>
16957                    <description>Analog mux bus B, DSI control</description>
16958                    <value>7</value>
16959                  </enumeratedValue>
16960                  <enumeratedValue>
16961                    <name>ACT_0</name>
16962                    <description>Active functionality 0</description>
16963                    <value>8</value>
16964                  </enumeratedValue>
16965                  <enumeratedValue>
16966                    <name>ACT_1</name>
16967                    <description>Active functionality 1</description>
16968                    <value>9</value>
16969                  </enumeratedValue>
16970                  <enumeratedValue>
16971                    <name>ACT_2</name>
16972                    <description>Active functionality 2</description>
16973                    <value>10</value>
16974                  </enumeratedValue>
16975                  <enumeratedValue>
16976                    <name>ACT_3</name>
16977                    <description>Active functionality 3</description>
16978                    <value>11</value>
16979                  </enumeratedValue>
16980                  <enumeratedValue>
16981                    <name>DS_0</name>
16982                    <description>DeepSleep functionality 0</description>
16983                    <value>12</value>
16984                  </enumeratedValue>
16985                  <enumeratedValue>
16986                    <name>DS_1</name>
16987                    <description>DeepSleep functionality 1</description>
16988                    <value>13</value>
16989                  </enumeratedValue>
16990                  <enumeratedValue>
16991                    <name>DS_2</name>
16992                    <description>DeepSleep functionality 2</description>
16993                    <value>14</value>
16994                  </enumeratedValue>
16995                  <enumeratedValue>
16996                    <name>DS_3</name>
16997                    <description>DeepSleep functionality 3</description>
16998                    <value>15</value>
16999                  </enumeratedValue>
17000                  <enumeratedValue>
17001                    <name>ACT_4</name>
17002                    <description>Active functionality 4</description>
17003                    <value>16</value>
17004                  </enumeratedValue>
17005                  <enumeratedValue>
17006                    <name>ACT_5</name>
17007                    <description>Active functionality 5</description>
17008                    <value>17</value>
17009                  </enumeratedValue>
17010                  <enumeratedValue>
17011                    <name>ACT_6</name>
17012                    <description>Active functionality 6</description>
17013                    <value>18</value>
17014                  </enumeratedValue>
17015                  <enumeratedValue>
17016                    <name>ACT_7</name>
17017                    <description>Active functionality 7</description>
17018                    <value>19</value>
17019                  </enumeratedValue>
17020                  <enumeratedValue>
17021                    <name>ACT_8</name>
17022                    <description>Active functionality 8</description>
17023                    <value>20</value>
17024                  </enumeratedValue>
17025                  <enumeratedValue>
17026                    <name>ACT_9</name>
17027                    <description>Active functionality 9</description>
17028                    <value>21</value>
17029                  </enumeratedValue>
17030                  <enumeratedValue>
17031                    <name>ACT_10</name>
17032                    <description>Active functionality 10</description>
17033                    <value>22</value>
17034                  </enumeratedValue>
17035                  <enumeratedValue>
17036                    <name>ACT_11</name>
17037                    <description>Active functionality 11</description>
17038                    <value>23</value>
17039                  </enumeratedValue>
17040                  <enumeratedValue>
17041                    <name>ACT_12</name>
17042                    <description>Active functionality 12</description>
17043                    <value>24</value>
17044                  </enumeratedValue>
17045                  <enumeratedValue>
17046                    <name>ACT_13</name>
17047                    <description>Active functionality 13</description>
17048                    <value>25</value>
17049                  </enumeratedValue>
17050                  <enumeratedValue>
17051                    <name>ACT_14</name>
17052                    <description>Active functionality 14</description>
17053                    <value>26</value>
17054                  </enumeratedValue>
17055                  <enumeratedValue>
17056                    <name>ACT_15</name>
17057                    <description>Active functionality 15</description>
17058                    <value>27</value>
17059                  </enumeratedValue>
17060                  <enumeratedValue>
17061                    <name>DS_4</name>
17062                    <description>DeepSleep functionality 4</description>
17063                    <value>28</value>
17064                  </enumeratedValue>
17065                  <enumeratedValue>
17066                    <name>DS_5</name>
17067                    <description>DeepSleep functionality 5</description>
17068                    <value>29</value>
17069                  </enumeratedValue>
17070                  <enumeratedValue>
17071                    <name>DS_6</name>
17072                    <description>DeepSleep functionality 6</description>
17073                    <value>30</value>
17074                  </enumeratedValue>
17075                  <enumeratedValue>
17076                    <name>DS_7</name>
17077                    <description>DeepSleep functionality 7</description>
17078                    <value>31</value>
17079                  </enumeratedValue>
17080                </enumeratedValues>
17081              </field>
17082              <field>
17083                <name>IO1_SEL</name>
17084                <description>Selects connection for IO pin 1 route.</description>
17085                <bitRange>[12:8]</bitRange>
17086                <access>read-write</access>
17087              </field>
17088              <field>
17089                <name>IO2_SEL</name>
17090                <description>Selects connection for IO pin 2 route.</description>
17091                <bitRange>[20:16]</bitRange>
17092                <access>read-write</access>
17093              </field>
17094              <field>
17095                <name>IO3_SEL</name>
17096                <description>Selects connection for IO pin 3 route.</description>
17097                <bitRange>[28:24]</bitRange>
17098                <access>read-write</access>
17099              </field>
17100            </fields>
17101          </register>
17102          <register>
17103            <name>PORT_SEL1</name>
17104            <description>Port selection 1</description>
17105            <addressOffset>0x4</addressOffset>
17106            <size>32</size>
17107            <access>read-write</access>
17108            <resetValue>0x0</resetValue>
17109            <resetMask>0x1F1F1F1F</resetMask>
17110            <fields>
17111              <field>
17112                <name>IO4_SEL</name>
17113                <description>Selects connection for IO pin 4 route.
17114See PORT_SEL0 for connection details.</description>
17115                <bitRange>[4:0]</bitRange>
17116                <access>read-write</access>
17117              </field>
17118              <field>
17119                <name>IO5_SEL</name>
17120                <description>Selects connection for IO pin 5 route.</description>
17121                <bitRange>[12:8]</bitRange>
17122                <access>read-write</access>
17123              </field>
17124              <field>
17125                <name>IO6_SEL</name>
17126                <description>Selects connection for IO pin 6 route.</description>
17127                <bitRange>[20:16]</bitRange>
17128                <access>read-write</access>
17129              </field>
17130              <field>
17131                <name>IO7_SEL</name>
17132                <description>Selects connection for IO pin 7 route.</description>
17133                <bitRange>[28:24]</bitRange>
17134                <access>read-write</access>
17135              </field>
17136            </fields>
17137          </register>
17138        </cluster>
17139        <register>
17140          <dim>64</dim>
17141          <dimIncrement>4</dimIncrement>
17142          <name>AMUX_SPLIT_CTL[%s]</name>
17143          <description>AMUX splitter cell control</description>
17144          <addressOffset>0x2000</addressOffset>
17145          <size>32</size>
17146          <access>read-write</access>
17147          <resetValue>0x0</resetValue>
17148          <resetMask>0x77</resetMask>
17149          <fields>
17150            <field>
17151              <name>SWITCH_AA_SL</name>
17152              <description>T-switch control for Left AMUXBUSA switch:
17153'0': switch open.
17154'1': switch closed.</description>
17155              <bitRange>[0:0]</bitRange>
17156              <access>read-write</access>
17157            </field>
17158            <field>
17159              <name>SWITCH_AA_SR</name>
17160              <description>T-switch control for Right AMUXBUSA switch:
17161'0': switch open.
17162'1': switch closed.</description>
17163              <bitRange>[1:1]</bitRange>
17164              <access>read-write</access>
17165            </field>
17166            <field>
17167              <name>SWITCH_AA_S0</name>
17168              <description>T-switch control for AMUXBUSA vssa/ground switch:
17169'0': switch open.
17170'1': switch closed.</description>
17171              <bitRange>[2:2]</bitRange>
17172              <access>read-write</access>
17173            </field>
17174            <field>
17175              <name>SWITCH_BB_SL</name>
17176              <description>T-switch control for Left AMUXBUSB switch.</description>
17177              <bitRange>[4:4]</bitRange>
17178              <access>read-write</access>
17179            </field>
17180            <field>
17181              <name>SWITCH_BB_SR</name>
17182              <description>T-switch control for Right AMUXBUSB switch.</description>
17183              <bitRange>[5:5]</bitRange>
17184              <access>read-write</access>
17185            </field>
17186            <field>
17187              <name>SWITCH_BB_S0</name>
17188              <description>T-switch control for AMUXBUSB vssa/ground switch.</description>
17189              <bitRange>[6:6]</bitRange>
17190              <access>read-write</access>
17191            </field>
17192          </fields>
17193        </register>
17194        <register>
17195          <name>MONITOR_CTL_0</name>
17196          <description>Power/Ground Monitor cell control 0</description>
17197          <addressOffset>0x2200</addressOffset>
17198          <size>32</size>
17199          <access>read-write</access>
17200          <resetValue>0x0</resetValue>
17201          <resetMask>0xFFFFFFFF</resetMask>
17202          <fields>
17203            <field>
17204              <name>MONITOR_EN</name>
17205              <description>control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:
17206'0': switch open.
17207'1': switch closed.</description>
17208              <bitRange>[31:0]</bitRange>
17209              <access>read-write</access>
17210            </field>
17211          </fields>
17212        </register>
17213        <register>
17214          <name>MONITOR_CTL_1</name>
17215          <description>Power/Ground Monitor cell control 1</description>
17216          <addressOffset>0x2204</addressOffset>
17217          <size>32</size>
17218          <access>read-write</access>
17219          <resetValue>0x0</resetValue>
17220          <resetMask>0xFFFFFFFF</resetMask>
17221          <fields>
17222            <field>
17223              <name>MONITOR_EN</name>
17224              <description>control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:
17225'0': switch open.
17226'1': switch closed.</description>
17227              <bitRange>[31:0]</bitRange>
17228              <access>read-write</access>
17229            </field>
17230          </fields>
17231        </register>
17232        <register>
17233          <name>MONITOR_CTL_2</name>
17234          <description>Power/Ground Monitor cell control 2</description>
17235          <addressOffset>0x2208</addressOffset>
17236          <size>32</size>
17237          <access>read-write</access>
17238          <resetValue>0x0</resetValue>
17239          <resetMask>0xFFFFFFFF</resetMask>
17240          <fields>
17241            <field>
17242              <name>MONITOR_EN</name>
17243              <description>control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:
17244'0': switch open.
17245'1': switch closed.</description>
17246              <bitRange>[31:0]</bitRange>
17247              <access>read-write</access>
17248            </field>
17249          </fields>
17250        </register>
17251        <register>
17252          <name>MONITOR_CTL_3</name>
17253          <description>Power/Ground Monitor cell control 3</description>
17254          <addressOffset>0x220C</addressOffset>
17255          <size>32</size>
17256          <access>read-write</access>
17257          <resetValue>0x0</resetValue>
17258          <resetMask>0xFFFFFFFF</resetMask>
17259          <fields>
17260            <field>
17261              <name>MONITOR_EN</name>
17262              <description>control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:
17263'0': switch open.
17264'1': switch closed.</description>
17265              <bitRange>[31:0]</bitRange>
17266              <access>read-write</access>
17267            </field>
17268          </fields>
17269        </register>
17270        <register>
17271          <name>ALT_JTAG_EN</name>
17272          <description>Alternate JTAG IF selection register</description>
17273          <addressOffset>0x2240</addressOffset>
17274          <size>32</size>
17275          <access>read-write</access>
17276          <resetValue>0x0</resetValue>
17277          <resetMask>0x80000000</resetMask>
17278          <fields>
17279            <field>
17280              <name>ENABLE</name>
17281              <description>Provides the selection for alternate JTAG IF connectivity.
172820: Primary JTAG interface is selected
172831: Secondary (alternate) JTAG interface is selected.
17284
17285This connectivity works ONLY in ACTIVE mode.</description>
17286              <bitRange>[31:31]</bitRange>
17287              <access>read-write</access>
17288            </field>
17289          </fields>
17290        </register>
17291      </registers>
17292    </peripheral>
17293    <peripheral>
17294      <name>GPIO</name>
17295      <description>GPIO port control/configuration</description>
17296      <baseAddress>0x40310000</baseAddress>
17297      <addressBlock>
17298        <offset>0</offset>
17299        <size>65536</size>
17300        <usage>registers</usage>
17301      </addressBlock>
17302      <registers>
17303        <cluster>
17304          <dim>24</dim>
17305          <dimIncrement>128</dimIncrement>
17306          <name>PRT[%s]</name>
17307          <description>GPIO port registers</description>
17308          <addressOffset>0x00000000</addressOffset>
17309          <register>
17310            <name>OUT</name>
17311            <description>Port output data register</description>
17312            <addressOffset>0x0</addressOffset>
17313            <size>32</size>
17314            <access>read-write</access>
17315            <resetValue>0x0</resetValue>
17316            <resetMask>0xFF</resetMask>
17317            <fields>
17318              <field>
17319                <name>OUT0</name>
17320                <description>IO output data for pin 0
17321'0': Output state set to '0'
17322'1': Output state set to '1'</description>
17323                <bitRange>[0:0]</bitRange>
17324                <access>read-write</access>
17325              </field>
17326              <field>
17327                <name>OUT1</name>
17328                <description>IO output data for pin 1</description>
17329                <bitRange>[1:1]</bitRange>
17330                <access>read-write</access>
17331              </field>
17332              <field>
17333                <name>OUT2</name>
17334                <description>IO output data for pin 2</description>
17335                <bitRange>[2:2]</bitRange>
17336                <access>read-write</access>
17337              </field>
17338              <field>
17339                <name>OUT3</name>
17340                <description>IO output data for pin 3</description>
17341                <bitRange>[3:3]</bitRange>
17342                <access>read-write</access>
17343              </field>
17344              <field>
17345                <name>OUT4</name>
17346                <description>IO output data for pin 4</description>
17347                <bitRange>[4:4]</bitRange>
17348                <access>read-write</access>
17349              </field>
17350              <field>
17351                <name>OUT5</name>
17352                <description>IO output data for pin 5</description>
17353                <bitRange>[5:5]</bitRange>
17354                <access>read-write</access>
17355              </field>
17356              <field>
17357                <name>OUT6</name>
17358                <description>IO output data for pin 6</description>
17359                <bitRange>[6:6]</bitRange>
17360                <access>read-write</access>
17361              </field>
17362              <field>
17363                <name>OUT7</name>
17364                <description>IO output data for pin 7</description>
17365                <bitRange>[7:7]</bitRange>
17366                <access>read-write</access>
17367              </field>
17368            </fields>
17369          </register>
17370          <register>
17371            <name>OUT_CLR</name>
17372            <description>Port output data clear register</description>
17373            <addressOffset>0x4</addressOffset>
17374            <size>32</size>
17375            <access>read-write</access>
17376            <resetValue>0x0</resetValue>
17377            <resetMask>0xFF</resetMask>
17378            <fields>
17379              <field>
17380                <name>OUT0</name>
17381                <description>IO clear output for pin 0:
17382'0': Output state not affected.
17383'1': Output state set to '0'.</description>
17384                <bitRange>[0:0]</bitRange>
17385                <access>read-write</access>
17386              </field>
17387              <field>
17388                <name>OUT1</name>
17389                <description>IO clear output for pin 1</description>
17390                <bitRange>[1:1]</bitRange>
17391                <access>read-write</access>
17392              </field>
17393              <field>
17394                <name>OUT2</name>
17395                <description>IO clear output for pin 2</description>
17396                <bitRange>[2:2]</bitRange>
17397                <access>read-write</access>
17398              </field>
17399              <field>
17400                <name>OUT3</name>
17401                <description>IO clear output for pin 3</description>
17402                <bitRange>[3:3]</bitRange>
17403                <access>read-write</access>
17404              </field>
17405              <field>
17406                <name>OUT4</name>
17407                <description>IO clear output for pin 4</description>
17408                <bitRange>[4:4]</bitRange>
17409                <access>read-write</access>
17410              </field>
17411              <field>
17412                <name>OUT5</name>
17413                <description>IO clear output for pin 5</description>
17414                <bitRange>[5:5]</bitRange>
17415                <access>read-write</access>
17416              </field>
17417              <field>
17418                <name>OUT6</name>
17419                <description>IO clear output for pin 6</description>
17420                <bitRange>[6:6]</bitRange>
17421                <access>read-write</access>
17422              </field>
17423              <field>
17424                <name>OUT7</name>
17425                <description>IO clear output for pin 7</description>
17426                <bitRange>[7:7]</bitRange>
17427                <access>read-write</access>
17428              </field>
17429            </fields>
17430          </register>
17431          <register>
17432            <name>OUT_SET</name>
17433            <description>Port output data set register</description>
17434            <addressOffset>0x8</addressOffset>
17435            <size>32</size>
17436            <access>read-write</access>
17437            <resetValue>0x0</resetValue>
17438            <resetMask>0xFF</resetMask>
17439            <fields>
17440              <field>
17441                <name>OUT0</name>
17442                <description>IO set output for pin 0:
17443'0': Output state not affected.
17444'1': Output state set to '1'.</description>
17445                <bitRange>[0:0]</bitRange>
17446                <access>read-write</access>
17447              </field>
17448              <field>
17449                <name>OUT1</name>
17450                <description>IO set output for pin 1</description>
17451                <bitRange>[1:1]</bitRange>
17452                <access>read-write</access>
17453              </field>
17454              <field>
17455                <name>OUT2</name>
17456                <description>IO set output for pin 2</description>
17457                <bitRange>[2:2]</bitRange>
17458                <access>read-write</access>
17459              </field>
17460              <field>
17461                <name>OUT3</name>
17462                <description>IO set output for pin 3</description>
17463                <bitRange>[3:3]</bitRange>
17464                <access>read-write</access>
17465              </field>
17466              <field>
17467                <name>OUT4</name>
17468                <description>IO set output for pin 4</description>
17469                <bitRange>[4:4]</bitRange>
17470                <access>read-write</access>
17471              </field>
17472              <field>
17473                <name>OUT5</name>
17474                <description>IO set output for pin 5</description>
17475                <bitRange>[5:5]</bitRange>
17476                <access>read-write</access>
17477              </field>
17478              <field>
17479                <name>OUT6</name>
17480                <description>IO set output for pin 6</description>
17481                <bitRange>[6:6]</bitRange>
17482                <access>read-write</access>
17483              </field>
17484              <field>
17485                <name>OUT7</name>
17486                <description>IO set output for pin 7</description>
17487                <bitRange>[7:7]</bitRange>
17488                <access>read-write</access>
17489              </field>
17490            </fields>
17491          </register>
17492          <register>
17493            <name>OUT_INV</name>
17494            <description>Port output data invert register</description>
17495            <addressOffset>0xC</addressOffset>
17496            <size>32</size>
17497            <access>read-write</access>
17498            <resetValue>0x0</resetValue>
17499            <resetMask>0xFF</resetMask>
17500            <fields>
17501              <field>
17502                <name>OUT0</name>
17503                <description>IO invert output for pin 0:
17504'0': Output state not affected.
17505'1': Output state inverted ('0' =&gt; '1', '1' =&gt; '0').</description>
17506                <bitRange>[0:0]</bitRange>
17507                <access>read-write</access>
17508              </field>
17509              <field>
17510                <name>OUT1</name>
17511                <description>IO invert output for pin 1</description>
17512                <bitRange>[1:1]</bitRange>
17513                <access>read-write</access>
17514              </field>
17515              <field>
17516                <name>OUT2</name>
17517                <description>IO invert output for pin 2</description>
17518                <bitRange>[2:2]</bitRange>
17519                <access>read-write</access>
17520              </field>
17521              <field>
17522                <name>OUT3</name>
17523                <description>IO invert output for pin 3</description>
17524                <bitRange>[3:3]</bitRange>
17525                <access>read-write</access>
17526              </field>
17527              <field>
17528                <name>OUT4</name>
17529                <description>IO invert output for pin 4</description>
17530                <bitRange>[4:4]</bitRange>
17531                <access>read-write</access>
17532              </field>
17533              <field>
17534                <name>OUT5</name>
17535                <description>IO invert output for pin 5</description>
17536                <bitRange>[5:5]</bitRange>
17537                <access>read-write</access>
17538              </field>
17539              <field>
17540                <name>OUT6</name>
17541                <description>IO invert output for pin 6</description>
17542                <bitRange>[6:6]</bitRange>
17543                <access>read-write</access>
17544              </field>
17545              <field>
17546                <name>OUT7</name>
17547                <description>IO invert output for pin 7</description>
17548                <bitRange>[7:7]</bitRange>
17549                <access>read-write</access>
17550              </field>
17551            </fields>
17552          </register>
17553          <register>
17554            <name>IN</name>
17555            <description>Port input state register</description>
17556            <addressOffset>0x10</addressOffset>
17557            <size>32</size>
17558            <access>read-only</access>
17559            <resetValue>0x0</resetValue>
17560            <resetMask>0x1FF</resetMask>
17561            <fields>
17562              <field>
17563                <name>IN0</name>
17564                <description>IO pin state for pin 0
17565'0': Low logic level present on pin.
17566'1': High logic level present on pin.
17567On reset assertion , IN register will get reset. The Pad value takes 2 clock cycles to be reflected into IN Register.  It's value then depends on the external pin value.</description>
17568                <bitRange>[0:0]</bitRange>
17569                <access>read-only</access>
17570              </field>
17571              <field>
17572                <name>IN1</name>
17573                <description>IO pin state for pin 1</description>
17574                <bitRange>[1:1]</bitRange>
17575                <access>read-only</access>
17576              </field>
17577              <field>
17578                <name>IN2</name>
17579                <description>IO pin state for pin 2</description>
17580                <bitRange>[2:2]</bitRange>
17581                <access>read-only</access>
17582              </field>
17583              <field>
17584                <name>IN3</name>
17585                <description>IO pin state for pin 3</description>
17586                <bitRange>[3:3]</bitRange>
17587                <access>read-only</access>
17588              </field>
17589              <field>
17590                <name>IN4</name>
17591                <description>IO pin state for pin 4</description>
17592                <bitRange>[4:4]</bitRange>
17593                <access>read-only</access>
17594              </field>
17595              <field>
17596                <name>IN5</name>
17597                <description>IO pin state for pin 5</description>
17598                <bitRange>[5:5]</bitRange>
17599                <access>read-only</access>
17600              </field>
17601              <field>
17602                <name>IN6</name>
17603                <description>IO pin state for pin 6</description>
17604                <bitRange>[6:6]</bitRange>
17605                <access>read-only</access>
17606              </field>
17607              <field>
17608                <name>IN7</name>
17609                <description>IO pin state for pin 7</description>
17610                <bitRange>[7:7]</bitRange>
17611                <access>read-only</access>
17612              </field>
17613              <field>
17614                <name>FLT_IN</name>
17615                <description>Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.</description>
17616                <bitRange>[8:8]</bitRange>
17617                <access>read-only</access>
17618              </field>
17619            </fields>
17620          </register>
17621          <register>
17622            <name>INTR</name>
17623            <description>Port interrupt status register</description>
17624            <addressOffset>0x14</addressOffset>
17625            <size>32</size>
17626            <access>read-write</access>
17627            <resetValue>0x0</resetValue>
17628            <resetMask>0x1FF01FF</resetMask>
17629            <fields>
17630              <field>
17631                <name>EDGE0</name>
17632                <description>Edge detect for IO pin 0
17633'0': No edge was detected on pin.
17634'1': An edge was detected on pin.</description>
17635                <bitRange>[0:0]</bitRange>
17636                <access>read-write</access>
17637              </field>
17638              <field>
17639                <name>EDGE1</name>
17640                <description>Edge detect for IO pin 1</description>
17641                <bitRange>[1:1]</bitRange>
17642                <access>read-write</access>
17643              </field>
17644              <field>
17645                <name>EDGE2</name>
17646                <description>Edge detect for IO pin 2</description>
17647                <bitRange>[2:2]</bitRange>
17648                <access>read-write</access>
17649              </field>
17650              <field>
17651                <name>EDGE3</name>
17652                <description>Edge detect for IO pin 3</description>
17653                <bitRange>[3:3]</bitRange>
17654                <access>read-write</access>
17655              </field>
17656              <field>
17657                <name>EDGE4</name>
17658                <description>Edge detect for IO pin 4</description>
17659                <bitRange>[4:4]</bitRange>
17660                <access>read-write</access>
17661              </field>
17662              <field>
17663                <name>EDGE5</name>
17664                <description>Edge detect for IO pin 5</description>
17665                <bitRange>[5:5]</bitRange>
17666                <access>read-write</access>
17667              </field>
17668              <field>
17669                <name>EDGE6</name>
17670                <description>Edge detect for IO pin 6</description>
17671                <bitRange>[6:6]</bitRange>
17672                <access>read-write</access>
17673              </field>
17674              <field>
17675                <name>EDGE7</name>
17676                <description>Edge detect for IO pin 7</description>
17677                <bitRange>[7:7]</bitRange>
17678                <access>read-write</access>
17679              </field>
17680              <field>
17681                <name>FLT_EDGE</name>
17682                <description>Edge detected on filtered pin selected by INTR_CFG.FLT_SEL</description>
17683                <bitRange>[8:8]</bitRange>
17684                <access>read-write</access>
17685              </field>
17686              <field>
17687                <name>IN_IN0</name>
17688                <description>IO pin state for pin 0</description>
17689                <bitRange>[16:16]</bitRange>
17690                <access>read-only</access>
17691              </field>
17692              <field>
17693                <name>IN_IN1</name>
17694                <description>IO pin state for pin 1</description>
17695                <bitRange>[17:17]</bitRange>
17696                <access>read-only</access>
17697              </field>
17698              <field>
17699                <name>IN_IN2</name>
17700                <description>IO pin state for pin 2</description>
17701                <bitRange>[18:18]</bitRange>
17702                <access>read-only</access>
17703              </field>
17704              <field>
17705                <name>IN_IN3</name>
17706                <description>IO pin state for pin 3</description>
17707                <bitRange>[19:19]</bitRange>
17708                <access>read-only</access>
17709              </field>
17710              <field>
17711                <name>IN_IN4</name>
17712                <description>IO pin state for pin 4</description>
17713                <bitRange>[20:20]</bitRange>
17714                <access>read-only</access>
17715              </field>
17716              <field>
17717                <name>IN_IN5</name>
17718                <description>IO pin state for pin 5</description>
17719                <bitRange>[21:21]</bitRange>
17720                <access>read-only</access>
17721              </field>
17722              <field>
17723                <name>IN_IN6</name>
17724                <description>IO pin state for pin 6</description>
17725                <bitRange>[22:22]</bitRange>
17726                <access>read-only</access>
17727              </field>
17728              <field>
17729                <name>IN_IN7</name>
17730                <description>IO pin state for pin 7</description>
17731                <bitRange>[23:23]</bitRange>
17732                <access>read-only</access>
17733              </field>
17734              <field>
17735                <name>FLT_IN_IN</name>
17736                <description>Filtered pin state for pin selected by INTR_CFG.FLT_SEL</description>
17737                <bitRange>[24:24]</bitRange>
17738                <access>read-only</access>
17739              </field>
17740            </fields>
17741          </register>
17742          <register>
17743            <name>INTR_MASK</name>
17744            <description>Port interrupt mask register</description>
17745            <addressOffset>0x18</addressOffset>
17746            <size>32</size>
17747            <access>read-write</access>
17748            <resetValue>0x0</resetValue>
17749            <resetMask>0x1FF</resetMask>
17750            <fields>
17751              <field>
17752                <name>EDGE0</name>
17753                <description>Masks edge interrupt on IO pin 0
17754'0': Pin interrupt forwarding disabled
17755'1': Pin interrupt forwarding enabled</description>
17756                <bitRange>[0:0]</bitRange>
17757                <access>read-write</access>
17758              </field>
17759              <field>
17760                <name>EDGE1</name>
17761                <description>Masks edge interrupt on IO pin 1</description>
17762                <bitRange>[1:1]</bitRange>
17763                <access>read-write</access>
17764              </field>
17765              <field>
17766                <name>EDGE2</name>
17767                <description>Masks edge interrupt on IO pin 2</description>
17768                <bitRange>[2:2]</bitRange>
17769                <access>read-write</access>
17770              </field>
17771              <field>
17772                <name>EDGE3</name>
17773                <description>Masks edge interrupt on IO pin 3</description>
17774                <bitRange>[3:3]</bitRange>
17775                <access>read-write</access>
17776              </field>
17777              <field>
17778                <name>EDGE4</name>
17779                <description>Masks edge interrupt on IO pin 4</description>
17780                <bitRange>[4:4]</bitRange>
17781                <access>read-write</access>
17782              </field>
17783              <field>
17784                <name>EDGE5</name>
17785                <description>Masks edge interrupt on IO pin 5</description>
17786                <bitRange>[5:5]</bitRange>
17787                <access>read-write</access>
17788              </field>
17789              <field>
17790                <name>EDGE6</name>
17791                <description>Masks edge interrupt on IO pin 6</description>
17792                <bitRange>[6:6]</bitRange>
17793                <access>read-write</access>
17794              </field>
17795              <field>
17796                <name>EDGE7</name>
17797                <description>Masks edge interrupt on IO pin 7</description>
17798                <bitRange>[7:7]</bitRange>
17799                <access>read-write</access>
17800              </field>
17801              <field>
17802                <name>FLT_EDGE</name>
17803                <description>Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL</description>
17804                <bitRange>[8:8]</bitRange>
17805                <access>read-write</access>
17806              </field>
17807            </fields>
17808          </register>
17809          <register>
17810            <name>INTR_MASKED</name>
17811            <description>Port interrupt masked status register</description>
17812            <addressOffset>0x1C</addressOffset>
17813            <size>32</size>
17814            <access>read-only</access>
17815            <resetValue>0x0</resetValue>
17816            <resetMask>0x1FF</resetMask>
17817            <fields>
17818              <field>
17819                <name>EDGE0</name>
17820                <description>Edge detected AND masked on IO pin 0
17821'0': Interrupt was not forwarded to CPU
17822'1': Interrupt occurred and was forwarded to CPU</description>
17823                <bitRange>[0:0]</bitRange>
17824                <access>read-only</access>
17825              </field>
17826              <field>
17827                <name>EDGE1</name>
17828                <description>Edge detected and masked on IO pin 1</description>
17829                <bitRange>[1:1]</bitRange>
17830                <access>read-only</access>
17831              </field>
17832              <field>
17833                <name>EDGE2</name>
17834                <description>Edge detected and masked on IO pin 2</description>
17835                <bitRange>[2:2]</bitRange>
17836                <access>read-only</access>
17837              </field>
17838              <field>
17839                <name>EDGE3</name>
17840                <description>Edge detected and masked on IO pin 3</description>
17841                <bitRange>[3:3]</bitRange>
17842                <access>read-only</access>
17843              </field>
17844              <field>
17845                <name>EDGE4</name>
17846                <description>Edge detected and masked on IO pin 4</description>
17847                <bitRange>[4:4]</bitRange>
17848                <access>read-only</access>
17849              </field>
17850              <field>
17851                <name>EDGE5</name>
17852                <description>Edge detected and masked on IO pin 5</description>
17853                <bitRange>[5:5]</bitRange>
17854                <access>read-only</access>
17855              </field>
17856              <field>
17857                <name>EDGE6</name>
17858                <description>Edge detected and masked on IO pin 6</description>
17859                <bitRange>[6:6]</bitRange>
17860                <access>read-only</access>
17861              </field>
17862              <field>
17863                <name>EDGE7</name>
17864                <description>Edge detected and masked on IO pin 7</description>
17865                <bitRange>[7:7]</bitRange>
17866                <access>read-only</access>
17867              </field>
17868              <field>
17869                <name>FLT_EDGE</name>
17870                <description>Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL</description>
17871                <bitRange>[8:8]</bitRange>
17872                <access>read-only</access>
17873              </field>
17874            </fields>
17875          </register>
17876          <register>
17877            <name>INTR_SET</name>
17878            <description>Port interrupt set register</description>
17879            <addressOffset>0x20</addressOffset>
17880            <size>32</size>
17881            <access>read-write</access>
17882            <resetValue>0x0</resetValue>
17883            <resetMask>0x1FF</resetMask>
17884            <fields>
17885              <field>
17886                <name>EDGE0</name>
17887                <description>Sets edge detect interrupt for IO pin 0
17888'0': Interrupt state not affected
17889'1': Interrupt set</description>
17890                <bitRange>[0:0]</bitRange>
17891                <access>read-write</access>
17892              </field>
17893              <field>
17894                <name>EDGE1</name>
17895                <description>Sets edge detect interrupt for IO pin 1</description>
17896                <bitRange>[1:1]</bitRange>
17897                <access>read-write</access>
17898              </field>
17899              <field>
17900                <name>EDGE2</name>
17901                <description>Sets edge detect interrupt for IO pin 2</description>
17902                <bitRange>[2:2]</bitRange>
17903                <access>read-write</access>
17904              </field>
17905              <field>
17906                <name>EDGE3</name>
17907                <description>Sets edge detect interrupt for IO pin 3</description>
17908                <bitRange>[3:3]</bitRange>
17909                <access>read-write</access>
17910              </field>
17911              <field>
17912                <name>EDGE4</name>
17913                <description>Sets edge detect interrupt for IO pin 4</description>
17914                <bitRange>[4:4]</bitRange>
17915                <access>read-write</access>
17916              </field>
17917              <field>
17918                <name>EDGE5</name>
17919                <description>Sets edge detect interrupt for IO pin 5</description>
17920                <bitRange>[5:5]</bitRange>
17921                <access>read-write</access>
17922              </field>
17923              <field>
17924                <name>EDGE6</name>
17925                <description>Sets edge detect interrupt for IO pin 6</description>
17926                <bitRange>[6:6]</bitRange>
17927                <access>read-write</access>
17928              </field>
17929              <field>
17930                <name>EDGE7</name>
17931                <description>Sets edge detect interrupt for IO pin 7</description>
17932                <bitRange>[7:7]</bitRange>
17933                <access>read-write</access>
17934              </field>
17935              <field>
17936                <name>FLT_EDGE</name>
17937                <description>Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL</description>
17938                <bitRange>[8:8]</bitRange>
17939                <access>read-write</access>
17940              </field>
17941            </fields>
17942          </register>
17943          <register>
17944            <name>INTR_CFG</name>
17945            <description>Port interrupt configuration register</description>
17946            <addressOffset>0x40</addressOffset>
17947            <size>32</size>
17948            <access>read-write</access>
17949            <resetValue>0x0</resetValue>
17950            <resetMask>0x1FFFFF</resetMask>
17951            <fields>
17952              <field>
17953                <name>EDGE0_SEL</name>
17954                <description>Sets which edge will trigger an IRQ for IO pin 0</description>
17955                <bitRange>[1:0]</bitRange>
17956                <access>read-write</access>
17957                <enumeratedValues>
17958                  <enumeratedValue>
17959                    <name>DISABLE</name>
17960                    <description>Disabled</description>
17961                    <value>0</value>
17962                  </enumeratedValue>
17963                  <enumeratedValue>
17964                    <name>RISING</name>
17965                    <description>Rising edge</description>
17966                    <value>1</value>
17967                  </enumeratedValue>
17968                  <enumeratedValue>
17969                    <name>FALLING</name>
17970                    <description>Falling edge</description>
17971                    <value>2</value>
17972                  </enumeratedValue>
17973                  <enumeratedValue>
17974                    <name>BOTH</name>
17975                    <description>Both rising and falling edges</description>
17976                    <value>3</value>
17977                  </enumeratedValue>
17978                </enumeratedValues>
17979              </field>
17980              <field>
17981                <name>EDGE1_SEL</name>
17982                <description>Sets which edge will trigger an IRQ for IO pin 1</description>
17983                <bitRange>[3:2]</bitRange>
17984                <access>read-write</access>
17985              </field>
17986              <field>
17987                <name>EDGE2_SEL</name>
17988                <description>Sets which edge will trigger an IRQ for IO pin 2</description>
17989                <bitRange>[5:4]</bitRange>
17990                <access>read-write</access>
17991              </field>
17992              <field>
17993                <name>EDGE3_SEL</name>
17994                <description>Sets which edge will trigger an IRQ for IO pin 3</description>
17995                <bitRange>[7:6]</bitRange>
17996                <access>read-write</access>
17997              </field>
17998              <field>
17999                <name>EDGE4_SEL</name>
18000                <description>Sets which edge will trigger an IRQ for IO pin 4</description>
18001                <bitRange>[9:8]</bitRange>
18002                <access>read-write</access>
18003              </field>
18004              <field>
18005                <name>EDGE5_SEL</name>
18006                <description>Sets which edge will trigger an IRQ for IO pin 5</description>
18007                <bitRange>[11:10]</bitRange>
18008                <access>read-write</access>
18009              </field>
18010              <field>
18011                <name>EDGE6_SEL</name>
18012                <description>Sets which edge will trigger an IRQ for IO pin 6</description>
18013                <bitRange>[13:12]</bitRange>
18014                <access>read-write</access>
18015              </field>
18016              <field>
18017                <name>EDGE7_SEL</name>
18018                <description>Sets which edge will trigger an IRQ for IO pin 7</description>
18019                <bitRange>[15:14]</bitRange>
18020                <access>read-write</access>
18021              </field>
18022              <field>
18023                <name>FLT_EDGE_SEL</name>
18024                <description>Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL</description>
18025                <bitRange>[17:16]</bitRange>
18026                <access>read-write</access>
18027                <enumeratedValues>
18028                  <enumeratedValue>
18029                    <name>DISABLE</name>
18030                    <description>Disabled</description>
18031                    <value>0</value>
18032                  </enumeratedValue>
18033                  <enumeratedValue>
18034                    <name>RISING</name>
18035                    <description>Rising edge</description>
18036                    <value>1</value>
18037                  </enumeratedValue>
18038                  <enumeratedValue>
18039                    <name>FALLING</name>
18040                    <description>Falling edge</description>
18041                    <value>2</value>
18042                  </enumeratedValue>
18043                  <enumeratedValue>
18044                    <name>BOTH</name>
18045                    <description>Both rising and falling edges</description>
18046                    <value>3</value>
18047                  </enumeratedValue>
18048                </enumeratedValues>
18049              </field>
18050              <field>
18051                <name>FLT_SEL</name>
18052                <description>Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.</description>
18053                <bitRange>[20:18]</bitRange>
18054                <access>read-write</access>
18055              </field>
18056            </fields>
18057          </register>
18058          <register>
18059            <name>CFG</name>
18060            <description>Port configuration register</description>
18061            <addressOffset>0x44</addressOffset>
18062            <size>32</size>
18063            <access>read-write</access>
18064            <resetValue>0x0</resetValue>
18065            <resetMask>0xFFFFFFFF</resetMask>
18066            <fields>
18067              <field>
18068                <name>DRIVE_MODE0</name>
18069                <description>The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode.
18070Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured  before turning the IO on here to avoid producing glitches on the bus.
18071Note: that peripherals other than GPIO &amp; UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0').
18072Note: D_OUT, D_OUT_EN are pins of GPIO cell.</description>
18073                <bitRange>[2:0]</bitRange>
18074                <access>read-write</access>
18075                <enumeratedValues>
18076                  <enumeratedValue>
18077                    <name>HIGHZ</name>
18078                    <description>Output buffer is off creating a high impedance input
18079D_OUT = '0': High Impedance
18080D_OUT = '1': High Impedance</description>
18081                    <value>0</value>
18082                  </enumeratedValue>
18083                  <enumeratedValue>
18084                    <name>RSVD</name>
18085                    <description>N/A</description>
18086                    <value>1</value>
18087                  </enumeratedValue>
18088                  <enumeratedValue>
18089                    <name>PULLUP</name>
18090                    <description>Resistive pull up
18091
18092For GPIO &amp; UDB/DSI peripherals:
18093When D_OUT_EN = 1:
18094   D_OUT = '0': Strong pull down
18095   D_OUT = '1': Weak/resistive pull up
18096When D_OUT_EN = 0:
18097   D_OUT = '0': High impedance
18098   D_OUT = '1': High impedance
18099
18100For peripherals other than GPIO &amp; UDB/DSI:
18101When D_OUT_EN = 1:
18102   D_OUT = '0': Strong pull down
18103   D_OUT = '1': Strong pull up
18104When D_OUT_EN = 0:
18105   D_OUT = '0': Weak/resistive pull up
18106   D_OUT = '1': Weak/resistive pull up</description>
18107                    <value>2</value>
18108                  </enumeratedValue>
18109                  <enumeratedValue>
18110                    <name>PULLDOWN</name>
18111                    <description>Resistive pull down
18112
18113For GPIO &amp; UDB/DSI peripherals:
18114When D_OUT_EN = 1:
18115   D_OUT = '0': Weak/resistive pull down
18116   D_OUT = '1': Strong pull up
18117When D_OUT_EN = 0:
18118   D_OUT = '0': High impedance
18119   D_OUT = '1': High impedance
18120
18121For peripherals other than GPIO &amp; UDB/DSI:
18122When D_OUT_EN = 1:
18123   D_OUT = '0': Strong pull down
18124   D_OUT = '1': Strong pull up
18125When D_OUT_EN = 0:
18126   D_OUT = '0': Weak/resistive pull down
18127   D_OUT = '1': Weak/resistive pull down</description>
18128                    <value>3</value>
18129                  </enumeratedValue>
18130                  <enumeratedValue>
18131                    <name>OD_DRIVESLOW</name>
18132                    <description>Open drain, drives low
18133
18134For GPIO &amp; UDB/DSI peripherals:
18135When D_OUT_EN = 1:
18136   D_OUT = '0': Strong pull down
18137   D_OUT = '1': High Impedance
18138When D_OUT_EN = 0:
18139   D_OUT = '0': High impedance
18140   D_OUT = '1': High impedance
18141
18142For peripherals other than GPIO &amp; UDB/DSI:
18143When D_OUT_EN = 1:
18144   D_OUT = '0': Strong pull down
18145   D_OUT = '1': Strong pull up
18146When D_OUT_EN = 0:
18147   D_OUT = '0': High Impedance
18148   D_OUT = '1': High Impedance</description>
18149                    <value>4</value>
18150                  </enumeratedValue>
18151                  <enumeratedValue>
18152                    <name>OD_DRIVESHIGH</name>
18153                    <description>Open drain, drives high
18154
18155For GPIO &amp; UDB/DSI peripherals:
18156When D_OUT_EN = 1:
18157   D_OUT = '0': High Impedance
18158   D_OUT = '1': Strong pull up
18159When D_OUT_EN = 0:
18160   D_OUT = '0': High impedance
18161   D_OUT = '1': High impedance
18162
18163For peripherals other than GPIO &amp; UDB/DSI:
18164When D_OUT_EN = 1:
18165   D_OUT = '0': Strong pull down
18166   D_OUT = '1': Strong pull up
18167When D_OUT_EN = 0:
18168   D_OUT = '0': High Impedance
18169   D_OUT = '1': High Impedance</description>
18170                    <value>5</value>
18171                  </enumeratedValue>
18172                  <enumeratedValue>
18173                    <name>STRONG</name>
18174                    <description>Strong D_OUTput buffer
18175
18176For GPIO &amp; UDB/DSI peripherals:
18177When D_OUT_EN = 1:
18178   D_OUT = '0': Strong pull down
18179   D_OUT = '1': Strong pull up
18180When D_OUT_EN = 0:
18181   D_OUT = '0': High impedance
18182   D_OUT = '1': High impedance
18183
18184For peripherals other than GPIO &amp; UDB/DSI:
18185When D_OUT_EN = 1:
18186   D_OUT = '0': Strong pull down
18187   D_OUT = '1': Strong pull up
18188When D_OUT_EN = 0:
18189   D_OUT = '0': High Impedance
18190   D_OUT = '1': High Impedance</description>
18191                    <value>6</value>
18192                  </enumeratedValue>
18193                  <enumeratedValue>
18194                    <name>PULLUP_DOWN</name>
18195                    <description>Pull up or pull down
18196
18197For GPIO &amp; UDB/DSI peripherals:
18198When D_OUT_EN = '0':
18199    GPIO_DSI_OUT = '0': Weak/resistive pull down
18200    GPIO_DSI_OUT = '1': Weak/resistive pull up
18201where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT &amp; DSI_DATA_OUT.
18202
18203For peripherals other than GPIO &amp; UDB/DSI:
18204When D_OUT_EN = 1:
18205   D_OUT = '0': Strong pull down
18206   D_OUT = '1': Strong pull up
18207When D_OUT_EN = 0:
18208    D_OUT = '0': Weak/resistive pull down
18209    D_OUT = '1': Weak/resistive pull up</description>
18210                    <value>7</value>
18211                  </enumeratedValue>
18212                </enumeratedValues>
18213              </field>
18214              <field>
18215                <name>IN_EN0</name>
18216                <description>Enables the input buffer for IO pin 0.  This bit should be cleared when analog signals are present on the pin to avoid crowbar currents.  The output buffer can be used to drive analog signals high or low without issue.
18217'0': Input buffer disabled
18218'1': Input buffer enabled</description>
18219                <bitRange>[3:3]</bitRange>
18220                <access>read-write</access>
18221              </field>
18222              <field>
18223                <name>DRIVE_MODE1</name>
18224                <description>The GPIO drive mode for IO pin 1</description>
18225                <bitRange>[6:4]</bitRange>
18226                <access>read-write</access>
18227              </field>
18228              <field>
18229                <name>IN_EN1</name>
18230                <description>Enables the input buffer for IO pin 1</description>
18231                <bitRange>[7:7]</bitRange>
18232                <access>read-write</access>
18233              </field>
18234              <field>
18235                <name>DRIVE_MODE2</name>
18236                <description>The GPIO drive mode for IO pin 2</description>
18237                <bitRange>[10:8]</bitRange>
18238                <access>read-write</access>
18239              </field>
18240              <field>
18241                <name>IN_EN2</name>
18242                <description>Enables the input buffer for IO pin 2</description>
18243                <bitRange>[11:11]</bitRange>
18244                <access>read-write</access>
18245              </field>
18246              <field>
18247                <name>DRIVE_MODE3</name>
18248                <description>The GPIO drive mode for IO pin 3</description>
18249                <bitRange>[14:12]</bitRange>
18250                <access>read-write</access>
18251              </field>
18252              <field>
18253                <name>IN_EN3</name>
18254                <description>Enables the input buffer for IO pin 3</description>
18255                <bitRange>[15:15]</bitRange>
18256                <access>read-write</access>
18257              </field>
18258              <field>
18259                <name>DRIVE_MODE4</name>
18260                <description>The GPIO drive mode for IO pin4</description>
18261                <bitRange>[18:16]</bitRange>
18262                <access>read-write</access>
18263              </field>
18264              <field>
18265                <name>IN_EN4</name>
18266                <description>Enables the input buffer for IO pin 4</description>
18267                <bitRange>[19:19]</bitRange>
18268                <access>read-write</access>
18269              </field>
18270              <field>
18271                <name>DRIVE_MODE5</name>
18272                <description>The GPIO drive mode for IO pin 5</description>
18273                <bitRange>[22:20]</bitRange>
18274                <access>read-write</access>
18275              </field>
18276              <field>
18277                <name>IN_EN5</name>
18278                <description>Enables the input buffer for IO pin 5</description>
18279                <bitRange>[23:23]</bitRange>
18280                <access>read-write</access>
18281              </field>
18282              <field>
18283                <name>DRIVE_MODE6</name>
18284                <description>The GPIO drive mode for IO pin 6</description>
18285                <bitRange>[26:24]</bitRange>
18286                <access>read-write</access>
18287              </field>
18288              <field>
18289                <name>IN_EN6</name>
18290                <description>Enables the input buffer for IO pin 6</description>
18291                <bitRange>[27:27]</bitRange>
18292                <access>read-write</access>
18293              </field>
18294              <field>
18295                <name>DRIVE_MODE7</name>
18296                <description>The GPIO drive mode for IO pin 7</description>
18297                <bitRange>[30:28]</bitRange>
18298                <access>read-write</access>
18299              </field>
18300              <field>
18301                <name>IN_EN7</name>
18302                <description>Enables the input buffer for IO pin 7</description>
18303                <bitRange>[31:31]</bitRange>
18304                <access>read-write</access>
18305              </field>
18306            </fields>
18307          </register>
18308          <register>
18309            <name>CFG_IN</name>
18310            <description>Port input buffer configuration register</description>
18311            <addressOffset>0x48</addressOffset>
18312            <size>32</size>
18313            <access>read-write</access>
18314            <resetValue>0x0</resetValue>
18315            <resetMask>0xFF</resetMask>
18316            <fields>
18317              <field>
18318                <name>VTRIP_SEL0_0</name>
18319                <description>Configures the pin 0 input buffer mode (trip points and hysteresis)</description>
18320                <bitRange>[0:0]</bitRange>
18321                <access>read-write</access>
18322                <enumeratedValues>
18323                  <enumeratedValue>
18324                    <name>CMOS</name>
18325                    <description>PSoC 6:: Input buffer compatible with CMOS and I2C interfaces
18326Traveo II: Full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1</description>
18327                    <value>0</value>
18328                  </enumeratedValue>
18329                  <enumeratedValue>
18330                    <name>TTL</name>
18331                    <description>PSoC 6:: Input buffer compatible with TTL and MediaLB interfaces
18332Traveo II: full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1</description>
18333                    <value>1</value>
18334                  </enumeratedValue>
18335                </enumeratedValues>
18336              </field>
18337              <field>
18338                <name>VTRIP_SEL1_0</name>
18339                <description>Configures the pin 1 input buffer mode (trip points and hysteresis)</description>
18340                <bitRange>[1:1]</bitRange>
18341                <access>read-write</access>
18342              </field>
18343              <field>
18344                <name>VTRIP_SEL2_0</name>
18345                <description>Configures the pin 2 input buffer mode (trip points and hysteresis)</description>
18346                <bitRange>[2:2]</bitRange>
18347                <access>read-write</access>
18348              </field>
18349              <field>
18350                <name>VTRIP_SEL3_0</name>
18351                <description>Configures the pin 3 input buffer mode (trip points and hysteresis)</description>
18352                <bitRange>[3:3]</bitRange>
18353                <access>read-write</access>
18354              </field>
18355              <field>
18356                <name>VTRIP_SEL4_0</name>
18357                <description>Configures the pin 4 input buffer mode (trip points and hysteresis)</description>
18358                <bitRange>[4:4]</bitRange>
18359                <access>read-write</access>
18360              </field>
18361              <field>
18362                <name>VTRIP_SEL5_0</name>
18363                <description>Configures the pin 5 input buffer mode (trip points and hysteresis)</description>
18364                <bitRange>[5:5]</bitRange>
18365                <access>read-write</access>
18366              </field>
18367              <field>
18368                <name>VTRIP_SEL6_0</name>
18369                <description>Configures the pin 6 input buffer mode (trip points and hysteresis)</description>
18370                <bitRange>[6:6]</bitRange>
18371                <access>read-write</access>
18372              </field>
18373              <field>
18374                <name>VTRIP_SEL7_0</name>
18375                <description>Configures the pin 7 input buffer mode (trip points and hysteresis)</description>
18376                <bitRange>[7:7]</bitRange>
18377                <access>read-write</access>
18378              </field>
18379            </fields>
18380          </register>
18381          <register>
18382            <name>CFG_OUT</name>
18383            <description>Port output buffer configuration register</description>
18384            <addressOffset>0x4C</addressOffset>
18385            <size>32</size>
18386            <access>read-write</access>
18387            <resetValue>0x0</resetValue>
18388            <resetMask>0xFFFF00FF</resetMask>
18389            <fields>
18390              <field>
18391                <name>SLOW0</name>
18392                <description>Enables slow slew rate for IO pin 0
18393'0': Fast slew rate
18394'1': Slow slew rate</description>
18395                <bitRange>[0:0]</bitRange>
18396                <access>read-write</access>
18397              </field>
18398              <field>
18399                <name>SLOW1</name>
18400                <description>Enables slow slew rate for IO pin 1</description>
18401                <bitRange>[1:1]</bitRange>
18402                <access>read-write</access>
18403              </field>
18404              <field>
18405                <name>SLOW2</name>
18406                <description>Enables slow slew rate for IO pin 2</description>
18407                <bitRange>[2:2]</bitRange>
18408                <access>read-write</access>
18409              </field>
18410              <field>
18411                <name>SLOW3</name>
18412                <description>Enables slow slew rate for IO pin 3</description>
18413                <bitRange>[3:3]</bitRange>
18414                <access>read-write</access>
18415              </field>
18416              <field>
18417                <name>SLOW4</name>
18418                <description>Enables slow slew rate for IO pin 4</description>
18419                <bitRange>[4:4]</bitRange>
18420                <access>read-write</access>
18421              </field>
18422              <field>
18423                <name>SLOW5</name>
18424                <description>Enables slow slew rate for IO pin 5</description>
18425                <bitRange>[5:5]</bitRange>
18426                <access>read-write</access>
18427              </field>
18428              <field>
18429                <name>SLOW6</name>
18430                <description>Enables slow slew rate for IO pin 6</description>
18431                <bitRange>[6:6]</bitRange>
18432                <access>read-write</access>
18433              </field>
18434              <field>
18435                <name>SLOW7</name>
18436                <description>Enables slow slew rate for IO pin 7</description>
18437                <bitRange>[7:7]</bitRange>
18438                <access>read-write</access>
18439              </field>
18440              <field>
18441                <name>DRIVE_SEL0</name>
18442                <description>Sets the GPIO drive strength for IO pin 0</description>
18443                <bitRange>[17:16]</bitRange>
18444                <access>read-write</access>
18445                <enumeratedValues>
18446                  <enumeratedValue>
18447                    <name>DRIVE_SEL_ZERO</name>
18448                    <description>Please refer to architecture TRM section I/O System</description>
18449                    <value>0</value>
18450                  </enumeratedValue>
18451                  <enumeratedValue>
18452                    <name>DRIVE_SEL_ONE</name>
18453                    <description>Please refer to architecture TRM section I/O System</description>
18454                    <value>1</value>
18455                  </enumeratedValue>
18456                  <enumeratedValue>
18457                    <name>DRIVE_SEL_TWO</name>
18458                    <description>Please refer to architecture TRM section I/O System</description>
18459                    <value>2</value>
18460                  </enumeratedValue>
18461                  <enumeratedValue>
18462                    <name>DRIVE_SEL_THREE</name>
18463                    <description>Please refer to architecture TRM section I/O System</description>
18464                    <value>3</value>
18465                  </enumeratedValue>
18466                </enumeratedValues>
18467              </field>
18468              <field>
18469                <name>DRIVE_SEL1</name>
18470                <description>Sets the GPIO drive strength for IO pin 1</description>
18471                <bitRange>[19:18]</bitRange>
18472                <access>read-write</access>
18473              </field>
18474              <field>
18475                <name>DRIVE_SEL2</name>
18476                <description>Sets the GPIO drive strength for IO pin 2</description>
18477                <bitRange>[21:20]</bitRange>
18478                <access>read-write</access>
18479              </field>
18480              <field>
18481                <name>DRIVE_SEL3</name>
18482                <description>Sets the GPIO drive strength for IO pin 3</description>
18483                <bitRange>[23:22]</bitRange>
18484                <access>read-write</access>
18485              </field>
18486              <field>
18487                <name>DRIVE_SEL4</name>
18488                <description>Sets the GPIO drive strength for IO pin 4</description>
18489                <bitRange>[25:24]</bitRange>
18490                <access>read-write</access>
18491              </field>
18492              <field>
18493                <name>DRIVE_SEL5</name>
18494                <description>Sets the GPIO drive strength for IO pin 5</description>
18495                <bitRange>[27:26]</bitRange>
18496                <access>read-write</access>
18497              </field>
18498              <field>
18499                <name>DRIVE_SEL6</name>
18500                <description>Sets the GPIO drive strength for IO pin 6</description>
18501                <bitRange>[29:28]</bitRange>
18502                <access>read-write</access>
18503              </field>
18504              <field>
18505                <name>DRIVE_SEL7</name>
18506                <description>Sets the GPIO drive strength for IO pin 7</description>
18507                <bitRange>[31:30]</bitRange>
18508                <access>read-write</access>
18509              </field>
18510            </fields>
18511          </register>
18512          <register>
18513            <name>CFG_SIO</name>
18514            <description>Port SIO configuration register</description>
18515            <addressOffset>0x50</addressOffset>
18516            <size>32</size>
18517            <access>read-write</access>
18518            <resetValue>0x0</resetValue>
18519            <resetMask>0xFFFFFFFF</resetMask>
18520            <fields>
18521              <field>
18522                <name>VREG_EN01</name>
18523                <description>Selects the output buffer mode:
18524'0': Unregulated output buffer
18525'1': Regulated output buffer
18526The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode. If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.</description>
18527                <bitRange>[0:0]</bitRange>
18528                <access>read-write</access>
18529              </field>
18530              <field>
18531                <name>IBUF_SEL01</name>
18532                <description>Selects the input buffer mode:
185330: Singled ended input buffer
185341: Differential input buffer</description>
18535                <bitRange>[1:1]</bitRange>
18536                <access>read-write</access>
18537              </field>
18538              <field>
18539                <name>VTRIP_SEL01</name>
18540                <description>Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'):
18541'0': Input buffer functions as a CMOS input buffer.
18542'1': Input buffer functions as a TTL input buffer.
18543In differential input buffer mode (IBUF_SEL = '1')
18544'0': Trip-point is 0.5*Vddio or 0.5*Voh (depends on VREF_SEL/VOH_SEL)
18545'1': Trip-point is 0.4*Vddio or 1.0*Vref  (depends on VREF_SEL)</description>
18546                <bitRange>[2:2]</bitRange>
18547                <access>read-write</access>
18548              </field>
18549              <field>
18550                <name>VREF_SEL01</name>
18551                <description>Selects reference voltage (Vref) trip-point of the input buffer:
18552'0': Trip-point reference from pin_ref
18553'1': Trip-point reference of SRSS internal reference Vref (1.2 V)
18554'2': Trip-point reference of AMUXBUS_A
18555'3': Trip-point reference of AMUXBUS_B</description>
18556                <bitRange>[4:3]</bitRange>
18557                <access>read-write</access>
18558              </field>
18559              <field>
18560                <name>VOH_SEL01</name>
18561                <description>Selects the regulated Voh output level and trip point of the input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL).
18562'0': Voh = 1*reference; e.g. reference at 1.2V -&gt; Voh = 1.2V
18563'1': Voh = 1.25*reference; e.g. reference at 1.2V -&gt; Voh = 1.5V
18564'2': Voh = 1.49*reference; e.g. reference at 1.2V -&gt; Voh = ~1.8V
18565'3': Voh = 1.67*reference; e.g. reference at 1.2V -&gt; Voh = 2V
18566'4': Voh = 2.08*reference; e.g. reference at 1.2V -&gt; Voh = 2.5V
18567'5': Voh = 2.5*reference; e.g. reference at 1.2V -&gt; Voh = 3V
18568'6': Voh = 2.78*reference; e.g. reference at 1.2V -&gt; Voh = ~3.3V
18569'7': Voh = 4.16*reference; e.g. reference at 1.2V -&gt; Voh = 5.0V
18570Note: The upper value on Voh is limited to Vddio - 400mV</description>
18571                <bitRange>[7:5]</bitRange>
18572                <access>read-write</access>
18573              </field>
18574              <field>
18575                <name>VREG_EN23</name>
18576                <description>See corresponding definition for IO pins 0 and 1</description>
18577                <bitRange>[8:8]</bitRange>
18578                <access>read-write</access>
18579              </field>
18580              <field>
18581                <name>IBUF_SEL23</name>
18582                <description>See corresponding definition for IO pins 0 and 1</description>
18583                <bitRange>[9:9]</bitRange>
18584                <access>read-write</access>
18585              </field>
18586              <field>
18587                <name>VTRIP_SEL23</name>
18588                <description>See corresponding definition for IO pins 0 and 1</description>
18589                <bitRange>[10:10]</bitRange>
18590                <access>read-write</access>
18591              </field>
18592              <field>
18593                <name>VREF_SEL23</name>
18594                <description>See corresponding definition for IO pins 0 and 1</description>
18595                <bitRange>[12:11]</bitRange>
18596                <access>read-write</access>
18597              </field>
18598              <field>
18599                <name>VOH_SEL23</name>
18600                <description>See corresponding definition for IO pins 0 and 1</description>
18601                <bitRange>[15:13]</bitRange>
18602                <access>read-write</access>
18603              </field>
18604              <field>
18605                <name>VREG_EN45</name>
18606                <description>See corresponding definition for IO pins 0 and 1</description>
18607                <bitRange>[16:16]</bitRange>
18608                <access>read-write</access>
18609              </field>
18610              <field>
18611                <name>IBUF_SEL45</name>
18612                <description>See corresponding definition for IO pins 0 and 1</description>
18613                <bitRange>[17:17]</bitRange>
18614                <access>read-write</access>
18615              </field>
18616              <field>
18617                <name>VTRIP_SEL45</name>
18618                <description>See corresponding definition for IO pins 0 and 1</description>
18619                <bitRange>[18:18]</bitRange>
18620                <access>read-write</access>
18621              </field>
18622              <field>
18623                <name>VREF_SEL45</name>
18624                <description>See corresponding definition for IO pins 0 and 1</description>
18625                <bitRange>[20:19]</bitRange>
18626                <access>read-write</access>
18627              </field>
18628              <field>
18629                <name>VOH_SEL45</name>
18630                <description>See corresponding definition for IO pins 0 and 1</description>
18631                <bitRange>[23:21]</bitRange>
18632                <access>read-write</access>
18633              </field>
18634              <field>
18635                <name>VREG_EN67</name>
18636                <description>See corresponding definition for IO pins 0 and 1</description>
18637                <bitRange>[24:24]</bitRange>
18638                <access>read-write</access>
18639              </field>
18640              <field>
18641                <name>IBUF_SEL67</name>
18642                <description>See corresponding definition for IO pins 0 and 1</description>
18643                <bitRange>[25:25]</bitRange>
18644                <access>read-write</access>
18645              </field>
18646              <field>
18647                <name>VTRIP_SEL67</name>
18648                <description>See corresponding definition for IO pins 0 and 1</description>
18649                <bitRange>[26:26]</bitRange>
18650                <access>read-write</access>
18651              </field>
18652              <field>
18653                <name>VREF_SEL67</name>
18654                <description>See corresponding definition for IO pins 0 and 1</description>
18655                <bitRange>[28:27]</bitRange>
18656                <access>read-write</access>
18657              </field>
18658              <field>
18659                <name>VOH_SEL67</name>
18660                <description>See corresponding definition for IO pins 0 and 1</description>
18661                <bitRange>[31:29]</bitRange>
18662                <access>read-write</access>
18663              </field>
18664            </fields>
18665          </register>
18666          <register>
18667            <name>CFG_IN_AUTOLVL</name>
18668            <description>Port input buffer AUTOLVL configuration register</description>
18669            <addressOffset>0x58</addressOffset>
18670            <size>32</size>
18671            <access>read-write</access>
18672            <resetValue>0x0</resetValue>
18673            <resetMask>0xFF</resetMask>
18674            <fields>
18675              <field>
18676                <name>VTRIP_SEL0_1</name>
18677                <description>Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit.  Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field.  This field is used along with CFG_IN.VTRIP_SEL0_0 field as below:
18678{CFG_IN_AUTOLVL.VTRIP_SEL0_1,CFG_IN.VTRIP_SEL0_0}:
186790,0: CMOS
186800,1: TTL
186811,0: input buffer is compatible with automotive.
186821,1: input buffer is compatible with automotvie</description>
18683                <bitRange>[0:0]</bitRange>
18684                <access>read-write</access>
18685                <enumeratedValues>
18686                  <enumeratedValue>
18687                    <name>CMOS_OR_TTL</name>
18688                    <description>Input buffer compatible with CMOS/TTL interfaces as described in CFG_IN.VTRIP_SEL0_0.</description>
18689                    <value>0</value>
18690                  </enumeratedValue>
18691                  <enumeratedValue>
18692                    <name>AUTO</name>
18693                    <description>Input buffer compatible with AUTO (elevated Vil) interfaces when used along with CFG_IN.VTRIP_SEL0_0.</description>
18694                    <value>1</value>
18695                  </enumeratedValue>
18696                </enumeratedValues>
18697              </field>
18698              <field>
18699                <name>VTRIP_SEL1_1</name>
18700                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
18701                <bitRange>[1:1]</bitRange>
18702                <access>read-write</access>
18703              </field>
18704              <field>
18705                <name>VTRIP_SEL2_1</name>
18706                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
18707                <bitRange>[2:2]</bitRange>
18708                <access>read-write</access>
18709              </field>
18710              <field>
18711                <name>VTRIP_SEL3_1</name>
18712                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
18713                <bitRange>[3:3]</bitRange>
18714                <access>read-write</access>
18715              </field>
18716              <field>
18717                <name>VTRIP_SEL4_1</name>
18718                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
18719                <bitRange>[4:4]</bitRange>
18720                <access>read-write</access>
18721              </field>
18722              <field>
18723                <name>VTRIP_SEL5_1</name>
18724                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
18725                <bitRange>[5:5]</bitRange>
18726                <access>read-write</access>
18727              </field>
18728              <field>
18729                <name>VTRIP_SEL6_1</name>
18730                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
18731                <bitRange>[6:6]</bitRange>
18732                <access>read-write</access>
18733              </field>
18734              <field>
18735                <name>VTRIP_SEL7_1</name>
18736                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
18737                <bitRange>[7:7]</bitRange>
18738                <access>read-write</access>
18739              </field>
18740            </fields>
18741          </register>
18742        </cluster>
18743        <register>
18744          <name>INTR_CAUSE0</name>
18745          <description>Interrupt port cause register 0</description>
18746          <addressOffset>0x4000</addressOffset>
18747          <size>32</size>
18748          <access>read-only</access>
18749          <resetValue>0x0</resetValue>
18750          <resetMask>0xFFFFFFFF</resetMask>
18751          <fields>
18752            <field>
18753              <name>PORT_INT</name>
18754              <description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
18755'0': Port has no pending interrupt
18756'1': Port has pending interrupt</description>
18757              <bitRange>[31:0]</bitRange>
18758              <access>read-only</access>
18759            </field>
18760          </fields>
18761        </register>
18762        <register>
18763          <name>INTR_CAUSE1</name>
18764          <description>Interrupt port cause register 1</description>
18765          <addressOffset>0x4004</addressOffset>
18766          <size>32</size>
18767          <access>read-only</access>
18768          <resetValue>0x0</resetValue>
18769          <resetMask>0xFFFFFFFF</resetMask>
18770          <fields>
18771            <field>
18772              <name>PORT_INT</name>
18773              <description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
18774'0': Port has no pending interrupt
18775'1': Port has pending interrupt</description>
18776              <bitRange>[31:0]</bitRange>
18777              <access>read-only</access>
18778            </field>
18779          </fields>
18780        </register>
18781        <register>
18782          <name>INTR_CAUSE2</name>
18783          <description>Interrupt port cause register 2</description>
18784          <addressOffset>0x4008</addressOffset>
18785          <size>32</size>
18786          <access>read-only</access>
18787          <resetValue>0x0</resetValue>
18788          <resetMask>0xFFFFFFFF</resetMask>
18789          <fields>
18790            <field>
18791              <name>PORT_INT</name>
18792              <description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
18793'0': Port has no pending interrupt
18794'1': Port has pending interrupt</description>
18795              <bitRange>[31:0]</bitRange>
18796              <access>read-only</access>
18797            </field>
18798          </fields>
18799        </register>
18800        <register>
18801          <name>INTR_CAUSE3</name>
18802          <description>Interrupt port cause register 3</description>
18803          <addressOffset>0x400C</addressOffset>
18804          <size>32</size>
18805          <access>read-only</access>
18806          <resetValue>0x0</resetValue>
18807          <resetMask>0xFFFFFFFF</resetMask>
18808          <fields>
18809            <field>
18810              <name>PORT_INT</name>
18811              <description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
18812'0': Port has no pending interrupt
18813'1': Port has pending interrupt</description>
18814              <bitRange>[31:0]</bitRange>
18815              <access>read-only</access>
18816            </field>
18817          </fields>
18818        </register>
18819        <register>
18820          <name>VDD_ACTIVE</name>
18821          <description>Extern power supply detection register</description>
18822          <addressOffset>0x4010</addressOffset>
18823          <size>32</size>
18824          <access>read-only</access>
18825          <resetValue>0x0</resetValue>
18826          <resetMask>0xC000FFFF</resetMask>
18827          <fields>
18828            <field>
18829              <name>VDDIO_ACTIVE</name>
18830              <description>Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1).  Note that VDDIO supplies have basic (crude) supply detectors only.  If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it.  For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground.  Any in-between voltage has an undefined result.
18831'0': Supply is not present
18832'1': Supply is present
18833
18834When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation.
18835For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below:
188360: vbackup,
188371: vddio_0,
188382: vddio_1,
188393: vddio_a,
188404: vddio_r,
188415: vddusb'</description>
18842              <bitRange>[15:0]</bitRange>
18843              <access>read-only</access>
18844            </field>
18845            <field>
18846              <name>VDDA_ACTIVE</name>
18847              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
18848              <bitRange>[30:30]</bitRange>
18849              <access>read-only</access>
18850            </field>
18851            <field>
18852              <name>VDDD_ACTIVE</name>
18853              <description>This bit indicates presence of the VDDD supply.  This bit will always read-back 1.  The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.)</description>
18854              <bitRange>[31:31]</bitRange>
18855              <access>read-only</access>
18856            </field>
18857          </fields>
18858        </register>
18859        <register>
18860          <name>VDD_INTR</name>
18861          <description>Supply detection interrupt register</description>
18862          <addressOffset>0x4014</addressOffset>
18863          <size>32</size>
18864          <access>read-write</access>
18865          <resetValue>0x0</resetValue>
18866          <resetMask>0xC000FFFF</resetMask>
18867          <fields>
18868            <field>
18869              <name>VDDIO_ACTIVE</name>
18870              <description>Supply state change detected.
18871'0': No change to supply detected
18872'1': Change to supply detected</description>
18873              <bitRange>[15:0]</bitRange>
18874              <access>read-write</access>
18875            </field>
18876            <field>
18877              <name>VDDA_ACTIVE</name>
18878              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
18879              <bitRange>[30:30]</bitRange>
18880              <access>read-write</access>
18881            </field>
18882            <field>
18883              <name>VDDD_ACTIVE</name>
18884              <description>The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'.</description>
18885              <bitRange>[31:31]</bitRange>
18886              <access>read-write</access>
18887            </field>
18888          </fields>
18889        </register>
18890        <register>
18891          <name>VDD_INTR_MASK</name>
18892          <description>Supply detection interrupt mask register</description>
18893          <addressOffset>0x4018</addressOffset>
18894          <size>32</size>
18895          <access>read-write</access>
18896          <resetValue>0x0</resetValue>
18897          <resetMask>0xC000FFFF</resetMask>
18898          <fields>
18899            <field>
18900              <name>VDDIO_ACTIVE</name>
18901              <description>Masks supply interrupt on VDDIO.
18902'0': VDDIO interrupt forwarding disabled
18903'1': VDDIO interrupt forwarding enabled</description>
18904              <bitRange>[15:0]</bitRange>
18905              <access>read-write</access>
18906            </field>
18907            <field>
18908              <name>VDDA_ACTIVE</name>
18909              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
18910              <bitRange>[30:30]</bitRange>
18911              <access>read-write</access>
18912            </field>
18913            <field>
18914              <name>VDDD_ACTIVE</name>
18915              <description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
18916              <bitRange>[31:31]</bitRange>
18917              <access>read-write</access>
18918            </field>
18919          </fields>
18920        </register>
18921        <register>
18922          <name>VDD_INTR_MASKED</name>
18923          <description>Supply detection interrupt masked register</description>
18924          <addressOffset>0x401C</addressOffset>
18925          <size>32</size>
18926          <access>read-only</access>
18927          <resetValue>0x0</resetValue>
18928          <resetMask>0xC000FFFF</resetMask>
18929          <fields>
18930            <field>
18931              <name>VDDIO_ACTIVE</name>
18932              <description>Supply transition detected AND masked
18933'0': Interrupt was not forwarded to CPU
18934'1': Interrupt occurred and was forwarded to CPU</description>
18935              <bitRange>[15:0]</bitRange>
18936              <access>read-only</access>
18937            </field>
18938            <field>
18939              <name>VDDA_ACTIVE</name>
18940              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
18941              <bitRange>[30:30]</bitRange>
18942              <access>read-only</access>
18943            </field>
18944            <field>
18945              <name>VDDD_ACTIVE</name>
18946              <description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
18947              <bitRange>[31:31]</bitRange>
18948              <access>read-only</access>
18949            </field>
18950          </fields>
18951        </register>
18952        <register>
18953          <name>VDD_INTR_SET</name>
18954          <description>Supply detection interrupt set register</description>
18955          <addressOffset>0x4020</addressOffset>
18956          <size>32</size>
18957          <access>read-write</access>
18958          <resetValue>0x0</resetValue>
18959          <resetMask>0xC000FFFF</resetMask>
18960          <fields>
18961            <field>
18962              <name>VDDIO_ACTIVE</name>
18963              <description>Sets supply interrupt.
18964'0': Interrupt state not affected
18965'1': Interrupt set</description>
18966              <bitRange>[15:0]</bitRange>
18967              <access>read-write</access>
18968            </field>
18969            <field>
18970              <name>VDDA_ACTIVE</name>
18971              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
18972              <bitRange>[30:30]</bitRange>
18973              <access>read-write</access>
18974            </field>
18975            <field>
18976              <name>VDDD_ACTIVE</name>
18977              <description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
18978              <bitRange>[31:31]</bitRange>
18979              <access>read-write</access>
18980            </field>
18981          </fields>
18982        </register>
18983      </registers>
18984    </peripheral>
18985    <peripheral>
18986      <name>SMARTIO</name>
18987      <description>Programmable IO configuration</description>
18988      <baseAddress>0x40320000</baseAddress>
18989      <addressBlock>
18990        <offset>0</offset>
18991        <size>65536</size>
18992        <usage>registers</usage>
18993      </addressBlock>
18994      <registers>
18995        <cluster>
18996          <dim>18</dim>
18997          <dimIncrement>256</dimIncrement>
18998          <name>PRT[%s]</name>
18999          <description>Programmable IO port registers</description>
19000          <addressOffset>0x00000000</addressOffset>
19001          <register>
19002            <name>CTL</name>
19003            <description>Control register</description>
19004            <addressOffset>0x0</addressOffset>
19005            <size>32</size>
19006            <access>read-write</access>
19007            <resetValue>0x2001400</resetValue>
19008            <resetMask>0x82001F00</resetMask>
19009            <fields>
19010              <field>
19011                <name>BYPASS</name>
19012                <description>Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1', this field is used. When ENABLED is '0', this field is NOT used and SMARTIO fabric is always bypassed.
19013'0': No bypass (programmable SMARTIO fabric is exposed).
19014'1': Bypass (programmable SMARTIOIO fabric is hidden).</description>
19015                <bitRange>[7:0]</bitRange>
19016                <access>read-write</access>
19017              </field>
19018              <field>
19019                <name>CLOCK_SRC</name>
19020                <description>Clock ('clk_fabric') and reset ('rst_fabric_n') source selection:
19021'0': io_data_in[0]/'1'.
19022...
19023'7': io_data_in[7]/'1'.
19024'8': chip_data[0]/'1'.
19025...
19026'15': chip_data[7]/'1'.
19027'16': clk_smartio/rst_sys_act_n. Used for both Active functionality synchronous logic on 'clk_smartio'. This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'.
19028'17': clk_smartio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on 'clk_smartio' (note that 'clk_smartio' is NOT available in DeepSleep and Hibernate power modes).  This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'.
19029'18': Same as '17'. Note that the M0S8 SMARTIO version used the Hibernate reset for this value, but the MXS40 SMARTIO version does not support Hibernate functionality.
19030'19': clk_lf/rst_lf_dpslp_n (note that 'clk_lf' is available in DeepSleep power mode). This selection is intended for synchronous operation on'clk_lf'. Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to other 'clk_lf' clocked elements.
19031'20'-'30': Clock source is constant '0'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption.
19032'31': asynchronous mode/'1'.  Select this when clockless operation is configured.
19033
19034NOTE: Two positive edges of the selected clock are required for the block to be enabled (to deactivate reset).  In asynchronous (clockless) mode clk_sys is used to enable the block, but is not available for clocking.</description>
19035                <bitRange>[12:8]</bitRange>
19036                <access>read-write</access>
19037              </field>
19038              <field>
19039                <name>HLD_OVR</name>
19040                <description>IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep output functionality on these IO pads. This field is used to control the hold override functionality from the SMARTIO:
19041'0': The HSIOM controls the IO cell hold override functionality ('hsiom_hld_ovr').
19042'1': The SMARTIO controls the IO cel hold override functionality:
19043- In bypass mode (ENABLED is '0' or BYPASS[i] is '1'), the HSIOM control is used.
19044- In NON bypass mode (ENABLED is '1' and BYPASS[i] is '0'), the SMARTIO sets hold override to 'pwr_hld_ovr_hib' to enable SMARTIO functionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode).</description>
19045                <bitRange>[24:24]</bitRange>
19046                <access>read-write</access>
19047              </field>
19048              <field>
19049                <name>PIPELINE_EN</name>
19050                <description>Enable for pipeline register:
19051'0': Disabled (register is bypassed).
19052'1': Enabled.</description>
19053                <bitRange>[25:25]</bitRange>
19054                <access>read-write</access>
19055              </field>
19056              <field>
19057                <name>ENABLED</name>
19058                <description>Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured:
19059'0': Disabled (signals are bypassed; behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated.
19060
19061If the IP is disabled:
19062- The PIPELINE_EN register field should be set to '1', to ensure low power consumption by preventing combinatorial loops.
19063- The CLOCK_SRC register field should be set to '20'-'30' (clock is constant '0'), to ensure low power consumption.
19064
19065'1': Enabled. Once enabled, it takes 3 'clk_fabric' clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins' input synchronizer states are flushed when the fabric is fully functional.</description>
19066                <bitRange>[31:31]</bitRange>
19067                <access>read-write</access>
19068              </field>
19069            </fields>
19070          </register>
19071          <register>
19072            <name>SYNC_CTL</name>
19073            <description>Synchronization control register</description>
19074            <addressOffset>0x10</addressOffset>
19075            <size>32</size>
19076            <access>read-write</access>
19077            <resetValue>0x0</resetValue>
19078            <resetMask>0x0</resetMask>
19079            <fields>
19080              <field>
19081                <name>IO_SYNC_EN</name>
19082                <description>Synchronization of the IO pin input signals to 'clk_fabric', one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i.
19083'0': No synchronization.
19084'1': Synchronization.</description>
19085                <bitRange>[7:0]</bitRange>
19086                <access>read-write</access>
19087              </field>
19088              <field>
19089                <name>CHIP_SYNC_EN</name>
19090                <description>Synchronization of the chip input signals to 'clk_fabric', one bit for each input: CHIP_SYNC_EN[i] is for input i.
19091'0': No synchronization.
19092'1': Synchronization.</description>
19093                <bitRange>[15:8]</bitRange>
19094                <access>read-write</access>
19095              </field>
19096            </fields>
19097          </register>
19098          <register>
19099            <dim>8</dim>
19100            <dimIncrement>4</dimIncrement>
19101            <name>LUT_SEL[%s]</name>
19102            <description>LUT component input selection</description>
19103            <addressOffset>0x20</addressOffset>
19104            <size>32</size>
19105            <access>read-write</access>
19106            <resetValue>0x0</resetValue>
19107            <resetMask>0x0</resetMask>
19108            <fields>
19109              <field>
19110                <name>LUT_TR0_SEL</name>
19111                <description>LUT input signal 'tr0_in' source selection:
19112'0': Data unit output.
19113'1': LUT 1 output.
19114'2': LUT 2 output.
19115'3': LUT 3 output.
19116'4': LUT 4 output.
19117'5': LUT 5 output.
19118'6': LUT 6 output.
19119'7': LUT 7 output.
19120'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7).
19121'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7).
19122'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7).
19123'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7).
19124'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7).
19125'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7).
19126'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7).
19127'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7).</description>
19128                <bitRange>[3:0]</bitRange>
19129                <access>read-write</access>
19130              </field>
19131              <field>
19132                <name>LUT_TR1_SEL</name>
19133                <description>LUT input signal 'tr1_in' source selection:
19134'0': LUT 0 output.
19135'1': LUT 1 output.
19136'2': LUT 2 output.
19137'3': LUT 3 output.
19138'4': LUT 4 output.
19139'5': LUT 5 output.
19140'6': LUT 6 output.
19141'7': LUT 7 output.
19142'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7).
19143'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7).
19144'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7).
19145'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7).
19146'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7).
19147'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7).
19148'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7).
19149'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7).</description>
19150                <bitRange>[11:8]</bitRange>
19151                <access>read-write</access>
19152              </field>
19153              <field>
19154                <name>LUT_TR2_SEL</name>
19155                <description>LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL.</description>
19156                <bitRange>[19:16]</bitRange>
19157                <access>read-write</access>
19158              </field>
19159            </fields>
19160          </register>
19161          <register>
19162            <dim>8</dim>
19163            <dimIncrement>4</dimIncrement>
19164            <name>LUT_CTL[%s]</name>
19165            <description>LUT component control register</description>
19166            <addressOffset>0x40</addressOffset>
19167            <size>32</size>
19168            <access>read-write</access>
19169            <resetValue>0x0</resetValue>
19170            <resetMask>0x0</resetMask>
19171            <fields>
19172              <field>
19173                <name>LUT</name>
19174                <description>LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg).</description>
19175                <bitRange>[7:0]</bitRange>
19176                <access>read-write</access>
19177              </field>
19178              <field>
19179                <name>LUT_OPC</name>
19180                <description>LUT opcode specifies the LUT operation:
19181'0': Combinatoral output, no feedback.
19182   tr_out   = LUT[{tr2_in, tr1_in, tr0_in}].
19183'1': Combinatorial output, feedback.
19184   tr_out   = LUT[{lut_reg, tr1_in, tr0_in}].
19185On clock:
19186    lut_reg &lt;= tr_in2.
19187'2': Sequential output, no feedback.
19188   temp    = LUT[{tr2_in, tr1_in, tr0_in}].
19189   tr_out   = lut_reg.
19190On clock:
19191   lut_reg &lt;= temp.
19192'3': Register with asynchronous set and reset.
19193   tr_out           = lut_reg.
19194   enable          = (tr2_in ^ LUT[4]) | LUT[5].
19195   set               = enable &amp; (tr1_in ^ LUT[2]) &amp; LUT[3].
19196   clr                = enable &amp; (tr0_in ^ LUT[0]) &amp; LUT[1].
19197Asynchronously (no clock required):
19198   lut_reg         &lt;= if (clr) '0' else if (set) '1'</description>
19199                <bitRange>[9:8]</bitRange>
19200                <access>read-write</access>
19201              </field>
19202            </fields>
19203          </register>
19204          <register>
19205            <name>DU_SEL</name>
19206            <description>Data unit component input selection</description>
19207            <addressOffset>0xC0</addressOffset>
19208            <size>32</size>
19209            <access>read-write</access>
19210            <resetValue>0x0</resetValue>
19211            <resetMask>0x0</resetMask>
19212            <fields>
19213              <field>
19214                <name>DU_TR0_SEL</name>
19215                <description>Data unit input signal 'tr0_in' source selection:
19216'0': Constant '0'.
19217'1': Constant '1'.
19218'2': Data unit output.
19219'10-3': LUT 7 - 0 outputs.
19220Otherwise: Undefined.</description>
19221                <bitRange>[3:0]</bitRange>
19222                <access>read-write</access>
19223              </field>
19224              <field>
19225                <name>DU_TR1_SEL</name>
19226                <description>Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL.</description>
19227                <bitRange>[11:8]</bitRange>
19228                <access>read-write</access>
19229              </field>
19230              <field>
19231                <name>DU_TR2_SEL</name>
19232                <description>Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL.</description>
19233                <bitRange>[19:16]</bitRange>
19234                <access>read-write</access>
19235              </field>
19236              <field>
19237                <name>DU_DATA0_SEL</name>
19238                <description>Data unit input data 'data0_in' source selection:
19239'0': Constant '0'.
19240'1': chip_data[7:0].
19241'2': io_data_in[7:0].
19242'3': DATA.DATA MMIO register field.</description>
19243                <bitRange>[25:24]</bitRange>
19244                <access>read-write</access>
19245              </field>
19246              <field>
19247                <name>DU_DATA1_SEL</name>
19248                <description>Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL.</description>
19249                <bitRange>[29:28]</bitRange>
19250                <access>read-write</access>
19251              </field>
19252            </fields>
19253          </register>
19254          <register>
19255            <name>DU_CTL</name>
19256            <description>Data unit component control register</description>
19257            <addressOffset>0xC4</addressOffset>
19258            <size>32</size>
19259            <access>read-write</access>
19260            <resetValue>0x0</resetValue>
19261            <resetMask>0x0</resetMask>
19262            <fields>
19263              <field>
19264                <name>DU_SIZE</name>
19265                <description>Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits.</description>
19266                <bitRange>[2:0]</bitRange>
19267                <access>read-write</access>
19268              </field>
19269              <field>
19270                <name>DU_OPC</name>
19271                <description>Data unit opcode specifies the data unit operation:
19272'1': INCR
19273'2': DECR
19274'3': INCR_WRAP
19275'4': DECR_WRAP
19276'5': INCR_DECR
19277'6': INCR_DECR_WRAP
19278'7': ROR
19279'8': SHR
19280'9': AND_OR
19281'10': SHR_MAJ3
19282'11': SHR_EQL.
19283Otherwise: Undefined.</description>
19284                <bitRange>[11:8]</bitRange>
19285                <access>read-write</access>
19286              </field>
19287            </fields>
19288          </register>
19289          <register>
19290            <name>DATA</name>
19291            <description>Data register</description>
19292            <addressOffset>0xF0</addressOffset>
19293            <size>32</size>
19294            <access>read-write</access>
19295            <resetValue>0x0</resetValue>
19296            <resetMask>0x0</resetMask>
19297            <fields>
19298              <field>
19299                <name>DATA</name>
19300                <description>Data unit input data source.</description>
19301                <bitRange>[7:0]</bitRange>
19302                <access>read-write</access>
19303              </field>
19304            </fields>
19305          </register>
19306        </cluster>
19307      </registers>
19308    </peripheral>
19309    <peripheral>
19310      <name>TCPWM0</name>
19311      <description>Timer/Counter/PWM</description>
19312      <headerStructName>TCPWM</headerStructName>
19313      <baseAddress>0x40380000</baseAddress>
19314      <addressBlock>
19315        <offset>0</offset>
19316        <size>131072</size>
19317        <usage>registers</usage>
19318      </addressBlock>
19319      <registers>
19320        <cluster>
19321          <dim>3</dim>
19322          <dimIncrement>32768</dimIncrement>
19323          <name>GRP[%s]</name>
19324          <description>Group of counters</description>
19325          <addressOffset>0x00000000</addressOffset>
19326          <cluster>
19327            <dim>63</dim>
19328            <dimIncrement>128</dimIncrement>
19329            <name>CNT[%s]</name>
19330            <description>Timer/Counter/PWM Counter Module</description>
19331            <addressOffset>0x00000000</addressOffset>
19332            <register>
19333              <name>CTRL</name>
19334              <description>Counter control register</description>
19335              <addressOffset>0x0</addressOffset>
19336              <size>32</size>
19337              <access>read-write</access>
19338              <resetValue>0xF0</resetValue>
19339              <resetMask>0xC73737FF</resetMask>
19340              <fields>
19341                <field>
19342                  <name>AUTO_RELOAD_CC0</name>
19343                  <description>Specifies switching of the CC0 and buffered CC0 values. This field has a function in TIMER, QUAD (QUAD_RANGE0_CMP, QUAD_RANGE1_CMP range modes), SR, PWM, PWM_DT and PWM_PR modes.
19344Timer, QUAD, SR modes:
19345'0': never switch.
19346'1': switch on a compare match 0 event.
19347PWM, PWM_DT, PWM_PR modes:
19348'0: never switch.
19349'1': switch on a terminal count event with an actively pending switch event.</description>
19350                  <bitRange>[0:0]</bitRange>
19351                  <access>read-write</access>
19352                </field>
19353                <field>
19354                  <name>AUTO_RELOAD_CC1</name>
19355                  <description>Specifies switching of the CC1 and buffered CC1 values. This field has a function in TIMER, QUAD (QUAD_RANGE0_CMP, QUAD_RANGE1_CMP range modes), SR, PWM, PWM_DT and PWM_PR modes.
19356Timer, QUAD, SR modes:
19357'0': never switch.
19358'1': switch on a compare match 1 event.
19359PWM, PWM_DT, PWM_PR modes:
19360'0: never switch.
19361'1': switch on a terminal count event with an actively pending switch event.</description>
19362                  <bitRange>[1:1]</bitRange>
19363                  <access>read-write</access>
19364                </field>
19365                <field>
19366                  <name>AUTO_RELOAD_PERIOD</name>
19367                  <description>Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM and PWM_DT modes.
19368'0': never switch.
19369'1': switch on a terminal count event with and actively pending switch event.
19370
19371In QUAD mode, QUAD_RANGE0_CMP range mode this field is used to select the index / wrap-around capture function.
19372'0': Captures on index (reload) event. The counter value is copied to the PERIOD register on an index (reload) event.
19373'1': Captures when COUNTER equals 0 or 0xffff. The counter value is copied to the PERIOD register when COUNTER equals 0 or 0xffff.</description>
19374                  <bitRange>[2:2]</bitRange>
19375                  <access>read-write</access>
19376                </field>
19377                <field>
19378                  <name>AUTO_RELOAD_LINE_SEL</name>
19379                  <description>Specifies switching of the LINE_SEL and LINE_BUFF_SEL values. This field has a function in PWM and PWM_PR modes.
19380'0': never switch.
19381'1': switch on a terminal count event with and actively pending switch event.</description>
19382                  <bitRange>[3:3]</bitRange>
19383                  <access>read-write</access>
19384                </field>
19385                <field>
19386                  <name>CC0_MATCH_UP_EN</name>
19387                  <description>Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode.
19388'0': compare match 0 event generation disabled when counting up
19389'1': compare match 0 event generation enabled when counting up
19390
19391This field has a function in PWM and PWM_DT modes only.</description>
19392                  <bitRange>[4:4]</bitRange>
19393                  <access>read-write</access>
19394                </field>
19395                <field>
19396                  <name>CC0_MATCH_DOWN_EN</name>
19397                  <description>Enables / disables the compare match 0 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode.
19398'0': compare match 0 event generation disabled when counting down
19399'1': compare match 0 event generation enabled when counting down
19400
19401This field has a function in PWM and PWM_DT modes only.</description>
19402                  <bitRange>[5:5]</bitRange>
19403                  <access>read-write</access>
19404                </field>
19405                <field>
19406                  <name>CC1_MATCH_UP_EN</name>
19407                  <description>Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting up (STATUS.DOWN = 0) in CNT_UPDN1/2 mode.
19408'0': compare match 1 event generation disabled when counting up
19409'1': compare match 1 event generation enabled when counting up
19410
19411This field has a function in PWM and PWM_DT modes only.</description>
19412                  <bitRange>[6:6]</bitRange>
19413                  <access>read-write</access>
19414                </field>
19415                <field>
19416                  <name>CC1_MATCH_DOWN_EN</name>
19417                  <description>Enables / disables the compare match 1 event generation (COUNTER equals CC0 register) when counting down (STATUS.DOWN = 1) in CNT_UPDN1/2 mode.
19418'0': compare match 1 event generation disabled when counting down
19419'1': compare match 1 event generation enabled when counting down
19420
19421This field has a function in PWM and PWM_DT modes only.</description>
19422                  <bitRange>[7:7]</bitRange>
19423                  <access>read-write</access>
19424                </field>
19425                <field>
19426                  <name>PWM_IMM_KILL</name>
19427                  <description>Specifies whether the kill event immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals or with the next module clock ('active count' pre-scaled 'clk_counter').
19428'0': synchronous kill activation. Deactivates the 'dt_line_out' and 'dt_line_compl_out' signals with the next module clock ('active count' pre-scaled 'clk_counter').
19429'1': immediate kill activation. Immediately deactivates the 'dt_line_out' and 'dt_line_compl_out' signals.
19430
19431This field has a function in PWM, PWM_DT and PWM_PR modes only.</description>
19432                  <bitRange>[8:8]</bitRange>
19433                  <access>read-write</access>
19434                </field>
19435                <field>
19436                  <name>PWM_STOP_ON_KILL</name>
19437                  <description>Specifies whether the counter stops on a kill events:
19438'0': kill event does NOT stop counter.
19439'1': kill event stops counter.
19440
19441This field has a function in PWM, PWM_DT and PWM_PR modes only.</description>
19442                  <bitRange>[9:9]</bitRange>
19443                  <access>read-write</access>
19444                </field>
19445                <field>
19446                  <name>PWM_SYNC_KILL</name>
19447                  <description>Specifies asynchronous/synchronous kill behavior:
19448'1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should  be RISING_EDGE.
19449'0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET.
19450
19451This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.</description>
19452                  <bitRange>[10:10]</bitRange>
19453                  <access>read-write</access>
19454                </field>
19455                <field>
19456                  <name>PWM_DISABLE_MODE</name>
19457                  <description>Specifies the behavior of the PWM outputs 'line_out' and 'line_compl_out' while the TCPWM counter is disabled (CTL.ENABLED='0') or stopped.
19458
19459Note: The output signal of this selection can be further modified by the immediate kill logic and line_out polarity settings (CTRL.QUAD_ENCODING_MODE).</description>
19460                  <bitRange>[13:12]</bitRange>
19461                  <access>read-write</access>
19462                  <enumeratedValues>
19463                    <enumeratedValue>
19464                      <name>Z</name>
19465                      <description>The behavior is the same is in previous mxtcpwm (version 1).
19466
19467When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are NOT driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance).
19468Note: This is realized by driving the TCPWM output 'line_out_en' to 0.
19469
19470When the counter is stopped upon a stop event the PWM outputs are deactivated (to the polarity defined by CTL.QUAD_ENCODING_MODE).</description>
19471                      <value>0</value>
19472                    </enumeratedValue>
19473                    <enumeratedValue>
19474                      <name>RETAIN</name>
19475                      <description>When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM.
19476When the counter is disabled or stopped upon a stop event the PWM outputs are retained (keep their previous levels).
19477While the counter is disabled or stopped the PWM outputs can be changed via LINE_SEL (when parameter GRP_SMC_PRESENT = 1).</description>
19478                      <value>1</value>
19479                    </enumeratedValue>
19480                    <enumeratedValue>
19481                      <name>L</name>
19482                      <description>When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM.
19483When the counter is disabled or stopped upon a stop event the PWM output 'line_out' is driven as a fixed '0' and the PWM output 'line_compl_out' is driven as a fixed '1'.</description>
19484                      <value>2</value>
19485                    </enumeratedValue>
19486                    <enumeratedValue>
19487                      <name>H</name>
19488                      <description>When the counter is disabled the PWM outputs 'line_out' and 'line_compl_out' are driven by the TCPWM.
19489When the counter is disabled or stopped upon a stop event the PWM output 'line_out' is driven as a fixed '1' and the PWM output 'line_compl_out' is driven as a fixed '0'.</description>
19490                      <value>3</value>
19491                    </enumeratedValue>
19492                  </enumeratedValues>
19493                </field>
19494                <field>
19495                  <name>UP_DOWN_MODE</name>
19496                  <description>Determines counter direction.
19497
19498In QUAD mode this field acts as QUAD_RANGE_MODE field selecting between different counter range, reload value and compare / capture behavior.</description>
19499                  <bitRange>[17:16]</bitRange>
19500                  <access>read-write</access>
19501                  <enumeratedValues>
19502                    <enumeratedValue>
19503                      <name>COUNT_UP</name>
19504                      <description>Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.</description>
19505                      <value>0</value>
19506                    </enumeratedValue>
19507                    <enumeratedValue>
19508                      <name>COUNT_DOWN</name>
19509                      <description>Count down (to '0'). An underflow event is generated when  the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.</description>
19510                      <value>1</value>
19511                    </enumeratedValue>
19512                    <enumeratedValue>
19513                      <name>COUNT_UPDN1</name>
19514                      <description>Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.</description>
19515                      <value>2</value>
19516                    </enumeratedValue>
19517                    <enumeratedValue>
19518                      <name>COUNT_UPDN2</name>
19519                      <description>Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).</description>
19520                      <value>3</value>
19521                    </enumeratedValue>
19522                  </enumeratedValues>
19523                </field>
19524                <field>
19525                  <name>ONE_SHOT</name>
19526                  <description>When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.</description>
19527                  <bitRange>[18:18]</bitRange>
19528                  <access>read-write</access>
19529                </field>
19530                <field>
19531                  <name>QUAD_ENCODING_MODE</name>
19532                  <description>In QUAD mode this field selects the quadrature encoding mode (X1/X2/X4) or the Up / Down rotary counting mode.
19533In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'.  Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUAD_ENCODING_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUAD_ENCODING_MODE[1].</description>
19534                  <bitRange>[21:20]</bitRange>
19535                  <access>read-write</access>
19536                  <enumeratedValues>
19537                    <enumeratedValue>
19538                      <name>X1</name>
19539                      <description>X1 encoding (QUAD mode)
19540This encoding is identical with an up / down counting functionality of the following way: Rising edges of input phiA increment or decrement the counter depending on the state of input phiB (direction input).</description>
19541                      <value>0</value>
19542                    </enumeratedValue>
19543                    <enumeratedValue>
19544                      <name>X2</name>
19545                      <description>X2 encoding (QUAD mode)</description>
19546                      <value>1</value>
19547                    </enumeratedValue>
19548                    <enumeratedValue>
19549                      <name>X4</name>
19550                      <description>X4 encoding (QUAD mode)</description>
19551                      <value>2</value>
19552                    </enumeratedValue>
19553                    <enumeratedValue>
19554                      <name>UP_DOWN</name>
19555                      <description>Up / Down rotary counting mode. Input phiA increments the counter, input phiB decrements the counter. The trigger edge detection settings apply.</description>
19556                      <value>3</value>
19557                    </enumeratedValue>
19558                  </enumeratedValues>
19559                </field>
19560                <field>
19561                  <name>MODE</name>
19562                  <description>Counter mode.</description>
19563                  <bitRange>[26:24]</bitRange>
19564                  <access>read-write</access>
19565                  <enumeratedValues>
19566                    <enumeratedValue>
19567                      <name>TIMER</name>
19568                      <description>Timer mode</description>
19569                      <value>0</value>
19570                    </enumeratedValue>
19571                    <enumeratedValue>
19572                      <name>RSVD1</name>
19573                      <description>N/A</description>
19574                      <value>1</value>
19575                    </enumeratedValue>
19576                    <enumeratedValue>
19577                      <name>CAPTURE</name>
19578                      <description>Capture mode</description>
19579                      <value>2</value>
19580                    </enumeratedValue>
19581                    <enumeratedValue>
19582                      <name>QUAD</name>
19583                      <description>Quadrature mode
19584
19585Different encoding modes can be selected by QUAD_ENCODING_MODE including up/down count functionality.
19586Different counter range, reload value and capture behavior can be selected by QUAD_RANGE_MODE (overloaded field UP_DOWN_MODE).</description>
19587                      <value>3</value>
19588                    </enumeratedValue>
19589                    <enumeratedValue>
19590                      <name>PWM</name>
19591                      <description>Pulse width modulation (PWM) mode</description>
19592                      <value>4</value>
19593                    </enumeratedValue>
19594                    <enumeratedValue>
19595                      <name>PWM_DT</name>
19596                      <description>PWM with deadtime insertion mode</description>
19597                      <value>5</value>
19598                    </enumeratedValue>
19599                    <enumeratedValue>
19600                      <name>PWM_PR</name>
19601                      <description>Pseudo random pulse width modulation</description>
19602                      <value>6</value>
19603                    </enumeratedValue>
19604                    <enumeratedValue>
19605                      <name>SR</name>
19606                      <description>Shift register mode.</description>
19607                      <value>7</value>
19608                    </enumeratedValue>
19609                  </enumeratedValues>
19610                </field>
19611                <field>
19612                  <name>DBG_FREEZE_EN</name>
19613                  <description>Specifies the counter behavior in debug mode.
19614'0': The counter operation continues in debug mode.
19615'1': The counter operation freezes in debug mode.</description>
19616                  <bitRange>[30:30]</bitRange>
19617                  <access>read-write</access>
19618                </field>
19619                <field>
19620                  <name>ENABLED</name>
19621                  <description>Counter enable.
19622'0': counter disabled.
19623'1': counter enabled.
19624Counter static configuration information (e.g. CTRL.MODE, all TR_IN_SEL, TR_IN_EDGE_SEL, TR_PWM_CTRL and TR_OUT_SEL register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes:
19625- the associated counter triggers in the CMD register are set to '0'.
19626- the counter's interrupt cause fields in counter's INTR register.
19627- the counter's status fields in counter's STATUS register..
19628- the counter's trigger outputs ('tr_out0' and tr_out1').
19629- the counter's line outputs ('line_out' and 'line_compl_out').</description>
19630                  <bitRange>[31:31]</bitRange>
19631                  <access>read-write</access>
19632                </field>
19633              </fields>
19634            </register>
19635            <register>
19636              <name>STATUS</name>
19637              <description>Counter status register</description>
19638              <addressOffset>0x4</addressOffset>
19639              <size>32</size>
19640              <access>read-only</access>
19641              <resetValue>0x20</resetValue>
19642              <resetMask>0xFFFF8FF1</resetMask>
19643              <fields>
19644                <field>
19645                  <name>DOWN</name>
19646                  <description>When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.</description>
19647                  <bitRange>[0:0]</bitRange>
19648                  <access>read-only</access>
19649                </field>
19650                <field>
19651                  <name>TR_CAPTURE0</name>
19652                  <description>Indicates the actual level of the selected capture 0 trigger.</description>
19653                  <bitRange>[4:4]</bitRange>
19654                  <access>read-only</access>
19655                </field>
19656                <field>
19657                  <name>TR_COUNT</name>
19658                  <description>Indicates the actual level of the selected count trigger.</description>
19659                  <bitRange>[5:5]</bitRange>
19660                  <access>read-only</access>
19661                </field>
19662                <field>
19663                  <name>TR_RELOAD</name>
19664                  <description>Indicates the actual level of the selected reload trigger.</description>
19665                  <bitRange>[6:6]</bitRange>
19666                  <access>read-only</access>
19667                </field>
19668                <field>
19669                  <name>TR_STOP</name>
19670                  <description>Indicates the actual level of the selected stop trigger.</description>
19671                  <bitRange>[7:7]</bitRange>
19672                  <access>read-only</access>
19673                </field>
19674                <field>
19675                  <name>TR_START</name>
19676                  <description>Indicates the actual level of the selected start trigger.</description>
19677                  <bitRange>[8:8]</bitRange>
19678                  <access>read-only</access>
19679                </field>
19680                <field>
19681                  <name>TR_CAPTURE1</name>
19682                  <description>Indicates the actual level of the selected capture 1 trigger.</description>
19683                  <bitRange>[9:9]</bitRange>
19684                  <access>read-only</access>
19685                </field>
19686                <field>
19687                  <name>LINE_OUT</name>
19688                  <description>Indicates the actual level of the PWM line output signal.</description>
19689                  <bitRange>[10:10]</bitRange>
19690                  <access>read-only</access>
19691                </field>
19692                <field>
19693                  <name>LINE_COMPL_OUT</name>
19694                  <description>Indicates the actual level of the complementary PWM line output signal.</description>
19695                  <bitRange>[11:11]</bitRange>
19696                  <access>read-only</access>
19697                </field>
19698                <field>
19699                  <name>RUNNING</name>
19700                  <description>When '0', the counter is NOT running. When '1', the counter is running.
19701
19702This field is used to indicate that the counter is running after a start/reload event and that the counter is stopped after a stop event.
19703When a running counter operation is paused in debug state (see CTRL.DBG_PAUSE) then the RUNNING bit is still '1'.</description>
19704                  <bitRange>[15:15]</bitRange>
19705                  <access>read-only</access>
19706                </field>
19707                <field>
19708                  <name>DT_CNT_L</name>
19709                  <description>Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion (8bit dead time counter or low byte of 16-bit dead time counter).
19710In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.</description>
19711                  <bitRange>[23:16]</bitRange>
19712                  <access>read-only</access>
19713                </field>
19714                <field>
19715                  <name>DT_CNT_H</name>
19716                  <description>High byte of 16-bit dead time counter. In PWM_DT mode, this counter is used for dead time insertion.
19717In all other modes, this field has no effect.
19718
19719Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8bit wide and the only the field DT_CNT_L is used as dead time counter.</description>
19720                  <bitRange>[31:24]</bitRange>
19721                  <access>read-only</access>
19722                </field>
19723              </fields>
19724            </register>
19725            <register>
19726              <name>COUNTER</name>
19727              <description>Counter count register</description>
19728              <addressOffset>0x8</addressOffset>
19729              <size>32</size>
19730              <access>read-write</access>
19731              <resetValue>0x0</resetValue>
19732              <resetMask>0xFFFFFFFF</resetMask>
19733              <fields>
19734                <field>
19735                  <name>COUNTER</name>
19736                  <description>16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.</description>
19737                  <bitRange>[31:0]</bitRange>
19738                  <access>read-write</access>
19739                </field>
19740              </fields>
19741            </register>
19742            <register>
19743              <name>CC0</name>
19744              <description>Counter compare/capture 0 register</description>
19745              <addressOffset>0x10</addressOffset>
19746              <size>32</size>
19747              <access>read-write</access>
19748              <resetValue>0xFFFFFFFF</resetValue>
19749              <resetMask>0xFFFFFFFF</resetMask>
19750              <fields>
19751                <field>
19752                  <name>CC</name>
19753                  <description>In CAPTURE mode, captures the counter value. In other modes, compared to counter value.</description>
19754                  <bitRange>[31:0]</bitRange>
19755                  <access>read-write</access>
19756                </field>
19757              </fields>
19758            </register>
19759            <register>
19760              <name>CC0_BUFF</name>
19761              <description>Counter buffered compare/capture 0 register</description>
19762              <addressOffset>0x14</addressOffset>
19763              <size>32</size>
19764              <access>read-write</access>
19765              <resetValue>0xFFFFFFFF</resetValue>
19766              <resetMask>0xFFFFFFFF</resetMask>
19767              <fields>
19768                <field>
19769                  <name>CC</name>
19770                  <description>Additional buffer for counter CC register.</description>
19771                  <bitRange>[31:0]</bitRange>
19772                  <access>read-write</access>
19773                </field>
19774              </fields>
19775            </register>
19776            <register>
19777              <name>CC1</name>
19778              <description>Counter compare/capture 1 register</description>
19779              <addressOffset>0x18</addressOffset>
19780              <size>32</size>
19781              <access>read-write</access>
19782              <resetValue>0xFFFFFFFF</resetValue>
19783              <resetMask>0xFFFFFFFF</resetMask>
19784              <fields>
19785                <field>
19786                  <name>CC</name>
19787                  <description>In CAPTURE mode, captures the counter value. In other modes, compared to counter value.</description>
19788                  <bitRange>[31:0]</bitRange>
19789                  <access>read-write</access>
19790                </field>
19791              </fields>
19792            </register>
19793            <register>
19794              <name>CC1_BUFF</name>
19795              <description>Counter buffered compare/capture 1 register</description>
19796              <addressOffset>0x1C</addressOffset>
19797              <size>32</size>
19798              <access>read-write</access>
19799              <resetValue>0xFFFFFFFF</resetValue>
19800              <resetMask>0xFFFFFFFF</resetMask>
19801              <fields>
19802                <field>
19803                  <name>CC</name>
19804                  <description>Additional buffer for counter CC1 register.</description>
19805                  <bitRange>[31:0]</bitRange>
19806                  <access>read-write</access>
19807                </field>
19808              </fields>
19809            </register>
19810            <register>
19811              <name>PERIOD</name>
19812              <description>Counter period register</description>
19813              <addressOffset>0x20</addressOffset>
19814              <size>32</size>
19815              <access>read-write</access>
19816              <resetValue>0xFFFFFFFF</resetValue>
19817              <resetMask>0xFFFFFFFF</resetMask>
19818              <fields>
19819                <field>
19820                  <name>PERIOD</name>
19821                  <description>Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.</description>
19822                  <bitRange>[31:0]</bitRange>
19823                  <access>read-write</access>
19824                </field>
19825              </fields>
19826            </register>
19827            <register>
19828              <name>PERIOD_BUFF</name>
19829              <description>Counter buffered period register</description>
19830              <addressOffset>0x24</addressOffset>
19831              <size>32</size>
19832              <access>read-write</access>
19833              <resetValue>0xFFFFFFFF</resetValue>
19834              <resetMask>0xFFFFFFFF</resetMask>
19835              <fields>
19836                <field>
19837                  <name>PERIOD</name>
19838                  <description>Additional buffer for counter PERIOD register.
19839
19840In PWM_PR mode PEROD_BUFF defines the LFSR polynomial. Each bit represents a tap of the shift register which can be feed back to the MSB via an XOR tree.
19841Examples for GRP_CNT_WIDTH = 16:
19842- Maximum length 16bit LFSR
19843  - polynomial x^16 + x^14 + x^13 + x^11 + 1
19844  - taps 0,2,3,5 -&gt; PERIOD = 0x002d
19845  - period is 2^16-1 = 65535 cycles
19846- Maximum length 8bit LFSR:
19847  - polynomial x^8 + x^6 + x^5 + x^4 + 1
19848  - taps 8,10,11,12 (realized in 8 MSBs of 16bit LFSR)
19849  - period is 2^8-1 = 255 cycles
19850
19851In SR mode PERIOD_BUFF defines which tap of the shift register generates the PWM output signals. For a delay of n cycles (from capture event to PWM output) the bit CNT_WIDTH-n should be set to '1'. For a shift register function only one tap should be use, i.e. a one-hot value must be written to PERIOD_BUFF. If multiple bits in PERIOD_BUFF are set then the taps are XOR combined.</description>
19852                  <bitRange>[31:0]</bitRange>
19853                  <access>read-write</access>
19854                </field>
19855              </fields>
19856            </register>
19857            <register>
19858              <name>LINE_SEL</name>
19859              <description>Counter line selection register</description>
19860              <addressOffset>0x28</addressOffset>
19861              <size>32</size>
19862              <access>read-write</access>
19863              <resetValue>0x32</resetValue>
19864              <resetMask>0x77</resetMask>
19865              <fields>
19866                <field>
19867                  <name>OUT_SEL</name>
19868                  <description>Selects the source for the output signal 'line_out'. Default setting is the PWM signal 'line'. Other settings are useful for Stepper Motor Control.
19869This field has a function in PWM and PWM_PR modes only.
19870
19871Note: The output signal of this selection can be further modified by the stop / kill logic and line_out polarity setting (CTRL.QUAD_ENCODING_MODE[0]).</description>
19872                  <bitRange>[2:0]</bitRange>
19873                  <access>read-write</access>
19874                  <enumeratedValues>
19875                    <enumeratedValue>
19876                      <name>L</name>
19877                      <description>fixed '0'</description>
19878                      <value>0</value>
19879                    </enumeratedValue>
19880                    <enumeratedValue>
19881                      <name>H</name>
19882                      <description>fixed '1'</description>
19883                      <value>1</value>
19884                    </enumeratedValue>
19885                    <enumeratedValue>
19886                      <name>PWM</name>
19887                      <description>PWM signal 'line'</description>
19888                      <value>2</value>
19889                    </enumeratedValue>
19890                    <enumeratedValue>
19891                      <name>PWM_INV</name>
19892                      <description>inverted PWM signal 'line'</description>
19893                      <value>3</value>
19894                    </enumeratedValue>
19895                    <enumeratedValue>
19896                      <name>Z</name>
19897                      <description>The output 'line_out' is not driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance).
19898
19899Note: This is realized by driving the output 'line_out_en' to 0.</description>
19900                      <value>4</value>
19901                    </enumeratedValue>
19902                    <enumeratedValue>
19903                      <name>RSVD5</name>
19904                      <description>N/A</description>
19905                      <value>5</value>
19906                    </enumeratedValue>
19907                    <enumeratedValue>
19908                      <name>RSVD6</name>
19909                      <description>N/A</description>
19910                      <value>6</value>
19911                    </enumeratedValue>
19912                    <enumeratedValue>
19913                      <name>RSVD7</name>
19914                      <description>N/A</description>
19915                      <value>7</value>
19916                    </enumeratedValue>
19917                  </enumeratedValues>
19918                </field>
19919                <field>
19920                  <name>COMPL_OUT_SEL</name>
19921                  <description>Selects the source for the output signal 'line_compl_out'. Default setting is the inverted PWM signal 'line'. Other settings are useful for Stepper Motor Control.
19922This field has a function in PWM and PWM_PR modes only.
19923
19924Note: The output signal of this selection can be further modified by the stop / kill logic and line_compl_out polarity setting (CTRL.QUAD_ENCODING_MODE[1]).</description>
19925                  <bitRange>[6:4]</bitRange>
19926                  <access>read-write</access>
19927                  <enumeratedValues>
19928                    <enumeratedValue>
19929                      <name>L</name>
19930                      <description>fixed '0'</description>
19931                      <value>0</value>
19932                    </enumeratedValue>
19933                    <enumeratedValue>
19934                      <name>H</name>
19935                      <description>fixed '1'</description>
19936                      <value>1</value>
19937                    </enumeratedValue>
19938                    <enumeratedValue>
19939                      <name>PWM</name>
19940                      <description>PWM signal 'line'</description>
19941                      <value>2</value>
19942                    </enumeratedValue>
19943                    <enumeratedValue>
19944                      <name>PWM_INV</name>
19945                      <description>inverted PWM signal 'line'</description>
19946                      <value>3</value>
19947                    </enumeratedValue>
19948                    <enumeratedValue>
19949                      <name>Z</name>
19950                      <description>The output 'line_compl_out' is not driven by the TCPWM. Instead the port default level configuration applies, e.g. 'Z' (high impedance).
19951
19952Note: This is realized by driving the output 'line_compl_out_en' to 0.</description>
19953                      <value>4</value>
19954                    </enumeratedValue>
19955                    <enumeratedValue>
19956                      <name>RSVD5</name>
19957                      <description>N/A</description>
19958                      <value>5</value>
19959                    </enumeratedValue>
19960                    <enumeratedValue>
19961                      <name>RSVD6</name>
19962                      <description>N/A</description>
19963                      <value>6</value>
19964                    </enumeratedValue>
19965                    <enumeratedValue>
19966                      <name>RSVD7</name>
19967                      <description>N/A</description>
19968                      <value>7</value>
19969                    </enumeratedValue>
19970                  </enumeratedValues>
19971                </field>
19972              </fields>
19973            </register>
19974            <register>
19975              <name>LINE_SEL_BUFF</name>
19976              <description>Counter buffered line selection register</description>
19977              <addressOffset>0x2C</addressOffset>
19978              <size>32</size>
19979              <access>read-write</access>
19980              <resetValue>0x32</resetValue>
19981              <resetMask>0x77</resetMask>
19982              <fields>
19983                <field>
19984                  <name>OUT_SEL</name>
19985                  <description>Buffer for LINE_SEL.OUT_SEL.
19986Can be exchanged with LINE_SEL.LINE_OUT_SEL on a terminal count event with an actively pending switch event.
19987
19988This field has a function in PWM and PWM_PR modes only.</description>
19989                  <bitRange>[2:0]</bitRange>
19990                  <access>read-write</access>
19991                </field>
19992                <field>
19993                  <name>COMPL_OUT_SEL</name>
19994                  <description>Buffer for LINE_SEL.COMPL.OUT_SEL.
19995Can be exchanged with LINE_SEL.LINE_COMPL_OUT_SEL on a terminal count event with an actively pending switch event.
19996
19997This field has a function in PWM and PWM_PR modes only.</description>
19998                  <bitRange>[6:4]</bitRange>
19999                  <access>read-write</access>
20000                </field>
20001              </fields>
20002            </register>
20003            <register>
20004              <name>DT</name>
20005              <description>Counter PWM dead time register</description>
20006              <addressOffset>0x30</addressOffset>
20007              <size>32</size>
20008              <access>read-write</access>
20009              <resetValue>0x0</resetValue>
20010              <resetMask>0xFFFFFFFF</resetMask>
20011              <fields>
20012                <field>
20013                  <name>DT_LINE_OUT_L</name>
20014                  <description>In PWM_DT mode, this field is used to determine the low byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain.
20015In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.
20016
20017Note: This field determines the low byte of the 16-bit dead time before activating 'line_out' when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by this DT_LINE_OUT_L field is used before activating 'line_out' and 'line_compl_out'.</description>
20018                  <bitRange>[7:0]</bitRange>
20019                  <access>read-write</access>
20020                </field>
20021                <field>
20022                  <name>DT_LINE_OUT_H</name>
20023                  <description>In PWM_DT mode, this field is used to determine the high byte of the dead time before activating the PWM line output signal 'line_out': amount of dead time cycles in the counter clock domain.
20024In all other modes, this field  has no effect.
20025
20026Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by field DT_LINE_OUT_L is used before activating 'line_out' and 'line_compl_out'.</description>
20027                  <bitRange>[15:8]</bitRange>
20028                  <access>read-write</access>
20029                </field>
20030                <field>
20031                  <name>DT_LINE_COMPL_OUT</name>
20032                  <description>In PWM_DT mode, this field is used to determine the dead time before activating the complementary PWM line output signal 'line_compl_out': amount of dead time cycles in the counter clock domain.
20033In all other modes, this field  has no effect.
20034
20035Note: This field only exists when parameter GRP_AMC_PRESENT for advanced motor control is set to 1. Otherwise the dead time is only 8 bit wide and the same dead time specified by field DT_LINE_OUT_L is used before activating 'line_out' and 'line_compl_out'.</description>
20036                  <bitRange>[31:16]</bitRange>
20037                  <access>read-write</access>
20038                </field>
20039              </fields>
20040            </register>
20041            <register>
20042              <name>TR_CMD</name>
20043              <description>Counter trigger command register</description>
20044              <addressOffset>0x40</addressOffset>
20045              <size>32</size>
20046              <access>read-write</access>
20047              <resetValue>0x0</resetValue>
20048              <resetMask>0x3D</resetMask>
20049              <fields>
20050                <field>
20051                  <name>CAPTURE0</name>
20052                  <description>SW capture 0 trigger. When written with '1', a capture 0 trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.ENABLED, the field is immediately set to '0'.</description>
20053                  <bitRange>[0:0]</bitRange>
20054                  <access>read-write</access>
20055                </field>
20056                <field>
20057                  <name>RELOAD</name>
20058                  <description>SW reload trigger. For HW behavior, see COUNTER_CAPTURE0 field.</description>
20059                  <bitRange>[2:2]</bitRange>
20060                  <access>read-write</access>
20061                </field>
20062                <field>
20063                  <name>STOP</name>
20064                  <description>SW stop trigger. For HW behavior, see COUNTER_CAPTURE0 field.</description>
20065                  <bitRange>[3:3]</bitRange>
20066                  <access>read-write</access>
20067                </field>
20068                <field>
20069                  <name>START</name>
20070                  <description>SW start trigger. For HW behavior, see COUNTER_CAPTURE0 field.</description>
20071                  <bitRange>[4:4]</bitRange>
20072                  <access>read-write</access>
20073                </field>
20074                <field>
20075                  <name>CAPTURE1</name>
20076                  <description>SW capture 1 trigger. For HW behavior, see COUNTER_CAPTURE0 field.</description>
20077                  <bitRange>[5:5]</bitRange>
20078                  <access>read-write</access>
20079                </field>
20080              </fields>
20081            </register>
20082            <register>
20083              <name>TR_IN_SEL0</name>
20084              <description>Counter input trigger selection register 0</description>
20085              <addressOffset>0x44</addressOffset>
20086              <size>32</size>
20087              <access>read-write</access>
20088              <resetValue>0x100</resetValue>
20089              <resetMask>0xFFFFFFFF</resetMask>
20090              <fields>
20091                <field>
20092                  <name>CAPTURE0_SEL</name>
20093                  <description>Selects one of the up to 256 input triggers as a capture0 trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. If existing, the one-to-one trigger inputs 'tr_one_cnt_in' (different to each counter) are selected by setting 2 and above. The settings above are used for the general purpose trigger inputs 'tr_all_cnt_in' connected to all counters selected.
20094In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.</description>
20095                  <bitRange>[7:0]</bitRange>
20096                  <access>read-write</access>
20097                </field>
20098                <field>
20099                  <name>COUNT_SEL</name>
20100                  <description>Selects one of the 256 input triggers as a count trigger.
20101In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.
20102
20103Note: In the modes: TIMER, CAPTURE, PWM, PWM_DT, and SR, If the counter is externally triggered ( COUNT_SEL &gt; 1), an external trigger will be required for each TR_CMD to execute. For example, a write to TR_CMD.START will not start the counter until the trigger selected by COUNT_SEL asserts. The next trigger will increment the counter since the counter is now running. This goes for all TR_CMD fields.</description>
20104                  <bitRange>[15:8]</bitRange>
20105                  <access>read-write</access>
20106                </field>
20107                <field>
20108                  <name>RELOAD_SEL</name>
20109                  <description>Selects one of the 256 input triggers as a reload trigger.
20110In QUAD mode, this is the index or revolution pulse. In these modes, it will update the counter with 0x8000 (counter midpoint) or 0x0000 depending on the QUAD_RANGE_MODE.</description>
20111                  <bitRange>[23:16]</bitRange>
20112                  <access>read-write</access>
20113                </field>
20114                <field>
20115                  <name>STOP_SEL</name>
20116                  <description>Selects one of the 256 input triggers as a stop trigger.
20117In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be  asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.</description>
20118                  <bitRange>[31:24]</bitRange>
20119                  <access>read-write</access>
20120                </field>
20121              </fields>
20122            </register>
20123            <register>
20124              <name>TR_IN_SEL1</name>
20125              <description>Counter input trigger selection register 1</description>
20126              <addressOffset>0x48</addressOffset>
20127              <size>32</size>
20128              <access>read-write</access>
20129              <resetValue>0x0</resetValue>
20130              <resetMask>0xFFFF</resetMask>
20131              <fields>
20132                <field>
20133                  <name>START_SEL</name>
20134                  <description>Selects one of the 256 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).</description>
20135                  <bitRange>[7:0]</bitRange>
20136                  <access>read-write</access>
20137                </field>
20138                <field>
20139                  <name>CAPTURE1_SEL</name>
20140                  <description>Selects one of the 256 input triggers as a capture 1 trigger.</description>
20141                  <bitRange>[15:8]</bitRange>
20142                  <access>read-write</access>
20143                </field>
20144              </fields>
20145            </register>
20146            <register>
20147              <name>TR_IN_EDGE_SEL</name>
20148              <description>Counter input trigger edge selection register</description>
20149              <addressOffset>0x4C</addressOffset>
20150              <size>32</size>
20151              <access>read-write</access>
20152              <resetValue>0xFFF</resetValue>
20153              <resetMask>0xFFF</resetMask>
20154              <fields>
20155                <field>
20156                  <name>CAPTURE0_EDGE</name>
20157                  <description>A capture 0 event will copy the counter value into the CC0 register.</description>
20158                  <bitRange>[1:0]</bitRange>
20159                  <access>read-write</access>
20160                  <enumeratedValues>
20161                    <enumeratedValue>
20162                      <name>RISING_EDGE</name>
20163                      <description>Rising edge. Any rising edge generates an event.</description>
20164                      <value>0</value>
20165                    </enumeratedValue>
20166                    <enumeratedValue>
20167                      <name>FALLING_EDGE</name>
20168                      <description>Falling edge. Any falling edge generates an event.</description>
20169                      <value>1</value>
20170                    </enumeratedValue>
20171                    <enumeratedValue>
20172                      <name>ANY_EDGE</name>
20173                      <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
20174                      <value>2</value>
20175                    </enumeratedValue>
20176                    <enumeratedValue>
20177                      <name>NO_EDGE_DET</name>
20178                      <description>No edge detection, use trigger as is.</description>
20179                      <value>3</value>
20180                    </enumeratedValue>
20181                  </enumeratedValues>
20182                </field>
20183                <field>
20184                  <name>COUNT_EDGE</name>
20185                  <description>A counter event will increase or decrease the counter by '1'.</description>
20186                  <bitRange>[3:2]</bitRange>
20187                  <access>read-write</access>
20188                  <enumeratedValues>
20189                    <enumeratedValue>
20190                      <name>RISING_EDGE</name>
20191                      <description>Rising edge. Any rising edge generates an event.</description>
20192                      <value>0</value>
20193                    </enumeratedValue>
20194                    <enumeratedValue>
20195                      <name>FALLING_EDGE</name>
20196                      <description>Falling edge. Any falling edge generates an event.</description>
20197                      <value>1</value>
20198                    </enumeratedValue>
20199                    <enumeratedValue>
20200                      <name>ANY_EDGE</name>
20201                      <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
20202                      <value>2</value>
20203                    </enumeratedValue>
20204                    <enumeratedValue>
20205                      <name>NO_EDGE_DET</name>
20206                      <description>No edge detection, use trigger as is.</description>
20207                      <value>3</value>
20208                    </enumeratedValue>
20209                  </enumeratedValues>
20210                </field>
20211                <field>
20212                  <name>RELOAD_EDGE</name>
20213                  <description>A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.</description>
20214                  <bitRange>[5:4]</bitRange>
20215                  <access>read-write</access>
20216                  <enumeratedValues>
20217                    <enumeratedValue>
20218                      <name>RISING_EDGE</name>
20219                      <description>Rising edge. Any rising edge generates an event.</description>
20220                      <value>0</value>
20221                    </enumeratedValue>
20222                    <enumeratedValue>
20223                      <name>FALLING_EDGE</name>
20224                      <description>Falling edge. Any falling edge generates an event.</description>
20225                      <value>1</value>
20226                    </enumeratedValue>
20227                    <enumeratedValue>
20228                      <name>ANY_EDGE</name>
20229                      <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
20230                      <value>2</value>
20231                    </enumeratedValue>
20232                    <enumeratedValue>
20233                      <name>NO_EDGE_DET</name>
20234                      <description>No edge detection, use trigger as is.</description>
20235                      <value>3</value>
20236                    </enumeratedValue>
20237                  </enumeratedValues>
20238                </field>
20239                <field>
20240                  <name>STOP_EDGE</name>
20241                  <description>A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.</description>
20242                  <bitRange>[7:6]</bitRange>
20243                  <access>read-write</access>
20244                  <enumeratedValues>
20245                    <enumeratedValue>
20246                      <name>RISING_EDGE</name>
20247                      <description>Rising edge. Any rising edge generates an event.</description>
20248                      <value>0</value>
20249                    </enumeratedValue>
20250                    <enumeratedValue>
20251                      <name>FALLING_EDGE</name>
20252                      <description>Falling edge. Any falling edge generates an event.</description>
20253                      <value>1</value>
20254                    </enumeratedValue>
20255                    <enumeratedValue>
20256                      <name>ANY_EDGE</name>
20257                      <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
20258                      <value>2</value>
20259                    </enumeratedValue>
20260                    <enumeratedValue>
20261                      <name>NO_EDGE_DET</name>
20262                      <description>No edge detection, use trigger as is.</description>
20263                      <value>3</value>
20264                    </enumeratedValue>
20265                  </enumeratedValues>
20266                </field>
20267                <field>
20268                  <name>START_EDGE</name>
20269                  <description>A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.</description>
20270                  <bitRange>[9:8]</bitRange>
20271                  <access>read-write</access>
20272                  <enumeratedValues>
20273                    <enumeratedValue>
20274                      <name>RISING_EDGE</name>
20275                      <description>Rising edge. Any rising edge generates an event.</description>
20276                      <value>0</value>
20277                    </enumeratedValue>
20278                    <enumeratedValue>
20279                      <name>FALLING_EDGE</name>
20280                      <description>Falling edge. Any falling edge generates an event.</description>
20281                      <value>1</value>
20282                    </enumeratedValue>
20283                    <enumeratedValue>
20284                      <name>ANY_EDGE</name>
20285                      <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
20286                      <value>2</value>
20287                    </enumeratedValue>
20288                    <enumeratedValue>
20289                      <name>NO_EDGE_DET</name>
20290                      <description>No edge detection, use trigger as is.</description>
20291                      <value>3</value>
20292                    </enumeratedValue>
20293                  </enumeratedValues>
20294                </field>
20295                <field>
20296                  <name>CAPTURE1_EDGE</name>
20297                  <description>A capture 1 event will copy the counter value into the CC1 register.</description>
20298                  <bitRange>[11:10]</bitRange>
20299                  <access>read-write</access>
20300                  <enumeratedValues>
20301                    <enumeratedValue>
20302                      <name>RISING_EDGE</name>
20303                      <description>Rising edge. Any rising edge generates an event.</description>
20304                      <value>0</value>
20305                    </enumeratedValue>
20306                    <enumeratedValue>
20307                      <name>FALLING_EDGE</name>
20308                      <description>Falling edge. Any falling edge generates an event.</description>
20309                      <value>1</value>
20310                    </enumeratedValue>
20311                    <enumeratedValue>
20312                      <name>ANY_EDGE</name>
20313                      <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
20314                      <value>2</value>
20315                    </enumeratedValue>
20316                    <enumeratedValue>
20317                      <name>NO_EDGE_DET</name>
20318                      <description>No edge detection, use trigger as is.</description>
20319                      <value>3</value>
20320                    </enumeratedValue>
20321                  </enumeratedValues>
20322                </field>
20323              </fields>
20324            </register>
20325            <register>
20326              <name>TR_PWM_CTRL</name>
20327              <description>Counter trigger PWM control register</description>
20328              <addressOffset>0x50</addressOffset>
20329              <size>32</size>
20330              <access>read-write</access>
20331              <resetValue>0xFF</resetValue>
20332              <resetMask>0xFF</resetMask>
20333              <fields>
20334                <field>
20335                  <name>CC0_MATCH_MODE</name>
20336                  <description>Determines the effect of a compare match 0 event (COUNTER equals CC0 register) on the 'line_out' output signals.  Note that INVERT is especially useful for center aligned pulse width modulation.
20337To generate a duty cycle of 0 percent, the counter CC0 register should be set to '0'. For a 100 percent duty cycle, the counter CC0 register should be set to larger than the counter PERIOD register.</description>
20338                  <bitRange>[1:0]</bitRange>
20339                  <access>read-write</access>
20340                  <enumeratedValues>
20341                    <enumeratedValue>
20342                      <name>SET</name>
20343                      <description>Set to '1'</description>
20344                      <value>0</value>
20345                    </enumeratedValue>
20346                    <enumeratedValue>
20347                      <name>CLEAR</name>
20348                      <description>Set to '0'</description>
20349                      <value>1</value>
20350                    </enumeratedValue>
20351                    <enumeratedValue>
20352                      <name>INVERT</name>
20353                      <description>Invert</description>
20354                      <value>2</value>
20355                    </enumeratedValue>
20356                    <enumeratedValue>
20357                      <name>NO_CHANGE</name>
20358                      <description>No Change</description>
20359                      <value>3</value>
20360                    </enumeratedValue>
20361                  </enumeratedValues>
20362                </field>
20363                <field>
20364                  <name>OVERFLOW_MODE</name>
20365                  <description>Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.</description>
20366                  <bitRange>[3:2]</bitRange>
20367                  <access>read-write</access>
20368                  <enumeratedValues>
20369                    <enumeratedValue>
20370                      <name>SET</name>
20371                      <description>Set to '1'</description>
20372                      <value>0</value>
20373                    </enumeratedValue>
20374                    <enumeratedValue>
20375                      <name>CLEAR</name>
20376                      <description>Set to '0'</description>
20377                      <value>1</value>
20378                    </enumeratedValue>
20379                    <enumeratedValue>
20380                      <name>INVERT</name>
20381                      <description>Invert</description>
20382                      <value>2</value>
20383                    </enumeratedValue>
20384                    <enumeratedValue>
20385                      <name>NO_CHANGE</name>
20386                      <description>No Change</description>
20387                      <value>3</value>
20388                    </enumeratedValue>
20389                  </enumeratedValues>
20390                </field>
20391                <field>
20392                  <name>UNDERFLOW_MODE</name>
20393                  <description>Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.</description>
20394                  <bitRange>[5:4]</bitRange>
20395                  <access>read-write</access>
20396                  <enumeratedValues>
20397                    <enumeratedValue>
20398                      <name>SET</name>
20399                      <description>Set to '1'</description>
20400                      <value>0</value>
20401                    </enumeratedValue>
20402                    <enumeratedValue>
20403                      <name>CLEAR</name>
20404                      <description>Set to '0'</description>
20405                      <value>1</value>
20406                    </enumeratedValue>
20407                    <enumeratedValue>
20408                      <name>INVERT</name>
20409                      <description>Invert</description>
20410                      <value>2</value>
20411                    </enumeratedValue>
20412                    <enumeratedValue>
20413                      <name>NO_CHANGE</name>
20414                      <description>No Change</description>
20415                      <value>3</value>
20416                    </enumeratedValue>
20417                  </enumeratedValues>
20418                </field>
20419                <field>
20420                  <name>CC1_MATCH_MODE</name>
20421                  <description>Determines the effect of a compare match 1 event (COUNTER equals CC1 register) on the 'line_out' output signals.</description>
20422                  <bitRange>[7:6]</bitRange>
20423                  <access>read-write</access>
20424                  <enumeratedValues>
20425                    <enumeratedValue>
20426                      <name>SET</name>
20427                      <description>Set to '1'</description>
20428                      <value>0</value>
20429                    </enumeratedValue>
20430                    <enumeratedValue>
20431                      <name>CLEAR</name>
20432                      <description>Set to '0'</description>
20433                      <value>1</value>
20434                    </enumeratedValue>
20435                    <enumeratedValue>
20436                      <name>INVERT</name>
20437                      <description>Invert</description>
20438                      <value>2</value>
20439                    </enumeratedValue>
20440                    <enumeratedValue>
20441                      <name>NO_CHANGE</name>
20442                      <description>No Change</description>
20443                      <value>3</value>
20444                    </enumeratedValue>
20445                  </enumeratedValues>
20446                </field>
20447              </fields>
20448            </register>
20449            <register>
20450              <name>TR_OUT_SEL</name>
20451              <description>Counter output trigger selection register</description>
20452              <addressOffset>0x54</addressOffset>
20453              <size>32</size>
20454              <access>read-write</access>
20455              <resetValue>0x32</resetValue>
20456              <resetMask>0x77</resetMask>
20457              <fields>
20458                <field>
20459                  <name>OUT0</name>
20460                  <description>Selects one of the internal events to generate the output trigger 0. Default setting selects the terminal count event.</description>
20461                  <bitRange>[2:0]</bitRange>
20462                  <access>read-write</access>
20463                  <enumeratedValues>
20464                    <enumeratedValue>
20465                      <name>OVERFLOW</name>
20466                      <description>Overflow event</description>
20467                      <value>0</value>
20468                    </enumeratedValue>
20469                    <enumeratedValue>
20470                      <name>UNDERFLOW</name>
20471                      <description>Underflow event</description>
20472                      <value>1</value>
20473                    </enumeratedValue>
20474                    <enumeratedValue>
20475                      <name>TC</name>
20476                      <description>Terminal count event (default selection)</description>
20477                      <value>2</value>
20478                    </enumeratedValue>
20479                    <enumeratedValue>
20480                      <name>CC0_MATCH</name>
20481                      <description>Compare match 0 event</description>
20482                      <value>3</value>
20483                    </enumeratedValue>
20484                    <enumeratedValue>
20485                      <name>CC1_MATCH</name>
20486                      <description>Compare match 1 event</description>
20487                      <value>4</value>
20488                    </enumeratedValue>
20489                    <enumeratedValue>
20490                      <name>LINE_OUT</name>
20491                      <description>PWM output signal 'line_out'</description>
20492                      <value>5</value>
20493                    </enumeratedValue>
20494                    <enumeratedValue>
20495                      <name>RSVD6</name>
20496                      <description>N/A</description>
20497                      <value>6</value>
20498                    </enumeratedValue>
20499                    <enumeratedValue>
20500                      <name>Disabled</name>
20501                      <description>Output trigger disabled.</description>
20502                      <value>7</value>
20503                    </enumeratedValue>
20504                  </enumeratedValues>
20505                </field>
20506                <field>
20507                  <name>OUT1</name>
20508                  <description>Selects one of the internal events to generate the output trigger 1. Default setting selects the compare match 0 event.</description>
20509                  <bitRange>[6:4]</bitRange>
20510                  <access>read-write</access>
20511                  <enumeratedValues>
20512                    <enumeratedValue>
20513                      <name>OVERFLOW</name>
20514                      <description>Overflow event</description>
20515                      <value>0</value>
20516                    </enumeratedValue>
20517                    <enumeratedValue>
20518                      <name>UNDERFLOW</name>
20519                      <description>Underflow event</description>
20520                      <value>1</value>
20521                    </enumeratedValue>
20522                    <enumeratedValue>
20523                      <name>TC</name>
20524                      <description>Terminal count event</description>
20525                      <value>2</value>
20526                    </enumeratedValue>
20527                    <enumeratedValue>
20528                      <name>CC0_MATCH</name>
20529                      <description>Compare match 0 event (default selection)</description>
20530                      <value>3</value>
20531                    </enumeratedValue>
20532                    <enumeratedValue>
20533                      <name>CC1_MATCH</name>
20534                      <description>Compare match 1 event</description>
20535                      <value>4</value>
20536                    </enumeratedValue>
20537                    <enumeratedValue>
20538                      <name>LINE_OUT</name>
20539                      <description>PWM output signal 'line_out'</description>
20540                      <value>5</value>
20541                    </enumeratedValue>
20542                    <enumeratedValue>
20543                      <name>RSVD6</name>
20544                      <description>N/A</description>
20545                      <value>6</value>
20546                    </enumeratedValue>
20547                    <enumeratedValue>
20548                      <name>Disabled</name>
20549                      <description>Output trigger disabled.</description>
20550                      <value>7</value>
20551                    </enumeratedValue>
20552                  </enumeratedValues>
20553                </field>
20554              </fields>
20555            </register>
20556            <register>
20557              <name>INTR</name>
20558              <description>Interrupt request register</description>
20559              <addressOffset>0x70</addressOffset>
20560              <size>32</size>
20561              <access>read-write</access>
20562              <resetValue>0x0</resetValue>
20563              <resetMask>0x7</resetMask>
20564              <fields>
20565                <field>
20566                  <name>TC</name>
20567                  <description>Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.</description>
20568                  <bitRange>[0:0]</bitRange>
20569                  <access>read-write</access>
20570                </field>
20571                <field>
20572                  <name>CC0_MATCH</name>
20573                  <description>Counter matches CC0 register event. Set to '1', when event is detected. Write with '1' to clear bit.</description>
20574                  <bitRange>[1:1]</bitRange>
20575                  <access>read-write</access>
20576                </field>
20577                <field>
20578                  <name>CC1_MATCH</name>
20579                  <description>Counter matches CC1 register event. Set to '1', when event is detected. Write with '1' to clear bit.</description>
20580                  <bitRange>[2:2]</bitRange>
20581                  <access>read-write</access>
20582                </field>
20583              </fields>
20584            </register>
20585            <register>
20586              <name>INTR_SET</name>
20587              <description>Interrupt set request register</description>
20588              <addressOffset>0x74</addressOffset>
20589              <size>32</size>
20590              <access>read-write</access>
20591              <resetValue>0x0</resetValue>
20592              <resetMask>0x7</resetMask>
20593              <fields>
20594                <field>
20595                  <name>TC</name>
20596                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
20597                  <bitRange>[0:0]</bitRange>
20598                  <access>read-write</access>
20599                </field>
20600                <field>
20601                  <name>CC0_MATCH</name>
20602                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
20603                  <bitRange>[1:1]</bitRange>
20604                  <access>read-write</access>
20605                </field>
20606                <field>
20607                  <name>CC1_MATCH</name>
20608                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
20609                  <bitRange>[2:2]</bitRange>
20610                  <access>read-write</access>
20611                </field>
20612              </fields>
20613            </register>
20614            <register>
20615              <name>INTR_MASK</name>
20616              <description>Interrupt mask register</description>
20617              <addressOffset>0x78</addressOffset>
20618              <size>32</size>
20619              <access>read-write</access>
20620              <resetValue>0x0</resetValue>
20621              <resetMask>0x7</resetMask>
20622              <fields>
20623                <field>
20624                  <name>TC</name>
20625                  <description>Mask bit for corresponding bit in interrupt request register.</description>
20626                  <bitRange>[0:0]</bitRange>
20627                  <access>read-write</access>
20628                </field>
20629                <field>
20630                  <name>CC0_MATCH</name>
20631                  <description>Mask bit for corresponding bit in interrupt request register.</description>
20632                  <bitRange>[1:1]</bitRange>
20633                  <access>read-write</access>
20634                </field>
20635                <field>
20636                  <name>CC1_MATCH</name>
20637                  <description>Mask bit for corresponding bit in interrupt request register.</description>
20638                  <bitRange>[2:2]</bitRange>
20639                  <access>read-write</access>
20640                </field>
20641              </fields>
20642            </register>
20643            <register>
20644              <name>INTR_MASKED</name>
20645              <description>Interrupt masked request register</description>
20646              <addressOffset>0x7C</addressOffset>
20647              <size>32</size>
20648              <access>read-only</access>
20649              <resetValue>0x0</resetValue>
20650              <resetMask>0x7</resetMask>
20651              <fields>
20652                <field>
20653                  <name>TC</name>
20654                  <description>Logical and of corresponding request and mask bits.</description>
20655                  <bitRange>[0:0]</bitRange>
20656                  <access>read-only</access>
20657                </field>
20658                <field>
20659                  <name>CC0_MATCH</name>
20660                  <description>Logical and of corresponding request and mask bits.</description>
20661                  <bitRange>[1:1]</bitRange>
20662                  <access>read-only</access>
20663                </field>
20664                <field>
20665                  <name>CC1_MATCH</name>
20666                  <description>Logical and of corresponding request and mask bits.</description>
20667                  <bitRange>[2:2]</bitRange>
20668                  <access>read-only</access>
20669                </field>
20670              </fields>
20671            </register>
20672          </cluster>
20673        </cluster>
20674      </registers>
20675    </peripheral>
20676    <peripheral>
20677      <name>EVTGEN0</name>
20678      <description>Event generator</description>
20679      <headerStructName>EVTGEN</headerStructName>
20680      <baseAddress>0x403F0000</baseAddress>
20681      <addressBlock>
20682        <offset>0</offset>
20683        <size>4096</size>
20684        <usage>registers</usage>
20685      </addressBlock>
20686      <registers>
20687        <register>
20688          <name>CTL</name>
20689          <description>Control</description>
20690          <addressOffset>0x0</addressOffset>
20691          <size>32</size>
20692          <access>read-write</access>
20693          <resetValue>0x0</resetValue>
20694          <resetMask>0x80000000</resetMask>
20695          <fields>
20696            <field>
20697              <name>ENABLED</name>
20698              <description>IP enable:
20699'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled.
20700'1': Enabled.</description>
20701              <bitRange>[31:31]</bitRange>
20702              <access>read-write</access>
20703              <enumeratedValues>
20704                <enumeratedValue>
20705                  <name>DISABLED</name>
20706                  <description>N/A</description>
20707                  <value>0</value>
20708                </enumeratedValue>
20709                <enumeratedValue>
20710                  <name>ENABLED</name>
20711                  <description>N/A</description>
20712                  <value>1</value>
20713                </enumeratedValue>
20714              </enumeratedValues>
20715            </field>
20716          </fields>
20717        </register>
20718        <register>
20719          <name>COMP0_STATUS</name>
20720          <description>Comparator structures comparator 0 status</description>
20721          <addressOffset>0x4</addressOffset>
20722          <size>32</size>
20723          <access>read-only</access>
20724          <resetValue>0x0</resetValue>
20725          <resetMask>0xFFFF</resetMask>
20726          <fields>
20727            <field>
20728              <name>COMP0_OUT</name>
20729              <description>Active comparator 'comp0_out[]' outputs.</description>
20730              <bitRange>[15:0]</bitRange>
20731              <access>read-only</access>
20732            </field>
20733          </fields>
20734        </register>
20735        <register>
20736          <name>COMP1_STATUS</name>
20737          <description>Comparator structures comparator 1 status</description>
20738          <addressOffset>0x8</addressOffset>
20739          <size>32</size>
20740          <access>read-only</access>
20741          <resetValue>0x0</resetValue>
20742          <resetMask>0xFFFF</resetMask>
20743          <fields>
20744            <field>
20745              <name>COMP1_OUT</name>
20746              <description>DeepSleep comparator 'comp1_out_lf[]' outputs (synchronized from clk_lf to the IP clock).</description>
20747              <bitRange>[15:0]</bitRange>
20748              <access>read-only</access>
20749            </field>
20750          </fields>
20751        </register>
20752        <register>
20753          <name>COUNTER_STATUS</name>
20754          <description>Counter status</description>
20755          <addressOffset>0x10</addressOffset>
20756          <size>32</size>
20757          <access>read-only</access>
20758          <resetValue>0x0</resetValue>
20759          <resetMask>0x80000000</resetMask>
20760          <fields>
20761            <field>
20762              <name>VALID</name>
20763              <description>Active counter validity:
20764'0': Invalid.
20765'1': Valid.
20766
20767The COUNTER register field INT32 is only valid when VALID is '1'.
20768
20769The COUNTER_STATUS and COUNTER registers are non-retention registers; i.e. the COUNTER_STATUS and COUNTER registers are reset during DeepSleep power mode. After entering the Active power mode, the Active counter is initialized with the DeepSleep counter. This initialization may take up to 1 clk_lf cycle.</description>
20770              <bitRange>[31:31]</bitRange>
20771              <access>read-only</access>
20772            </field>
20773          </fields>
20774        </register>
20775        <register>
20776          <name>COUNTER</name>
20777          <description>Counter</description>
20778          <addressOffset>0x14</addressOffset>
20779          <size>32</size>
20780          <access>read-only</access>
20781          <resetValue>0x0</resetValue>
20782          <resetMask>0x0</resetMask>
20783          <fields>
20784            <field>
20785              <name>INT32</name>
20786              <description>Active counter 'counter_int[31:0]' on clk_ref_div.</description>
20787              <bitRange>[31:0]</bitRange>
20788              <access>read-only</access>
20789            </field>
20790          </fields>
20791        </register>
20792        <register>
20793          <name>RATIO_CTL</name>
20794          <description>Ratio control</description>
20795          <addressOffset>0x20</addressOffset>
20796          <size>32</size>
20797          <access>read-write</access>
20798          <resetValue>0x0</resetValue>
20799          <resetMask>0xC0070000</resetMask>
20800          <fields>
20801            <field>
20802              <name>DYNAMIC_MODE</name>
20803              <description>Weighted average calculation (only used when DYNAMIC is '1'):
20804'0': new RATIO value = (RATIO + measurement + 1) / 2.
20805'1': new RATIO value = (3*RATIO + measurement + 2) / 4.
20806'2': new RATIO value = (7*RATIO + measurement + 4) / 8.
20807'3': new RATIO value = (15*RATIO + measurement + 8) / 16.
20808'4': new RATIO value = (31*RATIO + measurement + 16) / 32.
20809'5': new RATIO value = (63*RATIO + measurement + 32) / 64.
20810'6': new RATIO value = (127*RATIO + measurement + 64) / 128.
20811'7': new RATIO value = (255*RATIO + measurement + 128) / 256.
20812
20813Note: 'measurement' (integer component only) is defined as: 256 * 'number of measured clk_ref_div cycles per clk_lf cycle'. The RATIO value (integer and fractional component) is defined as: 256*RATIO.INT16 + RATIO.FRAC8 (RATIO.INT16 = RATIO &gt;&gt; 8 and RATIO.FRAC8 = RATIO  percent 256).</description>
20814              <bitRange>[18:16]</bitRange>
20815              <access>read-write</access>
20816            </field>
20817            <field>
20818              <name>DYNAMIC</name>
20819              <description>Specifies if RATIO_CTL.VALID and RATIO are under SW or HW control:
20820'0': SW control.
20821'1: HW control. Auto calibration is used to derive the RATIO value. HW measures the number of clk_ref_div cycles per clk_lf cycle. This measurement is combined with the current ratio value to calculate a new ratio value.</description>
20822              <bitRange>[30:30]</bitRange>
20823              <access>read-write</access>
20824            </field>
20825            <field>
20826              <name>VALID</name>
20827              <description>Ratio value valid:
20828'0': Invalid.
20829'1': Valid.
20830
20831The RATIO register fields INT16 and FRAC8 are only valid when VALID is '1'.</description>
20832              <bitRange>[31:31]</bitRange>
20833              <access>read-write</access>
20834            </field>
20835          </fields>
20836        </register>
20837        <register>
20838          <name>RATIO</name>
20839          <description>Ratio</description>
20840          <addressOffset>0x24</addressOffset>
20841          <size>32</size>
20842          <access>read-write</access>
20843          <resetValue>0x0</resetValue>
20844          <resetMask>0x0</resetMask>
20845          <fields>
20846            <field>
20847              <name>FRAC8</name>
20848              <description>Fractional component of ratio value.</description>
20849              <bitRange>[15:8]</bitRange>
20850              <access>read-write</access>
20851            </field>
20852            <field>
20853              <name>INT16</name>
20854              <description>Integer component of ratio value.</description>
20855              <bitRange>[31:16]</bitRange>
20856              <access>read-write</access>
20857            </field>
20858          </fields>
20859        </register>
20860        <register>
20861          <name>REF_CLOCK_CTL</name>
20862          <description>Reference clock control</description>
20863          <addressOffset>0x30</addressOffset>
20864          <size>32</size>
20865          <access>read-write</access>
20866          <resetValue>0x0</resetValue>
20867          <resetMask>0xFF</resetMask>
20868          <fields>
20869            <field>
20870              <name>INT_DIV</name>
20871              <description>Divider control for clk_ref_div:
20872'0': Divide by 1.
20873...
20874'255': Divide by '256'.
20875
20876Fclk_ref_div = Fclk_ref / (INT_DIV + 1)</description>
20877              <bitRange>[7:0]</bitRange>
20878              <access>read-write</access>
20879            </field>
20880          </fields>
20881        </register>
20882        <register>
20883          <name>INTR</name>
20884          <description>Interrupt</description>
20885          <addressOffset>0x700</addressOffset>
20886          <size>32</size>
20887          <access>read-write</access>
20888          <resetValue>0x0</resetValue>
20889          <resetMask>0xFFFF</resetMask>
20890          <fields>
20891            <field>
20892              <name>COMP0</name>
20893              <description>This interrupt cause field is activated (HW sets the field to '1') when a comparator 0 event is generated (Active counter 'counter_int[31:0]' becomes greater or equal to COMP0.INT[31:0]).</description>
20894              <bitRange>[15:0]</bitRange>
20895              <access>read-write</access>
20896            </field>
20897          </fields>
20898        </register>
20899        <register>
20900          <name>INTR_SET</name>
20901          <description>Interrupt set</description>
20902          <addressOffset>0x704</addressOffset>
20903          <size>32</size>
20904          <access>read-write</access>
20905          <resetValue>0x0</resetValue>
20906          <resetMask>0xFFFF</resetMask>
20907          <fields>
20908            <field>
20909              <name>COMP0</name>
20910              <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
20911              <bitRange>[15:0]</bitRange>
20912              <access>read-write</access>
20913            </field>
20914          </fields>
20915        </register>
20916        <register>
20917          <name>INTR_MASK</name>
20918          <description>Interrupt mask</description>
20919          <addressOffset>0x708</addressOffset>
20920          <size>32</size>
20921          <access>read-write</access>
20922          <resetValue>0x0</resetValue>
20923          <resetMask>0xFFFF</resetMask>
20924          <fields>
20925            <field>
20926              <name>COMP0</name>
20927              <description>Mask bit for corresponding field in the INTR register.</description>
20928              <bitRange>[15:0]</bitRange>
20929              <access>read-write</access>
20930            </field>
20931          </fields>
20932        </register>
20933        <register>
20934          <name>INTR_MASKED</name>
20935          <description>Interrupt masked</description>
20936          <addressOffset>0x70C</addressOffset>
20937          <size>32</size>
20938          <access>read-only</access>
20939          <resetValue>0x0</resetValue>
20940          <resetMask>0xFFFF</resetMask>
20941          <fields>
20942            <field>
20943              <name>COMP0</name>
20944              <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
20945              <bitRange>[15:0]</bitRange>
20946              <access>read-only</access>
20947            </field>
20948          </fields>
20949        </register>
20950        <register>
20951          <name>INTR_DPSLP</name>
20952          <description>DeepSleep interrupt</description>
20953          <addressOffset>0x710</addressOffset>
20954          <size>32</size>
20955          <access>read-write</access>
20956          <resetValue>0x0</resetValue>
20957          <resetMask>0xFFFF</resetMask>
20958          <fields>
20959            <field>
20960              <name>COMP1</name>
20961              <description>This interrupt cause field is activated (HW sets the field to '1') when a comparator 1 event is generated (DeepSleep counter 'counter_int_lf[31:0]' becomes greater or equal to COMP1.INT[31:0]).</description>
20962              <bitRange>[15:0]</bitRange>
20963              <access>read-write</access>
20964            </field>
20965          </fields>
20966        </register>
20967        <register>
20968          <name>INTR_DPSLP_SET</name>
20969          <description>DeepSleep interrupt set</description>
20970          <addressOffset>0x714</addressOffset>
20971          <size>32</size>
20972          <access>read-write</access>
20973          <resetValue>0x0</resetValue>
20974          <resetMask>0xFFFF</resetMask>
20975          <fields>
20976            <field>
20977              <name>COMP1</name>
20978              <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
20979              <bitRange>[15:0]</bitRange>
20980              <access>read-write</access>
20981            </field>
20982          </fields>
20983        </register>
20984        <register>
20985          <name>INTR_DPSLP_MASK</name>
20986          <description>DeepSleep interrupt mask</description>
20987          <addressOffset>0x718</addressOffset>
20988          <size>32</size>
20989          <access>read-write</access>
20990          <resetValue>0x0</resetValue>
20991          <resetMask>0xFFFF</resetMask>
20992          <fields>
20993            <field>
20994              <name>COMP1</name>
20995              <description>Mask bit for corresponding field in the INTR register.</description>
20996              <bitRange>[15:0]</bitRange>
20997              <access>read-write</access>
20998            </field>
20999          </fields>
21000        </register>
21001        <register>
21002          <name>INTR_DPSLP_MASKED</name>
21003          <description>DeepSleep interrupt masked</description>
21004          <addressOffset>0x71C</addressOffset>
21005          <size>32</size>
21006          <access>read-only</access>
21007          <resetValue>0x0</resetValue>
21008          <resetMask>0xFFFF</resetMask>
21009          <fields>
21010            <field>
21011              <name>COMP1</name>
21012              <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
21013              <bitRange>[15:0]</bitRange>
21014              <access>read-only</access>
21015            </field>
21016          </fields>
21017        </register>
21018        <cluster>
21019          <dim>11</dim>
21020          <dimIncrement>32</dimIncrement>
21021          <name>COMP_STRUCT[%s]</name>
21022          <description>Comparator structure</description>
21023          <addressOffset>0x00000800</addressOffset>
21024          <register>
21025            <name>COMP_CTL</name>
21026            <description>Comparator control</description>
21027            <addressOffset>0x0</addressOffset>
21028            <size>32</size>
21029            <access>read-write</access>
21030            <resetValue>0x0</resetValue>
21031            <resetMask>0x80010003</resetMask>
21032            <fields>
21033              <field>
21034                <name>COMP0_EN</name>
21035                <description>Active comparator (COMP0) enable:
21036'0': Disabled. The comparator output 'comp0_out' is '0'.
21037'1': Enabled.</description>
21038                <bitRange>[0:0]</bitRange>
21039                <access>read-write</access>
21040              </field>
21041              <field>
21042                <name>COMP1_EN</name>
21043                <description>DeepSleep comparator (COMP1) enable:
21044'0': Disabled. The comparator output 'comp1_out_lf' is '0'.
21045'1': Enabled.</description>
21046                <bitRange>[1:1]</bitRange>
21047                <access>read-write</access>
21048              </field>
21049              <field>
21050                <name>TR_OUT_EDGE</name>
21051                <description>Specifies the 'tr_out' output trigger:
21052'0': The trigger is a level sensitive trigger. The Active comparator output ('comp0_out') is reflected on 'tr_out'.
21053'1': The trigger is an edge sensitive trigger. Activation of the Active comparator output (rising edge on 'comp0_out') results in a two cycle '1'/high pulse on 'tr_out'.</description>
21054                <bitRange>[16:16]</bitRange>
21055                <access>read-write</access>
21056              </field>
21057              <field>
21058                <name>ENABLED</name>
21059                <description>Comparator structure enable:
21060'0': Disabled.
21061'1': Enabled.</description>
21062                <bitRange>[31:31]</bitRange>
21063                <access>read-write</access>
21064              </field>
21065            </fields>
21066          </register>
21067          <register>
21068            <name>COMP0</name>
21069            <description>Comparator 0 (Active functionality)</description>
21070            <addressOffset>0x4</addressOffset>
21071            <size>32</size>
21072            <access>read-write</access>
21073            <resetValue>0x0</resetValue>
21074            <resetMask>0x0</resetMask>
21075            <fields>
21076              <field>
21077                <name>INT32</name>
21078                <description>This value is a 32-bit unsigned integer in the range [0, 2^32-1]. The comparator 'comp0_out' output is activated when the Active counter 'counter_int[31:0]' becomes greater or equal to COMP0.
21079
21080Note: SW must ensure that COMP_CTL.COMP_EN[0] is '0' when COMP0 is written.</description>
21081                <bitRange>[31:0]</bitRange>
21082                <access>read-write</access>
21083              </field>
21084            </fields>
21085          </register>
21086          <register>
21087            <name>COMP1</name>
21088            <description>Comparator 1 (DeepSleep functionality)</description>
21089            <addressOffset>0x8</addressOffset>
21090            <size>32</size>
21091            <access>read-write</access>
21092            <resetValue>0x0</resetValue>
21093            <resetMask>0x0</resetMask>
21094            <fields>
21095              <field>
21096                <name>INT32</name>
21097                <description>This value is a 32-bit unsigned integer in the range [0, 2^32-1]. The comparator 'comp1_out_lf' output is activated when the DeepSleep counter 'counter_int_lf[31:0]' becomes greater or equal to COMP1.
21098
21099Note: SW must ensure that COMP_CTL.COMP_EN[1] is '0' when COMP1 is written.</description>
21100                <bitRange>[31:0]</bitRange>
21101                <access>read-write</access>
21102              </field>
21103            </fields>
21104          </register>
21105        </cluster>
21106      </registers>
21107    </peripheral>
21108    <peripheral>
21109      <name>LIN0</name>
21110      <description>LIN</description>
21111      <headerStructName>LIN</headerStructName>
21112      <baseAddress>0x40500000</baseAddress>
21113      <addressBlock>
21114        <offset>0</offset>
21115        <size>65536</size>
21116        <usage>registers</usage>
21117      </addressBlock>
21118      <registers>
21119        <register>
21120          <name>ERROR_CTL</name>
21121          <description>Error control</description>
21122          <addressOffset>0x0</addressOffset>
21123          <size>32</size>
21124          <access>read-write</access>
21125          <resetValue>0x0</resetValue>
21126          <resetMask>0x80EF001F</resetMask>
21127          <fields>
21128            <field>
21129              <name>CH_IDX</name>
21130              <description>Specifies the channel index of the channel to which HW  injected channel transmitter errors applies.</description>
21131              <bitRange>[4:0]</bitRange>
21132              <access>read-write</access>
21133            </field>
21134            <field>
21135              <name>TX_SYNC_ERROR</name>
21136              <description>The synchronization field is changed from 0x55 to 0x00.
21137
21138At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR activation.</description>
21139              <bitRange>[16:16]</bitRange>
21140              <access>read-write</access>
21141            </field>
21142            <field>
21143              <name>TX_SYNC_STOP_ERROR</name>
21144              <description>The synchronization field STOP bits are inverted to '0'.
21145
21146At the receiver, this should result in INTR.RX_HEADER_SYNC_ERROR or INTR.RX_HEADER_FRAME_ERROR activation.</description>
21147              <bitRange>[17:17]</bitRange>
21148              <access>read-write</access>
21149            </field>
21150            <field>
21151              <name>TX_PARITY_ERROR</name>
21152              <description>In LIN mode, the PID parity bit P[1] is inverted from !(ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) to (ID[5] ^ ID[4] ^ ID[3] ^ ID[1]).
21153
21154At the receiver, this should result in INTR.RX_HEADER_PARITY_ERROR activation.
21155
21156In UART mode, a data field's parity bit is inverted.</description>
21157              <bitRange>[18:18]</bitRange>
21158              <access>read-write</access>
21159            </field>
21160            <field>
21161              <name>TX_PID_STOP_ERROR</name>
21162              <description>The PID field STOP bits are inverted to '0'.
21163
21164At the receiver, this should result in INTR.RX_HEADER_FRAME_ERROR activation.</description>
21165              <bitRange>[19:19]</bitRange>
21166              <access>read-write</access>
21167            </field>
21168            <field>
21169              <name>TX_DATA_STOP_ERROR</name>
21170              <description>The data field STOP bits are inverted to '0'.
21171
21172At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation.
21173
21174Note: Used in UART mode.</description>
21175              <bitRange>[21:21]</bitRange>
21176              <access>read-write</access>
21177            </field>
21178            <field>
21179              <name>TX_CHECKSUM_ERROR</name>
21180              <description>The checksum field is inverted.
21181
21182At the receiver, this should result in INTR.RX_RESPONSE_CHECKSUM_ERROR activation.</description>
21183              <bitRange>[22:22]</bitRange>
21184              <access>read-write</access>
21185            </field>
21186            <field>
21187              <name>TX_CHECKSUM_STOP_ERROR</name>
21188              <description>The checksum field STOP bits are inverted to '0'.
21189
21190At the receiver, this should result in INTR.RX_RESPONSE_FRAME_ERROR activation.</description>
21191              <bitRange>[23:23]</bitRange>
21192              <access>read-write</access>
21193            </field>
21194            <field>
21195              <name>ENABLED</name>
21196              <description>Error injection enable:
21197'0': Disabled.
21198'1': Enabled.</description>
21199              <bitRange>[31:31]</bitRange>
21200              <access>read-write</access>
21201            </field>
21202          </fields>
21203        </register>
21204        <register>
21205          <name>TEST_CTL</name>
21206          <description>Test control</description>
21207          <addressOffset>0x4</addressOffset>
21208          <size>32</size>
21209          <access>read-write</access>
21210          <resetValue>0x0</resetValue>
21211          <resetMask>0x8001001F</resetMask>
21212          <fields>
21213            <field>
21214              <name>CH_IDX</name>
21215              <description>Specifies the channel index of the channel to which test applies. The channel IO signals of channel indices CH_IDX and CH_NR-1 are connected as specified by MODE. CH_IDX should be in the range [0, CH_NR-2], as channel index CH_NR-1 is always involved in test and cannot be connected to itself. The test mode allows BOTH of the two connected channels to be tested.
21216
21217Note: this testing functionality simplifies SW development, but may also be used in the field to verify correct channel functionality.</description>
21218              <bitRange>[4:0]</bitRange>
21219              <access>read-write</access>
21220            </field>
21221            <field>
21222              <name>MODE</name>
21223              <description>Test mode:
21224'0': Partial disconnect from IOSS. This mode's isolation allows for device test without relying on an external LIN transceiver. The IOSS 'tx' IO cell can be used to observe messages outside of the device.
21225- tx_in[CH_IDX] = IOSS lin_tx_in[CH_IDX].
21226- tx_in[CH_NR-1] = IOSS lin_tx_in[CH_IDX].
21227- rx_in[CH_IDX] = IOSS lin_tx_in[CH_IDX].
21228- rx_in[CH_NR-1] = IOSS lin_tx_in[CH_IDX].
21229- lin_tx_out[CH_IDX] = tx_out[CH_IDX] &amp; tx_out[CH_NR-1].
21230- lin_tx_out[CH_NR-1] = tx_out[CH_IDX] &amp; tx_out[CH_NR-1].
21231
21232'1': Full disconnect from IOSS (the IOSS/HSIOM should disconnect 'tx_out' from the 'tx' IO cell). This mode's isolation allows for device test without effecting an operational LIN cluster.
21233- tx_in[CH_IDX] = lin_tx_out[CH_IDX].
21234- tx_in[CH_NR-1] = lin_tx_out[CH_IDX].
21235- rx_in[CH_IDX] = lin_tx_out[CH_IDX].
21236- rx_in[CH_NR-1] = lin_tx_out[CH_IDX].
21237- lin_tx_out[CH_IDX] = tx_out[CH_IDX] &amp; tx_out[CH_NR-1].
21238- lin_tx_out[CH_NR-1] = tx_out[CH_IDX] &amp; tx_out[CH_NR-1].</description>
21239              <bitRange>[16:16]</bitRange>
21240              <access>read-write</access>
21241            </field>
21242            <field>
21243              <name>ENABLED</name>
21244              <description>Test enable:
21245'0': Disabled. Functional mode.
21246- tx_in[CH_IDX] = IOSS lin_tx_in[CH_IDX].
21247- tx_in[CH_NR-1] = IOSS lin_tx_in[CH_NR-1].
21248- rx_in[CH_IDX] = IOSS lin_rx_in[CH_IDX].
21249- rx_in[CH_NR-1] = IOSS lin_rx_in[CH_NR-1].
21250- lin_tx_out[CH_IDX] = tx_out[CH_IDX].
21251- lin_tx_out[CH_NR-1] = tx_out[CH_NR-1].
21252'1': Enabled. Test mode, specific test mode is specified by MODE.</description>
21253              <bitRange>[31:31]</bitRange>
21254              <access>read-write</access>
21255            </field>
21256          </fields>
21257        </register>
21258        <cluster>
21259          <dim>8</dim>
21260          <dimIncrement>256</dimIncrement>
21261          <name>CH[%s]</name>
21262          <description>LIN channel structure</description>
21263          <addressOffset>0x00008000</addressOffset>
21264          <register>
21265            <name>CTL0</name>
21266            <description>Control 0</description>
21267            <addressOffset>0x0</addressOffset>
21268            <size>32</size>
21269            <access>read-write</access>
21270            <resetValue>0x400C0101</resetValue>
21271            <resetMask>0xF91F0313</resetMask>
21272            <fields>
21273              <field>
21274                <name>STOP_BITS</name>
21275                <description>STOP bit periods:
21276'0': 1/2 bit period.
21277'1': 1 bit period.
21278'2': 1 1/2 bit period.
21279'3': 2 bit periods.
21280
21281
21282In LIN mode, this field should be set to '1' (the default value) .
21283
21284In UART mode, this field can be programmed as desired.
21285
21286Note: receiver STOP bit frame errors can only be detected if the number of STOP bit periods is 1 or more bit period.</description>
21287                <bitRange>[1:0]</bitRange>
21288                <access>read-write</access>
21289              </field>
21290              <field>
21291                <name>AUTO_EN</name>
21292                <description>LIN transceiver auto enable:
21293'0': Disabled.
21294'1': Enabled. The TX_RX_STATUS.EN_OUT field is controlled by HW.</description>
21295                <bitRange>[4:4]</bitRange>
21296                <access>read-write</access>
21297              </field>
21298              <field>
21299                <name>BREAK_DELIMITER_LENGTH</name>
21300                <description>In LIN mode, this field specifies the break delimiter length:
21301(used in header transmission, not used in header reception).
21302'0': 1 bit period.
21303'1': 2 bit periods (default value).
21304'2': 3 bit periods.
21305'3': 4 bit periods.
21306
21307In UART mode, this field specifies the data field size:
21308'0': 5 bit data field.
21309'1': 6 bit data field.
21310'2': 7 bit data field.
21311'3': 8 bit data field.
21312When the data field size is less than 8 bits, the most significant (unused) bits of the DATAx.DATAy[7:0] fields should be set to '0' for the transmitter.</description>
21313                <bitRange>[9:8]</bitRange>
21314                <access>read-write</access>
21315              </field>
21316              <field>
21317                <name>BREAK_WAKEUP_LENGTH</name>
21318                <description>Break/wakeup length (minus 1) in bit periods:
21319'0': 1 bit period.
21320...
21321'10': 11 bit periods (break length for slave nodes)
21322...
21323'12': 13 bit periods (break length for master nodes)
21324...
21325'30': 31 bit periods.
21326'31': Illegal (should NOT be used!!!)
21327
21328This field is used for transmission/reception of BOTH break and wakeup signals. Note that these functions are mutually exclusive:
21329- When CMD.TX_HEADER is '1', the field specifies the transmitted break field.
21330- When CMD.TX_WAKEUP is '1', the field specifies the transmitted wakeup field.
21331- When CMD.RX_HEADER is '1', the field specifies the to be received break field.
21332- Otherwise, the field specifies the to be received wakeup field.
21333
21334Per the standard, the master wakeup duration is between 250 us and 5 ms. To support uncalibrated slaves, a slave has a detection threshold of 150 us (3 bit periods at 20 kbps). After transmission of a break or wakeup signal, the INTR.TX_BREAK_WAKEUP_DONE interrupt cause is activated. After reception of a wakeup signal, the INTR.RX_BREAK_WAKEUP_DONE interrupt cause is activated.
21335
21336To specify longer wakeup signals in terms of absolute time (us/ms rather than bit periods), the associated PERI clock divider value can be (temporarily) increased to make the LIN bit period longer.
21337
21338Note: entering bus sleep mode is achieved with the 'go-to-sleep' command.</description>
21339                <bitRange>[20:16]</bitRange>
21340                <access>read-write</access>
21341              </field>
21342              <field>
21343                <name>MODE</name>
21344                <description>Mode of operation:
21345'0': LIN mode.
21346'1': UART mode.</description>
21347                <bitRange>[24:24]</bitRange>
21348                <access>read-write</access>
21349                <enumeratedValues>
21350                  <enumeratedValue>
21351                    <name>LIN</name>
21352                    <description>LIN mode.</description>
21353                    <value>0</value>
21354                  </enumeratedValue>
21355                  <enumeratedValue>
21356                    <name>UART</name>
21357                    <description>UART mode.</description>
21358                    <value>1</value>
21359                  </enumeratedValue>
21360                </enumeratedValues>
21361              </field>
21362              <field>
21363                <name>BIT_ERROR_IGNORE</name>
21364                <description>Specifies behavior on a detected bit error during header or response transmission:
21365'0': Message transfer is aborted.
21366'1': Message transfer is NOT aborted.
21367
21368Note: this field does NOT effect the reporting of the bit error through INTR/STATUS.TX_HEADER/RESPONSE_BIT_ERROR; i.e. bit errors are always reported.</description>
21369                <bitRange>[27:27]</bitRange>
21370                <access>read-write</access>
21371              </field>
21372              <field>
21373                <name>PARITY</name>
21374                <description>Parity mode:
21375'0': Even parity: even number of '1' bits (including parity).
21376'1': Odd parity.
21377
21378Note: Used in UART mode only.</description>
21379                <bitRange>[28:28]</bitRange>
21380                <access>read-write</access>
21381              </field>
21382              <field>
21383                <name>PARITY_EN</name>
21384                <description>Parity generation enable:
21385'0': Disabled. No parity bit is transferred.
21386'1': Enabled. The parity bit is transferred after the last (most significant) data field bit.
21387
21388Note: Used in UART mode only.</description>
21389                <bitRange>[29:29]</bitRange>
21390                <access>read-write</access>
21391              </field>
21392              <field>
21393                <name>FILTER_EN</name>
21394                <description>RX filter (for 'lin_rx_in'):
21395'0': No filter.
21396'1': Median 3 (default value) operates on the last three 'lin_rx_in' values. The sequences '000', '001', '010' and '100' result in a filtered value '0'. The sequences '111', '110', '101' and '011' result in a filtered value '1'.</description>
21397                <bitRange>[30:30]</bitRange>
21398                <access>read-write</access>
21399              </field>
21400              <field>
21401                <name>ENABLED</name>
21402                <description>Channel enable:
21403'0': Disabled. If a channel is disabled, all non-retained MMIO registers (e.g. the TX_RX_STATUS, and INTR registers) have their fields reset to their default value.
21404'1': Enabled.</description>
21405                <bitRange>[31:31]</bitRange>
21406                <access>read-write</access>
21407              </field>
21408            </fields>
21409          </register>
21410          <register>
21411            <name>CTL1</name>
21412            <description>Control 1</description>
21413            <addressOffset>0x4</addressOffset>
21414            <size>32</size>
21415            <access>read-write</access>
21416            <resetValue>0x0</resetValue>
21417            <resetMask>0x3000000</resetMask>
21418            <fields>
21419              <field>
21420                <name>DATA_NR</name>
21421                <description>Number of data fields (minus 1) in the response (not including the checksum):
21422'0': 1 data field.
21423'1': 2 data fields.
21424...
21425'7': 8 data fields.
21426
21427Note: master and slave nodes need to agree upon the number of data fields before message transfer.
21428In RX_RESPONSE case, When PID (header) is received, firmware has the time of one response data byte, to modify CTL1.DATA_NR.</description>
21429                <bitRange>[2:0]</bitRange>
21430                <access>read-write</access>
21431              </field>
21432              <field>
21433                <name>CHECKSUM_ENHANCED</name>
21434                <description>Checksum mode:
21435'0': Classic mode. PID field is NOT included in the checksum calculation.
21436'1': Enhanced mode. PID field is included in the checksum calculation. This mode requires special attention when the master node transmits the header and a (different) slave node transmits the response: the slave node will use the calculated partial checksum over the received PID field as a starting point for the calculation over the to be transmitted data fields.
21437
21438Note: If the frame identifier ID[5:0] is 0x3c or 0x3d, the classic mode will ALWAYS be used for transmission and assumed for reception, independent of the CHECKSUM_ENHANCED value.</description>
21439                <bitRange>[8:8]</bitRange>
21440                <access>read-write</access>
21441              </field>
21442              <field>
21443                <name>FRAME_TIMEOUT</name>
21444                <description>Specifies the maximum allowed length (timeout value) for a frame, frame header or frame response in bit periods. The LIN specification prescribes to set the maximum length to 1.4x the nominal length (Theader_max = 1.4 x Theader_nom and Tresponse_max = 1.4 x Tresponse_nom). The nominal header length Theader_nom is 34 bit periods and the nominal response length Tresponse_nom is 10 * (data_nr + 1) bit periods (data_nr is the number of data fields)
21445
21446Note: the LIN specification specifies the following: 'Tools and tests shall check the Tframe_max (= Theader_max + Tresponse_max). Nodes shall not check this time. The receiving node of the frame shall accept the frame up to the next frame slot (i.e. next break field), even if it is longer then Tframe_max).'</description>
21447                <bitRange>[23:16]</bitRange>
21448                <access>read-write</access>
21449              </field>
21450              <field>
21451                <name>FRAME_TIMEOUT_SEL</name>
21452                <description>Specifies the frame timeout mode:
21453'0': No timeout functionality (default value).
21454'1': Frame mode: detects timeout from the start of break field to checksum field STOP bits (inclusive). The minimum FRAME_TIMEOUT value is 34+20 bit periods (header and a response with 1 data field).
21455'2': Frame header mode: detects timeout from the start of break field to PID field STOP bits (inclusive). The minimum FRAME_TIMEOUT value is 34 bit periods (header).
21456'3': Frame response mode: detects timeout from the PID field STOP bits (exclusive) to checksum field STOP bits (the response space is included in the frame response). The minimum FRAME_TIMEOUT value is 20 bit periods (response with 1 data field).</description>
21457                <bitRange>[25:24]</bitRange>
21458                <access>read-write</access>
21459              </field>
21460            </fields>
21461          </register>
21462          <register>
21463            <name>STATUS</name>
21464            <description>Status</description>
21465            <addressOffset>0x8</addressOffset>
21466            <size>32</size>
21467            <access>read-only</access>
21468            <resetValue>0x0</resetValue>
21469            <resetMask>0x1F03333F</resetMask>
21470            <fields>
21471              <field>
21472                <name>DATA_IDX</name>
21473                <description>Number of transferred data and checksum fields in the response (also acts as an index/address into response data field and checksum field registers (DATA0, DATA1, PID_CHECKSUM)) :
21474'0': No data fields transferred.
21475'1': Data field 1 transferred.
21476...
21477'7': Data fields 1, 2, 3, ... and 7 transferred.
21478'8':  Data fields 1, 2, 3, ... and 8 transferred.
21479'9': Data fields 1, 2, 3, ..., 8 and checksum field transferred.
21480'10'-'15': Unused.
21481
21482Set to '0' on the start of a TX_HEADER or RX_HEADER command.</description>
21483                <bitRange>[3:0]</bitRange>
21484                <access>read-only</access>
21485              </field>
21486              <field>
21487                <name>HEADER_RESPONSE</name>
21488                <description>Frame header / response identifier (only valid when TX_BUSY or RX_BUSY is '1'):
21489'0': Frame header being transferred.
21490'1': Frame response being transferred.</description>
21491                <bitRange>[4:4]</bitRange>
21492                <access>read-only</access>
21493              </field>
21494              <field>
21495                <name>RX_DATA0_FRAME_ERROR</name>
21496                <description>Frame response, first data field frame error. HW sets this field to '1'  when the received STOP bits of the first response data field have an unexpected value (only after a RX_HEADER command), and this data byte is 0x00. HW clears this field to '0' at the falling edge of SYNC start bit (after INTR.RX_HEADER_BREAK_WAKEUP_DONE). This field is used together with INTR.RX_RESPONSE_FRAME_ERROR to distinguish 'no response', 'error response' and 'correct response' scenarios.
21497
21498Note: The ongoing message transfer is NOT aborted.</description>
21499                <bitRange>[5:5]</bitRange>
21500                <access>read-only</access>
21501              </field>
21502              <field>
21503                <name>TX_BUSY</name>
21504                <description>Transmitter busy.
21505- Set to '1' on the start of the following commands: TX_HEADER, TX_RESPONSE, TX_WAKEUP.
21506- Set to '0' on successful completion of previous commands or when an error is detected.
21507   In 'TX_HEADER, RX_RESPONSE' case, set to '0' at the start bit falling edge in the first response data byte, after header transmission</description>
21508                <bitRange>[8:8]</bitRange>
21509                <access>read-only</access>
21510              </field>
21511              <field>
21512                <name>RX_BUSY</name>
21513                <description>Receiver busy.
21514- Set to '1' on the start of the following commands: RX_HEADER, RX_RESPONSE.
21515   in RX_HEADER case, set at Break filed rising edge.
21516   in RX_RESPONSE case, set at the start bit falling edge in the first response data byte.
21517
21518- Set to '0' on successful completion of previous commands or when an error is detected.</description>
21519                <bitRange>[9:9]</bitRange>
21520                <access>read-only</access>
21521              </field>
21522              <field>
21523                <name>TX_DONE</name>
21524                <description>Transmitter done:
21525- Set to '0' on the start of a new command.
21526- Set to '1' on successful completion of the following command sequences (if CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble):
21527- TX_HEADER.
21528- TX_HEADER, TX_RESPONSE.
21529- RX_HEADER, TX_RESPONSE.
21530- TX_WAKEUP.</description>
21531                <bitRange>[12:12]</bitRange>
21532                <access>read-only</access>
21533              </field>
21534              <field>
21535                <name>RX_DONE</name>
21536                <description>Receiver done:
21537- Set to '0' on the start of a new command.
21538- Set to '1' on successful completion of the following command sequences (if CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble):
21539- RX_HEADER, RX_RESPONSE.
21540- TX_HEADER, RX_RESPONSE.</description>
21541                <bitRange>[13:13]</bitRange>
21542                <access>read-only</access>
21543              </field>
21544              <field>
21545                <name>TX_HEADER_BIT_ERROR</name>
21546                <description>Copy of INTR.TX_HEADER_BIT_ERROR.</description>
21547                <bitRange>[16:16]</bitRange>
21548                <access>read-only</access>
21549              </field>
21550              <field>
21551                <name>TX_RESPONSE_BIT_ERROR</name>
21552                <description>Copy of INTR.TX_RESPONSE_BIT_ERROR.</description>
21553                <bitRange>[17:17]</bitRange>
21554                <access>read-only</access>
21555              </field>
21556              <field>
21557                <name>RX_HEADER_FRAME_ERROR</name>
21558                <description>Copy of INTR.RX_HEADER_FRAME_ERROR.</description>
21559                <bitRange>[24:24]</bitRange>
21560                <access>read-only</access>
21561              </field>
21562              <field>
21563                <name>RX_HEADER_SYNC_ERROR</name>
21564                <description>Copy of INTR.RX_HEADER_SYNC_ERROR.</description>
21565                <bitRange>[25:25]</bitRange>
21566                <access>read-only</access>
21567              </field>
21568              <field>
21569                <name>RX_HEADER_PARITY_ERROR</name>
21570                <description>Copy of INTR.RX_HEADER_PARITY_ERROR.</description>
21571                <bitRange>[26:26]</bitRange>
21572                <access>read-only</access>
21573              </field>
21574              <field>
21575                <name>RX_RESPONSE_FRAME_ERROR</name>
21576                <description>Copy of INTR.RX_RESPONSE_FRAME_ERROR.</description>
21577                <bitRange>[27:27]</bitRange>
21578                <access>read-only</access>
21579              </field>
21580              <field>
21581                <name>RX_RESPONSE_CHECKSUM_ERROR</name>
21582                <description>Copy of INTR.RX_RESPONSE_CHECKSUM_ERROR.</description>
21583                <bitRange>[28:28]</bitRange>
21584                <access>read-only</access>
21585              </field>
21586            </fields>
21587          </register>
21588          <register>
21589            <name>CMD</name>
21590            <description>Command</description>
21591            <addressOffset>0x10</addressOffset>
21592            <size>32</size>
21593            <access>read-write</access>
21594            <resetValue>0x0</resetValue>
21595            <resetMask>0x307</resetMask>
21596            <fields>
21597              <field>
21598                <name>TX_HEADER</name>
21599                <description>SW sets this field to '1' to transmit a header. HW sets this field to '0' on successful completion of ANY of the following legal command sequences (also set to '0' when an error is detected):
21600- TX_HEADER
21601- TX_HEADER, TX_RESPONSE.
21602- TX_HEADER, RX_RESPONSE.
21603- RX_HEADER, TX_RESPONSE.
21604- RX_HEADER, RX_RESPONSE.
21605- TX_WAKEUP.
21606
21607The header is transmitted when the PID field STOP bits are transmitted (INTR.TX_HEADER_DONE).
21608
21609HW sets this field to '1', when the 'tr_cmd_tx_header' input trigger is activated. This allows for time triggered LIN message transfer. HW driven time triggered transfer eliminates the jitter that is typically associated with SW driven transfer.
21610
21611In UART mode, a single data field (DATA0.DATA1) is transmitted.</description>
21612                <bitRange>[0:0]</bitRange>
21613                <access>read-write</access>
21614              </field>
21615              <field>
21616                <name>TX_RESPONSE</name>
21617                <description>SW sets this field to '1' to transmit a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected).
21618
21619The response is transmitted when the checksum field STOP bits are transmitted (INTR.TX_RESPONSE_DONE).</description>
21620                <bitRange>[1:1]</bitRange>
21621                <access>read-write</access>
21622              </field>
21623              <field>
21624                <name>TX_WAKEUP</name>
21625                <description>SW sets this field to '1' to transmit a wakeup signal. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected).
21626
21627The command generates CTL.BREAK_WAKEUP_LENGTH bit periods in the dominant state (low/'0') and transitions to the recessive state (high/'1') (INTR.TX_WAKEUP_DONE).</description>
21628                <bitRange>[2:2]</bitRange>
21629                <access>read-write</access>
21630              </field>
21631              <field>
21632                <name>RX_HEADER</name>
21633                <description>SW sets this field to '1' to receive a header. HW sets this field to '0' on successful completion of the ANY of the legal command sequences (NOT set to '0' when an error is detected in LIN mode).
21634
21635The header is received when the PID field STOP bits are received (INTR.RX_HEADER_DONE).
21636
21637Typically, a slave node SW sets both RX_HEADER and RX_RESPONSE to '1', anticipating a transfer of a response from the master node to this slave node. After receipt of the header PID field (INTR.RX_HEADER_PID_DONE is activated), the slave node may decide to set TX_RESPONSE to '1' (which has a higher priority than RX_RESPONSE) to transmit a response.
21638
21639the Break detection is performed regardless of CMD.RX_HEADER.
21640INTR.RX_BREAK_WAKEUP_DONE will trigger at LIN_RX rising edge, when the low pulse meet CTL0.BREAK_WAKEUP_LENGTH. when Break is detected, HW check CMD.RX_HEADER before entering SYNC byte processing state. when RX_HEADER is cleared, SW has at least 11 bit times to set RX_HEADER again, before next Break is detected (RX_BREAK_WAKEUP_DONE). in this case, there is no gap, Break will never be missed.
21641
21642
21643In UART mode, a single data field in received (in DATA0.DATA1). HW set this field to '0' when the data field is received, or when an error is detected.</description>
21644                <bitRange>[8:8]</bitRange>
21645                <access>read-write</access>
21646              </field>
21647              <field>
21648                <name>RX_RESPONSE</name>
21649                <description>SW sets this field to '1' to receive a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (NOT set to '0' when an error is detected).
21650
21651The response is received when the checksum field STOP bits are received (INTR.RX_RESPONSE_DONE).</description>
21652                <bitRange>[9:9]</bitRange>
21653                <access>read-write</access>
21654              </field>
21655            </fields>
21656          </register>
21657          <register>
21658            <name>TX_RX_STATUS</name>
21659            <description>TX/RX status</description>
21660            <addressOffset>0x60</addressOffset>
21661            <size>32</size>
21662            <access>read-write</access>
21663            <resetValue>0x5000000</resetValue>
21664            <resetMask>0x5000000</resetMask>
21665            <fields>
21666              <field>
21667                <name>SYNC_COUNTER</name>
21668                <description>Synchronization counter in LIN channel clock periods. After the receipt of a synchronization field, this fields reflects the duration of the synchronization field. Ideally, SYNC_COUNTER = 8*16 = 128 (the synchronization fields consists of eight bit period of 16 LIN channel clock periods each).
21669- If SYNC_COUNTER is less than 128, the LIN channel clock is too slow and the PERI/PCLK divider value should be decreased.
21670- If SYNC_COUNTER is greater than 128, the LIN channel clock is too fast and the PERI/PCLK divider value should be increased.
21671
21672The biggest master-slave clock discrepancy occurs when the master is slow and the slave is fast or vice versa. At a 0.5 percent master inaccuracy and a 14 percent slave inaccuracy, this results in the extreme synchronization values of (.86 * 128) / 1.005 = 109.5 and (1.14 *128) / 0.995 = 146.6. We add a little margin for a valid range of [106, 152].
21673
21674Note: Only slave nodes with imprecise clocks require clock resynchronization. Master and slave nodes with precise clocks do NOT require clock resynchronization.</description>
21675                <bitRange>[7:0]</bitRange>
21676                <access>read-only</access>
21677              </field>
21678              <field>
21679                <name>TX_IN</name>
21680                <description>LIN transmitter input ('tx_in', 'lin_tx_in' in functional mode). TX_IN and RX_IN can be used to determine a wakeup source. Note that wakeup source detection relies on the external transceiver functionality.</description>
21681                <bitRange>[16:16]</bitRange>
21682                <access>read-only</access>
21683              </field>
21684              <field>
21685                <name>RX_IN</name>
21686                <description>LIN receiver input ('rx_in', 'lin_rx_in' in functional mode).</description>
21687                <bitRange>[17:17]</bitRange>
21688                <access>read-only</access>
21689              </field>
21690              <field>
21691                <name>TX_OUT</name>
21692                <description>LIN transmitter output ('tx_out', 'lin_tx_out').</description>
21693                <bitRange>[24:24]</bitRange>
21694                <access>read-only</access>
21695              </field>
21696              <field>
21697                <name>EN_OUT</name>
21698                <description>LIN transceiver enable ('en_out', 'lin_en_out'). This field controls the enable (or low active sleep enable) of the external transceiver:
21699'0': Disabled.
21700'1': Enabled.
21701
21702If CTL.AUTO_EN is '0', SW controls this field to enable the external transceiver. If CTL.AUTO_EN is '1', HW controls this field to enable the external transceiver:
21703- Before a legal command sequence, HW sets this field to '1', if it is '0'. The start of the command sequence is effectively postponed by a 4-bit period preamble.
21704- After a legal command sequence, HW clears this field to '0'. The end of the command sequence is effectively postponed by a 4-bit period postamble.
21705
21706Note: external transceivers require a 'power up' or 'power down' period of 1 or 2 bit periods, so a 4-bit period suffices for all known transceivers.</description>
21707                <bitRange>[26:26]</bitRange>
21708                <access>read-write</access>
21709              </field>
21710            </fields>
21711          </register>
21712          <register>
21713            <name>PID_CHECKSUM</name>
21714            <description>PID and checksum</description>
21715            <addressOffset>0x80</addressOffset>
21716            <size>32</size>
21717            <access>read-write</access>
21718            <resetValue>0x0</resetValue>
21719            <resetMask>0x0</resetMask>
21720            <fields>
21721              <field>
21722                <name>PID</name>
21723                <description>Header protected identifier (PID).
21724- Bits 5 down to 0: frame identifier ID[5:0].
21725Frame identifier 0x3c is for a 'master request' frame, 0x3d is for a 'slave response' frame, 0x3e and 0x3f are for future LIN enhancements. Frame identifier ID[5:4] is optionally used for length control; i.e. specifies the number of response data fields.
21726- Bits 1 down to 0: parity bits P[1] and P[0].
21727  - P[1] = ! (ID[5] ^ ID[4] ^ ID[3] ^ ID[1])
21728  - P[0] = (ID[4] ^ ID[2] ^ ID[1] ^ ID[0])
21729
21730Transmission: To be transmitted PID field. SW needs to calculate the PID field parity bits P[1] and P[0].
21731
21732Reception: Received PID field. Slave node SW uses the PID field to determine how to handle the response for a received frame header: TX_RESPONSE or  RX_RESPONSE.</description>
21733                <bitRange>[7:0]</bitRange>
21734                <access>read-write</access>
21735              </field>
21736              <field>
21737                <name>CHECKSUM</name>
21738                <description>Checksum.
21739
21740Transmission: HW calculated checksum (SW does not need to calculate the checksum) over the transmitted PID field (optional per CTL.CHECKSUM_ENHANCED) and data fields.
21741
21742Reception: Received checksum. Note that in case of a RX_CHECKSUM_ERROR, SW can use the received PID field and the  received data fields to calculate the correct checksum value.</description>
21743                <bitRange>[15:8]</bitRange>
21744                <access>read-only</access>
21745              </field>
21746            </fields>
21747          </register>
21748          <register>
21749            <name>DATA0</name>
21750            <description>Response data 0</description>
21751            <addressOffset>0x84</addressOffset>
21752            <size>32</size>
21753            <access>read-write</access>
21754            <resetValue>0x0</resetValue>
21755            <resetMask>0x0</resetMask>
21756            <fields>
21757              <field>
21758                <name>DATA1</name>
21759                <description>Data field 1.
21760
21761Transmission: To be transmitted data field. SW provides data field.
21762
21763Reception: Received data field. SW uses the data field.</description>
21764                <bitRange>[7:0]</bitRange>
21765                <access>read-write</access>
21766              </field>
21767              <field>
21768                <name>DATA2</name>
21769                <description>Data field 2.</description>
21770                <bitRange>[15:8]</bitRange>
21771                <access>read-write</access>
21772              </field>
21773              <field>
21774                <name>DATA3</name>
21775                <description>Data field 3.</description>
21776                <bitRange>[23:16]</bitRange>
21777                <access>read-write</access>
21778              </field>
21779              <field>
21780                <name>DATA4</name>
21781                <description>Data field 4.</description>
21782                <bitRange>[31:24]</bitRange>
21783                <access>read-write</access>
21784              </field>
21785            </fields>
21786          </register>
21787          <register>
21788            <name>DATA1</name>
21789            <description>Response data 1</description>
21790            <addressOffset>0x88</addressOffset>
21791            <size>32</size>
21792            <access>read-write</access>
21793            <resetValue>0x0</resetValue>
21794            <resetMask>0x0</resetMask>
21795            <fields>
21796              <field>
21797                <name>DATA5</name>
21798                <description>Data field 5.</description>
21799                <bitRange>[7:0]</bitRange>
21800                <access>read-write</access>
21801              </field>
21802              <field>
21803                <name>DATA6</name>
21804                <description>Data field 6.</description>
21805                <bitRange>[15:8]</bitRange>
21806                <access>read-write</access>
21807              </field>
21808              <field>
21809                <name>DATA7</name>
21810                <description>Data field 7.</description>
21811                <bitRange>[23:16]</bitRange>
21812                <access>read-write</access>
21813              </field>
21814              <field>
21815                <name>DATA8</name>
21816                <description>Data field 8.</description>
21817                <bitRange>[31:24]</bitRange>
21818                <access>read-write</access>
21819              </field>
21820            </fields>
21821          </register>
21822          <register>
21823            <name>INTR</name>
21824            <description>Interrupt</description>
21825            <addressOffset>0xC0</addressOffset>
21826            <size>32</size>
21827            <access>read-write</access>
21828            <resetValue>0x0</resetValue>
21829            <resetMask>0x1F036F07</resetMask>
21830            <fields>
21831              <field>
21832                <name>TX_HEADER_DONE</name>
21833                <description>HW sets this field to '1', when a frame header (break field, synchronization field and PID field) is transmitted (the CMD.TX_HEADER is completed). Specifically:
21834- When followed by CMD.TX_RESPONSE or CMD.RX_RESPONSE, this field is set to '1' after completion of the frame header transfer.
21835- When not followed by a response command, this field is set to '1' after completion of the frame header transfer. If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble.
21836
21837Note: used in UART mode.</description>
21838                <bitRange>[0:0]</bitRange>
21839                <access>read-write</access>
21840              </field>
21841              <field>
21842                <name>TX_RESPONSE_DONE</name>
21843                <description>HW sets this field to '1', when a frame response (data fields and checksum field) is transmitted (the CMD.TX_RESPONSE is completed). If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble.</description>
21844                <bitRange>[1:1]</bitRange>
21845                <access>read-write</access>
21846              </field>
21847              <field>
21848                <name>TX_WAKEUP_DONE</name>
21849                <description>HW sets this field to '1', when a wakeup signal is transmitted (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal.</description>
21850                <bitRange>[2:2]</bitRange>
21851                <access>read-write</access>
21852              </field>
21853              <field>
21854                <name>RX_HEADER_DONE</name>
21855                <description>HW sets this field to '1', when a frame header (break field, synchronization field and PID field) is received (the CMD.RX_HEADER is completed). Specifically:
21856- When followed by CMD.TX_RESPONSE or CMD.RX_RESPONSE, this field is set to '1' after completion of the frame header transfer.
21857- When not followed by a response command, this field is set to '1' after completion of the frame header transfer. If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble.
21858
21859Note: used in UART mode.</description>
21860                <bitRange>[8:8]</bitRange>
21861                <access>read-write</access>
21862              </field>
21863              <field>
21864                <name>RX_RESPONSE_DONE</name>
21865                <description>HW sets this field to '1', when a frame response (data fields and checksum field) is received (the CMD.RX_RESPONSE is completed). If CTL.AUTO_EN is '1', this includes the 4-bit period external transceiver disable post-amble.
21866
21867Note: activation implies that RX_RESPONSE_FRAME_ERROR and RX_RESPONSE_CHECKSUM_ERROR are not activated during response reception</description>
21868                <bitRange>[9:9]</bitRange>
21869                <access>read-write</access>
21870              </field>
21871              <field>
21872                <name>RX_BREAK_WAKEUP_DONE</name>
21873                <description>HW sets this field to '1', when a break or wakeup signal is received (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal.
21874
21875The break or wakeup detection is always enabled, regardless of CMD register setting.</description>
21876                <bitRange>[10:10]</bitRange>
21877                <access>read-write</access>
21878              </field>
21879              <field>
21880                <name>RX_HEADER_SYNC_DONE</name>
21881                <description>HW sets this field to '1', when a synchronization field is received (including trailing STOP bits).</description>
21882                <bitRange>[11:11]</bitRange>
21883                <access>read-write</access>
21884              </field>
21885              <field>
21886                <name>RX_NOISE_DETECT</name>
21887                <description>HW sets this field to '1', when isolated '0' or '1' 'in_rx_in' values are observed or when during sampling the last three 'lin_rx_in' values do NOT all have the same value. This mismatch is an indication of noise on the LIN line.
21888
21889Note: The ongoing frame transfer is NOT aborted.
21890
21891Note: Used in UART mode.</description>
21892                <bitRange>[13:13]</bitRange>
21893                <access>read-write</access>
21894              </field>
21895              <field>
21896                <name>TIMEOUT</name>
21897                <description>HW sets this field to '1', when a frame, frame header or frame response timeout is detected (per CTL.FRAME_TIMEOUT_SEL).
21898
21899Note: The ongoing frame transfer is NOT aborted.</description>
21900                <bitRange>[14:14]</bitRange>
21901                <access>read-write</access>
21902              </field>
21903              <field>
21904                <name>TX_HEADER_BIT_ERROR</name>
21905                <description>HW sets this field to '1', when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during header transmission). This specific test allows for delay through the external transceiver. This mismatch is an indication of bus collisions on the LIN line.
21906
21907The match is performed for the Wakeup, Break, SYNC and the PID fields (for the START bit, data Byte and STOP bit).
21908
21909Note: When CTL.BIT_ERROR_IGNORE is '0', the ongoing message transfer is aborted (INTR.TX_HEADER_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'.
21910
21911Note: Used in UART mode.</description>
21912                <bitRange>[16:16]</bitRange>
21913                <access>read-write</access>
21914              </field>
21915              <field>
21916                <name>TX_RESPONSE_BIT_ERROR</name>
21917                <description>HW sets this field to '1', when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during response transmission).
21918
21919The match is performed for the data fields and the checksum field (for the START bit, data Byte and STOP bit).
21920
21921Note: When CTL.BIT_ERROR_IGNORE is '0', the ongoing message transfer is aborted (INTR.TX_RESPONSE_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'.</description>
21922                <bitRange>[17:17]</bitRange>
21923                <access>read-write</access>
21924              </field>
21925              <field>
21926                <name>RX_HEADER_FRAME_ERROR</name>
21927                <description>HW sets this field to '1', when the received START or STOP bits have an unexpected value (during header reception).
21928
21929Note: The ongoing message transfer is aborted (INTR.RX_HEADER_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'.
21930
21931Note: Used in UART mode.</description>
21932                <bitRange>[24:24]</bitRange>
21933                <access>read-write</access>
21934              </field>
21935              <field>
21936                <name>RX_HEADER_SYNC_ERROR</name>
21937                <description>HW sets this field to '1', when the received synchronization field is not received within the synchronization counter range [106, 152] (see TX_RX_STATUS.SYNC_COUNTER).
21938
21939Note: The ongoing message transfer is aborted (INTR.RX_HEADER_SYNC_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'.</description>
21940                <bitRange>[25:25]</bitRange>
21941                <access>read-write</access>
21942              </field>
21943              <field>
21944                <name>RX_HEADER_PARITY_ERROR</name>
21945                <description>HW sets this field to '1', when the received PID field has a parity error.
21946
21947Note: The ongoing message transfer is aborted (INTR.RX_PID_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'.
21948
21949+G119 HW sets this field to '1', when the received data field has a parity error (when CTL0.PARITY_EN is '1').</description>
21950                <bitRange>[26:26]</bitRange>
21951                <access>read-write</access>
21952              </field>
21953              <field>
21954                <name>RX_RESPONSE_FRAME_ERROR</name>
21955                <description>HW sets this field to '1', when the received START or STOP bits have an unexpected value (during response reception). HW does NOT use this field for the STOP bits of the first data field after a RX_HEADER command, if the received data byte is 0x00. (STATUS.RX_DATA0_FRAME_ERROR is used instead).
21956
21957Note: The ongoing message transfer is aborted (INTR.RX_RESPONSE_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'.</description>
21958                <bitRange>[27:27]</bitRange>
21959                <access>read-write</access>
21960              </field>
21961              <field>
21962                <name>RX_RESPONSE_CHECKSUM_ERROR</name>
21963                <description>HW sets this field to '1', when the calculated checksum over the received PID and data fields is not the same as the received checksum.
21964
21965Note: The ongoing message transfer is aborted (INTR.RX_RESPONSE_DONE is NOT activated) and the TX_HEADER, TX_RESPONSE and TX_WAKEUP commands are set to '0'.</description>
21966                <bitRange>[28:28]</bitRange>
21967                <access>read-write</access>
21968              </field>
21969            </fields>
21970          </register>
21971          <register>
21972            <name>INTR_SET</name>
21973            <description>Interrupt set</description>
21974            <addressOffset>0xC4</addressOffset>
21975            <size>32</size>
21976            <access>read-write</access>
21977            <resetValue>0x0</resetValue>
21978            <resetMask>0x1F036F07</resetMask>
21979            <fields>
21980              <field>
21981                <name>TX_HEADER_DONE</name>
21982                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
21983                <bitRange>[0:0]</bitRange>
21984                <access>read-write</access>
21985              </field>
21986              <field>
21987                <name>TX_RESPONSE_DONE</name>
21988                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
21989                <bitRange>[1:1]</bitRange>
21990                <access>read-write</access>
21991              </field>
21992              <field>
21993                <name>TX_WAKEUP_DONE</name>
21994                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
21995                <bitRange>[2:2]</bitRange>
21996                <access>read-write</access>
21997              </field>
21998              <field>
21999                <name>RX_HEADER_DONE</name>
22000                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
22001                <bitRange>[8:8]</bitRange>
22002                <access>read-write</access>
22003              </field>
22004              <field>
22005                <name>RX_RESPONSE_DONE</name>
22006                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
22007                <bitRange>[9:9]</bitRange>
22008                <access>read-write</access>
22009              </field>
22010              <field>
22011                <name>RX_BREAK_WAKEUP_DONE</name>
22012                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
22013                <bitRange>[10:10]</bitRange>
22014                <access>read-write</access>
22015              </field>
22016              <field>
22017                <name>RX_HEADER_SYNC_DONE</name>
22018                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
22019                <bitRange>[11:11]</bitRange>
22020                <access>read-write</access>
22021              </field>
22022              <field>
22023                <name>RX_NOISE_DETECT</name>
22024                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
22025                <bitRange>[13:13]</bitRange>
22026                <access>read-write</access>
22027              </field>
22028              <field>
22029                <name>TIMEOUT</name>
22030                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
22031                <bitRange>[14:14]</bitRange>
22032                <access>read-write</access>
22033              </field>
22034              <field>
22035                <name>TX_HEADER_BIT_ERROR</name>
22036                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
22037                <bitRange>[16:16]</bitRange>
22038                <access>read-write</access>
22039              </field>
22040              <field>
22041                <name>TX_RESPONSE_BIT_ERROR</name>
22042                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
22043                <bitRange>[17:17]</bitRange>
22044                <access>read-write</access>
22045              </field>
22046              <field>
22047                <name>RX_HEADER_FRAME_ERROR</name>
22048                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
22049                <bitRange>[24:24]</bitRange>
22050                <access>read-write</access>
22051              </field>
22052              <field>
22053                <name>RX_HEADER_SYNC_ERROR</name>
22054                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
22055                <bitRange>[25:25]</bitRange>
22056                <access>read-write</access>
22057              </field>
22058              <field>
22059                <name>RX_HEADER_PARITY_ERROR</name>
22060                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
22061                <bitRange>[26:26]</bitRange>
22062                <access>read-write</access>
22063              </field>
22064              <field>
22065                <name>RX_RESPONSE_FRAME_ERROR</name>
22066                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
22067                <bitRange>[27:27]</bitRange>
22068                <access>read-write</access>
22069              </field>
22070              <field>
22071                <name>RX_RESPONSE_CHECKSUM_ERROR</name>
22072                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
22073                <bitRange>[28:28]</bitRange>
22074                <access>read-write</access>
22075              </field>
22076            </fields>
22077          </register>
22078          <register>
22079            <name>INTR_MASK</name>
22080            <description>Interrupt mask</description>
22081            <addressOffset>0xC8</addressOffset>
22082            <size>32</size>
22083            <access>read-write</access>
22084            <resetValue>0x0</resetValue>
22085            <resetMask>0x1F036F07</resetMask>
22086            <fields>
22087              <field>
22088                <name>TX_HEADER_DONE</name>
22089                <description>Mask for corresponding field in INTR register.</description>
22090                <bitRange>[0:0]</bitRange>
22091                <access>read-write</access>
22092              </field>
22093              <field>
22094                <name>TX_RESPONSE_DONE</name>
22095                <description>Mask for corresponding field in INTR register.</description>
22096                <bitRange>[1:1]</bitRange>
22097                <access>read-write</access>
22098              </field>
22099              <field>
22100                <name>TX_WAKEUP_DONE</name>
22101                <description>Mask for corresponding field in INTR register.</description>
22102                <bitRange>[2:2]</bitRange>
22103                <access>read-write</access>
22104              </field>
22105              <field>
22106                <name>RX_HEADER_DONE</name>
22107                <description>Mask for corresponding field in INTR register.</description>
22108                <bitRange>[8:8]</bitRange>
22109                <access>read-write</access>
22110              </field>
22111              <field>
22112                <name>RX_RESPONSE_DONE</name>
22113                <description>Mask for corresponding field in INTR register.</description>
22114                <bitRange>[9:9]</bitRange>
22115                <access>read-write</access>
22116              </field>
22117              <field>
22118                <name>RX_BREAK_WAKEUP_DONE</name>
22119                <description>Mask for corresponding field in INTR register.</description>
22120                <bitRange>[10:10]</bitRange>
22121                <access>read-write</access>
22122              </field>
22123              <field>
22124                <name>RX_HEADER_SYNC_DONE</name>
22125                <description>Mask for corresponding field in INTR register.</description>
22126                <bitRange>[11:11]</bitRange>
22127                <access>read-write</access>
22128              </field>
22129              <field>
22130                <name>RX_NOISE_DETECT</name>
22131                <description>Mask for corresponding field in INTR register.</description>
22132                <bitRange>[13:13]</bitRange>
22133                <access>read-write</access>
22134              </field>
22135              <field>
22136                <name>TIMEOUT</name>
22137                <description>Mask for corresponding field in INTR register.</description>
22138                <bitRange>[14:14]</bitRange>
22139                <access>read-write</access>
22140              </field>
22141              <field>
22142                <name>TX_HEADER_BIT_ERROR</name>
22143                <description>Mask for corresponding field in INTR register.</description>
22144                <bitRange>[16:16]</bitRange>
22145                <access>read-write</access>
22146              </field>
22147              <field>
22148                <name>TX_RESPONSE_BIT_ERROR</name>
22149                <description>Mask for corresponding field in INTR register.</description>
22150                <bitRange>[17:17]</bitRange>
22151                <access>read-write</access>
22152              </field>
22153              <field>
22154                <name>RX_HEADER_FRAME_ERROR</name>
22155                <description>Mask for corresponding field in INTR register.</description>
22156                <bitRange>[24:24]</bitRange>
22157                <access>read-write</access>
22158              </field>
22159              <field>
22160                <name>RX_HEADER_SYNC_ERROR</name>
22161                <description>Mask for corresponding field in INTR register.</description>
22162                <bitRange>[25:25]</bitRange>
22163                <access>read-write</access>
22164              </field>
22165              <field>
22166                <name>RX_HEADER_PARITY_ERROR</name>
22167                <description>Mask for corresponding field in INTR register.</description>
22168                <bitRange>[26:26]</bitRange>
22169                <access>read-write</access>
22170              </field>
22171              <field>
22172                <name>RX_RESPONSE_FRAME_ERROR</name>
22173                <description>Mask for corresponding field in INTR register.</description>
22174                <bitRange>[27:27]</bitRange>
22175                <access>read-write</access>
22176              </field>
22177              <field>
22178                <name>RX_RESPONSE_CHECKSUM_ERROR</name>
22179                <description>Mask for corresponding field in INTR register.</description>
22180                <bitRange>[28:28]</bitRange>
22181                <access>read-write</access>
22182              </field>
22183            </fields>
22184          </register>
22185          <register>
22186            <name>INTR_MASKED</name>
22187            <description>Interrupt masked</description>
22188            <addressOffset>0xCC</addressOffset>
22189            <size>32</size>
22190            <access>read-only</access>
22191            <resetValue>0x0</resetValue>
22192            <resetMask>0x1F036F07</resetMask>
22193            <fields>
22194              <field>
22195                <name>TX_HEADER_DONE</name>
22196                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
22197                <bitRange>[0:0]</bitRange>
22198                <access>read-only</access>
22199              </field>
22200              <field>
22201                <name>TX_RESPONSE_DONE</name>
22202                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
22203                <bitRange>[1:1]</bitRange>
22204                <access>read-only</access>
22205              </field>
22206              <field>
22207                <name>TX_WAKEUP_DONE</name>
22208                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
22209                <bitRange>[2:2]</bitRange>
22210                <access>read-only</access>
22211              </field>
22212              <field>
22213                <name>RX_HEADER_DONE</name>
22214                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
22215                <bitRange>[8:8]</bitRange>
22216                <access>read-only</access>
22217              </field>
22218              <field>
22219                <name>RX_RESPONSE_DONE</name>
22220                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
22221                <bitRange>[9:9]</bitRange>
22222                <access>read-only</access>
22223              </field>
22224              <field>
22225                <name>RX_BREAK_WAKEUP_DONE</name>
22226                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
22227                <bitRange>[10:10]</bitRange>
22228                <access>read-only</access>
22229              </field>
22230              <field>
22231                <name>RX_HEADER_SYNC_DONE</name>
22232                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
22233                <bitRange>[11:11]</bitRange>
22234                <access>read-only</access>
22235              </field>
22236              <field>
22237                <name>RX_NOISE_DETECT</name>
22238                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
22239                <bitRange>[13:13]</bitRange>
22240                <access>read-only</access>
22241              </field>
22242              <field>
22243                <name>TIMEOUT</name>
22244                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
22245                <bitRange>[14:14]</bitRange>
22246                <access>read-only</access>
22247              </field>
22248              <field>
22249                <name>TX_HEADER_BIT_ERROR</name>
22250                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
22251                <bitRange>[16:16]</bitRange>
22252                <access>read-only</access>
22253              </field>
22254              <field>
22255                <name>TX_RESPONSE_BIT_ERROR</name>
22256                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
22257                <bitRange>[17:17]</bitRange>
22258                <access>read-only</access>
22259              </field>
22260              <field>
22261                <name>RX_HEADER_FRAME_ERROR</name>
22262                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
22263                <bitRange>[24:24]</bitRange>
22264                <access>read-only</access>
22265              </field>
22266              <field>
22267                <name>RX_HEADER_SYNC_ERROR</name>
22268                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
22269                <bitRange>[25:25]</bitRange>
22270                <access>read-only</access>
22271              </field>
22272              <field>
22273                <name>RX_HEADER_PARITY_ERROR</name>
22274                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
22275                <bitRange>[26:26]</bitRange>
22276                <access>read-only</access>
22277              </field>
22278              <field>
22279                <name>RX_RESPONSE_FRAME_ERROR</name>
22280                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
22281                <bitRange>[27:27]</bitRange>
22282                <access>read-only</access>
22283              </field>
22284              <field>
22285                <name>RX_RESPONSE_CHECKSUM_ERROR</name>
22286                <description>Logical AND of corresponding INTR and INTR_MASK fields.</description>
22287                <bitRange>[28:28]</bitRange>
22288                <access>read-only</access>
22289              </field>
22290            </fields>
22291          </register>
22292        </cluster>
22293      </registers>
22294    </peripheral>
22295    <peripheral>
22296      <name>CANFD0</name>
22297      <description>CAN Controller</description>
22298      <headerStructName>CANFD</headerStructName>
22299      <baseAddress>0x40520000</baseAddress>
22300      <addressBlock>
22301        <offset>0</offset>
22302        <size>131072</size>
22303        <usage>registers</usage>
22304      </addressBlock>
22305      <registers>
22306        <cluster>
22307          <dim>3</dim>
22308          <dimIncrement>512</dimIncrement>
22309          <name>CH[%s]</name>
22310          <description>FIFO wrapper around M_TTCAN 3PIP, to enable DMA</description>
22311          <addressOffset>0x00000000</addressOffset>
22312          <cluster>
22313            <name>M_TTCAN</name>
22314            <description>TTCAN 3PIP, includes FD</description>
22315            <addressOffset>0x00000000</addressOffset>
22316            <register>
22317              <name>CREL</name>
22318              <description>Core Release Register</description>
22319              <addressOffset>0x0</addressOffset>
22320              <size>32</size>
22321              <access>read-only</access>
22322              <resetValue>0x32380609</resetValue>
22323              <resetMask>0xFFFFFFFF</resetMask>
22324              <fields>
22325                <field>
22326                  <name>DAY</name>
22327                  <description>Time Stamp Day
22328Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis.</description>
22329                  <bitRange>[7:0]</bitRange>
22330                  <access>read-only</access>
22331                </field>
22332                <field>
22333                  <name>MON</name>
22334                  <description>Time Stamp Month
22335Two digits, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis.</description>
22336                  <bitRange>[15:8]</bitRange>
22337                  <access>read-only</access>
22338                </field>
22339                <field>
22340                  <name>YEAR</name>
22341                  <description>Time Stamp Year
22342One digit, BCD-coded. This field is set by generic parameter on M_TTCAN synthesis.</description>
22343                  <bitRange>[19:16]</bitRange>
22344                  <access>read-only</access>
22345                </field>
22346                <field>
22347                  <name>SUBSTEP</name>
22348                  <description>Sub-step of Core Release
22349One digit, BCD-coded.</description>
22350                  <bitRange>[23:20]</bitRange>
22351                  <access>read-only</access>
22352                </field>
22353                <field>
22354                  <name>STEP</name>
22355                  <description>Step of Core Release
22356One digit, BCD-coded.</description>
22357                  <bitRange>[27:24]</bitRange>
22358                  <access>read-only</access>
22359                </field>
22360                <field>
22361                  <name>REL</name>
22362                  <description>Core Release
22363One digit, BCD-coded.</description>
22364                  <bitRange>[31:28]</bitRange>
22365                  <access>read-only</access>
22366                </field>
22367              </fields>
22368            </register>
22369            <register>
22370              <name>ENDN</name>
22371              <description>Endian Register</description>
22372              <addressOffset>0x4</addressOffset>
22373              <size>32</size>
22374              <access>read-only</access>
22375              <resetValue>0x87654321</resetValue>
22376              <resetMask>0xFFFFFFFF</resetMask>
22377              <fields>
22378                <field>
22379                  <name>ETV</name>
22380                  <description>Endianness Test Value
22381The endianness test value is 0x87654321.</description>
22382                  <bitRange>[31:0]</bitRange>
22383                  <access>read-only</access>
22384                </field>
22385              </fields>
22386            </register>
22387            <register>
22388              <name>DBTP</name>
22389              <description>Data Bit Timing &amp; Prescaler Register</description>
22390              <addressOffset>0xC</addressOffset>
22391              <size>32</size>
22392              <access>read-write</access>
22393              <resetValue>0xA33</resetValue>
22394              <resetMask>0x9F1FFF</resetMask>
22395              <fields>
22396                <field>
22397                  <name>DSJW</name>
22398                  <description>Data (Re)Synchronization Jump Width
223990x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is
22400such that one more than the value programmed here is used.</description>
22401                  <bitRange>[3:0]</bitRange>
22402                  <access>read-write</access>
22403                </field>
22404                <field>
22405                  <name>DTSEG2</name>
22406                  <description>Data time segment after sample point
224070x0-0xF Valid values are 0 to 15. The actual interpretation by the hardware of this value is
22408such that one more than the programmed value is used.</description>
22409                  <bitRange>[7:4]</bitRange>
22410                  <access>read-write</access>
22411                </field>
22412                <field>
22413                  <name>DTSEG1</name>
22414                  <description>Data time segment before sample point
224150x00-0x1F Valid values are 0 to 31. The actual interpretation by the hardware of this value is
22416such that one more than the programmed value is used.</description>
22417                  <bitRange>[12:8]</bitRange>
22418                  <access>read-write</access>
22419                </field>
22420                <field>
22421                  <name>DBRP</name>
22422                  <description>Data Bit Rate Prescaler
224230x00-0x1F The value by which the oscillator frequency is divided for generating the bit time
22424quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit
22425Rate Prescaler are 0 to 31. The actual interpretation by the hardware of this value is
22426such that one more than the value programmed here is used.</description>
22427                  <bitRange>[20:16]</bitRange>
22428                  <access>read-write</access>
22429                </field>
22430                <field>
22431                  <name>TDC</name>
22432                  <description>Transmitter Delay Compensation
224330= Transmitter Delay Compensation disabled
224341= Transmitter Delay Compensation enabled</description>
22435                  <bitRange>[23:23]</bitRange>
22436                  <access>read-write</access>
22437                </field>
22438              </fields>
22439            </register>
22440            <register>
22441              <name>TEST</name>
22442              <description>Test Register</description>
22443              <addressOffset>0x10</addressOffset>
22444              <size>32</size>
22445              <access>read-write</access>
22446              <resetValue>0x0</resetValue>
22447              <resetMask>0x7F</resetMask>
22448              <fields>
22449                <field>
22450                  <name>TAM</name>
22451                  <description>ASC is not supported by M_TTCAN
22452Test ASC Multiplexer Control
22453Controls output pin m_ttcan_ascm in test mode, ORed with the signal from the FSE
224540= Level at pin m_ttcan_ascm controlled by FSE
224551= Level at pin m_ttcan_ascm = '1'</description>
22456                  <bitRange>[0:0]</bitRange>
22457                  <access>read-write</access>
22458                </field>
22459                <field>
22460                  <name>TAT</name>
22461                  <description>ASC is not supported by M_TTCAN
22462Test ASC Transmit Control
22463Controls output pin m_ttcan_asct in test mode, ORed with the signal from the FSE
224640= Level at pin m_ttcan_asct controlled by FSE
224651= Level at pin m_ttcan_asct = '1'</description>
22466                  <bitRange>[1:1]</bitRange>
22467                  <access>read-write</access>
22468                </field>
22469                <field>
22470                  <name>CAM</name>
22471                  <description>ASC is not supported by M_TTCAN
22472Check ASC Multiplexer Control
22473Monitors level at output pin m_ttcan_ascm.
224740= Output pin m_ttcan_ascm = '0'
224751= Output pin m_ttcan_ascm = '1'</description>
22476                  <bitRange>[2:2]</bitRange>
22477                  <access>read-write</access>
22478                </field>
22479                <field>
22480                  <name>CAT</name>
22481                  <description>ASC is not supported by M_TTCAN
22482Check ASC Transmit Control
22483Monitors level at output pin m_ttcan_asct.
224840= Output pin m_ttcan_asct = '0'</description>
22485                  <bitRange>[3:3]</bitRange>
22486                  <access>read-write</access>
22487                </field>
22488                <field>
22489                  <name>LBCK</name>
22490                  <description>Loop Back Mode
224910= Reset value, Loop Back Mode is disabled
224921= Loop Back Mode is enabled (see Section 3.1.9, Test Modes)</description>
22493                  <bitRange>[4:4]</bitRange>
22494                  <access>read-write</access>
22495                </field>
22496                <field>
22497                  <name>TX</name>
22498                  <description>Control of Transmit Pin
2249900 Reset value, m_ttcan_tx controlled by the CAN Core, updated at the end of the CAN bit time
2250001 Sample Point can be monitored at pin m_ttcan_tx
2250110 Dominant ('0') level at pin m_ttcan_tx
2250211 Recessive ('1') at pin m_ttcan_tx</description>
22503                  <bitRange>[6:5]</bitRange>
22504                  <access>read-write</access>
22505                </field>
22506                <field>
22507                  <name>RX</name>
22508                  <description>Receive Pin
22509Monitors the actual value of pin m_ttcan_rx
225100= The CAN bus is dominant (m_ttcan_rx = '0')
225111= The CAN bus is recessive (m_ttcan_rx = '1')</description>
22512                  <bitRange>[7:7]</bitRange>
22513                  <access>read-only</access>
22514                </field>
22515              </fields>
22516            </register>
22517            <register>
22518              <name>RWD</name>
22519              <description>RAM Watchdog</description>
22520              <addressOffset>0x14</addressOffset>
22521              <size>32</size>
22522              <access>read-write</access>
22523              <resetValue>0x0</resetValue>
22524              <resetMask>0xFFFF</resetMask>
22525              <fields>
22526                <field>
22527                  <name>WDC</name>
22528                  <description>Watchdog Configuration
22529Start value of the Message RAM Watchdog Counter. With the reset value of '00' the counter is
22530disabled.</description>
22531                  <bitRange>[7:0]</bitRange>
22532                  <access>read-write</access>
22533                </field>
22534                <field>
22535                  <name>WDV</name>
22536                  <description>Watchdog Value
22537Actual Message RAM Watchdog Counter Value.</description>
22538                  <bitRange>[15:8]</bitRange>
22539                  <access>read-only</access>
22540                </field>
22541              </fields>
22542            </register>
22543            <register>
22544              <name>CCCR</name>
22545              <description>CC Control Register</description>
22546              <addressOffset>0x18</addressOffset>
22547              <size>32</size>
22548              <access>read-write</access>
22549              <resetValue>0x1</resetValue>
22550              <resetMask>0xF3FF</resetMask>
22551              <fields>
22552                <field>
22553                  <name>INIT</name>
22554                  <description>Initialization
225550= Normal Operation
225561= Initialization is started</description>
22557                  <bitRange>[0:0]</bitRange>
22558                  <access>read-write</access>
22559                </field>
22560                <field>
22561                  <name>CCE</name>
22562                  <description>Configuration Change Enable
225630= The CPU has no write access to the protected configuration registers
225641= The CPU has write access to the protected configuration registers (while CCCR.INIT = '1')</description>
22565                  <bitRange>[1:1]</bitRange>
22566                  <access>read-write</access>
22567                </field>
22568                <field>
22569                  <name>ASM</name>
22570                  <description>Restricted Operation Mode
22571Bit ASM can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by
22572the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5.
225730= Normal CAN operation
225741= Restricted Operation Mode active</description>
22575                  <bitRange>[2:2]</bitRange>
22576                  <access>read-write</access>
22577                </field>
22578                <field>
22579                  <name>CSA</name>
22580                  <description>Clock Stop Acknowledge
225810= No clock stop acknowledged
225821= M_TTCAN may be set in power down by stopping m_ttcan_hclk and m_ttcan_cclk</description>
22583                  <bitRange>[3:3]</bitRange>
22584                  <access>read-write</access>
22585                </field>
22586                <field>
22587                  <name>CSR</name>
22588                  <description>Clock Stop Request, not supported by M_TTCAN use CTL.STOP_REQ at the group level instead.
225890= No clock stop is requested
225901= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after
22591all pending transfer requests have been completed and the CAN bus reached idle.</description>
22592                  <bitRange>[4:4]</bitRange>
22593                  <access>read-write</access>
22594                </field>
22595                <field>
22596                  <name>MON_</name>
22597                  <description>Bus Monitoring Mode
22598Bit MON can only be set by the Host when both CCE and INIT are set to '1'. The bit can be reset by
22599the Host at any time.
226000= Bus Monitoring Mode is disabled
226011= Bus Monitoring Mode is enabled</description>
22602                  <bitRange>[5:5]</bitRange>
22603                  <access>read-write</access>
22604                </field>
22605                <field>
22606                  <name>DAR</name>
22607                  <description>Disable Automatic Retransmission
226080= Automatic retransmission of messages not transmitted successfully enabled
226091= Automatic retransmission disabled</description>
22610                  <bitRange>[6:6]</bitRange>
22611                  <access>read-write</access>
22612                </field>
22613                <field>
22614                  <name>TEST</name>
22615                  <description>Test Mode Enable
226160= Normal operation, register TEST holds reset values
226171= Test Mode, write access to register TEST enabled</description>
22618                  <bitRange>[7:7]</bitRange>
22619                  <access>read-write</access>
22620                </field>
22621                <field>
22622                  <name>FDOE</name>
22623                  <description>FD Operation Enable
226240= FD operation disabled
226251= FD operation enabled</description>
22626                  <bitRange>[8:8]</bitRange>
22627                  <access>read-write</access>
22628                </field>
22629                <field>
22630                  <name>BRSE</name>
22631                  <description>Bit Rate Switch Enable
226320= Bit rate switching for transmissions disabled
226331= Bit rate switching for transmissions enabled</description>
22634                  <bitRange>[9:9]</bitRange>
22635                  <access>read-write</access>
22636                </field>
22637                <field>
22638                  <name>PXHD</name>
22639                  <description>Protocol Exception Handling Disable
226400= Protocol exception handling enabled
226411= Protocol exception handling disabled</description>
22642                  <bitRange>[12:12]</bitRange>
22643                  <access>read-write</access>
22644                </field>
22645                <field>
22646                  <name>EFBI</name>
22647                  <description>Edge Filtering during Bus Integration
226480= Edge filtering disabled
226491= Two consecutive dominant tq required to detect an edge for hard synchronization</description>
22650                  <bitRange>[13:13]</bitRange>
22651                  <access>read-write</access>
22652                </field>
22653                <field>
22654                  <name>TXP</name>
22655                  <description>Transmit Pause
22656If this bit is set, the M_TTCAN pauses for two CAN bit times before starting the next transmission
22657after itself has successfully transmitted a frame (see Section 3.5).
226580= Transmit pause disabled
226591= Transmit pause enabled</description>
22660                  <bitRange>[14:14]</bitRange>
22661                  <access>read-write</access>
22662                </field>
22663                <field>
22664                  <name>NISO</name>
22665                  <description>Non ISO Operation
22666If this bit is set, the M_TTCAN uses the CAN FD frame format as specified by the Bosch CAN FD
22667Specification V1.0.
226680= CAN FD frame format according to ISO 11898-1:2015
226691= CAN FD frame format according to Bosch CAN FD Specification V1.0 addressing the non-ISO CAN FD</description>
22670                  <bitRange>[15:15]</bitRange>
22671                  <access>read-write</access>
22672                </field>
22673              </fields>
22674            </register>
22675            <register>
22676              <name>NBTP</name>
22677              <description>Nominal Bit Timing &amp; Prescaler Register</description>
22678              <addressOffset>0x1C</addressOffset>
22679              <size>32</size>
22680              <access>read-write</access>
22681              <resetValue>0x6000A03</resetValue>
22682              <resetMask>0xFFFFFF7F</resetMask>
22683              <fields>
22684                <field>
22685                  <name>NTSEG2</name>
22686                  <description>Nominal Time segment after sample point
226870x01-0x7F Valid values are 1 to 127. The actual interpretation by the hardware of this value is
22688such that one more than the programmed value is used.</description>
22689                  <bitRange>[6:0]</bitRange>
22690                  <access>read-write</access>
22691                </field>
22692                <field>
22693                  <name>NTSEG1</name>
22694                  <description>Nominal Time segment before sample point
226950x01-0xFF Valid values are 1 to 255. The actual interpretation by the hardware of this value is
22696such that one more than the programmed value is used.</description>
22697                  <bitRange>[15:8]</bitRange>
22698                  <access>read-write</access>
22699                </field>
22700                <field>
22701                  <name>NBRP</name>
22702                  <description>Nominal Bit Rate Prescaler
227030x000-0x1FFThe value by which the oscillator frequency is divided for generating the bit time
22704quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit
22705Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is
22706such that one more than the value programmed here is used.</description>
22707                  <bitRange>[24:16]</bitRange>
22708                  <access>read-write</access>
22709                </field>
22710                <field>
22711                  <name>NSJW</name>
22712                  <description>Nominal (Re)Synchronization Jump Width
227130x00-0x7F Valid values are 0 to 127. The actual interpretation by the hardware of this value is
22714such that one more than the value programmed here is used.</description>
22715                  <bitRange>[31:25]</bitRange>
22716                  <access>read-write</access>
22717                </field>
22718              </fields>
22719            </register>
22720            <register>
22721              <name>TSCC</name>
22722              <description>Timestamp Counter Configuration</description>
22723              <addressOffset>0x20</addressOffset>
22724              <size>32</size>
22725              <access>read-write</access>
22726              <resetValue>0x0</resetValue>
22727              <resetMask>0xF0003</resetMask>
22728              <fields>
22729                <field>
22730                  <name>TSS</name>
22731                  <description>Timestamp Select, should always be set to external timestamp counter
2273200= Timestamp counter value always 0x0000
2273301= Timestamp counter value incremented according to TCP
2273410= External timestamp counter value used
2273511= Same as '00'</description>
22736                  <bitRange>[1:0]</bitRange>
22737                  <access>read-write</access>
22738                </field>
22739                <field>
22740                  <name>TCP</name>
22741                  <description>Timestamp Counter Prescaler (still used for TOCC)
227420x0-0xF Configures the timestamp and timeout counters time unit in multiples of CAN bit times
22743[1...16]. The actual interpretation by the hardware of this value is such that one more
22744than the value programmed here is used.</description>
22745                  <bitRange>[19:16]</bitRange>
22746                  <access>read-write</access>
22747                </field>
22748              </fields>
22749            </register>
22750            <register>
22751              <name>TSCV</name>
22752              <description>Timestamp Counter Value</description>
22753              <addressOffset>0x24</addressOffset>
22754              <size>32</size>
22755              <access>read-write</access>
22756              <resetValue>0x0</resetValue>
22757              <resetMask>0xFFFF</resetMask>
22758              <fields>
22759                <field>
22760                  <name>TSC</name>
22761                  <description>Timestamp Counter, not used for M_TTCAN
22762The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).
22763When TSCC.TSS = '01', the Timestamp Counter is incremented in multiples of CAN bit times
22764[1...16] depending on the configuration of TSCC.TCP. A wrap around sets interrupt flag IR.TSW.
22765Write access resets the counter to zero. When TSCC.TSS = '10', TSC reflects the external
22766Timestamp Counter value. A write access has no impact.</description>
22767                  <bitRange>[15:0]</bitRange>
22768                  <access>read-write</access>
22769                </field>
22770              </fields>
22771            </register>
22772            <register>
22773              <name>TOCC</name>
22774              <description>Timeout Counter Configuration</description>
22775              <addressOffset>0x28</addressOffset>
22776              <size>32</size>
22777              <access>read-write</access>
22778              <resetValue>0xFFFF0000</resetValue>
22779              <resetMask>0xFFFF0007</resetMask>
22780              <fields>
22781                <field>
22782                  <name>ETOC</name>
22783                  <description>Enable Timeout Counter
227840= Timeout Counter disabled
227851= Timeout Counter enabled</description>
22786                  <bitRange>[0:0]</bitRange>
22787                  <access>read-write</access>
22788                </field>
22789                <field>
22790                  <name>TOS</name>
22791                  <description>Timeout Select
22792When operating in Continuous mode, a write to TOCV presets the counter to the value configured
22793by TOCC.TOP and continues down-counting. When the Timeout Counter is controlled by one of the
22794FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting
22795is started when the first FIFO element is stored.
2279600= Continuous operation
2279701= Timeout controlled by Tx Event FIFO
2279810= Timeout controlled by Rx FIFO 0
2279911= Timeout controlled by Rx FIFO 1</description>
22800                  <bitRange>[2:1]</bitRange>
22801                  <access>read-write</access>
22802                </field>
22803                <field>
22804                  <name>TOP</name>
22805                  <description>Timeout Period
22806Start value of the Timeout Counter (down-counter). Configures the Timeout Period.</description>
22807                  <bitRange>[31:16]</bitRange>
22808                  <access>read-write</access>
22809                </field>
22810              </fields>
22811            </register>
22812            <register>
22813              <name>TOCV</name>
22814              <description>Timeout Counter Value</description>
22815              <addressOffset>0x2C</addressOffset>
22816              <size>32</size>
22817              <access>read-write</access>
22818              <resetValue>0xFFFF</resetValue>
22819              <resetMask>0xFFFF</resetMask>
22820              <fields>
22821                <field>
22822                  <name>TOC</name>
22823                  <description>Timeout Counter
22824The Timeout Counter is decremented in multiples of CAN bit times [1...16] depending on the
22825configuration of TSCC.TCP. When decremented to zero, interrupt flag IR.TOO is set and the
22826Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS.</description>
22827                  <bitRange>[15:0]</bitRange>
22828                  <access>read-write</access>
22829                </field>
22830              </fields>
22831            </register>
22832            <register>
22833              <name>ECR</name>
22834              <description>Error Counter Register</description>
22835              <addressOffset>0x40</addressOffset>
22836              <size>32</size>
22837              <access>read-only</access>
22838              <resetValue>0x0</resetValue>
22839              <resetMask>0xFFFFFF</resetMask>
22840              <fields>
22841                <field>
22842                  <name>TEC</name>
22843                  <description>Transmit Error Counter
22844Actual state of the Transmit Error Counter, values between 0 and 255</description>
22845                  <bitRange>[7:0]</bitRange>
22846                  <access>read-only</access>
22847                </field>
22848                <field>
22849                  <name>REC</name>
22850                  <description>Receive Error Counter
22851Actual state of the Receive Error Counter, values between 0 and 127</description>
22852                  <bitRange>[14:8]</bitRange>
22853                  <access>read-only</access>
22854                </field>
22855                <field>
22856                  <name>RP</name>
22857                  <description>Receive Error Passive
228580= The Receive Error Counter is below the error passive level of 128
228591= The Receive Error Counter has reached the error passive level of 128</description>
22860                  <bitRange>[15:15]</bitRange>
22861                  <access>read-only</access>
22862                </field>
22863                <field>
22864                  <name>CEL</name>
22865                  <description>CAN Error Logging
22866The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter
22867or the Receive Error Counter to be incremented. It is reset by read access to CEL. The counter stops
22868at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO.</description>
22869                  <bitRange>[23:16]</bitRange>
22870                  <access>read-only</access>
22871                </field>
22872              </fields>
22873            </register>
22874            <register>
22875              <name>PSR</name>
22876              <description>Protocol Status Register</description>
22877              <addressOffset>0x44</addressOffset>
22878              <size>32</size>
22879              <access>read-only</access>
22880              <resetValue>0x707</resetValue>
22881              <resetMask>0x7F7FFF</resetMask>
22882              <fields>
22883                <field>
22884                  <name>LEC</name>
22885                  <description>Last Error Code,
22886Set on Read0
22887The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0'
22888when a message has been transferred (reception or transmission) without error.
22889
228900= No Error: No error occurred since LEC has been reset by successful reception or transmission.
228911= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
228922= Form Error: A fixed format part of a received frame has the wrong format.
228933= AckError: The message transmitted by the M_TTCAN was not acknowledged by another node.
228944= Bit1Error: During the transmission of a message (with the exception of the arbitration field),
22895the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus
22896 value was dominant.
228975= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or
22898overload flag), the device wanted to send a dominant level (data or identifier bit logical value
228990'), but the monitored bus value was recessive. During Bus_Off recovery this status is set
22900each time a sequence of 11 recessive bits has been monitored. This enables the CPU to
22901monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at
22902dominant or continuously disturbed).
229036= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming
22904message does not match with the CRC calculated from the received data.
229057= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to '7'.
22906When the LEC shows the value '7', no CAN bus event was detected since the last CPU read
22907access to the Protocol Status Register.</description>
22908                  <bitRange>[2:0]</bitRange>
22909                  <access>read-only</access>
22910                </field>
22911                <field>
22912                  <name>ACT</name>
22913                  <description>Activity
22914Monitors the module's CAN communication state.
2291500= Synchronizing - node is synchronizing on CAN communication
2291601= Idle - node is neither receiver nor transmitter
2291710= Receiver - node is operating as receiver
2291811= Transmitter - node is operating as transmitter</description>
22919                  <bitRange>[4:3]</bitRange>
22920                  <access>read-only</access>
22921                </field>
22922                <field>
22923                  <name>EP</name>
22924                  <description>Error Passive
229250= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected
229261= The M_CAN is in the Error_Passive state</description>
22927                  <bitRange>[5:5]</bitRange>
22928                  <access>read-only</access>
22929                </field>
22930                <field>
22931                  <name>EW</name>
22932                  <description>Warning Status
229330= Both error counters are below the Error_Warning limit of 96
229341= At least one of error counter has reached the Error_Warning limit of 96</description>
22935                  <bitRange>[6:6]</bitRange>
22936                  <access>read-only</access>
22937                </field>
22938                <field>
22939                  <name>BO</name>
22940                  <description>Bus_Off Status
229410= The M_CAN is not Bus_Off
229421= The M_CAN is in Bus_Off state</description>
22943                  <bitRange>[7:7]</bitRange>
22944                  <access>read-only</access>
22945                </field>
22946                <field>
22947                  <name>DLEC</name>
22948                  <description>Data Phase Last Error Code
22949, Set on Read
22950Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set. Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with its BRS flag set has been transferred (reception or transmission) without error.</description>
22951                  <bitRange>[10:8]</bitRange>
22952                  <access>read-only</access>
22953                </field>
22954                <field>
22955                  <name>RESI</name>
22956                  <description>ESI flag of last received CAN FD Message
22957, Reset on Read
22958This bit is set together with RFDF, independent of acceptance filtering.
229590= Last received CAN FD message did not have its ESI flag set
229601= Last received CAN FD message had its ESI flag set</description>
22961                  <bitRange>[11:11]</bitRange>
22962                  <access>read-only</access>
22963                </field>
22964                <field>
22965                  <name>RBRS</name>
22966                  <description>BRS flag of last received CAN FD Message
22967, Reset on Read
22968This bit is set together with RFDF, independent of acceptance filtering.
229690= Last received CAN FD message did not have its BRS flag set
229701= Last received CAN FD message had its BRS flag set</description>
22971                  <bitRange>[12:12]</bitRange>
22972                  <access>read-only</access>
22973                </field>
22974                <field>
22975                  <name>RFDF</name>
22976                  <description>Received a CAN FD Message
22977, Reset on Read
22978This bit is set independent of acceptance filtering.
229790= Since this bit was reset by the CPU, no CAN FD message has been received
229801= Message in CAN FD format with FDF flag set has been received</description>
22981                  <bitRange>[13:13]</bitRange>
22982                  <access>read-only</access>
22983                </field>
22984                <field>
22985                  <name>PXE</name>
22986                  <description>Protocol Exception Event
22987, Reset on Read
229880= No protocol exception event occurred since last read access
229891= Protocol exception event occurred</description>
22990                  <bitRange>[14:14]</bitRange>
22991                  <access>read-only</access>
22992                </field>
22993                <field>
22994                  <name>TDCV</name>
22995                  <description>Transmitter Delay Compensation Value
229960x00-0x7F Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq.</description>
22997                  <bitRange>[22:16]</bitRange>
22998                  <access>read-only</access>
22999                </field>
23000              </fields>
23001            </register>
23002            <register>
23003              <name>TDCR</name>
23004              <description>Transmitter Delay Compensation Register</description>
23005              <addressOffset>0x48</addressOffset>
23006              <size>32</size>
23007              <access>read-write</access>
23008              <resetValue>0x0</resetValue>
23009              <resetMask>0x7F7F</resetMask>
23010              <fields>
23011                <field>
23012                  <name>TDCF</name>
23013                  <description>Transmitter Delay Compensation Filter Window Length
230140x00-0x7F Defines the minimum value for the SSP position, dominant edges on m_ttcan_rx
23015that would result in an earlier SSP position are ignored for transmitter delay measurement.
23016The feature is enabled when TDCF is configured to a value greater than
23017TDCO. Valid values are 0 to 127 mtq</description>
23018                  <bitRange>[6:0]</bitRange>
23019                  <access>read-write</access>
23020                </field>
23021                <field>
23022                  <name>TDCO</name>
23023                  <description>Transmitter Delay Compensation Offset
230240x00-0x7F Offset value defining the distance between the measured delay from m_ttcan_tx to
23025m_ttcan_rx and the secondary sample point. Valid values are 0 to 127 mtq.</description>
23026                  <bitRange>[14:8]</bitRange>
23027                  <access>read-write</access>
23028                </field>
23029              </fields>
23030            </register>
23031            <register>
23032              <name>IR</name>
23033              <description>Interrupt Register</description>
23034              <addressOffset>0x50</addressOffset>
23035              <size>32</size>
23036              <access>read-write</access>
23037              <resetValue>0x0</resetValue>
23038              <resetMask>0x3FFFFFFF</resetMask>
23039              <fields>
23040                <field>
23041                  <name>RF0N</name>
23042                  <description>Rx FIFO 0 New Message
230430= No new message written to Rx FIFO 0
230441= New message written to Rx FIFO 0</description>
23045                  <bitRange>[0:0]</bitRange>
23046                  <access>read-write</access>
23047                </field>
23048                <field>
23049                  <name>RF0W</name>
23050                  <description>Rx FIFO 0 Watermark Reached
230510= Rx FIFO 0 fill level below watermark
230521= Rx FIFO 0 fill level reached watermark</description>
23053                  <bitRange>[1:1]</bitRange>
23054                  <access>read-write</access>
23055                </field>
23056                <field>
23057                  <name>RF0F</name>
23058                  <description>Rx FIFO 0 Full
230590= Rx FIFO 0 not full
230601= Rx FIFO 0 full</description>
23061                  <bitRange>[2:2]</bitRange>
23062                  <access>read-write</access>
23063                </field>
23064                <field>
23065                  <name>RF0L_</name>
23066                  <description>Rx FIFO 0 Message Lost
230670= No Rx FIFO 0 message lost
230681= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero</description>
23069                  <bitRange>[3:3]</bitRange>
23070                  <access>read-write</access>
23071                </field>
23072                <field>
23073                  <name>RF1N</name>
23074                  <description>Rx FIFO 1 New Message
230750= No new message written to Rx FIFO 1
230761= New message written to Rx FIFO 1</description>
23077                  <bitRange>[4:4]</bitRange>
23078                  <access>read-write</access>
23079                </field>
23080                <field>
23081                  <name>RF1W</name>
23082                  <description>Rx FIFO 1 Watermark Reached
230830= Rx FIFO 1 fill level below watermark
230841= Rx FIFO 1 fill level reached watermark</description>
23085                  <bitRange>[5:5]</bitRange>
23086                  <access>read-write</access>
23087                </field>
23088                <field>
23089                  <name>RF1F</name>
23090                  <description>Rx FIFO 1 Full
230910= Rx FIFO 1 not full
230921= Rx FIFO 1 full</description>
23093                  <bitRange>[6:6]</bitRange>
23094                  <access>read-write</access>
23095                </field>
23096                <field>
23097                  <name>RF1L_</name>
23098                  <description>Rx FIFO 1 Message Lost
230990= No Rx FIFO 1 message lost
231001= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero</description>
23101                  <bitRange>[7:7]</bitRange>
23102                  <access>read-write</access>
23103                </field>
23104                <field>
23105                  <name>HPM</name>
23106                  <description>High Priority Message
231070= No high priority message received
231081= High priority message received</description>
23109                  <bitRange>[8:8]</bitRange>
23110                  <access>read-write</access>
23111                </field>
23112                <field>
23113                  <name>TC</name>
23114                  <description>Transmission Completed
231150= No transmission completed
231161= Transmission completed</description>
23117                  <bitRange>[9:9]</bitRange>
23118                  <access>read-write</access>
23119                </field>
23120                <field>
23121                  <name>TCF</name>
23122                  <description>Transmission Cancellation Finished
231230= No transmission cancellation finished
231241= Transmission cancellation finished</description>
23125                  <bitRange>[10:10]</bitRange>
23126                  <access>read-write</access>
23127                </field>
23128                <field>
23129                  <name>TFE</name>
23130                  <description>Tx FIFO Empty
231310= Tx FIFO non-empty
231321= Tx FIFO empty</description>
23133                  <bitRange>[11:11]</bitRange>
23134                  <access>read-write</access>
23135                </field>
23136                <field>
23137                  <name>TEFN</name>
23138                  <description>Tx Event FIFO New Entry
231390= Tx Event FIFO unchanged
231401= Tx Handler wrote Tx Event FIFO element</description>
23141                  <bitRange>[12:12]</bitRange>
23142                  <access>read-write</access>
23143                </field>
23144                <field>
23145                  <name>TEFW</name>
23146                  <description>Tx Event FIFO Watermark Reached
231470= Tx Event FIFO fill level below watermark
231481= Tx Event FIFO fill level reached watermark</description>
23149                  <bitRange>[13:13]</bitRange>
23150                  <access>read-write</access>
23151                </field>
23152                <field>
23153                  <name>TEFF</name>
23154                  <description>Tx Event FIFO Full
231550= Tx Event FIFO not full
231561= Tx Event FIFO full</description>
23157                  <bitRange>[14:14]</bitRange>
23158                  <access>read-write</access>
23159                </field>
23160                <field>
23161                  <name>TEFL_</name>
23162                  <description>Tx Event FIFO Element Lost
231630= No Tx Event FIFO element lost
231641= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero</description>
23165                  <bitRange>[15:15]</bitRange>
23166                  <access>read-write</access>
23167                </field>
23168                <field>
23169                  <name>TSW</name>
23170                  <description>Timestamp Wraparound
231710= No timestamp counter wrap-around
231721= Timestamp counter wrapped around</description>
23173                  <bitRange>[16:16]</bitRange>
23174                  <access>read-write</access>
23175                </field>
23176                <field>
23177                  <name>MRAF</name>
23178                  <description>Message RAM Access Failure
23179The flag is set, when the Rx Handler
23180- has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message storage is aborted and the Rx Handler starts processing of the following message.
23181- was not able to write a message to the Message RAM. In this case message storage is aborted.
23182In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location.
23183The flag is also set when the Tx Handler was not able to read a message from the Message RAM
23184in time. In this case message transmission is aborted. In case of a Tx Handler access failure the
23185M_TTCAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted
23186Operation Mode, the Host CPU has to reset CCCR.ASM.
231870= No Message RAM access failure occurred
231881= Message RAM access failure occurred</description>
23189                  <bitRange>[17:17]</bitRange>
23190                  <access>read-write</access>
23191                </field>
23192                <field>
23193                  <name>TOO</name>
23194                  <description>Timeout Occurred
231950= No timeout
231961= Timeout reached</description>
23197                  <bitRange>[18:18]</bitRange>
23198                  <access>read-write</access>
23199                </field>
23200                <field>
23201                  <name>DRX</name>
23202                  <description>Message stored to Dedicated Rx Buffer
23203The flag is set whenever a received message has been stored into a dedicated Rx Buffer.
232040= No Rx Buffer updated
232051= At least one received message stored into a Rx Buffer</description>
23206                  <bitRange>[19:19]</bitRange>
23207                  <access>read-write</access>
23208                </field>
23209                <field>
23210                  <name>BEC</name>
23211                  <description>M_TTCAN reports correctable ECC fault to the generic fault structure, this bit always reads as 0.
23212Bit Error Corrected
23213Message RAM bit error detected and corrected. Controlled by input signal m_ttcan_aeim_berr[0]
23214generated by an optional external parity / ECC logic attached to the Message RAM.
232150= No bit error detected when reading from Message RAM
232161= Bit error detected and corrected (e.g. ECC)</description>
23217                  <bitRange>[20:20]</bitRange>
23218                  <access>read-write</access>
23219                </field>
23220                <field>
23221                  <name>BEU</name>
23222                  <description>Bit Error Uncorrected
23223Message RAM bit error detected, uncorrected. Controlled by input signal m_ttcan_aeim_berr[1]
23224generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected
23225Message RAM bit error sets CCCR.INIT to '1'. This is done to avoid transmission of corrupted data.
232260= No bit error detected when reading from Message RAM
232271= Bit error detected, uncorrected (e.g. parity logic)</description>
23228                  <bitRange>[21:21]</bitRange>
23229                  <access>read-write</access>
23230                </field>
23231                <field>
23232                  <name>ELO</name>
23233                  <description>Error Logging Overflow
232340= CAN Error Logging Counter did not overflow
232351= Overflow of CAN Error Logging Counter occurred</description>
23236                  <bitRange>[22:22]</bitRange>
23237                  <access>read-write</access>
23238                </field>
23239                <field>
23240                  <name>EP_</name>
23241                  <description>Error Passive
232420= Error_Passive status unchanged
232431= Error_Passive status changed</description>
23244                  <bitRange>[23:23]</bitRange>
23245                  <access>read-write</access>
23246                </field>
23247                <field>
23248                  <name>EW_</name>
23249                  <description>Warning Status
232500= Error_Warning status unchanged
232511= Error_Warning status changed</description>
23252                  <bitRange>[24:24]</bitRange>
23253                  <access>read-write</access>
23254                </field>
23255                <field>
23256                  <name>BO_</name>
23257                  <description>Bus_Off Status
232580= Bus_Off status unchanged
232591= Bus_Off status changed</description>
23260                  <bitRange>[25:25]</bitRange>
23261                  <access>read-write</access>
23262                </field>
23263                <field>
23264                  <name>WDI</name>
23265                  <description>Watchdog Interrupt
232660= No Message RAM Watchdog event occurred
232671= Message RAM Watchdog event due to missing READY</description>
23268                  <bitRange>[26:26]</bitRange>
23269                  <access>read-write</access>
23270                </field>
23271                <field>
23272                  <name>PEA</name>
23273                  <description>Protocol Error in Arbitration Phase (Nominal Bit Time is used)
232740= No protocol error in arbitration phase
232751= Protocol error in arbitration phase detected (PSR.LEC != 0,7)</description>
23276                  <bitRange>[27:27]</bitRange>
23277                  <access>read-write</access>
23278                </field>
23279                <field>
23280                  <name>PED</name>
23281                  <description>Protocol Error in Data Phase (Data Bit Time is used)
232820= No protocol error in data phase
232831= Protocol error in data phase detected (PSR.DLEC != 0,7)</description>
23284                  <bitRange>[28:28]</bitRange>
23285                  <access>read-write</access>
23286                </field>
23287                <field>
23288                  <name>ARA</name>
23289                  <description>N/A</description>
23290                  <bitRange>[29:29]</bitRange>
23291                  <access>read-write</access>
23292                </field>
23293              </fields>
23294            </register>
23295            <register>
23296              <name>IE</name>
23297              <description>Interrupt Enable</description>
23298              <addressOffset>0x54</addressOffset>
23299              <size>32</size>
23300              <access>read-write</access>
23301              <resetValue>0x0</resetValue>
23302              <resetMask>0x3FFFFFFF</resetMask>
23303              <fields>
23304                <field>
23305                  <name>RF0NE</name>
23306                  <description>Rx FIFO 0 New Message Interrupt Enable</description>
23307                  <bitRange>[0:0]</bitRange>
23308                  <access>read-write</access>
23309                </field>
23310                <field>
23311                  <name>RF0WE</name>
23312                  <description>Rx FIFO 0 Watermark Reached Interrupt Enable</description>
23313                  <bitRange>[1:1]</bitRange>
23314                  <access>read-write</access>
23315                </field>
23316                <field>
23317                  <name>RF0FE</name>
23318                  <description>Rx FIFO 0 Full Interrupt Enable</description>
23319                  <bitRange>[2:2]</bitRange>
23320                  <access>read-write</access>
23321                </field>
23322                <field>
23323                  <name>RF0LE</name>
23324                  <description>Rx FIFO 0 Message Lost Interrupt Enable</description>
23325                  <bitRange>[3:3]</bitRange>
23326                  <access>read-write</access>
23327                </field>
23328                <field>
23329                  <name>RF1NE</name>
23330                  <description>Rx FIFO 1 New Message Interrupt Enable</description>
23331                  <bitRange>[4:4]</bitRange>
23332                  <access>read-write</access>
23333                </field>
23334                <field>
23335                  <name>RF1WE</name>
23336                  <description>Rx FIFO 1 Watermark Reached Interrupt Enable</description>
23337                  <bitRange>[5:5]</bitRange>
23338                  <access>read-write</access>
23339                </field>
23340                <field>
23341                  <name>RF1FE</name>
23342                  <description>Rx FIFO 1 Full Interrupt Enable</description>
23343                  <bitRange>[6:6]</bitRange>
23344                  <access>read-write</access>
23345                </field>
23346                <field>
23347                  <name>RF1LE</name>
23348                  <description>Rx FIFO 1 Message Lost Interrupt Enable</description>
23349                  <bitRange>[7:7]</bitRange>
23350                  <access>read-write</access>
23351                </field>
23352                <field>
23353                  <name>HPME</name>
23354                  <description>High Priority Message Interrupt Enable</description>
23355                  <bitRange>[8:8]</bitRange>
23356                  <access>read-write</access>
23357                </field>
23358                <field>
23359                  <name>TCE</name>
23360                  <description>Transmission Completed Interrupt Enable</description>
23361                  <bitRange>[9:9]</bitRange>
23362                  <access>read-write</access>
23363                </field>
23364                <field>
23365                  <name>TCFE</name>
23366                  <description>Transmission Cancellation Finished Interrupt Enable</description>
23367                  <bitRange>[10:10]</bitRange>
23368                  <access>read-write</access>
23369                </field>
23370                <field>
23371                  <name>TFEE</name>
23372                  <description>Tx FIFO Empty Interrupt Enable</description>
23373                  <bitRange>[11:11]</bitRange>
23374                  <access>read-write</access>
23375                </field>
23376                <field>
23377                  <name>TEFNE</name>
23378                  <description>Tx Event FIDO New Entry Interrupt Enable</description>
23379                  <bitRange>[12:12]</bitRange>
23380                  <access>read-write</access>
23381                </field>
23382                <field>
23383                  <name>TEFWE</name>
23384                  <description>Tx Event FIFO Watermark Reached Interrupt Enable</description>
23385                  <bitRange>[13:13]</bitRange>
23386                  <access>read-write</access>
23387                </field>
23388                <field>
23389                  <name>TEFFE</name>
23390                  <description>Tx Event FIFO Full Interrupt Enable</description>
23391                  <bitRange>[14:14]</bitRange>
23392                  <access>read-write</access>
23393                </field>
23394                <field>
23395                  <name>TEFLE</name>
23396                  <description>Tx Event FIFO Event Lost Interrupt Enable</description>
23397                  <bitRange>[15:15]</bitRange>
23398                  <access>read-write</access>
23399                </field>
23400                <field>
23401                  <name>TSWE</name>
23402                  <description>Timestamp Wraparound Interrupt Enable</description>
23403                  <bitRange>[16:16]</bitRange>
23404                  <access>read-write</access>
23405                </field>
23406                <field>
23407                  <name>MRAFE</name>
23408                  <description>Message RAM Access Failure Interrupt Enable</description>
23409                  <bitRange>[17:17]</bitRange>
23410                  <access>read-write</access>
23411                </field>
23412                <field>
23413                  <name>TOOE</name>
23414                  <description>Timeout Occurred Interrupt Enable</description>
23415                  <bitRange>[18:18]</bitRange>
23416                  <access>read-write</access>
23417                </field>
23418                <field>
23419                  <name>DRXE</name>
23420                  <description>Message stored to Dedicated Rx Buffer Interrupt Enable</description>
23421                  <bitRange>[19:19]</bitRange>
23422                  <access>read-write</access>
23423                </field>
23424                <field>
23425                  <name>BECE</name>
23426                  <description>Bit Error Corrected Interrupt Enable (not used in M_TTCAN)</description>
23427                  <bitRange>[20:20]</bitRange>
23428                  <access>read-write</access>
23429                </field>
23430                <field>
23431                  <name>BEUE</name>
23432                  <description>Bit Error Uncorrected Interrupt Enable</description>
23433                  <bitRange>[21:21]</bitRange>
23434                  <access>read-write</access>
23435                </field>
23436                <field>
23437                  <name>ELOE</name>
23438                  <description>Error Logging Overflow Interrupt Enable</description>
23439                  <bitRange>[22:22]</bitRange>
23440                  <access>read-write</access>
23441                </field>
23442                <field>
23443                  <name>EPE</name>
23444                  <description>Error Passive Interrupt Enable</description>
23445                  <bitRange>[23:23]</bitRange>
23446                  <access>read-write</access>
23447                </field>
23448                <field>
23449                  <name>EWE</name>
23450                  <description>Warning Status Interrupt Enable</description>
23451                  <bitRange>[24:24]</bitRange>
23452                  <access>read-write</access>
23453                </field>
23454                <field>
23455                  <name>BOE</name>
23456                  <description>Bus_Off Status Interrupt Enable</description>
23457                  <bitRange>[25:25]</bitRange>
23458                  <access>read-write</access>
23459                </field>
23460                <field>
23461                  <name>WDIE</name>
23462                  <description>Watchdog Interrupt Enable</description>
23463                  <bitRange>[26:26]</bitRange>
23464                  <access>read-write</access>
23465                </field>
23466                <field>
23467                  <name>PEAE</name>
23468                  <description>Protocol Error in Arbitration Phase Enable</description>
23469                  <bitRange>[27:27]</bitRange>
23470                  <access>read-write</access>
23471                </field>
23472                <field>
23473                  <name>PEDE</name>
23474                  <description>Protocol Error in Data Phase Enable</description>
23475                  <bitRange>[28:28]</bitRange>
23476                  <access>read-write</access>
23477                </field>
23478                <field>
23479                  <name>ARAE</name>
23480                  <description>N/A</description>
23481                  <bitRange>[29:29]</bitRange>
23482                  <access>read-write</access>
23483                </field>
23484              </fields>
23485            </register>
23486            <register>
23487              <name>ILS</name>
23488              <description>Interrupt Line Select</description>
23489              <addressOffset>0x58</addressOffset>
23490              <size>32</size>
23491              <access>read-write</access>
23492              <resetValue>0x0</resetValue>
23493              <resetMask>0x3FFFFFFF</resetMask>
23494              <fields>
23495                <field>
23496                  <name>RF0NL</name>
23497                  <description>Rx FIFO 0 New Message Interrupt Line</description>
23498                  <bitRange>[0:0]</bitRange>
23499                  <access>read-write</access>
23500                </field>
23501                <field>
23502                  <name>RF0WL</name>
23503                  <description>Rx FIFO 0 Watermark Reached Interrupt Line</description>
23504                  <bitRange>[1:1]</bitRange>
23505                  <access>read-write</access>
23506                </field>
23507                <field>
23508                  <name>RF0FL</name>
23509                  <description>Rx FIFO 0 Full Interrupt Line</description>
23510                  <bitRange>[2:2]</bitRange>
23511                  <access>read-write</access>
23512                </field>
23513                <field>
23514                  <name>RF0LL</name>
23515                  <description>Rx FIFO 0 Message Lost Interrupt Line</description>
23516                  <bitRange>[3:3]</bitRange>
23517                  <access>read-write</access>
23518                </field>
23519                <field>
23520                  <name>RF1NL</name>
23521                  <description>Rx FIFO 1 New Message Interrupt Line</description>
23522                  <bitRange>[4:4]</bitRange>
23523                  <access>read-write</access>
23524                </field>
23525                <field>
23526                  <name>RF1WL</name>
23527                  <description>Rx FIFO 1 Watermark Reached Interrupt Line</description>
23528                  <bitRange>[5:5]</bitRange>
23529                  <access>read-write</access>
23530                </field>
23531                <field>
23532                  <name>RF1FL</name>
23533                  <description>Rx FIFO 1 Full Interrupt Line</description>
23534                  <bitRange>[6:6]</bitRange>
23535                  <access>read-write</access>
23536                </field>
23537                <field>
23538                  <name>RF1LL</name>
23539                  <description>Rx FIFO 1 Message Lost Interrupt Line</description>
23540                  <bitRange>[7:7]</bitRange>
23541                  <access>read-write</access>
23542                </field>
23543                <field>
23544                  <name>HPML</name>
23545                  <description>High Priority Message Interrupt Line</description>
23546                  <bitRange>[8:8]</bitRange>
23547                  <access>read-write</access>
23548                </field>
23549                <field>
23550                  <name>TCL</name>
23551                  <description>Transmission Completed Interrupt Line</description>
23552                  <bitRange>[9:9]</bitRange>
23553                  <access>read-write</access>
23554                </field>
23555                <field>
23556                  <name>TCFL</name>
23557                  <description>Transmission Cancellation Finished Interrupt Line</description>
23558                  <bitRange>[10:10]</bitRange>
23559                  <access>read-write</access>
23560                </field>
23561                <field>
23562                  <name>TFEL</name>
23563                  <description>Tx FIFO Empty Interrupt Line</description>
23564                  <bitRange>[11:11]</bitRange>
23565                  <access>read-write</access>
23566                </field>
23567                <field>
23568                  <name>TEFNL</name>
23569                  <description>Tx Event FIFO New Entry Interrupt Line</description>
23570                  <bitRange>[12:12]</bitRange>
23571                  <access>read-write</access>
23572                </field>
23573                <field>
23574                  <name>TEFWL</name>
23575                  <description>Tx Event FIFO Watermark Reached Interrupt Line</description>
23576                  <bitRange>[13:13]</bitRange>
23577                  <access>read-write</access>
23578                </field>
23579                <field>
23580                  <name>TEFFL</name>
23581                  <description>Tx Event FIFO Full Interrupt Line</description>
23582                  <bitRange>[14:14]</bitRange>
23583                  <access>read-write</access>
23584                </field>
23585                <field>
23586                  <name>TEFLL</name>
23587                  <description>Tx Event FIFO Event Lost Interrupt Line</description>
23588                  <bitRange>[15:15]</bitRange>
23589                  <access>read-write</access>
23590                </field>
23591                <field>
23592                  <name>TSWL</name>
23593                  <description>Timestamp Wraparound Interrupt Line</description>
23594                  <bitRange>[16:16]</bitRange>
23595                  <access>read-write</access>
23596                </field>
23597                <field>
23598                  <name>MRAFL</name>
23599                  <description>Message RAM Access Failure Interrupt Line</description>
23600                  <bitRange>[17:17]</bitRange>
23601                  <access>read-write</access>
23602                </field>
23603                <field>
23604                  <name>TOOL</name>
23605                  <description>Timeout Occurred Interrupt Line</description>
23606                  <bitRange>[18:18]</bitRange>
23607                  <access>read-write</access>
23608                </field>
23609                <field>
23610                  <name>DRXL</name>
23611                  <description>Message stored to Dedicated Rx Buffer Interrupt Line</description>
23612                  <bitRange>[19:19]</bitRange>
23613                  <access>read-write</access>
23614                </field>
23615                <field>
23616                  <name>BECL</name>
23617                  <description>Bit Error Corrected Interrupt Line  (not used in M_TTCAN)</description>
23618                  <bitRange>[20:20]</bitRange>
23619                  <access>read-write</access>
23620                </field>
23621                <field>
23622                  <name>BEUL</name>
23623                  <description>Bit Error Uncorrected Interrupt Line</description>
23624                  <bitRange>[21:21]</bitRange>
23625                  <access>read-write</access>
23626                </field>
23627                <field>
23628                  <name>ELOL</name>
23629                  <description>Error Logging Overflow Interrupt Line</description>
23630                  <bitRange>[22:22]</bitRange>
23631                  <access>read-write</access>
23632                </field>
23633                <field>
23634                  <name>EPL</name>
23635                  <description>Error Passive Interrupt Line</description>
23636                  <bitRange>[23:23]</bitRange>
23637                  <access>read-write</access>
23638                </field>
23639                <field>
23640                  <name>EWL</name>
23641                  <description>Warning Status Interrupt Line</description>
23642                  <bitRange>[24:24]</bitRange>
23643                  <access>read-write</access>
23644                </field>
23645                <field>
23646                  <name>BOL</name>
23647                  <description>Bus_Off Status Interrupt Line</description>
23648                  <bitRange>[25:25]</bitRange>
23649                  <access>read-write</access>
23650                </field>
23651                <field>
23652                  <name>WDIL</name>
23653                  <description>Watchdog Interrupt Line</description>
23654                  <bitRange>[26:26]</bitRange>
23655                  <access>read-write</access>
23656                </field>
23657                <field>
23658                  <name>PEAL</name>
23659                  <description>Protocol Error in Arbitration Phase Line</description>
23660                  <bitRange>[27:27]</bitRange>
23661                  <access>read-write</access>
23662                </field>
23663                <field>
23664                  <name>PEDL</name>
23665                  <description>Protocol Error in Data Phase Line</description>
23666                  <bitRange>[28:28]</bitRange>
23667                  <access>read-write</access>
23668                </field>
23669                <field>
23670                  <name>ARAL</name>
23671                  <description>N/A</description>
23672                  <bitRange>[29:29]</bitRange>
23673                  <access>read-write</access>
23674                </field>
23675              </fields>
23676            </register>
23677            <register>
23678              <name>ILE</name>
23679              <description>Interrupt Line Enable</description>
23680              <addressOffset>0x5C</addressOffset>
23681              <size>32</size>
23682              <access>read-write</access>
23683              <resetValue>0x0</resetValue>
23684              <resetMask>0x3</resetMask>
23685              <fields>
23686                <field>
23687                  <name>EINT0</name>
23688                  <description>Enable Interrupt Line 0
236890= Interrupt line m_ttcan_int0 disabled
236901= Interrupt line m_ttcan_int0 enabled</description>
23691                  <bitRange>[0:0]</bitRange>
23692                  <access>read-write</access>
23693                </field>
23694                <field>
23695                  <name>EINT1</name>
23696                  <description>Enable Interrupt Line 1
236970= Interrupt line m_ttcan_int1 disabled
236981= Interrupt line m_ttcan_int1 enabled</description>
23699                  <bitRange>[1:1]</bitRange>
23700                  <access>read-write</access>
23701                </field>
23702              </fields>
23703            </register>
23704            <register>
23705              <name>GFC</name>
23706              <description>Global Filter Configuration</description>
23707              <addressOffset>0x80</addressOffset>
23708              <size>32</size>
23709              <access>read-write</access>
23710              <resetValue>0x0</resetValue>
23711              <resetMask>0x3F</resetMask>
23712              <fields>
23713                <field>
23714                  <name>RRFE</name>
23715                  <description>Reject Remote Frames Extended
237160= Filter remote frames with 29-bit extended IDs
237171= Reject all remote frames with 29-bit extended IDs</description>
23718                  <bitRange>[0:0]</bitRange>
23719                  <access>read-write</access>
23720                </field>
23721                <field>
23722                  <name>RRFS</name>
23723                  <description>Reject Remote Frames Standard
237240= Filter remote frames with 11-bit standard IDs
237251= Reject all remote frames with 11-bit standard IDs</description>
23726                  <bitRange>[1:1]</bitRange>
23727                  <access>read-write</access>
23728                </field>
23729                <field>
23730                  <name>ANFE</name>
23731                  <description>Accept Non-matching Frames Extended
23732Defines how received messages with 29-bit IDs that do not match any element of the filter list are
23733treated.
2373400= Accept in Rx FIFO 0
2373501= Accept in Rx FIFO 1
2373610= Reject
2373711= Reject</description>
23738                  <bitRange>[3:2]</bitRange>
23739                  <access>read-write</access>
23740                </field>
23741                <field>
23742                  <name>ANFS</name>
23743                  <description>Accept Non-matching Frames Standard
23744Defines how received messages with 11-bit IDs that do not match any element of the filter list are
23745treated.
2374600= Accept in Rx FIFO 0
2374701= Accept in Rx FIFO 1
2374810= Reject
2374911= Reject</description>
23750                  <bitRange>[5:4]</bitRange>
23751                  <access>read-write</access>
23752                </field>
23753              </fields>
23754            </register>
23755            <register>
23756              <name>SIDFC</name>
23757              <description>Standard ID Filter Configuration</description>
23758              <addressOffset>0x84</addressOffset>
23759              <size>32</size>
23760              <access>read-write</access>
23761              <resetValue>0x0</resetValue>
23762              <resetMask>0xFFFFFC</resetMask>
23763              <fields>
23764                <field>
23765                  <name>FLSSA</name>
23766                  <description>Filter List Standard Start Address
23767Start address of standard Message ID filter list (32-bit word address, see Figure 2).</description>
23768                  <bitRange>[15:2]</bitRange>
23769                  <access>read-write</access>
23770                </field>
23771                <field>
23772                  <name>LSS</name>
23773                  <description>List Size Standard
237740= No standard Message ID filter
237751-128= Number of standard Message ID filter elements
23776128= Values greater than 128 are interpreted as 128</description>
23777                  <bitRange>[23:16]</bitRange>
23778                  <access>read-write</access>
23779                </field>
23780              </fields>
23781            </register>
23782            <register>
23783              <name>XIDFC</name>
23784              <description>Extended ID Filter Configuration</description>
23785              <addressOffset>0x88</addressOffset>
23786              <size>32</size>
23787              <access>read-write</access>
23788              <resetValue>0x0</resetValue>
23789              <resetMask>0x7FFFFC</resetMask>
23790              <fields>
23791                <field>
23792                  <name>FLESA</name>
23793                  <description>Filter List Extended Start Address
23794Start address of extended Message ID filter list (32-bit word address, see Figure 2).</description>
23795                  <bitRange>[15:2]</bitRange>
23796                  <access>read-write</access>
23797                </field>
23798                <field>
23799                  <name>LSE</name>
23800                  <description>List Size Extended
238010= No extended Message ID filter
238021-64= Number of extended Message ID filter elements
2380364= Values greater than 64 are interpreted as 64</description>
23804                  <bitRange>[22:16]</bitRange>
23805                  <access>read-write</access>
23806                </field>
23807              </fields>
23808            </register>
23809            <register>
23810              <name>XIDAM</name>
23811              <description>Extended ID AND Mask</description>
23812              <addressOffset>0x90</addressOffset>
23813              <size>32</size>
23814              <access>read-write</access>
23815              <resetValue>0x1FFFFFFF</resetValue>
23816              <resetMask>0x1FFFFFFF</resetMask>
23817              <fields>
23818                <field>
23819                  <name>EIDM</name>
23820                  <description>Extended ID Mask
23821For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message
23822ID of a received frame. Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all
23823bits set to one the mask is not active.</description>
23824                  <bitRange>[28:0]</bitRange>
23825                  <access>read-write</access>
23826                </field>
23827              </fields>
23828            </register>
23829            <register>
23830              <name>HPMS</name>
23831              <description>High Priority Message Status</description>
23832              <addressOffset>0x94</addressOffset>
23833              <size>32</size>
23834              <access>read-only</access>
23835              <resetValue>0x0</resetValue>
23836              <resetMask>0xFFFF</resetMask>
23837              <fields>
23838                <field>
23839                  <name>BIDX</name>
23840                  <description>Buffer Index
23841Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = '1'.</description>
23842                  <bitRange>[5:0]</bitRange>
23843                  <access>read-only</access>
23844                </field>
23845                <field>
23846                  <name>MSI</name>
23847                  <description>Message Storage Indicator
2384800= No FIFO selected
2384901= FIFO message lost
2385010= Message stored in FIFO 0
2385111= Message stored in FIFO 1</description>
23852                  <bitRange>[7:6]</bitRange>
23853                  <access>read-only</access>
23854                </field>
23855                <field>
23856                  <name>FIDX</name>
23857                  <description>Filter Index
23858Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1.</description>
23859                  <bitRange>[14:8]</bitRange>
23860                  <access>read-only</access>
23861                </field>
23862                <field>
23863                  <name>FLST</name>
23864                  <description>Filter List
23865Indicates the filter list of the matching filter element.
238660= Standard Filter List
238671= Extended Filter List</description>
23868                  <bitRange>[15:15]</bitRange>
23869                  <access>read-only</access>
23870                </field>
23871              </fields>
23872            </register>
23873            <register>
23874              <name>NDAT1</name>
23875              <description>New Data 1</description>
23876              <addressOffset>0x98</addressOffset>
23877              <size>32</size>
23878              <access>read-write</access>
23879              <resetValue>0x0</resetValue>
23880              <resetMask>0xFFFFFFFF</resetMask>
23881              <fields>
23882                <field>
23883                  <name>ND</name>
23884                  <description>New Data
23885The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective
23886Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.
23887A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard
23888reset will clear the register.
238890= Rx Buffer not updated
238901= Rx Buffer updated from new message</description>
23891                  <bitRange>[31:0]</bitRange>
23892                  <access>read-write</access>
23893                </field>
23894              </fields>
23895            </register>
23896            <register>
23897              <name>NDAT2</name>
23898              <description>New Data 2</description>
23899              <addressOffset>0x9C</addressOffset>
23900              <size>32</size>
23901              <access>read-write</access>
23902              <resetValue>0x0</resetValue>
23903              <resetMask>0xFFFFFFFF</resetMask>
23904              <fields>
23905                <field>
23906                  <name>ND</name>
23907                  <description>New Data
23908The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective
23909Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them.
23910A flag is cleared by writing a '1' to the corresponding bit position. Writing a '0' has no effect. A hard
23911reset will clear the register.
239120= Rx Buffer not updated
239131= Rx Buffer updated from new message</description>
23914                  <bitRange>[31:0]</bitRange>
23915                  <access>read-write</access>
23916                </field>
23917              </fields>
23918            </register>
23919            <register>
23920              <name>RXF0C</name>
23921              <description>Rx FIFO 0 Configuration</description>
23922              <addressOffset>0xA0</addressOffset>
23923              <size>32</size>
23924              <access>read-write</access>
23925              <resetValue>0x0</resetValue>
23926              <resetMask>0xFF7FFFFC</resetMask>
23927              <fields>
23928                <field>
23929                  <name>F0SA</name>
23930                  <description>Rx FIFO 0 Start Address
23931Start address of Rx FIFO 0 in Message RAM (32-bit word address, see Figure 2).</description>
23932                  <bitRange>[15:2]</bitRange>
23933                  <access>read-write</access>
23934                </field>
23935                <field>
23936                  <name>F0S</name>
23937                  <description>Rx FIFO 0 Size
239380= No Rx FIFO 0
239391-64= Number of Rx FIFO 0 elements
2394064= Values greater than 64 are interpreted as 64
23941The Rx FIFO 0 elements are indexed from 0 to F0S-1</description>
23942                  <bitRange>[22:16]</bitRange>
23943                  <access>read-write</access>
23944                </field>
23945                <field>
23946                  <name>F0WM</name>
23947                  <description>Rx FIFO 0 Watermark
239480= Watermark interrupt disabled
239491-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W)
2395064= Watermark interrupt disabled</description>
23951                  <bitRange>[30:24]</bitRange>
23952                  <access>read-write</access>
23953                </field>
23954                <field>
23955                  <name>F0OM</name>
23956                  <description>FIFO 0 Operation Mode
23957FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2).
239580= FIFO 0 blocking mode
239591= FIFO 0 overwrite mode</description>
23960                  <bitRange>[31:31]</bitRange>
23961                  <access>read-write</access>
23962                </field>
23963              </fields>
23964            </register>
23965            <register>
23966              <name>RXF0S</name>
23967              <description>Rx FIFO 0 Status</description>
23968              <addressOffset>0xA4</addressOffset>
23969              <size>32</size>
23970              <access>read-only</access>
23971              <resetValue>0x0</resetValue>
23972              <resetMask>0x33F3F7F</resetMask>
23973              <fields>
23974                <field>
23975                  <name>F0FL</name>
23976                  <description>Rx FIFO 0 Fill Level
23977Number of elements stored in Rx FIFO 0, range 0 to 64.
23978When the software reading the value immediately after writing to RXF0A.F0AI, this value should be read twice to ensure that the update is reflected.</description>
23979                  <bitRange>[6:0]</bitRange>
23980                  <access>read-only</access>
23981                </field>
23982                <field>
23983                  <name>F0GI</name>
23984                  <description>Rx FIFO 0 Get Index
23985Rx FIFO 0 read index pointer, range 0 to 63.
23986This field is updated by the software writing to RXF0A.F0AI.
23987When the software reading the value immediately after writing to RXF0A.F0AI, this value should be read twice to ensure that the update is reflected.</description>
23988                  <bitRange>[13:8]</bitRange>
23989                  <access>read-only</access>
23990                </field>
23991                <field>
23992                  <name>F0PI</name>
23993                  <description>Rx FIFO 0 Put Index
23994Rx FIFO 0 write index pointer, range 0 to 63.</description>
23995                  <bitRange>[21:16]</bitRange>
23996                  <access>read-only</access>
23997                </field>
23998                <field>
23999                  <name>F0F</name>
24000                  <description>Rx FIFO 0 Full
240010= Rx FIFO 0 not full
240021= Rx FIFO 0 full</description>
24003                  <bitRange>[24:24]</bitRange>
24004                  <access>read-only</access>
24005                </field>
24006                <field>
24007                  <name>RF0L</name>
24008                  <description>Rx FIFO 0 Message Lost
24009This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset.
240100= No Rx FIFO 0 message lost
240111= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero</description>
24012                  <bitRange>[25:25]</bitRange>
24013                  <access>read-only</access>
24014                </field>
24015              </fields>
24016            </register>
24017            <register>
24018              <name>RXF0A</name>
24019              <description>Rx FIFO 0 Acknowledge</description>
24020              <addressOffset>0xA8</addressOffset>
24021              <size>32</size>
24022              <access>read-write</access>
24023              <resetValue>0x0</resetValue>
24024              <resetMask>0x3F</resetMask>
24025              <fields>
24026                <field>
24027                  <name>F0AI</name>
24028                  <description>Rx FIFO 0 Acknowledge Index
24029After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the
24030 buffer index of the last element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO 0 Get Index
24031 RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL.</description>
24032                  <bitRange>[5:0]</bitRange>
24033                  <access>read-write</access>
24034                </field>
24035              </fields>
24036            </register>
24037            <register>
24038              <name>RXBC</name>
24039              <description>Rx Buffer Configuration</description>
24040              <addressOffset>0xAC</addressOffset>
24041              <size>32</size>
24042              <access>read-write</access>
24043              <resetValue>0x0</resetValue>
24044              <resetMask>0xFFFC</resetMask>
24045              <fields>
24046                <field>
24047                  <name>RBSA</name>
24048                  <description>Rx Buffer Start Address
24049Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).
24050Also used to reference debug messages A,B,C.</description>
24051                  <bitRange>[15:2]</bitRange>
24052                  <access>read-write</access>
24053                </field>
24054              </fields>
24055            </register>
24056            <register>
24057              <name>RXF1C</name>
24058              <description>Rx FIFO 1 Configuration</description>
24059              <addressOffset>0xB0</addressOffset>
24060              <size>32</size>
24061              <access>read-write</access>
24062              <resetValue>0x0</resetValue>
24063              <resetMask>0xFF7FFFFC</resetMask>
24064              <fields>
24065                <field>
24066                  <name>F1SA</name>
24067                  <description>Rx FIFO 1 Start Address
24068Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Figure 2).</description>
24069                  <bitRange>[15:2]</bitRange>
24070                  <access>read-write</access>
24071                </field>
24072                <field>
24073                  <name>F1S</name>
24074                  <description>Rx FIFO 1 Size
240750= No Rx FIFO 1
240761-64= Number of Rx FIFO 1 elements
2407764= Values greater than 64 are interpreted as 64
24078The Rx FIFO 1 elements are indexed from 0 to F1S - 1</description>
24079                  <bitRange>[22:16]</bitRange>
24080                  <access>read-write</access>
24081                </field>
24082                <field>
24083                  <name>F1WM</name>
24084                  <description>Rx FIFO 1 Watermark
240850= Watermark interrupt disabled
240861-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W)
2408764= Watermark interrupt disabled</description>
24088                  <bitRange>[30:24]</bitRange>
24089                  <access>read-write</access>
24090                </field>
24091                <field>
24092                  <name>F1OM</name>
24093                  <description>FIFO 1 Operation Mode
24094FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2).
240950= FIFO 1 blocking mode
240961= FIFO 1 overwrite mode</description>
24097                  <bitRange>[31:31]</bitRange>
24098                  <access>read-write</access>
24099                </field>
24100              </fields>
24101            </register>
24102            <register>
24103              <name>RXF1S</name>
24104              <description>Rx FIFO 1 Status</description>
24105              <addressOffset>0xB4</addressOffset>
24106              <size>32</size>
24107              <access>read-only</access>
24108              <resetValue>0x0</resetValue>
24109              <resetMask>0xC33F3F7F</resetMask>
24110              <fields>
24111                <field>
24112                  <name>F1FL</name>
24113                  <description>Rx FIFO 1 Fill Level
24114Number of elements stored in Rx FIFO 1, range 0 to 64.
24115When the software reading the value immediately after writing to RXF1A.F1AI, this value should be read twice to ensure that the update is reflected.</description>
24116                  <bitRange>[6:0]</bitRange>
24117                  <access>read-only</access>
24118                </field>
24119                <field>
24120                  <name>F1GI</name>
24121                  <description>Rx FIFO 1 Get Index
24122Rx FIFO 1 read index pointer, range 0 to 63.
24123This field is updated by the software writing to RXF1A.F1AI.
24124When the software reading the value immediately after writing to RXF1A.F1AI, this value should be read twice to ensure that the update is reflected.</description>
24125                  <bitRange>[13:8]</bitRange>
24126                  <access>read-only</access>
24127                </field>
24128                <field>
24129                  <name>F1PI</name>
24130                  <description>Rx FIFO 1 Put Index
24131Rx FIFO 1 write index pointer, range 0 to 63.</description>
24132                  <bitRange>[21:16]</bitRange>
24133                  <access>read-only</access>
24134                </field>
24135                <field>
24136                  <name>F1F</name>
24137                  <description>Rx FIFO 1 Full
241380= Rx FIFO 1 not full
241391= Rx FIFO 1 full</description>
24140                  <bitRange>[24:24]</bitRange>
24141                  <access>read-only</access>
24142                </field>
24143                <field>
24144                  <name>RF1L</name>
24145                  <description>Rx FIFO 1 Message Lost
24146This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset.
241470= No Rx FIFO 1 message lost
241481= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero</description>
24149                  <bitRange>[25:25]</bitRange>
24150                  <access>read-only</access>
24151                </field>
24152                <field>
24153                  <name>DMS</name>
24154                  <description>Debug Message Status
2415500= Idle state, wait for reception of debug messages, DMA request is cleared
2415601= Debug message A received
2415710= Debug messages A, B received
2415811= Debug messages A, B, C received, DMA request is set</description>
24159                  <bitRange>[31:30]</bitRange>
24160                  <access>read-only</access>
24161                </field>
24162              </fields>
24163            </register>
24164            <register>
24165              <name>RXF1A</name>
24166              <description>Rx FIFO 1 Acknowledge</description>
24167              <addressOffset>0xB8</addressOffset>
24168              <size>32</size>
24169              <access>read-write</access>
24170              <resetValue>0x0</resetValue>
24171              <resetMask>0x3F</resetMask>
24172              <fields>
24173                <field>
24174                  <name>F1AI</name>
24175                  <description>Rx FIFO 1 Acknowledge Index
24176After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the
24177 buffer index of the last element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO 1 Get Index
24178 RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL.</description>
24179                  <bitRange>[5:0]</bitRange>
24180                  <access>read-write</access>
24181                </field>
24182              </fields>
24183            </register>
24184            <register>
24185              <name>RXESC</name>
24186              <description>Rx Buffer / FIFO Element Size Configuration</description>
24187              <addressOffset>0xBC</addressOffset>
24188              <size>32</size>
24189              <access>read-write</access>
24190              <resetValue>0x0</resetValue>
24191              <resetMask>0x777</resetMask>
24192              <fields>
24193                <field>
24194                  <name>F0DS</name>
24195                  <description>Rx FIFO 0 Data Field Size
24196000= 8 byte data field
24197001= 12 byte data field
24198010= 16 byte data field
24199011= 20 byte data field
24200100= 24 byte data field
24201101= 32 byte data field
24202110= 48 byte data field
24203111= 64 byte data field</description>
24204                  <bitRange>[2:0]</bitRange>
24205                  <access>read-write</access>
24206                </field>
24207                <field>
24208                  <name>F1DS</name>
24209                  <description>Rx FIFO 1 Data Field Size
24210000= 8 byte data field
24211001= 12 byte data field
24212010= 16 byte data field
24213011= 20 byte data field
24214100= 24 byte data field
24215101= 32 byte data field
24216110= 48 byte data field
24217111= 64 byte data field</description>
24218                  <bitRange>[6:4]</bitRange>
24219                  <access>read-write</access>
24220                </field>
24221                <field>
24222                  <name>RBDS</name>
24223                  <description>Rx Buffer Data Field Size
24224000= 8 byte data field
24225001= 12 byte data field
24226010= 16 byte data field
24227011= 20 byte data field
24228100= 24 byte data field
24229101= 32 byte data field
24230110= 48 byte data field
24231111= 64 byte data field</description>
24232                  <bitRange>[10:8]</bitRange>
24233                  <access>read-write</access>
24234                </field>
24235              </fields>
24236            </register>
24237            <register>
24238              <name>TXBC</name>
24239              <description>Tx Buffer Configuration</description>
24240              <addressOffset>0xC0</addressOffset>
24241              <size>32</size>
24242              <access>read-write</access>
24243              <resetValue>0x0</resetValue>
24244              <resetMask>0x7F3FFFFC</resetMask>
24245              <fields>
24246                <field>
24247                  <name>TBSA</name>
24248                  <description>Tx Buffers Start Address
24249Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2).</description>
24250                  <bitRange>[15:2]</bitRange>
24251                  <access>read-write</access>
24252                </field>
24253                <field>
24254                  <name>NDTB</name>
24255                  <description>Number of Dedicated Transmit Buffers
242560= No Dedicated Tx Buffers
242571-32= Number of Dedicated Tx Buffers
2425832= Values greater than 32 are interpreted as 32</description>
24259                  <bitRange>[21:16]</bitRange>
24260                  <access>read-write</access>
24261                </field>
24262                <field>
24263                  <name>TFQS</name>
24264                  <description>Transmit FIFO/Queue Size
242650= No Tx FIFO/Queue
242661-32= Number of Tx Buffers used for Tx FIFO/Queue
2426732= Values greater than 32 are interpreted as 32</description>
24268                  <bitRange>[29:24]</bitRange>
24269                  <access>read-write</access>
24270                </field>
24271                <field>
24272                  <name>TFQM</name>
24273                  <description>Tx FIFO/Queue Mode
242740= Tx FIFO operation
242751= Tx Queue operation</description>
24276                  <bitRange>[30:30]</bitRange>
24277                  <access>read-write</access>
24278                </field>
24279              </fields>
24280            </register>
24281            <register>
24282              <name>TXFQS</name>
24283              <description>Tx FIFO/Queue Status</description>
24284              <addressOffset>0xC4</addressOffset>
24285              <size>32</size>
24286              <access>read-only</access>
24287              <resetValue>0x0</resetValue>
24288              <resetMask>0x3F1F3F</resetMask>
24289              <fields>
24290                <field>
24291                  <name>TFFL</name>
24292                  <description>Tx FIFO Free Level
24293Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when
24294Tx Queue operation is configured (TXBC.TFQM = '1')</description>
24295                  <bitRange>[5:0]</bitRange>
24296                  <access>read-only</access>
24297                </field>
24298                <field>
24299                  <name>TFGI</name>
24300                  <description>Tx FIFO Get Index
24301Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured
24302TXBC.TFQM = '1').</description>
24303                  <bitRange>[12:8]</bitRange>
24304                  <access>read-only</access>
24305                </field>
24306                <field>
24307                  <name>TFQPI</name>
24308                  <description>Tx FIFO/Queue Put Index
24309Tx FIFO/Queue write index pointer, range 0 to 31.</description>
24310                  <bitRange>[20:16]</bitRange>
24311                  <access>read-only</access>
24312                </field>
24313                <field>
24314                  <name>TFQF</name>
24315                  <description>Tx FIFO/Queue Full
243160= Tx FIFO/Queue not full
243171= Tx FIFO/Queue full</description>
24318                  <bitRange>[21:21]</bitRange>
24319                  <access>read-only</access>
24320                </field>
24321              </fields>
24322            </register>
24323            <register>
24324              <name>TXESC</name>
24325              <description>Tx Buffer Element Size Configuration</description>
24326              <addressOffset>0xC8</addressOffset>
24327              <size>32</size>
24328              <access>read-write</access>
24329              <resetValue>0x0</resetValue>
24330              <resetMask>0x7</resetMask>
24331              <fields>
24332                <field>
24333                  <name>TBDS</name>
24334                  <description>Tx Buffer Data Field Size
24335000= 8 byte data field
24336001= 12 byte data field
24337010= 16 byte data field
24338011= 20 byte data field
24339100= 24 byte data field
24340101= 32 byte data field
24341110= 48 byte data field
24342111= 64 byte data field</description>
24343                  <bitRange>[2:0]</bitRange>
24344                  <access>read-write</access>
24345                </field>
24346              </fields>
24347            </register>
24348            <register>
24349              <name>TXBRP</name>
24350              <description>Tx Buffer Request Pending</description>
24351              <addressOffset>0xCC</addressOffset>
24352              <size>32</size>
24353              <access>read-only</access>
24354              <resetValue>0x0</resetValue>
24355              <resetMask>0xFFFFFFFF</resetMask>
24356              <fields>
24357                <field>
24358                  <name>TRP</name>
24359                  <description>Transmission Request Pending
24360Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.
24361The bits are reset after a requested transmission has completed or has been cancelled via register
24362TXBCR.
24363TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set,
24364a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the
24365highest priority (Tx Buffer with lowest Message ID).
24366A cancellation request resets the corresponding transmission request pending bit of register
24367TXBRP. In case a transmission has already been started when a cancellation is requested, this is
24368done at the end of the transmission, regardless whether the transmission was successful or not. The
24369cancellation request bits are reset directly after the corresponding TXBRP bit has been reset.
24370After a cancellation has been requested, a finished cancellation is signaled via TXBCF
24371after successful transmission together with the corresponding TXBTO bit
24372when the transmission has not yet been started at the point of cancellation
24373when the transmission has been aborted due to lost arbitration
24374when an error occurred during frame transmission
24375In DAR mode all transmissions are automatically cancelled if they are not successful. The
24376corresponding TXBCF bit is set for all unsuccessful transmissions.
243770= No transmission request pending
243781= Transmission request pending</description>
24379                  <bitRange>[31:0]</bitRange>
24380                  <access>read-only</access>
24381                </field>
24382              </fields>
24383            </register>
24384            <register>
24385              <name>TXBAR</name>
24386              <description>Tx Buffer Add Request</description>
24387              <addressOffset>0xD0</addressOffset>
24388              <size>32</size>
24389              <access>read-write</access>
24390              <resetValue>0x0</resetValue>
24391              <resetMask>0xFFFFFFFF</resetMask>
24392              <fields>
24393                <field>
24394                  <name>AR</name>
24395                  <description>Add Request
24396Each Tx Buffer has its own Add Request bit. Writing a '1' will set the corresponding Add Request
24397bit; writing a '0' has no impact. This enables the Host to set transmission requests for multiple Tx
24398Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC.
24399When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan
24400process has completed.
244010= No transmission request added
244021= Transmission requested added</description>
24403                  <bitRange>[31:0]</bitRange>
24404                  <access>read-write</access>
24405                </field>
24406              </fields>
24407            </register>
24408            <register>
24409              <name>TXBCR</name>
24410              <description>Tx Buffer Cancellation Request</description>
24411              <addressOffset>0xD4</addressOffset>
24412              <size>32</size>
24413              <access>read-write</access>
24414              <resetValue>0x0</resetValue>
24415              <resetMask>0xFFFFFFFF</resetMask>
24416              <fields>
24417                <field>
24418                  <name>CR</name>
24419                  <description>Cancellation Request
24420Each Tx Buffer has its own Cancellation Request bit. Writing a '1' will set the corresponding
24421Cancellation Request bit; writing a '0' has no impact. This enables the Host to set cancellation
24422requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx
24423Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset.
244240= No cancellation pending
244251= Cancellation pending</description>
24426                  <bitRange>[31:0]</bitRange>
24427                  <access>read-write</access>
24428                </field>
24429              </fields>
24430            </register>
24431            <register>
24432              <name>TXBTO</name>
24433              <description>Tx Buffer Transmission Occurred</description>
24434              <addressOffset>0xD8</addressOffset>
24435              <size>32</size>
24436              <access>read-only</access>
24437              <resetValue>0x0</resetValue>
24438              <resetMask>0xFFFFFFFF</resetMask>
24439              <fields>
24440                <field>
24441                  <name>TO</name>
24442                  <description>Transmission Occurred
24443Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding
24444TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission
24445is requested by writing a '1' to the corresponding bit of register TXBAR.
244460= No transmission occurred
244471= Transmission occurred</description>
24448                  <bitRange>[31:0]</bitRange>
24449                  <access>read-only</access>
24450                </field>
24451              </fields>
24452            </register>
24453            <register>
24454              <name>TXBCF</name>
24455              <description>Tx Buffer Cancellation Finished</description>
24456              <addressOffset>0xDC</addressOffset>
24457              <size>32</size>
24458              <access>read-only</access>
24459              <resetValue>0x0</resetValue>
24460              <resetMask>0xFFFFFFFF</resetMask>
24461              <fields>
24462                <field>
24463                  <name>CF</name>
24464                  <description>Cancellation Finished
24465Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding
24466TXBRP bit is cleared after a cancellation was requested via TXBCR. In case the corresponding
24467TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a
24468new transmission is requested by writing a '1' to the corresponding bit of register TXBAR.
244690= No transmit buffer cancellation
244701= Transmit buffer cancellation finished</description>
24471                  <bitRange>[31:0]</bitRange>
24472                  <access>read-only</access>
24473                </field>
24474              </fields>
24475            </register>
24476            <register>
24477              <name>TXBTIE</name>
24478              <description>Tx Buffer Transmission Interrupt Enable</description>
24479              <addressOffset>0xE0</addressOffset>
24480              <size>32</size>
24481              <access>read-write</access>
24482              <resetValue>0x0</resetValue>
24483              <resetMask>0xFFFFFFFF</resetMask>
24484              <fields>
24485                <field>
24486                  <name>TIE</name>
24487                  <description>Transmission Interrupt Enable
24488Each Tx Buffer has its own Transmission Interrupt Enable bit.
244890= Transmission interrupt disabled
244901= Transmission interrupt enable</description>
24491                  <bitRange>[31:0]</bitRange>
24492                  <access>read-write</access>
24493                </field>
24494              </fields>
24495            </register>
24496            <register>
24497              <name>TXBCIE</name>
24498              <description>Tx Buffer Cancellation Finished Interrupt Enable</description>
24499              <addressOffset>0xE4</addressOffset>
24500              <size>32</size>
24501              <access>read-write</access>
24502              <resetValue>0x0</resetValue>
24503              <resetMask>0xFFFFFFFF</resetMask>
24504              <fields>
24505                <field>
24506                  <name>CFIE</name>
24507                  <description>Cancellation Finished Interrupt Enable
24508Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit.
245090= Cancellation finished interrupt disabled
245101= Cancellation finished interrupt enabled</description>
24511                  <bitRange>[31:0]</bitRange>
24512                  <access>read-write</access>
24513                </field>
24514              </fields>
24515            </register>
24516            <register>
24517              <name>TXEFC</name>
24518              <description>Tx Event FIFO Configuration</description>
24519              <addressOffset>0xF0</addressOffset>
24520              <size>32</size>
24521              <access>read-write</access>
24522              <resetValue>0x0</resetValue>
24523              <resetMask>0x3F3FFFFC</resetMask>
24524              <fields>
24525                <field>
24526                  <name>EFSA</name>
24527                  <description>Event FIFO Start Address
24528Start address of Tx Event FIFO in Message RAM (32-bit word address, see Figure 2).</description>
24529                  <bitRange>[15:2]</bitRange>
24530                  <access>read-write</access>
24531                </field>
24532                <field>
24533                  <name>EFS</name>
24534                  <description>Event FIFO Size
245350= Tx Event FIFO disabled
245361-32= Number of Tx Event FIFO elements
2453732= Values greater than 32 are interpreted as 32
24538The Tx Event FIFO elements are indexed from 0 to EFS-1</description>
24539                  <bitRange>[21:16]</bitRange>
24540                  <access>read-write</access>
24541                </field>
24542                <field>
24543                  <name>EFWM</name>
24544                  <description>Event FIFO Watermark
245450= Watermark interrupt disabled
245461-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW)
2454732= Watermark interrupt disabled</description>
24548                  <bitRange>[29:24]</bitRange>
24549                  <access>read-write</access>
24550                </field>
24551              </fields>
24552            </register>
24553            <register>
24554              <name>TXEFS</name>
24555              <description>Tx Event FIFO Status</description>
24556              <addressOffset>0xF4</addressOffset>
24557              <size>32</size>
24558              <access>read-only</access>
24559              <resetValue>0x0</resetValue>
24560              <resetMask>0x31F1F3F</resetMask>
24561              <fields>
24562                <field>
24563                  <name>EFFL</name>
24564                  <description>Event FIFO Fill Level
24565Number of elements stored in Tx Event FIFO, range 0 to 32.
24566When the software reading the value immediately after writing to TXEFA.EFAI, this value should be read twice to ensure that the update is reflected.</description>
24567                  <bitRange>[5:0]</bitRange>
24568                  <access>read-only</access>
24569                </field>
24570                <field>
24571                  <name>EFGI</name>
24572                  <description>Event FIFO Get Index
24573Tx Event FIFO read index pointer, range 0 to 31.
24574This field is updated by the software writing to TXEFA.EFAI.
24575When the software reading the value immediately after writing to TXEFA.EFAI, this value should be read twice to ensure that the update is reflected.</description>
24576                  <bitRange>[12:8]</bitRange>
24577                  <access>read-only</access>
24578                </field>
24579                <field>
24580                  <name>EFPI</name>
24581                  <description>Event FIFO Put Index
24582Tx Event FIFO write index pointer, range 0 to 31.</description>
24583                  <bitRange>[20:16]</bitRange>
24584                  <access>read-only</access>
24585                </field>
24586                <field>
24587                  <name>EFF</name>
24588                  <description>Event FIFO Full
245890= Tx Event FIFO not full
245901= Tx Event FIFO full</description>
24591                  <bitRange>[24:24]</bitRange>
24592                  <access>read-only</access>
24593                </field>
24594                <field>
24595                  <name>TEFL</name>
24596                  <description>Tx Event FIFO Element Lost
24597This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset.
245980= No Tx Event FIFO element lost
245991= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero.</description>
24600                  <bitRange>[25:25]</bitRange>
24601                  <access>read-only</access>
24602                </field>
24603              </fields>
24604            </register>
24605            <register>
24606              <name>TXEFA</name>
24607              <description>Tx Event FIFO Acknowledge</description>
24608              <addressOffset>0xF8</addressOffset>
24609              <size>32</size>
24610              <access>read-write</access>
24611              <resetValue>0x0</resetValue>
24612              <resetMask>0x1F</resetMask>
24613              <fields>
24614                <field>
24615                  <name>EFAI</name>
24616                  <description>Event FIFO Acknowledge Index
24617After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write
24618the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get
24619Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL.</description>
24620                  <bitRange>[4:0]</bitRange>
24621                  <access>read-write</access>
24622                </field>
24623              </fields>
24624            </register>
24625            <register>
24626              <name>TTTMC</name>
24627              <description>TT Trigger Memory Configuration</description>
24628              <addressOffset>0x100</addressOffset>
24629              <size>32</size>
24630              <access>read-write</access>
24631              <resetValue>0x0</resetValue>
24632              <resetMask>0x7FFFFC</resetMask>
24633              <fields>
24634                <field>
24635                  <name>TMSA</name>
24636                  <description>Trigger Memory Start Address
24637Start address of Trigger Memory in Message RAM (32-bit word address, see Figure 2).</description>
24638                  <bitRange>[15:2]</bitRange>
24639                  <access>read-write</access>
24640                </field>
24641                <field>
24642                  <name>TME</name>
24643                  <description>Trigger Memory Elements
246440= No Trigger Memory
246451-64= Number of Trigger Memory elements
2464664= Values greater than 64 are interpreted as 64</description>
24647                  <bitRange>[22:16]</bitRange>
24648                  <access>read-write</access>
24649                </field>
24650              </fields>
24651            </register>
24652            <register>
24653              <name>TTRMC</name>
24654              <description>TT Reference Message Configuration</description>
24655              <addressOffset>0x104</addressOffset>
24656              <size>32</size>
24657              <access>read-write</access>
24658              <resetValue>0x0</resetValue>
24659              <resetMask>0xDFFFFFFF</resetMask>
24660              <fields>
24661                <field>
24662                  <name>RID</name>
24663                  <description>Reference Identifier
24664Identifier transmitted with reference message and used for reference message filtering. Standard or
24665extended reference identifier depending on bit XTD. A standard identifier has to be written to
24666ID[28:18].</description>
24667                  <bitRange>[28:0]</bitRange>
24668                  <access>read-write</access>
24669                </field>
24670                <field>
24671                  <name>XTD</name>
24672                  <description>Extended Identifier
246730= 11-bit standard identifier
246741= 29-bit extended identifier</description>
24675                  <bitRange>[30:30]</bitRange>
24676                  <access>read-write</access>
24677                </field>
24678                <field>
24679                  <name>RMPS</name>
24680                  <description>Reference Message Payload Select
24681Ignored in case of time slaves.
246820= Reference message has no additional payload
246831= The following elements are taken from Tx Buffer 0:
24684Message Marker MM, Event FIFO Control EFC, Data Length Code DLC, Data Bytes DB
24685Level 1: bytes 2-8, Level 0,2: bytes 5-8)</description>
24686                  <bitRange>[31:31]</bitRange>
24687                  <access>read-write</access>
24688                </field>
24689              </fields>
24690            </register>
24691            <register>
24692              <name>TTOCF</name>
24693              <description>TT Operation Configuration</description>
24694              <addressOffset>0x108</addressOffset>
24695              <size>32</size>
24696              <access>read-write</access>
24697              <resetValue>0x10000</resetValue>
24698              <resetMask>0x7FFFFFB</resetMask>
24699              <fields>
24700                <field>
24701                  <name>OM</name>
24702                  <description>Operation Mode
2470300= Event-driven CAN communication, default
2470401= TTCAN level 1
2470510= TTCAN level 2
2470611= TTCAN level 0</description>
24707                  <bitRange>[1:0]</bitRange>
24708                  <access>read-write</access>
24709                </field>
24710                <field>
24711                  <name>GEN</name>
24712                  <description>Gap Enable
247130= Strictly time-triggered operation
247141= External event-synchronized time-triggered operation</description>
24715                  <bitRange>[3:3]</bitRange>
24716                  <access>read-write</access>
24717                </field>
24718                <field>
24719                  <name>TM</name>
24720                  <description>Time Master
247210= Time Master function disabled
247221= Potential Time Master</description>
24723                  <bitRange>[4:4]</bitRange>
24724                  <access>read-write</access>
24725                </field>
24726                <field>
24727                  <name>LDSDL</name>
24728                  <description>LD of Synchronization Deviation Limit
24729The Synchronization Deviation Limit SDL is configured by its dual logarithm LDSDL with SDL =
247302(LDSDL + 5). It should not exceed the clock tolerance given by the CAN bit timing configuration.
247310x0-7 LD of Synchronization Deviation Limit (SDL &lt;= 32...4096)</description>
24732                  <bitRange>[7:5]</bitRange>
24733                  <access>read-write</access>
24734                </field>
24735                <field>
24736                  <name>IRTO</name>
24737                  <description>Initial Reference Trigger Offset
247380x00-7F Positive offset, range from 0 to 127</description>
24739                  <bitRange>[14:8]</bitRange>
24740                  <access>read-write</access>
24741                </field>
24742                <field>
24743                  <name>EECS</name>
24744                  <description>Enable External Clock Synchronization
24745If enabled, TUR configuration (TURCF.NCL only) may be updated during TTCAN operation.
247460= External clock synchronization in TTCAN Level 0,2 disabled
247471= External clock synchronization in TTCAN Level 0,2 enabled</description>
24748                  <bitRange>[15:15]</bitRange>
24749                  <access>read-write</access>
24750                </field>
24751                <field>
24752                  <name>AWL</name>
24753                  <description>Application Watchdog Limit
24754The application watchdog can be disabled by programming AWL to 0x00.
247550x00-FF Maximum time after which the application has to serve the application watchdog.
24756The application watchdog is incremented once each 256 NTUs.</description>
24757                  <bitRange>[23:16]</bitRange>
24758                  <access>read-write</access>
24759                </field>
24760                <field>
24761                  <name>EGTF</name>
24762                  <description>Enable Global Time Filtering
247630= Global time filtering in TTCAN Level 0,2 is disabled
247641= Global time filtering in TTCAN Level 0,2 is enabled</description>
24765                  <bitRange>[24:24]</bitRange>
24766                  <access>read-write</access>
24767                </field>
24768                <field>
24769                  <name>ECC</name>
24770                  <description>Enable Clock Calibration
247710= Automatic clock calibration in TTCAN Level 0,2 is disabled
247721= Automatic clock calibration in TTCAN Level 0,2 is enabled</description>
24773                  <bitRange>[25:25]</bitRange>
24774                  <access>read-write</access>
24775                </field>
24776                <field>
24777                  <name>EVTP</name>
24778                  <description>Event Trigger Polarity
247790= Rising edge trigger
247801= Falling edge trigger</description>
24781                  <bitRange>[26:26]</bitRange>
24782                  <access>read-write</access>
24783                </field>
24784              </fields>
24785            </register>
24786            <register>
24787              <name>TTMLM</name>
24788              <description>TT Matrix Limits</description>
24789              <addressOffset>0x10C</addressOffset>
24790              <size>32</size>
24791              <access>read-write</access>
24792              <resetValue>0x0</resetValue>
24793              <resetMask>0xFFF0FFF</resetMask>
24794              <fields>
24795                <field>
24796                  <name>CCM</name>
24797                  <description>N/A</description>
24798                  <bitRange>[5:0]</bitRange>
24799                  <access>read-write</access>
24800                </field>
24801                <field>
24802                  <name>CSS</name>
24803                  <description>N/A</description>
24804                  <bitRange>[7:6]</bitRange>
24805                  <access>read-write</access>
24806                </field>
24807                <field>
24808                  <name>TXEW</name>
24809                  <description>Tx Enable Window
248100x0-F Length of Tx enable window, 1-16 NTU cycles</description>
24811                  <bitRange>[11:8]</bitRange>
24812                  <access>read-write</access>
24813                </field>
24814                <field>
24815                  <name>ENTT</name>
24816                  <description>Expected Number of Tx Triggers
248170x000-FFF Expected number of Tx Triggers in one Matrix Cycle</description>
24818                  <bitRange>[27:16]</bitRange>
24819                  <access>read-write</access>
24820                </field>
24821              </fields>
24822            </register>
24823            <register>
24824              <name>TURCF</name>
24825              <description>TUR Configuration</description>
24826              <addressOffset>0x110</addressOffset>
24827              <size>32</size>
24828              <access>read-write</access>
24829              <resetValue>0x10000000</resetValue>
24830              <resetMask>0xBFFFFFFF</resetMask>
24831              <fields>
24832                <field>
24833                  <name>NCL</name>
24834                  <description>Numerator Configuration Low
24835Write access to the TUR Numerator Configuration Low is only possible during configuration with
24836TURCF.ELT = '0' or if TTOCF.EECS (external clock synchronization enabled) is set. When a new
24837value for NCL is written outside TT Configuration Mode, the new value takes effect when
24838TTOST.WECS is cleared to '0'. NCL is locked TTOST.WECS is '1'.
248390x0000-FFFF Numerator Configuration Low</description>
24840                  <bitRange>[15:0]</bitRange>
24841                  <access>read-write</access>
24842                </field>
24843                <field>
24844                  <name>DC</name>
24845                  <description>Denominator Configuration
248460x0000 Illegal value
248470x0001-3FFF Denominator Configuration</description>
24848                  <bitRange>[29:16]</bitRange>
24849                  <access>read-write</access>
24850                </field>
24851                <field>
24852                  <name>ELT</name>
24853                  <description>Enable Local Time
248540= Local time is stopped, default
248551= Local time is enabled</description>
24856                  <bitRange>[31:31]</bitRange>
24857                  <access>read-write</access>
24858                </field>
24859              </fields>
24860            </register>
24861            <register>
24862              <name>TTOCN</name>
24863              <description>TT Operation Control</description>
24864              <addressOffset>0x114</addressOffset>
24865              <size>32</size>
24866              <access>read-write</access>
24867              <resetValue>0x0</resetValue>
24868              <resetMask>0xBFFF</resetMask>
24869              <fields>
24870                <field>
24871                  <name>SGT</name>
24872                  <description>Set Global time
24873Writing a '1' to SGT sets TTOST.WGDT if the node is the actual Time Master. SGT is reset after one
24874Host clock period. The global time preset takes effect when the node transmits the next reference
24875message with the Master_Ref_Mark modified by the preset value written to TTGTP.</description>
24876                  <bitRange>[0:0]</bitRange>
24877                  <access>read-write</access>
24878                </field>
24879                <field>
24880                  <name>ECS</name>
24881                  <description>External Clock Synchronization
24882Writing a '1' to ECS sets TTOST.WECS if the node is the actual Time Master. ECS is reset after one
24883Host clock period. The external clock synchronization takes effect at the start of the next basic cycle.</description>
24884                  <bitRange>[1:1]</bitRange>
24885                  <access>read-write</access>
24886                </field>
24887                <field>
24888                  <name>SWP</name>
24889                  <description>Stop Watch Polarity
248900= Rising edge trigger
248911= Falling edge trigger</description>
24892                  <bitRange>[2:2]</bitRange>
24893                  <access>read-write</access>
24894                </field>
24895                <field>
24896                  <name>SWS</name>
24897                  <description>Stop Watch Source
2489800= Stop Watch disabled
2489901= Actual value of cycle time is copied to TTCPT.SWV
2490010= Actual value of local time is copied to TTCPT.SWV
2490111= Actual value of global time is copied to TTCPT.SWV</description>
24902                  <bitRange>[4:3]</bitRange>
24903                  <access>read-write</access>
24904                </field>
24905                <field>
24906                  <name>RTIE</name>
24907                  <description>Register Time Mark Interrupt Pulse Enable
24908Register time mark interrupts are configured by register TTTMK. A register time mark interrupt pulse
24909with the length of one NTU is generated when the time referenced by TTOCN.TMC (cycle, local, or
24910global) equals TTTMK.TM, independent of the synchronization state.
249110= Register Time Mark Interrupt output m_ttcan_rtp disabled
249121= Register Time Mark Interrupt output m_ttcan_rtp enabled</description>
24913                  <bitRange>[5:5]</bitRange>
24914                  <access>read-write</access>
24915                </field>
24916                <field>
24917                  <name>TMC</name>
24918                  <description>Register Time Mark Compare
2491900= No Register Time Mark Interrupt generated
2492001= Register Time Mark Interrupt if Time Mark = cycle time
2492110= Register Time Mark Interrupt if Time Mark = local time
2492211= Register Time Mark Interrupt if Time Mark = global time</description>
24923                  <bitRange>[7:6]</bitRange>
24924                  <access>read-write</access>
24925                </field>
24926                <field>
24927                  <name>TTIE</name>
24928                  <description>Trigger Time Mark Interrupt Pulse Enable
24929External time mark events are configured by trigger memory element TMEX (see Section 2.4.7). A
24930trigger time mark interrupt pulse is generated when the trigger memory element becomes active,
24931and the M_TTCAN is in synchronization state In_Schedule or In_Gap.
249320= Trigger Time Mark Interrupt output m_ttcan_tmp disabled
249331= Trigger Time Mark Interrupt output m_ttcan_tmp enabled</description>
24934                  <bitRange>[8:8]</bitRange>
24935                  <access>read-write</access>
24936                </field>
24937                <field>
24938                  <name>GCS</name>
24939                  <description>Gap Control Select
249400= Gap control independent from m_ttcan_evt
249411= Gap control by input pin m_ttcan_evt</description>
24942                  <bitRange>[9:9]</bitRange>
24943                  <access>read-write</access>
24944                </field>
24945                <field>
24946                  <name>FGP</name>
24947                  <description>Finish Gap
24948Set by the CPU, reset by each reference message
249490= No reference message requested
249501= Application requested start of reference message</description>
24951                  <bitRange>[10:10]</bitRange>
24952                  <access>read-write</access>
24953                </field>
24954                <field>
24955                  <name>TMG</name>
24956                  <description>Time Mark Gap
249570= Reset by each reference message
249581= Next reference message started when Register Time Mark interrupt TTIR.RTMI is activated</description>
24959                  <bitRange>[11:11]</bitRange>
24960                  <access>read-write</access>
24961                </field>
24962                <field>
24963                  <name>NIG</name>
24964                  <description>Next is Gap
24965This bit can only be set when the M_TTCAN is the actual Time Master and when it is configured for
24966external event-synchronized time-triggered operation (TTOCF.GEN = '1')
249670= No action, reset by reception of any reference message
249681= Transmit next reference message with Next_is_Gap = '1'</description>
24969                  <bitRange>[12:12]</bitRange>
24970                  <access>read-write</access>
24971                </field>
24972                <field>
24973                  <name>ESCN</name>
24974                  <description>External Synchronization Control
24975If enabled the M_TTCAN synchronizes its cycle time phase to an external event signaled by a rising
24976edge at pin m_ttcan_evt (see Section 4.11).
249770= External synchronization disabled
249781= External synchronization enabled</description>
24979                  <bitRange>[13:13]</bitRange>
24980                  <access>read-write</access>
24981                </field>
24982                <field>
24983                  <name>LCKC</name>
24984                  <description>TT Operation Control Register Locked
24985Set by a write access to register TTOCN. Reset when the updated configuration has been
24986synchronized into the CAN clock domain.
249870= Write access to TTOCN enabled
249881= Write access to TTOCN locked</description>
24989                  <bitRange>[15:15]</bitRange>
24990                  <access>read-only</access>
24991                </field>
24992              </fields>
24993            </register>
24994            <register>
24995              <name>TTGTP</name>
24996              <description>TT Global Time Preset</description>
24997              <addressOffset>0x118</addressOffset>
24998              <size>32</size>
24999              <access>read-write</access>
25000              <resetValue>0x0</resetValue>
25001              <resetMask>0xFFFFFFFF</resetMask>
25002              <fields>
25003                <field>
25004                  <name>TP</name>
25005                  <description>N/A</description>
25006                  <bitRange>[15:0]</bitRange>
25007                  <access>read-write</access>
25008                </field>
25009                <field>
25010                  <name>CTP</name>
25011                  <description>Cycle Time Target Phase
25012CTP is write-protected while TTOCN.ESCN or TTOST.SPL are set (see Section 4.11).
250130x0000-FFFF Defines target value of cycle time when a rising edge of m_ttcan_evt is expected</description>
25014                  <bitRange>[31:16]</bitRange>
25015                  <access>read-write</access>
25016                </field>
25017              </fields>
25018            </register>
25019            <register>
25020              <name>TTTMK</name>
25021              <description>TT Time Mark</description>
25022              <addressOffset>0x11C</addressOffset>
25023              <size>32</size>
25024              <access>read-write</access>
25025              <resetValue>0x0</resetValue>
25026              <resetMask>0x807FFFFF</resetMask>
25027              <fields>
25028                <field>
25029                  <name>TM_</name>
25030                  <description>Time Mark
250310x0000-FFFF Time Mark</description>
25032                  <bitRange>[15:0]</bitRange>
25033                  <access>read-write</access>
25034                </field>
25035                <field>
25036                  <name>TICC</name>
25037                  <description>Time Mark Cycle Code
25038Cycle count for which the time mark is valid.
250390b000000x valid for all cycles
250400b000001c valid every second cycle at cycle count mod2 = c
250410b00001cc valid every fourth cycle at cycle count mod4 = cc
250420b0001ccc valid every eighth cycle at cycle count mod8 = ccc
250430b001cccc valid every sixteenth cycle at cycle count mod16 = cccc
250440b01ccccc valid every thirty-second cycle at cycle count mod32 = ccccc
250450b1cccccc valid every sixty-fourth cycle at cycle count mod64 = cccccc</description>
25046                  <bitRange>[22:16]</bitRange>
25047                  <access>read-write</access>
25048                </field>
25049                <field>
25050                  <name>LCKM</name>
25051                  <description>TT Time Mark Register Locked
25052Always set by a write access to registers TTOCN. Set by write access to register TTTMK when
25053TTOCN.TMC != '00'. Reset when the registers have been synchronized into the CAN clock domain.
250540= Write access to TTTMK enabled
250551= Write access to TTTMK locked</description>
25056                  <bitRange>[31:31]</bitRange>
25057                  <access>read-only</access>
25058                </field>
25059              </fields>
25060            </register>
25061            <register>
25062              <name>TTIR</name>
25063              <description>TT Interrupt Register</description>
25064              <addressOffset>0x120</addressOffset>
25065              <size>32</size>
25066              <access>read-write</access>
25067              <resetValue>0x0</resetValue>
25068              <resetMask>0x7FFFF</resetMask>
25069              <fields>
25070                <field>
25071                  <name>SBC</name>
25072                  <description>Start of Basic Cycle
250730= No Basic Cycle started since bit has been reset
250741= Basic Cycle started</description>
25075                  <bitRange>[0:0]</bitRange>
25076                  <access>read-write</access>
25077                </field>
25078                <field>
25079                  <name>SMC</name>
25080                  <description>Start of Matrix Cycle
250810= No Matrix Cycle started since bit has been reset
250821= Matrix Cycle started</description>
25083                  <bitRange>[1:1]</bitRange>
25084                  <access>read-write</access>
25085                </field>
25086                <field>
25087                  <name>CSM_</name>
25088                  <description>Change of Synchronization Mode
250890= No change in master to slave relation or schedule synchronization
250901= Master to slave relation or schedule synchronization changed,
25091also set when TTOST.SPL is reset</description>
25092                  <bitRange>[2:2]</bitRange>
25093                  <access>read-write</access>
25094                </field>
25095                <field>
25096                  <name>SOG</name>
25097                  <description>Start of Gap
250980= No reference message seen with Next_is_Gap bit set
250991= Reference message with Next_is_Gap bit set becomes valid</description>
25100                  <bitRange>[3:3]</bitRange>
25101                  <access>read-write</access>
25102                </field>
25103                <field>
25104                  <name>RTMI</name>
25105                  <description>Register Time Mark Interrupt
25106Set when time referenced by TTOCN.TMC (cycle, local, or global) equals TTTMK.TM, independent
25107of the synchronization state.
251080= Time mark not reached
251091= Time mark reached</description>
25110                  <bitRange>[4:4]</bitRange>
25111                  <access>read-write</access>
25112                </field>
25113                <field>
25114                  <name>TTMI</name>
25115                  <description>Trigger Time Mark Event Internal
25116Internal time mark events are configured by trigger memory element TMIN (see Section 2.4.7). Set
25117when the trigger memory element becomes active, and the M_TTCAN is in synchronization state
25118In_Gap or In_Schedule.
251190= Time mark not reached
251201= Time mark reached (Level 0: cycle time TTOCF.IRTO * 0x200)</description>
25121                  <bitRange>[5:5]</bitRange>
25122                  <access>read-write</access>
25123                </field>
25124                <field>
25125                  <name>SWE</name>
25126                  <description>Stop Watch Event
251270= No rising/falling edge at stop watch trigger pin m_ttcan_swt detected
251281= Rising/falling edge at stop watch trigger pin m_ttcan_swt detected</description>
25129                  <bitRange>[6:6]</bitRange>
25130                  <access>read-write</access>
25131                </field>
25132                <field>
25133                  <name>GTW</name>
25134                  <description>Global Time Wrap
251350= No global time wrap occurred
251361= Global time wrap from 0xFFFF to 0x0000 occurred</description>
25137                  <bitRange>[7:7]</bitRange>
25138                  <access>read-write</access>
25139                </field>
25140                <field>
25141                  <name>GTD</name>
25142                  <description>Global Time Discontinuity
251430= No discontinuity of global time
251441= Discontinuity of global time</description>
25145                  <bitRange>[8:8]</bitRange>
25146                  <access>read-write</access>
25147                </field>
25148                <field>
25149                  <name>GTE</name>
25150                  <description>Global Time Error
25151Synchronization deviation SD exceeds limit specified by TTOCF.LDSDL, TTCAN Level 0,2 only.
251520= Synchronization deviation within limit
251531= Synchronization deviation exceeded limit</description>
25154                  <bitRange>[9:9]</bitRange>
25155                  <access>read-write</access>
25156                </field>
25157                <field>
25158                  <name>TXU</name>
25159                  <description>Tx Count Underflow
251600= Number of Tx Trigger as expected
251611= Less Tx trigger than expected in one matrix cycle</description>
25162                  <bitRange>[10:10]</bitRange>
25163                  <access>read-write</access>
25164                </field>
25165                <field>
25166                  <name>TXO</name>
25167                  <description>Tx Count Overflow
251680= Number of Tx Trigger as expected
251691= More Tx trigger than expected in one matrix cycle</description>
25170                  <bitRange>[11:11]</bitRange>
25171                  <access>read-write</access>
25172                </field>
25173                <field>
25174                  <name>SE1</name>
25175                  <description>Scheduling Error 1
251760= No scheduling error 1
251771= Scheduling error 1 occurred</description>
25178                  <bitRange>[12:12]</bitRange>
25179                  <access>read-write</access>
25180                </field>
25181                <field>
25182                  <name>SE2</name>
25183                  <description>Scheduling Error 2
251840= No scheduling error 2
251851= Scheduling error 2 occurred</description>
25186                  <bitRange>[13:13]</bitRange>
25187                  <access>read-write</access>
25188                </field>
25189                <field>
25190                  <name>ELC</name>
25191                  <description>Error Level Changed
25192Not set when error level changed during initialization.
251930= No change in error level
251941= Error level changed</description>
25195                  <bitRange>[14:14]</bitRange>
25196                  <access>read-write</access>
25197                </field>
25198                <field>
25199                  <name>IWT</name>
25200                  <description>Initialization Watch Trigger
25201The initialization is restarted by resetting IWT.
252020= No missing reference message during system startup
252031= No system startup due to missing reference message</description>
25204                  <bitRange>[15:15]</bitRange>
25205                  <access>read-write</access>
25206                </field>
25207                <field>
25208                  <name>WT</name>
25209                  <description>Watch Trigger
252100= No missing reference message
252111= Missing reference message (Level 0: cycle time 0xFF00)</description>
25212                  <bitRange>[16:16]</bitRange>
25213                  <access>read-write</access>
25214                </field>
25215                <field>
25216                  <name>AW</name>
25217                  <description>Application Watchdog
252180= Application watchdog served in time
252191= Application watchdog not served in time</description>
25220                  <bitRange>[17:17]</bitRange>
25221                  <access>read-write</access>
25222                </field>
25223                <field>
25224                  <name>CER</name>
25225                  <description>Configuration Error
25226Trigger out of order.
252270= No error found in trigger list
252281= Error found in trigger list</description>
25229                  <bitRange>[18:18]</bitRange>
25230                  <access>read-write</access>
25231                </field>
25232              </fields>
25233            </register>
25234            <register>
25235              <name>TTIE</name>
25236              <description>TT Interrupt Enable</description>
25237              <addressOffset>0x124</addressOffset>
25238              <size>32</size>
25239              <access>read-write</access>
25240              <resetValue>0x0</resetValue>
25241              <resetMask>0x7FFFF</resetMask>
25242              <fields>
25243                <field>
25244                  <name>SBCE</name>
25245                  <description>Start of Basic Cycle Interrupt Enable</description>
25246                  <bitRange>[0:0]</bitRange>
25247                  <access>read-write</access>
25248                </field>
25249                <field>
25250                  <name>SMCE</name>
25251                  <description>Start of Matrix Cycle Interrupt Enable</description>
25252                  <bitRange>[1:1]</bitRange>
25253                  <access>read-write</access>
25254                </field>
25255                <field>
25256                  <name>CSME</name>
25257                  <description>Change of Synchronization Mode Interrupt Enable</description>
25258                  <bitRange>[2:2]</bitRange>
25259                  <access>read-write</access>
25260                </field>
25261                <field>
25262                  <name>SOGE</name>
25263                  <description>Start of Gap Interrupt Enable</description>
25264                  <bitRange>[3:3]</bitRange>
25265                  <access>read-write</access>
25266                </field>
25267                <field>
25268                  <name>RTMIE</name>
25269                  <description>Register Time Mark Interrupt Enable</description>
25270                  <bitRange>[4:4]</bitRange>
25271                  <access>read-write</access>
25272                </field>
25273                <field>
25274                  <name>TTMIE</name>
25275                  <description>Trigger Time Mark Event Internal Enable</description>
25276                  <bitRange>[5:5]</bitRange>
25277                  <access>read-write</access>
25278                </field>
25279                <field>
25280                  <name>SWEE</name>
25281                  <description>Stop Watch Event Interrupt Enable</description>
25282                  <bitRange>[6:6]</bitRange>
25283                  <access>read-write</access>
25284                </field>
25285                <field>
25286                  <name>GTWE</name>
25287                  <description>Global Time Wrap Interrupt Enable</description>
25288                  <bitRange>[7:7]</bitRange>
25289                  <access>read-write</access>
25290                </field>
25291                <field>
25292                  <name>GTDE</name>
25293                  <description>Global Time Discontinuity Interrupt Enable</description>
25294                  <bitRange>[8:8]</bitRange>
25295                  <access>read-write</access>
25296                </field>
25297                <field>
25298                  <name>GTEE</name>
25299                  <description>Global Time Error Interrupt Enable</description>
25300                  <bitRange>[9:9]</bitRange>
25301                  <access>read-write</access>
25302                </field>
25303                <field>
25304                  <name>TXUE</name>
25305                  <description>Tx Count Underflow Interrupt Enable</description>
25306                  <bitRange>[10:10]</bitRange>
25307                  <access>read-write</access>
25308                </field>
25309                <field>
25310                  <name>TXOE</name>
25311                  <description>Tx Count Overflow Interrupt Enable</description>
25312                  <bitRange>[11:11]</bitRange>
25313                  <access>read-write</access>
25314                </field>
25315                <field>
25316                  <name>SE1E</name>
25317                  <description>Scheduling Error 1 Interrupt Enable</description>
25318                  <bitRange>[12:12]</bitRange>
25319                  <access>read-write</access>
25320                </field>
25321                <field>
25322                  <name>SE2E</name>
25323                  <description>Scheduling Error 2 Interrupt Enable</description>
25324                  <bitRange>[13:13]</bitRange>
25325                  <access>read-write</access>
25326                </field>
25327                <field>
25328                  <name>ELCE</name>
25329                  <description>Change Error Level Interrupt Enable</description>
25330                  <bitRange>[14:14]</bitRange>
25331                  <access>read-write</access>
25332                </field>
25333                <field>
25334                  <name>IWTE</name>
25335                  <description>Initialization Watch Trigger Interrupt Enable</description>
25336                  <bitRange>[15:15]</bitRange>
25337                  <access>read-write</access>
25338                </field>
25339                <field>
25340                  <name>WTE</name>
25341                  <description>Watch Trigger Interrupt Enable</description>
25342                  <bitRange>[16:16]</bitRange>
25343                  <access>read-write</access>
25344                </field>
25345                <field>
25346                  <name>AWE_</name>
25347                  <description>Application Watchdog Interrupt Enable</description>
25348                  <bitRange>[17:17]</bitRange>
25349                  <access>read-write</access>
25350                </field>
25351                <field>
25352                  <name>CERE</name>
25353                  <description>Configuration Error Interrupt Enable</description>
25354                  <bitRange>[18:18]</bitRange>
25355                  <access>read-write</access>
25356                </field>
25357              </fields>
25358            </register>
25359            <register>
25360              <name>TTILS</name>
25361              <description>TT Interrupt Line Select</description>
25362              <addressOffset>0x128</addressOffset>
25363              <size>32</size>
25364              <access>read-write</access>
25365              <resetValue>0x0</resetValue>
25366              <resetMask>0x7FFFF</resetMask>
25367              <fields>
25368                <field>
25369                  <name>SBCL</name>
25370                  <description>Start of Basic Cycle Interrupt Line</description>
25371                  <bitRange>[0:0]</bitRange>
25372                  <access>read-write</access>
25373                </field>
25374                <field>
25375                  <name>SMCL</name>
25376                  <description>Start of Matrix Cycle Interrupt Line</description>
25377                  <bitRange>[1:1]</bitRange>
25378                  <access>read-write</access>
25379                </field>
25380                <field>
25381                  <name>CSML</name>
25382                  <description>Change of Synchronization Mode Interrupt Line</description>
25383                  <bitRange>[2:2]</bitRange>
25384                  <access>read-write</access>
25385                </field>
25386                <field>
25387                  <name>SOGL</name>
25388                  <description>Start of Gap Interrupt Line</description>
25389                  <bitRange>[3:3]</bitRange>
25390                  <access>read-write</access>
25391                </field>
25392                <field>
25393                  <name>RTMIL</name>
25394                  <description>Register Time Mark Interrupt Line</description>
25395                  <bitRange>[4:4]</bitRange>
25396                  <access>read-write</access>
25397                </field>
25398                <field>
25399                  <name>TTMIL</name>
25400                  <description>Trigger Time Mark Event Internal Line</description>
25401                  <bitRange>[5:5]</bitRange>
25402                  <access>read-write</access>
25403                </field>
25404                <field>
25405                  <name>SWEL</name>
25406                  <description>Stop Watch Event Interrupt Line</description>
25407                  <bitRange>[6:6]</bitRange>
25408                  <access>read-write</access>
25409                </field>
25410                <field>
25411                  <name>GTWL</name>
25412                  <description>Global Time Wrap Interrupt Line</description>
25413                  <bitRange>[7:7]</bitRange>
25414                  <access>read-write</access>
25415                </field>
25416                <field>
25417                  <name>GTDL</name>
25418                  <description>Global Time Discontinuity Interrupt Line</description>
25419                  <bitRange>[8:8]</bitRange>
25420                  <access>read-write</access>
25421                </field>
25422                <field>
25423                  <name>GTEL</name>
25424                  <description>Global Time Error Interrupt Line</description>
25425                  <bitRange>[9:9]</bitRange>
25426                  <access>read-write</access>
25427                </field>
25428                <field>
25429                  <name>TXUL</name>
25430                  <description>Tx Count Underflow Interrupt Line</description>
25431                  <bitRange>[10:10]</bitRange>
25432                  <access>read-write</access>
25433                </field>
25434                <field>
25435                  <name>TXOL</name>
25436                  <description>Tx Count Overflow Interrupt Line</description>
25437                  <bitRange>[11:11]</bitRange>
25438                  <access>read-write</access>
25439                </field>
25440                <field>
25441                  <name>SE1L</name>
25442                  <description>Scheduling Error 1 Interrupt Line</description>
25443                  <bitRange>[12:12]</bitRange>
25444                  <access>read-write</access>
25445                </field>
25446                <field>
25447                  <name>SE2L</name>
25448                  <description>Scheduling Error 2 Interrupt Line</description>
25449                  <bitRange>[13:13]</bitRange>
25450                  <access>read-write</access>
25451                </field>
25452                <field>
25453                  <name>ELCL</name>
25454                  <description>Change Error Level Interrupt Line</description>
25455                  <bitRange>[14:14]</bitRange>
25456                  <access>read-write</access>
25457                </field>
25458                <field>
25459                  <name>IWTL</name>
25460                  <description>Initialization Watch Trigger Interrupt Line</description>
25461                  <bitRange>[15:15]</bitRange>
25462                  <access>read-write</access>
25463                </field>
25464                <field>
25465                  <name>WTL</name>
25466                  <description>Watch Trigger Interrupt Line</description>
25467                  <bitRange>[16:16]</bitRange>
25468                  <access>read-write</access>
25469                </field>
25470                <field>
25471                  <name>AWL_</name>
25472                  <description>Application Watchdog Interrupt Line</description>
25473                  <bitRange>[17:17]</bitRange>
25474                  <access>read-write</access>
25475                </field>
25476                <field>
25477                  <name>CERL</name>
25478                  <description>Configuration Error Interrupt Line</description>
25479                  <bitRange>[18:18]</bitRange>
25480                  <access>read-write</access>
25481                </field>
25482              </fields>
25483            </register>
25484            <register>
25485              <name>TTOST</name>
25486              <description>TT Operation Status</description>
25487              <addressOffset>0x12C</addressOffset>
25488              <size>32</size>
25489              <access>read-only</access>
25490              <resetValue>0x80</resetValue>
25491              <resetMask>0xFFC0FFFF</resetMask>
25492              <fields>
25493                <field>
25494                  <name>EL</name>
25495                  <description>Error Level
2549600= Severity 0 - No Error
2549701= Severity 1 - Warning
2549810= Severity 2 - Error
2549911= Severity 3 - Severe Error</description>
25500                  <bitRange>[1:0]</bitRange>
25501                  <access>read-only</access>
25502                </field>
25503                <field>
25504                  <name>MS</name>
25505                  <description>Master State
2550600= Master_Off, no master properties relevant
2550701= Operating as Time Slave
2550810= Operating as Backup Time Master
2550911= Operating as current Time Master</description>
25510                  <bitRange>[3:2]</bitRange>
25511                  <access>read-only</access>
25512                </field>
25513                <field>
25514                  <name>SYS</name>
25515                  <description>Synchronization State
2551600= Out of Synchronization
2551701= Synchronizing to TTCAN communication
2551810= Schedule suspended by Gap (In_Gap)
2551911= Synchronized to schedule (In_Schedule)</description>
25520                  <bitRange>[5:4]</bitRange>
25521                  <access>read-only</access>
25522                </field>
25523                <field>
25524                  <name>QGTP</name>
25525                  <description>Quality of Global Time Phase
25526Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '0'.
255270= Global time not valid
255281= Global time in phase with Time Master</description>
25529                  <bitRange>[6:6]</bitRange>
25530                  <access>read-only</access>
25531                </field>
25532                <field>
25533                  <name>QCS</name>
25534                  <description>Quality of Clock Speed
25535Only relevant in TTCAN Level 0 and Level 2, otherwise fixed to '1'.
255360= Local clock speed not synchronized to Time Master clock speed
255371= Synchronization Deviation &lt;= SDL</description>
25538                  <bitRange>[7:7]</bitRange>
25539                  <access>read-only</access>
25540                </field>
25541                <field>
25542                  <name>RTO</name>
25543                  <description>Reference Trigger Offset
25544The Reference Trigger Offset value is a signed integer with a range from -127 (0x81) to 127 (0x7F).
25545There is no notification when the lower limit of -127 is reached. In case the M_TTCAN becomes
25546Time Master (MS[1:0] = '11'), the reset of RTO is delayed due to synchronization between Host and
25547CAN clock domain. For time slaves the value configured by TTOCF.IRTO is read.
255480x00-FF Actual Reference Trigger offset value</description>
25549                  <bitRange>[15:8]</bitRange>
25550                  <access>read-only</access>
25551                </field>
25552                <field>
25553                  <name>WGTD</name>
25554                  <description>Wait for Global Time Discontinuity
255550= No global time preset pending
255561= Node waits for the global time preset to take effect. The bit is reset when the node has transmitted
25557a reference message with Disc_Bit = '1' or after it received a reference message.</description>
25558                  <bitRange>[22:22]</bitRange>
25559                  <access>read-only</access>
25560                </field>
25561                <field>
25562                  <name>GFI</name>
25563                  <description>Gap Finished Indicator
25564Set when the CPU writes TTOCN.FGP, or by a time mark interrupt if TMG = '1', or via input pin
25565m_ttcan_evt if TTOCN.GCS = '1'. Not set by Ref_Trigger_Gap or when Gap is finished by another
25566node sending a reference message.
255670= Reset at the end of each reference message
255681= Gap finished by M_TTCAN</description>
25569                  <bitRange>[23:23]</bitRange>
25570                  <access>read-only</access>
25571                </field>
25572                <field>
25573                  <name>TMP</name>
25574                  <description>Time Master Priority
255750x0-7 Priority of actual Time Master</description>
25576                  <bitRange>[26:24]</bitRange>
25577                  <access>read-only</access>
25578                </field>
25579                <field>
25580                  <name>GSI</name>
25581                  <description>Gap Started Indicator
255820= No Gap in schedule, reset by each reference message and for all time slaves
255831= Gap time after Basic Cycle has started</description>
25584                  <bitRange>[27:27]</bitRange>
25585                  <access>read-only</access>
25586                </field>
25587                <field>
25588                  <name>WFE</name>
25589                  <description>Wait for Event
255900= No Gap announced, reset by a reference message with Next_is_Gap = '0'
255911= Reference message with Next_is_Gap = '1' received</description>
25592                  <bitRange>[28:28]</bitRange>
25593                  <access>read-only</access>
25594                </field>
25595                <field>
25596                  <name>AWE</name>
25597                  <description>Application Watchdog Event
25598The application watchdog is served by reading TTOST. When the watchdog is not served in time,
25599bit AWE is set, all TTCAN communication is stopped, and the M_TTCAN is set into Bus Monitoring
25600Mode.
256010= Application Watchdog served in time
256021= Failed to serve Application Watchdog in time</description>
25603                  <bitRange>[29:29]</bitRange>
25604                  <access>read-only</access>
25605                </field>
25606                <field>
25607                  <name>WECS</name>
25608                  <description>Wait for External Clock Synchronization
256090= No external clock synchronization pending
256101= Node waits for external clock synchronization to take effect. The bit is reset at the start of the
25611next basic cycle.</description>
25612                  <bitRange>[30:30]</bitRange>
25613                  <access>read-only</access>
25614                </field>
25615                <field>
25616                  <name>SPL</name>
25617                  <description>Schedule Phase Lock
25618The bit is valid only when external synchronization is enabled (TTOCN.ESCN = '1'). In this case it
25619signals that the difference between cycle time configured by TTGTP.CTP and the cycle time at the
25620rising edge at pin m_ttcan_evt is less or equal 9 NTU (see Section 4.11).
256210= Phase outside range
256221= Phase inside range</description>
25623                  <bitRange>[31:31]</bitRange>
25624                  <access>read-only</access>
25625                </field>
25626              </fields>
25627            </register>
25628            <register>
25629              <name>TURNA</name>
25630              <description>TUR Numerator Actual</description>
25631              <addressOffset>0x130</addressOffset>
25632              <size>32</size>
25633              <access>read-only</access>
25634              <resetValue>0x10000</resetValue>
25635              <resetMask>0x3FFFF</resetMask>
25636              <fields>
25637                <field>
25638                  <name>NAV</name>
25639                  <description>N/A</description>
25640                  <bitRange>[17:0]</bitRange>
25641                  <access>read-only</access>
25642                </field>
25643              </fields>
25644            </register>
25645            <register>
25646              <name>TTLGT</name>
25647              <description>TT Local &amp; Global Time</description>
25648              <addressOffset>0x134</addressOffset>
25649              <size>32</size>
25650              <access>read-only</access>
25651              <resetValue>0x0</resetValue>
25652              <resetMask>0xFFFFFFFF</resetMask>
25653              <fields>
25654                <field>
25655                  <name>LT</name>
25656                  <description>Local Time
25657Non-fractional part of local time, incremented once each local NTU (see Section 4.5).
256580x0000-FFFF Local time value of TTCAN node</description>
25659                  <bitRange>[15:0]</bitRange>
25660                  <access>read-only</access>
25661                </field>
25662                <field>
25663                  <name>GT</name>
25664                  <description>Global Time
25665Non-fractional part of the sum of the node's local time and its local offset (see Section 4.5).
256660x0000-FFFF Global time value of TTCAN network</description>
25667                  <bitRange>[31:16]</bitRange>
25668                  <access>read-only</access>
25669                </field>
25670              </fields>
25671            </register>
25672            <register>
25673              <name>TTCTC</name>
25674              <description>TT Cycle Time &amp; Count</description>
25675              <addressOffset>0x138</addressOffset>
25676              <size>32</size>
25677              <access>read-only</access>
25678              <resetValue>0x3F0000</resetValue>
25679              <resetMask>0x3FFFFF</resetMask>
25680              <fields>
25681                <field>
25682                  <name>CT</name>
25683                  <description>Cycle Time
25684Non-fractional part of the difference of the node's local time and Ref_Mark (see Section 4.5).
256850x0000-FFFF Cycle time value of TTCAN Basic Cycle</description>
25686                  <bitRange>[15:0]</bitRange>
25687                  <access>read-only</access>
25688                </field>
25689                <field>
25690                  <name>CC</name>
25691                  <description>Cycle Count
256920x00-3F Number of actual Basic Cycle in the System Matrix</description>
25693                  <bitRange>[21:16]</bitRange>
25694                  <access>read-only</access>
25695                </field>
25696              </fields>
25697            </register>
25698            <register>
25699              <name>TTCPT</name>
25700              <description>TT Capture Time</description>
25701              <addressOffset>0x13C</addressOffset>
25702              <size>32</size>
25703              <access>read-only</access>
25704              <resetValue>0x0</resetValue>
25705              <resetMask>0xFFFF003F</resetMask>
25706              <fields>
25707                <field>
25708                  <name>CCV</name>
25709                  <description>Cycle Count Value
25710Cycle count value captured together with SWV.
257110x00-3F Captured cycle count value</description>
25712                  <bitRange>[5:0]</bitRange>
25713                  <access>read-only</access>
25714                </field>
25715                <field>
25716                  <name>SWV</name>
25717                  <description>Stop Watch Value
25718On a rising/falling edge (as configured via TTOCN.SWP) at the Stop Watch Trigger pin m_ttcan_swt, when TTOCN.SWS is != '00' and TTIR.SWE is '0', the actual time value as selected
25719by TTOCN.SWS (cycle, local, global) is copied to SWV and TTIR.SWE will be set to '1'. Capturing of the next stop watch value is enabled by resetting TTIR.SWE.
257200x0000-FFFF Captured Stop Watch value</description>
25721                  <bitRange>[31:16]</bitRange>
25722                  <access>read-only</access>
25723                </field>
25724              </fields>
25725            </register>
25726            <register>
25727              <name>TTCSM</name>
25728              <description>TT Cycle Sync Mark</description>
25729              <addressOffset>0x140</addressOffset>
25730              <size>32</size>
25731              <access>read-only</access>
25732              <resetValue>0x0</resetValue>
25733              <resetMask>0xFFFF</resetMask>
25734              <fields>
25735                <field>
25736                  <name>CSM</name>
25737                  <description>Cycle Sync Mark
25738The Cycle Sync Mark is measured</description>
25739                  <bitRange>[15:0]</bitRange>
25740                  <access>read-only</access>
25741                </field>
25742              </fields>
25743            </register>
25744          </cluster>
25745          <register>
25746            <name>RXFTOP_CTL</name>
25747            <description>Receive FIFO Top control</description>
25748            <addressOffset>0x180</addressOffset>
25749            <size>32</size>
25750            <access>read-write</access>
25751            <resetValue>0x0</resetValue>
25752            <resetMask>0x3</resetMask>
25753            <fields>
25754              <field>
25755                <name>F0TPE</name>
25756                <description>FIFO 0 Top Pointer Enable.
25757This enables the FIFO top pointer logic to set the FIFO Top Address (FnTA) and message word counter.
25758This logic is also disabled when the IP is being reconfigured (CCCR.CCE=1).
25759When this logic is disabled a Read from RXFTOP0_DATA is undefined.</description>
25760                <bitRange>[0:0]</bitRange>
25761                <access>read-write</access>
25762              </field>
25763              <field>
25764                <name>F1TPE</name>
25765                <description>FIFO 1 Top Pointer Enable.</description>
25766                <bitRange>[1:1]</bitRange>
25767                <access>read-write</access>
25768              </field>
25769            </fields>
25770          </register>
25771          <register>
25772            <name>RXFTOP0_STAT</name>
25773            <description>Receive FIFO 0 Top Status</description>
25774            <addressOffset>0x1A0</addressOffset>
25775            <size>32</size>
25776            <access>read-only</access>
25777            <resetValue>0x0</resetValue>
25778            <resetMask>0xFFFF</resetMask>
25779            <fields>
25780              <field>
25781                <name>F0TA</name>
25782                <description>Current FIFO 0 Top Address.
25783This is a pointer to the next word in the message buffer defined by the FIFO Start Address (FnSA), Get Index (FnGI), the FIFO message size (FnDS) and the message word counter (FnMWC)
25784FnTA = FnSA + FnGI * msg_size[FnDS] + FnMWC</description>
25785                <bitRange>[15:0]</bitRange>
25786                <access>read-only</access>
25787              </field>
25788            </fields>
25789          </register>
25790          <register>
25791            <name>RXFTOP0_DATA</name>
25792            <description>Receive FIFO 0 Top Data</description>
25793            <addressOffset>0x1A8</addressOffset>
25794            <size>32</size>
25795            <access>read-only</access>
25796            <resetValue>0x0</resetValue>
25797            <resetMask>0x0</resetMask>
25798            <fields>
25799              <field>
25800                <name>F0TD</name>
25801                <description>When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met:
25802- M_TTCAN not being reconfigured (CCCR.CCE=0)
25803- FIFO Top Pointer logic is enabled (FnTPE=1)
25804- FIFO is not empty (FnFL!=0)
25805The read side effect is as follows:
25806- if FnMWC pointed to the last word of the message (as indicated by FnDS) then the corresponding message index (FnGI) is automatically acknowledge by a write to FnAI
25807- FnMWC is incremented (or restarted if FnMWC pointed to the last word of the message)
25808- the FIFO top address FnTA is incremented (with FIFO wrap around)
25809When this logic is disabled (F0TPE=0) a Read from this register returns undefined data.</description>
25810                <bitRange>[31:0]</bitRange>
25811                <access>read-only</access>
25812              </field>
25813            </fields>
25814          </register>
25815          <register>
25816            <name>RXFTOP1_STAT</name>
25817            <description>Receive FIFO 1 Top Status</description>
25818            <addressOffset>0x1B0</addressOffset>
25819            <size>32</size>
25820            <access>read-only</access>
25821            <resetValue>0x0</resetValue>
25822            <resetMask>0xFFFF</resetMask>
25823            <fields>
25824              <field>
25825                <name>F1TA</name>
25826                <description>See F0TA description</description>
25827                <bitRange>[15:0]</bitRange>
25828                <access>read-only</access>
25829              </field>
25830            </fields>
25831          </register>
25832          <register>
25833            <name>RXFTOP1_DATA</name>
25834            <description>Receive FIFO 1 Top Data</description>
25835            <addressOffset>0x1B8</addressOffset>
25836            <size>32</size>
25837            <access>read-only</access>
25838            <resetValue>0x0</resetValue>
25839            <resetMask>0x0</resetMask>
25840            <fields>
25841              <field>
25842                <name>F1TD</name>
25843                <description>See F0TD description</description>
25844                <bitRange>[31:0]</bitRange>
25845                <access>read-only</access>
25846              </field>
25847            </fields>
25848          </register>
25849        </cluster>
25850        <register>
25851          <name>CTL</name>
25852          <description>Global CAN control register</description>
25853          <addressOffset>0x1000</addressOffset>
25854          <size>32</size>
25855          <access>read-write</access>
25856          <resetValue>0x0</resetValue>
25857          <resetMask>0x800000FF</resetMask>
25858          <fields>
25859            <field>
25860              <name>STOP_REQ</name>
25861              <description>Clock Stop Request for each TTCAN IP .
25862The m_ttcan_clkstop_req of each TTCAN IP is directly driven by these bits.</description>
25863              <bitRange>[7:0]</bitRange>
25864              <access>read-write</access>
25865            </field>
25866            <field>
25867              <name>MRAM_OFF</name>
25868              <description>MRAM off
258690= Default MRAM on (with MRAM retained in DeepSleep).
258701= Switch MRAM off (not retained) to save power. Before setting this bit all the CAN channels have to be powered down using the STOP_REQ/ACK bits.
25871When the MRAM is off any access attempt to it is considered an address error (as if MRAM_SIZE=0).
25872After switching the MRAM on again software needs to allow for a certain power up time before MRAM can be used, i.e. before STOP_REQ can be de-asserted. The power up time is equivalent to the system SRAM power up time specified in the CPUSS.RAM_PWR_DELAY_CTL register.
25873
25874To meet S8 platform requirements, MRAM_OFF should be set to 0 prior to transitioning to Hibernate mode.</description>
25875              <bitRange>[31:31]</bitRange>
25876              <access>read-write</access>
25877            </field>
25878          </fields>
25879        </register>
25880        <register>
25881          <name>STATUS</name>
25882          <description>Global CAN status register</description>
25883          <addressOffset>0x1004</addressOffset>
25884          <size>32</size>
25885          <access>read-only</access>
25886          <resetValue>0x0</resetValue>
25887          <resetMask>0xFF</resetMask>
25888          <fields>
25889            <field>
25890              <name>STOP_ACK</name>
25891              <description>Clock Stop Acknowledge for each TTCAN IP.
25892These bits are directly driven by m_ttcan_clkstop_ack of each TTCAN IP.
25893When this bit is set the corresponding TTCAN IP clocks will be gated off, except HCLK will enabled for each AHB write</description>
25894              <bitRange>[7:0]</bitRange>
25895              <access>read-only</access>
25896            </field>
25897          </fields>
25898        </register>
25899        <register>
25900          <name>INTR0_CAUSE</name>
25901          <description>Consolidated interrupt0 cause register</description>
25902          <addressOffset>0x1010</addressOffset>
25903          <size>32</size>
25904          <access>read-only</access>
25905          <resetValue>0x0</resetValue>
25906          <resetMask>0xFF</resetMask>
25907          <fields>
25908            <field>
25909              <name>INT0</name>
25910              <description>Show pending m_ttcan_int0 of each channel</description>
25911              <bitRange>[7:0]</bitRange>
25912              <access>read-only</access>
25913            </field>
25914          </fields>
25915        </register>
25916        <register>
25917          <name>INTR1_CAUSE</name>
25918          <description>Consolidated interrupt1 cause register</description>
25919          <addressOffset>0x1014</addressOffset>
25920          <size>32</size>
25921          <access>read-only</access>
25922          <resetValue>0x0</resetValue>
25923          <resetMask>0xFF</resetMask>
25924          <fields>
25925            <field>
25926              <name>INT1</name>
25927              <description>Show pending m_ttcan_int1 of each channel</description>
25928              <bitRange>[7:0]</bitRange>
25929              <access>read-only</access>
25930            </field>
25931          </fields>
25932        </register>
25933        <register>
25934          <name>TS_CTL</name>
25935          <description>Time Stamp control register</description>
25936          <addressOffset>0x1020</addressOffset>
25937          <size>32</size>
25938          <access>read-write</access>
25939          <resetValue>0x0</resetValue>
25940          <resetMask>0x8000FFFF</resetMask>
25941          <fields>
25942            <field>
25943              <name>PRESCALE</name>
25944              <description>Time Stamp counter prescale value.
25945When enabled divide the Host clock (HCLK) by PRESCALE+1 to create Time Stamp clock ticks.</description>
25946              <bitRange>[15:0]</bitRange>
25947              <access>read-write</access>
25948            </field>
25949            <field>
25950              <name>ENABLED</name>
25951              <description>Counter enable bit
259520 = Count disabled. Stop counting up and keep the counter value
259531 = Count enabled. Start counting up from the current value</description>
25954              <bitRange>[31:31]</bitRange>
25955              <access>read-write</access>
25956            </field>
25957          </fields>
25958        </register>
25959        <register>
25960          <name>TS_CNT</name>
25961          <description>Time Stamp counter value</description>
25962          <addressOffset>0x1024</addressOffset>
25963          <size>32</size>
25964          <access>read-write</access>
25965          <resetValue>0x0</resetValue>
25966          <resetMask>0xFFFF</resetMask>
25967          <fields>
25968            <field>
25969              <name>VALUE</name>
25970              <description>The counter value of the Time Stamp Counter.
25971When enabled this counter will count Time Stamp clock ticks from the pre-scaler.
25972When written this counter and the pre-scaler will reset to 0 (write data is ignored).</description>
25973              <bitRange>[15:0]</bitRange>
25974              <access>read-write</access>
25975            </field>
25976          </fields>
25977        </register>
25978        <register>
25979          <name>ECC_CTL</name>
25980          <description>ECC control</description>
25981          <addressOffset>0x1080</addressOffset>
25982          <size>32</size>
25983          <access>read-write</access>
25984          <resetValue>0x0</resetValue>
25985          <resetMask>0x10000</resetMask>
25986          <fields>
25987            <field>
25988              <name>ECC_EN</name>
25989              <description>Enable ECC for CANFD SRAM
25990When disabled also all error injection functionality is disabled.</description>
25991              <bitRange>[16:16]</bitRange>
25992              <access>read-write</access>
25993            </field>
25994          </fields>
25995        </register>
25996        <register>
25997          <name>ECC_ERR_INJ</name>
25998          <description>ECC error injection</description>
25999          <addressOffset>0x1084</addressOffset>
26000          <size>32</size>
26001          <access>read-write</access>
26002          <resetValue>0xFFFC</resetValue>
26003          <resetMask>0x7F10FFFC</resetMask>
26004          <fields>
26005            <field>
26006              <name>ERR_ADDR</name>
26007              <description>Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed.
26008When the ERR_EN bit is set an error parity (ERR_PAR) is injected when any write, from bus or a CAN channel, is done to this address.
26009When the ERR_EN bit is set and the access address matches ERR_ADDR then a non-correctable ECC error or an Address error will NOT result in a bus error or CAN channel shutdown.
26010Note that error reporting to the fault structure cannot be suppressed.</description>
26011              <bitRange>[15:2]</bitRange>
26012              <access>read-write</access>
26013            </field>
26014            <field>
26015              <name>ERR_EN</name>
26016              <description>Enable error injection (ECC_EN must be 1).
26017When this bit is set the error parity (ERR_PAR) will be used when an AHB write is done to the ERR_ADDR address.
26018When the error word is read a single or double error will be reported to the fault structure just like for a real ECC error (even if this bit is no longer set).
26019When this bit is set (and ECC_EN=1) a non-correctable error (ECC or address error) for the ERR_ADDR will not be reported back to the CAN channel or  AHB bus.</description>
26020              <bitRange>[20:20]</bitRange>
26021              <access>read-write</access>
26022            </field>
26023            <field>
26024              <name>ERR_PAR</name>
26025              <description>ECC Parity bits to use for ECC error injection at address ERR_ADDR.</description>
26026              <bitRange>[30:24]</bitRange>
26027              <access>read-write</access>
26028            </field>
26029          </fields>
26030        </register>
26031      </registers>
26032    </peripheral>
26033    <peripheral derivedFrom="CANFD0">
26034      <name>CANFD1</name>
26035      <baseAddress>0x40540000</baseAddress>
26036    </peripheral>
26037    <peripheral>
26038      <name>SCB0</name>
26039      <description>Serial Communications Block (SPI/UART/I2C)</description>
26040      <headerStructName>SCB</headerStructName>
26041      <baseAddress>0x40600000</baseAddress>
26042      <addressBlock>
26043        <offset>0</offset>
26044        <size>65536</size>
26045        <usage>registers</usage>
26046      </addressBlock>
26047      <registers>
26048        <register>
26049          <name>CTRL</name>
26050          <description>Generic control</description>
26051          <addressOffset>0x0</addressOffset>
26052          <size>32</size>
26053          <access>read-write</access>
26054          <resetValue>0x300400F</resetValue>
26055          <resetMask>0x9303D70F</resetMask>
26056          <fields>
26057            <field>
26058              <name>OVS</name>
26059              <description>N/A</description>
26060              <bitRange>[3:0]</bitRange>
26061              <access>read-write</access>
26062            </field>
26063            <field>
26064              <name>EC_AM_MODE</name>
26065              <description>Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported.
26066
26067In UART mode this field should be '0'.</description>
26068              <bitRange>[8:8]</bitRange>
26069              <access>read-write</access>
26070            </field>
26071            <field>
26072              <name>EC_OP_MODE</name>
26073              <description>Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The maximum SPI slave, EZ mode bitrate is 48 Mbps (transmission and IO delays outside the IP will degrade the effective bitrate).
26074
26075In UART mode this field should be '0'.</description>
26076              <bitRange>[9:9]</bitRange>
26077              <access>read-write</access>
26078            </field>
26079            <field>
26080              <name>EZ_MODE</name>
26081              <description>Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode is only used for synchronous serial interface protocols: SPI and I2C. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported and the transmitter should use continuous data frames; i.e. data frames mot separated by slave deselection. This mode is only applicable to slave functionality. In EZ mode, the slave can read from and write to an addressable memory structure of up to 256 bytes. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first.
26082
26083In UART mode this field should be '0'.</description>
26084              <bitRange>[10:10]</bitRange>
26085              <access>read-write</access>
26086            </field>
26087            <field>
26088              <name>CMD_RESP_MODE</name>
26089              <description>Determines CMD_RESP mode of operation:
26090'0': CMD_RESP mode disabled.
26091'1': CMD_RESP mode enabled (also requires EC_AM_MODE and EC_OP_MODE to be set to '1').</description>
26092              <bitRange>[12:12]</bitRange>
26093              <access>read-write</access>
26094            </field>
26095            <field>
26096              <name>MEM_WIDTH</name>
26097              <description>Determines the number of bits per FIFO data element.</description>
26098              <bitRange>[15:14]</bitRange>
26099              <access>read-write</access>
26100              <enumeratedValues>
26101                <enumeratedValue>
26102                  <name>BYTE</name>
26103                  <description>8-bit FIFO data elements.
26104This mode provides the biggest amount of FIFO entries, but  TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 7].</description>
26105                  <value>0</value>
26106                </enumeratedValue>
26107                <enumeratedValue>
26108                  <name>HALFWORD</name>
26109                  <description>16-bit FIFO data elements.
26110TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 15].</description>
26111                  <value>1</value>
26112                </enumeratedValue>
26113                <enumeratedValue>
26114                  <name>WORD</name>
26115                  <description>32-bit FIFO data elements.
26116This mode provides the smallest amount of FIFO entries, but TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH can be in a range of [0, 31].</description>
26117                  <value>2</value>
26118                </enumeratedValue>
26119                <enumeratedValue>
26120                  <name>RSVD</name>
26121                  <description>N/A</description>
26122                  <value>3</value>
26123                </enumeratedValue>
26124              </enumeratedValues>
26125            </field>
26126            <field>
26127              <name>ADDR_ACCEPT</name>
26128              <description>Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0').
26129
26130In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when ADDR_ACCEPT is '1' for both I2C read and write transfers.
26131
26132In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO.</description>
26133              <bitRange>[16:16]</bitRange>
26134              <access>read-write</access>
26135            </field>
26136            <field>
26137              <name>BLOCK</name>
26138              <description>Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide, this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0'). IF BLOCK is '0' and the accesses collide, MMIO read operations return 0xffff:ffff and MMIO write operations are ignored. Colliding accesses are registered as interrupt causes: field BLOCKED of MMIO registers INTR_TX and INTR_RX.</description>
26139              <bitRange>[17:17]</bitRange>
26140              <access>read-write</access>
26141            </field>
26142            <field>
26143              <name>MODE</name>
26144              <description>N/A</description>
26145              <bitRange>[25:24]</bitRange>
26146              <access>read-write</access>
26147              <enumeratedValues>
26148                <enumeratedValue>
26149                  <name>I2C</name>
26150                  <description>Inter-Integrated Circuits (I2C) mode.</description>
26151                  <value>0</value>
26152                </enumeratedValue>
26153                <enumeratedValue>
26154                  <name>SPI</name>
26155                  <description>Serial Peripheral Interface (SPI) mode.</description>
26156                  <value>1</value>
26157                </enumeratedValue>
26158                <enumeratedValue>
26159                  <name>UART</name>
26160                  <description>Universal Asynchronous Receiver/Transmitter (UART) mode.</description>
26161                  <value>2</value>
26162                </enumeratedValue>
26163              </enumeratedValues>
26164            </field>
26165            <field>
26166              <name>EC_ACCESS</name>
26167              <description>used to enable I2CS_EC or SPIS_EC access to internal SRAM memory.
261680: enable clock_scb_en, has no effect on ec_busy_pp
261691: disable clock_scb_en, enable ec_busy_pp (grant I2CS_EC or SPIS_EC access)
26170
26171Before going to deepsleep this field should be set to 1.
26172when waking up from DeepSleep power mode, and PLL is locked (clk_scb is at expected frequency), this filed should be set to 0.</description>
26173              <bitRange>[28:28]</bitRange>
26174              <access>read-write</access>
26175            </field>
26176            <field>
26177              <name>ENABLED</name>
26178              <description>IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:
26179- Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable.
26180- Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality.
26181- Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information.
26182- Program CTRL to enable IP, select the specific operation mode and oversampling factor.
26183Generally hen the IP is enabled, no control information should be changed. Changes should be made AFTER disabling the IP, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the IP is re-enabled. Note that disabling the IP will cause re-initialization of the design and associated state is lost (e.g. FIFO content).
26184
26185Specific to SPI master case,  when SCB is idle,  below registers can be changed without disabling SCB block,
26186      TX_CTRL
26187      TX_FIFO_CTRL
26188      RX_CTRL
26189      RX_FIFO_CTRL
26190      SPI_CTRL.SSEL,</description>
26191              <bitRange>[31:31]</bitRange>
26192              <access>read-write</access>
26193            </field>
26194          </fields>
26195        </register>
26196        <register>
26197          <name>STATUS</name>
26198          <description>Generic status</description>
26199          <addressOffset>0x4</addressOffset>
26200          <size>32</size>
26201          <access>read-only</access>
26202          <resetValue>0x0</resetValue>
26203          <resetMask>0x0</resetMask>
26204          <fields>
26205            <field>
26206              <name>EC_BUSY</name>
26207              <description>Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a blocked SW access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether a SW access was actually blocked by externally clocked logic.</description>
26208              <bitRange>[0:0]</bitRange>
26209              <access>read-only</access>
26210            </field>
26211          </fields>
26212        </register>
26213        <register>
26214          <name>CMD_RESP_CTRL</name>
26215          <description>Command/response control</description>
26216          <addressOffset>0x8</addressOffset>
26217          <size>32</size>
26218          <access>read-write</access>
26219          <resetValue>0x0</resetValue>
26220          <resetMask>0x1FF01FF</resetMask>
26221          <fields>
26222            <field>
26223              <name>BASE_RD_ADDR</name>
26224              <description>I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers.</description>
26225              <bitRange>[8:0]</bitRange>
26226              <access>read-write</access>
26227            </field>
26228            <field>
26229              <name>BASE_WR_ADDR</name>
26230              <description>I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers.</description>
26231              <bitRange>[24:16]</bitRange>
26232              <access>read-write</access>
26233            </field>
26234          </fields>
26235        </register>
26236        <register>
26237          <name>CMD_RESP_STATUS</name>
26238          <description>Command/response status</description>
26239          <addressOffset>0xC</addressOffset>
26240          <size>32</size>
26241          <access>read-only</access>
26242          <resetValue>0x0</resetValue>
26243          <resetMask>0x0</resetMask>
26244          <fields>
26245            <field>
26246              <name>CURR_RD_ADDR</name>
26247              <description>I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address).
26248
26249The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR).
26250
26251This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable.</description>
26252              <bitRange>[8:0]</bitRange>
26253              <access>read-only</access>
26254            </field>
26255            <field>
26256              <name>CURR_WR_ADDR</name>
26257              <description>I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address).
26258
26259The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR).
26260
26261This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable.</description>
26262              <bitRange>[24:16]</bitRange>
26263              <access>read-only</access>
26264            </field>
26265            <field>
26266              <name>CMD_RESP_EC_BUS_BUSY</name>
26267              <description>Indicates whether there is an ongoing bus transfer to the IP.
26268'0': no ongoing bus transfer.
26269'1': ongoing bus transfer.
26270
26271For SPI, the field is '1' when the slave is selected.
26272
26273For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the  field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match.</description>
26274              <bitRange>[30:30]</bitRange>
26275              <access>read-only</access>
26276            </field>
26277            <field>
26278              <name>CMD_RESP_EC_BUSY</name>
26279              <description>Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:
26280- When there is no ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable).
26281- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable), when the CURR_RD_ADDR and CURR_WR_ADDR are not being updated by the HW.
26282- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '1' (not reliable), when the CURR_RD_ADDR or CURR_WR_ADDR are being updated by the HW.
26283   Note that this update lasts one I2C clock cycle, or two SPI clock cycles.</description>
26284              <bitRange>[31:31]</bitRange>
26285              <access>read-only</access>
26286            </field>
26287          </fields>
26288        </register>
26289        <register>
26290          <name>SPI_CTRL</name>
26291          <description>SPI control</description>
26292          <addressOffset>0x20</addressOffset>
26293          <size>32</size>
26294          <access>read-write</access>
26295          <resetValue>0x3000010</resetValue>
26296          <resetMask>0x8F017F3F</resetMask>
26297          <fields>
26298            <field>
26299              <name>SSEL_CONTINUOUS</name>
26300              <description>Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field.
26301
26302When continuous transfers are enabled individual data frame transfers are not necessarily separated by slave deselection (as indicated by the level or pulse on the SELECT line): if the TX FIFO has multiple data frames, data frames are send out without slave deselection.
26303
26304When continuous transfers are not enabled individual data frame transfers are always separated by slave deselection: data frames are always separated by slave deselection.</description>
26305              <bitRange>[0:0]</bitRange>
26306              <access>read-write</access>
26307            </field>
26308            <field>
26309              <name>SELECT_PRECEDE</name>
26310              <description>Only used in SPI Texas Instruments' submode.
26311
26312When '1', the data frame start indication is a pulse on the SELECT line that precedes the transfer of the first data frame bit.
26313
26314When '0', the data frame start indication is a pulse on the SELECT line that coincides with the transfer of the first data frame bit.</description>
26315              <bitRange>[1:1]</bitRange>
26316              <access>read-write</access>
26317            </field>
26318            <field>
26319              <name>CPHA</name>
26320              <description>Indicates the clock phase. This field, together with the CPOL field, indicates when MOSI data is driven and MISO data is captured:
26321- Motorola mode 0. CPOL is '0', CPHA is '0': MOSI  is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK.
26322- Motorola mode 1. CPOL is '0', CPHA is '1': MOSI  is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK.
26323- Motorola mode 2. CPOL is '1', CPHA is '0': MOSI  is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK.
26324- Motorola mode 3. CPOL is '1', CPHA is '1': MOSI  is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK.
26325
26326In SPI Motorola submode, all four CPOL/CPHA modes are valid.
26327in SPI NS submode, only CPOL=0 CPHA=0 mode is valid.
26328in SPI TI submode, only CPOL=0 CPHA=1 mode is valid.</description>
26329              <bitRange>[2:2]</bitRange>
26330              <access>read-write</access>
26331            </field>
26332            <field>
26333              <name>CPOL</name>
26334              <description>Indicates the clock polarity. This field, together with the CPHA field, indicates when MOSI data is driven and MISO data is captured:
26335- CPOL is '0': SCLK is '0' when not transmitting data.
26336- CPOL is '1': SCLK is '1' when not transmitting data.</description>
26337              <bitRange>[3:3]</bitRange>
26338              <access>read-write</access>
26339            </field>
26340            <field>
26341              <name>LATE_MISO_SAMPLE</name>
26342              <description>Changes the SCLK edge on which MISO is captured. Only used in master mode.
26343
26344When '0', the default applies (for Motorola as determined by CPOL and CPHA, for Texas Instruments on the falling edge of SCLK and for National Semiconductors on the rising edge of SCLK).
26345
26346When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master.</description>
26347              <bitRange>[4:4]</bitRange>
26348              <access>read-write</access>
26349            </field>
26350            <field>
26351              <name>SCLK_CONTINUOUS</name>
26352              <description>Only applicable in master mode.
26353'0': SCLK is generated, when the SPI master is enabled and data is transmitted.
26354'1': SCLK is generated, when the SPI master is enabled. This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality.</description>
26355              <bitRange>[5:5]</bitRange>
26356              <access>read-write</access>
26357            </field>
26358            <field>
26359              <name>SSEL_POLARITY0</name>
26360              <description>Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:
26361'0': slave select is low/'0' active.
26362'1': slave select is high/'1' active.
26363For Texas Instruments submode:
26364'0': high/'1' active precede/coincide pulse.
26365'1': low/'0' active precede/coincide pulse.</description>
26366              <bitRange>[8:8]</bitRange>
26367              <access>read-write</access>
26368            </field>
26369            <field>
26370              <name>SSEL_POLARITY1</name>
26371              <description>Slave select polarity.</description>
26372              <bitRange>[9:9]</bitRange>
26373              <access>read-write</access>
26374            </field>
26375            <field>
26376              <name>SSEL_POLARITY2</name>
26377              <description>Slave select polarity.</description>
26378              <bitRange>[10:10]</bitRange>
26379              <access>read-write</access>
26380            </field>
26381            <field>
26382              <name>SSEL_POLARITY3</name>
26383              <description>Slave select polarity.</description>
26384              <bitRange>[11:11]</bitRange>
26385              <access>read-write</access>
26386            </field>
26387            <field>
26388              <name>SSEL_SETUP_DEL</name>
26389              <description>Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit).
26390'0': 0.75 SPI clock cycles
26391'1': 1.75 SPI clock cycles
26392Only applies in SPI MOTOROLA submode and when SCLK_CONTINUOUS=0, CTRL.OVS&gt;=3.
26393
26394above are ideal case at SCB block level, and there is inaccuracy of one clk_scb cycle.</description>
26395              <bitRange>[12:12]</bitRange>
26396              <access>read-write</access>
26397            </field>
26398            <field>
26399              <name>SSEL_HOLD_DEL</name>
26400              <description>Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit, and SELECT deactivation).
26401'0': 0.75 SPI clock cycles
26402'1': 1.75 SPI clock cycles
26403Only applies in SPI MOTOROLA submode and when SCLK_CONTINUOUS=0, CTRL.OVS&gt;=3.
26404
26405above are ideal case at SCB block level, and there is inaccuracy of one clk_scb cycle.</description>
26406              <bitRange>[13:13]</bitRange>
26407              <access>read-write</access>
26408            </field>
26409            <field>
26410              <name>SSEL_INTER_FRAME_DEL</name>
26411              <description>Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation).
26412'0': 1.5 SPI clock cycles
26413'1': 2.5 SPI clock cycles
26414Only applies in SPI MOTOROLA submode and when SPI_CTRL.SSEL_CONTINUOUS=0, CTRL.OVS&gt;=3.
26415
26416above are ideal case at SCB block level, and there is inaccuracy of one clk_scb cycle.</description>
26417              <bitRange>[14:14]</bitRange>
26418              <access>read-write</access>
26419            </field>
26420            <field>
26421              <name>LOOPBACK</name>
26422              <description>Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode.
26423'0': the SPI master MISO line 'spi_miso_in' is connected to the SPI MISO pin.
26424'1': the SPI master MISO line 'spi_miso_in' is connected to the SPI master MOSI line 'spi_mosi_out'. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI.</description>
26425              <bitRange>[16:16]</bitRange>
26426              <access>read-write</access>
26427            </field>
26428            <field>
26429              <name>MODE</name>
26430              <description>N/A</description>
26431              <bitRange>[25:24]</bitRange>
26432              <access>read-write</access>
26433              <enumeratedValues>
26434                <enumeratedValue>
26435                  <name>SPI_MOTOROLA</name>
26436                  <description>SPI Motorola submode. In master mode, when not transmitting data (SELECT is inactive), SCLK is stable at CPOL. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive.</description>
26437                  <value>0</value>
26438                </enumeratedValue>
26439                <enumeratedValue>
26440                  <name>SPI_TI</name>
26441                  <description>SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive; i.e. no pulse is generated.</description>
26442                  <value>1</value>
26443                </enumeratedValue>
26444                <enumeratedValue>
26445                  <name>SPI_NS</name>
26446                  <description>SPI National Semiconductors submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive.</description>
26447                  <value>2</value>
26448                </enumeratedValue>
26449              </enumeratedValues>
26450            </field>
26451            <field>
26452              <name>SSEL</name>
26453              <description>Selects one of the four incoming/outgoing SPI slave select signals:
26454- 0: Slave 0, SSEL[0].
26455- 1: Slave 1, SSEL[1].
26456- 2: Slave 2, SSEL[2].
26457- 3: Slave 3, SSEL[3].
26458The IP should be disabled when changes are made to this field.</description>
26459              <bitRange>[27:26]</bitRange>
26460              <access>read-write</access>
26461            </field>
26462            <field>
26463              <name>MASTER_MODE</name>
26464              <description>Master ('1') or slave ('0') mode. In master mode, transmission will commence on availability of data frames in the TX FIFO. In slave mode, when selected and there is no data frame in the TX FIFO, the slave will transmit all '1's. In both master and slave modes, received data frames will be lost if the RX FIFO is full.</description>
26465              <bitRange>[31:31]</bitRange>
26466              <access>read-write</access>
26467            </field>
26468          </fields>
26469        </register>
26470        <register>
26471          <name>SPI_STATUS</name>
26472          <description>SPI status</description>
26473          <addressOffset>0x24</addressOffset>
26474          <size>32</size>
26475          <access>read-only</access>
26476          <resetValue>0x0</resetValue>
26477          <resetMask>0x0</resetMask>
26478          <fields>
26479            <field>
26480              <name>BUS_BUSY</name>
26481              <description>SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted.</description>
26482              <bitRange>[0:0]</bitRange>
26483              <access>read-only</access>
26484            </field>
26485            <field>
26486              <name>SPI_EC_BUSY</name>
26487              <description>Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable.</description>
26488              <bitRange>[1:1]</bitRange>
26489              <access>read-only</access>
26490            </field>
26491            <field>
26492              <name>CURR_EZ_ADDR</name>
26493              <description>SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design.</description>
26494              <bitRange>[15:8]</bitRange>
26495              <access>read-only</access>
26496            </field>
26497            <field>
26498              <name>BASE_EZ_ADDR</name>
26499              <description>SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design.</description>
26500              <bitRange>[23:16]</bitRange>
26501              <access>read-only</access>
26502            </field>
26503          </fields>
26504        </register>
26505        <register>
26506          <name>SPI_TX_CTRL</name>
26507          <description>SPI transmitter control</description>
26508          <addressOffset>0x28</addressOffset>
26509          <size>32</size>
26510          <access>read-write</access>
26511          <resetValue>0x0</resetValue>
26512          <resetMask>0x30</resetMask>
26513          <fields>
26514            <field>
26515              <name>PARITY</name>
26516              <description>Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity.</description>
26517              <bitRange>[4:4]</bitRange>
26518              <access>read-write</access>
26519            </field>
26520            <field>
26521              <name>PARITY_ENABLED</name>
26522              <description>Parity generation enabled ('1') or not ('0').</description>
26523              <bitRange>[5:5]</bitRange>
26524              <access>read-write</access>
26525            </field>
26526          </fields>
26527        </register>
26528        <register>
26529          <name>SPI_RX_CTRL</name>
26530          <description>SPI receiver control</description>
26531          <addressOffset>0x2C</addressOffset>
26532          <size>32</size>
26533          <access>read-write</access>
26534          <resetValue>0x0</resetValue>
26535          <resetMask>0x130</resetMask>
26536          <fields>
26537            <field>
26538              <name>PARITY</name>
26539              <description>Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity.</description>
26540              <bitRange>[4:4]</bitRange>
26541              <access>read-write</access>
26542            </field>
26543            <field>
26544              <name>PARITY_ENABLED</name>
26545              <description>Parity checking enabled ('1') or not ('0').</description>
26546              <bitRange>[5:5]</bitRange>
26547              <access>read-write</access>
26548            </field>
26549            <field>
26550              <name>DROP_ON_PARITY_ERROR</name>
26551              <description>Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost.</description>
26552              <bitRange>[8:8]</bitRange>
26553              <access>read-write</access>
26554            </field>
26555          </fields>
26556        </register>
26557        <register>
26558          <name>UART_CTRL</name>
26559          <description>UART control</description>
26560          <addressOffset>0x40</addressOffset>
26561          <size>32</size>
26562          <access>read-write</access>
26563          <resetValue>0x3000000</resetValue>
26564          <resetMask>0x3010000</resetMask>
26565          <fields>
26566            <field>
26567              <name>LOOPBACK</name>
26568              <description>Local loopback control (does NOT affect the information on the pins). When '0', the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1', the transmitter TX line 'uart_tx_out' is connected to the receiver RX line 'uart_rx_in'. A similar connections scheme is followed for 'uart_rts_out' and 'uart_cts_in'.
26569
26570This allows a SCB UART transmitter to communicate with its receiver counterpart.</description>
26571              <bitRange>[16:16]</bitRange>
26572              <access>read-write</access>
26573            </field>
26574            <field>
26575              <name>MODE</name>
26576              <description>N/A</description>
26577              <bitRange>[25:24]</bitRange>
26578              <access>read-write</access>
26579              <enumeratedValues>
26580                <enumeratedValue>
26581                  <name>UART_STD</name>
26582                  <description>Standard UART submode.</description>
26583                  <value>0</value>
26584                </enumeratedValue>
26585                <enumeratedValue>
26586                  <name>UART_SMARTCARD</name>
26587                  <description>SmartCard (ISO7816) submode. Support for negative acknowledgement (NACK) on the receiver side and retransmission on the transmitter side.</description>
26588                  <value>1</value>
26589                </enumeratedValue>
26590                <enumeratedValue>
26591                  <name>UART_IRDA</name>
26592                  <description>Infrared Data Association (IrDA) submode. Return to Zero modulation scheme.</description>
26593                  <value>2</value>
26594                </enumeratedValue>
26595              </enumeratedValues>
26596            </field>
26597          </fields>
26598        </register>
26599        <register>
26600          <name>UART_TX_CTRL</name>
26601          <description>UART transmitter control</description>
26602          <addressOffset>0x44</addressOffset>
26603          <size>32</size>
26604          <access>read-write</access>
26605          <resetValue>0x2</resetValue>
26606          <resetMask>0x137</resetMask>
26607          <fields>
26608            <field>
26609              <name>STOP_BITS</name>
26610              <description>Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period.</description>
26611              <bitRange>[2:0]</bitRange>
26612              <access>read-write</access>
26613            </field>
26614            <field>
26615              <name>PARITY</name>
26616              <description>Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes.</description>
26617              <bitRange>[4:4]</bitRange>
26618              <access>read-write</access>
26619            </field>
26620            <field>
26621              <name>PARITY_ENABLED</name>
26622              <description>Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware</description>
26623              <bitRange>[5:5]</bitRange>
26624              <access>read-write</access>
26625            </field>
26626            <field>
26627              <name>RETRY_ON_NACK</name>
26628              <description>When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode.</description>
26629              <bitRange>[8:8]</bitRange>
26630              <access>read-write</access>
26631            </field>
26632          </fields>
26633        </register>
26634        <register>
26635          <name>UART_RX_CTRL</name>
26636          <description>UART receiver control</description>
26637          <addressOffset>0x48</addressOffset>
26638          <size>32</size>
26639          <access>read-write</access>
26640          <resetValue>0xA0002</resetValue>
26641          <resetMask>0x10F3777</resetMask>
26642          <fields>
26643            <field>
26644              <name>STOP_BITS</name>
26645              <description>Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period.
26646
26647Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle ('1') time between data frames and the data frame value.</description>
26648              <bitRange>[2:0]</bitRange>
26649              <access>read-write</access>
26650            </field>
26651            <field>
26652              <name>PARITY</name>
26653              <description>Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes.</description>
26654              <bitRange>[4:4]</bitRange>
26655              <access>read-write</access>
26656            </field>
26657            <field>
26658              <name>PARITY_ENABLED</name>
26659              <description>Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware.</description>
26660              <bitRange>[5:5]</bitRange>
26661              <access>read-write</access>
26662            </field>
26663            <field>
26664              <name>POLARITY</name>
26665              <description>Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality.</description>
26666              <bitRange>[6:6]</bitRange>
26667              <access>read-write</access>
26668            </field>
26669            <field>
26670              <name>DROP_ON_PARITY_ERROR</name>
26671              <description>Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field).</description>
26672              <bitRange>[8:8]</bitRange>
26673              <access>read-write</access>
26674            </field>
26675            <field>
26676              <name>DROP_ON_FRAME_ERROR</name>
26677              <description>Behavior when an error is detected in a start or stop period. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost.</description>
26678              <bitRange>[9:9]</bitRange>
26679              <access>read-write</access>
26680            </field>
26681            <field>
26682              <name>MP_MODE</name>
26683              <description>Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode, the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data are sent to the RX FIFO. In the case of NO match, subsequent received data are dropped.</description>
26684              <bitRange>[10:10]</bitRange>
26685              <access>read-write</access>
26686            </field>
26687            <field>
26688              <name>LIN_MODE</name>
26689              <description>Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte.</description>
26690              <bitRange>[12:12]</bitRange>
26691              <access>read-write</access>
26692            </field>
26693            <field>
26694              <name>SKIP_START</name>
26695              <description>Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO2 IP. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit.</description>
26696              <bitRange>[13:13]</bitRange>
26697              <access>read-write</access>
26698            </field>
26699            <field>
26700              <name>BREAK_WIDTH</name>
26701              <description>Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note that break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value.</description>
26702              <bitRange>[19:16]</bitRange>
26703              <access>read-write</access>
26704            </field>
26705            <field>
26706              <name>BREAK_LEVEL</name>
26707              <description>0: low level pulse detection, like Break field in LIN protocol
267081: high level pulse detection, like IFS field in CXPI protocol, or idle line state in UART</description>
26709              <bitRange>[24:24]</bitRange>
26710              <access>read-write</access>
26711            </field>
26712          </fields>
26713        </register>
26714        <register>
26715          <name>UART_RX_STATUS</name>
26716          <description>UART receiver status</description>
26717          <addressOffset>0x4C</addressOffset>
26718          <size>32</size>
26719          <access>read-only</access>
26720          <resetValue>0x0</resetValue>
26721          <resetMask>0x0</resetMask>
26722          <fields>
26723            <field>
26724              <name>BR_COUNTER</name>
26725              <description>Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'.</description>
26726              <bitRange>[11:0]</bitRange>
26727              <access>read-only</access>
26728            </field>
26729          </fields>
26730        </register>
26731        <register>
26732          <name>UART_FLOW_CTRL</name>
26733          <description>UART flow control</description>
26734          <addressOffset>0x50</addressOffset>
26735          <size>32</size>
26736          <access>read-write</access>
26737          <resetValue>0x0</resetValue>
26738          <resetMask>0x30100FF</resetMask>
26739          <fields>
26740            <field>
26741              <name>TRIGGER_LEVEL</name>
26742              <description>Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0', flow control is effectively SW disabled (may be useful for debug purposes).</description>
26743              <bitRange>[7:0]</bitRange>
26744              <access>read-write</access>
26745            </field>
26746            <field>
26747              <name>RTS_POLARITY</name>
26748              <description>Polarity of the RTS output signal 'uart_rts_out':
26749'0': RTS is low/'0' active; 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive.
26750'1': RTS is high/'1' active; 'uart_rts_out' is '1' when active and 'uart_rts_out' is '0' when inactive.
26751
26752During IP reset (Hibernate system power mode), 'uart_rts_out' is '1'. This represents an inactive state assuming a low/'0' active polarity.</description>
26753              <bitRange>[16:16]</bitRange>
26754              <access>read-write</access>
26755            </field>
26756            <field>
26757              <name>CTS_POLARITY</name>
26758              <description>Polarity of the CTS input signal 'uart_cts_in':
26759'0': CTS is low/'0' active; 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive.
26760'1': CTS is high/'1' active; 'uart_cts_in' is '1' when active and 'uart_cts_in' is '0' when inactive.</description>
26761              <bitRange>[24:24]</bitRange>
26762              <access>read-write</access>
26763            </field>
26764            <field>
26765              <name>CTS_ENABLED</name>
26766              <description>Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:
26767'0': Disabled. The UART transmitter ignores 'uart_cts_in', and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register.
26768'1': Enabled. The UART transmitter uses 'uart_cts_in' to qualify the transmission of data. It transmits when 'uart_cts_in' is active and a data frame is available for transmission in the TX FIFO or the TX shift register.
26769
26770If UART_CTRL.LOOPBACK is '1', 'uart_cts_in' is connected to 'uart_rts_out' in the IP (both signals are subjected to signal polarity changes as indicated by RTS_POLARITY and CTS_POLARITY).</description>
26771              <bitRange>[25:25]</bitRange>
26772              <access>read-write</access>
26773            </field>
26774          </fields>
26775        </register>
26776        <register>
26777          <name>I2C_CTRL</name>
26778          <description>I2C control</description>
26779          <addressOffset>0x60</addressOffset>
26780          <size>32</size>
26781          <access>read-write</access>
26782          <resetValue>0xFB88</resetValue>
26783          <resetMask>0xC001FBFF</resetMask>
26784          <fields>
26785            <field>
26786              <name>HIGH_PHASE_OVS</name>
26787              <description>Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering.
26788
26789The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be &gt;= 6 IP clock cycles and &lt;= 16 IP clock cycles. Without input signal median filtering, the IF high time should be &gt;= 5 IP clock cycles and &lt;= 16 IP clock cycles.</description>
26790              <bitRange>[3:0]</bitRange>
26791              <access>read-write</access>
26792            </field>
26793            <field>
26794              <name>LOW_PHASE_OVS</name>
26795              <description>Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering.
26796
26797The field is mainly used in master mode. In slave mode, there is a frequency requirement for the IP clock wrt. the regular (no stretching) interface (IF) low time to guarantee functional correct behavior. With input signal median filtering, the IF low time should be &gt;= 8 IP clock cycles and &lt;= 16 IP clock cycles. Without input signal median filtering, the IF low time should be &gt;= 7 IP clock cycles and &lt;= 16 IP clock cycles.
26798
26799in slave mode, this field is used to define number of clk_scb cycles for tSU-DAT timing (from ACK/NACK/data ready, to SCL rising edge (released from I2C slave clock stretching))</description>
26800              <bitRange>[7:4]</bitRange>
26801              <access>read-write</access>
26802            </field>
26803            <field>
26804              <name>M_READY_DATA_ACK</name>
26805              <description>When '1', a received data element by the master is immediately ACK'd when the receiver FIFO is not full.</description>
26806              <bitRange>[8:8]</bitRange>
26807              <access>read-write</access>
26808            </field>
26809            <field>
26810              <name>M_NOT_READY_DATA_NACK</name>
26811              <description>When '1', a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0', clock stretching is used instead (till the receiver FIFO is no longer full).</description>
26812              <bitRange>[9:9]</bitRange>
26813              <access>read-write</access>
26814            </field>
26815            <field>
26816              <name>S_GENERAL_IGNORE</name>
26817              <description>When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure.</description>
26818              <bitRange>[11:11]</bitRange>
26819              <access>read-write</access>
26820            </field>
26821            <field>
26822              <name>S_READY_ADDR_ACK</name>
26823              <description>When '1', a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'.</description>
26824              <bitRange>[12:12]</bitRange>
26825              <access>read-write</access>
26826            </field>
26827            <field>
26828              <name>S_READY_DATA_ACK</name>
26829              <description>When '1', a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'.</description>
26830              <bitRange>[13:13]</bitRange>
26831              <access>read-write</access>
26832            </field>
26833            <field>
26834              <name>S_NOT_READY_ADDR_NACK</name>
26835              <description>For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:
26836- EC_AM is '0', EC_OP is '0' and non EZ mode.
26837Functionality is as follows:
26838- 1: a received (matching) slave address is immediately NACK'd when the receiver FIFO is full.
26839- 0: clock stretching is performed (till the receiver FIFO is no longer full).
26840
26841For externally clocked logic (EC_AM is '1') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when (NOT used when EC_AM is '1' and EC_OP is '1' and address match and EZ mode):
26842- EC_AM is '1' and EC_OP is '0'.
26843- EC_AM is '1' and general call address match.
26844- EC_AM is '1' and non EZ mode.
26845Functionality is as follows:
26846- 1: a received (matching or general) slave address is always immediately NACK'd. There are two possibilities: 1). the internally clocked logic is enabled (we are in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK. 2). the internally clocked logic is not enabled (we are in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode).
26847- 0: clock stretching is performed (till the internally clocked logic takes over). The internally clocked logic will handle the ongoing transfer as soon as it is enabled.</description>
26848              <bitRange>[14:14]</bitRange>
26849              <access>read-write</access>
26850            </field>
26851            <field>
26852              <name>S_NOT_READY_DATA_NACK</name>
26853              <description>For internally clocked logic only. Only used when:
26854- non EZ mode.
26855Functionality is as follows:
26856- 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full.
26857- 0: clock stretching is performed (till the receiver FIFO is no longer full).</description>
26858              <bitRange>[15:15]</bitRange>
26859              <access>read-write</access>
26860            </field>
26861            <field>
26862              <name>LOOPBACK</name>
26863              <description>Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0', the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1', I2C SCL and SDA lines are routed internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself.</description>
26864              <bitRange>[16:16]</bitRange>
26865              <access>read-write</access>
26866            </field>
26867            <field>
26868              <name>SLAVE_MODE</name>
26869              <description>Slave mode enabled ('1') or not ('0').</description>
26870              <bitRange>[30:30]</bitRange>
26871              <access>read-write</access>
26872            </field>
26873            <field>
26874              <name>MASTER_MODE</name>
26875              <description>Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself.</description>
26876              <bitRange>[31:31]</bitRange>
26877              <access>read-write</access>
26878            </field>
26879          </fields>
26880        </register>
26881        <register>
26882          <name>I2C_STATUS</name>
26883          <description>I2C status</description>
26884          <addressOffset>0x64</addressOffset>
26885          <size>32</size>
26886          <access>read-only</access>
26887          <resetValue>0x0</resetValue>
26888          <resetMask>0x35</resetMask>
26889          <fields>
26890            <field>
26891              <name>BUS_BUSY</name>
26892              <description>I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If the IP is disabled, BUS_BUSY is '0'. After enabling the IP, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period).
26893
26894For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions).
26895
26896For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions).</description>
26897              <bitRange>[0:0]</bitRange>
26898              <access>read-only</access>
26899            </field>
26900            <field>
26901              <name>I2C_EC_BUSY</name>
26902              <description>Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and CURR_EZ_ADDR are reliable.</description>
26903              <bitRange>[1:1]</bitRange>
26904              <access>read-only</access>
26905            </field>
26906            <field>
26907              <name>I2CS_IC_BUSY</name>
26908              <description>Indicates whether the internally clocked slave logic is being accessed by external I2C master.
26909--set at ADDR_MATCH
26910--clear at START/RESET, STOP detection, or BUS_ERROR
26911This bit can be used by SW to determine whether I2CS_IC is busy before entering DeepSleep.</description>
26912              <bitRange>[2:2]</bitRange>
26913              <access>read-only</access>
26914            </field>
26915            <field>
26916              <name>S_READ</name>
26917              <description>I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0''.</description>
26918              <bitRange>[4:4]</bitRange>
26919              <access>read-only</access>
26920            </field>
26921            <field>
26922              <name>M_READ</name>
26923              <description>I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START, REPEATED START, STOP or an address, this field is '0''.</description>
26924              <bitRange>[5:5]</bitRange>
26925              <access>read-only</access>
26926            </field>
26927            <field>
26928              <name>CURR_EZ_ADDR</name>
26929              <description>I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1'), as clock domain synchronization is not performed in the design.</description>
26930              <bitRange>[15:8]</bitRange>
26931              <access>read-only</access>
26932            </field>
26933            <field>
26934              <name>BASE_EZ_ADDR</name>
26935              <description>I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design.</description>
26936              <bitRange>[23:16]</bitRange>
26937              <access>read-only</access>
26938            </field>
26939          </fields>
26940        </register>
26941        <register>
26942          <name>I2C_M_CMD</name>
26943          <description>I2C master command</description>
26944          <addressOffset>0x68</addressOffset>
26945          <size>32</size>
26946          <access>read-write</access>
26947          <resetValue>0x0</resetValue>
26948          <resetMask>0x1F</resetMask>
26949          <fields>
26950            <field>
26951              <name>M_START</name>
26952              <description>When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'.</description>
26953              <bitRange>[0:0]</bitRange>
26954              <access>read-write</access>
26955            </field>
26956            <field>
26957              <name>M_START_ON_IDLE</name>
26958              <description>When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'.</description>
26959              <bitRange>[1:1]</bitRange>
26960              <access>read-write</access>
26961            </field>
26962            <field>
26963              <name>M_ACK</name>
26964              <description>When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'.</description>
26965              <bitRange>[2:2]</bitRange>
26966              <access>read-write</access>
26967            </field>
26968            <field>
26969              <name>M_NACK</name>
26970              <description>When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'.</description>
26971              <bitRange>[3:3]</bitRange>
26972              <access>read-write</access>
26973            </field>
26974            <field>
26975              <name>M_STOP</name>
26976              <description>When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'.
26977 I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP.</description>
26978              <bitRange>[4:4]</bitRange>
26979              <access>read-write</access>
26980            </field>
26981          </fields>
26982        </register>
26983        <register>
26984          <name>I2C_S_CMD</name>
26985          <description>I2C slave command</description>
26986          <addressOffset>0x6C</addressOffset>
26987          <size>32</size>
26988          <access>read-write</access>
26989          <resetValue>0x0</resetValue>
26990          <resetMask>0x3</resetMask>
26991          <fields>
26992            <field>
26993              <name>S_ACK</name>
26994              <description>When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode).</description>
26995              <bitRange>[0:0]</bitRange>
26996              <access>read-write</access>
26997            </field>
26998            <field>
26999              <name>S_NACK</name>
27000              <description>When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'.  In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK.</description>
27001              <bitRange>[1:1]</bitRange>
27002              <access>read-write</access>
27003            </field>
27004          </fields>
27005        </register>
27006        <register>
27007          <name>I2C_CFG</name>
27008          <description>I2C configuration</description>
27009          <addressOffset>0x70</addressOffset>
27010          <size>32</size>
27011          <access>read-write</access>
27012          <resetValue>0x2A1013</resetValue>
27013          <resetMask>0x303F1313</resetMask>
27014          <fields>
27015            <field>
27016              <name>SDA_IN_FILT_TRIM</name>
27017              <description>Trim bits for 'i2c_sda_in' 50 ns filter.
27018for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values.
27019For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values.</description>
27020              <bitRange>[1:0]</bitRange>
27021              <access>read-write</access>
27022            </field>
27023            <field>
27024              <name>SDA_IN_FILT_SEL</name>
27025              <description>Selection of 'i2c_sda_in' filter delay:
27026'0': 0 ns.
27027'1: 50 ns (filter enabled).</description>
27028              <bitRange>[4:4]</bitRange>
27029              <access>read-write</access>
27030            </field>
27031            <field>
27032              <name>SCL_IN_FILT_TRIM</name>
27033              <description>Trim bits for 'i2c_scl_in' 50 ns filter.
27034for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values.
27035For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values.</description>
27036              <bitRange>[9:8]</bitRange>
27037              <access>read-write</access>
27038            </field>
27039            <field>
27040              <name>SCL_IN_FILT_SEL</name>
27041              <description>Selection of 'i2c_scl_in' filter delay:
27042'0': 0 ns.
27043'1: 50 ns (filter enabled).</description>
27044              <bitRange>[12:12]</bitRange>
27045              <access>read-write</access>
27046            </field>
27047            <field>
27048              <name>SDA_OUT_FILT0_TRIM</name>
27049              <description>Trim bits for 'i2c_sda_out' 50 ns filter 0.
27050for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values.
27051For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values.</description>
27052              <bitRange>[17:16]</bitRange>
27053              <access>read-write</access>
27054            </field>
27055            <field>
27056              <name>SDA_OUT_FILT1_TRIM</name>
27057              <description>Trim bits for 'i2c_sda_out' 50 ns filter 1.
27058for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values.
27059For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values.</description>
27060              <bitRange>[19:18]</bitRange>
27061              <access>read-write</access>
27062            </field>
27063            <field>
27064              <name>SDA_OUT_FILT2_TRIM</name>
27065              <description>Trim bits for 'i2c_sda_out' 50 ns filter 2.
27066for M0S8 platform, see s8i2cs BROS (001-59539) for more details on the trim bit values.
27067For MXS40 platform, only the Least Significant Bit (LSB) is used, see s40iolib BROS (002-02511) for more details on the trim bit values.</description>
27068              <bitRange>[21:20]</bitRange>
27069              <access>read-write</access>
27070            </field>
27071            <field>
27072              <name>SDA_OUT_FILT_SEL</name>
27073              <description>Selection of cumulative 'i2c_sda_out' filter delay:
27074'0': 0 ns.
27075'1': 50 ns (filter 0 enabled).
27076'2': 100 ns (filters 0 and 1 enabled).
27077'3': 150 ns (filters 0, 1 and 2 enabled).</description>
27078              <bitRange>[29:28]</bitRange>
27079              <access>read-write</access>
27080            </field>
27081          </fields>
27082        </register>
27083        <register>
27084          <name>TX_CTRL</name>
27085          <description>Transmitter control</description>
27086          <addressOffset>0x200</addressOffset>
27087          <size>32</size>
27088          <access>read-write</access>
27089          <resetValue>0x107</resetValue>
27090          <resetMask>0x1011F</resetMask>
27091          <fields>
27092            <field>
27093              <name>DATA_WIDTH</name>
27094              <description>Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 31]. For I2C the only valid value is 7.</description>
27095              <bitRange>[4:0]</bitRange>
27096              <access>read-write</access>
27097            </field>
27098            <field>
27099              <name>MSB_FIRST</name>
27100              <description>Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'.</description>
27101              <bitRange>[8:8]</bitRange>
27102              <access>read-write</access>
27103            </field>
27104            <field>
27105              <name>OPEN_DRAIN</name>
27106              <description>Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'.
27107'0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'.
27108'1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1').
27109
27110The open drain mode is supported for:
27111- UART mode, 'uart_tx' IO cell.
27112- SPI mode, 'spi_miso' IO cell.
27113
27114not applicable to I2C mode, 'i2c_scl' and 'i2c_sda' IO cells. (I2C SCL/SDA always work in open-drain mode)</description>
27115              <bitRange>[16:16]</bitRange>
27116              <access>read-write</access>
27117            </field>
27118          </fields>
27119        </register>
27120        <register>
27121          <name>TX_FIFO_CTRL</name>
27122          <description>Transmitter FIFO control</description>
27123          <addressOffset>0x204</addressOffset>
27124          <size>32</size>
27125          <access>read-write</access>
27126          <resetValue>0x0</resetValue>
27127          <resetMask>0x300FF</resetMask>
27128          <fields>
27129            <field>
27130              <name>TRIGGER_LEVEL</name>
27131              <description>Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event INTR_TX.TRIGGER is generated.</description>
27132              <bitRange>[7:0]</bitRange>
27133              <access>read-write</access>
27134            </field>
27135            <field>
27136              <name>CLEAR</name>
27137              <description>When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
27138              <bitRange>[16:16]</bitRange>
27139              <access>read-write</access>
27140            </field>
27141            <field>
27142              <name>FREEZE</name>
27143              <description>When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer.</description>
27144              <bitRange>[17:17]</bitRange>
27145              <access>read-write</access>
27146            </field>
27147          </fields>
27148        </register>
27149        <register>
27150          <name>TX_FIFO_STATUS</name>
27151          <description>Transmitter FIFO status</description>
27152          <addressOffset>0x208</addressOffset>
27153          <size>32</size>
27154          <access>read-only</access>
27155          <resetValue>0x0</resetValue>
27156          <resetMask>0xFFFF81FF</resetMask>
27157          <fields>
27158            <field>
27159              <name>USED</name>
27160              <description>Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2).</description>
27161              <bitRange>[8:0]</bitRange>
27162              <access>read-only</access>
27163            </field>
27164            <field>
27165              <name>SR_VALID</name>
27166              <description>Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is transmitted next (when the protocol state machine is not transmitting a data frame).</description>
27167              <bitRange>[15:15]</bitRange>
27168              <access>read-only</access>
27169            </field>
27170            <field>
27171              <name>RD_PTR</name>
27172              <description>FIFO read pointer: FIFO location from which a data frame is read by the hardware.</description>
27173              <bitRange>[23:16]</bitRange>
27174              <access>read-only</access>
27175            </field>
27176            <field>
27177              <name>WR_PTR</name>
27178              <description>FIFO write pointer: FIFO location at which a new data frame is written.</description>
27179              <bitRange>[31:24]</bitRange>
27180              <access>read-only</access>
27181            </field>
27182          </fields>
27183        </register>
27184        <register>
27185          <name>TX_FIFO_WR</name>
27186          <description>Transmitter FIFO write</description>
27187          <addressOffset>0x240</addressOffset>
27188          <size>32</size>
27189          <access>write-only</access>
27190          <resetValue>0x0</resetValue>
27191          <resetMask>0xFFFFFFFF</resetMask>
27192          <fields>
27193            <field>
27194              <name>DATA</name>
27195              <description>Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0', only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1', only DATA[15:0] are used.
27196
27197A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'.</description>
27198              <bitRange>[31:0]</bitRange>
27199              <access>write-only</access>
27200            </field>
27201          </fields>
27202        </register>
27203        <register>
27204          <name>RX_CTRL</name>
27205          <description>Receiver control</description>
27206          <addressOffset>0x300</addressOffset>
27207          <size>32</size>
27208          <access>read-write</access>
27209          <resetValue>0x107</resetValue>
27210          <resetMask>0x31F</resetMask>
27211          <fields>
27212            <field>
27213              <name>DATA_WIDTH</name>
27214              <description>Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 31]. For I2C the only valid value is 7. In EZ mode (for both SPI and I2C), the only valid value is 7.</description>
27215              <bitRange>[4:0]</bitRange>
27216              <access>read-write</access>
27217            </field>
27218            <field>
27219              <name>MSB_FIRST</name>
27220              <description>Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'.</description>
27221              <bitRange>[8:8]</bitRange>
27222              <access>read-write</access>
27223            </field>
27224            <field>
27225              <name>MEDIAN</name>
27226              <description>Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'.</description>
27227              <bitRange>[9:9]</bitRange>
27228              <access>read-write</access>
27229            </field>
27230          </fields>
27231        </register>
27232        <register>
27233          <name>RX_FIFO_CTRL</name>
27234          <description>Receiver FIFO control</description>
27235          <addressOffset>0x304</addressOffset>
27236          <size>32</size>
27237          <access>read-write</access>
27238          <resetValue>0x0</resetValue>
27239          <resetMask>0x300FF</resetMask>
27240          <fields>
27241            <field>
27242              <name>TRIGGER_LEVEL</name>
27243              <description>Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event INTR_RX.TRIGGER is generated.</description>
27244              <bitRange>[7:0]</bitRange>
27245              <access>read-write</access>
27246            </field>
27247            <field>
27248              <name>CLEAR</name>
27249              <description>When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
27250              <bitRange>[16:16]</bitRange>
27251              <access>read-write</access>
27252            </field>
27253            <field>
27254              <name>FREEZE</name>
27255              <description>When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer.</description>
27256              <bitRange>[17:17]</bitRange>
27257              <access>read-write</access>
27258            </field>
27259          </fields>
27260        </register>
27261        <register>
27262          <name>RX_FIFO_STATUS</name>
27263          <description>Receiver FIFO status</description>
27264          <addressOffset>0x308</addressOffset>
27265          <size>32</size>
27266          <access>read-only</access>
27267          <resetValue>0x0</resetValue>
27268          <resetMask>0xFFFF81FF</resetMask>
27269          <fields>
27270            <field>
27271              <name>USED</name>
27272              <description>Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR  (EZ_DATA_NR/2).</description>
27273              <bitRange>[8:0]</bitRange>
27274              <access>read-only</access>
27275            </field>
27276            <field>
27277              <name>SR_VALID</name>
27278              <description>Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame).</description>
27279              <bitRange>[15:15]</bitRange>
27280              <access>read-only</access>
27281            </field>
27282            <field>
27283              <name>RD_PTR</name>
27284              <description>FIFO read pointer: FIFO location from which a data frame is read.</description>
27285              <bitRange>[23:16]</bitRange>
27286              <access>read-only</access>
27287            </field>
27288            <field>
27289              <name>WR_PTR</name>
27290              <description>FIFO write pointer: FIFO location at which a new data frame is written by the hardware.</description>
27291              <bitRange>[31:24]</bitRange>
27292              <access>read-only</access>
27293            </field>
27294          </fields>
27295        </register>
27296        <register>
27297          <name>RX_MATCH</name>
27298          <description>Slave address and mask</description>
27299          <addressOffset>0x310</addressOffset>
27300          <size>32</size>
27301          <access>read-write</access>
27302          <resetValue>0x0</resetValue>
27303          <resetMask>0xFF00FF</resetMask>
27304          <fields>
27305            <field>
27306              <name>ADDR</name>
27307              <description>Slave device address.
27308
27309In UART multi-processor mode, all 8 bits are used.
27310
27311In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read).</description>
27312              <bitRange>[7:0]</bitRange>
27313              <access>read-write</access>
27314            </field>
27315            <field>
27316              <name>MASK</name>
27317              <description>Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR &amp; MASK) == ('slave address' &amp; MASK)).</description>
27318              <bitRange>[23:16]</bitRange>
27319              <access>read-write</access>
27320            </field>
27321          </fields>
27322        </register>
27323        <register>
27324          <name>RX_FIFO_RD</name>
27325          <description>Receiver FIFO read</description>
27326          <addressOffset>0x340</addressOffset>
27327          <size>32</size>
27328          <access>read-only</access>
27329          <resetValue>0x0</resetValue>
27330          <resetMask>0x0</resetMask>
27331          <fields>
27332            <field>
27333              <name>DATA</name>
27334              <description>Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0', only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1', only DATA[15:0] are used.
27335
27336This register has a side effect when read by software: a data frame is removed from the FIFO. This may be undesirable during debug; i.e. a read during debug should NOT have a side effect. To this end, the IP uses the AHB-Lite 'hmaster[0]' input signal. When this signal is '1' in the address cycle of a bus transfer, a read transfer will not have a side effect. As a result, a read from this register will not remove a data frame from the FIFO. As a result, a read from this register behaves as a read from the SCB_RX_FIFO_RD_SILENT register.
27337
27338A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'.</description>
27339              <bitRange>[31:0]</bitRange>
27340              <access>read-only</access>
27341            </field>
27342          </fields>
27343        </register>
27344        <register>
27345          <name>RX_FIFO_RD_SILENT</name>
27346          <description>Receiver FIFO read silent</description>
27347          <addressOffset>0x344</addressOffset>
27348          <size>32</size>
27349          <access>read-only</access>
27350          <resetValue>0x0</resetValue>
27351          <resetMask>0x0</resetMask>
27352          <fields>
27353            <field>
27354              <name>DATA</name>
27355              <description>Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0', only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1', only DATA[15:0] are used
27356
27357A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'.</description>
27358              <bitRange>[31:0]</bitRange>
27359              <access>read-only</access>
27360            </field>
27361          </fields>
27362        </register>
27363        <register>
27364          <name>INTR_CAUSE</name>
27365          <description>Active clocked interrupt signal</description>
27366          <addressOffset>0xE00</addressOffset>
27367          <size>32</size>
27368          <access>read-only</access>
27369          <resetValue>0x0</resetValue>
27370          <resetMask>0x3F</resetMask>
27371          <fields>
27372            <field>
27373              <name>M</name>
27374              <description>Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0.</description>
27375              <bitRange>[0:0]</bitRange>
27376              <access>read-only</access>
27377            </field>
27378            <field>
27379              <name>S</name>
27380              <description>Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0.</description>
27381              <bitRange>[1:1]</bitRange>
27382              <access>read-only</access>
27383            </field>
27384            <field>
27385              <name>TX</name>
27386              <description>Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0.</description>
27387              <bitRange>[2:2]</bitRange>
27388              <access>read-only</access>
27389            </field>
27390            <field>
27391              <name>RX</name>
27392              <description>Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0.</description>
27393              <bitRange>[3:3]</bitRange>
27394              <access>read-only</access>
27395            </field>
27396            <field>
27397              <name>I2C_EC</name>
27398              <description>Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0.</description>
27399              <bitRange>[4:4]</bitRange>
27400              <access>read-only</access>
27401            </field>
27402            <field>
27403              <name>SPI_EC</name>
27404              <description>Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0.</description>
27405              <bitRange>[5:5]</bitRange>
27406              <access>read-only</access>
27407            </field>
27408          </fields>
27409        </register>
27410        <register>
27411          <name>INTR_I2C_EC</name>
27412          <description>Externally clocked I2C interrupt request</description>
27413          <addressOffset>0xE80</addressOffset>
27414          <size>32</size>
27415          <access>read-write</access>
27416          <resetValue>0x0</resetValue>
27417          <resetMask>0xF</resetMask>
27418          <fields>
27419            <field>
27420              <name>WAKE_UP</name>
27421              <description>Wake up request. Active on incoming slave request (with address match).
27422
27423Only used when EC_AM is '1'.</description>
27424              <bitRange>[0:0]</bitRange>
27425              <access>read-write</access>
27426            </field>
27427            <field>
27428              <name>EZ_STOP</name>
27429              <description>STOP detection. Activated on the end of a every transfer (I2C STOP).
27430
27431Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'.</description>
27432              <bitRange>[1:1]</bitRange>
27433              <access>read-write</access>
27434            </field>
27435            <field>
27436              <name>EZ_WRITE_STOP</name>
27437              <description>STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a  transfer that only writes the base address does NOT activate this event.
27438
27439Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'.</description>
27440              <bitRange>[2:2]</bitRange>
27441              <access>read-write</access>
27442            </field>
27443            <field>
27444              <name>EZ_READ_STOP</name>
27445              <description>STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from.
27446
27447Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'.</description>
27448              <bitRange>[3:3]</bitRange>
27449              <access>read-write</access>
27450            </field>
27451          </fields>
27452        </register>
27453        <register>
27454          <name>INTR_I2C_EC_MASK</name>
27455          <description>Externally clocked I2C interrupt mask</description>
27456          <addressOffset>0xE88</addressOffset>
27457          <size>32</size>
27458          <access>read-write</access>
27459          <resetValue>0x0</resetValue>
27460          <resetMask>0xF</resetMask>
27461          <fields>
27462            <field>
27463              <name>WAKE_UP</name>
27464              <description>Mask bit for corresponding bit in interrupt request register.</description>
27465              <bitRange>[0:0]</bitRange>
27466              <access>read-write</access>
27467            </field>
27468            <field>
27469              <name>EZ_STOP</name>
27470              <description>Mask bit for corresponding bit in interrupt request register.</description>
27471              <bitRange>[1:1]</bitRange>
27472              <access>read-write</access>
27473            </field>
27474            <field>
27475              <name>EZ_WRITE_STOP</name>
27476              <description>Mask bit for corresponding bit in interrupt request register.</description>
27477              <bitRange>[2:2]</bitRange>
27478              <access>read-write</access>
27479            </field>
27480            <field>
27481              <name>EZ_READ_STOP</name>
27482              <description>Mask bit for corresponding bit in interrupt request register.</description>
27483              <bitRange>[3:3]</bitRange>
27484              <access>read-write</access>
27485            </field>
27486          </fields>
27487        </register>
27488        <register>
27489          <name>INTR_I2C_EC_MASKED</name>
27490          <description>Externally clocked I2C interrupt masked</description>
27491          <addressOffset>0xE8C</addressOffset>
27492          <size>32</size>
27493          <access>read-only</access>
27494          <resetValue>0x0</resetValue>
27495          <resetMask>0xF</resetMask>
27496          <fields>
27497            <field>
27498              <name>WAKE_UP</name>
27499              <description>Logical and of corresponding request and mask bits.</description>
27500              <bitRange>[0:0]</bitRange>
27501              <access>read-only</access>
27502            </field>
27503            <field>
27504              <name>EZ_STOP</name>
27505              <description>Logical and of corresponding request and mask bits.</description>
27506              <bitRange>[1:1]</bitRange>
27507              <access>read-only</access>
27508            </field>
27509            <field>
27510              <name>EZ_WRITE_STOP</name>
27511              <description>Logical and of corresponding request and mask bits.</description>
27512              <bitRange>[2:2]</bitRange>
27513              <access>read-only</access>
27514            </field>
27515            <field>
27516              <name>EZ_READ_STOP</name>
27517              <description>Logical and of corresponding request and mask bits.</description>
27518              <bitRange>[3:3]</bitRange>
27519              <access>read-only</access>
27520            </field>
27521          </fields>
27522        </register>
27523        <register>
27524          <name>INTR_SPI_EC</name>
27525          <description>Externally clocked SPI interrupt request</description>
27526          <addressOffset>0xEC0</addressOffset>
27527          <size>32</size>
27528          <access>read-write</access>
27529          <resetValue>0x0</resetValue>
27530          <resetMask>0xF</resetMask>
27531          <fields>
27532            <field>
27533              <name>WAKE_UP</name>
27534              <description>Wake up request. Active on incoming slave request when externally clocked selection is '1'.
27535
27536Only used when EC_AM is '1'.</description>
27537              <bitRange>[0:0]</bitRange>
27538              <access>read-write</access>
27539            </field>
27540            <field>
27541              <name>EZ_STOP</name>
27542              <description>STOP detection. Activated on the end of a every transfer (SPI deselection).
27543
27544Only available in EZ and CMD_RESP mode and when EC_OP is '1'.</description>
27545              <bitRange>[1:1]</bitRange>
27546              <access>read-write</access>
27547            </field>
27548            <field>
27549              <name>EZ_WRITE_STOP</name>
27550              <description>STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a  transfer that only writes the base address does NOT activate this event.
27551
27552Only used in EZ and CMD_RESP modes and when EC_OP is '1'.</description>
27553              <bitRange>[2:2]</bitRange>
27554              <access>read-write</access>
27555            </field>
27556            <field>
27557              <name>EZ_READ_STOP</name>
27558              <description>STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from.
27559
27560Only used in EZ and CMD_RESP modes and when EC_OP is '1'.</description>
27561              <bitRange>[3:3]</bitRange>
27562              <access>read-write</access>
27563            </field>
27564          </fields>
27565        </register>
27566        <register>
27567          <name>INTR_SPI_EC_MASK</name>
27568          <description>Externally clocked SPI interrupt mask</description>
27569          <addressOffset>0xEC8</addressOffset>
27570          <size>32</size>
27571          <access>read-write</access>
27572          <resetValue>0x0</resetValue>
27573          <resetMask>0xF</resetMask>
27574          <fields>
27575            <field>
27576              <name>WAKE_UP</name>
27577              <description>Mask bit for corresponding bit in interrupt request register.</description>
27578              <bitRange>[0:0]</bitRange>
27579              <access>read-write</access>
27580            </field>
27581            <field>
27582              <name>EZ_STOP</name>
27583              <description>Mask bit for corresponding bit in interrupt request register.</description>
27584              <bitRange>[1:1]</bitRange>
27585              <access>read-write</access>
27586            </field>
27587            <field>
27588              <name>EZ_WRITE_STOP</name>
27589              <description>Mask bit for corresponding bit in interrupt request register.</description>
27590              <bitRange>[2:2]</bitRange>
27591              <access>read-write</access>
27592            </field>
27593            <field>
27594              <name>EZ_READ_STOP</name>
27595              <description>Mask bit for corresponding bit in interrupt request register.</description>
27596              <bitRange>[3:3]</bitRange>
27597              <access>read-write</access>
27598            </field>
27599          </fields>
27600        </register>
27601        <register>
27602          <name>INTR_SPI_EC_MASKED</name>
27603          <description>Externally clocked SPI interrupt masked</description>
27604          <addressOffset>0xECC</addressOffset>
27605          <size>32</size>
27606          <access>read-only</access>
27607          <resetValue>0x0</resetValue>
27608          <resetMask>0xF</resetMask>
27609          <fields>
27610            <field>
27611              <name>WAKE_UP</name>
27612              <description>Logical and of corresponding request and mask bits.</description>
27613              <bitRange>[0:0]</bitRange>
27614              <access>read-only</access>
27615            </field>
27616            <field>
27617              <name>EZ_STOP</name>
27618              <description>Logical and of corresponding request and mask bits.</description>
27619              <bitRange>[1:1]</bitRange>
27620              <access>read-only</access>
27621            </field>
27622            <field>
27623              <name>EZ_WRITE_STOP</name>
27624              <description>Logical and of corresponding request and mask bits.</description>
27625              <bitRange>[2:2]</bitRange>
27626              <access>read-only</access>
27627            </field>
27628            <field>
27629              <name>EZ_READ_STOP</name>
27630              <description>Logical and of corresponding request and mask bits.</description>
27631              <bitRange>[3:3]</bitRange>
27632              <access>read-only</access>
27633            </field>
27634          </fields>
27635        </register>
27636        <register>
27637          <name>INTR_M</name>
27638          <description>Master interrupt request</description>
27639          <addressOffset>0xF00</addressOffset>
27640          <size>32</size>
27641          <access>read-write</access>
27642          <resetValue>0x0</resetValue>
27643          <resetMask>0x317</resetMask>
27644          <fields>
27645            <field>
27646              <name>I2C_ARB_LOST</name>
27647              <description>I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line.</description>
27648              <bitRange>[0:0]</bitRange>
27649              <access>read-write</access>
27650            </field>
27651            <field>
27652              <name>I2C_NACK</name>
27653              <description>I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data).</description>
27654              <bitRange>[1:1]</bitRange>
27655              <access>read-write</access>
27656            </field>
27657            <field>
27658              <name>I2C_ACK</name>
27659              <description>I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data).</description>
27660              <bitRange>[2:2]</bitRange>
27661              <access>read-write</access>
27662            </field>
27663            <field>
27664              <name>I2C_STOP</name>
27665              <description>I2C master STOP. Set to '1', when the master has transmitted a STOP.</description>
27666              <bitRange>[4:4]</bitRange>
27667              <access>read-write</access>
27668            </field>
27669            <field>
27670              <name>I2C_BUS_ERROR</name>
27671              <description>I2C master bus error (unexpected detection of START or STOP condition).</description>
27672              <bitRange>[8:8]</bitRange>
27673              <access>read-write</access>
27674            </field>
27675            <field>
27676              <name>SPI_DONE</name>
27677              <description>SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected.</description>
27678              <bitRange>[9:9]</bitRange>
27679              <access>read-write</access>
27680            </field>
27681          </fields>
27682        </register>
27683        <register>
27684          <name>INTR_M_SET</name>
27685          <description>Master interrupt set request</description>
27686          <addressOffset>0xF04</addressOffset>
27687          <size>32</size>
27688          <access>read-write</access>
27689          <resetValue>0x0</resetValue>
27690          <resetMask>0x317</resetMask>
27691          <fields>
27692            <field>
27693              <name>I2C_ARB_LOST</name>
27694              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27695              <bitRange>[0:0]</bitRange>
27696              <access>read-write</access>
27697            </field>
27698            <field>
27699              <name>I2C_NACK</name>
27700              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27701              <bitRange>[1:1]</bitRange>
27702              <access>read-write</access>
27703            </field>
27704            <field>
27705              <name>I2C_ACK</name>
27706              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27707              <bitRange>[2:2]</bitRange>
27708              <access>read-write</access>
27709            </field>
27710            <field>
27711              <name>I2C_STOP</name>
27712              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27713              <bitRange>[4:4]</bitRange>
27714              <access>read-write</access>
27715            </field>
27716            <field>
27717              <name>I2C_BUS_ERROR</name>
27718              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27719              <bitRange>[8:8]</bitRange>
27720              <access>read-write</access>
27721            </field>
27722            <field>
27723              <name>SPI_DONE</name>
27724              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27725              <bitRange>[9:9]</bitRange>
27726              <access>read-write</access>
27727            </field>
27728          </fields>
27729        </register>
27730        <register>
27731          <name>INTR_M_MASK</name>
27732          <description>Master interrupt mask</description>
27733          <addressOffset>0xF08</addressOffset>
27734          <size>32</size>
27735          <access>read-write</access>
27736          <resetValue>0x0</resetValue>
27737          <resetMask>0x317</resetMask>
27738          <fields>
27739            <field>
27740              <name>I2C_ARB_LOST</name>
27741              <description>Mask bit for corresponding bit in interrupt request register.</description>
27742              <bitRange>[0:0]</bitRange>
27743              <access>read-write</access>
27744            </field>
27745            <field>
27746              <name>I2C_NACK</name>
27747              <description>Mask bit for corresponding bit in interrupt request register.</description>
27748              <bitRange>[1:1]</bitRange>
27749              <access>read-write</access>
27750            </field>
27751            <field>
27752              <name>I2C_ACK</name>
27753              <description>Mask bit for corresponding bit in interrupt request register.</description>
27754              <bitRange>[2:2]</bitRange>
27755              <access>read-write</access>
27756            </field>
27757            <field>
27758              <name>I2C_STOP</name>
27759              <description>Mask bit for corresponding bit in interrupt request register.</description>
27760              <bitRange>[4:4]</bitRange>
27761              <access>read-write</access>
27762            </field>
27763            <field>
27764              <name>I2C_BUS_ERROR</name>
27765              <description>Mask bit for corresponding bit in interrupt request register.</description>
27766              <bitRange>[8:8]</bitRange>
27767              <access>read-write</access>
27768            </field>
27769            <field>
27770              <name>SPI_DONE</name>
27771              <description>Mask bit for corresponding bit in interrupt request register.</description>
27772              <bitRange>[9:9]</bitRange>
27773              <access>read-write</access>
27774            </field>
27775          </fields>
27776        </register>
27777        <register>
27778          <name>INTR_M_MASKED</name>
27779          <description>Master interrupt masked request</description>
27780          <addressOffset>0xF0C</addressOffset>
27781          <size>32</size>
27782          <access>read-only</access>
27783          <resetValue>0x0</resetValue>
27784          <resetMask>0x317</resetMask>
27785          <fields>
27786            <field>
27787              <name>I2C_ARB_LOST</name>
27788              <description>Logical and of corresponding request and mask bits.</description>
27789              <bitRange>[0:0]</bitRange>
27790              <access>read-only</access>
27791            </field>
27792            <field>
27793              <name>I2C_NACK</name>
27794              <description>Logical and of corresponding request and mask bits.</description>
27795              <bitRange>[1:1]</bitRange>
27796              <access>read-only</access>
27797            </field>
27798            <field>
27799              <name>I2C_ACK</name>
27800              <description>Logical and of corresponding request and mask bits.</description>
27801              <bitRange>[2:2]</bitRange>
27802              <access>read-only</access>
27803            </field>
27804            <field>
27805              <name>I2C_STOP</name>
27806              <description>Logical and of corresponding request and mask bits.</description>
27807              <bitRange>[4:4]</bitRange>
27808              <access>read-only</access>
27809            </field>
27810            <field>
27811              <name>I2C_BUS_ERROR</name>
27812              <description>Logical and of corresponding request and mask bits.</description>
27813              <bitRange>[8:8]</bitRange>
27814              <access>read-only</access>
27815            </field>
27816            <field>
27817              <name>SPI_DONE</name>
27818              <description>Logical and of corresponding request and mask bits.</description>
27819              <bitRange>[9:9]</bitRange>
27820              <access>read-only</access>
27821            </field>
27822          </fields>
27823        </register>
27824        <register>
27825          <name>INTR_S</name>
27826          <description>Slave interrupt request</description>
27827          <addressOffset>0xF40</addressOffset>
27828          <size>32</size>
27829          <access>read-write</access>
27830          <resetValue>0x0</resetValue>
27831          <resetMask>0xFFF</resetMask>
27832          <fields>
27833            <field>
27834              <name>I2C_ARB_LOST</name>
27835              <description>I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error.</description>
27836              <bitRange>[0:0]</bitRange>
27837              <access>read-write</access>
27838            </field>
27839            <field>
27840              <name>I2C_NACK</name>
27841              <description>I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data).</description>
27842              <bitRange>[1:1]</bitRange>
27843              <access>read-write</access>
27844            </field>
27845            <field>
27846              <name>I2C_ACK</name>
27847              <description>I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data).</description>
27848              <bitRange>[2:2]</bitRange>
27849              <access>read-write</access>
27850            </field>
27851            <field>
27852              <name>I2C_WRITE_STOP</name>
27853              <description>I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address.
27854
27855In non EZ mode, the event is detected on any I2C write transfer intended for this slave. Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd.
27856
27857In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ address, will not result in this event being detected).</description>
27858              <bitRange>[3:3]</bitRange>
27859              <access>read-write</access>
27860            </field>
27861            <field>
27862              <name>I2C_STOP</name>
27863              <description>I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address.
27864
27865The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd.</description>
27866              <bitRange>[4:4]</bitRange>
27867              <access>read-write</access>
27868            </field>
27869            <field>
27870              <name>I2C_START</name>
27871              <description>I2C slave START received. Set to '1', when START or REPEATED START event is detected.
27872
27873In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (till the internally clocked logic takes over) (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL.</description>
27874              <bitRange>[5:5]</bitRange>
27875              <access>read-write</access>
27876            </field>
27877            <field>
27878              <name>I2C_ADDR_MATCH</name>
27879              <description>I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected.</description>
27880              <bitRange>[6:6]</bitRange>
27881              <access>read-write</access>
27882            </field>
27883            <field>
27884              <name>I2C_GENERAL</name>
27885              <description>I2C slave general call address received.  If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO.   In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected.</description>
27886              <bitRange>[7:7]</bitRange>
27887              <access>read-write</access>
27888            </field>
27889            <field>
27890              <name>I2C_BUS_ERROR</name>
27891              <description>I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error.</description>
27892              <bitRange>[8:8]</bitRange>
27893              <access>read-write</access>
27894            </field>
27895            <field>
27896              <name>SPI_EZ_WRITE_STOP</name>
27897              <description>SPI slave deselected after a write EZ SPI transfer occurred.</description>
27898              <bitRange>[9:9]</bitRange>
27899              <access>read-write</access>
27900            </field>
27901            <field>
27902              <name>SPI_EZ_STOP</name>
27903              <description>SPI slave deselected after any EZ SPI transfer occurred.</description>
27904              <bitRange>[10:10]</bitRange>
27905              <access>read-write</access>
27906            </field>
27907            <field>
27908              <name>SPI_BUS_ERROR</name>
27909              <description>SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error.</description>
27910              <bitRange>[11:11]</bitRange>
27911              <access>read-write</access>
27912            </field>
27913          </fields>
27914        </register>
27915        <register>
27916          <name>INTR_S_SET</name>
27917          <description>Slave interrupt set request</description>
27918          <addressOffset>0xF44</addressOffset>
27919          <size>32</size>
27920          <access>read-write</access>
27921          <resetValue>0x0</resetValue>
27922          <resetMask>0xFFF</resetMask>
27923          <fields>
27924            <field>
27925              <name>I2C_ARB_LOST</name>
27926              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27927              <bitRange>[0:0]</bitRange>
27928              <access>read-write</access>
27929            </field>
27930            <field>
27931              <name>I2C_NACK</name>
27932              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27933              <bitRange>[1:1]</bitRange>
27934              <access>read-write</access>
27935            </field>
27936            <field>
27937              <name>I2C_ACK</name>
27938              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27939              <bitRange>[2:2]</bitRange>
27940              <access>read-write</access>
27941            </field>
27942            <field>
27943              <name>I2C_WRITE_STOP</name>
27944              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27945              <bitRange>[3:3]</bitRange>
27946              <access>read-write</access>
27947            </field>
27948            <field>
27949              <name>I2C_STOP</name>
27950              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27951              <bitRange>[4:4]</bitRange>
27952              <access>read-write</access>
27953            </field>
27954            <field>
27955              <name>I2C_START</name>
27956              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27957              <bitRange>[5:5]</bitRange>
27958              <access>read-write</access>
27959            </field>
27960            <field>
27961              <name>I2C_ADDR_MATCH</name>
27962              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27963              <bitRange>[6:6]</bitRange>
27964              <access>read-write</access>
27965            </field>
27966            <field>
27967              <name>I2C_GENERAL</name>
27968              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27969              <bitRange>[7:7]</bitRange>
27970              <access>read-write</access>
27971            </field>
27972            <field>
27973              <name>I2C_BUS_ERROR</name>
27974              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27975              <bitRange>[8:8]</bitRange>
27976              <access>read-write</access>
27977            </field>
27978            <field>
27979              <name>SPI_EZ_WRITE_STOP</name>
27980              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27981              <bitRange>[9:9]</bitRange>
27982              <access>read-write</access>
27983            </field>
27984            <field>
27985              <name>SPI_EZ_STOP</name>
27986              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27987              <bitRange>[10:10]</bitRange>
27988              <access>read-write</access>
27989            </field>
27990            <field>
27991              <name>SPI_BUS_ERROR</name>
27992              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
27993              <bitRange>[11:11]</bitRange>
27994              <access>read-write</access>
27995            </field>
27996          </fields>
27997        </register>
27998        <register>
27999          <name>INTR_S_MASK</name>
28000          <description>Slave interrupt mask</description>
28001          <addressOffset>0xF48</addressOffset>
28002          <size>32</size>
28003          <access>read-write</access>
28004          <resetValue>0x0</resetValue>
28005          <resetMask>0xFFF</resetMask>
28006          <fields>
28007            <field>
28008              <name>I2C_ARB_LOST</name>
28009              <description>Mask bit for corresponding bit in interrupt request register.</description>
28010              <bitRange>[0:0]</bitRange>
28011              <access>read-write</access>
28012            </field>
28013            <field>
28014              <name>I2C_NACK</name>
28015              <description>Mask bit for corresponding bit in interrupt request register.</description>
28016              <bitRange>[1:1]</bitRange>
28017              <access>read-write</access>
28018            </field>
28019            <field>
28020              <name>I2C_ACK</name>
28021              <description>Mask bit for corresponding bit in interrupt request register.</description>
28022              <bitRange>[2:2]</bitRange>
28023              <access>read-write</access>
28024            </field>
28025            <field>
28026              <name>I2C_WRITE_STOP</name>
28027              <description>Mask bit for corresponding bit in interrupt request register.</description>
28028              <bitRange>[3:3]</bitRange>
28029              <access>read-write</access>
28030            </field>
28031            <field>
28032              <name>I2C_STOP</name>
28033              <description>Mask bit for corresponding bit in interrupt request register.</description>
28034              <bitRange>[4:4]</bitRange>
28035              <access>read-write</access>
28036            </field>
28037            <field>
28038              <name>I2C_START</name>
28039              <description>Mask bit for corresponding bit in interrupt request register.</description>
28040              <bitRange>[5:5]</bitRange>
28041              <access>read-write</access>
28042            </field>
28043            <field>
28044              <name>I2C_ADDR_MATCH</name>
28045              <description>Mask bit for corresponding bit in interrupt request register.</description>
28046              <bitRange>[6:6]</bitRange>
28047              <access>read-write</access>
28048            </field>
28049            <field>
28050              <name>I2C_GENERAL</name>
28051              <description>Mask bit for corresponding bit in interrupt request register.</description>
28052              <bitRange>[7:7]</bitRange>
28053              <access>read-write</access>
28054            </field>
28055            <field>
28056              <name>I2C_BUS_ERROR</name>
28057              <description>Mask bit for corresponding bit in interrupt request register.</description>
28058              <bitRange>[8:8]</bitRange>
28059              <access>read-write</access>
28060            </field>
28061            <field>
28062              <name>SPI_EZ_WRITE_STOP</name>
28063              <description>Mask bit for corresponding bit in interrupt request register.</description>
28064              <bitRange>[9:9]</bitRange>
28065              <access>read-write</access>
28066            </field>
28067            <field>
28068              <name>SPI_EZ_STOP</name>
28069              <description>Mask bit for corresponding bit in interrupt request register.</description>
28070              <bitRange>[10:10]</bitRange>
28071              <access>read-write</access>
28072            </field>
28073            <field>
28074              <name>SPI_BUS_ERROR</name>
28075              <description>Mask bit for corresponding bit in interrupt request register.</description>
28076              <bitRange>[11:11]</bitRange>
28077              <access>read-write</access>
28078            </field>
28079          </fields>
28080        </register>
28081        <register>
28082          <name>INTR_S_MASKED</name>
28083          <description>Slave interrupt masked request</description>
28084          <addressOffset>0xF4C</addressOffset>
28085          <size>32</size>
28086          <access>read-only</access>
28087          <resetValue>0x0</resetValue>
28088          <resetMask>0xFFF</resetMask>
28089          <fields>
28090            <field>
28091              <name>I2C_ARB_LOST</name>
28092              <description>Logical and of corresponding request and mask bits.</description>
28093              <bitRange>[0:0]</bitRange>
28094              <access>read-only</access>
28095            </field>
28096            <field>
28097              <name>I2C_NACK</name>
28098              <description>Logical and of corresponding request and mask bits.</description>
28099              <bitRange>[1:1]</bitRange>
28100              <access>read-only</access>
28101            </field>
28102            <field>
28103              <name>I2C_ACK</name>
28104              <description>Logical and of corresponding request and mask bits.</description>
28105              <bitRange>[2:2]</bitRange>
28106              <access>read-only</access>
28107            </field>
28108            <field>
28109              <name>I2C_WRITE_STOP</name>
28110              <description>Logical and of corresponding request and mask bits.</description>
28111              <bitRange>[3:3]</bitRange>
28112              <access>read-only</access>
28113            </field>
28114            <field>
28115              <name>I2C_STOP</name>
28116              <description>Logical and of corresponding request and mask bits.</description>
28117              <bitRange>[4:4]</bitRange>
28118              <access>read-only</access>
28119            </field>
28120            <field>
28121              <name>I2C_START</name>
28122              <description>Logical and of corresponding request and mask bits.</description>
28123              <bitRange>[5:5]</bitRange>
28124              <access>read-only</access>
28125            </field>
28126            <field>
28127              <name>I2C_ADDR_MATCH</name>
28128              <description>Logical and of corresponding request and mask bits.</description>
28129              <bitRange>[6:6]</bitRange>
28130              <access>read-only</access>
28131            </field>
28132            <field>
28133              <name>I2C_GENERAL</name>
28134              <description>Logical and of corresponding request and mask bits.</description>
28135              <bitRange>[7:7]</bitRange>
28136              <access>read-only</access>
28137            </field>
28138            <field>
28139              <name>I2C_BUS_ERROR</name>
28140              <description>Logical and of corresponding request and mask bits.</description>
28141              <bitRange>[8:8]</bitRange>
28142              <access>read-only</access>
28143            </field>
28144            <field>
28145              <name>SPI_EZ_WRITE_STOP</name>
28146              <description>Logical and of corresponding request and mask bits.</description>
28147              <bitRange>[9:9]</bitRange>
28148              <access>read-only</access>
28149            </field>
28150            <field>
28151              <name>SPI_EZ_STOP</name>
28152              <description>Logical and of corresponding request and mask bits.</description>
28153              <bitRange>[10:10]</bitRange>
28154              <access>read-only</access>
28155            </field>
28156            <field>
28157              <name>SPI_BUS_ERROR</name>
28158              <description>Logical and of corresponding request and mask bits.</description>
28159              <bitRange>[11:11]</bitRange>
28160              <access>read-only</access>
28161            </field>
28162          </fields>
28163        </register>
28164        <register>
28165          <name>INTR_TX</name>
28166          <description>Transmitter interrupt request</description>
28167          <addressOffset>0xF80</addressOffset>
28168          <size>32</size>
28169          <access>read-write</access>
28170          <resetValue>0x0</resetValue>
28171          <resetMask>0x7F3</resetMask>
28172          <fields>
28173            <field>
28174              <name>TRIGGER</name>
28175              <description>Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL.
28176
28177Only used in FIFO mode.</description>
28178              <bitRange>[0:0]</bitRange>
28179              <access>read-write</access>
28180            </field>
28181            <field>
28182              <name>NOT_FULL</name>
28183              <description>TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)
28184MEM_WIDTH is '0': # entries != FF_DATA_NR.
28185MEM_WIDTH is '1': # entries != FF_DATA_NR/2.
28186MEM_WIDTH is '2': # entries != FF_DATA_NR/4.
28187
28188Only used in FIFO mode.</description>
28189              <bitRange>[1:1]</bitRange>
28190              <access>read-write</access>
28191            </field>
28192            <field>
28193              <name>EMPTY</name>
28194              <description>TX FIFO is empty; i.e. it has 0 entries.
28195
28196Only used in FIFO mode.</description>
28197              <bitRange>[4:4]</bitRange>
28198              <access>read-write</access>
28199            </field>
28200            <field>
28201              <name>OVERFLOW</name>
28202              <description>Attempt to write to a full TX FIFO.
28203
28204Only used in FIFO mode.</description>
28205              <bitRange>[5:5]</bitRange>
28206              <access>read-write</access>
28207            </field>
28208            <field>
28209              <name>UNDERFLOW</name>
28210              <description>Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'.
28211
28212Only used in FIFO mode.</description>
28213              <bitRange>[6:6]</bitRange>
28214              <access>read-write</access>
28215            </field>
28216            <field>
28217              <name>BLOCKED</name>
28218              <description>AHB-Lite write transfer can not get access to the EZ memory (EZ data access), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'.</description>
28219              <bitRange>[7:7]</bitRange>
28220              <access>read-write</access>
28221            </field>
28222            <field>
28223              <name>UART_NACK</name>
28224              <description>UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1', when event is detected. Write with '1' to clear bit.</description>
28225              <bitRange>[8:8]</bitRange>
28226              <access>read-write</access>
28227            </field>
28228            <field>
28229              <name>UART_DONE</name>
28230              <description>UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO, and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1', when event is detected. Write with '1' to clear bit.</description>
28231              <bitRange>[9:9]</bitRange>
28232              <access>read-write</access>
28233            </field>
28234            <field>
28235              <name>UART_ARB_LOST</name>
28236              <description>UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to '1', when event is detected. Write with '1' to clear bit.</description>
28237              <bitRange>[10:10]</bitRange>
28238              <access>read-write</access>
28239            </field>
28240          </fields>
28241        </register>
28242        <register>
28243          <name>INTR_TX_SET</name>
28244          <description>Transmitter interrupt set request</description>
28245          <addressOffset>0xF84</addressOffset>
28246          <size>32</size>
28247          <access>read-write</access>
28248          <resetValue>0x0</resetValue>
28249          <resetMask>0x7F3</resetMask>
28250          <fields>
28251            <field>
28252              <name>TRIGGER</name>
28253              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28254              <bitRange>[0:0]</bitRange>
28255              <access>read-write</access>
28256            </field>
28257            <field>
28258              <name>NOT_FULL</name>
28259              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28260              <bitRange>[1:1]</bitRange>
28261              <access>read-write</access>
28262            </field>
28263            <field>
28264              <name>EMPTY</name>
28265              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28266              <bitRange>[4:4]</bitRange>
28267              <access>read-write</access>
28268            </field>
28269            <field>
28270              <name>OVERFLOW</name>
28271              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28272              <bitRange>[5:5]</bitRange>
28273              <access>read-write</access>
28274            </field>
28275            <field>
28276              <name>UNDERFLOW</name>
28277              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28278              <bitRange>[6:6]</bitRange>
28279              <access>read-write</access>
28280            </field>
28281            <field>
28282              <name>BLOCKED</name>
28283              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28284              <bitRange>[7:7]</bitRange>
28285              <access>read-write</access>
28286            </field>
28287            <field>
28288              <name>UART_NACK</name>
28289              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28290              <bitRange>[8:8]</bitRange>
28291              <access>read-write</access>
28292            </field>
28293            <field>
28294              <name>UART_DONE</name>
28295              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28296              <bitRange>[9:9]</bitRange>
28297              <access>read-write</access>
28298            </field>
28299            <field>
28300              <name>UART_ARB_LOST</name>
28301              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28302              <bitRange>[10:10]</bitRange>
28303              <access>read-write</access>
28304            </field>
28305          </fields>
28306        </register>
28307        <register>
28308          <name>INTR_TX_MASK</name>
28309          <description>Transmitter interrupt mask</description>
28310          <addressOffset>0xF88</addressOffset>
28311          <size>32</size>
28312          <access>read-write</access>
28313          <resetValue>0x0</resetValue>
28314          <resetMask>0x7F3</resetMask>
28315          <fields>
28316            <field>
28317              <name>TRIGGER</name>
28318              <description>Mask bit for corresponding bit in interrupt request register.</description>
28319              <bitRange>[0:0]</bitRange>
28320              <access>read-write</access>
28321            </field>
28322            <field>
28323              <name>NOT_FULL</name>
28324              <description>Mask bit for corresponding bit in interrupt request register.</description>
28325              <bitRange>[1:1]</bitRange>
28326              <access>read-write</access>
28327            </field>
28328            <field>
28329              <name>EMPTY</name>
28330              <description>Mask bit for corresponding bit in interrupt request register.</description>
28331              <bitRange>[4:4]</bitRange>
28332              <access>read-write</access>
28333            </field>
28334            <field>
28335              <name>OVERFLOW</name>
28336              <description>Mask bit for corresponding bit in interrupt request register.</description>
28337              <bitRange>[5:5]</bitRange>
28338              <access>read-write</access>
28339            </field>
28340            <field>
28341              <name>UNDERFLOW</name>
28342              <description>Mask bit for corresponding bit in interrupt request register.</description>
28343              <bitRange>[6:6]</bitRange>
28344              <access>read-write</access>
28345            </field>
28346            <field>
28347              <name>BLOCKED</name>
28348              <description>Mask bit for corresponding bit in interrupt request register.</description>
28349              <bitRange>[7:7]</bitRange>
28350              <access>read-write</access>
28351            </field>
28352            <field>
28353              <name>UART_NACK</name>
28354              <description>Mask bit for corresponding bit in interrupt request register.</description>
28355              <bitRange>[8:8]</bitRange>
28356              <access>read-write</access>
28357            </field>
28358            <field>
28359              <name>UART_DONE</name>
28360              <description>Mask bit for corresponding bit in interrupt request register.</description>
28361              <bitRange>[9:9]</bitRange>
28362              <access>read-write</access>
28363            </field>
28364            <field>
28365              <name>UART_ARB_LOST</name>
28366              <description>Mask bit for corresponding bit in interrupt request register.</description>
28367              <bitRange>[10:10]</bitRange>
28368              <access>read-write</access>
28369            </field>
28370          </fields>
28371        </register>
28372        <register>
28373          <name>INTR_TX_MASKED</name>
28374          <description>Transmitter interrupt masked request</description>
28375          <addressOffset>0xF8C</addressOffset>
28376          <size>32</size>
28377          <access>read-only</access>
28378          <resetValue>0x0</resetValue>
28379          <resetMask>0x7F3</resetMask>
28380          <fields>
28381            <field>
28382              <name>TRIGGER</name>
28383              <description>Logical and of corresponding request and mask bits.</description>
28384              <bitRange>[0:0]</bitRange>
28385              <access>read-only</access>
28386            </field>
28387            <field>
28388              <name>NOT_FULL</name>
28389              <description>Logical and of corresponding request and mask bits.</description>
28390              <bitRange>[1:1]</bitRange>
28391              <access>read-only</access>
28392            </field>
28393            <field>
28394              <name>EMPTY</name>
28395              <description>Logical and of corresponding request and mask bits.</description>
28396              <bitRange>[4:4]</bitRange>
28397              <access>read-only</access>
28398            </field>
28399            <field>
28400              <name>OVERFLOW</name>
28401              <description>Logical and of corresponding request and mask bits.</description>
28402              <bitRange>[5:5]</bitRange>
28403              <access>read-only</access>
28404            </field>
28405            <field>
28406              <name>UNDERFLOW</name>
28407              <description>Logical and of corresponding request and mask bits.</description>
28408              <bitRange>[6:6]</bitRange>
28409              <access>read-only</access>
28410            </field>
28411            <field>
28412              <name>BLOCKED</name>
28413              <description>Logical and of corresponding request and mask bits.</description>
28414              <bitRange>[7:7]</bitRange>
28415              <access>read-only</access>
28416            </field>
28417            <field>
28418              <name>UART_NACK</name>
28419              <description>Logical and of corresponding request and mask bits.</description>
28420              <bitRange>[8:8]</bitRange>
28421              <access>read-only</access>
28422            </field>
28423            <field>
28424              <name>UART_DONE</name>
28425              <description>Logical and of corresponding request and mask bits.</description>
28426              <bitRange>[9:9]</bitRange>
28427              <access>read-only</access>
28428            </field>
28429            <field>
28430              <name>UART_ARB_LOST</name>
28431              <description>Logical and of corresponding request and mask bits.</description>
28432              <bitRange>[10:10]</bitRange>
28433              <access>read-only</access>
28434            </field>
28435          </fields>
28436        </register>
28437        <register>
28438          <name>INTR_RX</name>
28439          <description>Receiver interrupt request</description>
28440          <addressOffset>0xFC0</addressOffset>
28441          <size>32</size>
28442          <access>read-write</access>
28443          <resetValue>0x0</resetValue>
28444          <resetMask>0xFED</resetMask>
28445          <fields>
28446            <field>
28447              <name>TRIGGER</name>
28448              <description>More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL.
28449
28450Only used in FIFO mode.</description>
28451              <bitRange>[0:0]</bitRange>
28452              <access>read-write</access>
28453            </field>
28454            <field>
28455              <name>NOT_EMPTY</name>
28456              <description>RX FIFO is not empty.
28457
28458Only used in FIFO mode.</description>
28459              <bitRange>[2:2]</bitRange>
28460              <access>read-write</access>
28461            </field>
28462            <field>
28463              <name>FULL</name>
28464              <description>RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)
28465MEM_WIDTH is '0': # entries == FF_DATA_NR.
28466MEM_WIDTH is '1': # entries == FF_DATA_NR/2.
28467MEM_WIDTH is '2': # entries == FF_DATA_NR/4.
28468
28469Only used in FIFO mode.</description>
28470              <bitRange>[3:3]</bitRange>
28471              <access>read-write</access>
28472            </field>
28473            <field>
28474              <name>OVERFLOW</name>
28475              <description>Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a data frame is received and the RX FIFO is full, independent of whether it is ACK'd or NACK'd.
28476
28477Only used in FIFO mode.</description>
28478              <bitRange>[5:5]</bitRange>
28479              <access>read-write</access>
28480            </field>
28481            <field>
28482              <name>UNDERFLOW</name>
28483              <description>Attempt to read from an empty RX FIFO.
28484
28485Only used in FIFO mode.</description>
28486              <bitRange>[6:6]</bitRange>
28487              <access>read-write</access>
28488            </field>
28489            <field>
28490              <name>BLOCKED</name>
28491              <description>AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'.</description>
28492              <bitRange>[7:7]</bitRange>
28493              <access>read-write</access>
28494            </field>
28495            <field>
28496              <name>FRAME_ERROR</name>
28497              <description>Frame error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:
28498Start bit error: after the detection of the beginning of a start bit period (RX line changes from '1' to '0'), the middle of the start bit period is sampled erroneously (RX line is '1').  Note: a start bit error is detected BEFORE a data frame is received.
28499Stop bit error: the RX line is sampled as '0', but a '1' was expected. Note: a stop bit error may result in failure to receive successive data frame(s). Note: a stop bit error is detected AFTER a data frame is received.
28500
28501A stop bit error is detected after a data frame is received, and the UART_RX_CTL.DROP_ON_FRAME_ERROR field specifies whether the received frame is dropped or send to the RX FIFO. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '1', the received data frame is dropped. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '0', the received data frame is send to the RX FIFO. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO; i.e. the RX FIFO does not have error flags to tag erroneous data frames.</description>
28502              <bitRange>[8:8]</bitRange>
28503              <access>read-write</access>
28504            </field>
28505            <field>
28506              <name>PARITY_ERROR</name>
28507              <description>Parity error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1', the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0', the received frame is send to the RX FIFO. In SmartCard submode, negatively acknowledged data frames generate a parity error. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO.</description>
28508              <bitRange>[9:9]</bitRange>
28509              <access>read-write</access>
28510            </field>
28511            <field>
28512              <name>BAUD_DETECT</name>
28513              <description>LIN baudrate detection is completed.  The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. Set to '1', when event is detected. Write with '1' to clear bit.</description>
28514              <bitRange>[10:10]</bitRange>
28515              <access>read-write</access>
28516            </field>
28517            <field>
28518              <name>BREAK_DETECT</name>
28519              <description>Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and LIN submodes. For the UART standard submodes, ongoing receipt of data frames is NOT affected; i.e. Firmware is expected to take the proper action. For the LIN submode, possible ongoing receipt of a data frame is stopped and the (partially) received data frame is dropped and baud rate detection is started. Set to '1', when event is detected. Write with '1' to clear bit.</description>
28520              <bitRange>[11:11]</bitRange>
28521              <access>read-write</access>
28522            </field>
28523          </fields>
28524        </register>
28525        <register>
28526          <name>INTR_RX_SET</name>
28527          <description>Receiver interrupt set request</description>
28528          <addressOffset>0xFC4</addressOffset>
28529          <size>32</size>
28530          <access>read-write</access>
28531          <resetValue>0x0</resetValue>
28532          <resetMask>0xFED</resetMask>
28533          <fields>
28534            <field>
28535              <name>TRIGGER</name>
28536              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
28537              <bitRange>[0:0]</bitRange>
28538              <access>read-write</access>
28539            </field>
28540            <field>
28541              <name>NOT_EMPTY</name>
28542              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
28543              <bitRange>[2:2]</bitRange>
28544              <access>read-write</access>
28545            </field>
28546            <field>
28547              <name>FULL</name>
28548              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
28549              <bitRange>[3:3]</bitRange>
28550              <access>read-write</access>
28551            </field>
28552            <field>
28553              <name>OVERFLOW</name>
28554              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
28555              <bitRange>[5:5]</bitRange>
28556              <access>read-write</access>
28557            </field>
28558            <field>
28559              <name>UNDERFLOW</name>
28560              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
28561              <bitRange>[6:6]</bitRange>
28562              <access>read-write</access>
28563            </field>
28564            <field>
28565              <name>BLOCKED</name>
28566              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
28567              <bitRange>[7:7]</bitRange>
28568              <access>read-write</access>
28569            </field>
28570            <field>
28571              <name>FRAME_ERROR</name>
28572              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
28573              <bitRange>[8:8]</bitRange>
28574              <access>read-write</access>
28575            </field>
28576            <field>
28577              <name>PARITY_ERROR</name>
28578              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
28579              <bitRange>[9:9]</bitRange>
28580              <access>read-write</access>
28581            </field>
28582            <field>
28583              <name>BAUD_DETECT</name>
28584              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
28585              <bitRange>[10:10]</bitRange>
28586              <access>read-write</access>
28587            </field>
28588            <field>
28589              <name>BREAK_DETECT</name>
28590              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
28591              <bitRange>[11:11]</bitRange>
28592              <access>read-write</access>
28593            </field>
28594          </fields>
28595        </register>
28596        <register>
28597          <name>INTR_RX_MASK</name>
28598          <description>Receiver interrupt mask</description>
28599          <addressOffset>0xFC8</addressOffset>
28600          <size>32</size>
28601          <access>read-write</access>
28602          <resetValue>0x0</resetValue>
28603          <resetMask>0xFED</resetMask>
28604          <fields>
28605            <field>
28606              <name>TRIGGER</name>
28607              <description>Mask bit for corresponding bit in interrupt request register.</description>
28608              <bitRange>[0:0]</bitRange>
28609              <access>read-write</access>
28610            </field>
28611            <field>
28612              <name>NOT_EMPTY</name>
28613              <description>Mask bit for corresponding bit in interrupt request register.</description>
28614              <bitRange>[2:2]</bitRange>
28615              <access>read-write</access>
28616            </field>
28617            <field>
28618              <name>FULL</name>
28619              <description>Mask bit for corresponding bit in interrupt request register.</description>
28620              <bitRange>[3:3]</bitRange>
28621              <access>read-write</access>
28622            </field>
28623            <field>
28624              <name>OVERFLOW</name>
28625              <description>Mask bit for corresponding bit in interrupt request register.</description>
28626              <bitRange>[5:5]</bitRange>
28627              <access>read-write</access>
28628            </field>
28629            <field>
28630              <name>UNDERFLOW</name>
28631              <description>Mask bit for corresponding bit in interrupt request register.</description>
28632              <bitRange>[6:6]</bitRange>
28633              <access>read-write</access>
28634            </field>
28635            <field>
28636              <name>BLOCKED</name>
28637              <description>Mask bit for corresponding bit in interrupt request register.</description>
28638              <bitRange>[7:7]</bitRange>
28639              <access>read-write</access>
28640            </field>
28641            <field>
28642              <name>FRAME_ERROR</name>
28643              <description>Mask bit for corresponding bit in interrupt request register.</description>
28644              <bitRange>[8:8]</bitRange>
28645              <access>read-write</access>
28646            </field>
28647            <field>
28648              <name>PARITY_ERROR</name>
28649              <description>Mask bit for corresponding bit in interrupt request register.</description>
28650              <bitRange>[9:9]</bitRange>
28651              <access>read-write</access>
28652            </field>
28653            <field>
28654              <name>BAUD_DETECT</name>
28655              <description>Mask bit for corresponding bit in interrupt request register.</description>
28656              <bitRange>[10:10]</bitRange>
28657              <access>read-write</access>
28658            </field>
28659            <field>
28660              <name>BREAK_DETECT</name>
28661              <description>Mask bit for corresponding bit in interrupt request register.</description>
28662              <bitRange>[11:11]</bitRange>
28663              <access>read-write</access>
28664            </field>
28665          </fields>
28666        </register>
28667        <register>
28668          <name>INTR_RX_MASKED</name>
28669          <description>Receiver interrupt masked request</description>
28670          <addressOffset>0xFCC</addressOffset>
28671          <size>32</size>
28672          <access>read-only</access>
28673          <resetValue>0x0</resetValue>
28674          <resetMask>0xFED</resetMask>
28675          <fields>
28676            <field>
28677              <name>TRIGGER</name>
28678              <description>Logical and of corresponding request and mask bits.</description>
28679              <bitRange>[0:0]</bitRange>
28680              <access>read-only</access>
28681            </field>
28682            <field>
28683              <name>NOT_EMPTY</name>
28684              <description>Logical and of corresponding request and mask bits.</description>
28685              <bitRange>[2:2]</bitRange>
28686              <access>read-only</access>
28687            </field>
28688            <field>
28689              <name>FULL</name>
28690              <description>Logical and of corresponding request and mask bits.</description>
28691              <bitRange>[3:3]</bitRange>
28692              <access>read-only</access>
28693            </field>
28694            <field>
28695              <name>OVERFLOW</name>
28696              <description>Logical and of corresponding request and mask bits.</description>
28697              <bitRange>[5:5]</bitRange>
28698              <access>read-only</access>
28699            </field>
28700            <field>
28701              <name>UNDERFLOW</name>
28702              <description>Logical and of corresponding request and mask bits.</description>
28703              <bitRange>[6:6]</bitRange>
28704              <access>read-only</access>
28705            </field>
28706            <field>
28707              <name>BLOCKED</name>
28708              <description>Logical and of corresponding request and mask bits.</description>
28709              <bitRange>[7:7]</bitRange>
28710              <access>read-only</access>
28711            </field>
28712            <field>
28713              <name>FRAME_ERROR</name>
28714              <description>Logical and of corresponding request and mask bits.</description>
28715              <bitRange>[8:8]</bitRange>
28716              <access>read-only</access>
28717            </field>
28718            <field>
28719              <name>PARITY_ERROR</name>
28720              <description>Logical and of corresponding request and mask bits.</description>
28721              <bitRange>[9:9]</bitRange>
28722              <access>read-only</access>
28723            </field>
28724            <field>
28725              <name>BAUD_DETECT</name>
28726              <description>Logical and of corresponding request and mask bits.</description>
28727              <bitRange>[10:10]</bitRange>
28728              <access>read-only</access>
28729            </field>
28730            <field>
28731              <name>BREAK_DETECT</name>
28732              <description>Logical and of corresponding request and mask bits.</description>
28733              <bitRange>[11:11]</bitRange>
28734              <access>read-only</access>
28735            </field>
28736          </fields>
28737        </register>
28738      </registers>
28739    </peripheral>
28740    <peripheral derivedFrom="SCB0">
28741      <name>SCB1</name>
28742      <baseAddress>0x40610000</baseAddress>
28743    </peripheral>
28744    <peripheral derivedFrom="SCB0">
28745      <name>SCB2</name>
28746      <baseAddress>0x40620000</baseAddress>
28747    </peripheral>
28748    <peripheral derivedFrom="SCB0">
28749      <name>SCB3</name>
28750      <baseAddress>0x40630000</baseAddress>
28751    </peripheral>
28752    <peripheral derivedFrom="SCB0">
28753      <name>SCB4</name>
28754      <baseAddress>0x40640000</baseAddress>
28755    </peripheral>
28756    <peripheral derivedFrom="SCB0">
28757      <name>SCB5</name>
28758      <baseAddress>0x40650000</baseAddress>
28759    </peripheral>
28760    <peripheral derivedFrom="SCB0">
28761      <name>SCB6</name>
28762      <baseAddress>0x40660000</baseAddress>
28763    </peripheral>
28764    <peripheral derivedFrom="SCB0">
28765      <name>SCB7</name>
28766      <baseAddress>0x40670000</baseAddress>
28767    </peripheral>
28768    <peripheral>
28769      <name>PASS0</name>
28770      <description>Programmable Analog Subsystem for S40E</description>
28771      <headerStructName>PASS</headerStructName>
28772      <baseAddress>0x40900000</baseAddress>
28773      <addressBlock>
28774        <offset>0</offset>
28775        <size>1048576</size>
28776        <usage>registers</usage>
28777      </addressBlock>
28778      <registers>
28779        <cluster>
28780          <dim>3</dim>
28781          <dimIncrement>4096</dimIncrement>
28782          <name>SAR[%s]</name>
28783          <description>SAR ADC with Sequencer for S40E</description>
28784          <addressOffset>0x00000000</addressOffset>
28785          <register>
28786            <name>CTL</name>
28787            <description>Analog control register.</description>
28788            <addressOffset>0x0</addressOffset>
28789            <size>32</size>
28790            <access>read-write</access>
28791            <resetValue>0x0</resetValue>
28792            <resetMask>0xE00007FF</resetMask>
28793            <fields>
28794              <field>
28795                <name>PWRUP_TIME</name>
28796                <description>Number cycles to wait to power up after IDLE_PWRDWN.
28797Check the STATUS.PWRUP_BUSY flag to see if the delay is still in progress.
28798The power up delay is 1 us.</description>
28799                <bitRange>[7:0]</bitRange>
28800                <access>read-write</access>
28801              </field>
28802              <field>
28803                <name>IDLE_PWRDWN</name>
28804                <description>When idle automatically power down the analog.
28805After an automatic power down a new trigger will power up the analog, however it will take PWRUP_TIME cycles before the first acquisition can be started. Note that re-arbitration happens at that time, i.e. the trigger that caused the power up may not get handled first.</description>
28806                <bitRange>[8:8]</bitRange>
28807                <access>read-write</access>
28808              </field>
28809              <field>
28810                <name>MSB_STRETCH</name>
28811                <description>When set use 2 cycles for the Most Significant Bit (MSB)
28812- 0: Use 1 clock cycle for MSB
28813- 1: Use 2 clock cycles for MSB</description>
28814                <bitRange>[9:9]</bitRange>
28815                <access>read-write</access>
28816              </field>
28817              <field>
28818                <name>HALF_LSB</name>
28819                <description>When set take an extra cycle to convert the half LSB and add it to 12-bit result for Missing Code Recovery
28820This bit should always be set to '1'
28821- 0: disable half LSB conversion (not recommended)
28822- 1: enable half LSB conversion</description>
28823                <bitRange>[10:10]</bitRange>
28824                <access>read-write</access>
28825              </field>
28826              <field>
28827                <name>SARMUX_EN</name>
28828                <description>Enable the SARMUX (only valid if ENABLED=1)
28829- 0: SARMUX disabled (put analog in power down)
28830- 1: SARMUX enabled.</description>
28831                <bitRange>[29:29]</bitRange>
28832                <access>read-write</access>
28833              </field>
28834              <field>
28835                <name>ADC_EN</name>
28836                <description>Enable the SAR ADC and SAR sequencer (only valid if ENABLED=1)
28837- 0: SARADC and SARSEQ are disabled (put SARADC analog in power down and stop clocks), also clears all pending triggers.
28838- 1: SAR ADC and SARSEQ are enabled.
28839To enable ADC0 to borrow SARMUX1-3 the corresponding ADC_EN must  be set to 0.</description>
28840                <bitRange>[30:30]</bitRange>
28841                <access>read-write</access>
28842              </field>
28843              <field>
28844                <name>ENABLED</name>
28845                <description>- 0: SAR IP disabled (put analog in power down and stop clocks), also clears all pending triggers.
28846- 1: SAR IP enabled.</description>
28847                <bitRange>[31:31]</bitRange>
28848                <access>read-write</access>
28849              </field>
28850            </fields>
28851          </register>
28852          <register>
28853            <name>DIAG_CTL</name>
28854            <description>Diagnostic Reference control register.</description>
28855            <addressOffset>0x4</addressOffset>
28856            <size>32</size>
28857            <access>read-write</access>
28858            <resetValue>0x0</resetValue>
28859            <resetMask>0x8000000F</resetMask>
28860            <fields>
28861              <field>
28862                <name>DIAG_SEL</name>
28863                <description>Select Diagnostic Reference function</description>
28864                <bitRange>[3:0]</bitRange>
28865                <access>read-write</access>
28866                <enumeratedValues>
28867                  <enumeratedValue>
28868                    <name>VREFL</name>
28869                    <description>DiagOut = VrefL</description>
28870                    <value>0</value>
28871                  </enumeratedValue>
28872                  <enumeratedValue>
28873                    <name>VREFH_1DIV8</name>
28874                    <description>DiagOut = VrefH * 1/8</description>
28875                    <value>1</value>
28876                  </enumeratedValue>
28877                  <enumeratedValue>
28878                    <name>VREFH_2DIV8</name>
28879                    <description>DiagOut = VrefH * 2/8</description>
28880                    <value>2</value>
28881                  </enumeratedValue>
28882                  <enumeratedValue>
28883                    <name>VREFH_3DIV8</name>
28884                    <description>DiagOut = VrefH * 3/8</description>
28885                    <value>3</value>
28886                  </enumeratedValue>
28887                  <enumeratedValue>
28888                    <name>VREFH_4DIV8</name>
28889                    <description>DiagOut = VrefH * 4/8</description>
28890                    <value>4</value>
28891                  </enumeratedValue>
28892                  <enumeratedValue>
28893                    <name>VREFH_5DIV8</name>
28894                    <description>DiagOut = VrefH * 5/8</description>
28895                    <value>5</value>
28896                  </enumeratedValue>
28897                  <enumeratedValue>
28898                    <name>VREFH_6DIV8</name>
28899                    <description>DiagOut = VrefH * 6/8</description>
28900                    <value>6</value>
28901                  </enumeratedValue>
28902                  <enumeratedValue>
28903                    <name>VREFH_7DIV8</name>
28904                    <description>DiagOut = VrefH * 7/8</description>
28905                    <value>7</value>
28906                  </enumeratedValue>
28907                  <enumeratedValue>
28908                    <name>VREFH</name>
28909                    <description>DiagOut = VrefH</description>
28910                    <value>8</value>
28911                  </enumeratedValue>
28912                  <enumeratedValue>
28913                    <name>VREFX</name>
28914                    <description>DiagOut = VrefX = VrefH * 199/200</description>
28915                    <value>9</value>
28916                  </enumeratedValue>
28917                  <enumeratedValue>
28918                    <name>VBG</name>
28919                    <description>DiagOut = Vbg from SRSS</description>
28920                    <value>10</value>
28921                  </enumeratedValue>
28922                  <enumeratedValue>
28923                    <name>VIN1</name>
28924                    <description>DiagOut = Vin1</description>
28925                    <value>11</value>
28926                  </enumeratedValue>
28927                  <enumeratedValue>
28928                    <name>VIN2</name>
28929                    <description>DiagOut = Vin2</description>
28930                    <value>12</value>
28931                  </enumeratedValue>
28932                  <enumeratedValue>
28933                    <name>VIN3</name>
28934                    <description>DiagOut = Vin3</description>
28935                    <value>13</value>
28936                  </enumeratedValue>
28937                  <enumeratedValue>
28938                    <name>I_SOURCE</name>
28939                    <description>DiagOut = Isource (10uA)</description>
28940                    <value>14</value>
28941                  </enumeratedValue>
28942                  <enumeratedValue>
28943                    <name>I_SINK</name>
28944                    <description>DiagOut = Isink (10uA)</description>
28945                    <value>15</value>
28946                  </enumeratedValue>
28947                </enumeratedValues>
28948              </field>
28949              <field>
28950                <name>DIAG_EN</name>
28951                <description>Diagnostic Reference enable (only valid if ENABLED=1)
28952- 0: Diagnostic Reference disabled (powered down resistor ladder and current mirrors, DiagOut = Vssa).
28953- 1: Diagnostic Reference enabled, output signal select according to DIAG_SEL (note also EPASS_MMIO.PASS_CTL.REFBUF_EN must be set).</description>
28954                <bitRange>[31:31]</bitRange>
28955                <access>read-write</access>
28956              </field>
28957            </fields>
28958          </register>
28959          <register>
28960            <name>PRECOND_CTL</name>
28961            <description>Preconditioning control register.</description>
28962            <addressOffset>0x10</addressOffset>
28963            <size>32</size>
28964            <access>read-write</access>
28965            <resetValue>0x0</resetValue>
28966            <resetMask>0xF</resetMask>
28967            <fields>
28968              <field>
28969                <name>PRECOND_TIME</name>
28970                <description>Number ADC clock cycles that Preconditioning is done before the sample window starts. If OVERLAP_EN=0 there will be 1 additional break before make cycle between preconditioning and sampling.
28971Note that the minimum value is 1 (0 gives the same result as 1).</description>
28972                <bitRange>[3:0]</bitRange>
28973                <access>read-write</access>
28974              </field>
28975            </fields>
28976          </register>
28977          <register>
28978            <name>ANA_CAL</name>
28979            <description>Current analog calibration values</description>
28980            <addressOffset>0x80</addressOffset>
28981            <size>32</size>
28982            <access>read-write</access>
28983            <resetValue>0x0</resetValue>
28984            <resetMask>0x1F00FF</resetMask>
28985            <fields>
28986              <field>
28987                <name>AOFFSET</name>
28988                <description>Analog offset correction</description>
28989                <bitRange>[7:0]</bitRange>
28990                <access>read-write</access>
28991              </field>
28992              <field>
28993                <name>AGAIN</name>
28994                <description>Analog gain correction</description>
28995                <bitRange>[20:16]</bitRange>
28996                <access>read-write</access>
28997              </field>
28998            </fields>
28999          </register>
29000          <register>
29001            <name>DIG_CAL</name>
29002            <description>Current digital calibration values</description>
29003            <addressOffset>0x84</addressOffset>
29004            <size>32</size>
29005            <access>read-write</access>
29006            <resetValue>0x0</resetValue>
29007            <resetMask>0x3F0FFF</resetMask>
29008            <fields>
29009              <field>
29010                <name>DOFFSET</name>
29011                <description>Digital offset correction
29012Subtract DOFFSET from ADC output.</description>
29013                <bitRange>[11:0]</bitRange>
29014                <access>read-write</access>
29015              </field>
29016              <field>
29017                <name>DGAIN</name>
29018                <description>Digital gain correction.
29019Signed value to correct +/- 30 codes for the maximum input voltage.
29020Corrected = (D - DOFFSET) + ( (D - DOFFSET) * DGAIN + 0x800) / 0x1000</description>
29021                <bitRange>[21:16]</bitRange>
29022                <access>read-write</access>
29023              </field>
29024            </fields>
29025          </register>
29026          <register>
29027            <name>ANA_CAL_ALT</name>
29028            <description>Alternate analog calibration values</description>
29029            <addressOffset>0x90</addressOffset>
29030            <size>32</size>
29031            <access>read-write</access>
29032            <resetValue>0x0</resetValue>
29033            <resetMask>0x1F00FF</resetMask>
29034            <fields>
29035              <field>
29036                <name>AOFFSET</name>
29037                <description>See corresponding ANA_CAL field</description>
29038                <bitRange>[7:0]</bitRange>
29039                <access>read-write</access>
29040              </field>
29041              <field>
29042                <name>AGAIN</name>
29043                <description>See corresponding ANA_CAL field</description>
29044                <bitRange>[20:16]</bitRange>
29045                <access>read-write</access>
29046              </field>
29047            </fields>
29048          </register>
29049          <register>
29050            <name>DIG_CAL_ALT</name>
29051            <description>Alternate digital calibration values</description>
29052            <addressOffset>0x94</addressOffset>
29053            <size>32</size>
29054            <access>read-write</access>
29055            <resetValue>0x0</resetValue>
29056            <resetMask>0x3F0FFF</resetMask>
29057            <fields>
29058              <field>
29059                <name>DOFFSET</name>
29060                <description>See corresponding DIG_CAL field</description>
29061                <bitRange>[11:0]</bitRange>
29062                <access>read-write</access>
29063              </field>
29064              <field>
29065                <name>DGAIN</name>
29066                <description>See corresponding DIG_CAL field</description>
29067                <bitRange>[21:16]</bitRange>
29068                <access>read-write</access>
29069              </field>
29070            </fields>
29071          </register>
29072          <register>
29073            <name>CAL_UPD_CMD</name>
29074            <description>Calibration update command</description>
29075            <addressOffset>0x98</addressOffset>
29076            <size>32</size>
29077            <access>read-write</access>
29078            <resetValue>0x0</resetValue>
29079            <resetMask>0x1</resetMask>
29080            <fields>
29081              <field>
29082                <name>UPDATE</name>
29083                <description>Calibration update command: coherently copy values from alternate calibration regs to current calibration regs.
29084Software sets this bit when the alternate calibration values have been set with the new values. Hardware will do the calibration update as soon as the ADC is idle or a 'continuous' triggered group completes. This ensures that all acquisitions within a group scan (even if preempted) are done with the same calibration values.
29085This bit is cleared at the same time the calibration update is done. By clearing this bit software can cancel a requested update.
29086Note: if the ADC is always busy with acquisitions for non continuously triggered groups/channels then the calibration update will remain pending forever. In such a case the software can either  do a non coherent update by writing directly to the current calibration registers, or software can force the ADC to idle by disabling some or all channels.
29087Software can check/poll this bit to see if the calibration update has taken effect.</description>
29088                <bitRange>[0:0]</bitRange>
29089                <access>read-write</access>
29090              </field>
29091            </fields>
29092          </register>
29093          <register>
29094            <name>TR_PEND</name>
29095            <description>Trigger pending status</description>
29096            <addressOffset>0x100</addressOffset>
29097            <size>32</size>
29098            <access>read-only</access>
29099            <resetValue>0x0</resetValue>
29100            <resetMask>0xFFFFFFFF</resetMask>
29101            <fields>
29102              <field>
29103                <name>TR_PEND</name>
29104                <description>Trigger Pending.
29105Hardware will set this bit if a hardware trigger is received.</description>
29106                <bitRange>[31:0]</bitRange>
29107                <access>read-only</access>
29108              </field>
29109            </fields>
29110          </register>
29111          <register>
29112            <name>WORK_VALID</name>
29113            <description>Channel working data register 'valid' bits</description>
29114            <addressOffset>0x180</addressOffset>
29115            <size>32</size>
29116            <access>read-only</access>
29117            <resetValue>0x0</resetValue>
29118            <resetMask>0xFFFFFFFF</resetMask>
29119            <fields>
29120              <field>
29121                <name>WORK_VALID</name>
29122                <description>If set the corresponding WORK register is valid, i.e. was already acquired during the current group scan. If this bit is low then either the channel is not enabled, not yet acquired or it is used as a pulse detect channel.</description>
29123                <bitRange>[31:0]</bitRange>
29124                <access>read-only</access>
29125              </field>
29126            </fields>
29127          </register>
29128          <register>
29129            <name>WORK_RANGE</name>
29130            <description>Range detected</description>
29131            <addressOffset>0x184</addressOffset>
29132            <size>32</size>
29133            <access>read-only</access>
29134            <resetValue>0x0</resetValue>
29135            <resetMask>0xFFFFFFFF</resetMask>
29136            <fields>
29137              <field>
29138                <name>RANGE</name>
29139                <description>N/A</description>
29140                <bitRange>[31:0]</bitRange>
29141                <access>read-only</access>
29142              </field>
29143            </fields>
29144          </register>
29145          <register>
29146            <name>WORK_RANGE_HI</name>
29147            <description>Range detect above Hi flag</description>
29148            <addressOffset>0x188</addressOffset>
29149            <size>32</size>
29150            <access>read-only</access>
29151            <resetValue>0x0</resetValue>
29152            <resetMask>0xFFFFFFFF</resetMask>
29153            <fields>
29154              <field>
29155                <name>ABOVE_HI</name>
29156                <description>Out of range was detected and the value was above the Hi threshold</description>
29157                <bitRange>[31:0]</bitRange>
29158                <access>read-only</access>
29159              </field>
29160            </fields>
29161          </register>
29162          <register>
29163            <name>WORK_PULSE</name>
29164            <description>Pulse detected</description>
29165            <addressOffset>0x18C</addressOffset>
29166            <size>32</size>
29167            <access>read-only</access>
29168            <resetValue>0x0</resetValue>
29169            <resetMask>0xFFFFFFFF</resetMask>
29170            <fields>
29171              <field>
29172                <name>PULSE</name>
29173                <description>N/A</description>
29174                <bitRange>[31:0]</bitRange>
29175                <access>read-only</access>
29176              </field>
29177            </fields>
29178          </register>
29179          <register>
29180            <name>RESULT_VALID</name>
29181            <description>Channel result data register 'valid' bits</description>
29182            <addressOffset>0x1A0</addressOffset>
29183            <size>32</size>
29184            <access>read-only</access>
29185            <resetValue>0x0</resetValue>
29186            <resetMask>0xFFFFFFFF</resetMask>
29187            <fields>
29188              <field>
29189                <name>RESULT_VALID</name>
29190                <description>If set the corresponding RESULT register is valid, i.e. was acquired during the preceding group scan. If this bit is low, after a group scan completed, then either the channel is not enabled or is used as a pulse  detect channel.</description>
29191                <bitRange>[31:0]</bitRange>
29192                <access>read-only</access>
29193              </field>
29194            </fields>
29195          </register>
29196          <register>
29197            <name>RESULT_RANGE_HI</name>
29198            <description>Channel Range above Hi flags</description>
29199            <addressOffset>0x1A4</addressOffset>
29200            <size>32</size>
29201            <access>read-only</access>
29202            <resetValue>0x0</resetValue>
29203            <resetMask>0xFFFFFFFF</resetMask>
29204            <fields>
29205              <field>
29206                <name>ABOVE_HI</name>
29207                <description>Out of range was detected and the value was above the Hi threshold</description>
29208                <bitRange>[31:0]</bitRange>
29209                <access>read-only</access>
29210              </field>
29211            </fields>
29212          </register>
29213          <register>
29214            <name>STATUS</name>
29215            <description>Current status of internal SAR registers (mostly for debug)</description>
29216            <addressOffset>0x200</addressOffset>
29217            <size>32</size>
29218            <access>read-only</access>
29219            <resetValue>0x0</resetValue>
29220            <resetMask>0xE000371F</resetMask>
29221            <fields>
29222              <field>
29223                <name>CUR_CHAN</name>
29224                <description>current channel being acquired, only valid if BUSY.</description>
29225                <bitRange>[4:0]</bitRange>
29226                <access>read-only</access>
29227              </field>
29228              <field>
29229                <name>CUR_PRIO</name>
29230                <description>priority of current group/channel, only valid if BUSY.</description>
29231                <bitRange>[10:8]</bitRange>
29232                <access>read-only</access>
29233              </field>
29234              <field>
29235                <name>CUR_PREEMPT_TYPE</name>
29236                <description>Preempting type of current group/channel, only valid if BUSY.</description>
29237                <bitRange>[13:12]</bitRange>
29238                <access>read-only</access>
29239              </field>
29240              <field>
29241                <name>DBG_FREEZE</name>
29242                <description>If high then the SAR is prevented from starting a new acquisition, see DBG_FREEZE_EN.</description>
29243                <bitRange>[29:29]</bitRange>
29244                <access>read-only</access>
29245              </field>
29246              <field>
29247                <name>PWRUP_BUSY</name>
29248                <description>If high then the SAR is waiting for PWRUP_TIME due to IDLE_PWRDWN</description>
29249                <bitRange>[30:30]</bitRange>
29250                <access>read-only</access>
29251              </field>
29252              <field>
29253                <name>BUSY</name>
29254                <description>If high then the SAR is busy with a conversion.</description>
29255                <bitRange>[31:31]</bitRange>
29256                <access>read-only</access>
29257              </field>
29258            </fields>
29259          </register>
29260          <register>
29261            <name>AVG_STAT</name>
29262            <description>Current averaging status (for debug)</description>
29263            <addressOffset>0x204</addressOffset>
29264            <size>32</size>
29265            <access>read-only</access>
29266            <resetValue>0x0</resetValue>
29267            <resetMask>0xFF0FFFFF</resetMask>
29268            <fields>
29269              <field>
29270                <name>CUR_AVG_ACCU</name>
29271                <description>the current value of the averaging accumulator</description>
29272                <bitRange>[19:0]</bitRange>
29273                <access>read-only</access>
29274              </field>
29275              <field>
29276                <name>CUR_AVG_CNT</name>
29277                <description>the current value of the averaging counter. Note that the value shown is updated after the sample window and therefore runs ahead of the accumulator update.</description>
29278                <bitRange>[31:24]</bitRange>
29279                <access>read-only</access>
29280              </field>
29281            </fields>
29282          </register>
29283          <cluster>
29284            <dim>32</dim>
29285            <dimIncrement>64</dimIncrement>
29286            <name>CH[%s]</name>
29287            <description>Channel structure</description>
29288            <addressOffset>0x00000800</addressOffset>
29289            <register>
29290              <name>TR_CTL</name>
29291              <description>Trigger control.</description>
29292              <addressOffset>0x0</addressOffset>
29293              <size>32</size>
29294              <access>read-write</access>
29295              <resetValue>0x800</resetValue>
29296              <resetMask>0x80000B77</resetMask>
29297              <fields>
29298                <field>
29299                  <name>SEL</name>
29300                  <description>Trigger select</description>
29301                  <bitRange>[2:0]</bitRange>
29302                  <access>read-write</access>
29303                  <enumeratedValues>
29304                    <enumeratedValue>
29305                      <name>OFF</name>
29306                      <description>Use for channels in group, except the first channel</description>
29307                      <value>0</value>
29308                    </enumeratedValue>
29309                    <enumeratedValue>
29310                      <name>TCPWM</name>
29311                      <description>Trigger from corresponding TCPWM channel</description>
29312                      <value>1</value>
29313                    </enumeratedValue>
29314                    <enumeratedValue>
29315                      <name>GENERIC0</name>
29316                      <description>Generic trigger input 0</description>
29317                      <value>2</value>
29318                    </enumeratedValue>
29319                    <enumeratedValue>
29320                      <name>GENERIC1</name>
29321                      <description>N/A</description>
29322                      <value>3</value>
29323                    </enumeratedValue>
29324                    <enumeratedValue>
29325                      <name>GENERIC2</name>
29326                      <description>N/A</description>
29327                      <value>4</value>
29328                    </enumeratedValue>
29329                    <enumeratedValue>
29330                      <name>GENERIC3</name>
29331                      <description>N/A</description>
29332                      <value>5</value>
29333                    </enumeratedValue>
29334                    <enumeratedValue>
29335                      <name>GENERIC4</name>
29336                      <description>N/A</description>
29337                      <value>6</value>
29338                    </enumeratedValue>
29339                    <enumeratedValue>
29340                      <name>CONTINUOUS</name>
29341                      <description>Always triggered (also called idle), can only be used for at most 1 channel</description>
29342                      <value>7</value>
29343                    </enumeratedValue>
29344                  </enumeratedValues>
29345                </field>
29346                <field>
29347                  <name>PRIO</name>
29348                  <description>Channel priority:
29349'0': highest priority.
29350'1'
29351...
29352'6'
29353'7': lowest priority.
29354
29355Channels with the same priority constitute a priority level. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority level with pending channels is identified. Second, within this priority level, round robin arbitration is applied. Round robin arbitration (within a priority level) gives the highest priority to the lower channel indices (within the priority level).</description>
29356                  <bitRange>[6:4]</bitRange>
29357                  <access>read-write</access>
29358                </field>
29359                <field>
29360                  <name>PREEMPT_TYPE</name>
29361                  <description>Preemption type allow for this group</description>
29362                  <bitRange>[9:8]</bitRange>
29363                  <access>read-write</access>
29364                  <enumeratedValues>
29365                    <enumeratedValue>
29366                      <name>ABORT_CANCEL</name>
29367                      <description>Abort ongoing acquisition, do not return
29368Clear pending trigger for aborted group and set Cancelled interrupt.
29369Also 'Abort' whenever this group (do not pend the trigger) is not immediately scheduled for acquisition after a new trigger arrives.
29370For this preemption type only, only a positive edge on the trigger can trigger the channel, i.e. CONTINUOUS or level high operation is not supported (to avoid continuous Cancelled interrupts).
29371In case CTL.IDLE_PWRDWN is used and the analog is powered down, the group cannot be immediately scheduled for acquisition and therefore a trigger for a group with this preemption type will power up the analog, but the group will ABORT and set the Cancelled interrupt</description>
29372                      <value>0</value>
29373                    </enumeratedValue>
29374                    <enumeratedValue>
29375                      <name>ABORT_RESTART</name>
29376                      <description>Abort ongoing acquisition, up on return Restart group from first channel.</description>
29377                      <value>1</value>
29378                    </enumeratedValue>
29379                    <enumeratedValue>
29380                      <name>ABORT_RESUME</name>
29381                      <description>Abort ongoing acquisition, up on return Resume group from aborted channel
29382If averaging, discard averaging results so far and restart averaging.</description>
29383                      <value>2</value>
29384                    </enumeratedValue>
29385                    <enumeratedValue>
29386                      <name>FINISH_RESUME</name>
29387                      <description>Complete ongoing acquisition (including averaging), up on return Resume group from next channel</description>
29388                      <value>3</value>
29389                    </enumeratedValue>
29390                  </enumeratedValues>
29391                </field>
29392                <field>
29393                  <name>GROUP_END</name>
29394                  <description>0: continue group with next channel
293951: last channel of a group.
29396
29397Note that for the channel with the highest index (SAR_CH_NR) this always needs to be set</description>
29398                  <bitRange>[11:11]</bitRange>
29399                  <access>read-write</access>
29400                </field>
29401                <field>
29402                  <name>DONE_LEVEL</name>
29403                  <description>select level or pulse for 'tr_ch_done' trigger output
29404Also see POST_CTL.TR_DONE_GRP_VIO</description>
29405                  <bitRange>[31:31]</bitRange>
29406                  <access>read-write</access>
29407                  <enumeratedValues>
29408                    <enumeratedValue>
29409                      <name>PULSE</name>
29410                      <description>tr_ch_done generates a 2 cycle pulse (clk_sys), no need to read the result to clear (also no ch_overflow detection)</description>
29411                      <value>0</value>
29412                    </enumeratedValue>
29413                    <enumeratedValue>
29414                      <name>LEVEL</name>
29415                      <description>tr_ch_done  is a level output until the result register is read (typical for DW usage, this also enables ch_overflow detection when DW is too slow)</description>
29416                      <value>1</value>
29417                    </enumeratedValue>
29418                  </enumeratedValues>
29419                </field>
29420              </fields>
29421            </register>
29422            <register>
29423              <name>SAMPLE_CTL</name>
29424              <description>Sample control.</description>
29425              <addressOffset>0x4</addressOffset>
29426              <size>32</size>
29427              <access>read-write</access>
29428              <resetValue>0x0</resetValue>
29429              <resetMask>0x0</resetMask>
29430              <fields>
29431                <field>
29432                  <name>PIN_ADDR</name>
29433                  <description>N/A</description>
29434                  <bitRange>[5:0]</bitRange>
29435                  <access>read-write</access>
29436                </field>
29437                <field>
29438                  <name>PORT_ADDR</name>
29439                  <description>Select the physical port. This field is only valid for ADC0.
29440ADC0 can control and connect to the SARMUX of the neighboring ADC1-3. This requires the corresponding ADC to be off while the SARMUX is left on.
29441When ADC0 controls another SARMUX it uses the PIN_ADDR, EXT_MUX_EN/SEL of this channel to control the other SARMUX.</description>
29442                  <bitRange>[7:6]</bitRange>
29443                  <access>read-write</access>
29444                  <enumeratedValues>
29445                    <enumeratedValue>
29446                      <name>SARMUX0</name>
29447                      <description>ADC uses it's own SARMUX</description>
29448                      <value>0</value>
29449                    </enumeratedValue>
29450                    <enumeratedValue>
29451                      <name>SARMUX1</name>
29452                      <description>ADC0 uses SARMUX1 (only valid for ADC0, undefined result if used for ADC1-3)</description>
29453                      <value>1</value>
29454                    </enumeratedValue>
29455                    <enumeratedValue>
29456                      <name>SARMUX2</name>
29457                      <description>ADC0 uses SARMUX2 (only valid for ADC0, undefined result if used for ADC1-3)</description>
29458                      <value>2</value>
29459                    </enumeratedValue>
29460                    <enumeratedValue>
29461                      <name>SARMUX3</name>
29462                      <description>ADC0 uses SARMUX3 (only valid for ADC0, undefined result if used for ADC1-3)</description>
29463                      <value>3</value>
29464                    </enumeratedValue>
29465                  </enumeratedValues>
29466                </field>
29467                <field>
29468                  <name>EXT_MUX_SEL</name>
29469                  <description>External analog mux select.
29470This bit setting is related to EXT_MUX[x]_y on pin assignment.
29471 0x0: Select EXT_MUX[x]_0 pin
29472 0x1: Select EXT_MUX[x]_1 pin</description>
29473                  <bitRange>[10:8]</bitRange>
29474                  <access>read-write</access>
29475                </field>
29476                <field>
29477                  <name>EXT_MUX_EN</name>
29478                  <description>External analog mux enable.
29479This enable can  be used as enable (chip select) for the external analog mux (this enable is not used as enable for the GPIO output driver).
29480This enable also prevents unnecessary toggle activity on the select signals of the external analog mux. When this enable is low EXT_MUX_SEL value will be ignored and the previous value will be maintained.
29481Note that an external analog mux can only be used in combination with a pin input, i.e. PIN_ADDR&lt;32 or Vmotor. If an internal signal is selected this enable should be 0.</description>
29482                  <bitRange>[11:11]</bitRange>
29483                  <access>read-write</access>
29484                </field>
29485                <field>
29486                  <name>PRECOND_MODE</name>
29487                  <description>Select preconditioning mode.
29488Preconditioning (dis)charges the SAR sample capacitor to the selected reference voltage for PRECOND_TIME (global) cycles, a break before make cycle will be inserted before sampling starts (SAMPLE_TIME).</description>
29489                  <bitRange>[13:12]</bitRange>
29490                  <access>read-write</access>
29491                  <enumeratedValues>
29492                    <enumeratedValue>
29493                      <name>OFF</name>
29494                      <description>No preconditioning</description>
29495                      <value>0</value>
29496                    </enumeratedValue>
29497                    <enumeratedValue>
29498                      <name>VREFL</name>
29499                      <description>Discharge to VREFL</description>
29500                      <value>1</value>
29501                    </enumeratedValue>
29502                    <enumeratedValue>
29503                      <name>VREFH</name>
29504                      <description>Charge to VREFH</description>
29505                      <value>2</value>
29506                    </enumeratedValue>
29507                    <enumeratedValue>
29508                      <name>DIAG</name>
29509                      <description>Connect the Diagnostic reference output during preconditioning. The Diagnostic reference should be configured to output a reference voltage.
29510Note: this selection is mutual exclusive with using the Diagnostic reference to supply an ibias current for OVERLAP.</description>
29511                      <value>3</value>
29512                    </enumeratedValue>
29513                  </enumeratedValues>
29514                </field>
29515                <field>
29516                  <name>OVERLAP_DIAG</name>
29517                  <description>Select Overlap mode or SARMUX Diagnostics, in both cases the Diagnostic reference is used.
29518With Overlap the Diagnostic reference typically sources or sinks a small current which is connected at the same time as the analog signal being sampled.
29519For SARMUX Diagnostics the Diagnostic reference should provide a reference voltage which is selected at the SARMUX input instead of the normal analog signal being sampled.</description>
29520                  <bitRange>[15:14]</bitRange>
29521                  <access>read-write</access>
29522                  <enumeratedValues>
29523                    <enumeratedValue>
29524                      <name>OFF</name>
29525                      <description>No overlap or SARMUX Diagnostics</description>
29526                      <value>0</value>
29527                    </enumeratedValue>
29528                    <enumeratedValue>
29529                      <name>HALF</name>
29530                      <description>Sample the selected analog input for 2 SAMPLE_TIME periods. During the first period use overlap sampling, i.e. connect both the analog input and Diagnostic reference. During second period only connect the analog input.</description>
29531                      <value>1</value>
29532                    </enumeratedValue>
29533                    <enumeratedValue>
29534                      <name>FULL</name>
29535                      <description>Like normal sample the selected analog input for a single SAMPLE_TIME period but use overlap sampling, i.e. connect both the analog input and Diagnostic reference.</description>
29536                      <value>2</value>
29537                    </enumeratedValue>
29538                    <enumeratedValue>
29539                      <name>MUX_DIAG</name>
29540                      <description>Select Diagnostic reference instead of analog signal at the input of the SARMUX. This enables a functional safety check of the SARMUX analog connections.</description>
29541                      <value>3</value>
29542                    </enumeratedValue>
29543                  </enumeratedValues>
29544                </field>
29545                <field>
29546                  <name>SAMPLE_TIME</name>
29547                  <description>Sample time (aperture) in ADC clock cycles. Minimum is 1 (0 gives the same result as 1), minimum time needed for proper settling is at least 412ns, i.e.11 clock cycles at the max frequency of 26.7MHz.</description>
29548                  <bitRange>[27:16]</bitRange>
29549                  <access>read-write</access>
29550                </field>
29551                <field>
29552                  <name>ALT_CAL</name>
29553                  <description>Use alternate calibration values instead of the current calibration values.
29554This allows the firmware to allocate one or more channels to quietly re-calibrate the ADC in the background of regular processing.
295550 = use regular calibration values (ANA/DIG_CAL)
295561 = use alternate calibration values (ANA/DIG_CAL_ALT)
29557Note: typically calibration measurements select VrefL (PIN_ADDR=62) or VrefH (PIN_ADDR=63)</description>
29558                  <bitRange>[31:31]</bitRange>
29559                  <access>read-write</access>
29560                </field>
29561              </fields>
29562            </register>
29563            <register>
29564              <name>POST_CTL</name>
29565              <description>Post processing control</description>
29566              <addressOffset>0x8</addressOffset>
29567              <size>32</size>
29568              <access>read-write</access>
29569              <resetValue>0x0</resetValue>
29570              <resetMask>0x0</resetMask>
29571              <fields>
29572                <field>
29573                  <name>POST_PROC</name>
29574                  <description>Post processing</description>
29575                  <bitRange>[2:0]</bitRange>
29576                  <access>read-write</access>
29577                  <enumeratedValues>
29578                    <enumeratedValue>
29579                      <name>NONE</name>
29580                      <description>No postprocessing</description>
29581                      <value>0</value>
29582                    </enumeratedValue>
29583                    <enumeratedValue>
29584                      <name>AVG</name>
29585                      <description>Averaging</description>
29586                      <value>1</value>
29587                    </enumeratedValue>
29588                    <enumeratedValue>
29589                      <name>AVG_RANGE</name>
29590                      <description>Averaging followed by Range detect</description>
29591                      <value>2</value>
29592                    </enumeratedValue>
29593                    <enumeratedValue>
29594                      <name>RANGE</name>
29595                      <description>Range detect</description>
29596                      <value>3</value>
29597                    </enumeratedValue>
29598                    <enumeratedValue>
29599                      <name>RANGE_PULSE</name>
29600                      <description>Range detect followed by pulse detect</description>
29601                      <value>4</value>
29602                    </enumeratedValue>
29603                    <enumeratedValue>
29604                      <name>RSVD0</name>
29605                      <description>N/A</description>
29606                      <value>5</value>
29607                    </enumeratedValue>
29608                    <enumeratedValue>
29609                      <name>RSVD1</name>
29610                      <description>N/A</description>
29611                      <value>6</value>
29612                    </enumeratedValue>
29613                    <enumeratedValue>
29614                      <name>RSVD2</name>
29615                      <description>N/A</description>
29616                      <value>7</value>
29617                    </enumeratedValue>
29618                  </enumeratedValues>
29619                </field>
29620                <field>
29621                  <name>LEFT_ALIGN</name>
29622                  <description>Left or right align data in result[15:0].
296230: the data is right aligned in result[11:0], with sign extension to 16 bits if enabled
296241: the data is left aligned in result[15:4] with the lower nibble 0. Caveat if the result was more than 12 bits (e.g. after averaging) then the bits above 12 will be discarded.</description>
29625                  <bitRange>[6:6]</bitRange>
29626                  <access>read-write</access>
29627                </field>
29628                <field>
29629                  <name>SIGN_EXT</name>
29630                  <description>Output data is sign extended</description>
29631                  <bitRange>[7:7]</bitRange>
29632                  <access>read-write</access>
29633                  <enumeratedValues>
29634                    <enumeratedValue>
29635                      <name>UNSIGNED</name>
29636                      <description>Default: result data is unsigned (zero extended if needed)</description>
29637                      <value>0</value>
29638                    </enumeratedValue>
29639                    <enumeratedValue>
29640                      <name>SIGNED</name>
29641                      <description>Result data is signed (sign extended if needed)</description>
29642                      <value>1</value>
29643                    </enumeratedValue>
29644                  </enumeratedValues>
29645                </field>
29646                <field>
29647                  <name>AVG_CNT</name>
29648                  <description>Either averaging count (minus 1) or Pulse positive reload value
29649
29650Averaging Count for channels that have averaging enabled. A channel will be sampled (AVG_CNT+1) = [1..256] times.
29651The signal will be acquired back to back  (1st order accumulate and dump filter), the average result is calculated and stored and then the next enabled channel is sampled.
29652If more than 16 sample are taken (AVG_CNT&gt;=16) then AVG_SHIFT must be set so that the result after shifting fits in 16 bits
29653
29654Pulse detect positive reload value PULSE_POS_RL[7:0]</description>
29655                  <bitRange>[15:8]</bitRange>
29656                  <access>read-write</access>
29657                </field>
29658                <field>
29659                  <name>SHIFT_R</name>
29660                  <description>Either Shift Right (no pulse detection) or Pulse negative reload value (if pulse detection is enabled)
29661
29662Shift right SHIFT_R[3:0] = [0..12]: the result (typically after averaging) is shifted right as specified here. Software has to make sure that the result fits in less than 16 bits.
29663Any value &gt;12 will be treated as 12, bit [4] is always ignored. This can also be used to fit the 12-bit result in 8 bits.
29664
29665Pulse detect negative reload value PULSE_NEG_RL[4:0]</description>
29666                  <bitRange>[20:16]</bitRange>
29667                  <access>read-write</access>
29668                </field>
29669                <field>
29670                  <name>RANGE_MODE</name>
29671                  <description>Range detect mode</description>
29672                  <bitRange>[23:22]</bitRange>
29673                  <access>read-write</access>
29674                  <enumeratedValues>
29675                    <enumeratedValue>
29676                      <name>BELOW_LO</name>
29677                      <description>Below Low threshold (result &lt; Lo)</description>
29678                      <value>0</value>
29679                    </enumeratedValue>
29680                    <enumeratedValue>
29681                      <name>INSIDE_RANGE</name>
29682                      <description>Inside range (Lo &lt;= result &lt; Hi)</description>
29683                      <value>1</value>
29684                    </enumeratedValue>
29685                    <enumeratedValue>
29686                      <name>ABOVE_HI</name>
29687                      <description>Above high threshold (Hi &lt;= result)</description>
29688                      <value>2</value>
29689                    </enumeratedValue>
29690                    <enumeratedValue>
29691                      <name>OUTSIDE_RANGE</name>
29692                      <description>Outside range (result &lt; Lo || Hi &lt;= result)</description>
29693                      <value>3</value>
29694                    </enumeratedValue>
29695                  </enumeratedValues>
29696                </field>
29697                <field>
29698                  <name>TR_DONE_GRP_VIO</name>
29699                  <description>Select tr_sar_ch_done mode for last channel of a group, ignored for all other channels
29700Also see TR_CTL.DONE_LEVEL</description>
29701                  <bitRange>[25:25]</bitRange>
29702                  <access>read-write</access>
29703                  <enumeratedValues>
29704                    <enumeratedValue>
29705                      <name>DONE</name>
29706                      <description>Default: tr_sar_ch_done is set when the group is done</description>
29707                      <value>0</value>
29708                    </enumeratedValue>
29709                    <enumeratedValue>
29710                      <name>GRP_RANGE_VIO</name>
29711                      <description>tr_sar_ch_done  is only set if any of the channels in the group has a Range Violation. This mode is ignored if this is not the last channel in the group.
29712Note that if none of the channels in the group have Range detection enabled then the trigger will never get set.</description>
29713                      <value>1</value>
29714                    </enumeratedValue>
29715                  </enumeratedValues>
29716                </field>
29717              </fields>
29718            </register>
29719            <register>
29720              <name>RANGE_CTL</name>
29721              <description>Range thresholds</description>
29722              <addressOffset>0xC</addressOffset>
29723              <size>32</size>
29724              <access>read-write</access>
29725              <resetValue>0x0</resetValue>
29726              <resetMask>0x0</resetMask>
29727              <fields>
29728                <field>
29729                  <name>RANGE_LO</name>
29730                  <description>Range detect low threshold (Lo)</description>
29731                  <bitRange>[15:0]</bitRange>
29732                  <access>read-write</access>
29733                </field>
29734                <field>
29735                  <name>RANGE_HI</name>
29736                  <description>Range detect high threshold (Hi)</description>
29737                  <bitRange>[31:16]</bitRange>
29738                  <access>read-write</access>
29739                </field>
29740              </fields>
29741            </register>
29742            <register>
29743              <name>INTR</name>
29744              <description>Interrupt request register.</description>
29745              <addressOffset>0x10</addressOffset>
29746              <size>32</size>
29747              <access>read-write</access>
29748              <resetValue>0x0</resetValue>
29749              <resetMask>0x707</resetMask>
29750              <fields>
29751                <field>
29752                  <name>GRP_DONE</name>
29753                  <description>Done Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done. Write with '1' to clear bit.</description>
29754                  <bitRange>[0:0]</bitRange>
29755                  <access>read-write</access>
29756                </field>
29757                <field>
29758                  <name>GRP_CANCELLED</name>
29759                  <description>Cancelled Interrupt: hardware sets this interrupt for the last channel of a group if the group scan was preempted and CANCELLED. Note that it is possible that also the GRP_DONE interrupt is set. If that is the case one or more new triggers were detected while the group was already busy, i.e. triggers are too fast.   Write with '1' to clear bit.</description>
29760                  <bitRange>[1:1]</bitRange>
29761                  <access>read-write</access>
29762                </field>
29763                <field>
29764                  <name>GRP_OVERFLOW</name>
29765                  <description>Overflow Interrupt: hardware sets this interrupt for the last channel of a group if the group scan is done and the Done interrupt is already (still) pending. Write with '1' to clear bit.</description>
29766                  <bitRange>[2:2]</bitRange>
29767                  <access>read-write</access>
29768                </field>
29769                <field>
29770                  <name>CH_RANGE</name>
29771                  <description>Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. This interrupt is mutual exclusive with Pulse detect interrupt. Write with '1' to clear bit.</description>
29772                  <bitRange>[8:8]</bitRange>
29773                  <access>read-write</access>
29774                </field>
29775                <field>
29776                  <name>CH_PULSE</name>
29777                  <description>Pulse detect Interrupt: hardware sets this interrupt for each channel if the positive pulse counter reaches zero. This interrupt is mutual exclusive with Range detect interrupt. Write with '1' to clear bit.</description>
29778                  <bitRange>[9:9]</bitRange>
29779                  <access>read-write</access>
29780                </field>
29781                <field>
29782                  <name>CH_OVERFLOW</name>
29783                  <description>Channel overflow Interrupt: hardware sets this interrupt for each channel if a new Pulse or Range interrupt is detected while the interrupt is still pending or when DW did not acknowledge data pickup. Write with '1' to clear bit.</description>
29784                  <bitRange>[10:10]</bitRange>
29785                  <access>read-write</access>
29786                </field>
29787              </fields>
29788            </register>
29789            <register>
29790              <name>INTR_SET</name>
29791              <description>Interrupt set request register</description>
29792              <addressOffset>0x14</addressOffset>
29793              <size>32</size>
29794              <access>read-write</access>
29795              <resetValue>0x0</resetValue>
29796              <resetMask>0x707</resetMask>
29797              <fields>
29798                <field>
29799                  <name>GRP_DONE_SET</name>
29800                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
29801                  <bitRange>[0:0]</bitRange>
29802                  <access>read-write</access>
29803                </field>
29804                <field>
29805                  <name>GRP_CANCELLED_SET</name>
29806                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
29807                  <bitRange>[1:1]</bitRange>
29808                  <access>read-write</access>
29809                </field>
29810                <field>
29811                  <name>GRP_OVERFLOW_SET</name>
29812                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
29813                  <bitRange>[2:2]</bitRange>
29814                  <access>read-write</access>
29815                </field>
29816                <field>
29817                  <name>CH_RANGE_SET</name>
29818                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
29819                  <bitRange>[8:8]</bitRange>
29820                  <access>read-write</access>
29821                </field>
29822                <field>
29823                  <name>CH_PULSE_SET</name>
29824                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
29825                  <bitRange>[9:9]</bitRange>
29826                  <access>read-write</access>
29827                </field>
29828                <field>
29829                  <name>CH_OVERFLOW_SET</name>
29830                  <description>Write with '1' to set corresponding bit in interrupt request register.</description>
29831                  <bitRange>[10:10]</bitRange>
29832                  <access>read-write</access>
29833                </field>
29834              </fields>
29835            </register>
29836            <register>
29837              <name>INTR_MASK</name>
29838              <description>Interrupt mask register.</description>
29839              <addressOffset>0x18</addressOffset>
29840              <size>32</size>
29841              <access>read-write</access>
29842              <resetValue>0x0</resetValue>
29843              <resetMask>0x707</resetMask>
29844              <fields>
29845                <field>
29846                  <name>GRP_DONE_MASK</name>
29847                  <description>Mask bit for corresponding bit in interrupt request register.</description>
29848                  <bitRange>[0:0]</bitRange>
29849                  <access>read-write</access>
29850                </field>
29851                <field>
29852                  <name>GRP_CANCELLED_MASK</name>
29853                  <description>Mask bit for corresponding bit in interrupt request register.</description>
29854                  <bitRange>[1:1]</bitRange>
29855                  <access>read-write</access>
29856                </field>
29857                <field>
29858                  <name>GRP_OVERFLOW_MASK</name>
29859                  <description>Mask bit for corresponding bit in interrupt request register.</description>
29860                  <bitRange>[2:2]</bitRange>
29861                  <access>read-write</access>
29862                </field>
29863                <field>
29864                  <name>CH_RANGE_MASK</name>
29865                  <description>Mask bit for corresponding bit in interrupt request register.</description>
29866                  <bitRange>[8:8]</bitRange>
29867                  <access>read-write</access>
29868                </field>
29869                <field>
29870                  <name>CH_PULSE_MASK</name>
29871                  <description>Mask bit for corresponding bit in interrupt request register.</description>
29872                  <bitRange>[9:9]</bitRange>
29873                  <access>read-write</access>
29874                </field>
29875                <field>
29876                  <name>CH_OVERFLOW_MASK</name>
29877                  <description>Mask bit for corresponding bit in interrupt request register.</description>
29878                  <bitRange>[10:10]</bitRange>
29879                  <access>read-write</access>
29880                </field>
29881              </fields>
29882            </register>
29883            <register>
29884              <name>INTR_MASKED</name>
29885              <description>Interrupt masked request register</description>
29886              <addressOffset>0x1C</addressOffset>
29887              <size>32</size>
29888              <access>read-only</access>
29889              <resetValue>0x0</resetValue>
29890              <resetMask>0x707</resetMask>
29891              <fields>
29892                <field>
29893                  <name>GRP_DONE_MASKED</name>
29894                  <description>Logical and of corresponding request and mask bits.</description>
29895                  <bitRange>[0:0]</bitRange>
29896                  <access>read-only</access>
29897                </field>
29898                <field>
29899                  <name>GRP_CANCELLED_MASKED</name>
29900                  <description>Logical and of corresponding request and mask bits.</description>
29901                  <bitRange>[1:1]</bitRange>
29902                  <access>read-only</access>
29903                </field>
29904                <field>
29905                  <name>GRP_OVERFLOW_MASKED</name>
29906                  <description>Logical and of corresponding request and mask bits.</description>
29907                  <bitRange>[2:2]</bitRange>
29908                  <access>read-only</access>
29909                </field>
29910                <field>
29911                  <name>CH_RANGE_MASKED</name>
29912                  <description>Logical and of corresponding request and mask bits.</description>
29913                  <bitRange>[8:8]</bitRange>
29914                  <access>read-only</access>
29915                </field>
29916                <field>
29917                  <name>CH_PULSE_MASKED</name>
29918                  <description>Logical and of corresponding request and mask bits.</description>
29919                  <bitRange>[9:9]</bitRange>
29920                  <access>read-only</access>
29921                </field>
29922                <field>
29923                  <name>CH_OVERFLOW_MASKED</name>
29924                  <description>Logical and of corresponding request and mask bits.</description>
29925                  <bitRange>[10:10]</bitRange>
29926                  <access>read-only</access>
29927                </field>
29928              </fields>
29929            </register>
29930            <register>
29931              <name>WORK</name>
29932              <description>Working data register</description>
29933              <addressOffset>0x20</addressOffset>
29934              <size>32</size>
29935              <access>read-only</access>
29936              <resetValue>0x0</resetValue>
29937              <resetMask>0xF0000000</resetMask>
29938              <fields>
29939                <field>
29940                  <name>WORK</name>
29941                  <description>SAR conversion working data of the channel. The data is written here right after sampling this channel.</description>
29942                  <bitRange>[15:0]</bitRange>
29943                  <access>read-only</access>
29944                </field>
29945                <field>
29946                  <name>ABOVE_HI_MIR</name>
29947                  <description>mirror bit of the corresponding ABOVE_HI bit</description>
29948                  <bitRange>[28:28]</bitRange>
29949                  <access>read-only</access>
29950                </field>
29951                <field>
29952                  <name>RANGE_MIR</name>
29953                  <description>mirror bit of corresponding bit in WORK_RANGE register</description>
29954                  <bitRange>[29:29]</bitRange>
29955                  <access>read-only</access>
29956                </field>
29957                <field>
29958                  <name>PULSE_MIR</name>
29959                  <description>mirror bit of corresponding bit in WORK_PULSE register</description>
29960                  <bitRange>[30:30]</bitRange>
29961                  <access>read-only</access>
29962                </field>
29963                <field>
29964                  <name>VALID_MIR</name>
29965                  <description>mirror bit of corresponding bit in WORK_VALID register</description>
29966                  <bitRange>[31:31]</bitRange>
29967                  <access>read-only</access>
29968                </field>
29969              </fields>
29970            </register>
29971            <register>
29972              <name>RESULT</name>
29973              <description>Result data register</description>
29974              <addressOffset>0x24</addressOffset>
29975              <size>32</size>
29976              <access>read-only</access>
29977              <resetValue>0x0</resetValue>
29978              <resetMask>0xF0000000</resetMask>
29979              <fields>
29980                <field>
29981                  <name>RESULT</name>
29982                  <description>SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.</description>
29983                  <bitRange>[15:0]</bitRange>
29984                  <access>read-only</access>
29985                </field>
29986                <field>
29987                  <name>ABOVE_HI_MIR</name>
29988                  <description>mirror bit of the corresponding ABOVE_HI bit</description>
29989                  <bitRange>[28:28]</bitRange>
29990                  <access>read-only</access>
29991                </field>
29992                <field>
29993                  <name>RANGE_INTR_MIR</name>
29994                  <description>mirror bit of INTR.CH_RANGE bit</description>
29995                  <bitRange>[29:29]</bitRange>
29996                  <access>read-only</access>
29997                </field>
29998                <field>
29999                  <name>PULSE_INTR_MIR</name>
30000                  <description>mirror bit of INTR.CH_PULSE bit</description>
30001                  <bitRange>[30:30]</bitRange>
30002                  <access>read-only</access>
30003                </field>
30004                <field>
30005                  <name>VALID_MIR</name>
30006                  <description>mirror bit of the corresponding bit in RESULT_VALID register</description>
30007                  <bitRange>[31:31]</bitRange>
30008                  <access>read-only</access>
30009                </field>
30010              </fields>
30011            </register>
30012            <register>
30013              <name>GRP_STAT</name>
30014              <description>Group status register</description>
30015              <addressOffset>0x28</addressOffset>
30016              <size>32</size>
30017              <access>read-only</access>
30018              <resetValue>0x0</resetValue>
30019              <resetMask>0x10707</resetMask>
30020              <fields>
30021                <field>
30022                  <name>GRP_COMPLETE</name>
30023                  <description>Group acquisition complete.
30024This is a copy of the INTR.GRP_DONE bit.</description>
30025                  <bitRange>[0:0]</bitRange>
30026                  <access>read-only</access>
30027                </field>
30028                <field>
30029                  <name>GRP_CANCELLED</name>
30030                  <description>Group Cancelled.
30031This is a copy of the INTR.GRP_CANCELLED bit.</description>
30032                  <bitRange>[1:1]</bitRange>
30033                  <access>read-only</access>
30034                </field>
30035                <field>
30036                  <name>GRP_OVERFLOW</name>
30037                  <description>Group Overflow.
30038This is a copy of the INTR.GRP_OVERFLOW bit.</description>
30039                  <bitRange>[2:2]</bitRange>
30040                  <access>read-only</access>
30041                </field>
30042                <field>
30043                  <name>CH_RANGE_COMPLETE</name>
30044                  <description>Channel Range complete.
30045This is a copy of the INTR.CH_RANGE bit.</description>
30046                  <bitRange>[8:8]</bitRange>
30047                  <access>read-only</access>
30048                </field>
30049                <field>
30050                  <name>CH_PULSE_COMPLETE</name>
30051                  <description>Channel Pulse complete.
30052This is a copy of the INTR.CH_PULSE bit.</description>
30053                  <bitRange>[9:9]</bitRange>
30054                  <access>read-only</access>
30055                </field>
30056                <field>
30057                  <name>CH_OVERFLOW</name>
30058                  <description>Channel Overflow.
30059This is a copy of the INTR.CH_OVERFLOW bit.</description>
30060                  <bitRange>[10:10]</bitRange>
30061                  <access>read-only</access>
30062                </field>
30063                <field>
30064                  <name>GRP_BUSY</name>
30065                  <description>Group acquisition busy.
30066This is a copy of the TR_PENDING bit of the first channel of the group.</description>
30067                  <bitRange>[16:16]</bitRange>
30068                  <access>read-only</access>
30069                </field>
30070              </fields>
30071            </register>
30072            <register>
30073              <name>ENABLE</name>
30074              <description>Enable register</description>
30075              <addressOffset>0x38</addressOffset>
30076              <size>32</size>
30077              <access>read-write</access>
30078              <resetValue>0x0</resetValue>
30079              <resetMask>0x1</resetMask>
30080              <fields>
30081                <field>
30082                  <name>CHAN_EN</name>
30083                  <description>Channel enable.
30084- 0: the corresponding channel is disabled. Corresponding trigger will be reset immediately.
30085- 1: the corresponding channel is enabled.
30086
30087Note: To disable a group either stop the trigger first or begin with disabling the lowest channel first. To enable a group either start with enabling the last channel first and the first channel last, or start the trigger after all channels are enabled. If these rules are not followed the result is undefined.</description>
30088                  <bitRange>[0:0]</bitRange>
30089                  <access>read-write</access>
30090                </field>
30091              </fields>
30092            </register>
30093            <register>
30094              <name>TR_CMD</name>
30095              <description>Software triggers</description>
30096              <addressOffset>0x3C</addressOffset>
30097              <size>32</size>
30098              <access>read-write</access>
30099              <resetValue>0x0</resetValue>
30100              <resetMask>0x1</resetMask>
30101              <fields>
30102                <field>
30103                  <name>START</name>
30104                  <description>Software start trigger. When written with '1', a start trigger is generated which sets the corresponding TR_PEND bit (only if the channel is enabled). A read always returns a 0.</description>
30105                  <bitRange>[0:0]</bitRange>
30106                  <access>read-write</access>
30107                </field>
30108              </fields>
30109            </register>
30110          </cluster>
30111        </cluster>
30112        <cluster>
30113          <name>EPASS_MMIO</name>
30114          <description>PASS top-level MMIO (Generic Triggers)</description>
30115          <addressOffset>0x000F0000</addressOffset>
30116          <register>
30117            <name>PASS_CTL</name>
30118            <description>PASS control register</description>
30119            <addressOffset>0x0</addressOffset>
30120            <size>32</size>
30121            <access>read-write</access>
30122            <resetValue>0x0</resetValue>
30123            <resetMask>0xF0600033</resetMask>
30124            <fields>
30125              <field>
30126                <name>SUPPLY_MON_EN_A</name>
30127                <description>Supply monitor enable for AMUXBUS_A (amuxbus_a_mon)</description>
30128                <bitRange>[0:0]</bitRange>
30129                <access>read-write</access>
30130              </field>
30131              <field>
30132                <name>SUPPLY_MON_LVL_A</name>
30133                <description>Supply monitor level select for AMUXBUS_A</description>
30134                <bitRange>[1:1]</bitRange>
30135                <access>read-write</access>
30136                <enumeratedValues>
30137                  <enumeratedValue>
30138                    <name>VRL</name>
30139                    <description>amuxbus_a_mon = VRL</description>
30140                    <value>0</value>
30141                  </enumeratedValue>
30142                  <enumeratedValue>
30143                    <name>VRH</name>
30144                    <description>amuxbus_a_mon = VRH</description>
30145                    <value>1</value>
30146                  </enumeratedValue>
30147                </enumeratedValues>
30148              </field>
30149              <field>
30150                <name>SUPPLY_MON_EN_B</name>
30151                <description>Supply monitor enable for AMUXBUS_B (amuxbus_b_mon)</description>
30152                <bitRange>[4:4]</bitRange>
30153                <access>read-write</access>
30154              </field>
30155              <field>
30156                <name>SUPPLY_MON_LVL_B</name>
30157                <description>Supply monitor level select for AMUXBUS_B</description>
30158                <bitRange>[5:5]</bitRange>
30159                <access>read-write</access>
30160                <enumeratedValues>
30161                  <enumeratedValue>
30162                    <name>VRL</name>
30163                    <description>amuxbus_b_mon = VRL</description>
30164                    <value>0</value>
30165                  </enumeratedValue>
30166                  <enumeratedValue>
30167                    <name>VRH</name>
30168                    <description>amuxbus_b_mon = VRH</description>
30169                    <value>1</value>
30170                  </enumeratedValue>
30171                </enumeratedValues>
30172              </field>
30173              <field>
30174                <name>REFBUF_MODE</name>
30175                <description>Reference mode.
30176The reference needs to be present when using TEMP sensor or diagnostic reference (in addition to SAR.DIAG_CTL.DIAG_EN).
30177Note that setting this mode is not required for the ADC operation itself.</description>
30178                <bitRange>[22:21]</bitRange>
30179                <access>read-write</access>
30180                <enumeratedValues>
30181                  <enumeratedValue>
30182                    <name>OFF</name>
30183                    <description>No reference</description>
30184                    <value>0</value>
30185                  </enumeratedValue>
30186                  <enumeratedValue>
30187                    <name>ON</name>
30188                    <description>Reference = buffered Vbg from SRSS</description>
30189                    <value>1</value>
30190                  </enumeratedValue>
30191                  <enumeratedValue>
30192                    <name>RSVD</name>
30193                    <description>undefined</description>
30194                    <value>2</value>
30195                  </enumeratedValue>
30196                  <enumeratedValue>
30197                    <name>BYPASS</name>
30198                    <description>Reference = unbuffered Vbg from SRSS</description>
30199                    <value>3</value>
30200                  </enumeratedValue>
30201                </enumeratedValues>
30202              </field>
30203              <field>
30204                <name>DBG_FREEZE_EN</name>
30205                <description>Debug pause enable, 1 per ADC.
30206When set a high tr_debug_freeze trigger will prevent the scheduler from starting acquisitions on a new channel. Note that averaging for an already started channel will be completed.</description>
30207                <bitRange>[31:28]</bitRange>
30208                <access>read-write</access>
30209              </field>
30210            </fields>
30211          </register>
30212          <register>
30213            <dim>4</dim>
30214            <dimIncrement>4</dimIncrement>
30215            <name>SAR_TR_IN_SEL[%s]</name>
30216            <description>per SAR generic input trigger select</description>
30217            <addressOffset>0x20</addressOffset>
30218            <size>32</size>
30219            <access>read-write</access>
30220            <resetValue>0x43210</resetValue>
30221            <resetMask>0xFFFFF</resetMask>
30222            <fields>
30223              <field>
30224                <name>IN0_SEL</name>
30225                <description>Select generic trigger for SAR generic trigger input 0</description>
30226                <bitRange>[3:0]</bitRange>
30227                <access>read-write</access>
30228              </field>
30229              <field>
30230                <name>IN1_SEL</name>
30231                <description>Select generic trigger for SAR generic trigger input 1</description>
30232                <bitRange>[7:4]</bitRange>
30233                <access>read-write</access>
30234              </field>
30235              <field>
30236                <name>IN2_SEL</name>
30237                <description>Select generic trigger for SAR generic trigger input 2</description>
30238                <bitRange>[11:8]</bitRange>
30239                <access>read-write</access>
30240              </field>
30241              <field>
30242                <name>IN3_SEL</name>
30243                <description>Select generic trigger for SAR generic trigger input 3</description>
30244                <bitRange>[15:12]</bitRange>
30245                <access>read-write</access>
30246              </field>
30247              <field>
30248                <name>IN4_SEL</name>
30249                <description>Select generic trigger for SAR generic trigger input 4</description>
30250                <bitRange>[19:16]</bitRange>
30251                <access>read-write</access>
30252              </field>
30253            </fields>
30254          </register>
30255          <register>
30256            <dim>4</dim>
30257            <dimIncrement>4</dimIncrement>
30258            <name>SAR_TR_OUT_SEL[%s]</name>
30259            <description>per SAR generic output trigger select</description>
30260            <addressOffset>0x40</addressOffset>
30261            <size>32</size>
30262            <access>read-write</access>
30263            <resetValue>0x100</resetValue>
30264            <resetMask>0x3F3F</resetMask>
30265            <fields>
30266              <field>
30267                <name>OUT0_SEL</name>
30268                <description>Select SAR output trigger for generic trigger output 0
302690-31: selects a tr_sar_ch_done trigger
3027032-63: selects a tr_sar_ch_rangvio trigger</description>
30271                <bitRange>[5:0]</bitRange>
30272                <access>read-write</access>
30273              </field>
30274              <field>
30275                <name>OUT1_SEL</name>
30276                <description>Select SAR output trigger for generic trigger output 1</description>
30277                <bitRange>[13:8]</bitRange>
30278                <access>read-write</access>
30279              </field>
30280            </fields>
30281          </register>
30282          <register>
30283            <name>TEST_CTL</name>
30284            <description>Test control bits</description>
30285            <addressOffset>0x80</addressOffset>
30286            <size>32</size>
30287            <access>read-write</access>
30288            <resetValue>0x0</resetValue>
30289            <resetMask>0x137D</resetMask>
30290            <fields>
30291              <field>
30292                <name>TS_CAL_CUR_IN</name>
30293                <description>External current input switch control, for Temperature Sensor Calibration</description>
30294                <bitRange>[0:0]</bitRange>
30295                <access>read-write</access>
30296              </field>
30297              <field>
30298                <name>TS_CAL_VB_OUT</name>
30299                <description>Voltage Base switch control, for Temperature Sensor Calibration</description>
30300                <bitRange>[2:2]</bitRange>
30301                <access>read-write</access>
30302              </field>
30303              <field>
30304                <name>TS_CAL_VE_OUT</name>
30305                <description>Voltage Emitter switch control, for Temperature Sensor Calibration</description>
30306                <bitRange>[3:3]</bitRange>
30307                <access>read-write</access>
30308              </field>
30309              <field>
30310                <name>TS_CAL_DIODE_EN</name>
30311                <description>Diode Enable, disconnect or connect the base and collector terminal of the BJT</description>
30312                <bitRange>[4:4]</bitRange>
30313                <access>read-write</access>
30314              </field>
30315              <field>
30316                <name>TS_CAL_DIODE_PNP_EN</name>
30317                <description>Enable signal for PNP transistor. This transistor will be used only during calibration for accurate estimation of chip temp.
303180 = Turn PNP off
303191 = Configure PNP as a diode (short base and collector)</description>
30320                <bitRange>[5:5]</bitRange>
30321                <access>read-write</access>
30322              </field>
30323              <field>
30324                <name>TS_CAL_VI_SEL</name>
30325                <description>Select current or voltage output on 'v_temp' pin, for Temperature Sensor Calibration</description>
30326                <bitRange>[6:6]</bitRange>
30327                <access>read-write</access>
30328                <enumeratedValues>
30329                  <enumeratedValue>
30330                    <name>CURRENT</name>
30331                    <description>Current is selected</description>
30332                    <value>0</value>
30333                  </enumeratedValue>
30334                  <enumeratedValue>
30335                    <name>VOLTAGE</name>
30336                    <description>Voltage is selected</description>
30337                    <value>1</value>
30338                  </enumeratedValue>
30339                </enumeratedValues>
30340              </field>
30341              <field>
30342                <name>TS_CAL_CUR_SEL</name>
30343                <description>Select the current going into the BJT, for Temperature Sensor Calibration</description>
30344                <bitRange>[9:8]</bitRange>
30345                <access>read-write</access>
30346                <enumeratedValues>
30347                  <enumeratedValue>
30348                    <name>I_1U</name>
30349                    <description>Select 1 uA</description>
30350                    <value>0</value>
30351                  </enumeratedValue>
30352                  <enumeratedValue>
30353                    <name>I_2U</name>
30354                    <description>Select 2 uA</description>
30355                    <value>1</value>
30356                  </enumeratedValue>
30357                  <enumeratedValue>
30358                    <name>I_5U</name>
30359                    <description>Select 5 uA</description>
30360                    <value>2</value>
30361                  </enumeratedValue>
30362                  <enumeratedValue>
30363                    <name>I_10U</name>
30364                    <description>Select 10 uA</description>
30365                    <value>3</value>
30366                  </enumeratedValue>
30367                </enumeratedValues>
30368              </field>
30369              <field>
30370                <name>TS_CAL_SPARE</name>
30371                <description>Spare</description>
30372                <bitRange>[12:12]</bitRange>
30373                <access>read-write</access>
30374              </field>
30375            </fields>
30376          </register>
30377        </cluster>
30378      </registers>
30379    </peripheral>
30380  </peripherals>
30381</device>