1<?xml version="1.0" encoding="utf-8"?>
2<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
3  <vendor>Cypress Semiconductor</vendor>
4  <vendorID>Cypress</vendorID>
5  <name>psoc6_02</name>
6  <series>PSoC6_02</series>
7  <version>1.0</version>
8  <description>PSoC6_02</description>
9  <licenseText>(c) (2016-2021), Cypress Semiconductor Corporation (an Infineon company)\n
10    or an affiliate of Cypress Semiconductor Corporation.\n
11\n
12    SPDX-License-Identifier: Apache-2.0\n
13\n
14    Licensed under the Apache License, Version 2.0 (the "License");\n
15    you may not use this file except in compliance with the License.\n
16    You may obtain a copy of the License at\n
17\n
18      http://www.apache.org/licenses/LICENSE-2.0\n
19\n
20    Unless required by applicable law or agreed to in writing, software\n
21    distributed under the License is distributed on an "AS IS" BASIS,\n
22    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n
23    See the License for the specific language governing permissions and\n
24    limitations under the License.</licenseText>
25  <cpu>
26    <name>CM4</name>
27    <revision>r0p1</revision>
28    <endian>little</endian>
29    <mpuPresent>true</mpuPresent>
30    <fpuPresent>true</fpuPresent>
31    <vtorPresent>1</vtorPresent>
32    <nvicPrioBits>3</nvicPrioBits>
33    <vendorSystickConfig>0</vendorSystickConfig>
34  </cpu>
35  <addressUnitBits>8</addressUnitBits>
36  <width>32</width>
37  <resetValue>0x00000000</resetValue>
38  <resetMask>0xFFFFFFFF</resetMask>
39  <peripherals>
40    <peripheral>
41      <name>PERI</name>
42      <description>Peripheral interconnect</description>
43      <baseAddress>0x40000000</baseAddress>
44      <addressBlock>
45        <offset>0</offset>
46        <size>65536</size>
47        <usage>registers</usage>
48      </addressBlock>
49      <registers>
50        <register>
51          <name>TIMEOUT_CTL</name>
52          <description>Timeout control</description>
53          <addressOffset>0x200</addressOffset>
54          <size>32</size>
55          <access>read-write</access>
56          <resetValue>0xFFFF</resetValue>
57          <resetMask>0xFFFF</resetMask>
58          <fields>
59            <field>
60              <name>TIMEOUT</name>
61              <description>This field specifies a number of clock cycles (clk_slow). If an AHB-Lite bus transfer takes more than the specified number of cycles (timeout detection), the bus transfer is terminated with an AHB-Lite bus error and a fault is generated (and possibly recorded in the fault report structure(s)).
62'0x0000'-'0xfffe': Number of clock cycles.
63'0xffff': This value is the default/reset value and specifies that no timeout detection is performed: a bus transfer will never be terminated and a fault will never be generated.</description>
64              <bitRange>[15:0]</bitRange>
65              <access>read-write</access>
66            </field>
67          </fields>
68        </register>
69        <register>
70          <name>TR_CMD</name>
71          <description>Trigger command</description>
72          <addressOffset>0x220</addressOffset>
73          <size>32</size>
74          <access>read-write</access>
75          <resetValue>0x0</resetValue>
76          <resetMask>0xE0001FFF</resetMask>
77          <fields>
78            <field>
79              <name>TR_SEL</name>
80              <description>Specifies the activated trigger when ACTIVATE is '1'. If the specified trigger is not present, the trigger activation has no effect.</description>
81              <bitRange>[7:0]</bitRange>
82              <access>read-write</access>
83            </field>
84            <field>
85              <name>GROUP_SEL</name>
86              <description>Specifies the trigger group:
87'0'-'15': trigger multiplexer groups.
88'16'-'31': trigger 1-to-1 groups.</description>
89              <bitRange>[12:8]</bitRange>
90              <access>read-write</access>
91            </field>
92            <field>
93              <name>TR_EDGE</name>
94              <description>Specifies if the activated  trigger is treated as a level sensitive or edge sensitive  trigger.
95'0': level sensitive. The trigger reflects TR_CMD.ACTIVATE.
96'1': edge sensitive trigger. The trigger is activated for two clk_peri cycles.</description>
97              <bitRange>[29:29]</bitRange>
98              <access>read-write</access>
99            </field>
100            <field>
101              <name>OUT_SEL</name>
102              <description>Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger, will result in activation of all output triggers that have the specific input trigger selected through their TR_OUT_CTL.TR_SEL  field. Activation of a specific output trigger, will result in activation of the specified TR_SEL output trigger only.
103'0': TR_SEL selection and trigger activation is for an input trigger to the trigger multiplexer.
104'1': TR_SEL selection and trigger activation is for an output trigger from the trigger multiplexer.
105
106Note: this field is not used for trigger 1-to-1 groups.</description>
107              <bitRange>[30:30]</bitRange>
108              <access>read-write</access>
109            </field>
110            <field>
111              <name>ACTIVATE</name>
112              <description>SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL, TR_EDGE and OUT_SEL. HW sets this field to '0' for edge sensitive triggers AFTER the selected trigger is activated for two clk_peri cycles.
113
114Note: when ACTIVATE is '1', SW should not modify the other register fields.
115SW MUST NOT set ACTIVATE bit to '1' while updating the other register bits simultaneously. At first the SW MUST update the other register bits as needed, and then set ACTIVATE to '1' with a new register write.</description>
116              <bitRange>[31:31]</bitRange>
117              <access>read-write</access>
118            </field>
119          </fields>
120        </register>
121        <register>
122          <name>DIV_CMD</name>
123          <description>Divider command</description>
124          <addressOffset>0x400</addressOffset>
125          <size>32</size>
126          <access>read-write</access>
127          <resetValue>0x3FF03FF</resetValue>
128          <resetMask>0xC3FF03FF</resetMask>
129          <fields>
130            <field>
131              <name>DIV_SEL</name>
132              <description>(TYPE_SEL, DIV_SEL) specifies the divider on which the command (DISABLE/ENABLE) is performed.
133
134If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock signal(s) are generated.</description>
135              <bitRange>[7:0]</bitRange>
136              <access>read-write</access>
137            </field>
138            <field>
139              <name>TYPE_SEL</name>
140              <description>Specifies the divider type of the divider on which the command is performed:
1410: 8.0 (integer) clock dividers.
1421: 16.0 (integer) clock dividers.
1432: 16.5 (fractional) clock dividers.
1443: 24.5 (fractional) clock dividers.</description>
145              <bitRange>[9:8]</bitRange>
146              <access>read-write</access>
147            </field>
148            <field>
149              <name>PA_DIV_SEL</name>
150              <description>(PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other, even when they are enabled at different times.
151
152If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3', 'clk_peri' is used as reference.</description>
153              <bitRange>[23:16]</bitRange>
154              <access>read-write</access>
155            </field>
156            <field>
157              <name>PA_TYPE_SEL</name>
158              <description>Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:
1590: 8.0 (integer) clock dividers.
1601: 16.0 (integer) clock dividers.
1612: 16.5 (fractional) clock dividers.
1623: 24.5 (fractional) clock dividers.</description>
163              <bitRange>[25:24]</bitRange>
164              <access>read-write</access>
165            </field>
166            <field>
167              <name>DISABLE</name>
168              <description>Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'.
169
170The DIV_SEL and TYPE_SEL fields specify which divider is to be disabled.
171
172The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately.</description>
173              <bitRange>[30:30]</bitRange>
174              <access>read-write</access>
175            </field>
176            <field>
177              <name>ENABLE</name>
178              <description>Clock divider enable command (mutually exclusive with DISABLE). Typically, SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled, its integer and fractional (if present) counters are initialized to '0'. If a divider is to be re-enabled using different integer and fractional divider values, the SW should follow these steps:
1790: Disable the divider using the DIV_CMD.DISABLE field.
1801: Configure the divider's DIV_XXX_CTL register.
1812: Enable the divider using the DIV_CMD_ENABLE field.
182
183The DIV_SEL and TYPE_SEL fields specify which divider is to be enabled. The enabled divider may be phase aligned to either 'clk_peri' (typical usage) or to ANY enabled divider.
184
185The PA_DIV_SEL and PA_TYPE_SEL fields specify the reference divider.
186
187The HW sets the ENABLE field to '0' when the enabling is performed and the HW set the DIV_XXX_CTL.EN field of the divider to '1' when the enabling is performed. Note that enabling with phase alignment to a low frequency divider takes time. E.g. To align to a divider that generates a clock of 'clk_peri'/n (with n being the integer divider value INT_DIV+1), up to n cycles may be required to perform alignment. Phase alignment to 'clk_peri' takes affect immediately. SW can set this field to '0' during phase alignment to abort the enabling process.</description>
188              <bitRange>[31:31]</bitRange>
189              <access>read-write</access>
190            </field>
191          </fields>
192        </register>
193        <register>
194          <dim>256</dim>
195          <dimIncrement>4</dimIncrement>
196          <name>CLOCK_CTL[%s]</name>
197          <description>Clock control</description>
198          <addressOffset>0xC00</addressOffset>
199          <size>32</size>
200          <access>read-write</access>
201          <resetValue>0x3FF</resetValue>
202          <resetMask>0x3FF</resetMask>
203          <fields>
204            <field>
205              <name>DIV_SEL</name>
206              <description>Specifies one of the dividers of the divider type specified by TYPE_SEL.
207
208If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset value), no divider is specified and no clock control signal(s) are generated.
209
210When transitioning a clock between two out-of-phase dividers, spurious clock control signals may be generated for one 'clk_peri' cycle during this transition. These clock control signals may cause a single clock period that is smaller than any of the two divider periods. To prevent these spurious clock signals, the clock multiplexer can be disconnected (DIV_SEL is '255' and TYPE_SEL is '3') for a transition time that is larger than the smaller of the two divider periods.</description>
211              <bitRange>[7:0]</bitRange>
212              <access>read-write</access>
213            </field>
214            <field>
215              <name>TYPE_SEL</name>
216              <description>Specifies divider type:
2170: 8.0 (integer) clock dividers.
2181: 16.0 (integer) clock dividers.
2192: 16.5 (fractional) clock dividers.
2203: 24.5 (fractional) clock dividers.</description>
221              <bitRange>[9:8]</bitRange>
222              <access>read-write</access>
223            </field>
224          </fields>
225        </register>
226        <register>
227          <dim>256</dim>
228          <dimIncrement>4</dimIncrement>
229          <name>DIV_8_CTL[%s]</name>
230          <description>Divider control (for 8.0 divider)</description>
231          <addressOffset>0x1000</addressOffset>
232          <size>32</size>
233          <access>read-write</access>
234          <resetValue>0x0</resetValue>
235          <resetMask>0xFF01</resetMask>
236          <fields>
237            <field>
238              <name>EN</name>
239              <description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
240
241Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
242              <bitRange>[0:0]</bitRange>
243              <access>read-only</access>
244            </field>
245            <field>
246              <name>INT8_DIV</name>
247              <description>Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256]. Note: this type of divider does NOT allow for a fractional division.
248
249For the generation of a divided clock, the integer division range is restricted to [2, 256].
250
251For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 256]. The generation of a 50/50  percent duty cycle analog divided clock has no restrictions.
252
253Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
254              <bitRange>[15:8]</bitRange>
255              <access>read-write</access>
256            </field>
257          </fields>
258        </register>
259        <register>
260          <dim>256</dim>
261          <dimIncrement>4</dimIncrement>
262          <name>DIV_16_CTL[%s]</name>
263          <description>Divider control (for 16.0 divider)</description>
264          <addressOffset>0x1400</addressOffset>
265          <size>32</size>
266          <access>read-write</access>
267          <resetValue>0x0</resetValue>
268          <resetMask>0xFFFF01</resetMask>
269          <fields>
270            <field>
271              <name>EN</name>
272              <description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
273
274Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
275              <bitRange>[0:0]</bitRange>
276              <access>read-only</access>
277            </field>
278            <field>
279              <name>INT16_DIV</name>
280              <description>Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: this type of divider does NOT allow for a fractional division.
281
282For the generation of a divided clock, the integer division range is restricted to [2, 65,536].
283
284For the generation of a 50/50 percent duty cycle digital divided clock, the integer division range is restricted to even numbers in the range [2, 65,536]. The generation of a 50/50  percent duty cycle analog divided clock has no restrictions.
285
286Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
287              <bitRange>[23:8]</bitRange>
288              <access>read-write</access>
289            </field>
290          </fields>
291        </register>
292        <register>
293          <dim>256</dim>
294          <dimIncrement>4</dimIncrement>
295          <name>DIV_16_5_CTL[%s]</name>
296          <description>Divider control (for 16.5 divider)</description>
297          <addressOffset>0x1800</addressOffset>
298          <size>32</size>
299          <access>read-write</access>
300          <resetValue>0x0</resetValue>
301          <resetMask>0xFFFFF9</resetMask>
302          <fields>
303            <field>
304              <name>EN</name>
305              <description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
306
307Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
308              <bitRange>[0:0]</bitRange>
309              <access>read-only</access>
310            </field>
311            <field>
312              <name>FRAC5_DIV</name>
313              <description>Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods.
314
315Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
316              <bitRange>[7:3]</bitRange>
317              <access>read-write</access>
318            </field>
319            <field>
320              <name>INT16_DIV</name>
321              <description>Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1, 65,536]. Note: combined with fractional division, this divider type allows for a division in the range [1, 65,536 31/32] in 1/32 increments.
322
323For the generation of a divided clock, the division range is restricted to [2, 65,536 31/32].
324
325For the generation of a 50/50 percent duty cycle divided clock, the  division range is restricted to [2, 65,536].
326
327Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
328              <bitRange>[23:8]</bitRange>
329              <access>read-write</access>
330            </field>
331          </fields>
332        </register>
333        <register>
334          <dim>255</dim>
335          <dimIncrement>4</dimIncrement>
336          <name>DIV_24_5_CTL[%s]</name>
337          <description>Divider control (for 24.5 divider)</description>
338          <addressOffset>0x1C00</addressOffset>
339          <size>32</size>
340          <access>read-write</access>
341          <resetValue>0x0</resetValue>
342          <resetMask>0xFFFFFFF9</resetMask>
343          <fields>
344            <field>
345              <name>EN</name>
346              <description>Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command.
347
348Note that this field is retained. As a result, the divider does NOT have to be re-enabled after transitioning from DeepSleep to Active power mode.</description>
349              <bitRange>[0:0]</bitRange>
350              <access>read-only</access>
351            </field>
352            <field>
353              <name>FRAC5_DIV</name>
354              <description>Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0, 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_peri' cycle longer than other clock periods.
355
356Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
357              <bitRange>[7:3]</bitRange>
358              <access>read-write</access>
359            </field>
360            <field>
361              <name>INT24_DIV</name>
362              <description>Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1, 16,777,216]. Note: combined with fractional division, this divider type allows for a division in the range [1, 16,777,216 31/32] in 1/32 increments.
363
364For the generation of a divided clock, the integer division range is restricted to [2, 16,777,216 31/32].
365
366For the generation of a 50/50 percent duty cycle divided clock, the  division range is restricted to [2, 16,777,216].
367
368Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
369              <bitRange>[31:8]</bitRange>
370              <access>read-write</access>
371            </field>
372          </fields>
373        </register>
374        <register>
375          <name>ECC_CTL</name>
376          <description>ECC control</description>
377          <addressOffset>0x2000</addressOffset>
378          <size>32</size>
379          <access>read-write</access>
380          <resetValue>0x10000</resetValue>
381          <resetMask>0xFF0507FF</resetMask>
382          <fields>
383            <field>
384              <name>WORD_ADDR</name>
385              <description>Specifies the word address where the parity is injected.
386- On a 32-bit write access to this SRAM address and when ECC_INJ_EN bit is '1', the parity (PARITY) is injected.</description>
387              <bitRange>[10:0]</bitRange>
388              <access>read-write</access>
389            </field>
390            <field>
391              <name>ECC_EN</name>
392              <description>Enable ECC checking:
393'0': Disabled.
394'1': Enabled.</description>
395              <bitRange>[16:16]</bitRange>
396              <access>read-write</access>
397            </field>
398            <field>
399              <name>ECC_INJ_EN</name>
400              <description>Enable error injection for PERI protection structure SRAM.
401When '1', the parity (PARITY) is used when a write is done to the WORD_ADDR word address of the SRAM.</description>
402              <bitRange>[18:18]</bitRange>
403              <access>read-write</access>
404            </field>
405            <field>
406              <name>PARITY</name>
407              <description>ECC parity to use for ECC error injection at address WORD_ADDR.</description>
408              <bitRange>[31:24]</bitRange>
409              <access>read-write</access>
410            </field>
411          </fields>
412        </register>
413        <cluster>
414          <dim>11</dim>
415          <dimIncrement>32</dimIncrement>
416          <name>GR[%s]</name>
417          <description>Peripheral group structure</description>
418          <addressOffset>0x00004000</addressOffset>
419          <register>
420            <name>CLOCK_CTL</name>
421            <description>Clock control</description>
422            <addressOffset>0x0</addressOffset>
423            <size>32</size>
424            <access>read-write</access>
425            <resetValue>0x0</resetValue>
426            <resetMask>0xFF00</resetMask>
427            <fields>
428              <field>
429                <name>INT8_DIV</name>
430                <description>Specifies a group clock divider (from the peripheral clock 'clk_peri' to the group clock 'clk_group[3/4/5/...15]'). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256].
431
432Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
433                <bitRange>[15:8]</bitRange>
434                <access>read-write</access>
435              </field>
436            </fields>
437          </register>
438          <register>
439            <name>SL_CTL</name>
440            <description>Slave control</description>
441            <addressOffset>0x10</addressOffset>
442            <size>32</size>
443            <access>read-write</access>
444            <resetValue>0xFFFF</resetValue>
445            <resetMask>0xFFFFFFFF</resetMask>
446            <fields>
447              <field>
448                <name>ENABLED_0</name>
449                <description>Peripheral group, slave 0 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated.
450
451Note: For peripheral group 0 (the peripheral interconnect MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.</description>
452                <bitRange>[0:0]</bitRange>
453                <access>read-write</access>
454              </field>
455              <field>
456                <name>ENABLED_1</name>
457                <description>Peripheral group, slave 1 enable. If the slave is disabled, its clock is gated off (constant '0') and its resets are activated.
458
459Note: For peripheral group 0 (the peripheral interconnect, master interface MMIO registers), this field is a constant '1' (SW: R): the slave can NOT be disabled.</description>
460                <bitRange>[1:1]</bitRange>
461                <access>read-write</access>
462              </field>
463              <field>
464                <name>ENABLED_2</name>
465                <description>N/A</description>
466                <bitRange>[2:2]</bitRange>
467                <access>read-write</access>
468              </field>
469              <field>
470                <name>ENABLED_3</name>
471                <description>N/A</description>
472                <bitRange>[3:3]</bitRange>
473                <access>read-write</access>
474              </field>
475              <field>
476                <name>ENABLED_4</name>
477                <description>N/A</description>
478                <bitRange>[4:4]</bitRange>
479                <access>read-write</access>
480              </field>
481              <field>
482                <name>ENABLED_5</name>
483                <description>N/A</description>
484                <bitRange>[5:5]</bitRange>
485                <access>read-write</access>
486              </field>
487              <field>
488                <name>ENABLED_6</name>
489                <description>N/A</description>
490                <bitRange>[6:6]</bitRange>
491                <access>read-write</access>
492              </field>
493              <field>
494                <name>ENABLED_7</name>
495                <description>N/A</description>
496                <bitRange>[7:7]</bitRange>
497                <access>read-write</access>
498              </field>
499              <field>
500                <name>ENABLED_8</name>
501                <description>N/A</description>
502                <bitRange>[8:8]</bitRange>
503                <access>read-write</access>
504              </field>
505              <field>
506                <name>ENABLED_9</name>
507                <description>N/A</description>
508                <bitRange>[9:9]</bitRange>
509                <access>read-write</access>
510              </field>
511              <field>
512                <name>ENABLED_10</name>
513                <description>N/A</description>
514                <bitRange>[10:10]</bitRange>
515                <access>read-write</access>
516              </field>
517              <field>
518                <name>ENABLED_11</name>
519                <description>N/A</description>
520                <bitRange>[11:11]</bitRange>
521                <access>read-write</access>
522              </field>
523              <field>
524                <name>ENABLED_12</name>
525                <description>N/A</description>
526                <bitRange>[12:12]</bitRange>
527                <access>read-write</access>
528              </field>
529              <field>
530                <name>ENABLED_13</name>
531                <description>N/A</description>
532                <bitRange>[13:13]</bitRange>
533                <access>read-write</access>
534              </field>
535              <field>
536                <name>ENABLED_14</name>
537                <description>N/A</description>
538                <bitRange>[14:14]</bitRange>
539                <access>read-write</access>
540              </field>
541              <field>
542                <name>ENABLED_15</name>
543                <description>N/A</description>
544                <bitRange>[15:15]</bitRange>
545                <access>read-write</access>
546              </field>
547              <field>
548                <name>DISABLED_0</name>
549                <description>Peripheral group, slave 0 permanent disable. Setting this bit to 1 has the same effect as setting ENABLED_0 to 0.  However, once set to 1, this bit cannot be changed back to 0 anymore.</description>
550                <bitRange>[16:16]</bitRange>
551                <access>read-write</access>
552              </field>
553              <field>
554                <name>DISABLED_1</name>
555                <description>N/A</description>
556                <bitRange>[17:17]</bitRange>
557                <access>read-write</access>
558              </field>
559              <field>
560                <name>DISABLED_2</name>
561                <description>N/A</description>
562                <bitRange>[18:18]</bitRange>
563                <access>read-write</access>
564              </field>
565              <field>
566                <name>DISABLED_3</name>
567                <description>N/A</description>
568                <bitRange>[19:19]</bitRange>
569                <access>read-write</access>
570              </field>
571              <field>
572                <name>DISABLED_4</name>
573                <description>N/A</description>
574                <bitRange>[20:20]</bitRange>
575                <access>read-write</access>
576              </field>
577              <field>
578                <name>DISABLED_5</name>
579                <description>N/A</description>
580                <bitRange>[21:21]</bitRange>
581                <access>read-write</access>
582              </field>
583              <field>
584                <name>DISABLED_6</name>
585                <description>N/A</description>
586                <bitRange>[22:22]</bitRange>
587                <access>read-write</access>
588              </field>
589              <field>
590                <name>DISABLED_7</name>
591                <description>N/A</description>
592                <bitRange>[23:23]</bitRange>
593                <access>read-write</access>
594              </field>
595              <field>
596                <name>DISABLED_8</name>
597                <description>N/A</description>
598                <bitRange>[24:24]</bitRange>
599                <access>read-write</access>
600              </field>
601              <field>
602                <name>DISABLED_9</name>
603                <description>N/A</description>
604                <bitRange>[25:25]</bitRange>
605                <access>read-write</access>
606              </field>
607              <field>
608                <name>DISABLED_10</name>
609                <description>N/A</description>
610                <bitRange>[26:26]</bitRange>
611                <access>read-write</access>
612              </field>
613              <field>
614                <name>DISABLED_11</name>
615                <description>N/A</description>
616                <bitRange>[27:27]</bitRange>
617                <access>read-write</access>
618              </field>
619              <field>
620                <name>DISABLED_12</name>
621                <description>N/A</description>
622                <bitRange>[28:28]</bitRange>
623                <access>read-write</access>
624              </field>
625              <field>
626                <name>DISABLED_13</name>
627                <description>N/A</description>
628                <bitRange>[29:29]</bitRange>
629                <access>read-write</access>
630              </field>
631              <field>
632                <name>DISABLED_14</name>
633                <description>N/A</description>
634                <bitRange>[30:30]</bitRange>
635                <access>read-write</access>
636              </field>
637              <field>
638                <name>DISABLED_15</name>
639                <description>N/A</description>
640                <bitRange>[31:31]</bitRange>
641                <access>read-write</access>
642              </field>
643            </fields>
644          </register>
645        </cluster>
646        <cluster>
647          <dim>10</dim>
648          <dimIncrement>1024</dimIncrement>
649          <name>TR_GR[%s]</name>
650          <description>Trigger group</description>
651          <addressOffset>0x00008000</addressOffset>
652          <register>
653            <dim>256</dim>
654            <dimIncrement>4</dimIncrement>
655            <name>TR_CTL[%s]</name>
656            <description>Trigger control register</description>
657            <addressOffset>0x0</addressOffset>
658            <size>32</size>
659            <access>read-write</access>
660            <resetValue>0x0</resetValue>
661            <resetMask>0x13FF</resetMask>
662            <fields>
663              <field>
664                <name>TR_SEL</name>
665                <description>Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default value) is typically connected to a constant signal level of '0', and as a result will not cause HW activation of the output trigger.</description>
666                <bitRange>[7:0]</bitRange>
667                <access>read-write</access>
668              </field>
669              <field>
670                <name>TR_INV</name>
671                <description>Specifies if the output trigger is inverted.</description>
672                <bitRange>[8:8]</bitRange>
673                <access>read-write</access>
674              </field>
675              <field>
676                <name>TR_EDGE</name>
677                <description>Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive  trigger.
678'0': level sensitive.
679'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.</description>
680                <bitRange>[9:9]</bitRange>
681                <access>read-write</access>
682              </field>
683              <field>
684                <name>DBG_FREEZE_EN</name>
685                <description>Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation.</description>
686                <bitRange>[12:12]</bitRange>
687                <access>read-write</access>
688              </field>
689            </fields>
690          </register>
691        </cluster>
692        <cluster>
693          <dim>7</dim>
694          <dimIncrement>1024</dimIncrement>
695          <name>TR_1TO1_GR[%s]</name>
696          <description>Trigger 1-to-1 group</description>
697          <addressOffset>0x0000C000</addressOffset>
698          <register>
699            <dim>256</dim>
700            <dimIncrement>4</dimIncrement>
701            <name>TR_CTL[%s]</name>
702            <description>Trigger control register</description>
703            <addressOffset>0x0</addressOffset>
704            <size>32</size>
705            <access>read-write</access>
706            <resetValue>0x0</resetValue>
707            <resetMask>0x1301</resetMask>
708            <fields>
709              <field>
710                <name>TR_SEL</name>
711                <description>Specifies input trigger:
712'0'': constant signal level '0'.
713'1': input trigger.</description>
714                <bitRange>[0:0]</bitRange>
715                <access>read-write</access>
716              </field>
717              <field>
718                <name>TR_INV</name>
719                <description>Specifies if the output trigger is inverted.</description>
720                <bitRange>[8:8]</bitRange>
721                <access>read-write</access>
722              </field>
723              <field>
724                <name>TR_EDGE</name>
725                <description>Specifies if the (inverted) output trigger is treated as a level sensitive or edge sensitive  trigger.
726'0': level sensitive.
727'1': edge sensitive trigger. The (inverted) output trigger duration needs to be at least 2 cycles on the consumer clock. the(inverted) output trigger is synchronized to the consumer clock and a two cycle pulse is generated on the consumer clock.</description>
728                <bitRange>[9:9]</bitRange>
729                <access>read-write</access>
730              </field>
731              <field>
732                <name>DBG_FREEZE_EN</name>
733                <description>Specifies if the output trigger is blocked in debug mode. When set high tr_dbg_freeze will block the output trigger generation.</description>
734                <bitRange>[12:12]</bitRange>
735                <access>read-write</access>
736              </field>
737            </fields>
738          </register>
739        </cluster>
740      </registers>
741    </peripheral>
742    <peripheral>
743      <name>PERI_MS</name>
744      <description>Peripheral interconnect, master interface</description>
745      <baseAddress>0x40010000</baseAddress>
746      <addressBlock>
747        <offset>0</offset>
748        <size>65536</size>
749        <usage>registers</usage>
750      </addressBlock>
751      <registers>
752        <cluster>
753          <dim>8</dim>
754          <dimIncrement>64</dimIncrement>
755          <name>PPU_PR[%s]</name>
756          <description>Programmable protection structure pair</description>
757          <addressOffset>0x00000000</addressOffset>
758          <register>
759            <name>SL_ADDR</name>
760            <description>Slave region, base address</description>
761            <addressOffset>0x0</addressOffset>
762            <size>32</size>
763            <access>read-write</access>
764            <resetValue>0x0</resetValue>
765            <resetMask>0x0</resetMask>
766            <fields>
767              <field>
768                <name>ADDR30</name>
769                <description>This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's.</description>
770                <bitRange>[31:2]</bitRange>
771                <access>read-write</access>
772              </field>
773            </fields>
774          </register>
775          <register>
776            <name>SL_SIZE</name>
777            <description>Slave region, size</description>
778            <addressOffset>0x4</addressOffset>
779            <size>32</size>
780            <access>read-write</access>
781            <resetValue>0x0</resetValue>
782            <resetMask>0x80000000</resetMask>
783            <fields>
784              <field>
785                <name>REGION_SIZE</name>
786                <description>This field specifies the size of the slave region:
787'0': Undefined.
788'1': 4 B region (this is the smallest region size).
789'2': 8 B region
790'3': 16 B region
791'4': 32 B region
792'5': 64 B region
793'6': 128 B region
794'7': 256 B region
795'8': 512 B region
796'9': 1 KB region
797'10': 2 KB region
798'11': 4 KB region
799'12': 8 KB region
800'13': 16 KB region
801'14': 32 KB region
802'15': 64 KB region
803'16': 128 KB region
804'17': 256 KB region
805'18': 512 KB region
806'19': 1 MB region
807'20': 2 MB region
808'21': 4 MB region
809'22': 8 MB region
810'23': 16 MB region
811'24': 32 MB region
812'25': 64 MB region
813'26': 128 MB region
814'27': 256 MB region
815'28': 512 MB region
816'29': 1 GB region
817'30': 2 GB region
818'31': 4 GB region</description>
819                <bitRange>[28:24]</bitRange>
820                <access>read-write</access>
821              </field>
822              <field>
823                <name>VALID</name>
824                <description>Slave region enable:
825'0': Disabled. A disabled region will never result in a match on the transfer address.
826'1': Enabled.</description>
827                <bitRange>[31:31]</bitRange>
828                <access>read-write</access>
829              </field>
830            </fields>
831          </register>
832          <register>
833            <name>SL_ATT0</name>
834            <description>Slave attributes 0</description>
835            <addressOffset>0x10</addressOffset>
836            <size>32</size>
837            <access>read-write</access>
838            <resetValue>0x1F1F1F1F</resetValue>
839            <resetMask>0x1F1F1F1F</resetMask>
840            <fields>
841              <field>
842                <name>PC0_UR</name>
843                <description>Protection context 0, user read enable:
844'0': Disabled (user, read accesses are NOT allowed).
845'1': Enabled (user, read accesses are allowed).</description>
846                <bitRange>[0:0]</bitRange>
847                <access>read-only</access>
848              </field>
849              <field>
850                <name>PC0_UW</name>
851                <description>Protection context 0, user write enable:
852'0': Disabled (user, write accesses are NOT allowed).
853'1': Enabled (user, write accesses are allowed).</description>
854                <bitRange>[1:1]</bitRange>
855                <access>read-only</access>
856              </field>
857              <field>
858                <name>PC0_PR</name>
859                <description>Protection context 0, privileged read enable:
860'0': Disabled (privileged, read accesses are NOT allowed).
861'1': Enabled (privileged, read accesses are allowed).</description>
862                <bitRange>[2:2]</bitRange>
863                <access>read-only</access>
864              </field>
865              <field>
866                <name>PC0_PW</name>
867                <description>Protection context 0, privileged write enable:
868'0': Disabled (privileged, write accesses are NOT allowed).
869'1': Enabled (privileged, write accesses are allowed).</description>
870                <bitRange>[3:3]</bitRange>
871                <access>read-only</access>
872              </field>
873              <field>
874                <name>PC0_NS</name>
875                <description>Protection context 0, non-secure:
876'0': Secure (secure accesses allowed, non-secure access NOT allowed).
877'1': Non-secure (both secure and non-secure accesses allowed).</description>
878                <bitRange>[4:4]</bitRange>
879                <access>read-only</access>
880              </field>
881              <field>
882                <name>PC1_UR</name>
883                <description>Protection context 1, user read enable.</description>
884                <bitRange>[8:8]</bitRange>
885                <access>read-write</access>
886              </field>
887              <field>
888                <name>PC1_UW</name>
889                <description>Protection context 1, user write enable.</description>
890                <bitRange>[9:9]</bitRange>
891                <access>read-write</access>
892              </field>
893              <field>
894                <name>PC1_PR</name>
895                <description>Protection context 1, privileged read enable.</description>
896                <bitRange>[10:10]</bitRange>
897                <access>read-write</access>
898              </field>
899              <field>
900                <name>PC1_PW</name>
901                <description>Protection context 1, privileged write enable.</description>
902                <bitRange>[11:11]</bitRange>
903                <access>read-write</access>
904              </field>
905              <field>
906                <name>PC1_NS</name>
907                <description>Protection context 1, non-secure.</description>
908                <bitRange>[12:12]</bitRange>
909                <access>read-write</access>
910              </field>
911              <field>
912                <name>PC2_UR</name>
913                <description>Protection context 2, user read enable.</description>
914                <bitRange>[16:16]</bitRange>
915                <access>read-write</access>
916              </field>
917              <field>
918                <name>PC2_UW</name>
919                <description>Protection context 2, user write enable.</description>
920                <bitRange>[17:17]</bitRange>
921                <access>read-write</access>
922              </field>
923              <field>
924                <name>PC2_PR</name>
925                <description>Protection context 2, privileged read enable.</description>
926                <bitRange>[18:18]</bitRange>
927                <access>read-write</access>
928              </field>
929              <field>
930                <name>PC2_PW</name>
931                <description>Protection context 2, privileged write enable.</description>
932                <bitRange>[19:19]</bitRange>
933                <access>read-write</access>
934              </field>
935              <field>
936                <name>PC2_NS</name>
937                <description>Protection context 2, non-secure.</description>
938                <bitRange>[20:20]</bitRange>
939                <access>read-write</access>
940              </field>
941              <field>
942                <name>PC3_UR</name>
943                <description>Protection context 3, user read enable.</description>
944                <bitRange>[24:24]</bitRange>
945                <access>read-write</access>
946              </field>
947              <field>
948                <name>PC3_UW</name>
949                <description>Protection context 3, user write enable.</description>
950                <bitRange>[25:25]</bitRange>
951                <access>read-write</access>
952              </field>
953              <field>
954                <name>PC3_PR</name>
955                <description>Protection context 3, privileged read enable.</description>
956                <bitRange>[26:26]</bitRange>
957                <access>read-write</access>
958              </field>
959              <field>
960                <name>PC3_PW</name>
961                <description>Protection context 3, privileged write enable.</description>
962                <bitRange>[27:27]</bitRange>
963                <access>read-write</access>
964              </field>
965              <field>
966                <name>PC3_NS</name>
967                <description>Protection context 3, non-secure.</description>
968                <bitRange>[28:28]</bitRange>
969                <access>read-write</access>
970              </field>
971            </fields>
972          </register>
973          <register>
974            <name>SL_ATT1</name>
975            <description>Slave attributes 1</description>
976            <addressOffset>0x14</addressOffset>
977            <size>32</size>
978            <access>read-write</access>
979            <resetValue>0x1F1F1F1F</resetValue>
980            <resetMask>0x1F1F1F1F</resetMask>
981            <fields>
982              <field>
983                <name>PC4_UR</name>
984                <description>Protection context 4, user read enable.</description>
985                <bitRange>[0:0]</bitRange>
986                <access>read-write</access>
987              </field>
988              <field>
989                <name>PC4_UW</name>
990                <description>Protection context 4, user write enable.</description>
991                <bitRange>[1:1]</bitRange>
992                <access>read-write</access>
993              </field>
994              <field>
995                <name>PC4_PR</name>
996                <description>Protection context 4, privileged read enable.</description>
997                <bitRange>[2:2]</bitRange>
998                <access>read-write</access>
999              </field>
1000              <field>
1001                <name>PC4_PW</name>
1002                <description>Protection context 4, privileged write enable.</description>
1003                <bitRange>[3:3]</bitRange>
1004                <access>read-write</access>
1005              </field>
1006              <field>
1007                <name>PC4_NS</name>
1008                <description>Protection context 4, non-secure.</description>
1009                <bitRange>[4:4]</bitRange>
1010                <access>read-write</access>
1011              </field>
1012              <field>
1013                <name>PC5_UR</name>
1014                <description>Protection context 5, user read enable.</description>
1015                <bitRange>[8:8]</bitRange>
1016                <access>read-write</access>
1017              </field>
1018              <field>
1019                <name>PC5_UW</name>
1020                <description>Protection context 5, user write enable.</description>
1021                <bitRange>[9:9]</bitRange>
1022                <access>read-write</access>
1023              </field>
1024              <field>
1025                <name>PC5_PR</name>
1026                <description>Protection context 5, privileged read enable.</description>
1027                <bitRange>[10:10]</bitRange>
1028                <access>read-write</access>
1029              </field>
1030              <field>
1031                <name>PC5_PW</name>
1032                <description>Protection context 5, privileged write enable.</description>
1033                <bitRange>[11:11]</bitRange>
1034                <access>read-write</access>
1035              </field>
1036              <field>
1037                <name>PC5_NS</name>
1038                <description>Protection context 5, non-secure.</description>
1039                <bitRange>[12:12]</bitRange>
1040                <access>read-write</access>
1041              </field>
1042              <field>
1043                <name>PC6_UR</name>
1044                <description>Protection context 6, user read enable.</description>
1045                <bitRange>[16:16]</bitRange>
1046                <access>read-write</access>
1047              </field>
1048              <field>
1049                <name>PC6_UW</name>
1050                <description>Protection context 6, user write enable.</description>
1051                <bitRange>[17:17]</bitRange>
1052                <access>read-write</access>
1053              </field>
1054              <field>
1055                <name>PC6_PR</name>
1056                <description>Protection context 6, privileged read enable.</description>
1057                <bitRange>[18:18]</bitRange>
1058                <access>read-write</access>
1059              </field>
1060              <field>
1061                <name>PC6_PW</name>
1062                <description>Protection context 6, privileged write enable.</description>
1063                <bitRange>[19:19]</bitRange>
1064                <access>read-write</access>
1065              </field>
1066              <field>
1067                <name>PC6_NS</name>
1068                <description>Protection context 6, non-secure.</description>
1069                <bitRange>[20:20]</bitRange>
1070                <access>read-write</access>
1071              </field>
1072              <field>
1073                <name>PC7_UR</name>
1074                <description>Protection context 7, user read enable.</description>
1075                <bitRange>[24:24]</bitRange>
1076                <access>read-write</access>
1077              </field>
1078              <field>
1079                <name>PC7_UW</name>
1080                <description>Protection context 7, user write enable.</description>
1081                <bitRange>[25:25]</bitRange>
1082                <access>read-write</access>
1083              </field>
1084              <field>
1085                <name>PC7_PR</name>
1086                <description>Protection context 7, privileged read enable.</description>
1087                <bitRange>[26:26]</bitRange>
1088                <access>read-write</access>
1089              </field>
1090              <field>
1091                <name>PC7_PW</name>
1092                <description>Protection context 7, privileged write enable.</description>
1093                <bitRange>[27:27]</bitRange>
1094                <access>read-write</access>
1095              </field>
1096              <field>
1097                <name>PC7_NS</name>
1098                <description>Protection context 7, non-secure.</description>
1099                <bitRange>[28:28]</bitRange>
1100                <access>read-write</access>
1101              </field>
1102            </fields>
1103          </register>
1104          <register>
1105            <name>SL_ATT2</name>
1106            <description>Slave attributes 2</description>
1107            <addressOffset>0x18</addressOffset>
1108            <size>32</size>
1109            <access>read-write</access>
1110            <resetValue>0x1F1F1F1F</resetValue>
1111            <resetMask>0x1F1F1F1F</resetMask>
1112            <fields>
1113              <field>
1114                <name>PC8_UR</name>
1115                <description>Protection context 8, user read enable.</description>
1116                <bitRange>[0:0]</bitRange>
1117                <access>read-write</access>
1118              </field>
1119              <field>
1120                <name>PC8_UW</name>
1121                <description>Protection context 8, user write enable.</description>
1122                <bitRange>[1:1]</bitRange>
1123                <access>read-write</access>
1124              </field>
1125              <field>
1126                <name>PC8_PR</name>
1127                <description>Protection context 8, privileged read enable.</description>
1128                <bitRange>[2:2]</bitRange>
1129                <access>read-write</access>
1130              </field>
1131              <field>
1132                <name>PC8_PW</name>
1133                <description>Protection context 8, privileged write enable.</description>
1134                <bitRange>[3:3]</bitRange>
1135                <access>read-write</access>
1136              </field>
1137              <field>
1138                <name>PC8_NS</name>
1139                <description>Protection context 8, non-secure.</description>
1140                <bitRange>[4:4]</bitRange>
1141                <access>read-write</access>
1142              </field>
1143              <field>
1144                <name>PC9_UR</name>
1145                <description>Protection context 9, user read enable.</description>
1146                <bitRange>[8:8]</bitRange>
1147                <access>read-write</access>
1148              </field>
1149              <field>
1150                <name>PC9_UW</name>
1151                <description>Protection context 9, user write enable.</description>
1152                <bitRange>[9:9]</bitRange>
1153                <access>read-write</access>
1154              </field>
1155              <field>
1156                <name>PC9_PR</name>
1157                <description>Protection context 9, privileged read enable.</description>
1158                <bitRange>[10:10]</bitRange>
1159                <access>read-write</access>
1160              </field>
1161              <field>
1162                <name>PC9_PW</name>
1163                <description>Protection context 9, privileged write enable.</description>
1164                <bitRange>[11:11]</bitRange>
1165                <access>read-write</access>
1166              </field>
1167              <field>
1168                <name>PC9_NS</name>
1169                <description>Protection context 9, non-secure.</description>
1170                <bitRange>[12:12]</bitRange>
1171                <access>read-write</access>
1172              </field>
1173              <field>
1174                <name>PC10_UR</name>
1175                <description>Protection context 10, user read enable.</description>
1176                <bitRange>[16:16]</bitRange>
1177                <access>read-write</access>
1178              </field>
1179              <field>
1180                <name>PC10_UW</name>
1181                <description>Protection context 10, user write enable.</description>
1182                <bitRange>[17:17]</bitRange>
1183                <access>read-write</access>
1184              </field>
1185              <field>
1186                <name>PC10_PR</name>
1187                <description>Protection context 10, privileged read enable.</description>
1188                <bitRange>[18:18]</bitRange>
1189                <access>read-write</access>
1190              </field>
1191              <field>
1192                <name>PC10_PW</name>
1193                <description>Protection context 10, privileged write enable.</description>
1194                <bitRange>[19:19]</bitRange>
1195                <access>read-write</access>
1196              </field>
1197              <field>
1198                <name>PC10_NS</name>
1199                <description>Protection context 10, non-secure.</description>
1200                <bitRange>[20:20]</bitRange>
1201                <access>read-write</access>
1202              </field>
1203              <field>
1204                <name>PC11_UR</name>
1205                <description>Protection context 11, user read enable.</description>
1206                <bitRange>[24:24]</bitRange>
1207                <access>read-write</access>
1208              </field>
1209              <field>
1210                <name>PC11_UW</name>
1211                <description>Protection context 11, user write enable.</description>
1212                <bitRange>[25:25]</bitRange>
1213                <access>read-write</access>
1214              </field>
1215              <field>
1216                <name>PC11_PR</name>
1217                <description>Protection context 11, privileged read enable.</description>
1218                <bitRange>[26:26]</bitRange>
1219                <access>read-write</access>
1220              </field>
1221              <field>
1222                <name>PC11_PW</name>
1223                <description>Protection context 11, privileged write enable.</description>
1224                <bitRange>[27:27]</bitRange>
1225                <access>read-write</access>
1226              </field>
1227              <field>
1228                <name>PC11_NS</name>
1229                <description>Protection context 11, non-secure.</description>
1230                <bitRange>[28:28]</bitRange>
1231                <access>read-write</access>
1232              </field>
1233            </fields>
1234          </register>
1235          <register>
1236            <name>SL_ATT3</name>
1237            <description>Slave attributes 3</description>
1238            <addressOffset>0x1C</addressOffset>
1239            <size>32</size>
1240            <access>read-write</access>
1241            <resetValue>0x1F1F1F1F</resetValue>
1242            <resetMask>0x1F1F1F1F</resetMask>
1243            <fields>
1244              <field>
1245                <name>PC12_UR</name>
1246                <description>Protection context 12, user read enable.</description>
1247                <bitRange>[0:0]</bitRange>
1248                <access>read-write</access>
1249              </field>
1250              <field>
1251                <name>PC12_UW</name>
1252                <description>Protection context 12, user write enable.</description>
1253                <bitRange>[1:1]</bitRange>
1254                <access>read-write</access>
1255              </field>
1256              <field>
1257                <name>PC12_PR</name>
1258                <description>Protection context 12, privileged read enable.</description>
1259                <bitRange>[2:2]</bitRange>
1260                <access>read-write</access>
1261              </field>
1262              <field>
1263                <name>PC12_PW</name>
1264                <description>Protection context 12, privileged write enable.</description>
1265                <bitRange>[3:3]</bitRange>
1266                <access>read-write</access>
1267              </field>
1268              <field>
1269                <name>PC12_NS</name>
1270                <description>Protection context 12, non-secure.</description>
1271                <bitRange>[4:4]</bitRange>
1272                <access>read-write</access>
1273              </field>
1274              <field>
1275                <name>PC13_UR</name>
1276                <description>Protection context 13, user read enable.</description>
1277                <bitRange>[8:8]</bitRange>
1278                <access>read-write</access>
1279              </field>
1280              <field>
1281                <name>PC13_UW</name>
1282                <description>Protection context 13, user write enable.</description>
1283                <bitRange>[9:9]</bitRange>
1284                <access>read-write</access>
1285              </field>
1286              <field>
1287                <name>PC13_PR</name>
1288                <description>Protection context 13, privileged read enable.</description>
1289                <bitRange>[10:10]</bitRange>
1290                <access>read-write</access>
1291              </field>
1292              <field>
1293                <name>PC13_PW</name>
1294                <description>Protection context 13, privileged write enable.</description>
1295                <bitRange>[11:11]</bitRange>
1296                <access>read-write</access>
1297              </field>
1298              <field>
1299                <name>PC13_NS</name>
1300                <description>Protection context 13, non-secure.</description>
1301                <bitRange>[12:12]</bitRange>
1302                <access>read-write</access>
1303              </field>
1304              <field>
1305                <name>PC14_UR</name>
1306                <description>Protection context 14, user read enable.</description>
1307                <bitRange>[16:16]</bitRange>
1308                <access>read-write</access>
1309              </field>
1310              <field>
1311                <name>PC14_UW</name>
1312                <description>Protection context 14, user write enable.</description>
1313                <bitRange>[17:17]</bitRange>
1314                <access>read-write</access>
1315              </field>
1316              <field>
1317                <name>PC14_PR</name>
1318                <description>Protection context 14, privileged read enable.</description>
1319                <bitRange>[18:18]</bitRange>
1320                <access>read-write</access>
1321              </field>
1322              <field>
1323                <name>PC14_PW</name>
1324                <description>Protection context 14, privileged write enable.</description>
1325                <bitRange>[19:19]</bitRange>
1326                <access>read-write</access>
1327              </field>
1328              <field>
1329                <name>PC14_NS</name>
1330                <description>Protection context 14, non-secure.</description>
1331                <bitRange>[20:20]</bitRange>
1332                <access>read-write</access>
1333              </field>
1334              <field>
1335                <name>PC15_UR</name>
1336                <description>Protection context 15, user read enable.</description>
1337                <bitRange>[24:24]</bitRange>
1338                <access>read-write</access>
1339              </field>
1340              <field>
1341                <name>PC15_UW</name>
1342                <description>Protection context 15, user write enable.</description>
1343                <bitRange>[25:25]</bitRange>
1344                <access>read-write</access>
1345              </field>
1346              <field>
1347                <name>PC15_PR</name>
1348                <description>Protection context 15, privileged read enable.</description>
1349                <bitRange>[26:26]</bitRange>
1350                <access>read-write</access>
1351              </field>
1352              <field>
1353                <name>PC15_PW</name>
1354                <description>Protection context 15, privileged write enable.</description>
1355                <bitRange>[27:27]</bitRange>
1356                <access>read-write</access>
1357              </field>
1358              <field>
1359                <name>PC15_NS</name>
1360                <description>Protection context 15, non-secure.</description>
1361                <bitRange>[28:28]</bitRange>
1362                <access>read-write</access>
1363              </field>
1364            </fields>
1365          </register>
1366          <register>
1367            <name>MS_ADDR</name>
1368            <description>Master region, base address</description>
1369            <addressOffset>0x20</addressOffset>
1370            <size>32</size>
1371            <access>read-only</access>
1372            <resetValue>0x0</resetValue>
1373            <resetMask>0xFFFFFFC0</resetMask>
1374            <fields>
1375              <field>
1376                <name>ADDR26</name>
1377                <description>This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register.</description>
1378                <bitRange>[31:6]</bitRange>
1379                <access>read-only</access>
1380              </field>
1381            </fields>
1382          </register>
1383          <register>
1384            <name>MS_SIZE</name>
1385            <description>Master region, size</description>
1386            <addressOffset>0x24</addressOffset>
1387            <size>32</size>
1388            <access>read-only</access>
1389            <resetValue>0x85000000</resetValue>
1390            <resetMask>0x9F000000</resetMask>
1391            <fields>
1392              <field>
1393                <name>REGION_SIZE</name>
1394                <description>This field specifies the size of the master region:
1395'5': 64 B region
1396
1397The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3.</description>
1398                <bitRange>[28:24]</bitRange>
1399                <access>read-only</access>
1400              </field>
1401              <field>
1402                <name>VALID</name>
1403                <description>Master region enable:
1404'1': Enabled.</description>
1405                <bitRange>[31:31]</bitRange>
1406                <access>read-only</access>
1407              </field>
1408            </fields>
1409          </register>
1410          <register>
1411            <name>MS_ATT0</name>
1412            <description>Master attributes 0</description>
1413            <addressOffset>0x30</addressOffset>
1414            <size>32</size>
1415            <access>read-write</access>
1416            <resetValue>0x1F1F1F1F</resetValue>
1417            <resetMask>0x1F1F1F1F</resetMask>
1418            <fields>
1419              <field>
1420                <name>PC0_UR</name>
1421                <description>Protection context 0, user read enable:
1422'0': Disabled (user, read accesses are NOT allowed).
1423'1': Enabled (user, read accesses are allowed).</description>
1424                <bitRange>[0:0]</bitRange>
1425                <access>read-only</access>
1426              </field>
1427              <field>
1428                <name>PC0_UW</name>
1429                <description>Protection context 0, user write enable:
1430'0': Disabled (user, write accesses are NOT allowed).
1431'1': Enabled (user, write accesses are allowed).</description>
1432                <bitRange>[1:1]</bitRange>
1433                <access>read-only</access>
1434              </field>
1435              <field>
1436                <name>PC0_PR</name>
1437                <description>Protection context 0, privileged read enable:
1438'0': Disabled (privileged, read accesses are NOT allowed).
1439'1': Enabled (privileged, read accesses are allowed).</description>
1440                <bitRange>[2:2]</bitRange>
1441                <access>read-only</access>
1442              </field>
1443              <field>
1444                <name>PC0_PW</name>
1445                <description>Protection context 0, privileged write enable:
1446'0': Disabled (privileged, write accesses are NOT allowed).
1447'1': Enabled (privileged, write accesses are allowed).</description>
1448                <bitRange>[3:3]</bitRange>
1449                <access>read-only</access>
1450              </field>
1451              <field>
1452                <name>PC0_NS</name>
1453                <description>Protection context 0, non-secure:
1454'0': Secure (secure accesses allowed, non-secure access NOT allowed).
1455'1': Non-secure (both secure and non-secure accesses allowed).</description>
1456                <bitRange>[4:4]</bitRange>
1457                <access>read-only</access>
1458              </field>
1459              <field>
1460                <name>PC1_UR</name>
1461                <description>Protection context 1, user read enable.</description>
1462                <bitRange>[8:8]</bitRange>
1463                <access>read-only</access>
1464              </field>
1465              <field>
1466                <name>PC1_UW</name>
1467                <description>Protection context 1, user write enable.</description>
1468                <bitRange>[9:9]</bitRange>
1469                <access>read-write</access>
1470              </field>
1471              <field>
1472                <name>PC1_PR</name>
1473                <description>Protection context 1, privileged read enable.</description>
1474                <bitRange>[10:10]</bitRange>
1475                <access>read-only</access>
1476              </field>
1477              <field>
1478                <name>PC1_PW</name>
1479                <description>Protection context 1, privileged write enable.</description>
1480                <bitRange>[11:11]</bitRange>
1481                <access>read-write</access>
1482              </field>
1483              <field>
1484                <name>PC1_NS</name>
1485                <description>Protection context 1, non-secure.</description>
1486                <bitRange>[12:12]</bitRange>
1487                <access>read-write</access>
1488              </field>
1489              <field>
1490                <name>PC2_UR</name>
1491                <description>Protection context 2, user read enable.</description>
1492                <bitRange>[16:16]</bitRange>
1493                <access>read-only</access>
1494              </field>
1495              <field>
1496                <name>PC2_UW</name>
1497                <description>Protection context 2, user write enable.</description>
1498                <bitRange>[17:17]</bitRange>
1499                <access>read-write</access>
1500              </field>
1501              <field>
1502                <name>PC2_PR</name>
1503                <description>Protection context 2, privileged read enable.</description>
1504                <bitRange>[18:18]</bitRange>
1505                <access>read-only</access>
1506              </field>
1507              <field>
1508                <name>PC2_PW</name>
1509                <description>Protection context 2, privileged write enable.</description>
1510                <bitRange>[19:19]</bitRange>
1511                <access>read-write</access>
1512              </field>
1513              <field>
1514                <name>PC2_NS</name>
1515                <description>Protection context 2, non-secure.</description>
1516                <bitRange>[20:20]</bitRange>
1517                <access>read-write</access>
1518              </field>
1519              <field>
1520                <name>PC3_UR</name>
1521                <description>Protection context 3, user read enable.</description>
1522                <bitRange>[24:24]</bitRange>
1523                <access>read-only</access>
1524              </field>
1525              <field>
1526                <name>PC3_UW</name>
1527                <description>Protection context 3, user write enable.</description>
1528                <bitRange>[25:25]</bitRange>
1529                <access>read-write</access>
1530              </field>
1531              <field>
1532                <name>PC3_PR</name>
1533                <description>Protection context 3, privileged read enable.</description>
1534                <bitRange>[26:26]</bitRange>
1535                <access>read-only</access>
1536              </field>
1537              <field>
1538                <name>PC3_PW</name>
1539                <description>Protection context 3, privileged write enable.</description>
1540                <bitRange>[27:27]</bitRange>
1541                <access>read-write</access>
1542              </field>
1543              <field>
1544                <name>PC3_NS</name>
1545                <description>Protection context 3, non-secure.</description>
1546                <bitRange>[28:28]</bitRange>
1547                <access>read-write</access>
1548              </field>
1549            </fields>
1550          </register>
1551          <register>
1552            <name>MS_ATT1</name>
1553            <description>Master attributes 1</description>
1554            <addressOffset>0x34</addressOffset>
1555            <size>32</size>
1556            <access>read-write</access>
1557            <resetValue>0x1F1F1F1F</resetValue>
1558            <resetMask>0x1F1F1F1F</resetMask>
1559            <fields>
1560              <field>
1561                <name>PC4_UR</name>
1562                <description>Protection context 4, user read enable.</description>
1563                <bitRange>[0:0]</bitRange>
1564                <access>read-only</access>
1565              </field>
1566              <field>
1567                <name>PC4_UW</name>
1568                <description>Protection context 4, user write enable.</description>
1569                <bitRange>[1:1]</bitRange>
1570                <access>read-write</access>
1571              </field>
1572              <field>
1573                <name>PC4_PR</name>
1574                <description>Protection context 4, privileged read enable.</description>
1575                <bitRange>[2:2]</bitRange>
1576                <access>read-only</access>
1577              </field>
1578              <field>
1579                <name>PC4_PW</name>
1580                <description>Protection context 4, privileged write enable.</description>
1581                <bitRange>[3:3]</bitRange>
1582                <access>read-write</access>
1583              </field>
1584              <field>
1585                <name>PC4_NS</name>
1586                <description>Protection context 4, non-secure.</description>
1587                <bitRange>[4:4]</bitRange>
1588                <access>read-write</access>
1589              </field>
1590              <field>
1591                <name>PC5_UR</name>
1592                <description>Protection context 5, user read enable.</description>
1593                <bitRange>[8:8]</bitRange>
1594                <access>read-only</access>
1595              </field>
1596              <field>
1597                <name>PC5_UW</name>
1598                <description>Protection context 5, user write enable.</description>
1599                <bitRange>[9:9]</bitRange>
1600                <access>read-write</access>
1601              </field>
1602              <field>
1603                <name>PC5_PR</name>
1604                <description>Protection context 5, privileged read enable.</description>
1605                <bitRange>[10:10]</bitRange>
1606                <access>read-only</access>
1607              </field>
1608              <field>
1609                <name>PC5_PW</name>
1610                <description>Protection context 5, privileged write enable.</description>
1611                <bitRange>[11:11]</bitRange>
1612                <access>read-write</access>
1613              </field>
1614              <field>
1615                <name>PC5_NS</name>
1616                <description>Protection context 5, non-secure.</description>
1617                <bitRange>[12:12]</bitRange>
1618                <access>read-write</access>
1619              </field>
1620              <field>
1621                <name>PC6_UR</name>
1622                <description>Protection context 6, user read enable.</description>
1623                <bitRange>[16:16]</bitRange>
1624                <access>read-only</access>
1625              </field>
1626              <field>
1627                <name>PC6_UW</name>
1628                <description>Protection context 6, user write enable.</description>
1629                <bitRange>[17:17]</bitRange>
1630                <access>read-write</access>
1631              </field>
1632              <field>
1633                <name>PC6_PR</name>
1634                <description>Protection context 6, privileged read enable.</description>
1635                <bitRange>[18:18]</bitRange>
1636                <access>read-only</access>
1637              </field>
1638              <field>
1639                <name>PC6_PW</name>
1640                <description>Protection context 6, privileged write enable.</description>
1641                <bitRange>[19:19]</bitRange>
1642                <access>read-write</access>
1643              </field>
1644              <field>
1645                <name>PC6_NS</name>
1646                <description>Protection context 6, non-secure.</description>
1647                <bitRange>[20:20]</bitRange>
1648                <access>read-write</access>
1649              </field>
1650              <field>
1651                <name>PC7_UR</name>
1652                <description>Protection context 7, user read enable.</description>
1653                <bitRange>[24:24]</bitRange>
1654                <access>read-only</access>
1655              </field>
1656              <field>
1657                <name>PC7_UW</name>
1658                <description>Protection context 7, user write enable.</description>
1659                <bitRange>[25:25]</bitRange>
1660                <access>read-write</access>
1661              </field>
1662              <field>
1663                <name>PC7_PR</name>
1664                <description>Protection context 7, privileged read enable.</description>
1665                <bitRange>[26:26]</bitRange>
1666                <access>read-only</access>
1667              </field>
1668              <field>
1669                <name>PC7_PW</name>
1670                <description>Protection context 7, privileged write enable.</description>
1671                <bitRange>[27:27]</bitRange>
1672                <access>read-write</access>
1673              </field>
1674              <field>
1675                <name>PC7_NS</name>
1676                <description>Protection context 7, non-secure.</description>
1677                <bitRange>[28:28]</bitRange>
1678                <access>read-write</access>
1679              </field>
1680            </fields>
1681          </register>
1682          <register>
1683            <name>MS_ATT2</name>
1684            <description>Master attributes 2</description>
1685            <addressOffset>0x38</addressOffset>
1686            <size>32</size>
1687            <access>read-write</access>
1688            <resetValue>0x1F1F1F1F</resetValue>
1689            <resetMask>0x1F1F1F1F</resetMask>
1690            <fields>
1691              <field>
1692                <name>PC8_UR</name>
1693                <description>Protection context 8, user read enable.</description>
1694                <bitRange>[0:0]</bitRange>
1695                <access>read-only</access>
1696              </field>
1697              <field>
1698                <name>PC8_UW</name>
1699                <description>Protection context 8, user write enable.</description>
1700                <bitRange>[1:1]</bitRange>
1701                <access>read-write</access>
1702              </field>
1703              <field>
1704                <name>PC8_PR</name>
1705                <description>Protection context 8, privileged read enable.</description>
1706                <bitRange>[2:2]</bitRange>
1707                <access>read-only</access>
1708              </field>
1709              <field>
1710                <name>PC8_PW</name>
1711                <description>Protection context 8, privileged write enable.</description>
1712                <bitRange>[3:3]</bitRange>
1713                <access>read-write</access>
1714              </field>
1715              <field>
1716                <name>PC8_NS</name>
1717                <description>Protection context 8, non-secure.</description>
1718                <bitRange>[4:4]</bitRange>
1719                <access>read-write</access>
1720              </field>
1721              <field>
1722                <name>PC9_UR</name>
1723                <description>Protection context 9, user read enable.</description>
1724                <bitRange>[8:8]</bitRange>
1725                <access>read-only</access>
1726              </field>
1727              <field>
1728                <name>PC9_UW</name>
1729                <description>Protection context 9, user write enable.</description>
1730                <bitRange>[9:9]</bitRange>
1731                <access>read-write</access>
1732              </field>
1733              <field>
1734                <name>PC9_PR</name>
1735                <description>Protection context 9, privileged read enable.</description>
1736                <bitRange>[10:10]</bitRange>
1737                <access>read-only</access>
1738              </field>
1739              <field>
1740                <name>PC9_PW</name>
1741                <description>Protection context 9, privileged write enable.</description>
1742                <bitRange>[11:11]</bitRange>
1743                <access>read-write</access>
1744              </field>
1745              <field>
1746                <name>PC9_NS</name>
1747                <description>Protection context 9, non-secure.</description>
1748                <bitRange>[12:12]</bitRange>
1749                <access>read-write</access>
1750              </field>
1751              <field>
1752                <name>PC10_UR</name>
1753                <description>Protection context 10, user read enable.</description>
1754                <bitRange>[16:16]</bitRange>
1755                <access>read-only</access>
1756              </field>
1757              <field>
1758                <name>PC10_UW</name>
1759                <description>Protection context 10, user write enable.</description>
1760                <bitRange>[17:17]</bitRange>
1761                <access>read-write</access>
1762              </field>
1763              <field>
1764                <name>PC10_PR</name>
1765                <description>Protection context 10, privileged read enable.</description>
1766                <bitRange>[18:18]</bitRange>
1767                <access>read-only</access>
1768              </field>
1769              <field>
1770                <name>PC10_PW</name>
1771                <description>Protection context 10, privileged write enable.</description>
1772                <bitRange>[19:19]</bitRange>
1773                <access>read-write</access>
1774              </field>
1775              <field>
1776                <name>PC10_NS</name>
1777                <description>Protection context 10, non-secure.</description>
1778                <bitRange>[20:20]</bitRange>
1779                <access>read-write</access>
1780              </field>
1781              <field>
1782                <name>PC11_UR</name>
1783                <description>Protection context 11, user read enable.</description>
1784                <bitRange>[24:24]</bitRange>
1785                <access>read-only</access>
1786              </field>
1787              <field>
1788                <name>PC11_UW</name>
1789                <description>Protection context 11, user write enable.</description>
1790                <bitRange>[25:25]</bitRange>
1791                <access>read-write</access>
1792              </field>
1793              <field>
1794                <name>PC11_PR</name>
1795                <description>Protection context 11, privileged read enable.</description>
1796                <bitRange>[26:26]</bitRange>
1797                <access>read-only</access>
1798              </field>
1799              <field>
1800                <name>PC11_PW</name>
1801                <description>Protection context 11, privileged write enable.</description>
1802                <bitRange>[27:27]</bitRange>
1803                <access>read-write</access>
1804              </field>
1805              <field>
1806                <name>PC11_NS</name>
1807                <description>Protection context 11, non-secure.</description>
1808                <bitRange>[28:28]</bitRange>
1809                <access>read-write</access>
1810              </field>
1811            </fields>
1812          </register>
1813          <register>
1814            <name>MS_ATT3</name>
1815            <description>Master attributes 3</description>
1816            <addressOffset>0x3C</addressOffset>
1817            <size>32</size>
1818            <access>read-write</access>
1819            <resetValue>0x1F1F1F1F</resetValue>
1820            <resetMask>0x1F1F1F1F</resetMask>
1821            <fields>
1822              <field>
1823                <name>PC12_UR</name>
1824                <description>Protection context 12, user read enable.</description>
1825                <bitRange>[0:0]</bitRange>
1826                <access>read-only</access>
1827              </field>
1828              <field>
1829                <name>PC12_UW</name>
1830                <description>Protection context 12, user write enable.</description>
1831                <bitRange>[1:1]</bitRange>
1832                <access>read-write</access>
1833              </field>
1834              <field>
1835                <name>PC12_PR</name>
1836                <description>Protection context 12, privileged read enable.</description>
1837                <bitRange>[2:2]</bitRange>
1838                <access>read-only</access>
1839              </field>
1840              <field>
1841                <name>PC12_PW</name>
1842                <description>Protection context 12, privileged write enable.</description>
1843                <bitRange>[3:3]</bitRange>
1844                <access>read-write</access>
1845              </field>
1846              <field>
1847                <name>PC12_NS</name>
1848                <description>Protection context 12, non-secure.</description>
1849                <bitRange>[4:4]</bitRange>
1850                <access>read-write</access>
1851              </field>
1852              <field>
1853                <name>PC13_UR</name>
1854                <description>Protection context 13, user read enable.</description>
1855                <bitRange>[8:8]</bitRange>
1856                <access>read-only</access>
1857              </field>
1858              <field>
1859                <name>PC13_UW</name>
1860                <description>Protection context 13, user write enable.</description>
1861                <bitRange>[9:9]</bitRange>
1862                <access>read-write</access>
1863              </field>
1864              <field>
1865                <name>PC13_PR</name>
1866                <description>Protection context 13, privileged read enable.</description>
1867                <bitRange>[10:10]</bitRange>
1868                <access>read-only</access>
1869              </field>
1870              <field>
1871                <name>PC13_PW</name>
1872                <description>Protection context 13, privileged write enable.</description>
1873                <bitRange>[11:11]</bitRange>
1874                <access>read-write</access>
1875              </field>
1876              <field>
1877                <name>PC13_NS</name>
1878                <description>Protection context 13, non-secure.</description>
1879                <bitRange>[12:12]</bitRange>
1880                <access>read-write</access>
1881              </field>
1882              <field>
1883                <name>PC14_UR</name>
1884                <description>Protection context 14, user read enable.</description>
1885                <bitRange>[16:16]</bitRange>
1886                <access>read-only</access>
1887              </field>
1888              <field>
1889                <name>PC14_UW</name>
1890                <description>Protection context 14, user write enable.</description>
1891                <bitRange>[17:17]</bitRange>
1892                <access>read-write</access>
1893              </field>
1894              <field>
1895                <name>PC14_PR</name>
1896                <description>Protection context 14, privileged read enable.</description>
1897                <bitRange>[18:18]</bitRange>
1898                <access>read-only</access>
1899              </field>
1900              <field>
1901                <name>PC14_PW</name>
1902                <description>Protection context 14, privileged write enable.</description>
1903                <bitRange>[19:19]</bitRange>
1904                <access>read-write</access>
1905              </field>
1906              <field>
1907                <name>PC14_NS</name>
1908                <description>Protection context 14, non-secure.</description>
1909                <bitRange>[20:20]</bitRange>
1910                <access>read-write</access>
1911              </field>
1912              <field>
1913                <name>PC15_UR</name>
1914                <description>Protection context 15, user read enable.</description>
1915                <bitRange>[24:24]</bitRange>
1916                <access>read-only</access>
1917              </field>
1918              <field>
1919                <name>PC15_UW</name>
1920                <description>Protection context 15, user write enable.</description>
1921                <bitRange>[25:25]</bitRange>
1922                <access>read-write</access>
1923              </field>
1924              <field>
1925                <name>PC15_PR</name>
1926                <description>Protection context 15, privileged read enable.</description>
1927                <bitRange>[26:26]</bitRange>
1928                <access>read-only</access>
1929              </field>
1930              <field>
1931                <name>PC15_PW</name>
1932                <description>Protection context 15, privileged write enable.</description>
1933                <bitRange>[27:27]</bitRange>
1934                <access>read-write</access>
1935              </field>
1936              <field>
1937                <name>PC15_NS</name>
1938                <description>Protection context 15, non-secure.</description>
1939                <bitRange>[28:28]</bitRange>
1940                <access>read-write</access>
1941              </field>
1942            </fields>
1943          </register>
1944        </cluster>
1945        <cluster>
1946          <dim>230</dim>
1947          <dimIncrement>64</dimIncrement>
1948          <name>PPU_FX[%s]</name>
1949          <description>Fixed protection structure pair</description>
1950          <addressOffset>0x00000800</addressOffset>
1951          <register>
1952            <name>SL_ADDR</name>
1953            <description>Slave region, base address</description>
1954            <addressOffset>0x0</addressOffset>
1955            <size>32</size>
1956            <access>read-only</access>
1957            <resetValue>0x0</resetValue>
1958            <resetMask>0xFFFFFFFC</resetMask>
1959            <fields>
1960              <field>
1961                <name>ADDR30</name>
1962                <description>This field specifies the base address of the slave region. The region size is defined by SL_SIZE.REGION_SIZE. A region of n Bytes must be n Byte aligned. Therefore, some of the lesser significant address bits of ADDR30 must be '0's. E.g., a 64 KB address region (REGION_SIZE is '15') must be 64 KByte aligned, and ADDR30[13:0] must be '0's.</description>
1963                <bitRange>[31:2]</bitRange>
1964                <access>read-only</access>
1965              </field>
1966            </fields>
1967          </register>
1968          <register>
1969            <name>SL_SIZE</name>
1970            <description>Slave region, size</description>
1971            <addressOffset>0x4</addressOffset>
1972            <size>32</size>
1973            <access>read-only</access>
1974            <resetValue>0x80000000</resetValue>
1975            <resetMask>0x9F000000</resetMask>
1976            <fields>
1977              <field>
1978                <name>REGION_SIZE</name>
1979                <description>This field specifies the size of the slave region:
1980'0': Undefined.
1981'1': 4 B region (this is the smallest region size).
1982'2': 8 B region
1983'3': 16 B region
1984'4': 32 B region
1985'5': 64 B region
1986'6': 128 B region
1987'7': 256 B region
1988'8': 512 B region
1989'9': 1 KB region
1990'10': 2 KB region
1991'11': 4 KB region
1992'12': 8 KB region
1993'13': 16 KB region
1994'14': 32 KB region
1995'15': 64 KB region
1996'16': 128 KB region
1997'17': 256 KB region
1998'18': 512 KB region
1999'19': 1 MB region
2000'20': 2 MB region
2001'21': 4 MB region
2002'22': 8 MB region
2003'23': 16 MB region
2004'24': 32 MB region
2005'25': 64 MB region
2006'26': 128 MB region
2007'27': 256 MB region
2008'28': 512 MB region
2009'29': 1 GB region
2010'30': 2 GB region
2011'31': 4 GB region</description>
2012                <bitRange>[28:24]</bitRange>
2013                <access>read-only</access>
2014              </field>
2015              <field>
2016                <name>VALID</name>
2017                <description>Slave region enable:
2018'0': Disabled. A disabled region will never result in a match on the transfer address.
2019'1': Enabled.</description>
2020                <bitRange>[31:31]</bitRange>
2021                <access>read-only</access>
2022              </field>
2023            </fields>
2024          </register>
2025          <register>
2026            <name>SL_ATT0</name>
2027            <description>Slave attributes 0</description>
2028            <addressOffset>0x10</addressOffset>
2029            <size>32</size>
2030            <access>read-write</access>
2031            <resetValue>0x1F1F1F1F</resetValue>
2032            <resetMask>0x1F1F1F1F</resetMask>
2033            <fields>
2034              <field>
2035                <name>PC0_UR</name>
2036                <description>Protection context 0, user read enable:
2037'0': Disabled (user, read accesses are NOT allowed).
2038'1': Enabled (user, read accesses are allowed).</description>
2039                <bitRange>[0:0]</bitRange>
2040                <access>read-only</access>
2041              </field>
2042              <field>
2043                <name>PC0_UW</name>
2044                <description>Protection context 0, user write enable:
2045'0': Disabled (user, write accesses are NOT allowed).
2046'1': Enabled (user, write accesses are allowed).</description>
2047                <bitRange>[1:1]</bitRange>
2048                <access>read-only</access>
2049              </field>
2050              <field>
2051                <name>PC0_PR</name>
2052                <description>Protection context 0, privileged read enable:
2053'0': Disabled (privileged, read accesses are NOT allowed).
2054'1': Enabled (privileged, read accesses are allowed).</description>
2055                <bitRange>[2:2]</bitRange>
2056                <access>read-only</access>
2057              </field>
2058              <field>
2059                <name>PC0_PW</name>
2060                <description>Protection context 0, privileged write enable:
2061'0': Disabled (privileged, write accesses are NOT allowed).
2062'1': Enabled (privileged, write accesses are allowed).</description>
2063                <bitRange>[3:3]</bitRange>
2064                <access>read-only</access>
2065              </field>
2066              <field>
2067                <name>PC0_NS</name>
2068                <description>Protection context 0, non-secure:
2069'0': Secure (secure accesses allowed, non-secure access NOT allowed).
2070'1': Non-secure (both secure and non-secure accesses allowed).</description>
2071                <bitRange>[4:4]</bitRange>
2072                <access>read-only</access>
2073              </field>
2074              <field>
2075                <name>PC1_UR</name>
2076                <description>Protection context 1, user read enable.</description>
2077                <bitRange>[8:8]</bitRange>
2078                <access>read-write</access>
2079              </field>
2080              <field>
2081                <name>PC1_UW</name>
2082                <description>Protection context 1, user write enable.</description>
2083                <bitRange>[9:9]</bitRange>
2084                <access>read-write</access>
2085              </field>
2086              <field>
2087                <name>PC1_PR</name>
2088                <description>Protection context 1, privileged read enable.</description>
2089                <bitRange>[10:10]</bitRange>
2090                <access>read-write</access>
2091              </field>
2092              <field>
2093                <name>PC1_PW</name>
2094                <description>Protection context 1, privileged write enable.</description>
2095                <bitRange>[11:11]</bitRange>
2096                <access>read-write</access>
2097              </field>
2098              <field>
2099                <name>PC1_NS</name>
2100                <description>Protection context 1, non-secure.</description>
2101                <bitRange>[12:12]</bitRange>
2102                <access>read-write</access>
2103              </field>
2104              <field>
2105                <name>PC2_UR</name>
2106                <description>Protection context 2, user read enable.</description>
2107                <bitRange>[16:16]</bitRange>
2108                <access>read-write</access>
2109              </field>
2110              <field>
2111                <name>PC2_UW</name>
2112                <description>Protection context 2, user write enable.</description>
2113                <bitRange>[17:17]</bitRange>
2114                <access>read-write</access>
2115              </field>
2116              <field>
2117                <name>PC2_PR</name>
2118                <description>Protection context 2, privileged read enable.</description>
2119                <bitRange>[18:18]</bitRange>
2120                <access>read-write</access>
2121              </field>
2122              <field>
2123                <name>PC2_PW</name>
2124                <description>Protection context 2, privileged write enable.</description>
2125                <bitRange>[19:19]</bitRange>
2126                <access>read-write</access>
2127              </field>
2128              <field>
2129                <name>PC2_NS</name>
2130                <description>Protection context 2, non-secure.</description>
2131                <bitRange>[20:20]</bitRange>
2132                <access>read-write</access>
2133              </field>
2134              <field>
2135                <name>PC3_UR</name>
2136                <description>Protection context 3, user read enable.</description>
2137                <bitRange>[24:24]</bitRange>
2138                <access>read-write</access>
2139              </field>
2140              <field>
2141                <name>PC3_UW</name>
2142                <description>Protection context 3, user write enable.</description>
2143                <bitRange>[25:25]</bitRange>
2144                <access>read-write</access>
2145              </field>
2146              <field>
2147                <name>PC3_PR</name>
2148                <description>Protection context 3, privileged read enable.</description>
2149                <bitRange>[26:26]</bitRange>
2150                <access>read-write</access>
2151              </field>
2152              <field>
2153                <name>PC3_PW</name>
2154                <description>Protection context 3, privileged write enable.</description>
2155                <bitRange>[27:27]</bitRange>
2156                <access>read-write</access>
2157              </field>
2158              <field>
2159                <name>PC3_NS</name>
2160                <description>Protection context 3, non-secure.</description>
2161                <bitRange>[28:28]</bitRange>
2162                <access>read-write</access>
2163              </field>
2164            </fields>
2165          </register>
2166          <register>
2167            <name>SL_ATT1</name>
2168            <description>Slave attributes 1</description>
2169            <addressOffset>0x14</addressOffset>
2170            <size>32</size>
2171            <access>read-write</access>
2172            <resetValue>0x1F1F1F1F</resetValue>
2173            <resetMask>0x1F1F1F1F</resetMask>
2174            <fields>
2175              <field>
2176                <name>PC4_UR</name>
2177                <description>Protection context 4, user read enable.</description>
2178                <bitRange>[0:0]</bitRange>
2179                <access>read-write</access>
2180              </field>
2181              <field>
2182                <name>PC4_UW</name>
2183                <description>Protection context 4, user write enable.</description>
2184                <bitRange>[1:1]</bitRange>
2185                <access>read-write</access>
2186              </field>
2187              <field>
2188                <name>PC4_PR</name>
2189                <description>Protection context 4, privileged read enable.</description>
2190                <bitRange>[2:2]</bitRange>
2191                <access>read-write</access>
2192              </field>
2193              <field>
2194                <name>PC4_PW</name>
2195                <description>Protection context 4, privileged write enable.</description>
2196                <bitRange>[3:3]</bitRange>
2197                <access>read-write</access>
2198              </field>
2199              <field>
2200                <name>PC4_NS</name>
2201                <description>Protection context 4, non-secure.</description>
2202                <bitRange>[4:4]</bitRange>
2203                <access>read-write</access>
2204              </field>
2205              <field>
2206                <name>PC5_UR</name>
2207                <description>Protection context 5, user read enable.</description>
2208                <bitRange>[8:8]</bitRange>
2209                <access>read-write</access>
2210              </field>
2211              <field>
2212                <name>PC5_UW</name>
2213                <description>Protection context 5, user write enable.</description>
2214                <bitRange>[9:9]</bitRange>
2215                <access>read-write</access>
2216              </field>
2217              <field>
2218                <name>PC5_PR</name>
2219                <description>Protection context 5, privileged read enable.</description>
2220                <bitRange>[10:10]</bitRange>
2221                <access>read-write</access>
2222              </field>
2223              <field>
2224                <name>PC5_PW</name>
2225                <description>Protection context 5, privileged write enable.</description>
2226                <bitRange>[11:11]</bitRange>
2227                <access>read-write</access>
2228              </field>
2229              <field>
2230                <name>PC5_NS</name>
2231                <description>Protection context 5, non-secure.</description>
2232                <bitRange>[12:12]</bitRange>
2233                <access>read-write</access>
2234              </field>
2235              <field>
2236                <name>PC6_UR</name>
2237                <description>Protection context 6, user read enable.</description>
2238                <bitRange>[16:16]</bitRange>
2239                <access>read-write</access>
2240              </field>
2241              <field>
2242                <name>PC6_UW</name>
2243                <description>Protection context 6, user write enable.</description>
2244                <bitRange>[17:17]</bitRange>
2245                <access>read-write</access>
2246              </field>
2247              <field>
2248                <name>PC6_PR</name>
2249                <description>Protection context 6, privileged read enable.</description>
2250                <bitRange>[18:18]</bitRange>
2251                <access>read-write</access>
2252              </field>
2253              <field>
2254                <name>PC6_PW</name>
2255                <description>Protection context 6, privileged write enable.</description>
2256                <bitRange>[19:19]</bitRange>
2257                <access>read-write</access>
2258              </field>
2259              <field>
2260                <name>PC6_NS</name>
2261                <description>Protection context 6, non-secure.</description>
2262                <bitRange>[20:20]</bitRange>
2263                <access>read-write</access>
2264              </field>
2265              <field>
2266                <name>PC7_UR</name>
2267                <description>Protection context 7, user read enable.</description>
2268                <bitRange>[24:24]</bitRange>
2269                <access>read-write</access>
2270              </field>
2271              <field>
2272                <name>PC7_UW</name>
2273                <description>Protection context 7, user write enable.</description>
2274                <bitRange>[25:25]</bitRange>
2275                <access>read-write</access>
2276              </field>
2277              <field>
2278                <name>PC7_PR</name>
2279                <description>Protection context 7, privileged read enable.</description>
2280                <bitRange>[26:26]</bitRange>
2281                <access>read-write</access>
2282              </field>
2283              <field>
2284                <name>PC7_PW</name>
2285                <description>Protection context 7, privileged write enable.</description>
2286                <bitRange>[27:27]</bitRange>
2287                <access>read-write</access>
2288              </field>
2289              <field>
2290                <name>PC7_NS</name>
2291                <description>Protection context 7, non-secure.</description>
2292                <bitRange>[28:28]</bitRange>
2293                <access>read-write</access>
2294              </field>
2295            </fields>
2296          </register>
2297          <register>
2298            <name>SL_ATT2</name>
2299            <description>Slave attributes 2</description>
2300            <addressOffset>0x18</addressOffset>
2301            <size>32</size>
2302            <access>read-write</access>
2303            <resetValue>0x1F1F1F1F</resetValue>
2304            <resetMask>0x1F1F1F1F</resetMask>
2305            <fields>
2306              <field>
2307                <name>PC8_UR</name>
2308                <description>Protection context 8, user read enable.</description>
2309                <bitRange>[0:0]</bitRange>
2310                <access>read-write</access>
2311              </field>
2312              <field>
2313                <name>PC8_UW</name>
2314                <description>Protection context 8, user write enable.</description>
2315                <bitRange>[1:1]</bitRange>
2316                <access>read-write</access>
2317              </field>
2318              <field>
2319                <name>PC8_PR</name>
2320                <description>Protection context 8, privileged read enable.</description>
2321                <bitRange>[2:2]</bitRange>
2322                <access>read-write</access>
2323              </field>
2324              <field>
2325                <name>PC8_PW</name>
2326                <description>Protection context 8, privileged write enable.</description>
2327                <bitRange>[3:3]</bitRange>
2328                <access>read-write</access>
2329              </field>
2330              <field>
2331                <name>PC8_NS</name>
2332                <description>Protection context 8, non-secure.</description>
2333                <bitRange>[4:4]</bitRange>
2334                <access>read-write</access>
2335              </field>
2336              <field>
2337                <name>PC9_UR</name>
2338                <description>Protection context 9, user read enable.</description>
2339                <bitRange>[8:8]</bitRange>
2340                <access>read-write</access>
2341              </field>
2342              <field>
2343                <name>PC9_UW</name>
2344                <description>Protection context 9, user write enable.</description>
2345                <bitRange>[9:9]</bitRange>
2346                <access>read-write</access>
2347              </field>
2348              <field>
2349                <name>PC9_PR</name>
2350                <description>Protection context 9, privileged read enable.</description>
2351                <bitRange>[10:10]</bitRange>
2352                <access>read-write</access>
2353              </field>
2354              <field>
2355                <name>PC9_PW</name>
2356                <description>Protection context 9, privileged write enable.</description>
2357                <bitRange>[11:11]</bitRange>
2358                <access>read-write</access>
2359              </field>
2360              <field>
2361                <name>PC9_NS</name>
2362                <description>Protection context 9, non-secure.</description>
2363                <bitRange>[12:12]</bitRange>
2364                <access>read-write</access>
2365              </field>
2366              <field>
2367                <name>PC10_UR</name>
2368                <description>Protection context 10, user read enable.</description>
2369                <bitRange>[16:16]</bitRange>
2370                <access>read-write</access>
2371              </field>
2372              <field>
2373                <name>PC10_UW</name>
2374                <description>Protection context 10, user write enable.</description>
2375                <bitRange>[17:17]</bitRange>
2376                <access>read-write</access>
2377              </field>
2378              <field>
2379                <name>PC10_PR</name>
2380                <description>Protection context 10, privileged read enable.</description>
2381                <bitRange>[18:18]</bitRange>
2382                <access>read-write</access>
2383              </field>
2384              <field>
2385                <name>PC10_PW</name>
2386                <description>Protection context 10, privileged write enable.</description>
2387                <bitRange>[19:19]</bitRange>
2388                <access>read-write</access>
2389              </field>
2390              <field>
2391                <name>PC10_NS</name>
2392                <description>Protection context 10, non-secure.</description>
2393                <bitRange>[20:20]</bitRange>
2394                <access>read-write</access>
2395              </field>
2396              <field>
2397                <name>PC11_UR</name>
2398                <description>Protection context 11, user read enable.</description>
2399                <bitRange>[24:24]</bitRange>
2400                <access>read-write</access>
2401              </field>
2402              <field>
2403                <name>PC11_UW</name>
2404                <description>Protection context 11, user write enable.</description>
2405                <bitRange>[25:25]</bitRange>
2406                <access>read-write</access>
2407              </field>
2408              <field>
2409                <name>PC11_PR</name>
2410                <description>Protection context 11, privileged read enable.</description>
2411                <bitRange>[26:26]</bitRange>
2412                <access>read-write</access>
2413              </field>
2414              <field>
2415                <name>PC11_PW</name>
2416                <description>Protection context 11, privileged write enable.</description>
2417                <bitRange>[27:27]</bitRange>
2418                <access>read-write</access>
2419              </field>
2420              <field>
2421                <name>PC11_NS</name>
2422                <description>Protection context 11, non-secure.</description>
2423                <bitRange>[28:28]</bitRange>
2424                <access>read-write</access>
2425              </field>
2426            </fields>
2427          </register>
2428          <register>
2429            <name>SL_ATT3</name>
2430            <description>Slave attributes 3</description>
2431            <addressOffset>0x1C</addressOffset>
2432            <size>32</size>
2433            <access>read-write</access>
2434            <resetValue>0x1F1F1F1F</resetValue>
2435            <resetMask>0x1F1F1F1F</resetMask>
2436            <fields>
2437              <field>
2438                <name>PC12_UR</name>
2439                <description>Protection context 12, user read enable.</description>
2440                <bitRange>[0:0]</bitRange>
2441                <access>read-write</access>
2442              </field>
2443              <field>
2444                <name>PC12_UW</name>
2445                <description>Protection context 12, user write enable.</description>
2446                <bitRange>[1:1]</bitRange>
2447                <access>read-write</access>
2448              </field>
2449              <field>
2450                <name>PC12_PR</name>
2451                <description>Protection context 12, privileged read enable.</description>
2452                <bitRange>[2:2]</bitRange>
2453                <access>read-write</access>
2454              </field>
2455              <field>
2456                <name>PC12_PW</name>
2457                <description>Protection context 12, privileged write enable.</description>
2458                <bitRange>[3:3]</bitRange>
2459                <access>read-write</access>
2460              </field>
2461              <field>
2462                <name>PC12_NS</name>
2463                <description>Protection context 12, non-secure.</description>
2464                <bitRange>[4:4]</bitRange>
2465                <access>read-write</access>
2466              </field>
2467              <field>
2468                <name>PC13_UR</name>
2469                <description>Protection context 13, user read enable.</description>
2470                <bitRange>[8:8]</bitRange>
2471                <access>read-write</access>
2472              </field>
2473              <field>
2474                <name>PC13_UW</name>
2475                <description>Protection context 13, user write enable.</description>
2476                <bitRange>[9:9]</bitRange>
2477                <access>read-write</access>
2478              </field>
2479              <field>
2480                <name>PC13_PR</name>
2481                <description>Protection context 13, privileged read enable.</description>
2482                <bitRange>[10:10]</bitRange>
2483                <access>read-write</access>
2484              </field>
2485              <field>
2486                <name>PC13_PW</name>
2487                <description>Protection context 13, privileged write enable.</description>
2488                <bitRange>[11:11]</bitRange>
2489                <access>read-write</access>
2490              </field>
2491              <field>
2492                <name>PC13_NS</name>
2493                <description>Protection context 13, non-secure.</description>
2494                <bitRange>[12:12]</bitRange>
2495                <access>read-write</access>
2496              </field>
2497              <field>
2498                <name>PC14_UR</name>
2499                <description>Protection context 14, user read enable.</description>
2500                <bitRange>[16:16]</bitRange>
2501                <access>read-write</access>
2502              </field>
2503              <field>
2504                <name>PC14_UW</name>
2505                <description>Protection context 14, user write enable.</description>
2506                <bitRange>[17:17]</bitRange>
2507                <access>read-write</access>
2508              </field>
2509              <field>
2510                <name>PC14_PR</name>
2511                <description>Protection context 14, privileged read enable.</description>
2512                <bitRange>[18:18]</bitRange>
2513                <access>read-write</access>
2514              </field>
2515              <field>
2516                <name>PC14_PW</name>
2517                <description>Protection context 14, privileged write enable.</description>
2518                <bitRange>[19:19]</bitRange>
2519                <access>read-write</access>
2520              </field>
2521              <field>
2522                <name>PC14_NS</name>
2523                <description>Protection context 14, non-secure.</description>
2524                <bitRange>[20:20]</bitRange>
2525                <access>read-write</access>
2526              </field>
2527              <field>
2528                <name>PC15_UR</name>
2529                <description>Protection context 15, user read enable.</description>
2530                <bitRange>[24:24]</bitRange>
2531                <access>read-write</access>
2532              </field>
2533              <field>
2534                <name>PC15_UW</name>
2535                <description>Protection context 15, user write enable.</description>
2536                <bitRange>[25:25]</bitRange>
2537                <access>read-write</access>
2538              </field>
2539              <field>
2540                <name>PC15_PR</name>
2541                <description>Protection context 15, privileged read enable.</description>
2542                <bitRange>[26:26]</bitRange>
2543                <access>read-write</access>
2544              </field>
2545              <field>
2546                <name>PC15_PW</name>
2547                <description>Protection context 15, privileged write enable.</description>
2548                <bitRange>[27:27]</bitRange>
2549                <access>read-write</access>
2550              </field>
2551              <field>
2552                <name>PC15_NS</name>
2553                <description>Protection context 15, non-secure.</description>
2554                <bitRange>[28:28]</bitRange>
2555                <access>read-write</access>
2556              </field>
2557            </fields>
2558          </register>
2559          <register>
2560            <name>MS_ADDR</name>
2561            <description>Master region, base address</description>
2562            <addressOffset>0x20</addressOffset>
2563            <size>32</size>
2564            <access>read-only</access>
2565            <resetValue>0x0</resetValue>
2566            <resetMask>0xFFFFFFC0</resetMask>
2567            <fields>
2568              <field>
2569                <name>ADDR26</name>
2570                <description>This field specifies the base address of the master region. The base address of the region is the address of the SL_ADDR register.</description>
2571                <bitRange>[31:6]</bitRange>
2572                <access>read-only</access>
2573              </field>
2574            </fields>
2575          </register>
2576          <register>
2577            <name>MS_SIZE</name>
2578            <description>Master region, size</description>
2579            <addressOffset>0x24</addressOffset>
2580            <size>32</size>
2581            <access>read-only</access>
2582            <resetValue>0x85000000</resetValue>
2583            <resetMask>0x9F000000</resetMask>
2584            <fields>
2585              <field>
2586                <name>REGION_SIZE</name>
2587                <description>This field specifies the size of the master region:
2588'5': 64 B region
2589
2590The master region includes the SL_ADDR, SL_SIZE, SL_ATT0, ..., SL_ATT3, MS_ADDR, MS_SIZE, MS_ATT0, ..., MS_ATT3 registers. Therefore, the access privileges for all these registers is determined by MS_ATT0, ..., MS_ATT3.</description>
2591                <bitRange>[28:24]</bitRange>
2592                <access>read-only</access>
2593              </field>
2594              <field>
2595                <name>VALID</name>
2596                <description>Master region enable:
2597'1': Enabled.</description>
2598                <bitRange>[31:31]</bitRange>
2599                <access>read-only</access>
2600              </field>
2601            </fields>
2602          </register>
2603          <register>
2604            <name>MS_ATT0</name>
2605            <description>Master attributes 0</description>
2606            <addressOffset>0x30</addressOffset>
2607            <size>32</size>
2608            <access>read-write</access>
2609            <resetValue>0x1F1F1F1F</resetValue>
2610            <resetMask>0x1F1F1F1F</resetMask>
2611            <fields>
2612              <field>
2613                <name>PC0_UR</name>
2614                <description>Protection context 0, user read enable:
2615'0': Disabled (user, read accesses are NOT allowed).
2616'1': Enabled (user, read accesses are allowed).</description>
2617                <bitRange>[0:0]</bitRange>
2618                <access>read-only</access>
2619              </field>
2620              <field>
2621                <name>PC0_UW</name>
2622                <description>Protection context 0, user write enable:
2623'0': Disabled (user, write accesses are NOT allowed).
2624'1': Enabled (user, write accesses are allowed).</description>
2625                <bitRange>[1:1]</bitRange>
2626                <access>read-only</access>
2627              </field>
2628              <field>
2629                <name>PC0_PR</name>
2630                <description>Protection context 0, privileged read enable:
2631'0': Disabled (privileged, read accesses are NOT allowed).
2632'1': Enabled (privileged, read accesses are allowed).</description>
2633                <bitRange>[2:2]</bitRange>
2634                <access>read-only</access>
2635              </field>
2636              <field>
2637                <name>PC0_PW</name>
2638                <description>Protection context 0, privileged write enable:
2639'0': Disabled (privileged, write accesses are NOT allowed).
2640'1': Enabled (privileged, write accesses are allowed).</description>
2641                <bitRange>[3:3]</bitRange>
2642                <access>read-only</access>
2643              </field>
2644              <field>
2645                <name>PC0_NS</name>
2646                <description>Protection context 0, non-secure:
2647'0': Secure (secure accesses allowed, non-secure access NOT allowed).
2648'1': Non-secure (both secure and non-secure accesses allowed).</description>
2649                <bitRange>[4:4]</bitRange>
2650                <access>read-only</access>
2651              </field>
2652              <field>
2653                <name>PC1_UR</name>
2654                <description>Protection context 1, user read enable.</description>
2655                <bitRange>[8:8]</bitRange>
2656                <access>read-only</access>
2657              </field>
2658              <field>
2659                <name>PC1_UW</name>
2660                <description>Protection context 1, user write enable.</description>
2661                <bitRange>[9:9]</bitRange>
2662                <access>read-write</access>
2663              </field>
2664              <field>
2665                <name>PC1_PR</name>
2666                <description>Protection context 1, privileged read enable.</description>
2667                <bitRange>[10:10]</bitRange>
2668                <access>read-only</access>
2669              </field>
2670              <field>
2671                <name>PC1_PW</name>
2672                <description>Protection context 1, privileged write enable.</description>
2673                <bitRange>[11:11]</bitRange>
2674                <access>read-write</access>
2675              </field>
2676              <field>
2677                <name>PC1_NS</name>
2678                <description>Protection context 1, non-secure.</description>
2679                <bitRange>[12:12]</bitRange>
2680                <access>read-write</access>
2681              </field>
2682              <field>
2683                <name>PC2_UR</name>
2684                <description>Protection context 2, user read enable.</description>
2685                <bitRange>[16:16]</bitRange>
2686                <access>read-only</access>
2687              </field>
2688              <field>
2689                <name>PC2_UW</name>
2690                <description>Protection context 2, user write enable.</description>
2691                <bitRange>[17:17]</bitRange>
2692                <access>read-write</access>
2693              </field>
2694              <field>
2695                <name>PC2_PR</name>
2696                <description>Protection context 2, privileged read enable.</description>
2697                <bitRange>[18:18]</bitRange>
2698                <access>read-only</access>
2699              </field>
2700              <field>
2701                <name>PC2_PW</name>
2702                <description>Protection context 2, privileged write enable.</description>
2703                <bitRange>[19:19]</bitRange>
2704                <access>read-write</access>
2705              </field>
2706              <field>
2707                <name>PC2_NS</name>
2708                <description>Protection context 2, non-secure.</description>
2709                <bitRange>[20:20]</bitRange>
2710                <access>read-write</access>
2711              </field>
2712              <field>
2713                <name>PC3_UR</name>
2714                <description>Protection context 3, user read enable.</description>
2715                <bitRange>[24:24]</bitRange>
2716                <access>read-only</access>
2717              </field>
2718              <field>
2719                <name>PC3_UW</name>
2720                <description>Protection context 3, user write enable.</description>
2721                <bitRange>[25:25]</bitRange>
2722                <access>read-write</access>
2723              </field>
2724              <field>
2725                <name>PC3_PR</name>
2726                <description>Protection context 3, privileged read enable.</description>
2727                <bitRange>[26:26]</bitRange>
2728                <access>read-only</access>
2729              </field>
2730              <field>
2731                <name>PC3_PW</name>
2732                <description>Protection context 3, privileged write enable.</description>
2733                <bitRange>[27:27]</bitRange>
2734                <access>read-write</access>
2735              </field>
2736              <field>
2737                <name>PC3_NS</name>
2738                <description>Protection context 3, non-secure.</description>
2739                <bitRange>[28:28]</bitRange>
2740                <access>read-write</access>
2741              </field>
2742            </fields>
2743          </register>
2744          <register>
2745            <name>MS_ATT1</name>
2746            <description>Master attributes 1</description>
2747            <addressOffset>0x34</addressOffset>
2748            <size>32</size>
2749            <access>read-write</access>
2750            <resetValue>0x1F1F1F1F</resetValue>
2751            <resetMask>0x1F1F1F1F</resetMask>
2752            <fields>
2753              <field>
2754                <name>PC4_UR</name>
2755                <description>Protection context 4, user read enable.</description>
2756                <bitRange>[0:0]</bitRange>
2757                <access>read-only</access>
2758              </field>
2759              <field>
2760                <name>PC4_UW</name>
2761                <description>Protection context 4, user write enable.</description>
2762                <bitRange>[1:1]</bitRange>
2763                <access>read-write</access>
2764              </field>
2765              <field>
2766                <name>PC4_PR</name>
2767                <description>Protection context 4, privileged read enable.</description>
2768                <bitRange>[2:2]</bitRange>
2769                <access>read-only</access>
2770              </field>
2771              <field>
2772                <name>PC4_PW</name>
2773                <description>Protection context 4, privileged write enable.</description>
2774                <bitRange>[3:3]</bitRange>
2775                <access>read-write</access>
2776              </field>
2777              <field>
2778                <name>PC4_NS</name>
2779                <description>Protection context 4, non-secure.</description>
2780                <bitRange>[4:4]</bitRange>
2781                <access>read-write</access>
2782              </field>
2783              <field>
2784                <name>PC5_UR</name>
2785                <description>Protection context 5, user read enable.</description>
2786                <bitRange>[8:8]</bitRange>
2787                <access>read-only</access>
2788              </field>
2789              <field>
2790                <name>PC5_UW</name>
2791                <description>Protection context 5, user write enable.</description>
2792                <bitRange>[9:9]</bitRange>
2793                <access>read-write</access>
2794              </field>
2795              <field>
2796                <name>PC5_PR</name>
2797                <description>Protection context 5, privileged read enable.</description>
2798                <bitRange>[10:10]</bitRange>
2799                <access>read-only</access>
2800              </field>
2801              <field>
2802                <name>PC5_PW</name>
2803                <description>Protection context 5, privileged write enable.</description>
2804                <bitRange>[11:11]</bitRange>
2805                <access>read-write</access>
2806              </field>
2807              <field>
2808                <name>PC5_NS</name>
2809                <description>Protection context 5, non-secure.</description>
2810                <bitRange>[12:12]</bitRange>
2811                <access>read-write</access>
2812              </field>
2813              <field>
2814                <name>PC6_UR</name>
2815                <description>Protection context 6, user read enable.</description>
2816                <bitRange>[16:16]</bitRange>
2817                <access>read-only</access>
2818              </field>
2819              <field>
2820                <name>PC6_UW</name>
2821                <description>Protection context 6, user write enable.</description>
2822                <bitRange>[17:17]</bitRange>
2823                <access>read-write</access>
2824              </field>
2825              <field>
2826                <name>PC6_PR</name>
2827                <description>Protection context 6, privileged read enable.</description>
2828                <bitRange>[18:18]</bitRange>
2829                <access>read-only</access>
2830              </field>
2831              <field>
2832                <name>PC6_PW</name>
2833                <description>Protection context 6, privileged write enable.</description>
2834                <bitRange>[19:19]</bitRange>
2835                <access>read-write</access>
2836              </field>
2837              <field>
2838                <name>PC6_NS</name>
2839                <description>Protection context 6, non-secure.</description>
2840                <bitRange>[20:20]</bitRange>
2841                <access>read-write</access>
2842              </field>
2843              <field>
2844                <name>PC7_UR</name>
2845                <description>Protection context 7, user read enable.</description>
2846                <bitRange>[24:24]</bitRange>
2847                <access>read-only</access>
2848              </field>
2849              <field>
2850                <name>PC7_UW</name>
2851                <description>Protection context 7, user write enable.</description>
2852                <bitRange>[25:25]</bitRange>
2853                <access>read-write</access>
2854              </field>
2855              <field>
2856                <name>PC7_PR</name>
2857                <description>Protection context 7, privileged read enable.</description>
2858                <bitRange>[26:26]</bitRange>
2859                <access>read-only</access>
2860              </field>
2861              <field>
2862                <name>PC7_PW</name>
2863                <description>Protection context 7, privileged write enable.</description>
2864                <bitRange>[27:27]</bitRange>
2865                <access>read-write</access>
2866              </field>
2867              <field>
2868                <name>PC7_NS</name>
2869                <description>Protection context 7, non-secure.</description>
2870                <bitRange>[28:28]</bitRange>
2871                <access>read-write</access>
2872              </field>
2873            </fields>
2874          </register>
2875          <register>
2876            <name>MS_ATT2</name>
2877            <description>Master attributes 2</description>
2878            <addressOffset>0x38</addressOffset>
2879            <size>32</size>
2880            <access>read-write</access>
2881            <resetValue>0x1F1F1F1F</resetValue>
2882            <resetMask>0x1F1F1F1F</resetMask>
2883            <fields>
2884              <field>
2885                <name>PC8_UR</name>
2886                <description>Protection context 8, user read enable.</description>
2887                <bitRange>[0:0]</bitRange>
2888                <access>read-only</access>
2889              </field>
2890              <field>
2891                <name>PC8_UW</name>
2892                <description>Protection context 8, user write enable.</description>
2893                <bitRange>[1:1]</bitRange>
2894                <access>read-write</access>
2895              </field>
2896              <field>
2897                <name>PC8_PR</name>
2898                <description>Protection context 8, privileged read enable.</description>
2899                <bitRange>[2:2]</bitRange>
2900                <access>read-only</access>
2901              </field>
2902              <field>
2903                <name>PC8_PW</name>
2904                <description>Protection context 8, privileged write enable.</description>
2905                <bitRange>[3:3]</bitRange>
2906                <access>read-write</access>
2907              </field>
2908              <field>
2909                <name>PC8_NS</name>
2910                <description>Protection context 8, non-secure.</description>
2911                <bitRange>[4:4]</bitRange>
2912                <access>read-write</access>
2913              </field>
2914              <field>
2915                <name>PC9_UR</name>
2916                <description>Protection context 9, user read enable.</description>
2917                <bitRange>[8:8]</bitRange>
2918                <access>read-only</access>
2919              </field>
2920              <field>
2921                <name>PC9_UW</name>
2922                <description>Protection context 9, user write enable.</description>
2923                <bitRange>[9:9]</bitRange>
2924                <access>read-write</access>
2925              </field>
2926              <field>
2927                <name>PC9_PR</name>
2928                <description>Protection context 9, privileged read enable.</description>
2929                <bitRange>[10:10]</bitRange>
2930                <access>read-only</access>
2931              </field>
2932              <field>
2933                <name>PC9_PW</name>
2934                <description>Protection context 9, privileged write enable.</description>
2935                <bitRange>[11:11]</bitRange>
2936                <access>read-write</access>
2937              </field>
2938              <field>
2939                <name>PC9_NS</name>
2940                <description>Protection context 9, non-secure.</description>
2941                <bitRange>[12:12]</bitRange>
2942                <access>read-write</access>
2943              </field>
2944              <field>
2945                <name>PC10_UR</name>
2946                <description>Protection context 10, user read enable.</description>
2947                <bitRange>[16:16]</bitRange>
2948                <access>read-only</access>
2949              </field>
2950              <field>
2951                <name>PC10_UW</name>
2952                <description>Protection context 10, user write enable.</description>
2953                <bitRange>[17:17]</bitRange>
2954                <access>read-write</access>
2955              </field>
2956              <field>
2957                <name>PC10_PR</name>
2958                <description>Protection context 10, privileged read enable.</description>
2959                <bitRange>[18:18]</bitRange>
2960                <access>read-only</access>
2961              </field>
2962              <field>
2963                <name>PC10_PW</name>
2964                <description>Protection context 10, privileged write enable.</description>
2965                <bitRange>[19:19]</bitRange>
2966                <access>read-write</access>
2967              </field>
2968              <field>
2969                <name>PC10_NS</name>
2970                <description>Protection context 10, non-secure.</description>
2971                <bitRange>[20:20]</bitRange>
2972                <access>read-write</access>
2973              </field>
2974              <field>
2975                <name>PC11_UR</name>
2976                <description>Protection context 11, user read enable.</description>
2977                <bitRange>[24:24]</bitRange>
2978                <access>read-only</access>
2979              </field>
2980              <field>
2981                <name>PC11_UW</name>
2982                <description>Protection context 11, user write enable.</description>
2983                <bitRange>[25:25]</bitRange>
2984                <access>read-write</access>
2985              </field>
2986              <field>
2987                <name>PC11_PR</name>
2988                <description>Protection context 11, privileged read enable.</description>
2989                <bitRange>[26:26]</bitRange>
2990                <access>read-only</access>
2991              </field>
2992              <field>
2993                <name>PC11_PW</name>
2994                <description>Protection context 11, privileged write enable.</description>
2995                <bitRange>[27:27]</bitRange>
2996                <access>read-write</access>
2997              </field>
2998              <field>
2999                <name>PC11_NS</name>
3000                <description>Protection context 11, non-secure.</description>
3001                <bitRange>[28:28]</bitRange>
3002                <access>read-write</access>
3003              </field>
3004            </fields>
3005          </register>
3006          <register>
3007            <name>MS_ATT3</name>
3008            <description>Master attributes 3</description>
3009            <addressOffset>0x3C</addressOffset>
3010            <size>32</size>
3011            <access>read-write</access>
3012            <resetValue>0x1F1F1F1F</resetValue>
3013            <resetMask>0x1F1F1F1F</resetMask>
3014            <fields>
3015              <field>
3016                <name>PC12_UR</name>
3017                <description>Protection context 12, user read enable.</description>
3018                <bitRange>[0:0]</bitRange>
3019                <access>read-only</access>
3020              </field>
3021              <field>
3022                <name>PC12_UW</name>
3023                <description>Protection context 12, user write enable.</description>
3024                <bitRange>[1:1]</bitRange>
3025                <access>read-write</access>
3026              </field>
3027              <field>
3028                <name>PC12_PR</name>
3029                <description>Protection context 12, privileged read enable.</description>
3030                <bitRange>[2:2]</bitRange>
3031                <access>read-only</access>
3032              </field>
3033              <field>
3034                <name>PC12_PW</name>
3035                <description>Protection context 12, privileged write enable.</description>
3036                <bitRange>[3:3]</bitRange>
3037                <access>read-write</access>
3038              </field>
3039              <field>
3040                <name>PC12_NS</name>
3041                <description>Protection context 12, non-secure.</description>
3042                <bitRange>[4:4]</bitRange>
3043                <access>read-write</access>
3044              </field>
3045              <field>
3046                <name>PC13_UR</name>
3047                <description>Protection context 13, user read enable.</description>
3048                <bitRange>[8:8]</bitRange>
3049                <access>read-only</access>
3050              </field>
3051              <field>
3052                <name>PC13_UW</name>
3053                <description>Protection context 13, user write enable.</description>
3054                <bitRange>[9:9]</bitRange>
3055                <access>read-write</access>
3056              </field>
3057              <field>
3058                <name>PC13_PR</name>
3059                <description>Protection context 13, privileged read enable.</description>
3060                <bitRange>[10:10]</bitRange>
3061                <access>read-only</access>
3062              </field>
3063              <field>
3064                <name>PC13_PW</name>
3065                <description>Protection context 13, privileged write enable.</description>
3066                <bitRange>[11:11]</bitRange>
3067                <access>read-write</access>
3068              </field>
3069              <field>
3070                <name>PC13_NS</name>
3071                <description>Protection context 13, non-secure.</description>
3072                <bitRange>[12:12]</bitRange>
3073                <access>read-write</access>
3074              </field>
3075              <field>
3076                <name>PC14_UR</name>
3077                <description>Protection context 14, user read enable.</description>
3078                <bitRange>[16:16]</bitRange>
3079                <access>read-only</access>
3080              </field>
3081              <field>
3082                <name>PC14_UW</name>
3083                <description>Protection context 14, user write enable.</description>
3084                <bitRange>[17:17]</bitRange>
3085                <access>read-write</access>
3086              </field>
3087              <field>
3088                <name>PC14_PR</name>
3089                <description>Protection context 14, privileged read enable.</description>
3090                <bitRange>[18:18]</bitRange>
3091                <access>read-only</access>
3092              </field>
3093              <field>
3094                <name>PC14_PW</name>
3095                <description>Protection context 14, privileged write enable.</description>
3096                <bitRange>[19:19]</bitRange>
3097                <access>read-write</access>
3098              </field>
3099              <field>
3100                <name>PC14_NS</name>
3101                <description>Protection context 14, non-secure.</description>
3102                <bitRange>[20:20]</bitRange>
3103                <access>read-write</access>
3104              </field>
3105              <field>
3106                <name>PC15_UR</name>
3107                <description>Protection context 15, user read enable.</description>
3108                <bitRange>[24:24]</bitRange>
3109                <access>read-only</access>
3110              </field>
3111              <field>
3112                <name>PC15_UW</name>
3113                <description>Protection context 15, user write enable.</description>
3114                <bitRange>[25:25]</bitRange>
3115                <access>read-write</access>
3116              </field>
3117              <field>
3118                <name>PC15_PR</name>
3119                <description>Protection context 15, privileged read enable.</description>
3120                <bitRange>[26:26]</bitRange>
3121                <access>read-only</access>
3122              </field>
3123              <field>
3124                <name>PC15_PW</name>
3125                <description>Protection context 15, privileged write enable.</description>
3126                <bitRange>[27:27]</bitRange>
3127                <access>read-write</access>
3128              </field>
3129              <field>
3130                <name>PC15_NS</name>
3131                <description>Protection context 15, non-secure.</description>
3132                <bitRange>[28:28]</bitRange>
3133                <access>read-write</access>
3134              </field>
3135            </fields>
3136          </register>
3137        </cluster>
3138      </registers>
3139    </peripheral>
3140    <peripheral>
3141      <name>CRYPTO</name>
3142      <description>Cryptography component</description>
3143      <baseAddress>0x40100000</baseAddress>
3144      <addressBlock>
3145        <offset>0</offset>
3146        <size>65536</size>
3147        <usage>registers</usage>
3148      </addressBlock>
3149      <registers>
3150        <register>
3151          <name>CTL</name>
3152          <description>Control</description>
3153          <addressOffset>0x0</addressOffset>
3154          <size>32</size>
3155          <access>read-write</access>
3156          <resetValue>0x10002</resetValue>
3157          <resetMask>0x800300F3</resetMask>
3158          <fields>
3159            <field>
3160              <name>P</name>
3161              <description>User/privileged access control:
3162'0': user mode.
3163'1': privileged mode.
3164
3165This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data.
3166
3167All IP master transactions use the P field for the user/privileged access control ('hprot[1]').</description>
3168              <bitRange>[0:0]</bitRange>
3169              <access>read-write</access>
3170            </field>
3171            <field>
3172              <name>NS</name>
3173              <description>Secure/on-secure access control:
3174'0': secure.
3175'1': non-secure.
3176
3177This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data.
3178
3179All IP master transactions use the NS field for the secure/non-secure access control ('hprot[4]').</description>
3180              <bitRange>[1:1]</bitRange>
3181              <access>read-write</access>
3182            </field>
3183            <field>
3184              <name>PC</name>
3185              <description>Protection context.
3186
3187This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data.
3188
3189All IP master transactions use the PC field for the protection context. There is one exception: the LOAD_DEV_KEY instruction IP master transactions are always performed with protection context '0'.</description>
3190              <bitRange>[7:4]</bitRange>
3191              <access>read-write</access>
3192            </field>
3193            <field>
3194              <name>ECC_EN</name>
3195              <description>Enable ECC checking:
3196'0': Disabled.
3197'1': Enabled.</description>
3198              <bitRange>[16:16]</bitRange>
3199              <access>read-write</access>
3200            </field>
3201            <field>
3202              <name>ECC_INJ_EN</name>
3203              <description>Enable parity injection for SRAM.
3204When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM.</description>
3205              <bitRange>[17:17]</bitRange>
3206              <access>read-write</access>
3207            </field>
3208            <field>
3209              <name>ENABLED</name>
3210              <description>IP enable:
3211'0': Disabled. All non-retention registers (command and status registers, instruct FIFO, internal component state machines) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled.
3212'1': Enabled. When the  IP is enabled, the IP register buffer is set to '0'.</description>
3213              <bitRange>[31:31]</bitRange>
3214              <access>read-write</access>
3215              <enumeratedValues>
3216                <enumeratedValue>
3217                  <name>DISABLED</name>
3218                  <description>N/A</description>
3219                  <value>0</value>
3220                </enumeratedValue>
3221                <enumeratedValue>
3222                  <name>ENABLED</name>
3223                  <description>N/A</description>
3224                  <value>1</value>
3225                </enumeratedValue>
3226              </enumeratedValues>
3227            </field>
3228          </fields>
3229        </register>
3230        <register>
3231          <name>RAM_PWR_CTL</name>
3232          <description>SRAM power control</description>
3233          <addressOffset>0x8</addressOffset>
3234          <size>32</size>
3235          <access>read-write</access>
3236          <resetValue>0x3</resetValue>
3237          <resetMask>0x3</resetMask>
3238          <fields>
3239            <field>
3240              <name>PWR_MODE</name>
3241              <description>Set power mode for memory buffer SRAM.</description>
3242              <bitRange>[1:0]</bitRange>
3243              <access>read-write</access>
3244              <enumeratedValues>
3245                <enumeratedValue>
3246                  <name>OFF</name>
3247                  <description>See CM4_PWR_CTL</description>
3248                  <value>0</value>
3249                </enumeratedValue>
3250                <enumeratedValue>
3251                  <name>RSVD</name>
3252                  <description>undefined</description>
3253                  <value>1</value>
3254                </enumeratedValue>
3255                <enumeratedValue>
3256                  <name>RETAINED</name>
3257                  <description>See CM4_PWR_CTL</description>
3258                  <value>2</value>
3259                </enumeratedValue>
3260                <enumeratedValue>
3261                  <name>ENABLED</name>
3262                  <description>See CM4_PWR_CTL</description>
3263                  <value>3</value>
3264                </enumeratedValue>
3265              </enumeratedValues>
3266            </field>
3267          </fields>
3268        </register>
3269        <register>
3270          <name>RAM_PWR_DELAY_CTL</name>
3271          <description>SRAM power delay control</description>
3272          <addressOffset>0xC</addressOffset>
3273          <size>32</size>
3274          <access>read-write</access>
3275          <resetValue>0x96</resetValue>
3276          <resetMask>0x3FF</resetMask>
3277          <fields>
3278            <field>
3279              <name>UP</name>
3280              <description>Number clock cycles delay needed after power domain power up</description>
3281              <bitRange>[9:0]</bitRange>
3282              <access>read-write</access>
3283            </field>
3284          </fields>
3285        </register>
3286        <register>
3287          <name>ECC_CTL</name>
3288          <description>ECC control</description>
3289          <addressOffset>0x10</addressOffset>
3290          <size>32</size>
3291          <access>read-write</access>
3292          <resetValue>0x0</resetValue>
3293          <resetMask>0xFE001FFF</resetMask>
3294          <fields>
3295            <field>
3296              <name>WORD_ADDR</name>
3297              <description>Specifies the word address where the parity is injected.
3298- On a 32-bit write access to this SRAM address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected.</description>
3299              <bitRange>[12:0]</bitRange>
3300              <access>read-write</access>
3301            </field>
3302            <field>
3303              <name>PARITY</name>
3304              <description>ECC parity to use for ECC error injection at address WORD_ADDR.</description>
3305              <bitRange>[31:25]</bitRange>
3306              <access>read-write</access>
3307            </field>
3308          </fields>
3309        </register>
3310        <register>
3311          <name>ERROR_STATUS0</name>
3312          <description>Error status 0</description>
3313          <addressOffset>0x20</addressOffset>
3314          <size>32</size>
3315          <access>read-only</access>
3316          <resetValue>0x0</resetValue>
3317          <resetMask>0x0</resetMask>
3318          <fields>
3319            <field>
3320              <name>DATA32</name>
3321              <description>Specifies error description information.
3322- For INSTR_OPC_ERROR/ INSTR_CC_ERROR/ INSTR_DEV_KEY_ERROR:
3323  - Violating instruction (from instruction FIFO).
3324- For BUS_ERROR:
3325  - Violating transfer, address.</description>
3326              <bitRange>[31:0]</bitRange>
3327              <access>read-only</access>
3328            </field>
3329          </fields>
3330        </register>
3331        <register>
3332          <name>ERROR_STATUS1</name>
3333          <description>Error status 1</description>
3334          <addressOffset>0x24</addressOffset>
3335          <size>32</size>
3336          <access>read-write</access>
3337          <resetValue>0x0</resetValue>
3338          <resetMask>0x80000000</resetMask>
3339          <fields>
3340            <field>
3341              <name>DATA24</name>
3342              <description>Specifies error description information.
3343- For BUS_ERROR:
3344  - Violating transfer, read attribute (DATA[0]).
3345  - Violating transfer, size attribute (DATA[5:4]). '0': 8-bit transfer, '1': 16 bits transfer, '2': 32-bit transfer.</description>
3346              <bitRange>[23:0]</bitRange>
3347              <access>read-only</access>
3348            </field>
3349            <field>
3350              <name>IDX</name>
3351              <description>Error source:
3352'0': INSTR_OPC_ERROR (instruction FIFO decoder error).
3353'1': INSTR_CC_ERROR (instruction FIFO decoder, VU CC error).
3354'2': BUS_ERROR (bus master interface AHB-Lite bus error).
3355'3': TR_AP_DETECT_ERROR.
3356'4': TR_RC_DETECT_ERROR.
3357'5': INSTR_DEV_KEY_ERROR.
3358'6'-'7': Undefined.</description>
3359              <bitRange>[26:24]</bitRange>
3360              <access>read-only</access>
3361            </field>
3362            <field>
3363              <name>VALID</name>
3364              <description>Specifies if ERROR_STATUS0 and ERROR_STATUS1 specify valid error information. No new error information is captured as long as VALID is '1'; i.e. the error information of the first detected error is NOT overwritten.</description>
3365              <bitRange>[31:31]</bitRange>
3366              <access>read-write</access>
3367            </field>
3368          </fields>
3369        </register>
3370        <register>
3371          <name>INTR</name>
3372          <description>Interrupt register</description>
3373          <addressOffset>0x100</addressOffset>
3374          <size>32</size>
3375          <access>read-write</access>
3376          <resetValue>0x0</resetValue>
3377          <resetMask>0x3F001F</resetMask>
3378          <fields>
3379            <field>
3380              <name>INSTR_FF_LEVEL</name>
3381              <description>This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO event is activated.</description>
3382              <bitRange>[0:0]</bitRange>
3383              <access>read-write</access>
3384            </field>
3385            <field>
3386              <name>INSTR_FF_OVERFLOW</name>
3387              <description>This interrupt cause is activated (HW sets the field to '1') when the instruction FIFO overflows (an attempt is made to write to a full FIFO).</description>
3388              <bitRange>[1:1]</bitRange>
3389              <access>read-write</access>
3390            </field>
3391            <field>
3392              <name>TR_INITIALIZED</name>
3393              <description>This interrupt cause is activated (HW sets the field to '1') when the true random number generator is initialized.</description>
3394              <bitRange>[2:2]</bitRange>
3395              <access>read-write</access>
3396            </field>
3397            <field>
3398              <name>TR_DATA_AVAILABLE</name>
3399              <description>This interrupt cause is activated (HW sets the field to '1') when the true random number generator has generated a data value of the specified bit size.</description>
3400              <bitRange>[3:3]</bitRange>
3401              <access>read-write</access>
3402            </field>
3403            <field>
3404              <name>PR_DATA_AVAILABLE</name>
3405              <description>This interrupt cause is activated (HW sets the field to '1') when the pseudo random number generator has generated a data value.</description>
3406              <bitRange>[4:4]</bitRange>
3407              <access>read-write</access>
3408            </field>
3409            <field>
3410              <name>INSTR_OPC_ERROR</name>
3411              <description>This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined operation code (opcode).
3412
3413When the interrupt cause is activated, HW sets INSTR_FF_CTL.CLEAR to '1'.</description>
3414              <bitRange>[16:16]</bitRange>
3415              <access>read-write</access>
3416            </field>
3417            <field>
3418              <name>INSTR_CC_ERROR</name>
3419              <description>This interrupt cause is activated (HW sets the field to '1') when the instruction decoder encounters an instruction with a non-defined condition code. This error is only generated for VU instructions.
3420
3421When the interrupt cause is activated, HW sets INSTR_FF_CTL.CLEAR to '1'.</description>
3422              <bitRange>[17:17]</bitRange>
3423              <access>read-write</access>
3424            </field>
3425            <field>
3426              <name>BUS_ERROR</name>
3427              <description>This interrupt cause is activated (HW sets the field to '1') when a AHB-Lite bus error is observed on the AHB-Lite master interface.
3428
3429When the interrupt cause is activated, HW sets INSTR_FF_CTL.CLEAR to '1'.</description>
3430              <bitRange>[18:18]</bitRange>
3431              <access>read-write</access>
3432            </field>
3433            <field>
3434              <name>TR_AP_DETECT_ERROR</name>
3435              <description>This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a repetition of a specific bit value.</description>
3436              <bitRange>[19:19]</bitRange>
3437              <access>read-write</access>
3438            </field>
3439            <field>
3440              <name>TR_RC_DETECT_ERROR</name>
3441              <description>This interrupt cause is activated (HW sets the field to '1') when the true random number generator monitor adaptive proportion test detects a disproportionate occurrence of a specific bit value.</description>
3442              <bitRange>[20:20]</bitRange>
3443              <access>read-write</access>
3444            </field>
3445            <field>
3446              <name>INSTR_DEV_KEY_ERROR</name>
3447              <description>This interrupt cause is activated (HW sets the field to '1') when the LOAD_DEV_KEY instruction tries to load a device key whose DEV_KEY_ADDR_CTL.VALID or DEV_KEY_CTL.ALLOWED is set to '0'.</description>
3448              <bitRange>[21:21]</bitRange>
3449              <access>read-write</access>
3450            </field>
3451          </fields>
3452        </register>
3453        <register>
3454          <name>INTR_SET</name>
3455          <description>Interrupt set register</description>
3456          <addressOffset>0x104</addressOffset>
3457          <size>32</size>
3458          <access>read-write</access>
3459          <resetValue>0x0</resetValue>
3460          <resetMask>0x3F001F</resetMask>
3461          <fields>
3462            <field>
3463              <name>INSTR_FF_LEVEL</name>
3464              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3465              <bitRange>[0:0]</bitRange>
3466              <access>read-write</access>
3467            </field>
3468            <field>
3469              <name>INSTR_FF_OVERFLOW</name>
3470              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3471              <bitRange>[1:1]</bitRange>
3472              <access>read-write</access>
3473            </field>
3474            <field>
3475              <name>TR_INITIALIZED</name>
3476              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3477              <bitRange>[2:2]</bitRange>
3478              <access>read-write</access>
3479            </field>
3480            <field>
3481              <name>TR_DATA_AVAILABLE</name>
3482              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3483              <bitRange>[3:3]</bitRange>
3484              <access>read-write</access>
3485            </field>
3486            <field>
3487              <name>PR_DATA_AVAILABLE</name>
3488              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3489              <bitRange>[4:4]</bitRange>
3490              <access>read-write</access>
3491            </field>
3492            <field>
3493              <name>INSTR_OPC_ERROR</name>
3494              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3495              <bitRange>[16:16]</bitRange>
3496              <access>read-write</access>
3497            </field>
3498            <field>
3499              <name>INSTR_CC_ERROR</name>
3500              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3501              <bitRange>[17:17]</bitRange>
3502              <access>read-write</access>
3503            </field>
3504            <field>
3505              <name>BUS_ERROR</name>
3506              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3507              <bitRange>[18:18]</bitRange>
3508              <access>read-write</access>
3509            </field>
3510            <field>
3511              <name>TR_AP_DETECT_ERROR</name>
3512              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3513              <bitRange>[19:19]</bitRange>
3514              <access>read-write</access>
3515            </field>
3516            <field>
3517              <name>TR_RC_DETECT_ERROR</name>
3518              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3519              <bitRange>[20:20]</bitRange>
3520              <access>read-write</access>
3521            </field>
3522            <field>
3523              <name>INSTR_DEV_KEY_ERROR</name>
3524              <description>SW writes a '1' to this field to set the corresponding field in interrupt request register.</description>
3525              <bitRange>[21:21]</bitRange>
3526              <access>read-write</access>
3527            </field>
3528          </fields>
3529        </register>
3530        <register>
3531          <name>INTR_MASK</name>
3532          <description>Interrupt mask register</description>
3533          <addressOffset>0x108</addressOffset>
3534          <size>32</size>
3535          <access>read-write</access>
3536          <resetValue>0x0</resetValue>
3537          <resetMask>0x3F001F</resetMask>
3538          <fields>
3539            <field>
3540              <name>INSTR_FF_LEVEL</name>
3541              <description>Mask bit for corresponding field in interrupt request register.</description>
3542              <bitRange>[0:0]</bitRange>
3543              <access>read-write</access>
3544            </field>
3545            <field>
3546              <name>INSTR_FF_OVERFLOW</name>
3547              <description>Mask bit for corresponding field in interrupt request register.</description>
3548              <bitRange>[1:1]</bitRange>
3549              <access>read-write</access>
3550            </field>
3551            <field>
3552              <name>TR_INITIALIZED</name>
3553              <description>Mask bit for corresponding field in interrupt request register.</description>
3554              <bitRange>[2:2]</bitRange>
3555              <access>read-write</access>
3556            </field>
3557            <field>
3558              <name>TR_DATA_AVAILABLE</name>
3559              <description>Mask bit for corresponding field in interrupt request register.</description>
3560              <bitRange>[3:3]</bitRange>
3561              <access>read-write</access>
3562            </field>
3563            <field>
3564              <name>PR_DATA_AVAILABLE</name>
3565              <description>Mask bit for corresponding field in interrupt request register.</description>
3566              <bitRange>[4:4]</bitRange>
3567              <access>read-write</access>
3568            </field>
3569            <field>
3570              <name>INSTR_OPC_ERROR</name>
3571              <description>Mask bit for corresponding field in interrupt request register.</description>
3572              <bitRange>[16:16]</bitRange>
3573              <access>read-write</access>
3574            </field>
3575            <field>
3576              <name>INSTR_CC_ERROR</name>
3577              <description>Mask bit for corresponding field in interrupt request register.</description>
3578              <bitRange>[17:17]</bitRange>
3579              <access>read-write</access>
3580            </field>
3581            <field>
3582              <name>BUS_ERROR</name>
3583              <description>Mask bit for corresponding field in interrupt request register.</description>
3584              <bitRange>[18:18]</bitRange>
3585              <access>read-write</access>
3586            </field>
3587            <field>
3588              <name>TR_AP_DETECT_ERROR</name>
3589              <description>Mask bit for corresponding field in interrupt request register.</description>
3590              <bitRange>[19:19]</bitRange>
3591              <access>read-write</access>
3592            </field>
3593            <field>
3594              <name>TR_RC_DETECT_ERROR</name>
3595              <description>Mask bit for corresponding field in interrupt request register.</description>
3596              <bitRange>[20:20]</bitRange>
3597              <access>read-write</access>
3598            </field>
3599            <field>
3600              <name>INSTR_DEV_KEY_ERROR</name>
3601              <description>Mask bit for corresponding field in interrupt request register.</description>
3602              <bitRange>[21:21]</bitRange>
3603              <access>read-write</access>
3604            </field>
3605          </fields>
3606        </register>
3607        <register>
3608          <name>INTR_MASKED</name>
3609          <description>Interrupt masked register</description>
3610          <addressOffset>0x10C</addressOffset>
3611          <size>32</size>
3612          <access>read-only</access>
3613          <resetValue>0x0</resetValue>
3614          <resetMask>0x3F001F</resetMask>
3615          <fields>
3616            <field>
3617              <name>INSTR_FF_LEVEL</name>
3618              <description>Logical and of corresponding request and mask bits.</description>
3619              <bitRange>[0:0]</bitRange>
3620              <access>read-only</access>
3621            </field>
3622            <field>
3623              <name>INSTR_FF_OVERFLOW</name>
3624              <description>Logical and of corresponding request and mask bits.</description>
3625              <bitRange>[1:1]</bitRange>
3626              <access>read-only</access>
3627            </field>
3628            <field>
3629              <name>TR_INITIALIZED</name>
3630              <description>Logical and of corresponding request and mask bits.</description>
3631              <bitRange>[2:2]</bitRange>
3632              <access>read-only</access>
3633            </field>
3634            <field>
3635              <name>TR_DATA_AVAILABLE</name>
3636              <description>Logical and of corresponding request and mask bits.</description>
3637              <bitRange>[3:3]</bitRange>
3638              <access>read-only</access>
3639            </field>
3640            <field>
3641              <name>PR_DATA_AVAILABLE</name>
3642              <description>Logical and of corresponding request and mask bits.</description>
3643              <bitRange>[4:4]</bitRange>
3644              <access>read-only</access>
3645            </field>
3646            <field>
3647              <name>INSTR_OPC_ERROR</name>
3648              <description>Logical and of corresponding request and mask bits.</description>
3649              <bitRange>[16:16]</bitRange>
3650              <access>read-only</access>
3651            </field>
3652            <field>
3653              <name>INSTR_CC_ERROR</name>
3654              <description>Logical and of corresponding request and mask bits.</description>
3655              <bitRange>[17:17]</bitRange>
3656              <access>read-only</access>
3657            </field>
3658            <field>
3659              <name>BUS_ERROR</name>
3660              <description>Logical and of corresponding request and mask bits.</description>
3661              <bitRange>[18:18]</bitRange>
3662              <access>read-only</access>
3663            </field>
3664            <field>
3665              <name>TR_AP_DETECT_ERROR</name>
3666              <description>Logical and of corresponding request and mask bits.</description>
3667              <bitRange>[19:19]</bitRange>
3668              <access>read-only</access>
3669            </field>
3670            <field>
3671              <name>TR_RC_DETECT_ERROR</name>
3672              <description>Logical and of corresponding request and mask bits.</description>
3673              <bitRange>[20:20]</bitRange>
3674              <access>read-only</access>
3675            </field>
3676            <field>
3677              <name>INSTR_DEV_KEY_ERROR</name>
3678              <description>Logical and of corresponding request and mask bits.</description>
3679              <bitRange>[21:21]</bitRange>
3680              <access>read-only</access>
3681            </field>
3682          </fields>
3683        </register>
3684        <register>
3685          <name>PR_LFSR_CTL0</name>
3686          <description>Pseudo random LFSR control 0</description>
3687          <addressOffset>0x200</addressOffset>
3688          <size>32</size>
3689          <access>read-write</access>
3690          <resetValue>0xD8959BC9</resetValue>
3691          <resetMask>0xFFFFFFFF</resetMask>
3692          <fields>
3693            <field>
3694              <name>LFSR32</name>
3695              <description>State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. This register needs to be initialized by SW. The initialization value should be different from '0'.
3696
3697The three PR_LFSR_CTL registers represents the state of a 32-bit, 31-bit and 29-bit LFSR. Individually, these LFSRs generate a pseudo random bit sequence that repeats itself after (2^32)-1, (2^31)-1 and (2^29)-1 bits. The numbers (2^32)-1, (2^31)-1 and (2^29)-1 are relatively prime (their greatest common denominator is '1'). The three bit sequence are combined (XOR'd) into a single bitstream to create a pseudo random bit sequence that repeats itself after ((2^32)-1) * ((2^31)-1) * ((2*29)-1) bits.
3698
3699The following polynomials are used:
3700- 32-bit irreducible polynomial: x^32+x^30+x^26+x^25+1.
3701- 31-bit irreducible polynomial: x^31+x^28+1.
3702- 29-bit irreducible polynomial: x^29+x^27+1.</description>
3703              <bitRange>[31:0]</bitRange>
3704              <access>read-write</access>
3705            </field>
3706          </fields>
3707        </register>
3708        <register>
3709          <name>PR_LFSR_CTL1</name>
3710          <description>Pseudo random LFSR control 1</description>
3711          <addressOffset>0x204</addressOffset>
3712          <size>32</size>
3713          <access>read-write</access>
3714          <resetValue>0x2BB911F8</resetValue>
3715          <resetMask>0x7FFFFFFF</resetMask>
3716          <fields>
3717            <field>
3718              <name>LFSR31</name>
3719              <description>State of a 31-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0.</description>
3720              <bitRange>[30:0]</bitRange>
3721              <access>read-write</access>
3722            </field>
3723          </fields>
3724        </register>
3725        <register>
3726          <name>PR_LFSR_CTL2</name>
3727          <description>Pseudo random LFSR control 2</description>
3728          <addressOffset>0x208</addressOffset>
3729          <size>32</size>
3730          <access>read-write</access>
3731          <resetValue>0x60C31B7</resetValue>
3732          <resetMask>0x1FFFFFFF</resetMask>
3733          <fields>
3734            <field>
3735              <name>LFSR29</name>
3736              <description>State of a 29-bit Linear Feedback Shift Registers (LFSR) that is used to generate a pseudo random bit sequence. See PR_LFSR_CTL0.</description>
3737              <bitRange>[28:0]</bitRange>
3738              <access>read-write</access>
3739            </field>
3740          </fields>
3741        </register>
3742        <register>
3743          <name>PR_MAX_CTL</name>
3744          <description>Pseudo random maximum control</description>
3745          <addressOffset>0x20C</addressOffset>
3746          <size>32</size>
3747          <access>read-write</access>
3748          <resetValue>0xFFFFFFFF</resetValue>
3749          <resetMask>0xFFFFFFFF</resetMask>
3750          <fields>
3751            <field>
3752              <name>DATA32</name>
3753              <description>Maximum value of to be generated random number</description>
3754              <bitRange>[31:0]</bitRange>
3755              <access>read-write</access>
3756            </field>
3757          </fields>
3758        </register>
3759        <register>
3760          <name>PR_CMD</name>
3761          <description>Pseudo random command</description>
3762          <addressOffset>0x210</addressOffset>
3763          <size>32</size>
3764          <access>read-write</access>
3765          <resetValue>0x0</resetValue>
3766          <resetMask>0x1</resetMask>
3767          <fields>
3768            <field>
3769              <name>START</name>
3770              <description>Pseudo random command. On a generated number, HW sets this field to '0' and sets INTR.PR_DATA_AVAILABLE to '1.</description>
3771              <bitRange>[0:0]</bitRange>
3772              <access>read-write</access>
3773            </field>
3774          </fields>
3775        </register>
3776        <register>
3777          <name>PR_RESULT</name>
3778          <description>Pseudo random result</description>
3779          <addressOffset>0x218</addressOffset>
3780          <size>32</size>
3781          <access>read-write</access>
3782          <resetValue>0x0</resetValue>
3783          <resetMask>0xFFFFFFFF</resetMask>
3784          <fields>
3785            <field>
3786              <name>DATA32</name>
3787              <description>Result of a pseudo random number generation operation. The resulting value DATA is in the range [0, PR_MAX_CTL.DATA32]. The PR_DATA_AVAILABLE interrupt cause is activated when the number is generated.
3788
3789Note that SW can write this field. This functionality can be used prevent information leakage.</description>
3790              <bitRange>[31:0]</bitRange>
3791              <access>read-write</access>
3792            </field>
3793          </fields>
3794        </register>
3795        <register>
3796          <name>TR_CTL0</name>
3797          <description>True random control 0</description>
3798          <addressOffset>0x280</addressOffset>
3799          <size>32</size>
3800          <access>read-write</access>
3801          <resetValue>0x30000</resetValue>
3802          <resetMask>0x31FFFFFF</resetMask>
3803          <fields>
3804            <field>
3805              <name>SAMPLE_CLOCK_DIV</name>
3806              <description>Specifies the clock divider that is used to sample oscillator data. This clock divider is wrt. 'clk_sys'.
3807'0': sample clock is 'clk_sys'.
3808'1': sample clock is 'clk_sys'/2.
3809...
3810'255': sample clock is 'clk_sys'/256.</description>
3811              <bitRange>[7:0]</bitRange>
3812              <access>read-write</access>
3813            </field>
3814            <field>
3815              <name>RED_CLOCK_DIV</name>
3816              <description>Specifies the clock divider that is used to produce reduced bits.
3817'0': 1 reduced bit is produced for each sample.
3818'1': 1 reduced bit is produced for each 2 samples.
3819...
3820'255': 1 reduced bit is produced for each 256 samples.
3821
3822The reduced bits are considered random bits and shifted into TR_RESULT0.DATA32.</description>
3823              <bitRange>[15:8]</bitRange>
3824              <access>read-write</access>
3825            </field>
3826            <field>
3827              <name>INIT_DELAY</name>
3828              <description>Specifies an initialization delay: number of removed/dropped samples before reduced bits are generated. This field should be programmed in the range [1, 255]. After starting the oscillators, at least the first 2 samples should be removed/dropped to clear the state of internal synchronizers. In addition, it is advised to drop at least the second 2 samples from the oscillators (to circumvent the semi-predictable oscillator startup behavior). This result in the default field value of '3'. Field encoding is as follows:
3829'0': 1 sample is dropped.
3830'1': 2 samples are dropped.
3831...
3832'255': 256 samples are dropped.
3833
3834The TR_INITIALIZED interrupt cause is set to '1', when the initialization delay is passed.</description>
3835              <bitRange>[23:16]</bitRange>
3836              <access>read-write</access>
3837            </field>
3838            <field>
3839              <name>VON_NEUMANN_CORR</name>
3840              <description>Specifies if the 'von Neumann corrector' is disabled or enabled:
3841'0': disabled.
3842'1': enabled.
3843The 'von Neumann corrector' post-processes the reduced bits to remove a '0' or '1' bias. The corrector operates on reduced bit pairs ('oldest bit, newest bit'):
3844'00': no bit is produced.
3845'01': '0' bit is produced (oldest bit).
3846'10': '1' bit is produced (oldest bit).
3847'11': no bit is produced.
3848Note that the corrector produces bits at a random pace and at a frequency that is 1/4 of the reduced bit frequency (reduced bits are processed in pairs, and half of the pairs do NOT produce a bit).</description>
3849              <bitRange>[24:24]</bitRange>
3850              <access>read-write</access>
3851            </field>
3852            <field>
3853              <name>STOP_ON_AP_DETECT</name>
3854              <description>Specifies if TRNG functionality is stopped on an adaptive proportion test detection (when HW sets INTR.TR_AP_DETECT to '1'):
3855'0': Functionality is NOT stopped.
3856'1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW).</description>
3857              <bitRange>[28:28]</bitRange>
3858              <access>read-write</access>
3859            </field>
3860            <field>
3861              <name>STOP_ON_RC_DETECT</name>
3862              <description>Specifies if TRNG functionality is stopped on a repetition count test detection (when HW sets INTR.TR_RC_DETECT to '1'):
3863'0': Functionality is NOT stopped.
3864'1': Functionality is stopped (TR_CTL1 fields are set to '0' by HW).</description>
3865              <bitRange>[29:29]</bitRange>
3866              <access>read-write</access>
3867            </field>
3868          </fields>
3869        </register>
3870        <register>
3871          <name>TR_CTL1</name>
3872          <description>True random control 1</description>
3873          <addressOffset>0x284</addressOffset>
3874          <size>32</size>
3875          <access>read-write</access>
3876          <resetValue>0x0</resetValue>
3877          <resetMask>0x3F</resetMask>
3878          <fields>
3879            <field>
3880              <name>RO11_EN</name>
3881              <description>FW sets this field to '1' to enable the ring oscillator with 11 inverters.</description>
3882              <bitRange>[0:0]</bitRange>
3883              <access>read-write</access>
3884            </field>
3885            <field>
3886              <name>RO15_EN</name>
3887              <description>FW sets this field to '1' to enable the ring oscillator with 15 inverters.</description>
3888              <bitRange>[1:1]</bitRange>
3889              <access>read-write</access>
3890            </field>
3891            <field>
3892              <name>GARO15_EN</name>
3893              <description>FW sets this field to '1' to enable the fixed Galois ring oscillator with 15 inverters.</description>
3894              <bitRange>[2:2]</bitRange>
3895              <access>read-write</access>
3896            </field>
3897            <field>
3898              <name>GARO31_EN</name>
3899              <description>FW sets this field to '1' to enable the programmable Galois ring oscillator with up to 31 inverters. The TR_GARO_CTL register specifies the programmable polynomial.</description>
3900              <bitRange>[3:3]</bitRange>
3901              <access>read-write</access>
3902            </field>
3903            <field>
3904              <name>FIRO15_EN</name>
3905              <description>FW sets this field to '1' to enable the fixed Fibonacci ring oscillator with 15 inverters.</description>
3906              <bitRange>[4:4]</bitRange>
3907              <access>read-write</access>
3908            </field>
3909            <field>
3910              <name>FIRO31_EN</name>
3911              <description>FW sets this field to '1' to enable the programmable Fibonacci ring oscillator with up to 31 inverters. The TR_FIRO_CTL register specifies the programmable polynomial.</description>
3912              <bitRange>[5:5]</bitRange>
3913              <access>read-write</access>
3914            </field>
3915          </fields>
3916        </register>
3917        <register>
3918          <name>TR_CTL2</name>
3919          <description>True random control 2</description>
3920          <addressOffset>0x288</addressOffset>
3921          <size>32</size>
3922          <access>read-write</access>
3923          <resetValue>0x0</resetValue>
3924          <resetMask>0x3F</resetMask>
3925          <fields>
3926            <field>
3927              <name>SIZE</name>
3928              <description>Bit size of generated random number in TR_RESULT. Legal range is in [0, 32].</description>
3929              <bitRange>[5:0]</bitRange>
3930              <access>read-write</access>
3931            </field>
3932          </fields>
3933        </register>
3934        <register>
3935          <name>TR_STATUS</name>
3936          <description>True random status</description>
3937          <addressOffset>0x28C</addressOffset>
3938          <size>32</size>
3939          <access>read-only</access>
3940          <resetValue>0x0</resetValue>
3941          <resetMask>0x1</resetMask>
3942          <fields>
3943            <field>
3944              <name>INITIALIZED</name>
3945              <description>Reflects the state of the true random number generator:
3946'0': Not initialized (TR_CTL0.INIT_DELAY has NOT passed).
3947'1': Initialized (TR_CTL0.INIT_DELAY has passed).</description>
3948              <bitRange>[0:0]</bitRange>
3949              <access>read-only</access>
3950            </field>
3951          </fields>
3952        </register>
3953        <register>
3954          <name>TR_CMD</name>
3955          <description>True random command</description>
3956          <addressOffset>0x290</addressOffset>
3957          <size>32</size>
3958          <access>read-write</access>
3959          <resetValue>0x0</resetValue>
3960          <resetMask>0x1</resetMask>
3961          <fields>
3962            <field>
3963              <name>START</name>
3964              <description>True random command. On completion of the command, HW sets this field to '0' and sets INTR.TR_DATA_AVAILABLE to '1 when:
3965- A random number is generated in TR_RESULT.
3966- All ring oscillators are off (per TR_CTL1).
3967- A repetition count (RC) or adaptive proportion (AP) error is detected during the random number generation (INTR.TR_RC/AP_DETECT_ERROR).
3968
3969Note: On completion of the command, SW should check TR_CTL1 and INTR.TR_RC/AP_DETECT_ERROR to ensure that no unexpected error occurred during random number generation.</description>
3970              <bitRange>[0:0]</bitRange>
3971              <access>read-write</access>
3972            </field>
3973          </fields>
3974        </register>
3975        <register>
3976          <name>TR_RESULT</name>
3977          <description>True random result</description>
3978          <addressOffset>0x298</addressOffset>
3979          <size>32</size>
3980          <access>read-write</access>
3981          <resetValue>0x0</resetValue>
3982          <resetMask>0xFFFFFFFF</resetMask>
3983          <fields>
3984            <field>
3985              <name>DATA32</name>
3986              <description>Generated true random number. HW generates the number in the least significant bit positions (TR_CTL2.SIZE) of this field. The TR_DATA_AVAILABLE interrupt cause is activated when the number is generated.
3987
3988Note that SW can write this field. This functionality can be used prevent information leakage.</description>
3989              <bitRange>[31:0]</bitRange>
3990              <access>read-write</access>
3991            </field>
3992          </fields>
3993        </register>
3994        <register>
3995          <name>TR_GARO_CTL</name>
3996          <description>True random GARO control</description>
3997          <addressOffset>0x2A0</addressOffset>
3998          <size>32</size>
3999          <access>read-write</access>
4000          <resetValue>0x0</resetValue>
4001          <resetMask>0x7FFFFFFF</resetMask>
4002          <fields>
4003            <field>
4004              <name>POLYNOMIAL31</name>
4005              <description>Polynomial for programmable Galois ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's.</description>
4006              <bitRange>[30:0]</bitRange>
4007              <access>read-write</access>
4008            </field>
4009          </fields>
4010        </register>
4011        <register>
4012          <name>TR_FIRO_CTL</name>
4013          <description>True random FIRO control</description>
4014          <addressOffset>0x2A4</addressOffset>
4015          <size>32</size>
4016          <access>read-write</access>
4017          <resetValue>0x0</resetValue>
4018          <resetMask>0x7FFFFFFF</resetMask>
4019          <fields>
4020            <field>
4021              <name>POLYNOMIAL31</name>
4022              <description>Polynomial for programmable Fibonacci ring oscillator. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned such that the more significant bits (bit 30 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's.</description>
4023              <bitRange>[30:0]</bitRange>
4024              <access>read-write</access>
4025            </field>
4026          </fields>
4027        </register>
4028        <register>
4029          <name>TR_MON_CTL</name>
4030          <description>True random monitor control</description>
4031          <addressOffset>0x2C0</addressOffset>
4032          <size>32</size>
4033          <access>read-write</access>
4034          <resetValue>0x2</resetValue>
4035          <resetMask>0x3</resetMask>
4036          <fields>
4037            <field>
4038              <name>BITSTREAM_SEL</name>
4039              <description>Selection of the bitstream:
4040'0': DAS bitstream.
4041'1': RED bitstream.
4042'2': TR bitstream.
4043'3': Undefined.</description>
4044              <bitRange>[1:0]</bitRange>
4045              <access>read-write</access>
4046            </field>
4047          </fields>
4048        </register>
4049        <register>
4050          <name>TR_MON_CMD</name>
4051          <description>True random monitor command</description>
4052          <addressOffset>0x2C8</addressOffset>
4053          <size>32</size>
4054          <access>read-write</access>
4055          <resetValue>0x0</resetValue>
4056          <resetMask>0x3</resetMask>
4057          <fields>
4058            <field>
4059              <name>START_AP</name>
4060              <description>Adaptive proportion (AP) test enable:
4061'0': Stopped.
4062'1': Started.
4063
4064On a AP detection, HW sets this field to '0' and sets INTR.TR_AP_DETECT to '1.</description>
4065              <bitRange>[0:0]</bitRange>
4066              <access>read-write</access>
4067            </field>
4068            <field>
4069              <name>START_RC</name>
4070              <description>Repetition count (RC) test enable:
4071'0': Disabled.
4072'1': Enabled.
4073
4074On a RC detection, HW sets this field to '0' and sets INTR.TR_RC_DETECT to '1.</description>
4075              <bitRange>[1:1]</bitRange>
4076              <access>read-write</access>
4077            </field>
4078          </fields>
4079        </register>
4080        <register>
4081          <name>TR_MON_RC_CTL</name>
4082          <description>True random monitor RC control</description>
4083          <addressOffset>0x2D0</addressOffset>
4084          <size>32</size>
4085          <access>read-write</access>
4086          <resetValue>0xFF</resetValue>
4087          <resetMask>0xFF</resetMask>
4088          <fields>
4089            <field>
4090              <name>CUTOFF_COUNT8</name>
4091              <description>Cutoff count (legal range is [1, 255]):
4092'0': Illegal.
4093'1': 1 repetition.
4094...
4095'255': 255 repetitions.</description>
4096              <bitRange>[7:0]</bitRange>
4097              <access>read-write</access>
4098            </field>
4099          </fields>
4100        </register>
4101        <register>
4102          <name>TR_MON_RC_STATUS0</name>
4103          <description>True random monitor RC status 0</description>
4104          <addressOffset>0x2D8</addressOffset>
4105          <size>32</size>
4106          <access>read-only</access>
4107          <resetValue>0x0</resetValue>
4108          <resetMask>0x1</resetMask>
4109          <fields>
4110            <field>
4111              <name>BIT</name>
4112              <description>Current active bit value:
4113'0': '0'.
4114'1': '1'.
4115
4116This field is only valid when TR_MON_RC_STATUS1.REP_COUNT is NOT equal to '0'.</description>
4117              <bitRange>[0:0]</bitRange>
4118              <access>read-only</access>
4119            </field>
4120          </fields>
4121        </register>
4122        <register>
4123          <name>TR_MON_RC_STATUS1</name>
4124          <description>True random monitor RC status 1</description>
4125          <addressOffset>0x2DC</addressOffset>
4126          <size>32</size>
4127          <access>read-only</access>
4128          <resetValue>0x0</resetValue>
4129          <resetMask>0xFF</resetMask>
4130          <fields>
4131            <field>
4132              <name>REP_COUNT</name>
4133              <description>Number of repetitions of the current active bit counter:
4134'0': 0 repetitions.
4135...
4136'255': 255 repetitions.</description>
4137              <bitRange>[7:0]</bitRange>
4138              <access>read-only</access>
4139            </field>
4140          </fields>
4141        </register>
4142        <register>
4143          <name>TR_MON_AP_CTL</name>
4144          <description>True random monitor AP control</description>
4145          <addressOffset>0x2E0</addressOffset>
4146          <size>32</size>
4147          <access>read-write</access>
4148          <resetValue>0xFFFFFFFF</resetValue>
4149          <resetMask>0xFFFFFFFF</resetMask>
4150          <fields>
4151            <field>
4152              <name>CUTOFF_COUNT16</name>
4153              <description>Cutoff count (legal range is [1, 65535]).
4154'0': Illegal.
4155'1': 1 occurrence.
4156...
4157'65535': 65535 occurrences.</description>
4158              <bitRange>[15:0]</bitRange>
4159              <access>read-write</access>
4160            </field>
4161            <field>
4162              <name>WINDOW_SIZE</name>
4163              <description>Window size (minus 1) :
4164'0': 1 bit.
4165...
4166'65535': 65536 bits.</description>
4167              <bitRange>[31:16]</bitRange>
4168              <access>read-write</access>
4169            </field>
4170          </fields>
4171        </register>
4172        <register>
4173          <name>TR_MON_AP_STATUS0</name>
4174          <description>True random monitor AP status 0</description>
4175          <addressOffset>0x2E8</addressOffset>
4176          <size>32</size>
4177          <access>read-only</access>
4178          <resetValue>0x0</resetValue>
4179          <resetMask>0x1</resetMask>
4180          <fields>
4181            <field>
4182              <name>BIT</name>
4183              <description>Current active bit value:
4184'0': '0'.
4185'1': '1'.
4186
4187This field is only valid when TR_MON_AP_STATUS1.OCC_COUNT is NOT equal to '0'.</description>
4188              <bitRange>[0:0]</bitRange>
4189              <access>read-only</access>
4190            </field>
4191          </fields>
4192        </register>
4193        <register>
4194          <name>TR_MON_AP_STATUS1</name>
4195          <description>True random monitor AP status 1</description>
4196          <addressOffset>0x2EC</addressOffset>
4197          <size>32</size>
4198          <access>read-only</access>
4199          <resetValue>0x0</resetValue>
4200          <resetMask>0xFFFFFFFF</resetMask>
4201          <fields>
4202            <field>
4203              <name>OCC_COUNT</name>
4204              <description>Number of occurrences of the current active bit counter:
4205'0': 0 occurrences
4206...
4207'65535': 65535 occurrences</description>
4208              <bitRange>[15:0]</bitRange>
4209              <access>read-only</access>
4210            </field>
4211            <field>
4212              <name>WINDOW_INDEX</name>
4213              <description>Counter to keep track of the current index in the window (counts from '0' to TR_MON_AP_CTL.WINDOW_SIZE to '0').</description>
4214              <bitRange>[31:16]</bitRange>
4215              <access>read-only</access>
4216            </field>
4217          </fields>
4218        </register>
4219        <register>
4220          <name>STATUS</name>
4221          <description>Status</description>
4222          <addressOffset>0x1004</addressOffset>
4223          <size>32</size>
4224          <access>read-only</access>
4225          <resetValue>0x0</resetValue>
4226          <resetMask>0x80000000</resetMask>
4227          <fields>
4228            <field>
4229              <name>BUSY</name>
4230              <description>Reflects the state of the IP:
4231'0': Idle/no busy.
4232'1': Busy:
4233  - Instruction is pending in the instruction FIFO.
4234  - Instruction is busy in a IP component (e.g. SHA1, SHA2, SHA3, DES, TDES, AES, CHACHA, ...).
4235  - Store FIFO is busy.
4236  - TR or PR command is busy.</description>
4237              <bitRange>[31:31]</bitRange>
4238              <access>read-only</access>
4239            </field>
4240          </fields>
4241        </register>
4242        <register>
4243          <name>INSTR_FF_CTL</name>
4244          <description>Instruction FIFO control</description>
4245          <addressOffset>0x1040</addressOffset>
4246          <size>32</size>
4247          <access>read-write</access>
4248          <resetValue>0x20000</resetValue>
4249          <resetMask>0x30007</resetMask>
4250          <fields>
4251            <field>
4252              <name>EVENT_LEVEL</name>
4253              <description>Event level. When the number of entries in the instruction FIFO is less than the amount of this field, an event is generated:
4254- 'event' = INSTR_FF_STATUS.USED &lt; EVENT_LEVEL.</description>
4255              <bitRange>[2:0]</bitRange>
4256              <access>read-write</access>
4257            </field>
4258            <field>
4259              <name>CLEAR</name>
4260              <description>When '1', the instruction FIFO is cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.
4261
4262HW sets this field to '1' on when a INSTR_OPC_ERROR, INSTR_CC_ERROR or BUS_ERROR interrupt cause is activated.</description>
4263              <bitRange>[16:16]</bitRange>
4264              <access>read-write</access>
4265            </field>
4266            <field>
4267              <name>BLOCK</name>
4268              <description>This field specifies the behavior when an instruction is written to a full FIFO (INSTR_FIFO_WR MMIO register):
4269'0': The write is ignored/dropped and the INTR.INSTR_FF_OVERFLOW interrupt cause is set to '1'.
4270'1': The write is blocked, resulting in AHB-Lite wait states and the INTR.INSTR_FF_OVERFLOW interrupt cause is set to '1' (this cause may be masked out). The instruction is written to the FIFO as soon as a FIFO entry becomes available. The maximum time is roughly the time of the execution of the slowest/longest instruction. Note that this setting may 'lock up' /stall the CPU. When the CPU is 'locked up'/stalled it can not respond to any system interrupts. As a result, the interrupt latency is increased. Note that this may not be an issue if the associated CPU is only performing cryptography functionality, e.g. the CM0+ during boot time.</description>
4271              <bitRange>[17:17]</bitRange>
4272              <access>read-write</access>
4273            </field>
4274          </fields>
4275        </register>
4276        <register>
4277          <name>INSTR_FF_STATUS</name>
4278          <description>Instruction FIFO status</description>
4279          <addressOffset>0x1044</addressOffset>
4280          <size>32</size>
4281          <access>read-only</access>
4282          <resetValue>0x0</resetValue>
4283          <resetMask>0x1000F</resetMask>
4284          <fields>
4285            <field>
4286              <name>USED</name>
4287              <description>Number of instructions in the instruction FIFO. The value of this field ranges from 0 to 8.</description>
4288              <bitRange>[3:0]</bitRange>
4289              <access>read-only</access>
4290            </field>
4291            <field>
4292              <name>EVENT</name>
4293              <description>Instruction FIFO  event.</description>
4294              <bitRange>[16:16]</bitRange>
4295              <access>read-only</access>
4296            </field>
4297          </fields>
4298        </register>
4299        <register>
4300          <name>INSTR_FF_WR</name>
4301          <description>Instruction FIFO write</description>
4302          <addressOffset>0x1048</addressOffset>
4303          <size>32</size>
4304          <access>write-only</access>
4305          <resetValue>0x0</resetValue>
4306          <resetMask>0xFFFFFFFF</resetMask>
4307          <fields>
4308            <field>
4309              <name>DATA32</name>
4310              <description>Instruction or instruction operand data that is written to the instruction FIFO.</description>
4311              <bitRange>[31:0]</bitRange>
4312              <access>write-only</access>
4313            </field>
4314          </fields>
4315        </register>
4316        <register>
4317          <name>LOAD0_FF_STATUS</name>
4318          <description>Load 0 FIFO status</description>
4319          <addressOffset>0x10C0</addressOffset>
4320          <size>32</size>
4321          <access>read-only</access>
4322          <resetValue>0x0</resetValue>
4323          <resetMask>0x8000001F</resetMask>
4324          <fields>
4325            <field>
4326              <name>USED5</name>
4327              <description>Number of Bytes in the FIFO. The value of this field is in the range [0, 19].</description>
4328              <bitRange>[4:0]</bitRange>
4329              <access>read-only</access>
4330            </field>
4331            <field>
4332              <name>BUSY</name>
4333              <description>Reflects the state of the FIFO:
4334'0': FIFO load engine is idle and a new FIFO instruction can be accepted.
4335'1': FIFO load engine is busy and NO new FIFO instruction can be accepted.</description>
4336              <bitRange>[31:31]</bitRange>
4337              <access>read-only</access>
4338            </field>
4339          </fields>
4340        </register>
4341        <register>
4342          <name>LOAD1_FF_STATUS</name>
4343          <description>Load 1 FIFO status</description>
4344          <addressOffset>0x10D0</addressOffset>
4345          <size>32</size>
4346          <access>read-only</access>
4347          <resetValue>0x0</resetValue>
4348          <resetMask>0x8000001F</resetMask>
4349          <fields>
4350            <field>
4351              <name>USED5</name>
4352              <description>See LOAD1_FF_STATUS.USED.</description>
4353              <bitRange>[4:0]</bitRange>
4354              <access>read-only</access>
4355            </field>
4356            <field>
4357              <name>BUSY</name>
4358              <description>See LOAD1_FF_STATUS.BUSY.</description>
4359              <bitRange>[31:31]</bitRange>
4360              <access>read-only</access>
4361            </field>
4362          </fields>
4363        </register>
4364        <register>
4365          <name>STORE_FF_STATUS</name>
4366          <description>Store FIFO status</description>
4367          <addressOffset>0x10F0</addressOffset>
4368          <size>32</size>
4369          <access>read-only</access>
4370          <resetValue>0x0</resetValue>
4371          <resetMask>0x8000001F</resetMask>
4372          <fields>
4373            <field>
4374              <name>USED5</name>
4375              <description>Number of Bytes in the FIFO. The value of this field is in the range [0, 16].</description>
4376              <bitRange>[4:0]</bitRange>
4377              <access>read-only</access>
4378            </field>
4379            <field>
4380              <name>BUSY</name>
4381              <description>Reflects the state of the FIFO:
4382'0': FIFO store engine is idle and a new FIFO instruction can be accepted (USED is '0').
4383'1': FIFO store engine is busy and NO new FIFO instruction can be accepted.</description>
4384              <bitRange>[31:31]</bitRange>
4385              <access>read-only</access>
4386            </field>
4387          </fields>
4388        </register>
4389        <register>
4390          <name>AES_CTL</name>
4391          <description>AES control</description>
4392          <addressOffset>0x1100</addressOffset>
4393          <size>32</size>
4394          <access>read-write</access>
4395          <resetValue>0x0</resetValue>
4396          <resetMask>0x3</resetMask>
4397          <fields>
4398            <field>
4399              <name>KEY_SIZE</name>
4400              <description>AES key size:
4401'0': 128-bit key, 10 rounds AES (inverse) cipher operation.
4402'1': 192-bit key, 12 rounds AES (inverse) cipher operation.
4403'2': 256-bit key, 14 rounds AES (inverse) cipher operation.
4404'3': Undefined</description>
4405              <bitRange>[1:0]</bitRange>
4406              <access>read-write</access>
4407              <enumeratedValues>
4408                <enumeratedValue>
4409                  <name>AES128</name>
4410                  <description>N/A</description>
4411                  <value>0</value>
4412                </enumeratedValue>
4413                <enumeratedValue>
4414                  <name>AES192</name>
4415                  <description>N/A</description>
4416                  <value>1</value>
4417                </enumeratedValue>
4418                <enumeratedValue>
4419                  <name>AES256</name>
4420                  <description>N/A</description>
4421                  <value>2</value>
4422                </enumeratedValue>
4423              </enumeratedValues>
4424            </field>
4425          </fields>
4426        </register>
4427        <register>
4428          <name>RESULT</name>
4429          <description>Result</description>
4430          <addressOffset>0x1180</addressOffset>
4431          <size>32</size>
4432          <access>read-write</access>
4433          <resetValue>0x0</resetValue>
4434          <resetMask>0xFFFFFFFF</resetMask>
4435          <fields>
4436            <field>
4437              <name>DATA</name>
4438              <description>BLOCK_CMP operation (DATA[0]):
4439'0': source 0 equals source 1.
4440'1': source 0 does NOT equal source 1.
4441
4442CRC operation (DATA[31:0]). State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value.
4443
4444The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's.
4445
4446Note that SW can write this field. This functionality can be used prevent information leakage.</description>
4447              <bitRange>[31:0]</bitRange>
4448              <access>read-write</access>
4449            </field>
4450          </fields>
4451        </register>
4452        <register>
4453          <name>CRC_CTL</name>
4454          <description>CRC control</description>
4455          <addressOffset>0x1400</addressOffset>
4456          <size>32</size>
4457          <access>read-write</access>
4458          <resetValue>0x0</resetValue>
4459          <resetMask>0x101</resetMask>
4460          <fields>
4461            <field>
4462              <name>DATA_REVERSE</name>
4463              <description>Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):
4464'0': Most significant bit (bit 1) first.
4465'1': Least significant bit (bit 0) first.</description>
4466              <bitRange>[0:0]</bitRange>
4467              <access>read-write</access>
4468            </field>
4469            <field>
4470              <name>REM_REVERSE</name>
4471              <description>Specifies whether the remainder is bit reversed (reversal is performed after XORing):
4472'0': No.
4473'1': Yes.</description>
4474              <bitRange>[8:8]</bitRange>
4475              <access>read-write</access>
4476            </field>
4477          </fields>
4478        </register>
4479        <register>
4480          <name>CRC_DATA_CTL</name>
4481          <description>CRC data control</description>
4482          <addressOffset>0x1410</addressOffset>
4483          <size>32</size>
4484          <access>read-write</access>
4485          <resetValue>0x0</resetValue>
4486          <resetMask>0xFF</resetMask>
4487          <fields>
4488            <field>
4489              <name>DATA_XOR</name>
4490              <description>Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal.</description>
4491              <bitRange>[7:0]</bitRange>
4492              <access>read-write</access>
4493            </field>
4494          </fields>
4495        </register>
4496        <register>
4497          <name>CRC_POL_CTL</name>
4498          <description>CRC polynomial control</description>
4499          <addressOffset>0x1420</addressOffset>
4500          <size>32</size>
4501          <access>read-write</access>
4502          <resetValue>0x0</resetValue>
4503          <resetMask>0xFFFFFFFF</resetMask>
4504          <fields>
4505            <field>
4506              <name>POLYNOMIAL</name>
4507              <description>CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials:
4508- CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1).
4509- CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions).
4510- CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions).</description>
4511              <bitRange>[31:0]</bitRange>
4512              <access>read-write</access>
4513            </field>
4514          </fields>
4515        </register>
4516        <register>
4517          <name>CRC_REM_CTL</name>
4518          <description>CRC remainder control</description>
4519          <addressOffset>0x1440</addressOffset>
4520          <size>32</size>
4521          <access>read-write</access>
4522          <resetValue>0x0</resetValue>
4523          <resetMask>0xFFFFFFFF</resetMask>
4524          <fields>
4525            <field>
4526              <name>REM_XOR</name>
4527              <description>Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal.</description>
4528              <bitRange>[31:0]</bitRange>
4529              <access>read-write</access>
4530            </field>
4531          </fields>
4532        </register>
4533        <register>
4534          <name>CRC_REM_RESULT</name>
4535          <description>CRC remainder result</description>
4536          <addressOffset>0x1448</addressOffset>
4537          <size>32</size>
4538          <access>read-only</access>
4539          <resetValue>0x0</resetValue>
4540          <resetMask>0xFFFFFFFF</resetMask>
4541          <fields>
4542            <field>
4543              <name>REM</name>
4544              <description>Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:
4545'0': the more significant bits (bit 31 and down) contain the remainder.
4546'1': the less significant bits (bit 0 and up) contain the remainder.
4547
4548Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_REM_CTL0.REM_REVERSE and CRC_REM_CTL1.REM_XOR.</description>
4549              <bitRange>[31:0]</bitRange>
4550              <access>read-only</access>
4551            </field>
4552          </fields>
4553        </register>
4554        <register>
4555          <name>VU_CTL0</name>
4556          <description>Vector unit control 0</description>
4557          <addressOffset>0x1480</addressOffset>
4558          <size>32</size>
4559          <access>read-write</access>
4560          <resetValue>0x0</resetValue>
4561          <resetMask>0x1</resetMask>
4562          <fields>
4563            <field>
4564              <name>ALWAYS_EXECUTE</name>
4565              <description>Specifies if a conditional instruction is executed or not, when its condition code evaluates to false/'0'.
4566'0': The instruction is NOT executed. As a result, the instruction may be handled faster than when it is executed.
4567'1': The instruction is executed, but the execution result (including status field information) is not reflected in the IP. The instruction is handled just as fast as when it is executed.
4568
4569Note: a conditional instruction with a condition code that evaluates to false/'0' does not affect the architectural state: VU_STATUS fields, memory or register-file data.
4570
4571Note: Always execution is useful to prevent/complicate differential timing and differential power attacks.</description>
4572              <bitRange>[0:0]</bitRange>
4573              <access>read-write</access>
4574            </field>
4575          </fields>
4576        </register>
4577        <register>
4578          <name>VU_CTL1</name>
4579          <description>Vector unit control 1</description>
4580          <addressOffset>0x1484</addressOffset>
4581          <size>32</size>
4582          <access>read-write</access>
4583          <resetValue>0x0</resetValue>
4584          <resetMask>0xFFFFFF00</resetMask>
4585          <fields>
4586            <field>
4587              <name>ADDR24</name>
4588              <description>Specifies the memory address for the vector unit operand memory region. The register-file registers provide 13-bit word offsets within this memory region. Given ADDR[31:8], VU_VTL2.MASK[14:8] and a 13-bit word offset offset[14:2], a vector operand memory address VU_OPERAND_ADDR[31:0] is calculated as follows:
4589- VU_OPERAND_ADDR[31:15] = ADDR[31:15]
4590- VU_OPERAND_ADDR[14:8] = (ADDR[14:8] &amp; MASK[14:8]) | (offset[14:8] &amp; ~MASK[14:8])
4591- VU_OPERAND_ADDR[7:2] = offset[7:2]
4592- VU_OPERAND_ADDR[1:0] = 0 (always word aligned)
4593
4594The vector unit operand memory region uses either the IP's memory buffer or system memory. For best performance, the IP's memory buffer should be used and ADDR should be set to MEM_BUFF and MASK should specify the IP memory buffer size.
4595
4596If a vector operand memory address is mapped on a memory hole, read accesses return a '0' and write accesses are ignored.</description>
4597              <bitRange>[31:8]</bitRange>
4598              <access>read-write</access>
4599            </field>
4600          </fields>
4601        </register>
4602        <register>
4603          <name>VU_CTL2</name>
4604          <description>Vector unit control 2</description>
4605          <addressOffset>0x1488</addressOffset>
4606          <size>32</size>
4607          <access>read-write</access>
4608          <resetValue>0x7F00</resetValue>
4609          <resetMask>0x7F00</resetMask>
4610          <fields>
4611            <field>
4612              <name>MASK</name>
4613              <description>Specifies the size of  the vector operand memory region. Legal values:
4614'0b0000000': 32 KB memory region (VU_VTL1.ADDR[14:8] ignored).
4615'0b1000000': 16 KB memory region (VU_VTL1.ADDR[13:8] ignored).
4616'0b1100000': 8 KB memory region (VU_VTL1.ADDR[12:8] ignored).
4617'0b1110000': 4 KB memory region (VU_VTL1.ADDR[11:8] ignored).
4618'0b1111000': 2 KB memory region (VU_VTL1.ADDR[10:8] ignored).
4619'0b1111100': 1 KB memory region (VU_VTL1.ADDR[9:8] ignored).
4620'0b1111110': 512 B memory region (VU_VTL1.ADDR[8] ignored).
4621'0b1111111': 256 B memory region.
4622
4623Note: the default specifies a 256 B memory region.</description>
4624              <bitRange>[14:8]</bitRange>
4625              <access>read-write</access>
4626            </field>
4627          </fields>
4628        </register>
4629        <register>
4630          <name>VU_STATUS</name>
4631          <description>Vector unit status</description>
4632          <addressOffset>0x1490</addressOffset>
4633          <size>32</size>
4634          <access>read-only</access>
4635          <resetValue>0x0</resetValue>
4636          <resetMask>0xF</resetMask>
4637          <fields>
4638            <field>
4639              <name>CARRY</name>
4640              <description>STATUS CARRY field.</description>
4641              <bitRange>[0:0]</bitRange>
4642              <access>read-only</access>
4643            </field>
4644            <field>
4645              <name>EVEN</name>
4646              <description>STATUS EVEN field.</description>
4647              <bitRange>[1:1]</bitRange>
4648              <access>read-only</access>
4649            </field>
4650            <field>
4651              <name>ZERO</name>
4652              <description>STATUS ZERO field.</description>
4653              <bitRange>[2:2]</bitRange>
4654              <access>read-only</access>
4655            </field>
4656            <field>
4657              <name>ONE</name>
4658              <description>STATUS ONE field.</description>
4659              <bitRange>[3:3]</bitRange>
4660              <access>read-only</access>
4661            </field>
4662          </fields>
4663        </register>
4664        <register>
4665          <dim>16</dim>
4666          <dimIncrement>4</dimIncrement>
4667          <name>VU_RF_DATA[%s]</name>
4668          <description>Vector unit register-file</description>
4669          <addressOffset>0x14C0</addressOffset>
4670          <size>32</size>
4671          <access>read-only</access>
4672          <resetValue>0x0</resetValue>
4673          <resetMask>0xFFFFFFFF</resetMask>
4674          <fields>
4675            <field>
4676              <name>DATA32</name>
4677              <description>Vector unit register-file data. A register-file register has the following layout:
4678DATA[28:16]: data (typically used as a word offset in vector unit operand memory).
4679DATA[12:0]: bit size minus 1.</description>
4680              <bitRange>[31:0]</bitRange>
4681              <access>read-only</access>
4682            </field>
4683          </fields>
4684        </register>
4685        <register>
4686          <name>DEV_KEY_ADDR0_CTL</name>
4687          <description>Device key address 0 control</description>
4688          <addressOffset>0x2000</addressOffset>
4689          <size>32</size>
4690          <access>read-write</access>
4691          <resetValue>0x0</resetValue>
4692          <resetMask>0x80000000</resetMask>
4693          <fields>
4694            <field>
4695              <name>VALID</name>
4696              <description>Specifies if the address in the associated DEV_KEY_ADDR0 is valid:
4697'0': Address not valid; i.e. no device key specified.
4698'1': Address valid; i.e. device key specified.
4699
4700Note: A LOAD_DEV_KEY instruction requires that the device key's valid field is '1'.</description>
4701              <bitRange>[31:31]</bitRange>
4702              <access>read-write</access>
4703            </field>
4704          </fields>
4705        </register>
4706        <register>
4707          <name>DEV_KEY_ADDR0</name>
4708          <description>Device key address 0</description>
4709          <addressOffset>0x2004</addressOffset>
4710          <size>32</size>
4711          <access>read-write</access>
4712          <resetValue>0x0</resetValue>
4713          <resetMask>0xFFFFFFFF</resetMask>
4714          <fields>
4715            <field>
4716              <name>ADDR32</name>
4717              <description>Specifies the memory address of the device key in memory. A LOAD_DEV_KEY instruction uses this address to load a device key from memory into the IP register buffer blocks 4 and 5.</description>
4718              <bitRange>[31:0]</bitRange>
4719              <access>read-write</access>
4720            </field>
4721          </fields>
4722        </register>
4723        <register>
4724          <name>DEV_KEY_ADDR1_CTL</name>
4725          <description>Device key address 1 control</description>
4726          <addressOffset>0x2020</addressOffset>
4727          <size>32</size>
4728          <access>read-write</access>
4729          <resetValue>0x0</resetValue>
4730          <resetMask>0x80000000</resetMask>
4731          <fields>
4732            <field>
4733              <name>VALID</name>
4734              <description>See DEV_KEY_ADDR0_CTL.</description>
4735              <bitRange>[31:31]</bitRange>
4736              <access>read-write</access>
4737            </field>
4738          </fields>
4739        </register>
4740        <register>
4741          <name>DEV_KEY_ADDR1</name>
4742          <description>Device key address 1 control</description>
4743          <addressOffset>0x2024</addressOffset>
4744          <size>32</size>
4745          <access>read-write</access>
4746          <resetValue>0x0</resetValue>
4747          <resetMask>0xFFFFFFFF</resetMask>
4748          <fields>
4749            <field>
4750              <name>ADDR32</name>
4751              <description>See DEV_KEY_ADDR0.</description>
4752              <bitRange>[31:0]</bitRange>
4753              <access>read-write</access>
4754            </field>
4755          </fields>
4756        </register>
4757        <register>
4758          <name>DEV_KEY_STATUS</name>
4759          <description>Device key status</description>
4760          <addressOffset>0x2080</addressOffset>
4761          <size>32</size>
4762          <access>read-only</access>
4763          <resetValue>0x0</resetValue>
4764          <resetMask>0x1</resetMask>
4765          <fields>
4766            <field>
4767              <name>LOADED</name>
4768              <description>Specifies if a device key is present in the IP register buffer blocks 4 and 5.
4769
4770HW sets this field to '1' on successful completion of a LOAD_DEV_KEY instruction.
4771HW clears this field to '0' when a CLEAR instruction is executed (the CLEAR instruction also sets the IP register buffer to '0').</description>
4772              <bitRange>[0:0]</bitRange>
4773              <access>read-only</access>
4774            </field>
4775          </fields>
4776        </register>
4777        <register>
4778          <name>DEV_KEY_CTL0</name>
4779          <description>Device key control 0</description>
4780          <addressOffset>0x2100</addressOffset>
4781          <size>32</size>
4782          <access>read-write</access>
4783          <resetValue>0x0</resetValue>
4784          <resetMask>0x1</resetMask>
4785          <fields>
4786            <field>
4787              <name>ALLOWED</name>
4788              <description>Specifies if a LOAD_DEV_KEY instruction is allowed to use the device key in memory:
4789'0': Not allowed.
4790'1': Allowed.
4791
4792Note: For successful completion of a LOAD_DEV_KEY instruction, both the associated DEV_KEY_ADDR_CTL.VALID and DEV_KEY_CTL.ALLOWED fields must be '1'. On successful instruction completion, DEV_KEY_STATUS.LOADED is set to '1'. On unsuccessful completion, the instruction FIFO is cleared and the IP is locked; an Active reset or an IP reset (CTL.ENABLED), which reinitializes the IP, is required.
4793
4794Note: A LOAD_DEV_KEY loads the device key from memory with protection context '0'.</description>
4795              <bitRange>[0:0]</bitRange>
4796              <access>read-write</access>
4797            </field>
4798          </fields>
4799        </register>
4800        <register>
4801          <name>DEV_KEY_CTL1</name>
4802          <description>Device key control 1</description>
4803          <addressOffset>0x2120</addressOffset>
4804          <size>32</size>
4805          <access>read-write</access>
4806          <resetValue>0x0</resetValue>
4807          <resetMask>0x1</resetMask>
4808          <fields>
4809            <field>
4810              <name>ALLOWED</name>
4811              <description>See DEV_KEY_CTL0.</description>
4812              <bitRange>[0:0]</bitRange>
4813              <access>read-write</access>
4814            </field>
4815          </fields>
4816        </register>
4817      </registers>
4818    </peripheral>
4819    <peripheral>
4820      <name>CPUSS</name>
4821      <description>CPU subsystem (CPUSS)</description>
4822      <baseAddress>0x40200000</baseAddress>
4823      <addressBlock>
4824        <offset>0</offset>
4825        <size>65536</size>
4826        <usage>registers</usage>
4827      </addressBlock>
4828      <interrupt>
4829        <name>ioss_interrupts_gpio_0</name>
4830        <description>GPIO Port Interrupt #0</description>
4831        <value>0</value>
4832      </interrupt>
4833      <interrupt>
4834        <name>ioss_interrupts_gpio_1</name>
4835        <description>GPIO Port Interrupt #1</description>
4836        <value>1</value>
4837      </interrupt>
4838      <interrupt>
4839        <name>ioss_interrupts_gpio_2</name>
4840        <description>GPIO Port Interrupt #2</description>
4841        <value>2</value>
4842      </interrupt>
4843      <interrupt>
4844        <name>ioss_interrupts_gpio_3</name>
4845        <description>GPIO Port Interrupt #3</description>
4846        <value>3</value>
4847      </interrupt>
4848      <interrupt>
4849        <name>ioss_interrupts_gpio_4</name>
4850        <description>GPIO Port Interrupt #4</description>
4851        <value>4</value>
4852      </interrupt>
4853      <interrupt>
4854        <name>ioss_interrupts_gpio_5</name>
4855        <description>GPIO Port Interrupt #5</description>
4856        <value>5</value>
4857      </interrupt>
4858      <interrupt>
4859        <name>ioss_interrupts_gpio_6</name>
4860        <description>GPIO Port Interrupt #6</description>
4861        <value>6</value>
4862      </interrupt>
4863      <interrupt>
4864        <name>ioss_interrupts_gpio_7</name>
4865        <description>GPIO Port Interrupt #7</description>
4866        <value>7</value>
4867      </interrupt>
4868      <interrupt>
4869        <name>ioss_interrupts_gpio_8</name>
4870        <description>GPIO Port Interrupt #8</description>
4871        <value>8</value>
4872      </interrupt>
4873      <interrupt>
4874        <name>ioss_interrupts_gpio_9</name>
4875        <description>GPIO Port Interrupt #9</description>
4876        <value>9</value>
4877      </interrupt>
4878      <interrupt>
4879        <name>ioss_interrupts_gpio_10</name>
4880        <description>GPIO Port Interrupt #10</description>
4881        <value>10</value>
4882      </interrupt>
4883      <interrupt>
4884        <name>ioss_interrupts_gpio_11</name>
4885        <description>GPIO Port Interrupt #11</description>
4886        <value>11</value>
4887      </interrupt>
4888      <interrupt>
4889        <name>ioss_interrupts_gpio_12</name>
4890        <description>GPIO Port Interrupt #12</description>
4891        <value>12</value>
4892      </interrupt>
4893      <interrupt>
4894        <name>ioss_interrupts_gpio_13</name>
4895        <description>GPIO Port Interrupt #13</description>
4896        <value>13</value>
4897      </interrupt>
4898      <interrupt>
4899        <name>ioss_interrupts_gpio_14</name>
4900        <description>GPIO Port Interrupt #14</description>
4901        <value>14</value>
4902      </interrupt>
4903      <interrupt>
4904        <name>ioss_interrupt_gpio</name>
4905        <description>GPIO All Ports</description>
4906        <value>15</value>
4907      </interrupt>
4908      <interrupt>
4909        <name>ioss_interrupt_vdd</name>
4910        <description>GPIO Supply Detect Interrupt</description>
4911        <value>16</value>
4912      </interrupt>
4913      <interrupt>
4914        <name>lpcomp_interrupt</name>
4915        <description>Low Power Comparator Interrupt</description>
4916        <value>17</value>
4917      </interrupt>
4918      <interrupt>
4919        <name>scb_8_interrupt</name>
4920        <description>Serial Communication Block #8 (DeepSleep capable)</description>
4921        <value>18</value>
4922      </interrupt>
4923      <interrupt>
4924        <name>srss_interrupt_mcwdt_0</name>
4925        <description>Multi Counter Watchdog Timer interrupt</description>
4926        <value>19</value>
4927      </interrupt>
4928      <interrupt>
4929        <name>srss_interrupt_mcwdt_1</name>
4930        <description>Multi Counter Watchdog Timer interrupt</description>
4931        <value>20</value>
4932      </interrupt>
4933      <interrupt>
4934        <name>srss_interrupt_backup</name>
4935        <description>Backup domain interrupt</description>
4936        <value>21</value>
4937      </interrupt>
4938      <interrupt>
4939        <name>srss_interrupt</name>
4940        <description>Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)</description>
4941        <value>22</value>
4942      </interrupt>
4943      <interrupt>
4944        <name>cpuss_interrupts_ipc_0</name>
4945        <description>CPUSS Inter Process Communication Interrupt #0</description>
4946        <value>23</value>
4947      </interrupt>
4948      <interrupt>
4949        <name>cpuss_interrupts_ipc_1</name>
4950        <description>CPUSS Inter Process Communication Interrupt #1</description>
4951        <value>24</value>
4952      </interrupt>
4953      <interrupt>
4954        <name>cpuss_interrupts_ipc_2</name>
4955        <description>CPUSS Inter Process Communication Interrupt #2</description>
4956        <value>25</value>
4957      </interrupt>
4958      <interrupt>
4959        <name>cpuss_interrupts_ipc_3</name>
4960        <description>CPUSS Inter Process Communication Interrupt #3</description>
4961        <value>26</value>
4962      </interrupt>
4963      <interrupt>
4964        <name>cpuss_interrupts_ipc_4</name>
4965        <description>CPUSS Inter Process Communication Interrupt #4</description>
4966        <value>27</value>
4967      </interrupt>
4968      <interrupt>
4969        <name>cpuss_interrupts_ipc_5</name>
4970        <description>CPUSS Inter Process Communication Interrupt #5</description>
4971        <value>28</value>
4972      </interrupt>
4973      <interrupt>
4974        <name>cpuss_interrupts_ipc_6</name>
4975        <description>CPUSS Inter Process Communication Interrupt #6</description>
4976        <value>29</value>
4977      </interrupt>
4978      <interrupt>
4979        <name>cpuss_interrupts_ipc_7</name>
4980        <description>CPUSS Inter Process Communication Interrupt #7</description>
4981        <value>30</value>
4982      </interrupt>
4983      <interrupt>
4984        <name>cpuss_interrupts_ipc_8</name>
4985        <description>CPUSS Inter Process Communication Interrupt #8</description>
4986        <value>31</value>
4987      </interrupt>
4988      <interrupt>
4989        <name>cpuss_interrupts_ipc_9</name>
4990        <description>CPUSS Inter Process Communication Interrupt #9</description>
4991        <value>32</value>
4992      </interrupt>
4993      <interrupt>
4994        <name>cpuss_interrupts_ipc_10</name>
4995        <description>CPUSS Inter Process Communication Interrupt #10</description>
4996        <value>33</value>
4997      </interrupt>
4998      <interrupt>
4999        <name>cpuss_interrupts_ipc_11</name>
5000        <description>CPUSS Inter Process Communication Interrupt #11</description>
5001        <value>34</value>
5002      </interrupt>
5003      <interrupt>
5004        <name>cpuss_interrupts_ipc_12</name>
5005        <description>CPUSS Inter Process Communication Interrupt #12</description>
5006        <value>35</value>
5007      </interrupt>
5008      <interrupt>
5009        <name>cpuss_interrupts_ipc_13</name>
5010        <description>CPUSS Inter Process Communication Interrupt #13</description>
5011        <value>36</value>
5012      </interrupt>
5013      <interrupt>
5014        <name>cpuss_interrupts_ipc_14</name>
5015        <description>CPUSS Inter Process Communication Interrupt #14</description>
5016        <value>37</value>
5017      </interrupt>
5018      <interrupt>
5019        <name>cpuss_interrupts_ipc_15</name>
5020        <description>CPUSS Inter Process Communication Interrupt #15</description>
5021        <value>38</value>
5022      </interrupt>
5023      <interrupt>
5024        <name>scb_0_interrupt</name>
5025        <description>Serial Communication Block #0</description>
5026        <value>39</value>
5027      </interrupt>
5028      <interrupt>
5029        <name>scb_1_interrupt</name>
5030        <description>Serial Communication Block #1</description>
5031        <value>40</value>
5032      </interrupt>
5033      <interrupt>
5034        <name>scb_2_interrupt</name>
5035        <description>Serial Communication Block #2</description>
5036        <value>41</value>
5037      </interrupt>
5038      <interrupt>
5039        <name>scb_3_interrupt</name>
5040        <description>Serial Communication Block #3</description>
5041        <value>42</value>
5042      </interrupt>
5043      <interrupt>
5044        <name>scb_4_interrupt</name>
5045        <description>Serial Communication Block #4</description>
5046        <value>43</value>
5047      </interrupt>
5048      <interrupt>
5049        <name>scb_5_interrupt</name>
5050        <description>Serial Communication Block #5</description>
5051        <value>44</value>
5052      </interrupt>
5053      <interrupt>
5054        <name>scb_6_interrupt</name>
5055        <description>Serial Communication Block #6</description>
5056        <value>45</value>
5057      </interrupt>
5058      <interrupt>
5059        <name>scb_7_interrupt</name>
5060        <description>Serial Communication Block #7</description>
5061        <value>46</value>
5062      </interrupt>
5063      <interrupt>
5064        <name>scb_9_interrupt</name>
5065        <description>Serial Communication Block #9</description>
5066        <value>47</value>
5067      </interrupt>
5068      <interrupt>
5069        <name>scb_10_interrupt</name>
5070        <description>Serial Communication Block #10</description>
5071        <value>48</value>
5072      </interrupt>
5073      <interrupt>
5074        <name>scb_11_interrupt</name>
5075        <description>Serial Communication Block #11</description>
5076        <value>49</value>
5077      </interrupt>
5078      <interrupt>
5079        <name>scb_12_interrupt</name>
5080        <description>Serial Communication Block #12</description>
5081        <value>50</value>
5082      </interrupt>
5083      <interrupt>
5084        <name>csd_interrupt</name>
5085        <description>CSD (Capsense) interrupt</description>
5086        <value>51</value>
5087      </interrupt>
5088      <interrupt>
5089        <name>cpuss_interrupts_dmac_0</name>
5090        <description>CPUSS DMAC, Channel #0</description>
5091        <value>52</value>
5092      </interrupt>
5093      <interrupt>
5094        <name>cpuss_interrupts_dmac_1</name>
5095        <description>CPUSS DMAC, Channel #1</description>
5096        <value>53</value>
5097      </interrupt>
5098      <interrupt>
5099        <name>cpuss_interrupts_dmac_2</name>
5100        <description>CPUSS DMAC, Channel #2</description>
5101        <value>54</value>
5102      </interrupt>
5103      <interrupt>
5104        <name>cpuss_interrupts_dmac_3</name>
5105        <description>CPUSS DMAC, Channel #3</description>
5106        <value>55</value>
5107      </interrupt>
5108      <interrupt>
5109        <name>cpuss_interrupts_dw0_0</name>
5110        <description>CPUSS DataWire #0, Channel #0</description>
5111        <value>56</value>
5112      </interrupt>
5113      <interrupt>
5114        <name>cpuss_interrupts_dw0_1</name>
5115        <description>CPUSS DataWire #0, Channel #1</description>
5116        <value>57</value>
5117      </interrupt>
5118      <interrupt>
5119        <name>cpuss_interrupts_dw0_2</name>
5120        <description>CPUSS DataWire #0, Channel #2</description>
5121        <value>58</value>
5122      </interrupt>
5123      <interrupt>
5124        <name>cpuss_interrupts_dw0_3</name>
5125        <description>CPUSS DataWire #0, Channel #3</description>
5126        <value>59</value>
5127      </interrupt>
5128      <interrupt>
5129        <name>cpuss_interrupts_dw0_4</name>
5130        <description>CPUSS DataWire #0, Channel #4</description>
5131        <value>60</value>
5132      </interrupt>
5133      <interrupt>
5134        <name>cpuss_interrupts_dw0_5</name>
5135        <description>CPUSS DataWire #0, Channel #5</description>
5136        <value>61</value>
5137      </interrupt>
5138      <interrupt>
5139        <name>cpuss_interrupts_dw0_6</name>
5140        <description>CPUSS DataWire #0, Channel #6</description>
5141        <value>62</value>
5142      </interrupt>
5143      <interrupt>
5144        <name>cpuss_interrupts_dw0_7</name>
5145        <description>CPUSS DataWire #0, Channel #7</description>
5146        <value>63</value>
5147      </interrupt>
5148      <interrupt>
5149        <name>cpuss_interrupts_dw0_8</name>
5150        <description>CPUSS DataWire #0, Channel #8</description>
5151        <value>64</value>
5152      </interrupt>
5153      <interrupt>
5154        <name>cpuss_interrupts_dw0_9</name>
5155        <description>CPUSS DataWire #0, Channel #9</description>
5156        <value>65</value>
5157      </interrupt>
5158      <interrupt>
5159        <name>cpuss_interrupts_dw0_10</name>
5160        <description>CPUSS DataWire #0, Channel #10</description>
5161        <value>66</value>
5162      </interrupt>
5163      <interrupt>
5164        <name>cpuss_interrupts_dw0_11</name>
5165        <description>CPUSS DataWire #0, Channel #11</description>
5166        <value>67</value>
5167      </interrupt>
5168      <interrupt>
5169        <name>cpuss_interrupts_dw0_12</name>
5170        <description>CPUSS DataWire #0, Channel #12</description>
5171        <value>68</value>
5172      </interrupt>
5173      <interrupt>
5174        <name>cpuss_interrupts_dw0_13</name>
5175        <description>CPUSS DataWire #0, Channel #13</description>
5176        <value>69</value>
5177      </interrupt>
5178      <interrupt>
5179        <name>cpuss_interrupts_dw0_14</name>
5180        <description>CPUSS DataWire #0, Channel #14</description>
5181        <value>70</value>
5182      </interrupt>
5183      <interrupt>
5184        <name>cpuss_interrupts_dw0_15</name>
5185        <description>CPUSS DataWire #0, Channel #15</description>
5186        <value>71</value>
5187      </interrupt>
5188      <interrupt>
5189        <name>cpuss_interrupts_dw0_16</name>
5190        <description>CPUSS DataWire #0, Channel #16</description>
5191        <value>72</value>
5192      </interrupt>
5193      <interrupt>
5194        <name>cpuss_interrupts_dw0_17</name>
5195        <description>CPUSS DataWire #0, Channel #17</description>
5196        <value>73</value>
5197      </interrupt>
5198      <interrupt>
5199        <name>cpuss_interrupts_dw0_18</name>
5200        <description>CPUSS DataWire #0, Channel #18</description>
5201        <value>74</value>
5202      </interrupt>
5203      <interrupt>
5204        <name>cpuss_interrupts_dw0_19</name>
5205        <description>CPUSS DataWire #0, Channel #19</description>
5206        <value>75</value>
5207      </interrupt>
5208      <interrupt>
5209        <name>cpuss_interrupts_dw0_20</name>
5210        <description>CPUSS DataWire #0, Channel #20</description>
5211        <value>76</value>
5212      </interrupt>
5213      <interrupt>
5214        <name>cpuss_interrupts_dw0_21</name>
5215        <description>CPUSS DataWire #0, Channel #21</description>
5216        <value>77</value>
5217      </interrupt>
5218      <interrupt>
5219        <name>cpuss_interrupts_dw0_22</name>
5220        <description>CPUSS DataWire #0, Channel #22</description>
5221        <value>78</value>
5222      </interrupt>
5223      <interrupt>
5224        <name>cpuss_interrupts_dw0_23</name>
5225        <description>CPUSS DataWire #0, Channel #23</description>
5226        <value>79</value>
5227      </interrupt>
5228      <interrupt>
5229        <name>cpuss_interrupts_dw0_24</name>
5230        <description>CPUSS DataWire #0, Channel #24</description>
5231        <value>80</value>
5232      </interrupt>
5233      <interrupt>
5234        <name>cpuss_interrupts_dw0_25</name>
5235        <description>CPUSS DataWire #0, Channel #25</description>
5236        <value>81</value>
5237      </interrupt>
5238      <interrupt>
5239        <name>cpuss_interrupts_dw0_26</name>
5240        <description>CPUSS DataWire #0, Channel #26</description>
5241        <value>82</value>
5242      </interrupt>
5243      <interrupt>
5244        <name>cpuss_interrupts_dw0_27</name>
5245        <description>CPUSS DataWire #0, Channel #27</description>
5246        <value>83</value>
5247      </interrupt>
5248      <interrupt>
5249        <name>cpuss_interrupts_dw0_28</name>
5250        <description>CPUSS DataWire #0, Channel #28</description>
5251        <value>84</value>
5252      </interrupt>
5253      <interrupt>
5254        <name>cpuss_interrupts_dw1_0</name>
5255        <description>CPUSS DataWire #1, Channel #0</description>
5256        <value>85</value>
5257      </interrupt>
5258      <interrupt>
5259        <name>cpuss_interrupts_dw1_1</name>
5260        <description>CPUSS DataWire #1, Channel #1</description>
5261        <value>86</value>
5262      </interrupt>
5263      <interrupt>
5264        <name>cpuss_interrupts_dw1_2</name>
5265        <description>CPUSS DataWire #1, Channel #2</description>
5266        <value>87</value>
5267      </interrupt>
5268      <interrupt>
5269        <name>cpuss_interrupts_dw1_3</name>
5270        <description>CPUSS DataWire #1, Channel #3</description>
5271        <value>88</value>
5272      </interrupt>
5273      <interrupt>
5274        <name>cpuss_interrupts_dw1_4</name>
5275        <description>CPUSS DataWire #1, Channel #4</description>
5276        <value>89</value>
5277      </interrupt>
5278      <interrupt>
5279        <name>cpuss_interrupts_dw1_5</name>
5280        <description>CPUSS DataWire #1, Channel #5</description>
5281        <value>90</value>
5282      </interrupt>
5283      <interrupt>
5284        <name>cpuss_interrupts_dw1_6</name>
5285        <description>CPUSS DataWire #1, Channel #6</description>
5286        <value>91</value>
5287      </interrupt>
5288      <interrupt>
5289        <name>cpuss_interrupts_dw1_7</name>
5290        <description>CPUSS DataWire #1, Channel #7</description>
5291        <value>92</value>
5292      </interrupt>
5293      <interrupt>
5294        <name>cpuss_interrupts_dw1_8</name>
5295        <description>CPUSS DataWire #1, Channel #8</description>
5296        <value>93</value>
5297      </interrupt>
5298      <interrupt>
5299        <name>cpuss_interrupts_dw1_9</name>
5300        <description>CPUSS DataWire #1, Channel #9</description>
5301        <value>94</value>
5302      </interrupt>
5303      <interrupt>
5304        <name>cpuss_interrupts_dw1_10</name>
5305        <description>CPUSS DataWire #1, Channel #10</description>
5306        <value>95</value>
5307      </interrupt>
5308      <interrupt>
5309        <name>cpuss_interrupts_dw1_11</name>
5310        <description>CPUSS DataWire #1, Channel #11</description>
5311        <value>96</value>
5312      </interrupt>
5313      <interrupt>
5314        <name>cpuss_interrupts_dw1_12</name>
5315        <description>CPUSS DataWire #1, Channel #12</description>
5316        <value>97</value>
5317      </interrupt>
5318      <interrupt>
5319        <name>cpuss_interrupts_dw1_13</name>
5320        <description>CPUSS DataWire #1, Channel #13</description>
5321        <value>98</value>
5322      </interrupt>
5323      <interrupt>
5324        <name>cpuss_interrupts_dw1_14</name>
5325        <description>CPUSS DataWire #1, Channel #14</description>
5326        <value>99</value>
5327      </interrupt>
5328      <interrupt>
5329        <name>cpuss_interrupts_dw1_15</name>
5330        <description>CPUSS DataWire #1, Channel #15</description>
5331        <value>100</value>
5332      </interrupt>
5333      <interrupt>
5334        <name>cpuss_interrupts_dw1_16</name>
5335        <description>CPUSS DataWire #1, Channel #16</description>
5336        <value>101</value>
5337      </interrupt>
5338      <interrupt>
5339        <name>cpuss_interrupts_dw1_17</name>
5340        <description>CPUSS DataWire #1, Channel #17</description>
5341        <value>102</value>
5342      </interrupt>
5343      <interrupt>
5344        <name>cpuss_interrupts_dw1_18</name>
5345        <description>CPUSS DataWire #1, Channel #18</description>
5346        <value>103</value>
5347      </interrupt>
5348      <interrupt>
5349        <name>cpuss_interrupts_dw1_19</name>
5350        <description>CPUSS DataWire #1, Channel #19</description>
5351        <value>104</value>
5352      </interrupt>
5353      <interrupt>
5354        <name>cpuss_interrupts_dw1_20</name>
5355        <description>CPUSS DataWire #1, Channel #20</description>
5356        <value>105</value>
5357      </interrupt>
5358      <interrupt>
5359        <name>cpuss_interrupts_dw1_21</name>
5360        <description>CPUSS DataWire #1, Channel #21</description>
5361        <value>106</value>
5362      </interrupt>
5363      <interrupt>
5364        <name>cpuss_interrupts_dw1_22</name>
5365        <description>CPUSS DataWire #1, Channel #22</description>
5366        <value>107</value>
5367      </interrupt>
5368      <interrupt>
5369        <name>cpuss_interrupts_dw1_23</name>
5370        <description>CPUSS DataWire #1, Channel #23</description>
5371        <value>108</value>
5372      </interrupt>
5373      <interrupt>
5374        <name>cpuss_interrupts_dw1_24</name>
5375        <description>CPUSS DataWire #1, Channel #24</description>
5376        <value>109</value>
5377      </interrupt>
5378      <interrupt>
5379        <name>cpuss_interrupts_dw1_25</name>
5380        <description>CPUSS DataWire #1, Channel #25</description>
5381        <value>110</value>
5382      </interrupt>
5383      <interrupt>
5384        <name>cpuss_interrupts_dw1_26</name>
5385        <description>CPUSS DataWire #1, Channel #26</description>
5386        <value>111</value>
5387      </interrupt>
5388      <interrupt>
5389        <name>cpuss_interrupts_dw1_27</name>
5390        <description>CPUSS DataWire #1, Channel #27</description>
5391        <value>112</value>
5392      </interrupt>
5393      <interrupt>
5394        <name>cpuss_interrupts_dw1_28</name>
5395        <description>CPUSS DataWire #1, Channel #28</description>
5396        <value>113</value>
5397      </interrupt>
5398      <interrupt>
5399        <name>cpuss_interrupts_fault_0</name>
5400        <description>CPUSS Fault Structure Interrupt #0</description>
5401        <value>114</value>
5402      </interrupt>
5403      <interrupt>
5404        <name>cpuss_interrupts_fault_1</name>
5405        <description>CPUSS Fault Structure Interrupt #1</description>
5406        <value>115</value>
5407      </interrupt>
5408      <interrupt>
5409        <name>cpuss_interrupt_crypto</name>
5410        <description>CRYPTO Accelerator Interrupt</description>
5411        <value>116</value>
5412      </interrupt>
5413      <interrupt>
5414        <name>cpuss_interrupt_fm</name>
5415        <description>FLASH Macro Interrupt</description>
5416        <value>117</value>
5417      </interrupt>
5418      <interrupt>
5419        <name>cpuss_interrupts_cm4_fp</name>
5420        <description>Floating Point operation fault</description>
5421        <value>118</value>
5422      </interrupt>
5423      <interrupt>
5424        <name>cpuss_interrupts_cm0_cti_0</name>
5425        <description>CM0+ CTI #0</description>
5426        <value>119</value>
5427      </interrupt>
5428      <interrupt>
5429        <name>cpuss_interrupts_cm0_cti_1</name>
5430        <description>CM0+ CTI #1</description>
5431        <value>120</value>
5432      </interrupt>
5433      <interrupt>
5434        <name>cpuss_interrupts_cm4_cti_0</name>
5435        <description>CM4 CTI #0</description>
5436        <value>121</value>
5437      </interrupt>
5438      <interrupt>
5439        <name>cpuss_interrupts_cm4_cti_1</name>
5440        <description>CM4 CTI #1</description>
5441        <value>122</value>
5442      </interrupt>
5443      <interrupt>
5444        <name>tcpwm_0_interrupts_0</name>
5445        <description>TCPWM #0, Counter #0</description>
5446        <value>123</value>
5447      </interrupt>
5448      <interrupt>
5449        <name>tcpwm_0_interrupts_1</name>
5450        <description>TCPWM #0, Counter #1</description>
5451        <value>124</value>
5452      </interrupt>
5453      <interrupt>
5454        <name>tcpwm_0_interrupts_2</name>
5455        <description>TCPWM #0, Counter #2</description>
5456        <value>125</value>
5457      </interrupt>
5458      <interrupt>
5459        <name>tcpwm_0_interrupts_3</name>
5460        <description>TCPWM #0, Counter #3</description>
5461        <value>126</value>
5462      </interrupt>
5463      <interrupt>
5464        <name>tcpwm_0_interrupts_4</name>
5465        <description>TCPWM #0, Counter #4</description>
5466        <value>127</value>
5467      </interrupt>
5468      <interrupt>
5469        <name>tcpwm_0_interrupts_5</name>
5470        <description>TCPWM #0, Counter #5</description>
5471        <value>128</value>
5472      </interrupt>
5473      <interrupt>
5474        <name>tcpwm_0_interrupts_6</name>
5475        <description>TCPWM #0, Counter #6</description>
5476        <value>129</value>
5477      </interrupt>
5478      <interrupt>
5479        <name>tcpwm_0_interrupts_7</name>
5480        <description>TCPWM #0, Counter #7</description>
5481        <value>130</value>
5482      </interrupt>
5483      <interrupt>
5484        <name>tcpwm_1_interrupts_0</name>
5485        <description>TCPWM #1, Counter #0</description>
5486        <value>131</value>
5487      </interrupt>
5488      <interrupt>
5489        <name>tcpwm_1_interrupts_1</name>
5490        <description>TCPWM #1, Counter #1</description>
5491        <value>132</value>
5492      </interrupt>
5493      <interrupt>
5494        <name>tcpwm_1_interrupts_2</name>
5495        <description>TCPWM #1, Counter #2</description>
5496        <value>133</value>
5497      </interrupt>
5498      <interrupt>
5499        <name>tcpwm_1_interrupts_3</name>
5500        <description>TCPWM #1, Counter #3</description>
5501        <value>134</value>
5502      </interrupt>
5503      <interrupt>
5504        <name>tcpwm_1_interrupts_4</name>
5505        <description>TCPWM #1, Counter #4</description>
5506        <value>135</value>
5507      </interrupt>
5508      <interrupt>
5509        <name>tcpwm_1_interrupts_5</name>
5510        <description>TCPWM #1, Counter #5</description>
5511        <value>136</value>
5512      </interrupt>
5513      <interrupt>
5514        <name>tcpwm_1_interrupts_6</name>
5515        <description>TCPWM #1, Counter #6</description>
5516        <value>137</value>
5517      </interrupt>
5518      <interrupt>
5519        <name>tcpwm_1_interrupts_7</name>
5520        <description>TCPWM #1, Counter #7</description>
5521        <value>138</value>
5522      </interrupt>
5523      <interrupt>
5524        <name>tcpwm_1_interrupts_8</name>
5525        <description>TCPWM #1, Counter #8</description>
5526        <value>139</value>
5527      </interrupt>
5528      <interrupt>
5529        <name>tcpwm_1_interrupts_9</name>
5530        <description>TCPWM #1, Counter #9</description>
5531        <value>140</value>
5532      </interrupt>
5533      <interrupt>
5534        <name>tcpwm_1_interrupts_10</name>
5535        <description>TCPWM #1, Counter #10</description>
5536        <value>141</value>
5537      </interrupt>
5538      <interrupt>
5539        <name>tcpwm_1_interrupts_11</name>
5540        <description>TCPWM #1, Counter #11</description>
5541        <value>142</value>
5542      </interrupt>
5543      <interrupt>
5544        <name>tcpwm_1_interrupts_12</name>
5545        <description>TCPWM #1, Counter #12</description>
5546        <value>143</value>
5547      </interrupt>
5548      <interrupt>
5549        <name>tcpwm_1_interrupts_13</name>
5550        <description>TCPWM #1, Counter #13</description>
5551        <value>144</value>
5552      </interrupt>
5553      <interrupt>
5554        <name>tcpwm_1_interrupts_14</name>
5555        <description>TCPWM #1, Counter #14</description>
5556        <value>145</value>
5557      </interrupt>
5558      <interrupt>
5559        <name>tcpwm_1_interrupts_15</name>
5560        <description>TCPWM #1, Counter #15</description>
5561        <value>146</value>
5562      </interrupt>
5563      <interrupt>
5564        <name>tcpwm_1_interrupts_16</name>
5565        <description>TCPWM #1, Counter #16</description>
5566        <value>147</value>
5567      </interrupt>
5568      <interrupt>
5569        <name>tcpwm_1_interrupts_17</name>
5570        <description>TCPWM #1, Counter #17</description>
5571        <value>148</value>
5572      </interrupt>
5573      <interrupt>
5574        <name>tcpwm_1_interrupts_18</name>
5575        <description>TCPWM #1, Counter #18</description>
5576        <value>149</value>
5577      </interrupt>
5578      <interrupt>
5579        <name>tcpwm_1_interrupts_19</name>
5580        <description>TCPWM #1, Counter #19</description>
5581        <value>150</value>
5582      </interrupt>
5583      <interrupt>
5584        <name>tcpwm_1_interrupts_20</name>
5585        <description>TCPWM #1, Counter #20</description>
5586        <value>151</value>
5587      </interrupt>
5588      <interrupt>
5589        <name>tcpwm_1_interrupts_21</name>
5590        <description>TCPWM #1, Counter #21</description>
5591        <value>152</value>
5592      </interrupt>
5593      <interrupt>
5594        <name>tcpwm_1_interrupts_22</name>
5595        <description>TCPWM #1, Counter #22</description>
5596        <value>153</value>
5597      </interrupt>
5598      <interrupt>
5599        <name>tcpwm_1_interrupts_23</name>
5600        <description>TCPWM #1, Counter #23</description>
5601        <value>154</value>
5602      </interrupt>
5603      <interrupt>
5604        <name>pass_interrupt_sar</name>
5605        <description>SAR ADC interrupt</description>
5606        <value>155</value>
5607      </interrupt>
5608      <interrupt>
5609        <name>audioss_0_interrupt_i2s</name>
5610        <description>I2S0 Audio interrupt</description>
5611        <value>156</value>
5612      </interrupt>
5613      <interrupt>
5614        <name>audioss_0_interrupt_pdm</name>
5615        <description>PDM0/PCM0 Audio interrupt</description>
5616        <value>157</value>
5617      </interrupt>
5618      <interrupt>
5619        <name>audioss_1_interrupt_i2s</name>
5620        <description>I2S1 Audio interrupt</description>
5621        <value>158</value>
5622      </interrupt>
5623      <interrupt>
5624        <name>profile_interrupt</name>
5625        <description>Energy Profiler interrupt</description>
5626        <value>159</value>
5627      </interrupt>
5628      <interrupt>
5629        <name>smif_interrupt</name>
5630        <description>Serial Memory Interface interrupt</description>
5631        <value>160</value>
5632      </interrupt>
5633      <interrupt>
5634        <name>usb_interrupt_hi</name>
5635        <description>USB Interrupt</description>
5636        <value>161</value>
5637      </interrupt>
5638      <interrupt>
5639        <name>usb_interrupt_med</name>
5640        <description>USB Interrupt</description>
5641        <value>162</value>
5642      </interrupt>
5643      <interrupt>
5644        <name>usb_interrupt_lo</name>
5645        <description>USB Interrupt</description>
5646        <value>163</value>
5647      </interrupt>
5648      <interrupt>
5649        <name>sdhc_0_interrupt_wakeup</name>
5650        <description>SDIO wakeup interrupt for mxsdhc</description>
5651        <value>164</value>
5652      </interrupt>
5653      <interrupt>
5654        <name>sdhc_0_interrupt_general</name>
5655        <description>Consolidated interrupt for mxsdhc for everything else</description>
5656        <value>165</value>
5657      </interrupt>
5658      <interrupt>
5659        <name>sdhc_1_interrupt_wakeup</name>
5660        <description>EEMC wakeup interrupt for mxsdhc, not used</description>
5661        <value>166</value>
5662      </interrupt>
5663      <interrupt>
5664        <name>sdhc_1_interrupt_general</name>
5665        <description>Consolidated interrupt for mxsdhc for everything else</description>
5666        <value>167</value>
5667      </interrupt>
5668      <registers>
5669        <register>
5670          <name>IDENTITY</name>
5671          <description>Identity</description>
5672          <addressOffset>0x0</addressOffset>
5673          <size>32</size>
5674          <access>read-only</access>
5675          <resetValue>0x0</resetValue>
5676          <resetMask>0x0</resetMask>
5677          <fields>
5678            <field>
5679              <name>P</name>
5680              <description>This field specifies the privileged setting ('0': user mode; '1': privileged mode) of the transfer that reads the register.</description>
5681              <bitRange>[0:0]</bitRange>
5682              <access>read-only</access>
5683            </field>
5684            <field>
5685              <name>NS</name>
5686              <description>This field specifies the security setting ('0': secure mode; '1': non-secure mode) of the transfer that reads the register.</description>
5687              <bitRange>[1:1]</bitRange>
5688              <access>read-only</access>
5689            </field>
5690            <field>
5691              <name>PC</name>
5692              <description>This field specifies the protection context of the transfer that reads the register.</description>
5693              <bitRange>[7:4]</bitRange>
5694              <access>read-only</access>
5695            </field>
5696            <field>
5697              <name>MS</name>
5698              <description>This field specifies the bus master identifier of the transfer that reads the register.</description>
5699              <bitRange>[11:8]</bitRange>
5700              <access>read-only</access>
5701            </field>
5702          </fields>
5703        </register>
5704        <register>
5705          <name>CM4_STATUS</name>
5706          <description>CM4 status</description>
5707          <addressOffset>0x4</addressOffset>
5708          <size>32</size>
5709          <access>read-only</access>
5710          <resetValue>0x13</resetValue>
5711          <resetMask>0x13</resetMask>
5712          <fields>
5713            <field>
5714              <name>SLEEPING</name>
5715              <description>Specifies if the CPU is in Active, Sleep or DeepSleep power mode:
5716- Active power mode: SLEEPING is '0'.
5717- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'.
5718- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.</description>
5719              <bitRange>[0:0]</bitRange>
5720              <access>read-only</access>
5721            </field>
5722            <field>
5723              <name>SLEEPDEEP</name>
5724              <description>Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.</description>
5725              <bitRange>[1:1]</bitRange>
5726              <access>read-only</access>
5727            </field>
5728            <field>
5729              <name>PWR_DONE</name>
5730              <description>After a PWR_MODE change this flag indicates if the new power mode has taken effect or not.
5731Note: this flag can also change as a result of  a change in debug power up req</description>
5732              <bitRange>[4:4]</bitRange>
5733              <access>read-only</access>
5734            </field>
5735          </fields>
5736        </register>
5737        <register>
5738          <name>CM4_CLOCK_CTL</name>
5739          <description>CM4 clock control</description>
5740          <addressOffset>0x8</addressOffset>
5741          <size>32</size>
5742          <access>read-write</access>
5743          <resetValue>0x0</resetValue>
5744          <resetMask>0xFF00</resetMask>
5745          <fields>
5746            <field>
5747              <name>FAST_INT_DIV</name>
5748              <description>Specifies the fast clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_fast'). Integer division by (1+FAST_INT_DIV). Allows for integer divisions in the range [1, 256] (FAST_INT_DIV is in the range [0, 255]).
5749
5750Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
5751              <bitRange>[15:8]</bitRange>
5752              <access>read-write</access>
5753            </field>
5754          </fields>
5755        </register>
5756        <register>
5757          <name>CM4_CTL</name>
5758          <description>CM4 control</description>
5759          <addressOffset>0xC</addressOffset>
5760          <size>32</size>
5761          <access>read-write</access>
5762          <resetValue>0x0</resetValue>
5763          <resetMask>0x9F000000</resetMask>
5764          <fields>
5765            <field>
5766              <name>IOC_MASK</name>
5767              <description>CPU floating point unit (FPU) exception mask for the CPU's FPCSR.IOC 'invalid operation' exception condition:
5768'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5769'1': the CPU's exception condition activates the CPU's floating point interrupt.
5770
5771Note: the ARM architecture does NOT support FPU exceptions; i.e. there is no precise FPU exception handler. Instead, FPU conditions are captured in the CPU's FPCSR register and the conditions are provided as CPU interface signals. The interface signals are 'masked' with the fields a provide by this register (CM7_0_CTL). The 'masked' signals are reduced/OR-ed into a single CPU floating point interrupt signal. The associated CPU interrupt handler allows for imprecise handling of FPU exception conditions.
5772
5773Note: the CPU's FPCSR exception conditions are 'sticky'. Typically, the CPU FPU interrupt handler will clear the exception condition(s) to '0'.
5774
5775Note: by default, the FPU exception masks are '0'. Therefore, FPU exception conditions will NOT activate the CPU's floating point interrupt.</description>
5776              <bitRange>[24:24]</bitRange>
5777              <access>read-write</access>
5778            </field>
5779            <field>
5780              <name>DZC_MASK</name>
5781              <description>CPU FPU exception mask for the CPU's FPCSR.DZC 'divide by zero' exception condition:
5782'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5783'1': the CPU's exception condition activates the CPU's floating point interrupt.</description>
5784              <bitRange>[25:25]</bitRange>
5785              <access>read-write</access>
5786            </field>
5787            <field>
5788              <name>OFC_MASK</name>
5789              <description>CPU FPU exception mask for the CPU's FPCSR.OFC 'overflow' exception condition:
5790'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5791'1': the CPU's exception condition activates the CPU's floating point interrupt.</description>
5792              <bitRange>[26:26]</bitRange>
5793              <access>read-write</access>
5794            </field>
5795            <field>
5796              <name>UFC_MASK</name>
5797              <description>CPU FPU exception mask for the CPU's FPCSR.UFC 'underflow' exception condition:
5798'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5799'1': the CPU's exception condition activates the CPU's floating point interrupt.</description>
5800              <bitRange>[27:27]</bitRange>
5801              <access>read-write</access>
5802            </field>
5803            <field>
5804              <name>IXC_MASK</name>
5805              <description>CPU FPU exception mask for the CPU's FPCSR.IXC 'inexact' exception condition:
5806'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5807'1': the CPU's exception condition activates the CPU's floating point interrupt.
5808
5809Note: the 'inexact' condition is set as a result of rounding. Rounding may occur frequently and is typically not an error condition. To prevent frequent CPU FPU interrupts as a result of rounding, this field is typically set to '0'.</description>
5810              <bitRange>[28:28]</bitRange>
5811              <access>read-write</access>
5812            </field>
5813            <field>
5814              <name>IDC_MASK</name>
5815              <description>CPU FPU exception mask for the CPU's FPCSR.IDC 'input denormalized' exception condition:
5816'0': The CPU's exception condition does NOT activate the CPU's floating point interrupt.
5817'1': the CPU's exception condition activates the CPU's floating point interrupt.
5818
5819Note: if the CPU FPCSR.FZ field is set to '1', denormalized inputs are 'flushed to zero'. Dependent on the FPU algorithm, this may or may not occur frequently. To prevent frequent CPU FPU interrupts as a result of denormalized inputs, this field may be set to '0'.</description>
5820              <bitRange>[31:31]</bitRange>
5821              <access>read-write</access>
5822            </field>
5823          </fields>
5824        </register>
5825        <register>
5826          <name>CM4_INT0_STATUS</name>
5827          <description>CM4 interrupt 0 status</description>
5828          <addressOffset>0x100</addressOffset>
5829          <size>32</size>
5830          <access>read-only</access>
5831          <resetValue>0x0</resetValue>
5832          <resetMask>0x80000000</resetMask>
5833          <fields>
5834            <field>
5835              <name>SYSTEM_INT_IDX</name>
5836              <description>Lowest CM4 activated system interrupt index for CPU interrupt 0.
5837
5838See description of CM0_INT0_STATUS.</description>
5839              <bitRange>[9:0]</bitRange>
5840              <access>read-only</access>
5841            </field>
5842            <field>
5843              <name>SYSTEM_INT_VALID</name>
5844              <description>See description of CM0_INT0_STATUS.</description>
5845              <bitRange>[31:31]</bitRange>
5846              <access>read-only</access>
5847            </field>
5848          </fields>
5849        </register>
5850        <register>
5851          <name>CM4_INT1_STATUS</name>
5852          <description>CM4 interrupt 1 status</description>
5853          <addressOffset>0x104</addressOffset>
5854          <size>32</size>
5855          <access>read-only</access>
5856          <resetValue>0x0</resetValue>
5857          <resetMask>0x80000000</resetMask>
5858          <fields>
5859            <field>
5860              <name>SYSTEM_INT_IDX</name>
5861              <description>Lowest CM4 activated system interrupt index for CPU interrupt 1.
5862
5863See description of CM0_INT0_STATUS.</description>
5864              <bitRange>[9:0]</bitRange>
5865              <access>read-only</access>
5866            </field>
5867            <field>
5868              <name>SYSTEM_INT_VALID</name>
5869              <description>See description of CM0_INT0_STATUS.</description>
5870              <bitRange>[31:31]</bitRange>
5871              <access>read-only</access>
5872            </field>
5873          </fields>
5874        </register>
5875        <register>
5876          <name>CM4_INT2_STATUS</name>
5877          <description>CM4 interrupt 2 status</description>
5878          <addressOffset>0x108</addressOffset>
5879          <size>32</size>
5880          <access>read-only</access>
5881          <resetValue>0x0</resetValue>
5882          <resetMask>0x80000000</resetMask>
5883          <fields>
5884            <field>
5885              <name>SYSTEM_INT_IDX</name>
5886              <description>Lowest CM4 activated system interrupt index for CPU interrupt 2.
5887
5888See description of CM0_INT0_STATUS.</description>
5889              <bitRange>[9:0]</bitRange>
5890              <access>read-only</access>
5891            </field>
5892            <field>
5893              <name>SYSTEM_INT_VALID</name>
5894              <description>See description of CM0_INT0_STATUS.</description>
5895              <bitRange>[31:31]</bitRange>
5896              <access>read-only</access>
5897            </field>
5898          </fields>
5899        </register>
5900        <register>
5901          <name>CM4_INT3_STATUS</name>
5902          <description>CM4 interrupt 3 status</description>
5903          <addressOffset>0x10C</addressOffset>
5904          <size>32</size>
5905          <access>read-only</access>
5906          <resetValue>0x0</resetValue>
5907          <resetMask>0x80000000</resetMask>
5908          <fields>
5909            <field>
5910              <name>SYSTEM_INT_IDX</name>
5911              <description>Lowest CM4 activated system interrupt index for CPU interrupt 3.
5912
5913See description of CM0_INT0_STATUS.</description>
5914              <bitRange>[9:0]</bitRange>
5915              <access>read-only</access>
5916            </field>
5917            <field>
5918              <name>SYSTEM_INT_VALID</name>
5919              <description>See description of CM0_INT0_STATUS.</description>
5920              <bitRange>[31:31]</bitRange>
5921              <access>read-only</access>
5922            </field>
5923          </fields>
5924        </register>
5925        <register>
5926          <name>CM4_INT4_STATUS</name>
5927          <description>CM4 interrupt 4 status</description>
5928          <addressOffset>0x110</addressOffset>
5929          <size>32</size>
5930          <access>read-only</access>
5931          <resetValue>0x0</resetValue>
5932          <resetMask>0x80000000</resetMask>
5933          <fields>
5934            <field>
5935              <name>SYSTEM_INT_IDX</name>
5936              <description>Lowest CM4 activated system interrupt index for CPU interrupt 4.
5937
5938See description of CM0_INT0_STATUS.</description>
5939              <bitRange>[9:0]</bitRange>
5940              <access>read-only</access>
5941            </field>
5942            <field>
5943              <name>SYSTEM_INT_VALID</name>
5944              <description>See description of CM0_INT0_STATUS.</description>
5945              <bitRange>[31:31]</bitRange>
5946              <access>read-only</access>
5947            </field>
5948          </fields>
5949        </register>
5950        <register>
5951          <name>CM4_INT5_STATUS</name>
5952          <description>CM4 interrupt 5 status</description>
5953          <addressOffset>0x114</addressOffset>
5954          <size>32</size>
5955          <access>read-only</access>
5956          <resetValue>0x0</resetValue>
5957          <resetMask>0x80000000</resetMask>
5958          <fields>
5959            <field>
5960              <name>SYSTEM_INT_IDX</name>
5961              <description>Lowest CM4 activated system interrupt index for CPU interrupt 5.
5962
5963See description of CM0_INT0_STATUS.</description>
5964              <bitRange>[9:0]</bitRange>
5965              <access>read-only</access>
5966            </field>
5967            <field>
5968              <name>SYSTEM_INT_VALID</name>
5969              <description>See description of CM0_INT0_STATUS.</description>
5970              <bitRange>[31:31]</bitRange>
5971              <access>read-only</access>
5972            </field>
5973          </fields>
5974        </register>
5975        <register>
5976          <name>CM4_INT6_STATUS</name>
5977          <description>CM4 interrupt 6 status</description>
5978          <addressOffset>0x118</addressOffset>
5979          <size>32</size>
5980          <access>read-only</access>
5981          <resetValue>0x0</resetValue>
5982          <resetMask>0x80000000</resetMask>
5983          <fields>
5984            <field>
5985              <name>SYSTEM_INT_IDX</name>
5986              <description>Lowest CM4 activated system interrupt index for CPU interrupt 6.
5987
5988See description of CM0_INT0_STATUS.</description>
5989              <bitRange>[9:0]</bitRange>
5990              <access>read-only</access>
5991            </field>
5992            <field>
5993              <name>SYSTEM_INT_VALID</name>
5994              <description>See description of CM0_INT0_STATUS.</description>
5995              <bitRange>[31:31]</bitRange>
5996              <access>read-only</access>
5997            </field>
5998          </fields>
5999        </register>
6000        <register>
6001          <name>CM4_INT7_STATUS</name>
6002          <description>CM4 interrupt 7 status</description>
6003          <addressOffset>0x11C</addressOffset>
6004          <size>32</size>
6005          <access>read-only</access>
6006          <resetValue>0x0</resetValue>
6007          <resetMask>0x80000000</resetMask>
6008          <fields>
6009            <field>
6010              <name>SYSTEM_INT_IDX</name>
6011              <description>Lowest CM4 activated system interrupt index for CPU interrupt 7.
6012
6013See description of CM0_INT0_STATUS.</description>
6014              <bitRange>[9:0]</bitRange>
6015              <access>read-only</access>
6016            </field>
6017            <field>
6018              <name>SYSTEM_INT_VALID</name>
6019              <description>See description of CM0_INT0_STATUS.</description>
6020              <bitRange>[31:31]</bitRange>
6021              <access>read-only</access>
6022            </field>
6023          </fields>
6024        </register>
6025        <register>
6026          <name>CM4_VECTOR_TABLE_BASE</name>
6027          <description>CM4 vector table base</description>
6028          <addressOffset>0x200</addressOffset>
6029          <size>32</size>
6030          <access>read-write</access>
6031          <resetValue>0x0</resetValue>
6032          <resetMask>0xFFFFFC00</resetMask>
6033          <fields>
6034            <field>
6035              <name>ADDR22</name>
6036              <description>Address of CM4 vector table. This register is used for CM4 warm and cold boot purposes: the CM0+ CPU initializes the CM4_VECTOR_TABLE_BASE register and the CM4 boot code uses the register to initialize the CM4 internal VTOR register.
6037
6038Note: the CM4 vector table is at an address that is a 1024 B multiple.</description>
6039              <bitRange>[31:10]</bitRange>
6040              <access>read-write</access>
6041            </field>
6042          </fields>
6043        </register>
6044        <register>
6045          <dim>4</dim>
6046          <dimIncrement>4</dimIncrement>
6047          <name>CM4_NMI_CTL[%s]</name>
6048          <description>CM4 NMI control</description>
6049          <addressOffset>0x240</addressOffset>
6050          <size>32</size>
6051          <access>read-write</access>
6052          <resetValue>0x3FF</resetValue>
6053          <resetMask>0x3FF</resetMask>
6054          <fields>
6055            <field>
6056              <name>SYSTEM_INT_IDX</name>
6057              <description>System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.</description>
6058              <bitRange>[9:0]</bitRange>
6059              <access>read-write</access>
6060            </field>
6061          </fields>
6062        </register>
6063        <register>
6064          <name>UDB_PWR_CTL</name>
6065          <description>UDB power control</description>
6066          <addressOffset>0x300</addressOffset>
6067          <size>32</size>
6068          <access>read-write</access>
6069          <resetValue>0xFA050001</resetValue>
6070          <resetMask>0xFFFF0003</resetMask>
6071          <fields>
6072            <field>
6073              <name>PWR_MODE</name>
6074              <description>Set Power mode for UDBs</description>
6075              <bitRange>[1:0]</bitRange>
6076              <access>read-write</access>
6077              <enumeratedValues>
6078                <enumeratedValue>
6079                  <name>OFF</name>
6080                  <description>See CM4_PWR_CTL</description>
6081                  <value>0</value>
6082                </enumeratedValue>
6083                <enumeratedValue>
6084                  <name>RESET</name>
6085                  <description>See CM4_PWR_CTL</description>
6086                  <value>1</value>
6087                </enumeratedValue>
6088                <enumeratedValue>
6089                  <name>RETAINED</name>
6090                  <description>See CM4_PWR_CTL</description>
6091                  <value>2</value>
6092                </enumeratedValue>
6093                <enumeratedValue>
6094                  <name>ENABLED</name>
6095                  <description>See CM4_PWR_CTL</description>
6096                  <value>3</value>
6097                </enumeratedValue>
6098              </enumeratedValues>
6099            </field>
6100            <field>
6101              <name>VECTKEYSTAT</name>
6102              <description>Register key (to prevent accidental writes).
6103- Should be written with a 0x05fa key value for the write to take effect.
6104- Always reads as 0xfa05.</description>
6105              <bitRange>[31:16]</bitRange>
6106              <access>read-only</access>
6107            </field>
6108          </fields>
6109        </register>
6110        <register>
6111          <name>UDB_PWR_DELAY_CTL</name>
6112          <description>UDB power control</description>
6113          <addressOffset>0x304</addressOffset>
6114          <size>32</size>
6115          <access>read-write</access>
6116          <resetValue>0x12C</resetValue>
6117          <resetMask>0x3FF</resetMask>
6118          <fields>
6119            <field>
6120              <name>UP</name>
6121              <description>Number clock cycles delay needed after power domain power up</description>
6122              <bitRange>[9:0]</bitRange>
6123              <access>read-write</access>
6124            </field>
6125          </fields>
6126        </register>
6127        <register>
6128          <name>CM0_CTL</name>
6129          <description>CM0+ control</description>
6130          <addressOffset>0x1000</addressOffset>
6131          <size>32</size>
6132          <access>read-write</access>
6133          <resetValue>0xFA050002</resetValue>
6134          <resetMask>0xFFFF0003</resetMask>
6135          <fields>
6136            <field>
6137              <name>SLV_STALL</name>
6138              <description>Processor debug access control:
6139'0': Access.
6140'1': Stall access.
6141
6142This field is used to stall/delay debug accesses. This is useful to protect execution of code that needs to be protected from debug accesses.</description>
6143              <bitRange>[0:0]</bitRange>
6144              <access>read-write</access>
6145            </field>
6146            <field>
6147              <name>ENABLED</name>
6148              <description>Processor enable:
6149'0': Disabled. Processor clock is turned off and reset is activated. After SW clears this field to '0', HW automatically sets this field to '1'. This effectively results in a CM0+ reset, followed by a CM0+ warm boot.
6150'1': Enabled.
6151Note: The intent is that this bit is modified only through an external probe or by the CM4 while the CM0+ is in Sleep or DeepSleep power mode. If this field is cleared to '0' by the CM0+ itself, it should be done under controlled conditions (such that undesirable side effects can be prevented).
6152
6153Note: The CM0+ CPU has a AIRCR.SYSRESETREQ register field that allows the CM0+ to reset the complete device (ENABLED only disables/enables the CM0+), resulting in a warm boot. This CPU register field has similar 'built-in protection' as this CM0_CTL register to prevent accidental system writes (the upper 16-bits of the register need to be written with a 0x05fa key value; see CPU user manual for more details).</description>
6154              <bitRange>[1:1]</bitRange>
6155              <access>read-write</access>
6156            </field>
6157            <field>
6158              <name>VECTKEYSTAT</name>
6159              <description>Register key (to prevent accidental writes).
6160- Should be written with a 0x05fa key value for the write to take effect.
6161- Always reads as 0xfa05.
6162
6163Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.</description>
6164              <bitRange>[31:16]</bitRange>
6165              <access>read-only</access>
6166            </field>
6167          </fields>
6168        </register>
6169        <register>
6170          <name>CM0_STATUS</name>
6171          <description>CM0+ status</description>
6172          <addressOffset>0x1004</addressOffset>
6173          <size>32</size>
6174          <access>read-only</access>
6175          <resetValue>0x0</resetValue>
6176          <resetMask>0x3</resetMask>
6177          <fields>
6178            <field>
6179              <name>SLEEPING</name>
6180              <description>Specifies if the CPU is in Active, Sleep or DeepSleep power mode:
6181- Active power mode: SLEEPING is '0'.
6182- Sleep power mode: SLEEPING is '1' and SLEEPDEEP is '0'.
6183- DeepSleep power mode: SLEEPING is '1' and SLEEPDEEP is '1'.</description>
6184              <bitRange>[0:0]</bitRange>
6185              <access>read-only</access>
6186            </field>
6187            <field>
6188              <name>SLEEPDEEP</name>
6189              <description>Specifies if the CPU is in Sleep or DeepSleep power mode. See SLEEPING field.</description>
6190              <bitRange>[1:1]</bitRange>
6191              <access>read-only</access>
6192            </field>
6193          </fields>
6194        </register>
6195        <register>
6196          <name>CM0_CLOCK_CTL</name>
6197          <description>CM0+ clock control</description>
6198          <addressOffset>0x1008</addressOffset>
6199          <size>32</size>
6200          <access>read-write</access>
6201          <resetValue>0x0</resetValue>
6202          <resetMask>0xFF00FF00</resetMask>
6203          <fields>
6204            <field>
6205              <name>SLOW_INT_DIV</name>
6206              <description>Specifies the slow clock divider (from the peripheral clock 'clk_peri' to the slow clock 'clk_slow'). Integer division by (1+SLOW_INT_DIV). Allows for integer divisions in the range [1, 256] (SLOW_INT_DIV is in the range [0, 255]).
6207
6208Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.</description>
6209              <bitRange>[15:8]</bitRange>
6210              <access>read-write</access>
6211            </field>
6212            <field>
6213              <name>PERI_INT_DIV</name>
6214              <description>Specifies the peripheral clock divider (from the high frequency clock 'clk_hf' to the peripheral clock 'clk_peri'). Integer division by (1+PERI_INT_DIV). Allows for integer divisions in the range [1, 256] (PERI_INT_DIV is in the range [0, 255]).
6215
6216Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to '0' when transitioning from DeepSleep to Active power mode.
6217
6218Note that Fperi &lt;= Fperi_max. Fperi_max is likely to be smaller than Fhf_max. In other words, if Fhf = Fhf_max, PERI_INT_DIV should not be set to '0'.</description>
6219              <bitRange>[31:24]</bitRange>
6220              <access>read-write</access>
6221            </field>
6222          </fields>
6223        </register>
6224        <register>
6225          <name>CM0_INT0_STATUS</name>
6226          <description>CM0+ interrupt 0 status</description>
6227          <addressOffset>0x1100</addressOffset>
6228          <size>32</size>
6229          <access>read-only</access>
6230          <resetValue>0x0</resetValue>
6231          <resetMask>0x80000000</resetMask>
6232          <fields>
6233            <field>
6234              <name>SYSTEM_INT_IDX</name>
6235              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 0.
6236
6237Multiple system interrupts can be mapped on the same CPU interrupt. The selected system interrupt is the system interrupt with the lowest system interrupt index that has an activated interrupt request at the time of the fetch (system_interrupts[SYSTEM_INT_IDX] is '1').
6238
6239The CPU interrupt handler SW can read SYSTEM_INT_IDX to determine the system interrupt that activated the handler.</description>
6240              <bitRange>[9:0]</bitRange>
6241              <access>read-only</access>
6242            </field>
6243            <field>
6244              <name>SYSTEM_INT_VALID</name>
6245              <description>Valid indication for SYSTEM_INT_IDX. When '0', no system interrupt for CPU interrupt 0 is valid/activated.</description>
6246              <bitRange>[31:31]</bitRange>
6247              <access>read-only</access>
6248            </field>
6249          </fields>
6250        </register>
6251        <register>
6252          <name>CM0_INT1_STATUS</name>
6253          <description>CM0+ interrupt 1 status</description>
6254          <addressOffset>0x1104</addressOffset>
6255          <size>32</size>
6256          <access>read-only</access>
6257          <resetValue>0x0</resetValue>
6258          <resetMask>0x80000000</resetMask>
6259          <fields>
6260            <field>
6261              <name>SYSTEM_INT_IDX</name>
6262              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 1.
6263
6264See description of CM0_INT0_STATUS.</description>
6265              <bitRange>[9:0]</bitRange>
6266              <access>read-only</access>
6267            </field>
6268            <field>
6269              <name>SYSTEM_INT_VALID</name>
6270              <description>See description of CM0_INT0_STATUS.</description>
6271              <bitRange>[31:31]</bitRange>
6272              <access>read-only</access>
6273            </field>
6274          </fields>
6275        </register>
6276        <register>
6277          <name>CM0_INT2_STATUS</name>
6278          <description>CM0+ interrupt 2 status</description>
6279          <addressOffset>0x1108</addressOffset>
6280          <size>32</size>
6281          <access>read-only</access>
6282          <resetValue>0x0</resetValue>
6283          <resetMask>0x80000000</resetMask>
6284          <fields>
6285            <field>
6286              <name>SYSTEM_INT_IDX</name>
6287              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 2.
6288
6289See description of CM0_INT0_STATUS.</description>
6290              <bitRange>[9:0]</bitRange>
6291              <access>read-only</access>
6292            </field>
6293            <field>
6294              <name>SYSTEM_INT_VALID</name>
6295              <description>See description of CM0_INT0_STATUS.</description>
6296              <bitRange>[31:31]</bitRange>
6297              <access>read-only</access>
6298            </field>
6299          </fields>
6300        </register>
6301        <register>
6302          <name>CM0_INT3_STATUS</name>
6303          <description>CM0+ interrupt 3 status</description>
6304          <addressOffset>0x110C</addressOffset>
6305          <size>32</size>
6306          <access>read-only</access>
6307          <resetValue>0x0</resetValue>
6308          <resetMask>0x80000000</resetMask>
6309          <fields>
6310            <field>
6311              <name>SYSTEM_INT_IDX</name>
6312              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 3.
6313
6314See description of CM0_INT0_STATUS.</description>
6315              <bitRange>[9:0]</bitRange>
6316              <access>read-only</access>
6317            </field>
6318            <field>
6319              <name>SYSTEM_INT_VALID</name>
6320              <description>See description of CM0_INT0_STATUS.</description>
6321              <bitRange>[31:31]</bitRange>
6322              <access>read-only</access>
6323            </field>
6324          </fields>
6325        </register>
6326        <register>
6327          <name>CM0_INT4_STATUS</name>
6328          <description>CM0+ interrupt 4 status</description>
6329          <addressOffset>0x1110</addressOffset>
6330          <size>32</size>
6331          <access>read-only</access>
6332          <resetValue>0x0</resetValue>
6333          <resetMask>0x80000000</resetMask>
6334          <fields>
6335            <field>
6336              <name>SYSTEM_INT_IDX</name>
6337              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 4.
6338
6339See description of CM0_INT0_STATUS.</description>
6340              <bitRange>[9:0]</bitRange>
6341              <access>read-only</access>
6342            </field>
6343            <field>
6344              <name>SYSTEM_INT_VALID</name>
6345              <description>See description of CM0_INT0_STATUS.</description>
6346              <bitRange>[31:31]</bitRange>
6347              <access>read-only</access>
6348            </field>
6349          </fields>
6350        </register>
6351        <register>
6352          <name>CM0_INT5_STATUS</name>
6353          <description>CM0+ interrupt 5 status</description>
6354          <addressOffset>0x1114</addressOffset>
6355          <size>32</size>
6356          <access>read-only</access>
6357          <resetValue>0x0</resetValue>
6358          <resetMask>0x80000000</resetMask>
6359          <fields>
6360            <field>
6361              <name>SYSTEM_INT_IDX</name>
6362              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 5.
6363
6364See description of CM0_INT0_STATUS.</description>
6365              <bitRange>[9:0]</bitRange>
6366              <access>read-only</access>
6367            </field>
6368            <field>
6369              <name>SYSTEM_INT_VALID</name>
6370              <description>See description of CM0_INT0_STATUS.</description>
6371              <bitRange>[31:31]</bitRange>
6372              <access>read-only</access>
6373            </field>
6374          </fields>
6375        </register>
6376        <register>
6377          <name>CM0_INT6_STATUS</name>
6378          <description>CM0+ interrupt 6 status</description>
6379          <addressOffset>0x1118</addressOffset>
6380          <size>32</size>
6381          <access>read-only</access>
6382          <resetValue>0x0</resetValue>
6383          <resetMask>0x80000000</resetMask>
6384          <fields>
6385            <field>
6386              <name>SYSTEM_INT_IDX</name>
6387              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 6.
6388
6389See description of CM0_INT0_STATUS.</description>
6390              <bitRange>[9:0]</bitRange>
6391              <access>read-only</access>
6392            </field>
6393            <field>
6394              <name>SYSTEM_INT_VALID</name>
6395              <description>See description of CM0_INT0_STATUS.</description>
6396              <bitRange>[31:31]</bitRange>
6397              <access>read-only</access>
6398            </field>
6399          </fields>
6400        </register>
6401        <register>
6402          <name>CM0_INT7_STATUS</name>
6403          <description>CM0+ interrupt 7 status</description>
6404          <addressOffset>0x111C</addressOffset>
6405          <size>32</size>
6406          <access>read-only</access>
6407          <resetValue>0x0</resetValue>
6408          <resetMask>0x80000000</resetMask>
6409          <fields>
6410            <field>
6411              <name>SYSTEM_INT_IDX</name>
6412              <description>Lowest CM0+ activated system interrupt index for CPU interrupt 7.
6413
6414See description of CM0_INT0_STATUS.</description>
6415              <bitRange>[9:0]</bitRange>
6416              <access>read-only</access>
6417            </field>
6418            <field>
6419              <name>SYSTEM_INT_VALID</name>
6420              <description>See description of CM0_INT0_STATUS.</description>
6421              <bitRange>[31:31]</bitRange>
6422              <access>read-only</access>
6423            </field>
6424          </fields>
6425        </register>
6426        <register>
6427          <name>CM0_VECTOR_TABLE_BASE</name>
6428          <description>CM0+ vector table base</description>
6429          <addressOffset>0x1120</addressOffset>
6430          <size>32</size>
6431          <access>read-write</access>
6432          <resetValue>0x0</resetValue>
6433          <resetMask>0xFFFFFF00</resetMask>
6434          <fields>
6435            <field>
6436              <name>ADDR24</name>
6437              <description>Address of CM0+ vector table. This register is used for CM0+ warm boot purposes: the CM0+ warm boot code uses the register to initialize the CM0+ internal VTOR register.
6438
6439Note: the CM0+ vector table is at an address that is a 256 B multiple.</description>
6440              <bitRange>[31:8]</bitRange>
6441              <access>read-write</access>
6442            </field>
6443          </fields>
6444        </register>
6445        <register>
6446          <dim>4</dim>
6447          <dimIncrement>4</dimIncrement>
6448          <name>CM0_NMI_CTL[%s]</name>
6449          <description>CM0+ NMI control</description>
6450          <addressOffset>0x1140</addressOffset>
6451          <size>32</size>
6452          <access>read-write</access>
6453          <resetValue>0x3FF</resetValue>
6454          <resetMask>0x3FF</resetMask>
6455          <fields>
6456            <field>
6457              <name>SYSTEM_INT_IDX</name>
6458              <description>System interrupt select for CPU NMI. The reset value ('1023') ensures that the CPU NMI is NOT connected to any system interrupt after DeepSleep reset.</description>
6459              <bitRange>[9:0]</bitRange>
6460              <access>read-write</access>
6461            </field>
6462          </fields>
6463        </register>
6464        <register>
6465          <name>CM4_PWR_CTL</name>
6466          <description>CM4 power control</description>
6467          <addressOffset>0x1200</addressOffset>
6468          <size>32</size>
6469          <access>read-write</access>
6470          <resetValue>0xFA050001</resetValue>
6471          <resetMask>0xFFFF0003</resetMask>
6472          <fields>
6473            <field>
6474              <name>PWR_MODE</name>
6475              <description>Power mode.</description>
6476              <bitRange>[1:0]</bitRange>
6477              <access>read-write</access>
6478              <enumeratedValues>
6479                <enumeratedValue>
6480                  <name>OFF</name>
6481                  <description>Switch CM4 off
6482Power off, clock off, isolate, reset and no retain.</description>
6483                  <value>0</value>
6484                </enumeratedValue>
6485                <enumeratedValue>
6486                  <name>RESET</name>
6487                  <description>Reset CM4
6488Clock off, no isolated, no retain and reset.
6489
6490Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot.</description>
6491                  <value>1</value>
6492                </enumeratedValue>
6493                <enumeratedValue>
6494                  <name>RETAINED</name>
6495                  <description>Put CM4 in Retained mode
6496This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached.
6497Power off, clock off, isolate, no reset and retain.</description>
6498                  <value>2</value>
6499                </enumeratedValue>
6500                <enumeratedValue>
6501                  <name>ENABLED</name>
6502                  <description>Switch CM4 on.
6503Power on, clock on, no isolate, no reset and no retain.</description>
6504                  <value>3</value>
6505                </enumeratedValue>
6506              </enumeratedValues>
6507            </field>
6508            <field>
6509              <name>VECTKEYSTAT</name>
6510              <description>Register key (to prevent accidental writes).
6511- Should be written with a 0x05fa key value for the write to take effect.
6512- Always reads as 0xfa05.
6513
6514Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.</description>
6515              <bitRange>[31:16]</bitRange>
6516              <access>read-only</access>
6517            </field>
6518          </fields>
6519        </register>
6520        <register>
6521          <name>CM4_PWR_DELAY_CTL</name>
6522          <description>CM4 power control</description>
6523          <addressOffset>0x1204</addressOffset>
6524          <size>32</size>
6525          <access>read-write</access>
6526          <resetValue>0x12C</resetValue>
6527          <resetMask>0x3FF</resetMask>
6528          <fields>
6529            <field>
6530              <name>UP</name>
6531              <description>Number clock cycles delay needed after power domain power up</description>
6532              <bitRange>[9:0]</bitRange>
6533              <access>read-write</access>
6534            </field>
6535          </fields>
6536        </register>
6537        <register>
6538          <name>RAM0_CTL0</name>
6539          <description>RAM 0 control</description>
6540          <addressOffset>0x1300</addressOffset>
6541          <size>32</size>
6542          <access>read-write</access>
6543          <resetValue>0x30001</resetValue>
6544          <resetMask>0x70303</resetMask>
6545          <fields>
6546            <field>
6547              <name>SLOW_WS</name>
6548              <description>Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.</description>
6549              <bitRange>[1:0]</bitRange>
6550              <access>read-write</access>
6551            </field>
6552            <field>
6553              <name>FAST_WS</name>
6554              <description>Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.</description>
6555              <bitRange>[9:8]</bitRange>
6556              <access>read-write</access>
6557            </field>
6558            <field>
6559              <name>ECC_EN</name>
6560              <description>Enable ECC checking:
6561'0': Disabled.
6562'1': Enabled.</description>
6563              <bitRange>[16:16]</bitRange>
6564              <access>read-write</access>
6565            </field>
6566            <field>
6567              <name>ECC_AUTO_CORRECT</name>
6568              <description>HW ECC autocorrect functionality:
6569'0': Disabled.
6570'1': Enabled. HW automatically writes back SRAM with corrected data when a recoverable ECC error is detected.</description>
6571              <bitRange>[17:17]</bitRange>
6572              <access>read-write</access>
6573            </field>
6574            <field>
6575              <name>ECC_INJ_EN</name>
6576              <description>Enable error injection for system SRAM 0.
6577When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of system SRAM 0.</description>
6578              <bitRange>[18:18]</bitRange>
6579              <access>read-write</access>
6580            </field>
6581          </fields>
6582        </register>
6583        <register>
6584          <name>RAM0_STATUS</name>
6585          <description>RAM 0 status</description>
6586          <addressOffset>0x1304</addressOffset>
6587          <size>32</size>
6588          <access>read-only</access>
6589          <resetValue>0x1</resetValue>
6590          <resetMask>0x1</resetMask>
6591          <fields>
6592            <field>
6593              <name>WB_EMPTY</name>
6594              <description>Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode.
6595'0': Write buffer NOT empty.
6596'1': Write buffer empty.
6597
6598Note: the SRAM controller write buffer is only used when ECC checking is enabled. (RAMi_CTL.ECC_EN is '1').</description>
6599              <bitRange>[0:0]</bitRange>
6600              <access>read-only</access>
6601            </field>
6602          </fields>
6603        </register>
6604        <register>
6605          <dim>16</dim>
6606          <dimIncrement>4</dimIncrement>
6607          <name>RAM0_PWR_MACRO_CTL[%s]</name>
6608          <description>RAM 0 power control</description>
6609          <addressOffset>0x1340</addressOffset>
6610          <size>32</size>
6611          <access>read-write</access>
6612          <resetValue>0xFA050003</resetValue>
6613          <resetMask>0xFFFF0003</resetMask>
6614          <fields>
6615            <field>
6616              <name>PWR_MODE</name>
6617              <description>SRAM Power mode.</description>
6618              <bitRange>[1:0]</bitRange>
6619              <access>read-write</access>
6620              <enumeratedValues>
6621                <enumeratedValue>
6622                  <name>OFF</name>
6623                  <description>Turn OFF the SRAM. This will trun OFF both array and periphery power of the SRAM and SRAM memory contents are lost.</description>
6624                  <value>0</value>
6625                </enumeratedValue>
6626                <enumeratedValue>
6627                  <name>RSVD</name>
6628                  <description>undefined</description>
6629                  <value>1</value>
6630                </enumeratedValue>
6631                <enumeratedValue>
6632                  <name>RETAINED</name>
6633                  <description>Keep SRAM in Retained mode. This will turn OFF the SRAM periphery power, but array power is ON to retain memory contents.
6634The SRAM contents will be retained in DeepSleep system power mode.</description>
6635                  <value>2</value>
6636                </enumeratedValue>
6637                <enumeratedValue>
6638                  <name>ENABLED</name>
6639                  <description>Enable SRAM for regular operation.
6640The SRAM contents will be retained in DeepSleep system power mode.</description>
6641                  <value>3</value>
6642                </enumeratedValue>
6643              </enumeratedValues>
6644            </field>
6645            <field>
6646              <name>VECTKEYSTAT</name>
6647              <description>Register key (to prevent accidental writes).
6648- Should be written with a 0x05fa key value for the write to take effect.
6649- Always reads as 0xfa05.
6650
6651Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.</description>
6652              <bitRange>[31:16]</bitRange>
6653              <access>read-only</access>
6654            </field>
6655          </fields>
6656        </register>
6657        <register>
6658          <name>RAM1_CTL0</name>
6659          <description>RAM 1 control</description>
6660          <addressOffset>0x1380</addressOffset>
6661          <size>32</size>
6662          <access>read-write</access>
6663          <resetValue>0x30001</resetValue>
6664          <resetMask>0x70303</resetMask>
6665          <fields>
6666            <field>
6667              <name>SLOW_WS</name>
6668              <description>See RAM0_CTL.</description>
6669              <bitRange>[1:0]</bitRange>
6670              <access>read-write</access>
6671            </field>
6672            <field>
6673              <name>FAST_WS</name>
6674              <description>See RAM0_CTL.</description>
6675              <bitRange>[9:8]</bitRange>
6676              <access>read-write</access>
6677            </field>
6678            <field>
6679              <name>ECC_EN</name>
6680              <description>See RAM0_CTL.</description>
6681              <bitRange>[16:16]</bitRange>
6682              <access>read-write</access>
6683            </field>
6684            <field>
6685              <name>ECC_AUTO_CORRECT</name>
6686              <description>See RAM0_CTL.</description>
6687              <bitRange>[17:17]</bitRange>
6688              <access>read-write</access>
6689            </field>
6690            <field>
6691              <name>ECC_INJ_EN</name>
6692              <description>See RAM0_CTL.</description>
6693              <bitRange>[18:18]</bitRange>
6694              <access>read-write</access>
6695            </field>
6696          </fields>
6697        </register>
6698        <register>
6699          <name>RAM1_STATUS</name>
6700          <description>RAM 1 status</description>
6701          <addressOffset>0x1384</addressOffset>
6702          <size>32</size>
6703          <access>read-only</access>
6704          <resetValue>0x1</resetValue>
6705          <resetMask>0x1</resetMask>
6706          <fields>
6707            <field>
6708              <name>WB_EMPTY</name>
6709              <description>See RAM0_STATUS.</description>
6710              <bitRange>[0:0]</bitRange>
6711              <access>read-only</access>
6712            </field>
6713          </fields>
6714        </register>
6715        <register>
6716          <name>RAM1_PWR_CTL</name>
6717          <description>RAM 1 power control</description>
6718          <addressOffset>0x1388</addressOffset>
6719          <size>32</size>
6720          <access>read-write</access>
6721          <resetValue>0xFA050003</resetValue>
6722          <resetMask>0xFFFF0003</resetMask>
6723          <fields>
6724            <field>
6725              <name>PWR_MODE</name>
6726              <description>Power mode.</description>
6727              <bitRange>[1:0]</bitRange>
6728              <access>read-write</access>
6729              <enumeratedValues>
6730                <enumeratedValue>
6731                  <name>OFF</name>
6732                  <description>See RAM0_PWR_MACRO_CTL.</description>
6733                  <value>0</value>
6734                </enumeratedValue>
6735                <enumeratedValue>
6736                  <name>RSVD</name>
6737                  <description>undefined</description>
6738                  <value>1</value>
6739                </enumeratedValue>
6740                <enumeratedValue>
6741                  <name>RETAINED</name>
6742                  <description>See RAM0_PWR_MACRO_CTL.</description>
6743                  <value>2</value>
6744                </enumeratedValue>
6745                <enumeratedValue>
6746                  <name>ENABLED</name>
6747                  <description>See RAM0_PWR_MACRO_CTL.</description>
6748                  <value>3</value>
6749                </enumeratedValue>
6750              </enumeratedValues>
6751            </field>
6752            <field>
6753              <name>VECTKEYSTAT</name>
6754              <description>See RAM0_PWR_MACRO_CTL.</description>
6755              <bitRange>[31:16]</bitRange>
6756              <access>read-only</access>
6757            </field>
6758          </fields>
6759        </register>
6760        <register>
6761          <name>RAM2_CTL0</name>
6762          <description>RAM 2 control</description>
6763          <addressOffset>0x13A0</addressOffset>
6764          <size>32</size>
6765          <access>read-write</access>
6766          <resetValue>0x30001</resetValue>
6767          <resetMask>0x70303</resetMask>
6768          <fields>
6769            <field>
6770              <name>SLOW_WS</name>
6771              <description>See RAM0_CTL.</description>
6772              <bitRange>[1:0]</bitRange>
6773              <access>read-write</access>
6774            </field>
6775            <field>
6776              <name>FAST_WS</name>
6777              <description>See RAM0_CTL.</description>
6778              <bitRange>[9:8]</bitRange>
6779              <access>read-write</access>
6780            </field>
6781            <field>
6782              <name>ECC_EN</name>
6783              <description>See RAM0_CTL.</description>
6784              <bitRange>[16:16]</bitRange>
6785              <access>read-write</access>
6786            </field>
6787            <field>
6788              <name>ECC_AUTO_CORRECT</name>
6789              <description>See RAM0_CTL.</description>
6790              <bitRange>[17:17]</bitRange>
6791              <access>read-write</access>
6792            </field>
6793            <field>
6794              <name>ECC_INJ_EN</name>
6795              <description>See RAM0_CTL.</description>
6796              <bitRange>[18:18]</bitRange>
6797              <access>read-write</access>
6798            </field>
6799          </fields>
6800        </register>
6801        <register>
6802          <name>RAM2_STATUS</name>
6803          <description>RAM 2 status</description>
6804          <addressOffset>0x13A4</addressOffset>
6805          <size>32</size>
6806          <access>read-only</access>
6807          <resetValue>0x1</resetValue>
6808          <resetMask>0x1</resetMask>
6809          <fields>
6810            <field>
6811              <name>WB_EMPTY</name>
6812              <description>See RAM0_STATUS.</description>
6813              <bitRange>[0:0]</bitRange>
6814              <access>read-only</access>
6815            </field>
6816          </fields>
6817        </register>
6818        <register>
6819          <name>RAM2_PWR_CTL</name>
6820          <description>RAM 2 power control</description>
6821          <addressOffset>0x13A8</addressOffset>
6822          <size>32</size>
6823          <access>read-write</access>
6824          <resetValue>0xFA050003</resetValue>
6825          <resetMask>0xFFFF0003</resetMask>
6826          <fields>
6827            <field>
6828              <name>PWR_MODE</name>
6829              <description>Power mode.</description>
6830              <bitRange>[1:0]</bitRange>
6831              <access>read-write</access>
6832              <enumeratedValues>
6833                <enumeratedValue>
6834                  <name>OFF</name>
6835                  <description>See RAM0_PWR_MACRO_CTL.</description>
6836                  <value>0</value>
6837                </enumeratedValue>
6838                <enumeratedValue>
6839                  <name>RSVD</name>
6840                  <description>undefined</description>
6841                  <value>1</value>
6842                </enumeratedValue>
6843                <enumeratedValue>
6844                  <name>RETAINED</name>
6845                  <description>See RAM0_PWR_MACRO_CTL.</description>
6846                  <value>2</value>
6847                </enumeratedValue>
6848                <enumeratedValue>
6849                  <name>ENABLED</name>
6850                  <description>See RAM0_PWR_MACRO_CTL.</description>
6851                  <value>3</value>
6852                </enumeratedValue>
6853              </enumeratedValues>
6854            </field>
6855            <field>
6856              <name>VECTKEYSTAT</name>
6857              <description>See RAM0_PWR_MACRO_CTL.</description>
6858              <bitRange>[31:16]</bitRange>
6859              <access>read-only</access>
6860            </field>
6861          </fields>
6862        </register>
6863        <register>
6864          <name>RAM_PWR_DELAY_CTL</name>
6865          <description>Power up delay used for all SRAM power domains</description>
6866          <addressOffset>0x13C0</addressOffset>
6867          <size>32</size>
6868          <access>read-write</access>
6869          <resetValue>0x96</resetValue>
6870          <resetMask>0x3FF</resetMask>
6871          <fields>
6872            <field>
6873              <name>UP</name>
6874              <description>Number clock cycles (clk_slow) delay needed after power domain power up</description>
6875              <bitRange>[9:0]</bitRange>
6876              <access>read-write</access>
6877            </field>
6878          </fields>
6879        </register>
6880        <register>
6881          <name>ROM_CTL</name>
6882          <description>ROM control</description>
6883          <addressOffset>0x13C4</addressOffset>
6884          <size>32</size>
6885          <access>read-write</access>
6886          <resetValue>0x1</resetValue>
6887          <resetMask>0x303</resetMask>
6888          <fields>
6889            <field>
6890              <name>SLOW_WS</name>
6891              <description>Memory wait states for the slow clock domain ('clk_slow'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
6892
6893Timing paths to and from the memory have a (fixed) minimum duration  that always needs to be considered/met. The 'clk_hf' clock domain frequency determines this field's value such that the timing paths minimum duration is met.
6894ROM_CTL.SLOW_WS = '0' when clk_hf &lt;=100 MHz.
6895ROM_CTL.SLOW_WS = '1' when 100MHz &lt; clk_hf &lt;=clk_hf_max.
6896Note: clk_hf_max depends on the target device. Refer datasheet.</description>
6897              <bitRange>[1:0]</bitRange>
6898              <access>read-write</access>
6899            </field>
6900            <field>
6901              <name>FAST_WS</name>
6902              <description>Memory wait states for the fast clock domain ('clk_fast'). The number of wait states is expressed in 'clk_hf' clock domain cycles.
6903ROM_CTL.FAST_WS = '0' when clk_hf &lt;= clk_hf_max.</description>
6904              <bitRange>[9:8]</bitRange>
6905              <access>read-write</access>
6906            </field>
6907          </fields>
6908        </register>
6909        <register>
6910          <name>ECC_CTL</name>
6911          <description>ECC control</description>
6912          <addressOffset>0x13C8</addressOffset>
6913          <size>32</size>
6914          <access>read-write</access>
6915          <resetValue>0x0</resetValue>
6916          <resetMask>0xFFFFFFFF</resetMask>
6917          <fields>
6918            <field>
6919              <name>WORD_ADDR</name>
6920              <description>Specifies the word address where an error will be injected.
6921- On a write transfer to this SRAM address and when the corresponding RAM0/RAM1/RAM2_CTL0.ECC_INJ_EN bit is '1', the parity (PARITY) is injected.
6922This field needs to be written with the offset address within the memory, divided by 4.
6923For example, if the RAM1 start address is 0x08010000, and an error is to be injected to address 0x08010040, then this field needs to configured to 0x000010.</description>
6924              <bitRange>[24:0]</bitRange>
6925              <access>read-write</access>
6926            </field>
6927            <field>
6928              <name>PARITY</name>
6929              <description>ECC parity to use for ECC error injection at address WORD_ADDR.</description>
6930              <bitRange>[31:25]</bitRange>
6931              <access>read-write</access>
6932            </field>
6933          </fields>
6934        </register>
6935        <register>
6936          <name>PRODUCT_ID</name>
6937          <description>Product identifier and version (same as CoreSight RomTables)</description>
6938          <addressOffset>0x1400</addressOffset>
6939          <size>32</size>
6940          <access>read-only</access>
6941          <resetValue>0x0</resetValue>
6942          <resetMask>0xFFF</resetMask>
6943          <fields>
6944            <field>
6945              <name>FAMILY_ID</name>
6946              <description>Family ID. Common ID for a product family.</description>
6947              <bitRange>[11:0]</bitRange>
6948              <access>read-only</access>
6949            </field>
6950            <field>
6951              <name>MAJOR_REV</name>
6952              <description>Major Revision, starts with 1, increments with all layer tape-out (implemented with metal ECO-able  tie-off)</description>
6953              <bitRange>[19:16]</bitRange>
6954              <access>read-only</access>
6955            </field>
6956            <field>
6957              <name>MINOR_REV</name>
6958              <description>Minor Revision, starts with 1, increments with metal layer only tape-out (implemented with metal ECO-able  tie-off)</description>
6959              <bitRange>[23:20]</bitRange>
6960              <access>read-only</access>
6961            </field>
6962          </fields>
6963        </register>
6964        <register>
6965          <name>DP_STATUS</name>
6966          <description>Debug port status</description>
6967          <addressOffset>0x1410</addressOffset>
6968          <size>32</size>
6969          <access>read-only</access>
6970          <resetValue>0x4</resetValue>
6971          <resetMask>0x7</resetMask>
6972          <fields>
6973            <field>
6974              <name>SWJ_CONNECTED</name>
6975              <description>Specifies if the SWJ debug port is connected; i.e. debug host interface is active:
6976'0': Not connected/not active.
6977'1': Connected/active.</description>
6978              <bitRange>[0:0]</bitRange>
6979              <access>read-only</access>
6980            </field>
6981            <field>
6982              <name>SWJ_DEBUG_EN</name>
6983              <description>Specifies if SWJ debug is enabled, i.e. CDBGPWRUPACK is '1' and thus debug clocks are on:
6984'0': Disabled.
6985'1': Enabled.</description>
6986              <bitRange>[1:1]</bitRange>
6987              <access>read-only</access>
6988            </field>
6989            <field>
6990              <name>SWJ_JTAG_SEL</name>
6991              <description>Specifies if the JTAG or SWD interface is selected. This signal is valid when DP_CTL.PTM_SEL is '0' (SWJ mode selected) and SWJ_CONNECTED is '1' (SWJ is connected).
6992'0': SWD selected.
6993'1': JTAG selected.</description>
6994              <bitRange>[2:2]</bitRange>
6995              <access>read-only</access>
6996            </field>
6997          </fields>
6998        </register>
6999        <register>
7000          <name>AP_CTL</name>
7001          <description>Access port control</description>
7002          <addressOffset>0x1414</addressOffset>
7003          <size>32</size>
7004          <access>read-write</access>
7005          <resetValue>0x0</resetValue>
7006          <resetMask>0x70007</resetMask>
7007          <fields>
7008            <field>
7009              <name>CM0_ENABLE</name>
7010              <description>Enables the CM0 AP interface:
7011'0': Disabled.
7012'1': Enabled.</description>
7013              <bitRange>[0:0]</bitRange>
7014              <access>read-write</access>
7015            </field>
7016            <field>
7017              <name>CM4_ENABLE</name>
7018              <description>Enables the CM4 AP interface:
7019'0': Disabled.
7020'1': Enabled.</description>
7021              <bitRange>[1:1]</bitRange>
7022              <access>read-write</access>
7023            </field>
7024            <field>
7025              <name>SYS_ENABLE</name>
7026              <description>Enables the system AP interface:
7027'0': Disabled.
7028'1': Enabled.</description>
7029              <bitRange>[2:2]</bitRange>
7030              <access>read-write</access>
7031            </field>
7032            <field>
7033              <name>CM0_DISABLE</name>
7034              <description>Disables the CM0 AP interface:
7035'0': Enabled.
7036'1': Disabled.
7037
7038Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM0_DISABLE is '0' and CM0_ENABLE is '1'.</description>
7039              <bitRange>[16:16]</bitRange>
7040              <access>read-write</access>
7041            </field>
7042            <field>
7043              <name>CM4_DISABLE</name>
7044              <description>Disables the CM4 AP interface:
7045'0': Enabled.
7046'1': Disabled.
7047
7048Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when CM4_DISABLE is '0' and CM4_ENABLE is '1'.</description>
7049              <bitRange>[17:17]</bitRange>
7050              <access>read-write</access>
7051            </field>
7052            <field>
7053              <name>SYS_DISABLE</name>
7054              <description>Disables the system AP interface:
7055'0': Enabled.
7056'1': Disabled.
7057
7058Typically, this field is set by the Cypress boot code with information from eFUSE. The access port is only enabled when SYS_DISABLE is '0' and SYS_ENABLE is '1'.</description>
7059              <bitRange>[18:18]</bitRange>
7060              <access>read-write</access>
7061            </field>
7062          </fields>
7063        </register>
7064        <register>
7065          <name>BUFF_CTL</name>
7066          <description>Buffer control</description>
7067          <addressOffset>0x1500</addressOffset>
7068          <size>32</size>
7069          <access>read-write</access>
7070          <resetValue>0x1</resetValue>
7071          <resetMask>0x1</resetMask>
7072          <fields>
7073            <field>
7074              <name>WRITE_BUFF</name>
7075              <description>Specifies if write transfer can be buffered in the bus infrastructure bridges:
7076'0': Write transfers are not buffered, independent of the transfer's bufferable attribute.
7077'1': Write transfers can be buffered, if the transfer's bufferable attribute indicates that the transfer is a bufferable/posted write.</description>
7078              <bitRange>[0:0]</bitRange>
7079              <access>read-write</access>
7080            </field>
7081          </fields>
7082        </register>
7083        <register>
7084          <name>SYSTICK_CTL</name>
7085          <description>SysTick timer control</description>
7086          <addressOffset>0x1600</addressOffset>
7087          <size>32</size>
7088          <access>read-write</access>
7089          <resetValue>0x40000147</resetValue>
7090          <resetMask>0xC3FFFFFF</resetMask>
7091          <fields>
7092            <field>
7093              <name>TENMS</name>
7094              <description>Specifies the number of clock source cycles (minus 1) that make up 10 ms. E.g., for a 32,768 Hz reference clock, TENMS is 328 - 1 = 327.</description>
7095              <bitRange>[23:0]</bitRange>
7096              <access>read-write</access>
7097            </field>
7098            <field>
7099              <name>CLOCK_SOURCE</name>
7100              <description>Specifies an external clock source:
7101'0': The low frequency clock 'clk_lf' is selected. The precision of this clock depends on whether the low frequency clock source is a SRSS internal RC oscillator (imprecise) or a device external crystal oscillator (precise).
7102'1': The internal main oscillator (IMO) clock 'clk_imo' is selected. The MXS40 platform uses a fixed frequency IMO clock.
7103o '2': The external crystal oscillator (ECO) clock 'clk_eco' is selected.
7104'3': The SRSS 'clk_timer' is selected ('clk_timer' is a divided/gated version of 'clk_hf' or 'clk_imo').
7105
7106Note: If NOREF is '1', the CLOCK_SOURCE value is NOT used.
7107Note: It is SW's responsibility to provide the correct NOREF, SKEW and TENMS field values for the selected clock source.</description>
7108              <bitRange>[25:24]</bitRange>
7109              <access>read-write</access>
7110            </field>
7111            <field>
7112              <name>SKEW</name>
7113              <description>Specifies the precision of the clock source and if the TENMS field represents exactly 10 ms (clock source frequency is a multiple of 100 Hz). This affects the suitability of the SysTick timer as a SW real-time clock:
7114'0': Precise.
7115'1': Imprecise.</description>
7116              <bitRange>[30:30]</bitRange>
7117              <access>read-write</access>
7118            </field>
7119            <field>
7120              <name>NOREF</name>
7121              <description>Specifies if an external clock source is provided:
7122'0': An external clock source is provided.
7123'1': An external clock source is NOT provided and only the CPU internal clock can be used as SysTick timer clock source.</description>
7124              <bitRange>[31:31]</bitRange>
7125              <access>read-write</access>
7126            </field>
7127          </fields>
7128        </register>
7129        <register>
7130          <name>MBIST_STAT</name>
7131          <description>Memory BIST status</description>
7132          <addressOffset>0x1704</addressOffset>
7133          <size>32</size>
7134          <access>read-only</access>
7135          <resetValue>0x0</resetValue>
7136          <resetMask>0x3</resetMask>
7137          <fields>
7138            <field>
7139              <name>SFP_READY</name>
7140              <description>Flag indicating the BIST run is done. Note that after starting a BIST run this flag must be set before a new run can be started. For the first BIST run this will be 0.</description>
7141              <bitRange>[0:0]</bitRange>
7142              <access>read-only</access>
7143            </field>
7144            <field>
7145              <name>SFP_FAIL</name>
7146              <description>Report status of the BIST run, only valid if SFP_READY=1</description>
7147              <bitRange>[1:1]</bitRange>
7148              <access>read-only</access>
7149            </field>
7150          </fields>
7151        </register>
7152        <register>
7153          <name>CAL_SUP_SET</name>
7154          <description>Calibration support set and read</description>
7155          <addressOffset>0x1800</addressOffset>
7156          <size>32</size>
7157          <access>read-write</access>
7158          <resetValue>0x0</resetValue>
7159          <resetMask>0xFFFFFFFF</resetMask>
7160          <fields>
7161            <field>
7162              <name>DATA</name>
7163              <description>Read without side effect, write 1 to set</description>
7164              <bitRange>[31:0]</bitRange>
7165              <access>read-write</access>
7166            </field>
7167          </fields>
7168        </register>
7169        <register>
7170          <name>CAL_SUP_CLR</name>
7171          <description>Calibration support clear and reset</description>
7172          <addressOffset>0x1804</addressOffset>
7173          <size>32</size>
7174          <access>read-write</access>
7175          <resetValue>0x0</resetValue>
7176          <resetMask>0xFFFFFFFF</resetMask>
7177          <fields>
7178            <field>
7179              <name>DATA</name>
7180              <description>Read side effect: when read all bits are cleared, write 1 to clear a specific bit
7181Note: no exception for the debug host, it also causes the read side effect</description>
7182              <bitRange>[31:0]</bitRange>
7183              <access>read-write</access>
7184            </field>
7185          </fields>
7186        </register>
7187        <register>
7188          <name>CM0_PC_CTL</name>
7189          <description>CM0+ protection context control</description>
7190          <addressOffset>0x2000</addressOffset>
7191          <size>32</size>
7192          <access>read-write</access>
7193          <resetValue>0x0</resetValue>
7194          <resetMask>0xF</resetMask>
7195          <fields>
7196            <field>
7197              <name>VALID</name>
7198              <description>Valid fields for the protection context handler CM0_PCi_HANDLER registers:
7199Bit 0: Valid field for CM0_PC0_HANDLER.
7200Bit 1: Valid field for CM0_PC1_HANDLER.
7201Bit 2: Valid field for CM0_PC2_HANDLER.
7202Bit 3: Valid field for CM0_PC3_HANDLER.</description>
7203              <bitRange>[3:0]</bitRange>
7204              <access>read-write</access>
7205            </field>
7206          </fields>
7207        </register>
7208        <register>
7209          <name>CM0_PC0_HANDLER</name>
7210          <description>CM0+ protection context 0 handler</description>
7211          <addressOffset>0x2040</addressOffset>
7212          <size>32</size>
7213          <access>read-write</access>
7214          <resetValue>0x0</resetValue>
7215          <resetMask>0xFFFFFFFF</resetMask>
7216          <fields>
7217            <field>
7218              <name>ADDR</name>
7219              <description>Address of the protection context 0 handler. This field is used to detect entry to Cypress 'trusted' code through an exception/interrupt.</description>
7220              <bitRange>[31:0]</bitRange>
7221              <access>read-write</access>
7222            </field>
7223          </fields>
7224        </register>
7225        <register>
7226          <name>CM0_PC1_HANDLER</name>
7227          <description>CM0+ protection context 1 handler</description>
7228          <addressOffset>0x2044</addressOffset>
7229          <size>32</size>
7230          <access>read-write</access>
7231          <resetValue>0x0</resetValue>
7232          <resetMask>0xFFFFFFFF</resetMask>
7233          <fields>
7234            <field>
7235              <name>ADDR</name>
7236              <description>Address of the protection context 1 handler.</description>
7237              <bitRange>[31:0]</bitRange>
7238              <access>read-write</access>
7239            </field>
7240          </fields>
7241        </register>
7242        <register>
7243          <name>CM0_PC2_HANDLER</name>
7244          <description>CM0+ protection context 2 handler</description>
7245          <addressOffset>0x2048</addressOffset>
7246          <size>32</size>
7247          <access>read-write</access>
7248          <resetValue>0x0</resetValue>
7249          <resetMask>0xFFFFFFFF</resetMask>
7250          <fields>
7251            <field>
7252              <name>ADDR</name>
7253              <description>Address of the protection context 2 handler.</description>
7254              <bitRange>[31:0]</bitRange>
7255              <access>read-write</access>
7256            </field>
7257          </fields>
7258        </register>
7259        <register>
7260          <name>CM0_PC3_HANDLER</name>
7261          <description>CM0+ protection context 3 handler</description>
7262          <addressOffset>0x204C</addressOffset>
7263          <size>32</size>
7264          <access>read-write</access>
7265          <resetValue>0x0</resetValue>
7266          <resetMask>0xFFFFFFFF</resetMask>
7267          <fields>
7268            <field>
7269              <name>ADDR</name>
7270              <description>Address of the protection context 3 handler.</description>
7271              <bitRange>[31:0]</bitRange>
7272              <access>read-write</access>
7273            </field>
7274          </fields>
7275        </register>
7276        <register>
7277          <name>PROTECTION</name>
7278          <description>Protection status</description>
7279          <addressOffset>0x20C4</addressOffset>
7280          <size>32</size>
7281          <access>read-write</access>
7282          <resetValue>0x0</resetValue>
7283          <resetMask>0x7</resetMask>
7284          <fields>
7285            <field>
7286              <name>STATE</name>
7287              <description>Protection state:
7288'0': UNKNOWN.
7289'1': VIRGIN.
7290'2': NORMAL.
7291'3': SECURE.
7292'4': DEAD.
7293
7294The following state transitions are allowed (and enforced by HW):
7295- UNKNOWN =&gt; VIRGIN/NORMAL/SECURE/DEAD
7296- NORMAL =&gt; DEAD
7297- SECURE =&gt; DEAD
7298An attempt to make a NOT allowed state transition will NOT affect this register field.</description>
7299              <bitRange>[2:0]</bitRange>
7300              <access>read-write</access>
7301            </field>
7302          </fields>
7303        </register>
7304        <register>
7305          <name>TRIM_ROM_CTL</name>
7306          <description>ROM trim control</description>
7307          <addressOffset>0x2100</addressOffset>
7308          <size>32</size>
7309          <access>read-write</access>
7310          <resetValue>0x0</resetValue>
7311          <resetMask>0xFFFFFFFF</resetMask>
7312          <fields>
7313            <field>
7314              <name>TRIM</name>
7315              <description>N/A</description>
7316              <bitRange>[31:0]</bitRange>
7317              <access>read-write</access>
7318            </field>
7319          </fields>
7320        </register>
7321        <register>
7322          <name>TRIM_RAM_CTL</name>
7323          <description>RAM trim control</description>
7324          <addressOffset>0x2104</addressOffset>
7325          <size>32</size>
7326          <access>read-write</access>
7327          <resetValue>0x0</resetValue>
7328          <resetMask>0xFFFFFFFF</resetMask>
7329          <fields>
7330            <field>
7331              <name>TRIM</name>
7332              <description>N/A</description>
7333              <bitRange>[31:0]</bitRange>
7334              <access>read-write</access>
7335            </field>
7336          </fields>
7337        </register>
7338        <register>
7339          <dim>1023</dim>
7340          <dimIncrement>4</dimIncrement>
7341          <name>CM0_SYSTEM_INT_CTL[%s]</name>
7342          <description>CM0+ system interrupt control</description>
7343          <addressOffset>0x8000</addressOffset>
7344          <size>32</size>
7345          <access>read-write</access>
7346          <resetValue>0x0</resetValue>
7347          <resetMask>0x80000000</resetMask>
7348          <fields>
7349            <field>
7350              <name>CPU_INT_IDX</name>
7351              <description>CPU interrupt index (legal range [0, 7]). This field specifies to which CPU interrupt the system interrupt is mapped. E.g., if CPU_INT_IDX is '6', the system interrupt is mapped to CPU interrupt '6'.
7352
7353Note: it is possible to map multiple system interrupts to the same CPU interrupt. It is advised to assign different priorities to the CPU interrupts and to assign system interrupts to CPU interrupts accordingly.</description>
7354              <bitRange>[2:0]</bitRange>
7355              <access>read-write</access>
7356            </field>
7357            <field>
7358              <name>CPU_INT_VALID</name>
7359              <description>Interrupt enable:
7360'0': Disabled. The system interrupt will NOT be mapped to any CPU interrupt.
7361'1': Enabled. The system interrupt is mapped on CPU interrupt CPU_INT_IDX.
7362
7363Note: the CPUs have dedicated XXX_SYSTEM_INT_CTL registers. In other words, the CPUs can use different CPU interrupts for the same system interrupt. However, typically only one of the CPUs will have the ENABLED field of a specific system interrupt set to '1'.</description>
7364              <bitRange>[31:31]</bitRange>
7365              <access>read-write</access>
7366            </field>
7367          </fields>
7368        </register>
7369        <register>
7370          <dim>1023</dim>
7371          <dimIncrement>4</dimIncrement>
7372          <name>CM4_SYSTEM_INT_CTL[%s]</name>
7373          <description>CM4 system interrupt control</description>
7374          <addressOffset>0xA000</addressOffset>
7375          <size>32</size>
7376          <access>read-write</access>
7377          <resetValue>0x0</resetValue>
7378          <resetMask>0x80000000</resetMask>
7379          <fields>
7380            <field>
7381              <name>CPU_INT_IDX</name>
7382              <description>N/A</description>
7383              <bitRange>[2:0]</bitRange>
7384              <access>read-write</access>
7385            </field>
7386            <field>
7387              <name>CPU_INT_VALID</name>
7388              <description>N/A</description>
7389              <bitRange>[31:31]</bitRange>
7390              <access>read-write</access>
7391            </field>
7392          </fields>
7393        </register>
7394      </registers>
7395    </peripheral>
7396    <peripheral>
7397      <name>FAULT</name>
7398      <description>Fault structures</description>
7399      <baseAddress>0x40210000</baseAddress>
7400      <addressBlock>
7401        <offset>0</offset>
7402        <size>65536</size>
7403        <usage>registers</usage>
7404      </addressBlock>
7405      <registers>
7406        <cluster>
7407          <dim>2</dim>
7408          <dimIncrement>256</dimIncrement>
7409          <name>STRUCT[%s]</name>
7410          <description>Fault structure</description>
7411          <addressOffset>0x00000000</addressOffset>
7412          <register>
7413            <name>CTL</name>
7414            <description>Fault control</description>
7415            <addressOffset>0x0</addressOffset>
7416            <size>32</size>
7417            <access>read-write</access>
7418            <resetValue>0x0</resetValue>
7419            <resetMask>0x7</resetMask>
7420            <fields>
7421              <field>
7422                <name>TR_EN</name>
7423                <description>Trigger output enable:
7424'0': Disabled. The trigger output 'tr_fault' is '0'.
7425'1': Enabled. The trigger output 'tr_fault' reflects STATUS.VALID. The trigger can be used to initiate a Datawire transfer of the FAULT data (FAULT_DATA0 through FAULT_DATA3).</description>
7426                <bitRange>[0:0]</bitRange>
7427                <access>read-write</access>
7428              </field>
7429              <field>
7430                <name>OUT_EN</name>
7431                <description>IO output signal enable:
7432'0': Disabled. The IO output signal 'fault_out' is '0'. The IO output enable signal 'fault_out_en' is '0'.
7433'1': Enabled. The IO output signal 'fault_out' reflects STATUS.VALID. The IO output enable signal 'fault_out_en' is '1'.</description>
7434                <bitRange>[1:1]</bitRange>
7435                <access>read-write</access>
7436              </field>
7437              <field>
7438                <name>RESET_REQ_EN</name>
7439                <description>Reset request enable:
7440'0': Disabled.
7441'1': Enabled. The output reset request signal 'fault_reset_req' reflects STATUS.VALID. This reset causes a warm/soft/core reset. This warm/soft/core reset does not affect the fault logic STATUS, DATA0, ..., DATA3 registers (allowing for post soft reset failure analysis).
7442
7443The 'fault_reset_req' signals of the individual fault report structures are combined (logically OR'd) into a single SRSS 'fault_reset_req' signal.</description>
7444                <bitRange>[2:2]</bitRange>
7445                <access>read-write</access>
7446              </field>
7447            </fields>
7448          </register>
7449          <register>
7450            <name>STATUS</name>
7451            <description>Fault status</description>
7452            <addressOffset>0xC</addressOffset>
7453            <size>32</size>
7454            <access>read-write</access>
7455            <resetValue>0x0</resetValue>
7456            <resetMask>0x80000000</resetMask>
7457            <fields>
7458              <field>
7459                <name>IDX</name>
7460                <description>The fault source index for which fault information is captured in DATA0 through DATA3. The fault information is fault source specific and described below.
7461
7462Note: this register field (and associated fault source data in DATA0 through DATA3) should only be considered valid, when VALID is '1'.</description>
7463                <bitRange>[6:0]</bitRange>
7464                <access>read-write</access>
7465              </field>
7466              <field>
7467                <name>VALID</name>
7468                <description>Valid indication:
7469'0': Invalid.
7470'1': Valid. STATUS.IDX, DATA0, ..., DATA3 specify the fault.
7471
7472Note: Typically, HW sets this field to '1' (on an activated HW fault source that is 'enabled' by the MASK registers) and SW clears this field to '0' (typically by boot code SW (after a warm system reset, when the fault is handled). In this typical use case scenario, the HW source fault data is simultaneously captured into DATA0, ..., DATA3 when the VALID field is set to '1'.
7473
7474An exceptional SW use case scenario is identified as well. In this scenario, SW sets this field to '1' with a fault source index different to one of the defined HW fault sources. SW update is not restricted by the MASK registers). In both use case scenarios, the following holds:
7475- STATUS.IDX, DATA0, ..., DATA3 can only be written when STATUS.VALID is '0'; the fault structure is not in use yet. Writing STATUS.VALID to '1' effectively locks the fault structure (until SW clears STATUS.VALID to '0'). This restriction requires a SW update to sequentially update the DATA registers followed by an update of the STATUS register.
7476
7477Note: For the exceptional SW use case, sequential updates to the DATA and STATUS registers may be 'interrupted' by a HW fault capture. In this case, the SW DATA register updates are overwritten by the HW update (and the STATUS.IDX field will reflect the HW capture)</description>
7478                <bitRange>[31:31]</bitRange>
7479                <access>read-write</access>
7480              </field>
7481            </fields>
7482          </register>
7483          <register>
7484            <dim>4</dim>
7485            <dimIncrement>4</dimIncrement>
7486            <name>DATA[%s]</name>
7487            <description>Fault data</description>
7488            <addressOffset>0x10</addressOffset>
7489            <size>32</size>
7490            <access>read-write</access>
7491            <resetValue>0x0</resetValue>
7492            <resetMask>0x0</resetMask>
7493            <fields>
7494              <field>
7495                <name>DATA</name>
7496                <description>Captured fault source data.
7497
7498Note: the DATA registers can only be written when STATUS.VALID is '0'.
7499
7500Note: the fault source index STATUS.IDX specifies the format of the DATA registers.</description>
7501                <bitRange>[31:0]</bitRange>
7502                <access>read-write</access>
7503              </field>
7504            </fields>
7505          </register>
7506          <register>
7507            <name>PENDING0</name>
7508            <description>Fault pending 0</description>
7509            <addressOffset>0x40</addressOffset>
7510            <size>32</size>
7511            <access>read-only</access>
7512            <resetValue>0x0</resetValue>
7513            <resetMask>0x0</resetMask>
7514            <fields>
7515              <field>
7516                <name>SOURCE</name>
7517                <description>This field specifies the following sources:
7518Bit 0: CM0 MPU.
7519Bit 1: CRYPTO MPU.
7520Bit 2: DW 0 MPU.
7521Bit 3: DW 1 MPU.
7522Bit 4: DMA controller MPU.
7523...
7524Bit 15: DAP MPU.
7525Bit 16: CM4 system bus MPU.
7526Bit 17: CM4 code bus MPU (for non FLASH controller accesses).
7527Bit 18: CM4 code bus MPU (for FLASH controller accesses).</description>
7528                <bitRange>[31:0]</bitRange>
7529                <access>read-only</access>
7530              </field>
7531            </fields>
7532          </register>
7533          <register>
7534            <name>PENDING1</name>
7535            <description>Fault pending 1</description>
7536            <addressOffset>0x44</addressOffset>
7537            <size>32</size>
7538            <access>read-only</access>
7539            <resetValue>0x0</resetValue>
7540            <resetMask>0x0</resetMask>
7541            <fields>
7542              <field>
7543                <name>SOURCE</name>
7544                <description>This field specifies the following sources:
7545Bit 0: Peripheral group 0 PPU.
7546Bit 1: Peripheral group 1 PPU.
7547Bit 2: Peripheral group 2 PPU.
7548Bit 3: Peripheral group 3 PPU.
7549Bit 4: Peripheral group 4 PPU.
7550Bit 5: Peripheral group 5 PPU.
7551Bit 6: Peripheral group 6 PPU.
7552Bit 7: Peripheral group 7 PPU.
7553...
7554Bit 15: Peripheral group 15 PPU.
7555
7556Bit 16 - 31: See STATUS register.</description>
7557                <bitRange>[31:0]</bitRange>
7558                <access>read-only</access>
7559              </field>
7560            </fields>
7561          </register>
7562          <register>
7563            <name>PENDING2</name>
7564            <description>Fault pending 2</description>
7565            <addressOffset>0x48</addressOffset>
7566            <size>32</size>
7567            <access>read-only</access>
7568            <resetValue>0x0</resetValue>
7569            <resetMask>0x0</resetMask>
7570            <fields>
7571              <field>
7572                <name>SOURCE</name>
7573                <description>This field specifies the following sources:
7574Bit 0 - 31: See STATUS register.</description>
7575                <bitRange>[31:0]</bitRange>
7576                <access>read-only</access>
7577              </field>
7578            </fields>
7579          </register>
7580          <register>
7581            <name>MASK0</name>
7582            <description>Fault mask 0</description>
7583            <addressOffset>0x50</addressOffset>
7584            <size>32</size>
7585            <access>read-write</access>
7586            <resetValue>0x0</resetValue>
7587            <resetMask>0xFFFFFFFF</resetMask>
7588            <fields>
7589              <field>
7590                <name>SOURCE</name>
7591                <description>Fault source enables:
7592Bits 31-0: Fault sources 31 to 0.</description>
7593                <bitRange>[31:0]</bitRange>
7594                <access>read-write</access>
7595              </field>
7596            </fields>
7597          </register>
7598          <register>
7599            <name>MASK1</name>
7600            <description>Fault mask 1</description>
7601            <addressOffset>0x54</addressOffset>
7602            <size>32</size>
7603            <access>read-write</access>
7604            <resetValue>0x0</resetValue>
7605            <resetMask>0xFFFFFFFF</resetMask>
7606            <fields>
7607              <field>
7608                <name>SOURCE</name>
7609                <description>Fault source enables:
7610Bits 31-0: Fault sources 63 to 32.</description>
7611                <bitRange>[31:0]</bitRange>
7612                <access>read-write</access>
7613              </field>
7614            </fields>
7615          </register>
7616          <register>
7617            <name>MASK2</name>
7618            <description>Fault mask 2</description>
7619            <addressOffset>0x58</addressOffset>
7620            <size>32</size>
7621            <access>read-write</access>
7622            <resetValue>0x0</resetValue>
7623            <resetMask>0xFFFFFFFF</resetMask>
7624            <fields>
7625              <field>
7626                <name>SOURCE</name>
7627                <description>Fault source enables:
7628Bits 31-0: Fault sources 95 to 64.</description>
7629                <bitRange>[31:0]</bitRange>
7630                <access>read-write</access>
7631              </field>
7632            </fields>
7633          </register>
7634          <register>
7635            <name>INTR</name>
7636            <description>Interrupt</description>
7637            <addressOffset>0xC0</addressOffset>
7638            <size>32</size>
7639            <access>read-write</access>
7640            <resetValue>0x0</resetValue>
7641            <resetMask>0x1</resetMask>
7642            <fields>
7643              <field>
7644                <name>FAULT</name>
7645                <description>This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0/MASK1/MASK2) pending fault source is captured:
7646- STATUS.VALID is set to '1'.
7647- STATUS.IDX specifies the fault source index.
7648- DATA0 through DATA3 captures the fault source data.
7649
7650SW writes a '1' to this field to clear the interrupt cause to '0'. SW clear STATUS.VALID to '0' to enable capture of the next fault. Note that when there is an enabled pending fault source, the pending fault source is captured immediately and INTR.FAULT is immediately activated (set to '1').</description>
7651                <bitRange>[0:0]</bitRange>
7652                <access>read-write</access>
7653              </field>
7654            </fields>
7655          </register>
7656          <register>
7657            <name>INTR_SET</name>
7658            <description>Interrupt set</description>
7659            <addressOffset>0xC4</addressOffset>
7660            <size>32</size>
7661            <access>read-write</access>
7662            <resetValue>0x0</resetValue>
7663            <resetMask>0x1</resetMask>
7664            <fields>
7665              <field>
7666                <name>FAULT</name>
7667                <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
7668                <bitRange>[0:0]</bitRange>
7669                <access>read-write</access>
7670              </field>
7671            </fields>
7672          </register>
7673          <register>
7674            <name>INTR_MASK</name>
7675            <description>Interrupt mask</description>
7676            <addressOffset>0xC8</addressOffset>
7677            <size>32</size>
7678            <access>read-write</access>
7679            <resetValue>0x0</resetValue>
7680            <resetMask>0x1</resetMask>
7681            <fields>
7682              <field>
7683                <name>FAULT</name>
7684                <description>Mask bit for corresponding field in the INTR register.</description>
7685                <bitRange>[0:0]</bitRange>
7686                <access>read-write</access>
7687              </field>
7688            </fields>
7689          </register>
7690          <register>
7691            <name>INTR_MASKED</name>
7692            <description>Interrupt masked</description>
7693            <addressOffset>0xCC</addressOffset>
7694            <size>32</size>
7695            <access>read-only</access>
7696            <resetValue>0x0</resetValue>
7697            <resetMask>0x1</resetMask>
7698            <fields>
7699              <field>
7700                <name>FAULT</name>
7701                <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
7702                <bitRange>[0:0]</bitRange>
7703                <access>read-only</access>
7704              </field>
7705            </fields>
7706          </register>
7707        </cluster>
7708      </registers>
7709    </peripheral>
7710    <peripheral>
7711      <name>IPC</name>
7712      <description>IPC</description>
7713      <baseAddress>0x40220000</baseAddress>
7714      <addressBlock>
7715        <offset>0</offset>
7716        <size>65536</size>
7717        <usage>registers</usage>
7718      </addressBlock>
7719      <registers>
7720        <cluster>
7721          <dim>16</dim>
7722          <dimIncrement>32</dimIncrement>
7723          <name>STRUCT[%s]</name>
7724          <description>IPC structure</description>
7725          <addressOffset>0x00000000</addressOffset>
7726          <register>
7727            <name>ACQUIRE</name>
7728            <description>IPC acquire</description>
7729            <addressOffset>0x0</addressOffset>
7730            <size>32</size>
7731            <access>read-only</access>
7732            <resetValue>0x0</resetValue>
7733            <resetMask>0x80000000</resetMask>
7734            <fields>
7735              <field>
7736                <name>P</name>
7737                <description>User/privileged access control:
7738'0': user mode.
7739'1': privileged mode.
7740
7741This field is set with the user/privileged access control of the access that successfully acquired the lock.</description>
7742                <bitRange>[0:0]</bitRange>
7743                <access>read-only</access>
7744              </field>
7745              <field>
7746                <name>NS</name>
7747                <description>Secure/non-secure access control:
7748'0': secure.
7749'1': non-secure.
7750
7751This field is set with the secure/non-secure access control of the access that successfully acquired the lock.</description>
7752                <bitRange>[1:1]</bitRange>
7753                <access>read-only</access>
7754              </field>
7755              <field>
7756                <name>PC</name>
7757                <description>This field specifies the protection context that successfully acquired the lock.</description>
7758                <bitRange>[7:4]</bitRange>
7759                <access>read-only</access>
7760              </field>
7761              <field>
7762                <name>MS</name>
7763                <description>This field specifies the bus master identifier that successfully acquired the lock.</description>
7764                <bitRange>[11:8]</bitRange>
7765                <access>read-only</access>
7766              </field>
7767              <field>
7768                <name>SUCCESS</name>
7769                <description>Specifies if the lock is successfully acquired or not (reading the ACQUIRE register can have affect on SUCCESS and LOCK_STATUS.ACQUIRED):
7770'0': Not successfully acquired; i.e. the lock was already acquired by another read transaction and not released. The P, NS, PC and MS fields reflect the access attributes of the transaction that previously successfully acuired the lock; the fields are NOT affected by the current access.
7771'1': Successfully acquired. The P, NS, PC and MS fields reflect the access attributes of the current access.
7772
7773Note that this field is NOT SW writable. A lock is released by writing to the associated RELEASE register (irrespective of the write value).</description>
7774                <bitRange>[31:31]</bitRange>
7775                <access>read-only</access>
7776              </field>
7777            </fields>
7778          </register>
7779          <register>
7780            <name>RELEASE</name>
7781            <description>IPC release</description>
7782            <addressOffset>0x4</addressOffset>
7783            <size>32</size>
7784            <access>write-only</access>
7785            <resetValue>0x0</resetValue>
7786            <resetMask>0xFFFF</resetMask>
7787            <fields>
7788              <field>
7789                <name>INTR_RELEASE</name>
7790                <description>Writing this field releases a lock and allows for the generation of release events to the IPC interrupt structures, but only when the lock is acquired (LOCK_STATUS.ACQUIRED is '1'). The IPC release cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_RELEASE[] is set to '1'.
7791
7792SW writes a '1' to the bit fields to generate a release event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
7793                <bitRange>[15:0]</bitRange>
7794                <access>write-only</access>
7795              </field>
7796            </fields>
7797          </register>
7798          <register>
7799            <name>NOTIFY</name>
7800            <description>IPC notification</description>
7801            <addressOffset>0x8</addressOffset>
7802            <size>32</size>
7803            <access>write-only</access>
7804            <resetValue>0x0</resetValue>
7805            <resetMask>0xFFFF</resetMask>
7806            <fields>
7807              <field>
7808                <name>INTR_NOTIFY</name>
7809                <description>This field allows for the generation of notification events to the IPC interrupt structures. The IPC notification cause fields associated with this IPC structure are set to '1', but only for those IPC interrupt structures for which the corresponding bit field in INTR_NOTIFY[] is set to '1'.
7810
7811SW writes a '1' to the bit fields to generate a notify event. Due to the transient nature of this event, SW always reads a '0' from this field.</description>
7812                <bitRange>[15:0]</bitRange>
7813                <access>write-only</access>
7814              </field>
7815            </fields>
7816          </register>
7817          <register>
7818            <name>DATA0</name>
7819            <description>IPC data 0</description>
7820            <addressOffset>0xC</addressOffset>
7821            <size>32</size>
7822            <access>read-write</access>
7823            <resetValue>0x0</resetValue>
7824            <resetMask>0x0</resetMask>
7825            <fields>
7826              <field>
7827                <name>DATA</name>
7828                <description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
7829                <bitRange>[31:0]</bitRange>
7830                <access>read-write</access>
7831              </field>
7832            </fields>
7833          </register>
7834          <register>
7835            <name>DATA1</name>
7836            <description>IPC data 1</description>
7837            <addressOffset>0x10</addressOffset>
7838            <size>32</size>
7839            <access>read-write</access>
7840            <resetValue>0x0</resetValue>
7841            <resetMask>0x0</resetMask>
7842            <fields>
7843              <field>
7844                <name>DATA</name>
7845                <description>This field holds a 32-bit data element that is associated with the IPC structure.</description>
7846                <bitRange>[31:0]</bitRange>
7847                <access>read-write</access>
7848              </field>
7849            </fields>
7850          </register>
7851          <register>
7852            <name>LOCK_STATUS</name>
7853            <description>IPC lock status</description>
7854            <addressOffset>0x1C</addressOffset>
7855            <size>32</size>
7856            <access>read-only</access>
7857            <resetValue>0x0</resetValue>
7858            <resetMask>0x80000000</resetMask>
7859            <fields>
7860              <field>
7861                <name>P</name>
7862                <description>This field specifies the user/privileged access control:
7863'0': user mode.
7864'1': privileged mode.</description>
7865                <bitRange>[0:0]</bitRange>
7866                <access>read-only</access>
7867              </field>
7868              <field>
7869                <name>NS</name>
7870                <description>This field specifies the secure/non-secure access control:
7871'0': secure.
7872'1': non-secure.</description>
7873                <bitRange>[1:1]</bitRange>
7874                <access>read-only</access>
7875              </field>
7876              <field>
7877                <name>PC</name>
7878                <description>This field specifies the protection context that successfully acquired the lock.</description>
7879                <bitRange>[7:4]</bitRange>
7880                <access>read-only</access>
7881              </field>
7882              <field>
7883                <name>MS</name>
7884                <description>This field specifies the bus master identifier that successfully acquired the lock.</description>
7885                <bitRange>[11:8]</bitRange>
7886                <access>read-only</access>
7887              </field>
7888              <field>
7889                <name>ACQUIRED</name>
7890                <description>Specifies if the lock is acquired. This field is set to '1', if a ACQUIRE read transfer successfully acquires the lock (the ACQUIRE read transfer returns ACQUIRE.SUCCESS as '1'). If zero, P, NS, PC, and MS are not valid.</description>
7891                <bitRange>[31:31]</bitRange>
7892                <access>read-only</access>
7893              </field>
7894            </fields>
7895          </register>
7896        </cluster>
7897        <cluster>
7898          <dim>16</dim>
7899          <dimIncrement>32</dimIncrement>
7900          <name>INTR_STRUCT[%s]</name>
7901          <description>IPC interrupt structure</description>
7902          <addressOffset>0x00001000</addressOffset>
7903          <register>
7904            <name>INTR</name>
7905            <description>Interrupt</description>
7906            <addressOffset>0x0</addressOffset>
7907            <size>32</size>
7908            <access>read-write</access>
7909            <resetValue>0x0</resetValue>
7910            <resetMask>0xFFFFFFFF</resetMask>
7911            <fields>
7912              <field>
7913                <name>RELEASE</name>
7914                <description>These interrupt cause fields are activated (HW sets the field to '1') when a IPC release event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.</description>
7915                <bitRange>[15:0]</bitRange>
7916                <access>read-write</access>
7917              </field>
7918              <field>
7919                <name>NOTIFY</name>
7920                <description>These interrupt cause fields are activated (HW sets the field to '1') when a IPC notification event is detected. One bit field for each master. SW writes a '1' to these field to clear the interrupt cause.</description>
7921                <bitRange>[31:16]</bitRange>
7922                <access>read-write</access>
7923              </field>
7924            </fields>
7925          </register>
7926          <register>
7927            <name>INTR_SET</name>
7928            <description>Interrupt set</description>
7929            <addressOffset>0x4</addressOffset>
7930            <size>32</size>
7931            <access>read-write</access>
7932            <resetValue>0x0</resetValue>
7933            <resetMask>0xFFFFFFFF</resetMask>
7934            <fields>
7935              <field>
7936                <name>RELEASE</name>
7937                <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
7938                <bitRange>[15:0]</bitRange>
7939                <access>read-write</access>
7940              </field>
7941              <field>
7942                <name>NOTIFY</name>
7943                <description>SW writes a '1' to this field to set the corresponding field in the INTR register.</description>
7944                <bitRange>[31:16]</bitRange>
7945                <access>read-write</access>
7946              </field>
7947            </fields>
7948          </register>
7949          <register>
7950            <name>INTR_MASK</name>
7951            <description>Interrupt mask</description>
7952            <addressOffset>0x8</addressOffset>
7953            <size>32</size>
7954            <access>read-write</access>
7955            <resetValue>0x0</resetValue>
7956            <resetMask>0xFFFFFFFF</resetMask>
7957            <fields>
7958              <field>
7959                <name>RELEASE</name>
7960                <description>Mask bit for corresponding field in the INTR register.</description>
7961                <bitRange>[15:0]</bitRange>
7962                <access>read-write</access>
7963              </field>
7964              <field>
7965                <name>NOTIFY</name>
7966                <description>Mask bit for corresponding field in the INTR register.</description>
7967                <bitRange>[31:16]</bitRange>
7968                <access>read-write</access>
7969              </field>
7970            </fields>
7971          </register>
7972          <register>
7973            <name>INTR_MASKED</name>
7974            <description>Interrupt masked</description>
7975            <addressOffset>0xC</addressOffset>
7976            <size>32</size>
7977            <access>read-only</access>
7978            <resetValue>0x0</resetValue>
7979            <resetMask>0xFFFFFFFF</resetMask>
7980            <fields>
7981              <field>
7982                <name>RELEASE</name>
7983                <description>Logical and of corresponding request and mask bits.</description>
7984                <bitRange>[15:0]</bitRange>
7985                <access>read-only</access>
7986              </field>
7987              <field>
7988                <name>NOTIFY</name>
7989                <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
7990                <bitRange>[31:16]</bitRange>
7991                <access>read-only</access>
7992              </field>
7993            </fields>
7994          </register>
7995        </cluster>
7996      </registers>
7997    </peripheral>
7998    <peripheral>
7999      <name>PROT</name>
8000      <description>Protection</description>
8001      <baseAddress>0x40230000</baseAddress>
8002      <addressBlock>
8003        <offset>0</offset>
8004        <size>65536</size>
8005        <usage>registers</usage>
8006      </addressBlock>
8007      <registers>
8008        <cluster>
8009          <name>SMPU</name>
8010          <description>SMPU</description>
8011          <addressOffset>0x00000000</addressOffset>
8012          <register>
8013            <name>MS0_CTL</name>
8014            <description>Master 0 protection context control</description>
8015            <addressOffset>0x0</addressOffset>
8016            <size>32</size>
8017            <access>read-write</access>
8018            <resetValue>0x303</resetValue>
8019            <resetMask>0xFFFF0303</resetMask>
8020            <fields>
8021              <field>
8022                <name>P</name>
8023                <description>Privileged setting ('0': user mode; '1': privileged mode).
8024
8025Notes:
8026This field is ONLY used for masters that do NOT provide their own user/privileged access control attribute.
8027The default/reset field value provides privileged mode access capabilities.</description>
8028                <bitRange>[0:0]</bitRange>
8029                <access>read-write</access>
8030              </field>
8031              <field>
8032                <name>NS</name>
8033                <description>Security setting ('0': secure mode; '1': non-secure mode).
8034
8035Notes:
8036This field is ONLY used for masters that do NOT provide their own secure/non-secure access control attribute.
8037Note that the default/reset field value provides non-secure mode access capabilities to all masters.</description>
8038                <bitRange>[1:1]</bitRange>
8039                <access>read-write</access>
8040              </field>
8041              <field>
8042                <name>PRIO</name>
8043                <description>Device wide bus arbitration priority setting ('0': highest priority, '3': lowest priority).
8044
8045Notes:
8046The AHB-Lite interconnect performs arbitration on the individual  beats/transfers of a burst (this optimizes latency over locality/bandwidth).
8047The AXI-Lite interconnects performs a single arbitration for the complete burst (this optimizes locality/bandwidth over latency).
8048Masters with the same priority setting form a 'priority group'. Within a 'priority group', round robin arbitration is performed.</description>
8049                <bitRange>[9:8]</bitRange>
8050                <access>read-write</access>
8051              </field>
8052              <field>
8053                <name>PC_MASK_0</name>
8054                <description>Protection context mask for protection context '0'. This field is a constant '0':
8055- PC_MASK_0 is '0': MPU MS_CTL.PC[3:0] can NOT be set to '0' and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed.</description>
8056                <bitRange>[16:16]</bitRange>
8057                <access>read-only</access>
8058              </field>
8059              <field>
8060                <name>PC_MASK_15_TO_1</name>
8061                <description>Protection context mask for protection contexts '15' down to '1'. Bit PC_MASK_15_TO_1[i] indicates if the MPU MS_CTL.PC[3:0] protection context field can be set to the value 'i+1':
8062- PC_MASK_15_TO_1[i] is '0': MPU MS_CTL.PC[3:0] can NOT be set to 'i+1'; and PC[3:0] is not changed. If the protection context of the write transfer is '0', protection is not applied and PC[3:0] can be changed.
8063- PC_MASK_15_TO_1[i] is '1': MPU MS_CTL.PC[3:0] can be set to 'i+1'.
8064
8065Note: When CPUSS_CM0_PC_CTL.VALID[i] is '1' (the associated protection context handler is valid), write transfers to PC_MASK_15_TO_1[i-1] always write '0', regardless of data written. This ensures that when valid protection context handlers are used to enter protection contexts 1, 2 or 3 through (HW modifies MPU MS_CTL.PC[3:0] on entry of the handler), it is NOT possible for SW to enter those protection contexts (SW modifies MPU MS_CTL.PC[3:0]).</description>
8066                <bitRange>[31:17]</bitRange>
8067                <access>read-write</access>
8068              </field>
8069            </fields>
8070          </register>
8071          <register>
8072            <name>MS1_CTL</name>
8073            <description>Master 1 protection context control</description>
8074            <addressOffset>0x4</addressOffset>
8075            <size>32</size>
8076            <access>read-write</access>
8077            <resetValue>0x303</resetValue>
8078            <resetMask>0xFFFF0303</resetMask>
8079            <fields>
8080              <field>
8081                <name>P</name>
8082                <description>See MS0_CTL.P.</description>
8083                <bitRange>[0:0]</bitRange>
8084                <access>read-write</access>
8085              </field>
8086              <field>
8087                <name>NS</name>
8088                <description>See MS0_CTL.NS.</description>
8089                <bitRange>[1:1]</bitRange>
8090                <access>read-write</access>
8091              </field>
8092              <field>
8093                <name>PRIO</name>
8094                <description>See MS0_CTL.PRIO</description>
8095                <bitRange>[9:8]</bitRange>
8096                <access>read-write</access>
8097              </field>
8098              <field>
8099                <name>PC_MASK_0</name>
8100                <description>See MS0_CTL.PC_MASK_0.</description>
8101                <bitRange>[16:16]</bitRange>
8102                <access>read-only</access>
8103              </field>
8104              <field>
8105                <name>PC_MASK_15_TO_1</name>
8106                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
8107                <bitRange>[31:17]</bitRange>
8108                <access>read-write</access>
8109              </field>
8110            </fields>
8111          </register>
8112          <register>
8113            <name>MS2_CTL</name>
8114            <description>Master 2 protection context control</description>
8115            <addressOffset>0x8</addressOffset>
8116            <size>32</size>
8117            <access>read-write</access>
8118            <resetValue>0x303</resetValue>
8119            <resetMask>0xFFFF0303</resetMask>
8120            <fields>
8121              <field>
8122                <name>P</name>
8123                <description>See MS0_CTL.P.</description>
8124                <bitRange>[0:0]</bitRange>
8125                <access>read-write</access>
8126              </field>
8127              <field>
8128                <name>NS</name>
8129                <description>See MS0_CTL.NS.</description>
8130                <bitRange>[1:1]</bitRange>
8131                <access>read-write</access>
8132              </field>
8133              <field>
8134                <name>PRIO</name>
8135                <description>See MS0_CTL.PRIO</description>
8136                <bitRange>[9:8]</bitRange>
8137                <access>read-write</access>
8138              </field>
8139              <field>
8140                <name>PC_MASK_0</name>
8141                <description>See MS0_CTL.PC_MASK_0.</description>
8142                <bitRange>[16:16]</bitRange>
8143                <access>read-only</access>
8144              </field>
8145              <field>
8146                <name>PC_MASK_15_TO_1</name>
8147                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
8148                <bitRange>[31:17]</bitRange>
8149                <access>read-write</access>
8150              </field>
8151            </fields>
8152          </register>
8153          <register>
8154            <name>MS3_CTL</name>
8155            <description>Master 3 protection context control</description>
8156            <addressOffset>0xC</addressOffset>
8157            <size>32</size>
8158            <access>read-write</access>
8159            <resetValue>0x303</resetValue>
8160            <resetMask>0xFFFF0303</resetMask>
8161            <fields>
8162              <field>
8163                <name>P</name>
8164                <description>See MS0_CTL.P.</description>
8165                <bitRange>[0:0]</bitRange>
8166                <access>read-write</access>
8167              </field>
8168              <field>
8169                <name>NS</name>
8170                <description>See MS0_CTL.NS.</description>
8171                <bitRange>[1:1]</bitRange>
8172                <access>read-write</access>
8173              </field>
8174              <field>
8175                <name>PRIO</name>
8176                <description>See MS0_CTL.PRIO</description>
8177                <bitRange>[9:8]</bitRange>
8178                <access>read-write</access>
8179              </field>
8180              <field>
8181                <name>PC_MASK_0</name>
8182                <description>See MS0_CTL.PC_MASK_0.</description>
8183                <bitRange>[16:16]</bitRange>
8184                <access>read-only</access>
8185              </field>
8186              <field>
8187                <name>PC_MASK_15_TO_1</name>
8188                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
8189                <bitRange>[31:17]</bitRange>
8190                <access>read-write</access>
8191              </field>
8192            </fields>
8193          </register>
8194          <register>
8195            <name>MS4_CTL</name>
8196            <description>Master 4 protection context control</description>
8197            <addressOffset>0x10</addressOffset>
8198            <size>32</size>
8199            <access>read-write</access>
8200            <resetValue>0x303</resetValue>
8201            <resetMask>0xFFFF0303</resetMask>
8202            <fields>
8203              <field>
8204                <name>P</name>
8205                <description>See MS0_CTL.P.</description>
8206                <bitRange>[0:0]</bitRange>
8207                <access>read-write</access>
8208              </field>
8209              <field>
8210                <name>NS</name>
8211                <description>See MS0_CTL.NS.</description>
8212                <bitRange>[1:1]</bitRange>
8213                <access>read-write</access>
8214              </field>
8215              <field>
8216                <name>PRIO</name>
8217                <description>See MS0_CTL.PRIO</description>
8218                <bitRange>[9:8]</bitRange>
8219                <access>read-write</access>
8220              </field>
8221              <field>
8222                <name>PC_MASK_0</name>
8223                <description>See MS0_CTL.PC_MASK_0.</description>
8224                <bitRange>[16:16]</bitRange>
8225                <access>read-only</access>
8226              </field>
8227              <field>
8228                <name>PC_MASK_15_TO_1</name>
8229                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
8230                <bitRange>[31:17]</bitRange>
8231                <access>read-write</access>
8232              </field>
8233            </fields>
8234          </register>
8235          <register>
8236            <name>MS5_CTL</name>
8237            <description>Master 5 protection context control</description>
8238            <addressOffset>0x14</addressOffset>
8239            <size>32</size>
8240            <access>read-write</access>
8241            <resetValue>0x303</resetValue>
8242            <resetMask>0xFFFF0303</resetMask>
8243            <fields>
8244              <field>
8245                <name>P</name>
8246                <description>See MS0_CTL.P.</description>
8247                <bitRange>[0:0]</bitRange>
8248                <access>read-write</access>
8249              </field>
8250              <field>
8251                <name>NS</name>
8252                <description>See MS0_CTL.NS.</description>
8253                <bitRange>[1:1]</bitRange>
8254                <access>read-write</access>
8255              </field>
8256              <field>
8257                <name>PRIO</name>
8258                <description>See MS0_CTL.PRIO</description>
8259                <bitRange>[9:8]</bitRange>
8260                <access>read-write</access>
8261              </field>
8262              <field>
8263                <name>PC_MASK_0</name>
8264                <description>See MS0_CTL.PC_MASK_0.</description>
8265                <bitRange>[16:16]</bitRange>
8266                <access>read-only</access>
8267              </field>
8268              <field>
8269                <name>PC_MASK_15_TO_1</name>
8270                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
8271                <bitRange>[31:17]</bitRange>
8272                <access>read-write</access>
8273              </field>
8274            </fields>
8275          </register>
8276          <register>
8277            <name>MS6_CTL</name>
8278            <description>Master 6 protection context control</description>
8279            <addressOffset>0x18</addressOffset>
8280            <size>32</size>
8281            <access>read-write</access>
8282            <resetValue>0x303</resetValue>
8283            <resetMask>0xFFFF0303</resetMask>
8284            <fields>
8285              <field>
8286                <name>P</name>
8287                <description>See MS0_CTL.P.</description>
8288                <bitRange>[0:0]</bitRange>
8289                <access>read-write</access>
8290              </field>
8291              <field>
8292                <name>NS</name>
8293                <description>See MS0_CTL.NS.</description>
8294                <bitRange>[1:1]</bitRange>
8295                <access>read-write</access>
8296              </field>
8297              <field>
8298                <name>PRIO</name>
8299                <description>See MS0_CTL.PRIO</description>
8300                <bitRange>[9:8]</bitRange>
8301                <access>read-write</access>
8302              </field>
8303              <field>
8304                <name>PC_MASK_0</name>
8305                <description>See MS0_CTL.PC_MASK_0.</description>
8306                <bitRange>[16:16]</bitRange>
8307                <access>read-only</access>
8308              </field>
8309              <field>
8310                <name>PC_MASK_15_TO_1</name>
8311                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
8312                <bitRange>[31:17]</bitRange>
8313                <access>read-write</access>
8314              </field>
8315            </fields>
8316          </register>
8317          <register>
8318            <name>MS7_CTL</name>
8319            <description>Master 7 protection context control</description>
8320            <addressOffset>0x1C</addressOffset>
8321            <size>32</size>
8322            <access>read-write</access>
8323            <resetValue>0x303</resetValue>
8324            <resetMask>0xFFFF0303</resetMask>
8325            <fields>
8326              <field>
8327                <name>P</name>
8328                <description>See MS0_CTL.P.</description>
8329                <bitRange>[0:0]</bitRange>
8330                <access>read-write</access>
8331              </field>
8332              <field>
8333                <name>NS</name>
8334                <description>See MS0_CTL.NS.</description>
8335                <bitRange>[1:1]</bitRange>
8336                <access>read-write</access>
8337              </field>
8338              <field>
8339                <name>PRIO</name>
8340                <description>See MS0_CTL.PRIO</description>
8341                <bitRange>[9:8]</bitRange>
8342                <access>read-write</access>
8343              </field>
8344              <field>
8345                <name>PC_MASK_0</name>
8346                <description>See MS0_CTL.PC_MASK_0.</description>
8347                <bitRange>[16:16]</bitRange>
8348                <access>read-only</access>
8349              </field>
8350              <field>
8351                <name>PC_MASK_15_TO_1</name>
8352                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
8353                <bitRange>[31:17]</bitRange>
8354                <access>read-write</access>
8355              </field>
8356            </fields>
8357          </register>
8358          <register>
8359            <name>MS8_CTL</name>
8360            <description>Master 8 protection context control</description>
8361            <addressOffset>0x20</addressOffset>
8362            <size>32</size>
8363            <access>read-write</access>
8364            <resetValue>0x303</resetValue>
8365            <resetMask>0xFFFF0303</resetMask>
8366            <fields>
8367              <field>
8368                <name>P</name>
8369                <description>See MS0_CTL.P.</description>
8370                <bitRange>[0:0]</bitRange>
8371                <access>read-write</access>
8372              </field>
8373              <field>
8374                <name>NS</name>
8375                <description>See MS0_CTL.NS.</description>
8376                <bitRange>[1:1]</bitRange>
8377                <access>read-write</access>
8378              </field>
8379              <field>
8380                <name>PRIO</name>
8381                <description>See MS0_CTL.PRIO</description>
8382                <bitRange>[9:8]</bitRange>
8383                <access>read-write</access>
8384              </field>
8385              <field>
8386                <name>PC_MASK_0</name>
8387                <description>See MS0_CTL.PC_MASK_0.</description>
8388                <bitRange>[16:16]</bitRange>
8389                <access>read-only</access>
8390              </field>
8391              <field>
8392                <name>PC_MASK_15_TO_1</name>
8393                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
8394                <bitRange>[31:17]</bitRange>
8395                <access>read-write</access>
8396              </field>
8397            </fields>
8398          </register>
8399          <register>
8400            <name>MS9_CTL</name>
8401            <description>Master 9 protection context control</description>
8402            <addressOffset>0x24</addressOffset>
8403            <size>32</size>
8404            <access>read-write</access>
8405            <resetValue>0x303</resetValue>
8406            <resetMask>0xFFFF0303</resetMask>
8407            <fields>
8408              <field>
8409                <name>P</name>
8410                <description>See MS0_CTL.P.</description>
8411                <bitRange>[0:0]</bitRange>
8412                <access>read-write</access>
8413              </field>
8414              <field>
8415                <name>NS</name>
8416                <description>See MS0_CTL.NS.</description>
8417                <bitRange>[1:1]</bitRange>
8418                <access>read-write</access>
8419              </field>
8420              <field>
8421                <name>PRIO</name>
8422                <description>See MS0_CTL.PRIO</description>
8423                <bitRange>[9:8]</bitRange>
8424                <access>read-write</access>
8425              </field>
8426              <field>
8427                <name>PC_MASK_0</name>
8428                <description>See MS0_CTL.PC_MASK_0.</description>
8429                <bitRange>[16:16]</bitRange>
8430                <access>read-only</access>
8431              </field>
8432              <field>
8433                <name>PC_MASK_15_TO_1</name>
8434                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
8435                <bitRange>[31:17]</bitRange>
8436                <access>read-write</access>
8437              </field>
8438            </fields>
8439          </register>
8440          <register>
8441            <name>MS10_CTL</name>
8442            <description>Master 10 protection context control</description>
8443            <addressOffset>0x28</addressOffset>
8444            <size>32</size>
8445            <access>read-write</access>
8446            <resetValue>0x303</resetValue>
8447            <resetMask>0xFFFF0303</resetMask>
8448            <fields>
8449              <field>
8450                <name>P</name>
8451                <description>See MS0_CTL.P.</description>
8452                <bitRange>[0:0]</bitRange>
8453                <access>read-write</access>
8454              </field>
8455              <field>
8456                <name>NS</name>
8457                <description>See MS0_CTL.NS.</description>
8458                <bitRange>[1:1]</bitRange>
8459                <access>read-write</access>
8460              </field>
8461              <field>
8462                <name>PRIO</name>
8463                <description>See MS0_CTL.PRIO</description>
8464                <bitRange>[9:8]</bitRange>
8465                <access>read-write</access>
8466              </field>
8467              <field>
8468                <name>PC_MASK_0</name>
8469                <description>See MS0_CTL.PC_MASK_0.</description>
8470                <bitRange>[16:16]</bitRange>
8471                <access>read-only</access>
8472              </field>
8473              <field>
8474                <name>PC_MASK_15_TO_1</name>
8475                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
8476                <bitRange>[31:17]</bitRange>
8477                <access>read-write</access>
8478              </field>
8479            </fields>
8480          </register>
8481          <register>
8482            <name>MS11_CTL</name>
8483            <description>Master 11 protection context control</description>
8484            <addressOffset>0x2C</addressOffset>
8485            <size>32</size>
8486            <access>read-write</access>
8487            <resetValue>0x303</resetValue>
8488            <resetMask>0xFFFF0303</resetMask>
8489            <fields>
8490              <field>
8491                <name>P</name>
8492                <description>See MS0_CTL.P.</description>
8493                <bitRange>[0:0]</bitRange>
8494                <access>read-write</access>
8495              </field>
8496              <field>
8497                <name>NS</name>
8498                <description>See MS0_CTL.NS.</description>
8499                <bitRange>[1:1]</bitRange>
8500                <access>read-write</access>
8501              </field>
8502              <field>
8503                <name>PRIO</name>
8504                <description>See MS0_CTL.PRIO</description>
8505                <bitRange>[9:8]</bitRange>
8506                <access>read-write</access>
8507              </field>
8508              <field>
8509                <name>PC_MASK_0</name>
8510                <description>See MS0_CTL.PC_MASK_0.</description>
8511                <bitRange>[16:16]</bitRange>
8512                <access>read-only</access>
8513              </field>
8514              <field>
8515                <name>PC_MASK_15_TO_1</name>
8516                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
8517                <bitRange>[31:17]</bitRange>
8518                <access>read-write</access>
8519              </field>
8520            </fields>
8521          </register>
8522          <register>
8523            <name>MS12_CTL</name>
8524            <description>Master 12 protection context control</description>
8525            <addressOffset>0x30</addressOffset>
8526            <size>32</size>
8527            <access>read-write</access>
8528            <resetValue>0x303</resetValue>
8529            <resetMask>0xFFFF0303</resetMask>
8530            <fields>
8531              <field>
8532                <name>P</name>
8533                <description>See MS0_CTL.P.</description>
8534                <bitRange>[0:0]</bitRange>
8535                <access>read-write</access>
8536              </field>
8537              <field>
8538                <name>NS</name>
8539                <description>See MS0_CTL.NS.</description>
8540                <bitRange>[1:1]</bitRange>
8541                <access>read-write</access>
8542              </field>
8543              <field>
8544                <name>PRIO</name>
8545                <description>See MS0_CTL.PRIO</description>
8546                <bitRange>[9:8]</bitRange>
8547                <access>read-write</access>
8548              </field>
8549              <field>
8550                <name>PC_MASK_0</name>
8551                <description>See MS0_CTL.PC_MASK_0.</description>
8552                <bitRange>[16:16]</bitRange>
8553                <access>read-only</access>
8554              </field>
8555              <field>
8556                <name>PC_MASK_15_TO_1</name>
8557                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
8558                <bitRange>[31:17]</bitRange>
8559                <access>read-write</access>
8560              </field>
8561            </fields>
8562          </register>
8563          <register>
8564            <name>MS13_CTL</name>
8565            <description>Master 13 protection context control</description>
8566            <addressOffset>0x34</addressOffset>
8567            <size>32</size>
8568            <access>read-write</access>
8569            <resetValue>0x303</resetValue>
8570            <resetMask>0xFFFF0303</resetMask>
8571            <fields>
8572              <field>
8573                <name>P</name>
8574                <description>See MS0_CTL.P.</description>
8575                <bitRange>[0:0]</bitRange>
8576                <access>read-write</access>
8577              </field>
8578              <field>
8579                <name>NS</name>
8580                <description>See MS0_CTL.NS.</description>
8581                <bitRange>[1:1]</bitRange>
8582                <access>read-write</access>
8583              </field>
8584              <field>
8585                <name>PRIO</name>
8586                <description>See MS0_CTL.PRIO</description>
8587                <bitRange>[9:8]</bitRange>
8588                <access>read-write</access>
8589              </field>
8590              <field>
8591                <name>PC_MASK_0</name>
8592                <description>See MS0_CTL.PC_MASK_0.</description>
8593                <bitRange>[16:16]</bitRange>
8594                <access>read-only</access>
8595              </field>
8596              <field>
8597                <name>PC_MASK_15_TO_1</name>
8598                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
8599                <bitRange>[31:17]</bitRange>
8600                <access>read-write</access>
8601              </field>
8602            </fields>
8603          </register>
8604          <register>
8605            <name>MS14_CTL</name>
8606            <description>Master 14 protection context control</description>
8607            <addressOffset>0x38</addressOffset>
8608            <size>32</size>
8609            <access>read-write</access>
8610            <resetValue>0x303</resetValue>
8611            <resetMask>0xFFFF0303</resetMask>
8612            <fields>
8613              <field>
8614                <name>P</name>
8615                <description>See MS0_CTL.P.</description>
8616                <bitRange>[0:0]</bitRange>
8617                <access>read-write</access>
8618              </field>
8619              <field>
8620                <name>NS</name>
8621                <description>See MS0_CTL.NS.</description>
8622                <bitRange>[1:1]</bitRange>
8623                <access>read-write</access>
8624              </field>
8625              <field>
8626                <name>PRIO</name>
8627                <description>See MS0_CTL.PRIO</description>
8628                <bitRange>[9:8]</bitRange>
8629                <access>read-write</access>
8630              </field>
8631              <field>
8632                <name>PC_MASK_0</name>
8633                <description>See MS0_CTL.PC_MASK_0.</description>
8634                <bitRange>[16:16]</bitRange>
8635                <access>read-only</access>
8636              </field>
8637              <field>
8638                <name>PC_MASK_15_TO_1</name>
8639                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
8640                <bitRange>[31:17]</bitRange>
8641                <access>read-write</access>
8642              </field>
8643            </fields>
8644          </register>
8645          <register>
8646            <name>MS15_CTL</name>
8647            <description>Master 15 protection context control</description>
8648            <addressOffset>0x3C</addressOffset>
8649            <size>32</size>
8650            <access>read-write</access>
8651            <resetValue>0x303</resetValue>
8652            <resetMask>0xFFFF0303</resetMask>
8653            <fields>
8654              <field>
8655                <name>P</name>
8656                <description>See MS0_CTL.P.</description>
8657                <bitRange>[0:0]</bitRange>
8658                <access>read-write</access>
8659              </field>
8660              <field>
8661                <name>NS</name>
8662                <description>See MS0_CTL.NS.</description>
8663                <bitRange>[1:1]</bitRange>
8664                <access>read-write</access>
8665              </field>
8666              <field>
8667                <name>PRIO</name>
8668                <description>See MS0_CTL.PRIO</description>
8669                <bitRange>[9:8]</bitRange>
8670                <access>read-write</access>
8671              </field>
8672              <field>
8673                <name>PC_MASK_0</name>
8674                <description>See MS0_CTL.PC_MASK_0.</description>
8675                <bitRange>[16:16]</bitRange>
8676                <access>read-only</access>
8677              </field>
8678              <field>
8679                <name>PC_MASK_15_TO_1</name>
8680                <description>See MS0_CTL.PC_MASK_15_TO_1.</description>
8681                <bitRange>[31:17]</bitRange>
8682                <access>read-write</access>
8683              </field>
8684            </fields>
8685          </register>
8686          <cluster>
8687            <dim>16</dim>
8688            <dimIncrement>64</dimIncrement>
8689            <name>SMPU_STRUCT[%s]</name>
8690            <description>SMPU structure</description>
8691            <addressOffset>0x00002000</addressOffset>
8692            <register>
8693              <name>ADDR0</name>
8694              <description>SMPU region address 0 (slave structure)</description>
8695              <addressOffset>0x0</addressOffset>
8696              <size>32</size>
8697              <access>read-write</access>
8698              <resetValue>0x0</resetValue>
8699              <resetMask>0x0</resetMask>
8700              <fields>
8701                <field>
8702                  <name>SUBREGION_DISABLE</name>
8703                  <description>This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:
8704Bit 0: subregion 0 disable.
8705Bit 1: subregion 1 disable.
8706Bit 2: subregion 2 disable.
8707Bit 3: subregion 3 disable.
8708Bit 4: subregion 4 disable.
8709Bit 5: subregion 5 disable.
8710Bit 6: subregion 6 disable.
8711Bit 7: subregion 7 disable.
8712E.g., a 64 KByte address region (ATT0.REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by ATT0 applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.</description>
8713                  <bitRange>[7:0]</bitRange>
8714                  <access>read-write</access>
8715                </field>
8716                <field>
8717                  <name>ADDR24</name>
8718                  <description>This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT0.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.</description>
8719                  <bitRange>[31:8]</bitRange>
8720                  <access>read-write</access>
8721                </field>
8722              </fields>
8723            </register>
8724            <register>
8725              <name>ATT0</name>
8726              <description>SMPU region attributes 0 (slave structure)</description>
8727              <addressOffset>0x4</addressOffset>
8728              <size>32</size>
8729              <access>read-write</access>
8730              <resetValue>0x100</resetValue>
8731              <resetMask>0x80000100</resetMask>
8732              <fields>
8733                <field>
8734                  <name>UR</name>
8735                  <description>User read enable:
8736'0': Disabled (user, read accesses are NOT allowed).
8737'1': Enabled (user, read accesses are allowed).</description>
8738                  <bitRange>[0:0]</bitRange>
8739                  <access>read-write</access>
8740                </field>
8741                <field>
8742                  <name>UW</name>
8743                  <description>User write enable:
8744'0': Disabled (user, write accesses are NOT allowed).
8745'1': Enabled (user, write accesses are allowed).</description>
8746                  <bitRange>[1:1]</bitRange>
8747                  <access>read-write</access>
8748                </field>
8749                <field>
8750                  <name>UX</name>
8751                  <description>User execute enable:
8752'0': Disabled (user, execute accesses are NOT allowed).
8753'1': Enabled (user, execute accesses are allowed).</description>
8754                  <bitRange>[2:2]</bitRange>
8755                  <access>read-write</access>
8756                </field>
8757                <field>
8758                  <name>PR</name>
8759                  <description>Privileged read enable:
8760'0': Disabled (privileged, read accesses are NOT allowed).
8761'1': Enabled (privileged, read accesses are allowed).</description>
8762                  <bitRange>[3:3]</bitRange>
8763                  <access>read-write</access>
8764                </field>
8765                <field>
8766                  <name>PW</name>
8767                  <description>Privileged write enable:
8768'0': Disabled (privileged, write accesses are NOT allowed).
8769'1': Enabled (privileged, write accesses are allowed).</description>
8770                  <bitRange>[4:4]</bitRange>
8771                  <access>read-write</access>
8772                </field>
8773                <field>
8774                  <name>PX</name>
8775                  <description>Privileged execute enable:
8776'0': Disabled (privileged, execute accesses are NOT allowed).
8777'1': Enabled (privileged, execute accesses are allowed).</description>
8778                  <bitRange>[5:5]</bitRange>
8779                  <access>read-write</access>
8780                </field>
8781                <field>
8782                  <name>NS</name>
8783                  <description>Non-secure:
8784'0': Secure (secure accesses allowed, non-secure access NOT allowed).
8785'1': Non-secure (both secure and non-secure accesses allowed).</description>
8786                  <bitRange>[6:6]</bitRange>
8787                  <access>read-write</access>
8788                </field>
8789                <field>
8790                  <name>PC_MASK_0</name>
8791                  <description>This field specifies protection context identifier based access control for protection context '0'.</description>
8792                  <bitRange>[8:8]</bitRange>
8793                  <access>read-only</access>
8794                </field>
8795                <field>
8796                  <name>PC_MASK_15_TO_1</name>
8797                  <description>This field specifies protection context identifier based access control.
8798Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.</description>
8799                  <bitRange>[23:9]</bitRange>
8800                  <access>read-write</access>
8801                </field>
8802                <field>
8803                  <name>REGION_SIZE</name>
8804                  <description>This field specifies the region size:
8805'0'-'6': Undefined.
8806'7': 256 B region
8807'8': 512 B region
8808'9': 1 KB region
8809'10': 2 KB region
8810'11': 4 KB region
8811'12': 8 KB region
8812'13': 16 KB region
8813'14': 32 KB region
8814'15': 64 KB region
8815'16': 128 KB region
8816'17': 256 KB region
8817'18': 512 KB region
8818'19': 1 MB region
8819'20': 2 MB region
8820'21': 4 MB region
8821'22': 8 MB region
8822'23': 16 MB region
8823'24': 32 MB region
8824'25': 64 MB region
8825'26': 128 MB region
8826'27': 256 MB region
8827'28': 512 MB region
8828'39': 1 GB region
8829'30': 2 GB region
8830'31': 4 GB region</description>
8831                  <bitRange>[28:24]</bitRange>
8832                  <access>read-write</access>
8833                </field>
8834                <field>
8835                  <name>PC_MATCH</name>
8836                  <description>This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:
8837'0': PC field participates in 'access evaluation'.
8838'1': PC field participates in 'matching'.
8839
8840'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions.
8841'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes.
8842
8843Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.</description>
8844                  <bitRange>[30:30]</bitRange>
8845                  <access>read-write</access>
8846                </field>
8847                <field>
8848                  <name>ENABLED</name>
8849                  <description>Region enable:
8850'0': Disabled. A disabled region will never result in a match on the bus transfer address.
8851'1': Enabled.
8852
8853Note: a disabled address region performs logic gating to reduce dynamic power consumption.</description>
8854                  <bitRange>[31:31]</bitRange>
8855                  <access>read-write</access>
8856                </field>
8857              </fields>
8858            </register>
8859            <register>
8860              <name>ADDR1</name>
8861              <description>SMPU region address 1 (master structure)</description>
8862              <addressOffset>0x20</addressOffset>
8863              <size>32</size>
8864              <access>read-only</access>
8865              <resetValue>0x0</resetValue>
8866              <resetMask>0xFFFFFFFF</resetMask>
8867              <fields>
8868                <field>
8869                  <name>SUBREGION_DISABLE</name>
8870                  <description>This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:
8871Bit 0: subregion 0 disable.
8872Bit 1: subregion 1 disable.
8873Bit 2: subregion 2 disable.
8874Bit 3: subregion 3 disable.
8875Bit 4: subregion 4 disable.
8876Bit 5: subregion 5 disable.
8877Bit 6: subregion 6 disable.
8878Bit 7: subregion 7 disable.
8879
8880Two out of a total of eight 32 B subregions are enabled. These subregions includes region structures 0 and 1.
8881
8882Note: this field is read-only.</description>
8883                  <bitRange>[7:0]</bitRange>
8884                  <access>read-only</access>
8885                </field>
8886                <field>
8887                  <name>ADDR24</name>
8888                  <description>This field specifies the most significant bits of the 32-bit address of an address region.
8889
8890'ADDR_DEF1': base address of structure.
8891
8892Note: this field is read-only.</description>
8893                  <bitRange>[31:8]</bitRange>
8894                  <access>read-only</access>
8895                </field>
8896              </fields>
8897            </register>
8898            <register>
8899              <name>ATT1</name>
8900              <description>SMPU region attributes 1 (master structure)</description>
8901              <addressOffset>0x24</addressOffset>
8902              <size>32</size>
8903              <access>read-write</access>
8904              <resetValue>0x7000109</resetValue>
8905              <resetMask>0x9F00012D</resetMask>
8906              <fields>
8907                <field>
8908                  <name>UR</name>
8909                  <description>User read enable:
8910'0': Disabled (user, read accesses are NOT allowed).
8911'1': Enabled (user, read accesses are allowed).
8912
8913Note that this register is constant '1'; i.e. user read accesses are ALWAYS allowed.</description>
8914                  <bitRange>[0:0]</bitRange>
8915                  <access>read-only</access>
8916                </field>
8917                <field>
8918                  <name>UW</name>
8919                  <description>User write enable:
8920'0': Disabled (user, write accesses are NOT allowed).
8921'1': Enabled (user, write accesses are allowed).</description>
8922                  <bitRange>[1:1]</bitRange>
8923                  <access>read-write</access>
8924                </field>
8925                <field>
8926                  <name>UX</name>
8927                  <description>User execute enable:
8928'0': Disabled (user, execute accesses are NOT allowed).
8929'1': Enabled (user, execute accesses are allowed).
8930
8931Note that this register is constant '0'; i.e. user execute accesses are NEVER allowed.</description>
8932                  <bitRange>[2:2]</bitRange>
8933                  <access>read-only</access>
8934                </field>
8935                <field>
8936                  <name>PR</name>
8937                  <description>Privileged read enable:
8938'0': Disabled (privileged, read accesses are NOT allowed).
8939'1': Enabled (privileged, read accesses are allowed).
8940
8941Note that this register is constant '1'; i.e. privileged read accesses are ALWAYS allowed.</description>
8942                  <bitRange>[3:3]</bitRange>
8943                  <access>read-only</access>
8944                </field>
8945                <field>
8946                  <name>PW</name>
8947                  <description>Privileged write enable:
8948'0': Disabled (privileged, write accesses are NOT allowed).
8949'1': Enabled (privileged, write accesses are allowed).</description>
8950                  <bitRange>[4:4]</bitRange>
8951                  <access>read-write</access>
8952                </field>
8953                <field>
8954                  <name>PX</name>
8955                  <description>Privileged execute enable:
8956'0': Disabled (privileged, execute accesses are NOT allowed).
8957'1': Enabled (privileged, execute accesses are allowed).
8958
8959Note that this register is constant '0'; i.e. privileged execute accesses are NEVER allowed.</description>
8960                  <bitRange>[5:5]</bitRange>
8961                  <access>read-only</access>
8962                </field>
8963                <field>
8964                  <name>NS</name>
8965                  <description>Non-secure:
8966'0': Secure (secure accesses allowed, non-secure access NOT allowed).
8967'1': Non-secure (both secure and non-secure accesses allowed).</description>
8968                  <bitRange>[6:6]</bitRange>
8969                  <access>read-write</access>
8970                </field>
8971                <field>
8972                  <name>PC_MASK_0</name>
8973                  <description>This field specifies protection context identifier based access control for protection context '0'.</description>
8974                  <bitRange>[8:8]</bitRange>
8975                  <access>read-only</access>
8976                </field>
8977                <field>
8978                  <name>PC_MASK_15_TO_1</name>
8979                  <description>This field specifies protection context identifier based access control.
8980Bit i: protection context i+1 enable. If '0', protection context i+1 access is disabled; i.e. not allowed. If '1', protection context i+1 access is enabled; i.e. allowed.</description>
8981                  <bitRange>[23:9]</bitRange>
8982                  <access>read-write</access>
8983                </field>
8984                <field>
8985                  <name>REGION_SIZE</name>
8986                  <description>This field specifies the region size:
8987'7': 256 B region (8 32 B subregions)
8988
8989Note: this field is read-only.</description>
8990                  <bitRange>[28:24]</bitRange>
8991                  <access>read-only</access>
8992                </field>
8993                <field>
8994                  <name>PC_MATCH</name>
8995                  <description>This field specifies if the PC field participates in the 'matching' process or the 'access evaluation' process:
8996'0': PC field participates in 'access evaluation'.
8997'1': PC field participates in 'matching'.
8998
8999'Matching' process. For each protection structure, the process identifies if a transfer address is contained within the address range. This identifies the 'matching' regions.
9000'Access evaluation' process. For each protection structure, the process evaluates the bus transfer access attributes against the access control attributes.
9001
9002Note that it is possible to define different access control for multiple protection contexts by using multiple protection structures with the same address region and PC_MATCH set to '1'.</description>
9003                  <bitRange>[30:30]</bitRange>
9004                  <access>read-write</access>
9005                </field>
9006                <field>
9007                  <name>ENABLED</name>
9008                  <description>Region enable:
9009'0': Disabled. A disabled region will never result in a match on the bus transfer address.
9010'1': Enabled.</description>
9011                  <bitRange>[31:31]</bitRange>
9012                  <access>read-write</access>
9013                </field>
9014              </fields>
9015            </register>
9016          </cluster>
9017        </cluster>
9018        <cluster>
9019          <dim>16</dim>
9020          <dimIncrement>1024</dimIncrement>
9021          <name>MPU[%s]</name>
9022          <description>MPU</description>
9023          <addressOffset>0x00004000</addressOffset>
9024          <register>
9025            <name>MS_CTL</name>
9026            <description>Master control</description>
9027            <addressOffset>0x0</addressOffset>
9028            <size>32</size>
9029            <access>read-write</access>
9030            <resetValue>0x0</resetValue>
9031            <resetMask>0xF000F</resetMask>
9032            <fields>
9033              <field>
9034                <name>PC</name>
9035                <description>Active protection context (PC). Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields. In addition, a write transfer with protection context '0' can change this field (protection context 0 has unrestricted access).
9036
9037The CM0+ MPU MS_CTL register is special: the PC field is modifiable by BOTH HW and SW (for all other masters, the MPU MS_CTL.PC field is modifiable by SW ONLY. For CM0+ PC field HW modifications, the following holds:
9038* On entry of a CM0_PC0/1/2/3_HANDLER exception/interrupt handler:
9039   IF (the new PC is the same as MS_CTL.PC)
9040       PC is not affected; PC_SAVED is not affected.
9041   ELSE IF (CM0_PC_CTL.VALID[MS_CTL.PC])
9042       An AHB-Lite bus error is generated for the exception handler fetch;
9043       PC is not affected; PC_SAVED is not affected.
9044   ELSE
9045       PC = 'new PC'; PC_SAVED = PC (push operation).
9046* On entry of any other exception/interrupt handler:
9047   PC = PC_SAVED; PC_SAVED is not affected (pop operation).
9048
9049Note that the CM0_PC0/1/2/3_HANDLER and CM0_PC_CTL registers are part of repecitve CPUSS MMIO registers.
9050
9051Note: this field is NOT used by the DW controllers, DMA controller, AXI DMA controller, CRYPTO component and VIDEOSS.</description>
9052                <bitRange>[3:0]</bitRange>
9053                <access>read-write</access>
9054              </field>
9055              <field>
9056                <name>PC_SAVED</name>
9057                <description>Saved protection context. Modifications to this field are constrained by the associated SMPU MS_CTL.PC_MASK_0 and MS_CTL.PC_MASK_15_TO_1[] fields.
9058
9059Note: this field is ONLY used by the CM0+.</description>
9060                <bitRange>[19:16]</bitRange>
9061                <access>read-write</access>
9062              </field>
9063            </fields>
9064          </register>
9065          <register>
9066            <dim>127</dim>
9067            <dimIncrement>4</dimIncrement>
9068            <name>MS_CTL_READ_MIR[%s]</name>
9069            <description>Master control read mirror</description>
9070            <addressOffset>0x4</addressOffset>
9071            <size>32</size>
9072            <access>read-only</access>
9073            <resetValue>0x0</resetValue>
9074            <resetMask>0xF000F</resetMask>
9075            <fields>
9076              <field>
9077                <name>PC</name>
9078                <description>Read-only mirror of MS_CTL.PC</description>
9079                <bitRange>[3:0]</bitRange>
9080                <access>read-only</access>
9081              </field>
9082              <field>
9083                <name>PC_SAVED</name>
9084                <description>Read-only mirror of MS_CTL.PC_SAVED</description>
9085                <bitRange>[19:16]</bitRange>
9086                <access>read-only</access>
9087              </field>
9088            </fields>
9089          </register>
9090          <cluster>
9091            <dim>8</dim>
9092            <dimIncrement>32</dimIncrement>
9093            <name>MPU_STRUCT[%s]</name>
9094            <description>MPU structure</description>
9095            <addressOffset>0x00000200</addressOffset>
9096            <register>
9097              <name>ADDR</name>
9098              <description>MPU region address</description>
9099              <addressOffset>0x0</addressOffset>
9100              <size>32</size>
9101              <access>read-write</access>
9102              <resetValue>0x0</resetValue>
9103              <resetMask>0x0</resetMask>
9104              <fields>
9105                <field>
9106                  <name>SUBREGION_DISABLE</name>
9107                  <description>This field is used to individually disabled the eight equally sized subregions in which a region is partitioned. Subregion disable:
9108Bit 0: subregion 0 disable.
9109Bit 1: subregion 1 disable.
9110Bit 2: subregion 2 disable.
9111Bit 3: subregion 3 disable.
9112Bit 4: subregion 4 disable.
9113Bit 5: subregion 5 disable.
9114Bit 6: subregion 6 disable.
9115Bit 7: subregion 7 disable.
9116E.g., a 64 KByte address region (REGION_SIZE is '15') has eight 8 KByte subregions. The access control as defined by MPU_REGION_ATT applies if the bus transfer address is within the address region AND the addressed subregion is NOT disabled. Note that the smallest region size is 256 B and the smallest subregion size is 32 B.</description>
9117                  <bitRange>[7:0]</bitRange>
9118                  <access>read-write</access>
9119                </field>
9120                <field>
9121                  <name>ADDR24</name>
9122                  <description>This field specifies the most significant bits of the 32-bit address of an address region. The region size is defined by ATT.REGION_SIZE. A region of n Byte is always n Byte aligned. As a result, some of the lesser significant address bits of ADDR24 may be ignored in determining whether a bus transfer address is within an address region. E.g., a 64 KByte address region (REGION_SIZE is '15') is 64 KByte aligned, and ADDR24[7:0] are ignored.</description>
9123                  <bitRange>[31:8]</bitRange>
9124                  <access>read-write</access>
9125                </field>
9126              </fields>
9127            </register>
9128            <register>
9129              <name>ATT</name>
9130              <description>MPU region attrributes</description>
9131              <addressOffset>0x4</addressOffset>
9132              <size>32</size>
9133              <access>read-write</access>
9134              <resetValue>0x0</resetValue>
9135              <resetMask>0x80000000</resetMask>
9136              <fields>
9137                <field>
9138                  <name>UR</name>
9139                  <description>User read enable:
9140'0': Disabled (user, read accesses are NOT allowed).
9141'1': Enabled (user, read accesses are allowed).</description>
9142                  <bitRange>[0:0]</bitRange>
9143                  <access>read-write</access>
9144                </field>
9145                <field>
9146                  <name>UW</name>
9147                  <description>User write enable:
9148'0': Disabled (user, write accesses are NOT allowed).
9149'1': Enabled (user, write accesses are allowed).</description>
9150                  <bitRange>[1:1]</bitRange>
9151                  <access>read-write</access>
9152                </field>
9153                <field>
9154                  <name>UX</name>
9155                  <description>User execute enable:
9156'0': Disabled (user, execute accesses are NOT allowed).
9157'1': Enabled (user, execute accesses are allowed).</description>
9158                  <bitRange>[2:2]</bitRange>
9159                  <access>read-write</access>
9160                </field>
9161                <field>
9162                  <name>PR</name>
9163                  <description>Privileged read enable:
9164'0': Disabled (privileged, read accesses are NOT allowed).
9165'1': Enabled (privileged, read accesses are allowed).</description>
9166                  <bitRange>[3:3]</bitRange>
9167                  <access>read-write</access>
9168                </field>
9169                <field>
9170                  <name>PW</name>
9171                  <description>Privileged write enable:
9172'0': Disabled (privileged, write accesses are NOT allowed).
9173'1': Enabled (privileged, write accesses are allowed).</description>
9174                  <bitRange>[4:4]</bitRange>
9175                  <access>read-write</access>
9176                </field>
9177                <field>
9178                  <name>PX</name>
9179                  <description>Privileged execute enable:
9180'0': Disabled (privileged, execute accesses are NOT allowed).
9181'1': Enabled (privileged, execute accesses are allowed).</description>
9182                  <bitRange>[5:5]</bitRange>
9183                  <access>read-write</access>
9184                </field>
9185                <field>
9186                  <name>NS</name>
9187                  <description>Non-secure:
9188'0': Secure (secure accesses allowed, non-secure access NOT allowed).
9189'1': Non-secure (both secure and non-secure accesses allowed).</description>
9190                  <bitRange>[6:6]</bitRange>
9191                  <access>read-write</access>
9192                </field>
9193                <field>
9194                  <name>REGION_SIZE</name>
9195                  <description>This field specifies the region size:
9196'0'-'6': Undefined.
9197'7': 256 B region
9198'8': 512 B region
9199'9': 1 KB region
9200'10': 2 KB region
9201'11': 4 KB region
9202'12': 8 KB region
9203'13': 16 KB region
9204'14': 32 KB region
9205'15': 64 KB region
9206'16': 128 KB region
9207'17': 256 KB region
9208'18': 512 KB region
9209'19': 1 MB region
9210'20': 2 MB region
9211'21': 4 MB region
9212'22': 8 MB region
9213'23': 16 MB region
9214'24': 32 MB region
9215'25': 64 MB region
9216'26': 128 MB region
9217'27': 256 MB region
9218'28': 512 MB region
9219'39': 1 GB region
9220'30': 2 GB region
9221'31': 4 GB region</description>
9222                  <bitRange>[28:24]</bitRange>
9223                  <access>read-write</access>
9224                </field>
9225                <field>
9226                  <name>ENABLED</name>
9227                  <description>Region enable:
9228'0': Disabled. A disabled region will never result in a match on the bus transfer address.
9229'1': Enabled.
9230
9231Note: a disabled address region performs logic gating to reduce dynamic power consumption.</description>
9232                  <bitRange>[31:31]</bitRange>
9233                  <access>read-write</access>
9234                </field>
9235              </fields>
9236            </register>
9237          </cluster>
9238        </cluster>
9239      </registers>
9240    </peripheral>
9241    <peripheral>
9242      <name>FLASHC</name>
9243      <description>Flash controller</description>
9244      <baseAddress>0x40240000</baseAddress>
9245      <addressBlock>
9246        <offset>0</offset>
9247        <size>65536</size>
9248        <usage>registers</usage>
9249      </addressBlock>
9250      <registers>
9251        <register>
9252          <name>FLASH_CTL</name>
9253          <description>Control</description>
9254          <addressOffset>0x0</addressOffset>
9255          <size>32</size>
9256          <access>read-write</access>
9257          <resetValue>0x110000</resetValue>
9258          <resetMask>0x77330F</resetMask>
9259          <fields>
9260            <field>
9261              <name>MAIN_WS</name>
9262              <description>FLASH macro main interface wait states:
9263'0': 0 wait states.
9264...
9265'15': 15 wait states</description>
9266              <bitRange>[3:0]</bitRange>
9267              <access>read-write</access>
9268            </field>
9269            <field>
9270              <name>MAIN_MAP</name>
9271              <description>Specifies mapping of FLASH macro main array.
92720: Mapping A.
92731: Mapping B.
9274
9275This field is only used when MAIN_BANK_MODE is '1' (dual bank mode).</description>
9276              <bitRange>[8:8]</bitRange>
9277              <access>read-write</access>
9278            </field>
9279            <field>
9280              <name>WORK_MAP</name>
9281              <description>Specifies mapping of FLASH macro work array.
92820: Mapping A.
92831: Mapping B.
9284
9285This field is only used when WORK_BANK_MODE is '1' (dual bank mode).</description>
9286              <bitRange>[9:9]</bitRange>
9287              <access>read-write</access>
9288            </field>
9289            <field>
9290              <name>MAIN_BANK_MODE</name>
9291              <description>Specifies bank mode of FLASH macro main array.
92920: Single bank mode.
92931: Dual bank mode.</description>
9294              <bitRange>[12:12]</bitRange>
9295              <access>read-write</access>
9296            </field>
9297            <field>
9298              <name>WORK_BANK_MODE</name>
9299              <description>Specifies bank mode of FLASH macro work array.
93000: Single bank mode.
93011: Dual bank mode.</description>
9302              <bitRange>[13:13]</bitRange>
9303              <access>read-write</access>
9304            </field>
9305            <field>
9306              <name>MAIN_ECC_EN</name>
9307              <description>Enable ECC checking for FLASH main interface:
93080: Disabled. ECC checking/reporting on FLASH main interface is disabled. No correctable or non-correctable faults are reported.
93091: Enabled.</description>
9310              <bitRange>[16:16]</bitRange>
9311              <access>read-write</access>
9312            </field>
9313            <field>
9314              <name>MAIN_ECC_INJ_EN</name>
9315              <description>Enable error injection for FLASH main interface.
9316When'1', the parity (ECC_CTL.PARITY[7:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address.</description>
9317              <bitRange>[17:17]</bitRange>
9318              <access>read-write</access>
9319            </field>
9320            <field>
9321              <name>MAIN_ERR_SILENT</name>
9322              <description>Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error, a FLASH macro main interface internal error, a FLASH macro main interface memory hole access):
93230: Bus transfer has a bus error.
93241: Bus transfer does NOT have a bus error; i.e. the error is 'silent'
9325In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer.
9326
9327This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error.
9328
9329Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro main interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered).
9330
9331Note: fault reporting can be used to identify the error that occurred:
9332- FLASH macro main interface internal error.
9333- FLASH macro main interface non-recoverable ECC error.
9334- FLASH macro main interface recoverable ECC error.
9335- FLASH macro main interface memory hole error.</description>
9336              <bitRange>[18:18]</bitRange>
9337              <access>read-write</access>
9338            </field>
9339            <field>
9340              <name>WORK_ECC_EN</name>
9341              <description>Enable ECC checking for FLASH work interface:
93420: Disabled. ECC checking/reporting on FLASH work interface is disabled. No correctable or non-correctable faults are reported.
93431: Enabled.</description>
9344              <bitRange>[20:20]</bitRange>
9345              <access>read-write</access>
9346            </field>
9347            <field>
9348              <name>WORK_ECC_INJ_EN</name>
9349              <description>Enable error injection for FLASH work interface.
9350When'1', the parity (ECC_CTL.PARITY[6:0]) is used for a load from the ECC_CTL.WORD_ADDR[23:0] word address.</description>
9351              <bitRange>[21:21]</bitRange>
9352              <access>read-write</access>
9353            </field>
9354            <field>
9355              <name>WORK_ERR_SILENT</name>
9356              <description>Specifies bus transfer behavior for a non-recoverable error on the FLASH macro work interface (either a non-correctable ECC error, a FLASH macro work interface internal error, a FLASH macro work interface memory hole access):
93570: Bus transfer has a bus error.
93581: Bus transfer does NOT have a bus error; i.e. the error is 'silent'
9359In either case, the erroneous FLASH macro data is returned by the bus master interface. The erroneous data is NOT placed in a bus master interface's cache and/or buffer.
9360
9361This field is ONLY used by CPU (and debug i.e. SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU bus transfers always have a bus transfer with a bus error, in case of a non-recoverable error.
9362
9363Note: All CPU bus masters have dedicated status registers (CM0_STATUS and CM4_STATUS) to register the occurrence of FLASH macro work interface internal errors (non-correctable ECC errors and memory hole errors are NOT registered).
9364
9365Note: fault reporting can be used to identify the error that occurred:
9366- FLASH macro work interface internal error.
9367- FLASH macro work interface non-recoverable ECC error.
9368- FLASH macro work interface recoverable ECC error.
9369- FLASH macro work interface memory hole error.</description>
9370              <bitRange>[22:22]</bitRange>
9371              <access>read-write</access>
9372            </field>
9373          </fields>
9374        </register>
9375        <register>
9376          <name>FLASH_PWR_CTL</name>
9377          <description>Flash power control</description>
9378          <addressOffset>0x4</addressOffset>
9379          <size>32</size>
9380          <access>read-write</access>
9381          <resetValue>0x3</resetValue>
9382          <resetMask>0x3</resetMask>
9383          <fields>
9384            <field>
9385              <name>ENABLE</name>
9386              <description>Controls 'enable' pin of the Flash memory.</description>
9387              <bitRange>[0:0]</bitRange>
9388              <access>read-write</access>
9389            </field>
9390            <field>
9391              <name>ENABLE_HV</name>
9392              <description>Controls 'enable_hv' pin of the Flash memory.</description>
9393              <bitRange>[1:1]</bitRange>
9394              <access>read-write</access>
9395            </field>
9396          </fields>
9397        </register>
9398        <register>
9399          <name>FLASH_CMD</name>
9400          <description>Command</description>
9401          <addressOffset>0x8</addressOffset>
9402          <size>32</size>
9403          <access>read-write</access>
9404          <resetValue>0x0</resetValue>
9405          <resetMask>0x3</resetMask>
9406          <fields>
9407            <field>
9408              <name>INV</name>
9409              <description>Invalidation of ALL caches (for CM0+ and CM4) and ALL buffers. SW writes a '1' to clear the caches. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks. The caches' LRU structures are also reset to their default state.</description>
9410              <bitRange>[0:0]</bitRange>
9411              <access>read-write</access>
9412            </field>
9413            <field>
9414              <name>BUFF_INV</name>
9415              <description>Invalidation of ALL buffers (does not invalidate the caches). SW writes a '1' to clear the buffers. HW sets this field to '0' when the operation is completed. The operation takes a maximum of three clock cycles on the slowest of the clk_slow and clk_fast clocks.
9416
9417Note: the caches only capture FLASH macro main array data. Therefore, invalidating just the buffers (BUFF_INV) does not invalidate captures main array data in the caches.</description>
9418              <bitRange>[1:1]</bitRange>
9419              <access>read-write</access>
9420            </field>
9421          </fields>
9422        </register>
9423        <register>
9424          <name>ECC_CTL</name>
9425          <description>ECC control</description>
9426          <addressOffset>0x2A0</addressOffset>
9427          <size>32</size>
9428          <access>read-write</access>
9429          <resetValue>0x0</resetValue>
9430          <resetMask>0xFFFFFFFF</resetMask>
9431          <fields>
9432            <field>
9433              <name>WORD_ADDR</name>
9434              <description>Specifies the word address where an error will be injected.
9435- For cache SRAM ECC, the word address WORD_ADDR[23:0] is device address A[25:2]. On a FLASH macro refill to this word address and when the corresponding CM0/4_CA_CTL.RAM_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) is injected and stored in the cache.
9436- For FLASH main interface ECC, the word address WORD_ADDR[23:0] is device address A[26:3]. On a FLASH main interface read and when FLASH_CTL.MAIN_ECC_INJ_EN bit is '1', the parity (PARITY[7:0]) replaces the FLASH macro parity (FLASH main interface read path is manipulated).
9437- For FLASH work interface ECC, the word address WORD_ADDR[23:0] is device address A[24:2]. On a FLASH work interface read and when FLASH_CTL.WORK_ECC_INJ_EN bit is '1', the parity (PARITY[6:0]) replaces the FLASH macro parity (FLASH work interface read path is manipulated).</description>
9438              <bitRange>[23:0]</bitRange>
9439              <access>read-write</access>
9440            </field>
9441            <field>
9442              <name>PARITY</name>
9443              <description>ECC parity to use for ECC error injection at address WORD_ADDR.
9444- For cache SRAM ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word.
9445- For FLASH main interface ECC, the 8-bit parity PARITY[7:0] is for a 64-bit word.
9446- For FLASH work interface ECC, the 7-bit parity PARITY[6:0] is for a 32-bit word.</description>
9447              <bitRange>[31:24]</bitRange>
9448              <access>read-write</access>
9449            </field>
9450          </fields>
9451        </register>
9452        <register>
9453          <name>FM_SRAM_ECC_CTL0</name>
9454          <description>eCT Flash SRAM ECC control 0</description>
9455          <addressOffset>0x2B0</addressOffset>
9456          <size>32</size>
9457          <access>read-write</access>
9458          <resetValue>0x0</resetValue>
9459          <resetMask>0xFFFFFFFF</resetMask>
9460          <fields>
9461            <field>
9462              <name>ECC_INJ_DATA</name>
9463              <description>32-bit data for ECC error injection test of eCT Flash SRAM ECC logic.</description>
9464              <bitRange>[31:0]</bitRange>
9465              <access>read-write</access>
9466            </field>
9467          </fields>
9468        </register>
9469        <register>
9470          <name>FM_SRAM_ECC_CTL1</name>
9471          <description>eCT Flash SRAM ECC control 1</description>
9472          <addressOffset>0x2B4</addressOffset>
9473          <size>32</size>
9474          <access>read-write</access>
9475          <resetValue>0x0</resetValue>
9476          <resetMask>0x7F</resetMask>
9477          <fields>
9478            <field>
9479              <name>ECC_INJ_PARITY</name>
9480              <description>7-bit parity for ECC error injection test of eCT Flash SRAM ECC logic.</description>
9481              <bitRange>[6:0]</bitRange>
9482              <access>read-write</access>
9483            </field>
9484          </fields>
9485        </register>
9486        <register>
9487          <name>FM_SRAM_ECC_CTL2</name>
9488          <description>eCT Flash SRAM ECC control 2</description>
9489          <addressOffset>0x2B8</addressOffset>
9490          <size>32</size>
9491          <access>read-only</access>
9492          <resetValue>0x0</resetValue>
9493          <resetMask>0xFFFFFFFF</resetMask>
9494          <fields>
9495            <field>
9496              <name>CORRECTED_DATA</name>
9497              <description>32-bit corrected data output of the ECC syndrome logic.</description>
9498              <bitRange>[31:0]</bitRange>
9499              <access>read-only</access>
9500            </field>
9501          </fields>
9502        </register>
9503        <register>
9504          <name>FM_SRAM_ECC_CTL3</name>
9505          <description>eCT Flash SRAM ECC control 3</description>
9506          <addressOffset>0x2BC</addressOffset>
9507          <size>32</size>
9508          <access>read-write</access>
9509          <resetValue>0x1</resetValue>
9510          <resetMask>0x111</resetMask>
9511          <fields>
9512            <field>
9513              <name>ECC_ENABLE</name>
9514              <description>ECC generation/check enable for eCT Flash SRAM memory.</description>
9515              <bitRange>[0:0]</bitRange>
9516              <access>read-write</access>
9517            </field>
9518            <field>
9519              <name>ECC_INJ_EN</name>
9520              <description>eCT Flash SRAM ECC error injection test enable. Follow the steps below for ECC logic test:
95211. Write corrupted or uncorrupted 39-bit data to FM_SRAM_ECC_CTL0/1 registers.
95222. Set the ECC_INJ_EN bit to '1'.
95233. Confirm that the bit ECC_TEST_FAIL is '0'. If this is not the case, start over at item 1 because the eCT Flash was not idle.
95244. Check the corrected data in FM_SRAM_ECC_CTL2.
95255. Confirm that fault was reported to fault structure, and check syndrome (only applicable if
9526corrupted data was written in step 1).
95276. If not finished, start over at 1 with different data.</description>
9528              <bitRange>[4:4]</bitRange>
9529              <access>read-write</access>
9530            </field>
9531            <field>
9532              <name>ECC_TEST_FAIL</name>
9533              <description>Status of ECC test.
95341 : ECC test failed because eCT Flash macro is busy and using the SRAM.
95350: ECC was performed.</description>
9536              <bitRange>[8:8]</bitRange>
9537              <access>read-only</access>
9538            </field>
9539          </fields>
9540        </register>
9541        <register>
9542          <name>CM0_CA_CTL0</name>
9543          <description>CM0+ cache control</description>
9544          <addressOffset>0x400</addressOffset>
9545          <size>32</size>
9546          <access>read-write</access>
9547          <resetValue>0xC0000001</resetValue>
9548          <resetMask>0xC7030003</resetMask>
9549          <fields>
9550            <field>
9551              <name>RAM_ECC_EN</name>
9552              <description>Enable ECC checking for cache accesses:
95530: Disabled.
95541: Enabled.</description>
9555              <bitRange>[0:0]</bitRange>
9556              <access>read-write</access>
9557            </field>
9558            <field>
9559              <name>RAM_ECC_INJ_EN</name>
9560              <description>Enable error injection for cache.
9561When '1', the parity (ECC_CTL.PARITY[6:0]) is used when a refill is done from the FLASH macro to the ECC_CTL.WORD_ADDR[23:0] word address.</description>
9562              <bitRange>[1:1]</bitRange>
9563              <access>read-write</access>
9564            </field>
9565            <field>
9566              <name>WAY</name>
9567              <description>Specifies the cache way for which cache information is provided in CM0_CA_STATUS0/1/2.</description>
9568              <bitRange>[17:16]</bitRange>
9569              <access>read-write</access>
9570            </field>
9571            <field>
9572              <name>SET_ADDR</name>
9573              <description>Specifies the cache set for which cache information is provided in CM0_CA_STATUS0/1/2.</description>
9574              <bitRange>[26:24]</bitRange>
9575              <access>read-write</access>
9576            </field>
9577            <field>
9578              <name>PREF_EN</name>
9579              <description>Prefetch enable:
95800: Disabled.
95811: Enabled.
9582
9583Prefetching requires the cache to be enabled; i.e. ENABLED is '1'.</description>
9584              <bitRange>[30:30]</bitRange>
9585              <access>read-write</access>
9586            </field>
9587            <field>
9588              <name>CA_EN</name>
9589              <description>Cache enable:
95900: Disabled. The cache tag valid bits are reset to '0's and the cache LRU information is set to '1's (making way 0 the LRU way and way 3 the MRU way).
95911: Enabled.</description>
9592              <bitRange>[31:31]</bitRange>
9593              <access>read-write</access>
9594            </field>
9595          </fields>
9596        </register>
9597        <register>
9598          <name>CM0_CA_CTL1</name>
9599          <description>CM0+ cache control</description>
9600          <addressOffset>0x404</addressOffset>
9601          <size>32</size>
9602          <access>read-write</access>
9603          <resetValue>0xFA050003</resetValue>
9604          <resetMask>0xFFFF0003</resetMask>
9605          <fields>
9606            <field>
9607              <name>PWR_MODE</name>
9608              <description>Specifies power mode for CM0 cache.
9609The following sequnece should be followed for turning OFF/ON the cache SRAM.
9610Turn OFF sequence:
9611a) Write CM0_CA_CTL0 to disable cache.
9612b) Write CM0_CA_CTL1 to turn OFF cache SRAM.
9613Turn ON sequence:
9614a) Write CM0_CA_CTL1 to turn ON cache SRAM.
9615b) Delay to allow power up of cache SRAM. Delay should be at a minimum of CM0_CA_CTL2.PWRUP_DELAY CLK_SLOW clock cycles.
9616c) Write CM0_CA_CTL0 to enable cache.</description>
9617              <bitRange>[1:0]</bitRange>
9618              <access>read-write</access>
9619              <enumeratedValues>
9620                <enumeratedValue>
9621                  <name>OFF</name>
9622                  <description>Power OFF the CM0 cache SRAM.</description>
9623                  <value>0</value>
9624                </enumeratedValue>
9625                <enumeratedValue>
9626                  <name>RSVD</name>
9627                  <description>Undefined</description>
9628                  <value>1</value>
9629                </enumeratedValue>
9630                <enumeratedValue>
9631                  <name>RETAINED</name>
9632                  <description>Put CM0 cache SRAM in retained mode.</description>
9633                  <value>2</value>
9634                </enumeratedValue>
9635                <enumeratedValue>
9636                  <name>ENABLED</name>
9637                  <description>Enable/Turn ON the CM0 cache SRAM.</description>
9638                  <value>3</value>
9639                </enumeratedValue>
9640              </enumeratedValues>
9641            </field>
9642            <field>
9643              <name>VECTKEYSTAT</name>
9644              <description>Register key (to prevent accidental writes).
9645- Should be written with a 0x05fa key value for the write to take effect.
9646- Always reads as 0xfa05.
9647
9648Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.</description>
9649              <bitRange>[31:16]</bitRange>
9650              <access>read-only</access>
9651            </field>
9652          </fields>
9653        </register>
9654        <register>
9655          <name>CM0_CA_CTL2</name>
9656          <description>CM0+ cache control</description>
9657          <addressOffset>0x408</addressOffset>
9658          <size>32</size>
9659          <access>read-write</access>
9660          <resetValue>0x12C</resetValue>
9661          <resetMask>0x3FF</resetMask>
9662          <fields>
9663            <field>
9664              <name>PWRUP_DELAY</name>
9665              <description>Number clock cycles delay needed after power domain power up</description>
9666              <bitRange>[9:0]</bitRange>
9667              <access>read-write</access>
9668            </field>
9669          </fields>
9670        </register>
9671        <register>
9672          <name>CM0_CA_STATUS0</name>
9673          <description>CM0+ cache status 0</description>
9674          <addressOffset>0x440</addressOffset>
9675          <size>32</size>
9676          <access>read-only</access>
9677          <resetValue>0x0</resetValue>
9678          <resetMask>0xFFFFFFFF</resetMask>
9679          <fields>
9680            <field>
9681              <name>VALID32</name>
9682              <description>Sixteen valid bits of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR.</description>
9683              <bitRange>[31:0]</bitRange>
9684              <access>read-only</access>
9685            </field>
9686          </fields>
9687        </register>
9688        <register>
9689          <name>CM0_CA_STATUS1</name>
9690          <description>CM0+ cache status 1</description>
9691          <addressOffset>0x444</addressOffset>
9692          <size>32</size>
9693          <access>read-only</access>
9694          <resetValue>0x0</resetValue>
9695          <resetMask>0x0</resetMask>
9696          <fields>
9697            <field>
9698              <name>TAG</name>
9699              <description>Cache line address of the cache line specified by CM0_CA_CTL.WAY and CM0_CA_CTL.SET_ADDR.</description>
9700              <bitRange>[31:0]</bitRange>
9701              <access>read-only</access>
9702            </field>
9703          </fields>
9704        </register>
9705        <register>
9706          <name>CM0_CA_STATUS2</name>
9707          <description>CM0+ cache status 2</description>
9708          <addressOffset>0x448</addressOffset>
9709          <size>32</size>
9710          <access>read-only</access>
9711          <resetValue>0x0</resetValue>
9712          <resetMask>0x0</resetMask>
9713          <fields>
9714            <field>
9715              <name>LRU</name>
9716              <description>Six bit LRU representation of the cache set specified by CM0_CA_CTL.SET_ADDR. The encoding of the field is as follows ('X_LRU_Y' indicates that way X is Less Recently Used than way Y):
9717Bit 5: 0_LRU_1: way 0 less recently used than way 1.
9718Bit 4: 0_LRU_2.
9719Bit 3: 0_LRU_3.
9720Bit 2: 1_LRU_2.
9721Bit 1: 1_LRU_3.
9722Bit 0: 2_LRU_3.</description>
9723              <bitRange>[5:0]</bitRange>
9724              <access>read-only</access>
9725            </field>
9726          </fields>
9727        </register>
9728        <register>
9729          <name>CM0_STATUS</name>
9730          <description>CM0+ interface status</description>
9731          <addressOffset>0x460</addressOffset>
9732          <size>32</size>
9733          <access>read-write</access>
9734          <resetValue>0x0</resetValue>
9735          <resetMask>0x3</resetMask>
9736          <fields>
9737            <field>
9738              <name>MAIN_INTERNAL_ERR</name>
9739              <description>Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access (or debug access via SYS_AP/CM0_AP).
9740
9741SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error.
9742
9743Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT.</description>
9744              <bitRange>[0:0]</bitRange>
9745              <access>read-write</access>
9746            </field>
9747            <field>
9748              <name>WORK_INTERNAL_ERR</name>
9749              <description>See CM0_STATUS.MAIN_INTERNAL_ERROR.</description>
9750              <bitRange>[1:1]</bitRange>
9751              <access>read-write</access>
9752            </field>
9753          </fields>
9754        </register>
9755        <register>
9756          <name>CM4_CA_CTL0</name>
9757          <description>CM4 cache control</description>
9758          <addressOffset>0x480</addressOffset>
9759          <size>32</size>
9760          <access>read-write</access>
9761          <resetValue>0xC0000001</resetValue>
9762          <resetMask>0xC7030003</resetMask>
9763          <fields>
9764            <field>
9765              <name>RAM_ECC_EN</name>
9766              <description>See CM0_CA_CTL.</description>
9767              <bitRange>[0:0]</bitRange>
9768              <access>read-write</access>
9769            </field>
9770            <field>
9771              <name>RAM_ECC_INJ_EN</name>
9772              <description>See CM0_CA_CTL.</description>
9773              <bitRange>[1:1]</bitRange>
9774              <access>read-write</access>
9775            </field>
9776            <field>
9777              <name>WAY</name>
9778              <description>See CM0_CA_CTL.</description>
9779              <bitRange>[17:16]</bitRange>
9780              <access>read-write</access>
9781            </field>
9782            <field>
9783              <name>SET_ADDR</name>
9784              <description>See CM0_CA_CTL.</description>
9785              <bitRange>[26:24]</bitRange>
9786              <access>read-write</access>
9787            </field>
9788            <field>
9789              <name>PREF_EN</name>
9790              <description>See CM0_CA_CTL.</description>
9791              <bitRange>[30:30]</bitRange>
9792              <access>read-write</access>
9793            </field>
9794            <field>
9795              <name>CA_EN</name>
9796              <description>See CM0_CA_CTL.</description>
9797              <bitRange>[31:31]</bitRange>
9798              <access>read-write</access>
9799            </field>
9800          </fields>
9801        </register>
9802        <register>
9803          <name>CM4_CA_CTL1</name>
9804          <description>CM4 cache control</description>
9805          <addressOffset>0x484</addressOffset>
9806          <size>32</size>
9807          <access>read-write</access>
9808          <resetValue>0xFA050003</resetValue>
9809          <resetMask>0xFFFF0003</resetMask>
9810          <fields>
9811            <field>
9812              <name>PWR_MODE</name>
9813              <description>Specifies power mode for CM4 cache. Refer CM0_CA_CTL1 for more details.</description>
9814              <bitRange>[1:0]</bitRange>
9815              <access>read-write</access>
9816              <enumeratedValues>
9817                <enumeratedValue>
9818                  <name>OFF</name>
9819                  <description>See CM0_CA_CTL1</description>
9820                  <value>0</value>
9821                </enumeratedValue>
9822                <enumeratedValue>
9823                  <name>RSVD</name>
9824                  <description>Undefined</description>
9825                  <value>1</value>
9826                </enumeratedValue>
9827                <enumeratedValue>
9828                  <name>RETAINED</name>
9829                  <description>See CM0_CA_CTL1</description>
9830                  <value>2</value>
9831                </enumeratedValue>
9832                <enumeratedValue>
9833                  <name>ENABLED</name>
9834                  <description>See CM0_CA_CTL1</description>
9835                  <value>3</value>
9836                </enumeratedValue>
9837              </enumeratedValues>
9838            </field>
9839            <field>
9840              <name>VECTKEYSTAT</name>
9841              <description>Register key (to prevent accidental writes).
9842- Should be written with a 0x05fa key value for the write to take effect.
9843- Always reads as 0xfa05.
9844
9845Note: Although the SW attribute for this field says ''R', SW need to write the key 0x05fa in this field for this register write to happen. This is a built in protection provided to prevent accidental writes from SW.</description>
9846              <bitRange>[31:16]</bitRange>
9847              <access>read-only</access>
9848            </field>
9849          </fields>
9850        </register>
9851        <register>
9852          <name>CM4_CA_CTL2</name>
9853          <description>CM4 cache control</description>
9854          <addressOffset>0x488</addressOffset>
9855          <size>32</size>
9856          <access>read-write</access>
9857          <resetValue>0x12C</resetValue>
9858          <resetMask>0x3FF</resetMask>
9859          <fields>
9860            <field>
9861              <name>PWRUP_DELAY</name>
9862              <description>Number clock cycles delay needed after power domain power up</description>
9863              <bitRange>[9:0]</bitRange>
9864              <access>read-write</access>
9865            </field>
9866          </fields>
9867        </register>
9868        <register>
9869          <name>CM4_CA_STATUS0</name>
9870          <description>CM4 cache status 0</description>
9871          <addressOffset>0x4C0</addressOffset>
9872          <size>32</size>
9873          <access>read-only</access>
9874          <resetValue>0x0</resetValue>
9875          <resetMask>0xFFFFFFFF</resetMask>
9876          <fields>
9877            <field>
9878              <name>VALID32</name>
9879              <description>See CM0_CA_STATUS0.</description>
9880              <bitRange>[31:0]</bitRange>
9881              <access>read-only</access>
9882            </field>
9883          </fields>
9884        </register>
9885        <register>
9886          <name>CM4_CA_STATUS1</name>
9887          <description>CM4 cache status 1</description>
9888          <addressOffset>0x4C4</addressOffset>
9889          <size>32</size>
9890          <access>read-only</access>
9891          <resetValue>0x0</resetValue>
9892          <resetMask>0x0</resetMask>
9893          <fields>
9894            <field>
9895              <name>TAG</name>
9896              <description>See CM0_CA_STATUS1.</description>
9897              <bitRange>[31:0]</bitRange>
9898              <access>read-only</access>
9899            </field>
9900          </fields>
9901        </register>
9902        <register>
9903          <name>CM4_CA_STATUS2</name>
9904          <description>CM4 cache status 2</description>
9905          <addressOffset>0x4C8</addressOffset>
9906          <size>32</size>
9907          <access>read-only</access>
9908          <resetValue>0x0</resetValue>
9909          <resetMask>0x0</resetMask>
9910          <fields>
9911            <field>
9912              <name>LRU</name>
9913              <description>See CM0_CA_STATUS2.</description>
9914              <bitRange>[5:0]</bitRange>
9915              <access>read-only</access>
9916            </field>
9917          </fields>
9918        </register>
9919        <register>
9920          <name>CM4_STATUS</name>
9921          <description>CM4 interface status</description>
9922          <addressOffset>0x4E0</addressOffset>
9923          <size>32</size>
9924          <access>read-write</access>
9925          <resetValue>0x0</resetValue>
9926          <resetMask>0x3</resetMask>
9927          <fields>
9928            <field>
9929              <name>MAIN_INTERNAL_ERR</name>
9930              <description>Specifies/registers the occurrence of a FLASH macro main interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM4 access (or debug access via SYS_AP/CM4_AP).
9931
9932SW clears this field to '0'. HW sets this field to '1' on a FLASH macro main interface internal error. Typically, SW reads this field after a code section to detect the occurrence of an error.
9933
9934Note: this field is independent of FLASH_CTL.MAIN_ERR_SILENT.</description>
9935              <bitRange>[0:0]</bitRange>
9936              <access>read-write</access>
9937            </field>
9938            <field>
9939              <name>WORK_INTERNAL_ERR</name>
9940              <description>See CM4_STATUS.MAIN_INTERNAL_ERROR.</description>
9941              <bitRange>[1:1]</bitRange>
9942              <access>read-write</access>
9943            </field>
9944          </fields>
9945        </register>
9946        <register>
9947          <name>CRYPTO_BUFF_CTL</name>
9948          <description>Cryptography buffer control</description>
9949          <addressOffset>0x500</addressOffset>
9950          <size>32</size>
9951          <access>read-write</access>
9952          <resetValue>0x40000000</resetValue>
9953          <resetMask>0x40000000</resetMask>
9954          <fields>
9955            <field>
9956              <name>PREF_EN</name>
9957              <description>Prefetch enable:
99580: Disabled.
99591: Enabled.
9960A prefetch will be done when there is read 'hit' on the last 32-bit word of the buffer.
9961For eCT work Flash, prefetch will not be done.</description>
9962              <bitRange>[30:30]</bitRange>
9963              <access>read-write</access>
9964            </field>
9965          </fields>
9966        </register>
9967        <register>
9968          <name>DW0_BUFF_CTL</name>
9969          <description>Datawire 0 buffer control</description>
9970          <addressOffset>0x580</addressOffset>
9971          <size>32</size>
9972          <access>read-write</access>
9973          <resetValue>0x40000000</resetValue>
9974          <resetMask>0x40000000</resetMask>
9975          <fields>
9976            <field>
9977              <name>PREF_EN</name>
9978              <description>See CRYPTO_BUFF_CTL.</description>
9979              <bitRange>[30:30]</bitRange>
9980              <access>read-write</access>
9981            </field>
9982          </fields>
9983        </register>
9984        <register>
9985          <name>DW1_BUFF_CTL</name>
9986          <description>Datawire 1 buffer control</description>
9987          <addressOffset>0x600</addressOffset>
9988          <size>32</size>
9989          <access>read-write</access>
9990          <resetValue>0x40000000</resetValue>
9991          <resetMask>0x40000000</resetMask>
9992          <fields>
9993            <field>
9994              <name>PREF_EN</name>
9995              <description>See CRYPTO_BUFF_CTL.</description>
9996              <bitRange>[30:30]</bitRange>
9997              <access>read-write</access>
9998            </field>
9999          </fields>
10000        </register>
10001        <register>
10002          <name>DMAC_BUFF_CTL</name>
10003          <description>DMA controller buffer control</description>
10004          <addressOffset>0x680</addressOffset>
10005          <size>32</size>
10006          <access>read-write</access>
10007          <resetValue>0x40000000</resetValue>
10008          <resetMask>0x40000000</resetMask>
10009          <fields>
10010            <field>
10011              <name>PREF_EN</name>
10012              <description>See CRYPTO_BUFF_CTL.</description>
10013              <bitRange>[30:30]</bitRange>
10014              <access>read-write</access>
10015            </field>
10016          </fields>
10017        </register>
10018        <register>
10019          <name>EXT_MS0_BUFF_CTL</name>
10020          <description>External master 0 buffer control</description>
10021          <addressOffset>0x700</addressOffset>
10022          <size>32</size>
10023          <access>read-write</access>
10024          <resetValue>0x40000000</resetValue>
10025          <resetMask>0x40000000</resetMask>
10026          <fields>
10027            <field>
10028              <name>PREF_EN</name>
10029              <description>See CRYPTO_BUFF_CTL.</description>
10030              <bitRange>[30:30]</bitRange>
10031              <access>read-write</access>
10032            </field>
10033          </fields>
10034        </register>
10035        <register>
10036          <name>EXT_MS1_BUFF_CTL</name>
10037          <description>External master 1 buffer control</description>
10038          <addressOffset>0x780</addressOffset>
10039          <size>32</size>
10040          <access>read-write</access>
10041          <resetValue>0x40000000</resetValue>
10042          <resetMask>0x40000000</resetMask>
10043          <fields>
10044            <field>
10045              <name>PREF_EN</name>
10046              <description>See CRYPTO_BUFF_CTL.</description>
10047              <bitRange>[30:30]</bitRange>
10048              <access>read-write</access>
10049            </field>
10050          </fields>
10051        </register>
10052        <cluster>
10053          <name>FM_CTL</name>
10054          <description>Flash Macro Registers</description>
10055          <addressOffset>0x0000F000</addressOffset>
10056          <register>
10057            <name>FM_CTL</name>
10058            <description>Flash macro control</description>
10059            <addressOffset>0x0</addressOffset>
10060            <size>32</size>
10061            <access>read-write</access>
10062            <resetValue>0x0</resetValue>
10063            <resetMask>0x37F030F</resetMask>
10064            <fields>
10065              <field>
10066                <name>FM_MODE</name>
10067                <description>Requires (IF_SEL|WR_EN)=1
10068Flash macro mode selection</description>
10069                <bitRange>[3:0]</bitRange>
10070                <access>read-write</access>
10071              </field>
10072              <field>
10073                <name>FM_SEQ</name>
10074                <description>Requires (IF_SEL|WR_EN)=1
10075Flash macro sequence selection</description>
10076                <bitRange>[9:8]</bitRange>
10077                <access>read-write</access>
10078              </field>
10079              <field>
10080                <name>DAA_MUX_SEL</name>
10081                <description>Direct memory cell access address.</description>
10082                <bitRange>[22:16]</bitRange>
10083                <access>read-write</access>
10084              </field>
10085              <field>
10086                <name>IF_SEL</name>
10087                <description>Interface selection. Specifies the interface that is used for flash memory read operations:
100880: R interface is used (default value). In this case, the flash memory address is provided as part of the R signal interface.
100891: C interface is used. In this case, the flash memory address is provided by FM_MEM_ADDR (the page address) and by the C interface access offset in the FM_MEM_DATA structure.
10090Note: IF_SEL and WR_EN cannot be changed at the same time</description>
10091                <bitRange>[24:24]</bitRange>
10092                <access>read-write</access>
10093              </field>
10094              <field>
10095                <name>WR_EN</name>
10096                <description>0: normal mode
100971: Fm Write Enable
10098Note: IF_SEL and WR_EN cannot be changed at the same time</description>
10099                <bitRange>[25:25]</bitRange>
10100                <access>read-write</access>
10101              </field>
10102            </fields>
10103          </register>
10104          <register>
10105            <name>STATUS</name>
10106            <description>Status</description>
10107            <addressOffset>0x4</addressOffset>
10108            <size>32</size>
10109            <access>read-only</access>
10110            <resetValue>0x1800</resetValue>
10111            <resetMask>0xFFFFFFFF</resetMask>
10112            <fields>
10113              <field>
10114                <name>TIMER_ENABLED</name>
10115                <description>This is the timer_en bit set by writing a '1' in the TIMER_CTL bit 31. It is reset by HW when the timer expires
101160: timer not running
101171: Timer is enabled and not expired yet</description>
10118                <bitRange>[0:0]</bitRange>
10119                <access>read-only</access>
10120              </field>
10121              <field>
10122                <name>HV_REGS_ISOLATED</name>
10123                <description>Indicates the isolation status at HV trim and redundancy registers inputs
101240: Not isolated, writing permitted
101251: isolated writing disabled</description>
10126                <bitRange>[1:1]</bitRange>
10127                <access>read-only</access>
10128              </field>
10129              <field>
10130                <name>ILLEGAL_HVOP</name>
10131                <description>Indicates a bulk, sector erase, program has been requested when axa=1
101320: no error
101331: illegal HV operation error</description>
10134                <bitRange>[2:2]</bitRange>
10135                <access>read-only</access>
10136              </field>
10137              <field>
10138                <name>TURBO_N</name>
10139                <description>After FM power up indicates the analog blocks currents are boosted to faster reach their functional state..
10140Used in the testchip boot only as an 'FM READY' flag.
101410: turbo mode
101421: normal mode</description>
10143                <bitRange>[3:3]</bitRange>
10144                <access>read-only</access>
10145              </field>
10146              <field>
10147                <name>WR_EN_MON</name>
10148                <description>FM_CTL.WR_EN bit after being synchronized in clk_r domain</description>
10149                <bitRange>[4:4]</bitRange>
10150                <access>read-only</access>
10151              </field>
10152              <field>
10153                <name>IF_SEL_MON</name>
10154                <description>FM_CTL.IF_SEL bit after being synchronized in clk_r domain</description>
10155                <bitRange>[5:5]</bitRange>
10156                <access>read-only</access>
10157              </field>
10158              <field>
10159                <name>TIMER_STATUS</name>
10160                <description>The actual timer state sync-ed in clk_c domain:
101610: timer is not running:
101621: timer is running;</description>
10163                <bitRange>[6:6]</bitRange>
10164                <access>read-only</access>
10165              </field>
10166              <field>
10167                <name>R_GRANT_DELAY_STATUS</name>
10168                <description>0: R_GRANT_DELAY timer is not running
101691: R_GRANT_DELAY timer is running</description>
10170                <bitRange>[7:7]</bitRange>
10171                <access>read-only</access>
10172              </field>
10173              <field>
10174                <name>FM_BUSY</name>
10175                <description>0': FM not busy
101761: FM BUSY : R_GRANT is 0 as result of a busy request from FM ready, or from HV operations.</description>
10177                <bitRange>[8:8]</bitRange>
10178                <access>read-only</access>
10179              </field>
10180              <field>
10181                <name>FM_READY</name>
10182                <description>0: FM not ready
101831: FM ready</description>
10184                <bitRange>[9:9]</bitRange>
10185                <access>read-only</access>
10186              </field>
10187              <field>
10188                <name>POS_PUMP_VLO</name>
10189                <description>POS pump VLO</description>
10190                <bitRange>[10:10]</bitRange>
10191                <access>read-only</access>
10192              </field>
10193              <field>
10194                <name>NEG_PUMP_VHI</name>
10195                <description>NEG pump VHI</description>
10196                <bitRange>[11:11]</bitRange>
10197                <access>read-only</access>
10198              </field>
10199              <field>
10200                <name>RWW</name>
10201                <description>FM Type  (Read While Write or Not Read While Write):
102020: Non RWW FM Type
102031:  RWW FM Type</description>
10204                <bitRange>[12:12]</bitRange>
10205                <access>read-only</access>
10206              </field>
10207              <field>
10208                <name>MAX_DOUT_WIDTH</name>
10209                <description>Internal memory core max data out size
10210(number of data out bits per column):
102110: x128 bits
102121: x256 bits</description>
10213                <bitRange>[13:13]</bitRange>
10214                <access>read-only</access>
10215              </field>
10216              <field>
10217                <name>SECTOR0_SR</name>
10218                <description>0:  Sector 0 does not contain special rows. The special rows are located in separate special sectors.
102191:  Sector 0 contains special rows</description>
10220                <bitRange>[14:14]</bitRange>
10221                <access>read-only</access>
10222              </field>
10223              <field>
10224                <name>RESET_MM</name>
10225                <description>Test_only, internal node: mpcon  reset_mm</description>
10226                <bitRange>[15:15]</bitRange>
10227                <access>read-only</access>
10228              </field>
10229              <field>
10230                <name>ROW_ODD</name>
10231                <description>Test_only, internal node: mpcon  row_odd</description>
10232                <bitRange>[16:16]</bitRange>
10233                <access>read-only</access>
10234              </field>
10235              <field>
10236                <name>ROW_EVEN</name>
10237                <description>Test_only, internal node: mpcon  row_even</description>
10238                <bitRange>[17:17]</bitRange>
10239                <access>read-only</access>
10240              </field>
10241              <field>
10242                <name>HVOP_SUB_SECTOR_N</name>
10243                <description>Test_only, internal node: mpcon  bk_subb</description>
10244                <bitRange>[18:18]</bitRange>
10245                <access>read-only</access>
10246              </field>
10247              <field>
10248                <name>HVOP_SECTOR</name>
10249                <description>Test_only, internal node: mpcon  bk_sec</description>
10250                <bitRange>[19:19]</bitRange>
10251                <access>read-only</access>
10252              </field>
10253              <field>
10254                <name>HVOP_BULK_ALL</name>
10255                <description>Test_only, internal node: mpcon  bk_all</description>
10256                <bitRange>[20:20]</bitRange>
10257                <access>read-only</access>
10258              </field>
10259              <field>
10260                <name>CBUS_RA_MATCH</name>
10261                <description>Test_only, internal node: mpcon  ra match</description>
10262                <bitRange>[21:21]</bitRange>
10263                <access>read-only</access>
10264              </field>
10265              <field>
10266                <name>CBUS_RED_ROW_EN</name>
10267                <description>Test_only, internal node: mpcon  red_row_en</description>
10268                <bitRange>[22:22]</bitRange>
10269                <access>read-only</access>
10270              </field>
10271              <field>
10272                <name>RQ_ERROR</name>
10273                <description>Test_only, internal node:  rq_error  sync-de in clk_c domain</description>
10274                <bitRange>[23:23]</bitRange>
10275                <access>read-only</access>
10276              </field>
10277              <field>
10278                <name>PUMP_PDAC</name>
10279                <description>Test_only, internal node: regif pdac outputs to pos pump</description>
10280                <bitRange>[27:24]</bitRange>
10281                <access>read-only</access>
10282              </field>
10283              <field>
10284                <name>PUMP_NDAC</name>
10285                <description>Test_only, internal node: regif ndac outputs to pos pump</description>
10286                <bitRange>[31:28]</bitRange>
10287                <access>read-only</access>
10288              </field>
10289            </fields>
10290          </register>
10291          <register>
10292            <name>FM_ADDR</name>
10293            <description>Flash macro address</description>
10294            <addressOffset>0x8</addressOffset>
10295            <size>32</size>
10296            <access>read-write</access>
10297            <resetValue>0x0</resetValue>
10298            <resetMask>0x1FFFFFF</resetMask>
10299            <fields>
10300              <field>
10301                <name>RA</name>
10302                <description>Row address.</description>
10303                <bitRange>[15:0]</bitRange>
10304                <access>read-write</access>
10305              </field>
10306              <field>
10307                <name>BA</name>
10308                <description>Bank address.</description>
10309                <bitRange>[23:16]</bitRange>
10310                <access>read-write</access>
10311              </field>
10312              <field>
10313                <name>AXA</name>
10314                <description>Auxiliary address field:
103150: regular flash memory.
103161: supervisory flash memory.</description>
10317                <bitRange>[24:24]</bitRange>
10318                <access>read-write</access>
10319              </field>
10320            </fields>
10321          </register>
10322          <register>
10323            <name>BOOKMARK</name>
10324            <description>Bookmark register - keeps the current FW HV seq</description>
10325            <addressOffset>0xC</addressOffset>
10326            <size>32</size>
10327            <access>read-write</access>
10328            <resetValue>0x0</resetValue>
10329            <resetMask>0xFFFFFFFF</resetMask>
10330            <fields>
10331              <field>
10332                <name>BOOKMARK</name>
10333                <description>Used by FW. Keeps the Current HV cycle sequence</description>
10334                <bitRange>[31:0]</bitRange>
10335                <access>read-write</access>
10336              </field>
10337            </fields>
10338          </register>
10339          <register>
10340            <name>GEOMETRY</name>
10341            <description>Regular flash geometry</description>
10342            <addressOffset>0x10</addressOffset>
10343            <size>32</size>
10344            <access>read-only</access>
10345            <resetValue>0x0</resetValue>
10346            <resetMask>0xFFFFFFFF</resetMask>
10347            <fields>
10348              <field>
10349                <name>ROW_COUNT</name>
10350                <description>Number of rows (minus 1):
103510: 1 row
103521: 2 rows
103532: 3 rows
10354...
10355'65535': 65536 rows</description>
10356                <bitRange>[15:0]</bitRange>
10357                <access>read-only</access>
10358              </field>
10359              <field>
10360                <name>BANK_COUNT</name>
10361                <description>Number of banks (minus 1):
103620: 1 bank
103631: 2 banks
10364...
10365'255': 256 banks</description>
10366                <bitRange>[23:16]</bitRange>
10367                <access>read-only</access>
10368              </field>
10369              <field>
10370                <name>WORD_SIZE_LOG2</name>
10371                <description>Number of Bytes per word (log 2). A word is defined as the data that is read from the flash macro over the R interface with a single read access:
103720: 1 Byte
103731: 2 Bytes
103742: 4 Bytes
10375...
103763: 128 Bytes
10377
10378The currently planned flash macros have a word size of either 32-bit, 64-bit or 128-bit, resulting in WORD_SIZE_LOG2 settings of 2, 3 and 4 respectively.</description>
10379                <bitRange>[27:24]</bitRange>
10380                <access>read-only</access>
10381              </field>
10382              <field>
10383                <name>PAGE_SIZE_LOG2</name>
10384                <description>Number of Bytes per page (log 2):
103850: 1 Byte
103861: 2 Bytes
103872: 4 Bytes
10388...
1038915: 32768 Bytes
10390
10391The currently planned flash macros have a page size of either 256 Byte or 512 Byte, resulting in PAGE_SIZE_LOG2 settings of 8 and 9 respectively.</description>
10392                <bitRange>[31:28]</bitRange>
10393                <access>read-only</access>
10394              </field>
10395            </fields>
10396          </register>
10397          <register>
10398            <name>GEOMETRY_SUPERVISORY</name>
10399            <description>Supervisory flash geometry</description>
10400            <addressOffset>0x14</addressOffset>
10401            <size>32</size>
10402            <access>read-only</access>
10403            <resetValue>0x0</resetValue>
10404            <resetMask>0xFFFFFFFF</resetMask>
10405            <fields>
10406              <field>
10407                <name>ROW_COUNT</name>
10408                <description>Number of rows (minus 1). ROW_COUNT is typically less than GEOMETRY.ROW_COUNT</description>
10409                <bitRange>[15:0]</bitRange>
10410                <access>read-only</access>
10411              </field>
10412              <field>
10413                <name>BANK_COUNT</name>
10414                <description>Number of banks (minus 1). BANK_COUNT is less or equal to GEOMETRY.BANK_COUNT.</description>
10415                <bitRange>[23:16]</bitRange>
10416                <access>read-only</access>
10417              </field>
10418              <field>
10419                <name>WORD_SIZE_LOG2</name>
10420                <description>Number of Bytes per word (log 2). See GEOMETRY.WORD_SIZE_LOG2. Typically, WORD_SIZE_LOG2 equals GEOMETRY.WORD_SIZE_LOG2.</description>
10421                <bitRange>[27:24]</bitRange>
10422                <access>read-only</access>
10423              </field>
10424              <field>
10425                <name>PAGE_SIZE_LOG2</name>
10426                <description>Number of Bytes per page (log 2). See GEOMETRY.PAGE_SIZE_LOG2. Typically, PAGE_SIZE_LOG2 equals GEOMETRY.PAGE_SIZE_LOG2.</description>
10427                <bitRange>[31:28]</bitRange>
10428                <access>read-only</access>
10429              </field>
10430            </fields>
10431          </register>
10432          <register>
10433            <name>ANA_CTL0</name>
10434            <description>Analog control 0</description>
10435            <addressOffset>0x18</addressOffset>
10436            <size>32</size>
10437            <access>read-write</access>
10438            <resetValue>0x400</resetValue>
10439            <resetMask>0xFFFFFFFF</resetMask>
10440            <fields>
10441              <field>
10442                <name>MDAC</name>
10443                <description>Trimming of the output margin Voltage as a function of Vpos and Vneg.</description>
10444                <bitRange>[7:0]</bitRange>
10445                <access>read-write</access>
10446              </field>
10447              <field>
10448                <name>CSLDAC</name>
10449                <description>Trimming of common source line DAC.</description>
10450                <bitRange>[10:8]</bitRange>
10451                <access>read-write</access>
10452              </field>
10453              <field>
10454                <name>FLIP_AMUXBUS_AB</name>
10455                <description>Flips amuxbusa and amuxbusb
104560: amuxbusa, amuxbusb
104571:  amuxbusb, amuxbusb</description>
10458                <bitRange>[11:11]</bitRange>
10459                <access>read-write</access>
10460              </field>
10461              <field>
10462                <name>NDAC_MIN</name>
10463                <description>NDAC staircase min value</description>
10464                <bitRange>[15:12]</bitRange>
10465                <access>read-write</access>
10466              </field>
10467              <field>
10468                <name>PDAC_MIN</name>
10469                <description>PDAC staircase min value</description>
10470                <bitRange>[19:16]</bitRange>
10471                <access>read-write</access>
10472              </field>
10473              <field>
10474                <name>SCALE_PRG_SEQ01</name>
10475                <description>PROG&amp;PRE_PROG: Scale for R_GRANT_DELAY on seq0-seq1 transition:
1047600: 0.125uS
1047701: 1uS
1047810: 10uS
1047911: 100uS</description>
10480                <bitRange>[21:20]</bitRange>
10481                <access>read-write</access>
10482              </field>
10483              <field>
10484                <name>SCALE_PRG_SEQ12</name>
10485                <description>PROG&amp;PRE_PROG: Scale for R_GRANT_DELAY on seq1-seq2 transition:
1048600: 0.125uS
1048701: 1uS
1048810: 10uS
1048911: 100uS</description>
10490                <bitRange>[23:22]</bitRange>
10491                <access>read-write</access>
10492              </field>
10493              <field>
10494                <name>SCALE_PRG_SEQ23</name>
10495                <description>PROG&amp;PRE_PROG: Scale for R_GRANT_DELAY on seq2-seq3 transition:
1049600: 0.125uS
1049701: 1uS
1049810: 10uS
1049911: 100uS</description>
10500                <bitRange>[25:24]</bitRange>
10501                <access>read-write</access>
10502              </field>
10503              <field>
10504                <name>SCALE_SEQ30</name>
10505                <description>PROG&amp;PRE_PROG&amp; ERASE: Scale for R_GRANT_DELAY on seq3-seq0 transition:
1050600: 0.125uS
1050701: 1uS
1050810: 10uS
1050911: 100uS</description>
10510                <bitRange>[27:26]</bitRange>
10511                <access>read-write</access>
10512              </field>
10513              <field>
10514                <name>SCALE_PRG_PEON</name>
10515                <description>PROG&amp;PRE_PROG: Scale for R_GRANT_DELAY on PE On transition:
1051600: 0.125uS
1051701: 1uS
1051810: 10uS
1051911: 100uS</description>
10520                <bitRange>[29:28]</bitRange>
10521                <access>read-write</access>
10522              </field>
10523              <field>
10524                <name>SCALE_PRG_PEOFF</name>
10525                <description>PROG&amp;PRE_PROG: Scale for R_GRANT_DELAY on PE OFF transition:
1052600: 0.125uS
1052701: 1uS
1052810: 10uS
1052911: 100uS</description>
10530                <bitRange>[31:30]</bitRange>
10531                <access>read-write</access>
10532              </field>
10533            </fields>
10534          </register>
10535          <register>
10536            <name>ANA_CTL1</name>
10537            <description>Analog control 1</description>
10538            <addressOffset>0x1C</addressOffset>
10539            <size>32</size>
10540            <access>read-write</access>
10541            <resetValue>0xD32FAFA</resetValue>
10542            <resetMask>0xFFFFFFFF</resetMask>
10543            <fields>
10544              <field>
10545                <name>NDAC_MAX</name>
10546                <description>Ndac Max Value.Trimming of negative pump output Voltage.</description>
10547                <bitRange>[3:0]</bitRange>
10548                <access>read-write</access>
10549              </field>
10550              <field>
10551                <name>NDAC_STEP</name>
10552                <description>Ndac step increment</description>
10553                <bitRange>[7:4]</bitRange>
10554                <access>read-write</access>
10555              </field>
10556              <field>
10557                <name>PDAC_MAX</name>
10558                <description>Pdac Max Value.Trimming of positive pump output Voltage:</description>
10559                <bitRange>[11:8]</bitRange>
10560                <access>read-write</access>
10561              </field>
10562              <field>
10563                <name>PDAC_STEP</name>
10564                <description>Pdac step increment</description>
10565                <bitRange>[15:12]</bitRange>
10566                <access>read-write</access>
10567              </field>
10568              <field>
10569                <name>NPDAC_STEP_TIME</name>
10570                <description>Ndac/Pdac step duration: (1uS .. 255uS) * 8
10571When = 0 N/PDAC_MAX control the pumps</description>
10572                <bitRange>[23:16]</bitRange>
10573                <access>read-write</access>
10574              </field>
10575              <field>
10576                <name>NPDAC_ZERO_TIME</name>
10577                <description>Ndac/Pdac LO duration: (1uS .. 255uS) * 8
10578When 0, N/PDAC don't return to 0</description>
10579                <bitRange>[31:24]</bitRange>
10580                <access>read-write</access>
10581              </field>
10582            </fields>
10583          </register>
10584          <register>
10585            <name>WAIT_CTL</name>
10586            <description>Wait State control</description>
10587            <addressOffset>0x28</addressOffset>
10588            <size>32</size>
10589            <access>read-write</access>
10590            <resetValue>0x30B09</resetValue>
10591            <resetMask>0x3F070F0F</resetMask>
10592            <fields>
10593              <field>
10594                <name>WAIT_FM_MEM_RD</name>
10595                <description>Number of C interface wait cycles (on 'clk_c') for a read from the memory</description>
10596                <bitRange>[3:0]</bitRange>
10597                <access>read-write</access>
10598              </field>
10599              <field>
10600                <name>WAIT_FM_HV_RD</name>
10601                <description>Number of C interface wait cycles (on 'clk_c') for a read from the high Voltage page latches.
10602Common for reading HV Page Latches and the DATA_COMP_RESULT bit</description>
10603                <bitRange>[11:8]</bitRange>
10604                <access>read-write</access>
10605              </field>
10606              <field>
10607                <name>WAIT_FM_HV_WR</name>
10608                <description>Number of C interface wait cycles (on 'clk_c') for a write to the high Voltage page latches.</description>
10609                <bitRange>[18:16]</bitRange>
10610                <access>read-write</access>
10611              </field>
10612              <field>
10613                <name>FM_RWW_MODE</name>
10614                <description>00: Full CBUS MODE
1061501: RWW
1061610: RWW. R_GRANT is stalling r_bus for the whole program/erase duration</description>
10617                <bitRange>[25:24]</bitRange>
10618                <access>read-write</access>
10619              </field>
10620              <field>
10621                <name>LV_SPARE_1</name>
10622                <description>Spare register</description>
10623                <bitRange>[26:26]</bitRange>
10624                <access>read-write</access>
10625              </field>
10626              <field>
10627                <name>DRMM</name>
10628                <description>0: Normal
106291: Test mode to enable Margin mode for 2 rows at a time</description>
10630                <bitRange>[27:27]</bitRange>
10631                <access>read-write</access>
10632              </field>
10633              <field>
10634                <name>MBA</name>
10635                <description>0: Normal
106361: Test mode to enable Master Bulk Access which allows both normal rows and redundant rows to be erased / programmed in one HV cycle (Bulk / Sector Erase and Sector Program).</description>
10637                <bitRange>[28:28]</bitRange>
10638                <access>read-write</access>
10639              </field>
10640              <field>
10641                <name>PL_SOFT_SET_EN</name>
10642                <description>Page latch soft set enable, 0 = disabled, 1 = enabled (at end of seq_2), taken care in API</description>
10643                <bitRange>[29:29]</bitRange>
10644                <access>read-write</access>
10645              </field>
10646            </fields>
10647          </register>
10648          <register>
10649            <name>TIMER_CLK_CTL</name>
10650            <description>Timer prescaler (clk_t to timer clock frequency divider)</description>
10651            <addressOffset>0x34</addressOffset>
10652            <size>32</size>
10653            <access>read-write</access>
10654            <resetValue>0x8</resetValue>
10655            <resetMask>0xFFFFFFFF</resetMask>
10656            <fields>
10657              <field>
10658                <name>TIMER_CLOCK_FREQ</name>
10659                <description>Clk_t frequency divider to provide the 1MHz reference clock for the Regif Timer.
10660Equal to the frequency in MHz of the timer clock 'clk_t'.
10661Example: if 'clk_t' has a frequency of 4 MHz then this field value is '4'
10662Max clk_t frequency = 100MHz.
10663This field is updated at runtime with the  'SW_TIMER_CLOCK_FREQ ' value from the HV parameters table</description>
10664                <bitRange>[7:0]</bitRange>
10665                <access>read-write</access>
10666              </field>
10667              <field>
10668                <name>RGRANT_DELAY_PRG_PEON</name>
10669                <description>PROG&amp;PRE_PROG: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON
10670When = 0  R_GRANT_DELAY control is disabled
10671when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
10672                <bitRange>[15:8]</bitRange>
10673                <access>read-write</access>
10674              </field>
10675              <field>
10676                <name>RGRANT_DELAY_PRG_PEOFF</name>
10677                <description>PROG&amp;PRE_PROG: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF
10678When = 0  R_GRANT_DELAY control is disabled
10679when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
10680                <bitRange>[23:16]</bitRange>
10681                <access>read-write</access>
10682              </field>
10683              <field>
10684                <name>RGRANT_DELAY_PRG_SEQ01</name>
10685                <description>PROG&amp;PRE_PROG: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01
10686When = 0  R_GRANT_DELAY control is disabled
10687when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
10688                <bitRange>[31:24]</bitRange>
10689                <access>read-write</access>
10690              </field>
10691            </fields>
10692          </register>
10693          <register>
10694            <name>TIMER_CTL</name>
10695            <description>Timer control</description>
10696            <addressOffset>0x38</addressOffset>
10697            <size>32</size>
10698            <access>read-write</access>
10699            <resetValue>0x4000001</resetValue>
10700            <resetMask>0xE700FFFF</resetMask>
10701            <fields>
10702              <field>
10703                <name>PERIOD</name>
10704                <description>Timer period in either microseconds (SCALE is '0') or 100's of microseconds (SCALE is '1') multiples.</description>
10705                <bitRange>[14:0]</bitRange>
10706                <access>read-write</access>
10707              </field>
10708              <field>
10709                <name>SCALE</name>
10710                <description>Timer tick scale:
107110: 1 microsecond.
107121: 100 microseconds.</description>
10713                <bitRange>[15:15]</bitRange>
10714                <access>read-write</access>
10715              </field>
10716              <field>
10717                <name>AUTO_SEQUENCE</name>
10718                <description>1': Starts1 the HV automatic sequencing
10719Cleared by HW</description>
10720                <bitRange>[24:24]</bitRange>
10721                <access>read-write</access>
10722              </field>
10723              <field>
10724                <name>PRE_PROG</name>
10725                <description>1 during pre-program operation</description>
10726                <bitRange>[25:25]</bitRange>
10727                <access>read-write</access>
10728              </field>
10729              <field>
10730                <name>PRE_PROG_CSL</name>
10731                <description>0: CSL lines driven by CSL_DAC
107321: CSL lines driven by VNEG_G</description>
10733                <bitRange>[26:26]</bitRange>
10734                <access>read-write</access>
10735              </field>
10736              <field>
10737                <name>PUMP_EN</name>
10738                <description>Pump enable:
107390: disabled
107401: enabled (also requires FM_CTL.IF_SEL to be'1', this additional restriction is required to prevent non intentional clearing of the FM).
10741SW sets this field to '1' to generate a single PE pulse.
10742HW clears this field when timer is expired.</description>
10743                <bitRange>[29:29]</bitRange>
10744                <access>read-write</access>
10745              </field>
10746              <field>
10747                <name>ACLK_EN</name>
10748                <description>ACLK enable (generates a single cycle pulse for the FM):
107490: disabled
107501: enabled. SW set this field to '1' to generate a single cycle pulse. HW sets this field to '0' when the pulse is generated.</description>
10751                <bitRange>[30:30]</bitRange>
10752                <access>read-write</access>
10753              </field>
10754              <field>
10755                <name>TIMER_EN</name>
10756                <description>Timer enable:
107570: disabled
107581: enabled. SW sets this field to '1' to start the timer. HW sets this field to '0' when the timer is expired.</description>
10759                <bitRange>[31:31]</bitRange>
10760                <access>read-write</access>
10761              </field>
10762            </fields>
10763          </register>
10764          <register>
10765            <name>ACLK_CTL</name>
10766            <description>MPCON clock</description>
10767            <addressOffset>0x3C</addressOffset>
10768            <size>32</size>
10769            <access>write-only</access>
10770            <resetValue>0x0</resetValue>
10771            <resetMask>0x1</resetMask>
10772            <fields>
10773              <field>
10774                <name>ACLK_GEN</name>
10775                <description>A write to this register generates the clock pulse for HV control registers (mpcon outputs)</description>
10776                <bitRange>[0:0]</bitRange>
10777                <access>write-only</access>
10778              </field>
10779            </fields>
10780          </register>
10781          <register>
10782            <name>INTR</name>
10783            <description>Interrupt</description>
10784            <addressOffset>0x40</addressOffset>
10785            <size>32</size>
10786            <access>read-write</access>
10787            <resetValue>0x0</resetValue>
10788            <resetMask>0x1</resetMask>
10789            <fields>
10790              <field>
10791                <name>TIMER_EXPIRED</name>
10792                <description>Set to '1', when event is detected. Write INTR field with '1', to clear bit. Write INTR_SET field with '1', to set bit.</description>
10793                <bitRange>[0:0]</bitRange>
10794                <access>read-write</access>
10795              </field>
10796            </fields>
10797          </register>
10798          <register>
10799            <name>INTR_SET</name>
10800            <description>Interrupt set</description>
10801            <addressOffset>0x44</addressOffset>
10802            <size>32</size>
10803            <access>read-write</access>
10804            <resetValue>0x0</resetValue>
10805            <resetMask>0x1</resetMask>
10806            <fields>
10807              <field>
10808                <name>TIMER_EXPIRED</name>
10809                <description>Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect).</description>
10810                <bitRange>[0:0]</bitRange>
10811                <access>read-write</access>
10812              </field>
10813            </fields>
10814          </register>
10815          <register>
10816            <name>INTR_MASK</name>
10817            <description>Interrupt mask</description>
10818            <addressOffset>0x48</addressOffset>
10819            <size>32</size>
10820            <access>read-write</access>
10821            <resetValue>0x0</resetValue>
10822            <resetMask>0x1</resetMask>
10823            <fields>
10824              <field>
10825                <name>TIMER_EXPIRED</name>
10826                <description>Mask for corresponding field in INTR register.</description>
10827                <bitRange>[0:0]</bitRange>
10828                <access>read-write</access>
10829              </field>
10830            </fields>
10831          </register>
10832          <register>
10833            <name>INTR_MASKED</name>
10834            <description>Interrupt masked</description>
10835            <addressOffset>0x4C</addressOffset>
10836            <size>32</size>
10837            <access>read-only</access>
10838            <resetValue>0x0</resetValue>
10839            <resetMask>0x1</resetMask>
10840            <fields>
10841              <field>
10842                <name>TIMER_EXPIRED</name>
10843                <description>Logical and of corresponding request and mask fields.</description>
10844                <bitRange>[0:0]</bitRange>
10845                <access>read-only</access>
10846              </field>
10847            </fields>
10848          </register>
10849          <register>
10850            <name>CAL_CTL0</name>
10851            <description>Cal control BG LO trim bits</description>
10852            <addressOffset>0x50</addressOffset>
10853            <size>32</size>
10854            <access>read-write</access>
10855            <resetValue>0x38F8F</resetValue>
10856            <resetMask>0xFFFFF</resetMask>
10857            <fields>
10858              <field>
10859                <name>VCT_TRIM_LO_HV</name>
10860                <description>LO Bandgap Voltage Temperature Compensation trim control.</description>
10861                <bitRange>[4:0]</bitRange>
10862                <access>read-write</access>
10863              </field>
10864              <field>
10865                <name>CDAC_LO_HV</name>
10866                <description>LO Temperature compensated trim DAC. To control Vcstat slope for Vpos.</description>
10867                <bitRange>[7:5]</bitRange>
10868                <access>read-write</access>
10869              </field>
10870              <field>
10871                <name>VBG_TRIM_LO_HV</name>
10872                <description>LO Bandgap Voltage trim control.</description>
10873                <bitRange>[12:8]</bitRange>
10874                <access>read-write</access>
10875              </field>
10876              <field>
10877                <name>VBG_TC_TRIM_LO_HV</name>
10878                <description>LO Bandgap Voltage Temperature Compensation trim control</description>
10879                <bitRange>[15:13]</bitRange>
10880                <access>read-write</access>
10881              </field>
10882              <field>
10883                <name>ICREF_TC_TRIM_LO_HV</name>
10884                <description>LO Bandgap Current Temperature Compensation trim control</description>
10885                <bitRange>[18:16]</bitRange>
10886                <access>read-write</access>
10887              </field>
10888              <field>
10889                <name>IPREF_TRIMA_LO_HV</name>
10890                <description>Adds 100-150nA boost on IPREF_LO</description>
10891                <bitRange>[19:19]</bitRange>
10892                <access>read-write</access>
10893              </field>
10894            </fields>
10895          </register>
10896          <register>
10897            <name>CAL_CTL1</name>
10898            <description>Cal control BG HI trim bits</description>
10899            <addressOffset>0x54</addressOffset>
10900            <size>32</size>
10901            <access>read-write</access>
10902            <resetValue>0x38F8F</resetValue>
10903            <resetMask>0xFFFFF</resetMask>
10904            <fields>
10905              <field>
10906                <name>VCT_TRIM_HI_HV</name>
10907                <description>HI Bandgap Voltage Temperature Compensation trim control.</description>
10908                <bitRange>[4:0]</bitRange>
10909                <access>read-write</access>
10910              </field>
10911              <field>
10912                <name>CDAC_HI_HV</name>
10913                <description>HI Temperature compensated trim DAC. To control Vcstat slope for Vpos.</description>
10914                <bitRange>[7:5]</bitRange>
10915                <access>read-write</access>
10916              </field>
10917              <field>
10918                <name>VBG_TRIM_HI_HV</name>
10919                <description>HI Bandgap Voltage trim control.</description>
10920                <bitRange>[12:8]</bitRange>
10921                <access>read-write</access>
10922              </field>
10923              <field>
10924                <name>VBG_TC_TRIM_HI_HV</name>
10925                <description>HI Bandgap Voltage Temperature Compensation trim control.</description>
10926                <bitRange>[15:13]</bitRange>
10927                <access>read-write</access>
10928              </field>
10929              <field>
10930                <name>ICREF_TC_TRIM_HI_HV</name>
10931                <description>HI Bandgap Current Temperature Compensation trim control.</description>
10932                <bitRange>[18:16]</bitRange>
10933                <access>read-write</access>
10934              </field>
10935              <field>
10936                <name>IPREF_TRIMA_HI_HV</name>
10937                <description>Adds 100-150nA boost on IPREF_HI</description>
10938                <bitRange>[19:19]</bitRange>
10939                <access>read-write</access>
10940              </field>
10941            </fields>
10942          </register>
10943          <register>
10944            <name>CAL_CTL2</name>
10945            <description>Cal control BG LO&amp;HI trim bits</description>
10946            <addressOffset>0x58</addressOffset>
10947            <size>32</size>
10948            <access>read-write</access>
10949            <resetValue>0x7BE10</resetValue>
10950            <resetMask>0xFFFFF</resetMask>
10951            <fields>
10952              <field>
10953                <name>ICREF_TRIM_LO_HV</name>
10954                <description>LO Bandgap Current  trim control.</description>
10955                <bitRange>[4:0]</bitRange>
10956                <access>read-write</access>
10957              </field>
10958              <field>
10959                <name>ICREF_TRIM_HI_HV</name>
10960                <description>HI Bandgap Current  trim control.</description>
10961                <bitRange>[9:5]</bitRange>
10962                <access>read-write</access>
10963              </field>
10964              <field>
10965                <name>IPREF_TRIM_LO_HV</name>
10966                <description>LO Bandgap IPTAT trim control.</description>
10967                <bitRange>[14:10]</bitRange>
10968                <access>read-write</access>
10969              </field>
10970              <field>
10971                <name>IPREF_TRIM_HI_HV</name>
10972                <description>HI  Bandgap IPTAT trim control.</description>
10973                <bitRange>[19:15]</bitRange>
10974                <access>read-write</access>
10975              </field>
10976            </fields>
10977          </register>
10978          <register>
10979            <name>CAL_CTL3</name>
10980            <description>Cal control osc trim bits, idac, sdac, itim</description>
10981            <addressOffset>0x5C</addressOffset>
10982            <size>32</size>
10983            <access>read-write</access>
10984            <resetValue>0x2004</resetValue>
10985            <resetMask>0xFFFFF</resetMask>
10986            <fields>
10987              <field>
10988                <name>OSC_TRIM_HV</name>
10989                <description>Flash macro pump clock trim control.</description>
10990                <bitRange>[3:0]</bitRange>
10991                <access>read-write</access>
10992              </field>
10993              <field>
10994                <name>OSC_RANGE_TRIM_HV</name>
10995                <description>0: Oscillator High Frequency Range
109961: Oscillator Low Frequency range</description>
10997                <bitRange>[4:4]</bitRange>
10998                <access>read-write</access>
10999              </field>
11000              <field>
11001                <name>VPROT_ACT_HV</name>
11002                <description>Forces VPROT in active mode all the time</description>
11003                <bitRange>[5:5]</bitRange>
11004                <access>read-write</access>
11005              </field>
11006              <field>
11007                <name>IPREF_TC_HV</name>
11008                <description>0: Increases the IPREF Tempco by subtracting ICREF from IPREF - IPREF internal will be 0.5uA
110091: Reduces the IPREF Tempco without subtracting ICREF from IPREF - IPREF internal will be 1uA</description>
11010                <bitRange>[6:6]</bitRange>
11011                <access>read-write</access>
11012              </field>
11013              <field>
11014                <name>VREF_SEL_HV</name>
11015                <description>Voltage reference:
110160: internal bandgap reference
110171: external voltage reference</description>
11018                <bitRange>[7:7]</bitRange>
11019                <access>read-write</access>
11020              </field>
11021              <field>
11022                <name>IREF_SEL_HV</name>
11023                <description>Current reference:
110240: internal current reference
110251: external current reference</description>
11026                <bitRange>[8:8]</bitRange>
11027                <access>read-write</access>
11028              </field>
11029              <field>
11030                <name>REG_ACT_HV</name>
11031                <description>0: VBST regulator will operate in active/standby mode based on control signal.
110321: Forces the VBST regulator in active mode all the time</description>
11033                <bitRange>[9:9]</bitRange>
11034                <access>read-write</access>
11035              </field>
11036              <field>
11037                <name>FDIV_TRIM_HV</name>
11038                <description>FDIV_TRIM_HV[1:0]: Assuming oscillator frequency of 8MHz in standby.
11039Following are the clock frequencies seen by doubler
1104000: F = 1MHz
1104101: F = 0.5MHz
1104210: F = 2MHz
1104311: F = 4MHz</description>
11044                <bitRange>[11:10]</bitRange>
11045                <access>read-write</access>
11046              </field>
11047              <field>
11048                <name>VDDHI_HV</name>
11049                <description>0: vdd &lt; 2.3V
110501: vdd &gt;= 2.3V
11051'0' setting can used for vdd &gt; 2.3V also, but with a current penalty.</description>
11052                <bitRange>[12:12]</bitRange>
11053                <access>read-write</access>
11054              </field>
11055              <field>
11056                <name>TURBO_PULSEW_HV</name>
11057                <description>Turbo pulse width trim (Typical)
1105800: 40 us
1105901: 20 us
1106010: 15 us
1106111: 8 us</description>
11062                <bitRange>[14:13]</bitRange>
11063                <access>read-write</access>
11064              </field>
11065              <field>
11066                <name>BGLO_EN_HV</name>
11067                <description>0: Normal (Automatic change over from HI to LO)
110681: Force enable LO Bandgap</description>
11069                <bitRange>[15:15]</bitRange>
11070                <access>read-write</access>
11071              </field>
11072              <field>
11073                <name>BGHI_EN_HV</name>
11074                <description>0: Normal (Automatic change over from HI to LO)
110751: Force enable HI Bandgap
11076When both BGLO_EN_HV and BGHI_EN_HV are HIGH, only BGHI output is used and turbo_hv_n pulse is active</description>
11077                <bitRange>[16:16]</bitRange>
11078                <access>read-write</access>
11079              </field>
11080              <field>
11081                <name>CL_ISO_DIS_HV</name>
11082                <description>0: The internal logic controls the CL isolation
110831: Forces CL bypass</description>
11084                <bitRange>[17:17]</bitRange>
11085                <access>read-write</access>
11086              </field>
11087              <field>
11088                <name>R_GRANT_EN_HV</name>
11089                <description>0: r_grant handshake disabled, r_grant always 1.
110901: r_grand handshake  enabled</description>
11091                <bitRange>[18:18]</bitRange>
11092                <access>read-write</access>
11093              </field>
11094              <field>
11095                <name>LP_ULP_SW_HV</name>
11096                <description>LP&lt;--&gt;ULP switch for trim signals:
110970: LP
110981: ULP</description>
11099                <bitRange>[19:19]</bitRange>
11100                <access>read-write</access>
11101              </field>
11102            </fields>
11103          </register>
11104          <register>
11105            <name>CAL_CTL4</name>
11106            <description>Cal Control Vlim, SA, fdiv, reg_act</description>
11107            <addressOffset>0x60</addressOffset>
11108            <size>32</size>
11109            <access>read-write</access>
11110            <resetValue>0x12AE0</resetValue>
11111            <resetMask>0xFFFFF</resetMask>
11112            <fields>
11113              <field>
11114                <name>VLIM_TRIM_ULP_HV</name>
11115                <description>VLIM_TRIM[1:0]:
1111600: V2 = 650mV
1111701: V2 = 600mV
1111810: V2 = 750mV
1111911: V2 = 700mV</description>
11120                <bitRange>[1:0]</bitRange>
11121                <access>read-write</access>
11122              </field>
11123              <field>
11124                <name>IDAC_ULP_HV</name>
11125                <description>Sets the sense current reference offset value. Refer to trim tables for details.</description>
11126                <bitRange>[5:2]</bitRange>
11127                <access>read-write</access>
11128              </field>
11129              <field>
11130                <name>SDAC_ULP_HV</name>
11131                <description>Sets the sense current reference temp slope. Refer to trim tables for details.</description>
11132                <bitRange>[7:6]</bitRange>
11133                <access>read-write</access>
11134              </field>
11135              <field>
11136                <name>ITIM_ULP_HV</name>
11137                <description>Trimming of timing current</description>
11138                <bitRange>[12:8]</bitRange>
11139                <access>read-write</access>
11140              </field>
11141              <field>
11142                <name>FM_READY_DEL_ULP_HV</name>
11143                <description>00: Default : delay 1ns
1114401: Delayed by 1.5us
1114510: Delayed by 2.0us
1114611: Delayed by 2.5us</description>
11147                <bitRange>[14:13]</bitRange>
11148                <access>read-write</access>
11149              </field>
11150              <field>
11151                <name>SPARE451_ULP_HV</name>
11152                <description>N/A</description>
11153                <bitRange>[15:15]</bitRange>
11154                <access>read-write</access>
11155              </field>
11156              <field>
11157                <name>READY_RESTART_N_HV</name>
11158                <description>Toggle: 1--&gt;0, ready goes low, ready will remain low as long as the bit is low. Toggle the bit back to 1 to activate the ready logic. To be used by API only.</description>
11159                <bitRange>[16:16]</bitRange>
11160                <access>read-write</access>
11161              </field>
11162              <field>
11163                <name>VBST_S_DIS_HV</name>
11164                <description>0: VBST_S voltage for each sector to allow VBST level to be dropped to VCC during Erase in the selected sector, reducing coupling to GBL.
111651: VBST_S voltage for each sector stays at VBST level during Erase in the selected sector.</description>
11166                <bitRange>[17:17]</bitRange>
11167                <access>read-write</access>
11168              </field>
11169              <field>
11170                <name>AUTO_HVPULSE_HV</name>
11171                <description>0: HV Pulse controlled by FW
111721: HV Pulse controlled by Hardware</description>
11173                <bitRange>[18:18]</bitRange>
11174                <access>read-write</access>
11175              </field>
11176              <field>
11177                <name>UGB_EN_HV</name>
11178                <description>UGB enable in TM control</description>
11179                <bitRange>[19:19]</bitRange>
11180                <access>read-write</access>
11181              </field>
11182            </fields>
11183          </register>
11184          <register>
11185            <name>CAL_CTL5</name>
11186            <description>Cal control</description>
11187            <addressOffset>0x64</addressOffset>
11188            <size>32</size>
11189            <access>read-write</access>
11190            <resetValue>0x2AE0</resetValue>
11191            <resetMask>0xFFFFF</resetMask>
11192            <fields>
11193              <field>
11194                <name>VLIM_TRIM_LP_HV</name>
11195                <description>VLIM_TRIM[1:0]:
1119600: V2 = 650mV
1119701: V2 = 600mV
1119810: V2 = 750mV
1119911: V2 = 700mV</description>
11200                <bitRange>[1:0]</bitRange>
11201                <access>read-write</access>
11202              </field>
11203              <field>
11204                <name>IDAC_LP_HV</name>
11205                <description>Sets the sense current reference offset value. Refer to trim tables for details.</description>
11206                <bitRange>[5:2]</bitRange>
11207                <access>read-write</access>
11208              </field>
11209              <field>
11210                <name>SDAC_LP_HV</name>
11211                <description>Sets the sense current reference temp slope. Refer to trim tables for details.</description>
11212                <bitRange>[7:6]</bitRange>
11213                <access>read-write</access>
11214              </field>
11215              <field>
11216                <name>ITIM_LP_HV</name>
11217                <description>Trimming of timing current</description>
11218                <bitRange>[12:8]</bitRange>
11219                <access>read-write</access>
11220              </field>
11221              <field>
11222                <name>FM_READY_DEL_LP_HV</name>
11223                <description>00: Delayed by 1us
1122401: Delayed by 1.5us
1122510: Delayed by 2.0us
1122611: Delayed by 2.5us</description>
11227                <bitRange>[14:13]</bitRange>
11228                <access>read-write</access>
11229              </field>
11230              <field>
11231                <name>SPARE451_LP_HV</name>
11232                <description>N/A</description>
11233                <bitRange>[15:15]</bitRange>
11234                <access>read-write</access>
11235              </field>
11236              <field>
11237                <name>SPARE52_HV</name>
11238                <description>N/A</description>
11239                <bitRange>[17:16]</bitRange>
11240                <access>read-write</access>
11241              </field>
11242              <field>
11243                <name>AMUX_SEL_HV</name>
11244                <description>Amux Select in AMUX_UGB
1124500: Bypass UGB for both amuxbusa and amuxbusb
1124601: Bypass UGB for amuxbusb while passing amuxbusa through UGB.
1124710: Bypass UGB for amuxbusa while passing amuxbusb through UGB.
1124811: UGB Calibrate mode</description>
11249                <bitRange>[19:18]</bitRange>
11250                <access>read-write</access>
11251              </field>
11252            </fields>
11253          </register>
11254          <register>
11255            <name>CAL_CTL6</name>
11256            <description>SA trim LP/ULP</description>
11257            <addressOffset>0x68</addressOffset>
11258            <size>32</size>
11259            <access>read-write</access>
11260            <resetValue>0x36F7F</resetValue>
11261            <resetMask>0xFFFFF</resetMask>
11262            <fields>
11263              <field>
11264                <name>SA_CTL_TRIM_T1_ULP_HV</name>
11265                <description>clk_trk delay</description>
11266                <bitRange>[0:0]</bitRange>
11267                <access>read-write</access>
11268              </field>
11269              <field>
11270                <name>SA_CTL_TRIM_T4_ULP_HV</name>
11271                <description>SA_CTL_TRIM_T4_ULP_HV&lt;2&gt;= eqi (eq current trim)
11272SA_CTL_TRIM_T4_ULP_HV&lt;1:0&gt; = eqc (eq cap trim)</description>
11273                <bitRange>[3:1]</bitRange>
11274                <access>read-write</access>
11275              </field>
11276              <field>
11277                <name>SA_CTL_TRIM_T5_ULP_HV</name>
11278                <description>SA_CTL_TRIM_T5_ULP_HV&lt;2&gt;= evi (integration current trim)
11279SA_CTL_TRIM_T5_ULP_HV&lt;1:0&gt; = evc (integration cap trim)</description>
11280                <bitRange>[6:4]</bitRange>
11281                <access>read-write</access>
11282              </field>
11283              <field>
11284                <name>SA_CTL_TRIM_T6_ULP_HV</name>
11285                <description>SA_CTL_TRIM_T6_ULP_HV&lt;1&gt;= eni (enable current trim)
11286SA_CTL_TRIM_T6_ULP_HV&lt;0&gt; = ecn (enable cap trim)</description>
11287                <bitRange>[8:7]</bitRange>
11288                <access>read-write</access>
11289              </field>
11290              <field>
11291                <name>SA_CTL_TRIM_T8_ULP_HV</name>
11292                <description>saen3 pulse width trim (Current trim)</description>
11293                <bitRange>[9:9]</bitRange>
11294                <access>read-write</access>
11295              </field>
11296              <field>
11297                <name>SA_CTL_TRIM_T1_LP_HV</name>
11298                <description>clk_trk delay</description>
11299                <bitRange>[10:10]</bitRange>
11300                <access>read-write</access>
11301              </field>
11302              <field>
11303                <name>SA_CTL_TRIM_T4_LP_HV</name>
11304                <description>SA_CTL_TRIM_T4_LP_HV&lt;2&gt;= eqi (eq current trim)
11305SA_CTL_TRIM_T4_LP_HV&lt;1:0&gt; = eqc (eq cap trim)</description>
11306                <bitRange>[13:11]</bitRange>
11307                <access>read-write</access>
11308              </field>
11309              <field>
11310                <name>SA_CTL_TRIM_T5_LP_HV</name>
11311                <description>SA_CTL_TRIM_T5_LP_HV&lt;2&gt;= evi (integration current trim)
11312SA_CTL_TRIM_T5_LP_HV&lt;1:0&gt; = evc (integration cap trim)</description>
11313                <bitRange>[16:14]</bitRange>
11314                <access>read-write</access>
11315              </field>
11316              <field>
11317                <name>SA_CTL_TRIM_T6_LP_HV</name>
11318                <description>SA_CTL_TRIM_T6_LP_HV&lt;1&gt;= eni (enable current trim)
11319SA_CTL_TRIM_T6_LP_HV&lt;0&gt; = ecn (enable cap trim)</description>
11320                <bitRange>[18:17]</bitRange>
11321                <access>read-write</access>
11322              </field>
11323              <field>
11324                <name>SA_CTL_TRIM_T8_LP_HV</name>
11325                <description>saen3 pulse width trim (Current trim)</description>
11326                <bitRange>[19:19]</bitRange>
11327                <access>read-write</access>
11328              </field>
11329            </fields>
11330          </register>
11331          <register>
11332            <name>CAL_CTL7</name>
11333            <description>Cal control</description>
11334            <addressOffset>0x6C</addressOffset>
11335            <size>32</size>
11336            <access>read-write</access>
11337            <resetValue>0x0</resetValue>
11338            <resetMask>0xFFFFF</resetMask>
11339            <fields>
11340              <field>
11341                <name>ERSX8_CLK_SEL_HV</name>
11342                <description>Clock frequency into the ersx8 shift register block
1134300: Oscillator clock
1134401: Oscillator clock / 2
1134510: Oscillator clock / 4
1134611: Oscillator clock</description>
11347                <bitRange>[1:0]</bitRange>
11348                <access>read-write</access>
11349              </field>
11350              <field>
11351                <name>FM_ACTIVE_HV</name>
11352                <description>0: Normal operation
113531: Forces FM SYS in active mode</description>
11354                <bitRange>[2:2]</bitRange>
11355                <access>read-write</access>
11356              </field>
11357              <field>
11358                <name>TURBO_EXT_HV</name>
11359                <description>0: Normal operation
113601: Uses external turbo pulse</description>
11361                <bitRange>[3:3]</bitRange>
11362                <access>read-write</access>
11363              </field>
11364              <field>
11365                <name>NPDAC_HWCTL_DIS_HV</name>
11366                <description>0': ndac, pdac staircase hardware controlled
113671: ndac, pdac staircase disabled. Enables FW control.</description>
11368                <bitRange>[4:4]</bitRange>
11369                <access>read-write</access>
11370              </field>
11371              <field>
11372                <name>FM_READY_DIS_HV</name>
11373                <description>0': fm ready is enabled
113741: fm ready is disabled (fm_ready is always '1')</description>
11375                <bitRange>[5:5]</bitRange>
11376                <access>read-write</access>
11377              </field>
11378              <field>
11379                <name>ERSX8_EN_ALL_HV</name>
11380                <description>0': Staggered turn on/off of GWL
113811: GWL are turned on/off at the same time (old FM legacy)</description>
11382                <bitRange>[6:6]</bitRange>
11383                <access>read-write</access>
11384              </field>
11385              <field>
11386                <name>DISABLE_LOAD_ONCE_HV</name>
11387                <description>0: Load common HV params during API HV operations depends on the HV_PARAMS_LOADED bit in RGRANT_DELAY_PRG register.
113881: All HV params are loaded during every API HV operation irrespective of HV_PARAMS_LOADED bit in the RGRANT_DELAY_PRG register.</description>
11389                <bitRange>[7:7]</bitRange>
11390                <access>read-write</access>
11391              </field>
11392              <field>
11393                <name>SPARE7_HV</name>
11394                <description>N/A</description>
11395                <bitRange>[9:8]</bitRange>
11396                <access>read-write</access>
11397              </field>
11398              <field>
11399                <name>SPARE7_ULP_HV</name>
11400                <description>N/A</description>
11401                <bitRange>[14:10]</bitRange>
11402                <access>read-write</access>
11403              </field>
11404              <field>
11405                <name>SPARE7_LP_HV</name>
11406                <description>N/A</description>
11407                <bitRange>[19:15]</bitRange>
11408                <access>read-write</access>
11409              </field>
11410            </fields>
11411          </register>
11412          <register>
11413            <name>RED_CTL01</name>
11414            <description>Redundancy Control normal sectors 0,1</description>
11415            <addressOffset>0x80</addressOffset>
11416            <size>32</size>
11417            <access>read-write</access>
11418            <resetValue>0x0</resetValue>
11419            <resetMask>0x1FF01FF</resetMask>
11420            <fields>
11421              <field>
11422                <name>RED_ADDR_0</name>
11423                <description>Bad Row Pair Address for Sector 0</description>
11424                <bitRange>[7:0]</bitRange>
11425                <access>read-write</access>
11426              </field>
11427              <field>
11428                <name>RED_EN_0</name>
11429                <description>1: Redundancy Enable for Sector 0</description>
11430                <bitRange>[8:8]</bitRange>
11431                <access>read-write</access>
11432              </field>
11433              <field>
11434                <name>RED_ADDR_1</name>
11435                <description>Bad Row Pair Address for Sector 1</description>
11436                <bitRange>[23:16]</bitRange>
11437                <access>read-write</access>
11438              </field>
11439              <field>
11440                <name>RED_EN_1</name>
11441                <description>1: Redundancy Enable for Sector 1</description>
11442                <bitRange>[24:24]</bitRange>
11443                <access>read-write</access>
11444              </field>
11445            </fields>
11446          </register>
11447          <register>
11448            <name>RED_CTL23</name>
11449            <description>Redundancy Control normal sectors 2,3</description>
11450            <addressOffset>0x84</addressOffset>
11451            <size>32</size>
11452            <access>read-write</access>
11453            <resetValue>0x0</resetValue>
11454            <resetMask>0x1FF01FF</resetMask>
11455            <fields>
11456              <field>
11457                <name>RED_ADDR_2</name>
11458                <description>Bad Row Pair Address for Sector 2</description>
11459                <bitRange>[7:0]</bitRange>
11460                <access>read-write</access>
11461              </field>
11462              <field>
11463                <name>RED_EN_2</name>
11464                <description>1: Redundancy Enable for Sector 2</description>
11465                <bitRange>[8:8]</bitRange>
11466                <access>read-write</access>
11467              </field>
11468              <field>
11469                <name>RED_ADDR_3</name>
11470                <description>Bad Row Pair Address for Sector 3</description>
11471                <bitRange>[23:16]</bitRange>
11472                <access>read-write</access>
11473              </field>
11474              <field>
11475                <name>RED_EN_3</name>
11476                <description>1: Redundancy Enable for Sector 3</description>
11477                <bitRange>[24:24]</bitRange>
11478                <access>read-write</access>
11479              </field>
11480            </fields>
11481          </register>
11482          <register>
11483            <name>RED_CTL45</name>
11484            <description>Redundancy Control normal sectors 4,5</description>
11485            <addressOffset>0x88</addressOffset>
11486            <size>32</size>
11487            <access>read-write</access>
11488            <resetValue>0x0</resetValue>
11489            <resetMask>0x1FF01FF</resetMask>
11490            <fields>
11491              <field>
11492                <name>RED_ADDR_4</name>
11493                <description>Bad Row Pair Address for Sector 4</description>
11494                <bitRange>[7:0]</bitRange>
11495                <access>read-write</access>
11496              </field>
11497              <field>
11498                <name>RED_EN_4</name>
11499                <description>1: Redundancy Enable for Sector 4</description>
11500                <bitRange>[8:8]</bitRange>
11501                <access>read-write</access>
11502              </field>
11503              <field>
11504                <name>RED_ADDR_5</name>
11505                <description>Bad Row Pair Address for Sector 5</description>
11506                <bitRange>[23:16]</bitRange>
11507                <access>read-write</access>
11508              </field>
11509              <field>
11510                <name>RED_EN_5</name>
11511                <description>1: Redundancy Enable for Sector 5</description>
11512                <bitRange>[24:24]</bitRange>
11513                <access>read-write</access>
11514              </field>
11515            </fields>
11516          </register>
11517          <register>
11518            <name>RED_CTL67</name>
11519            <description>Redundancy Control normal sectors 6,7</description>
11520            <addressOffset>0x8C</addressOffset>
11521            <size>32</size>
11522            <access>read-write</access>
11523            <resetValue>0x0</resetValue>
11524            <resetMask>0x1FF01FF</resetMask>
11525            <fields>
11526              <field>
11527                <name>RED_ADDR_6</name>
11528                <description>Bad Row Pair Address for Sector 6</description>
11529                <bitRange>[7:0]</bitRange>
11530                <access>read-write</access>
11531              </field>
11532              <field>
11533                <name>RED_EN_6</name>
11534                <description>1: Redundancy Enable for Sector 6</description>
11535                <bitRange>[8:8]</bitRange>
11536                <access>read-write</access>
11537              </field>
11538              <field>
11539                <name>RED_ADDR_7</name>
11540                <description>Bad Row Pair Address for Sector 7</description>
11541                <bitRange>[23:16]</bitRange>
11542                <access>read-write</access>
11543              </field>
11544              <field>
11545                <name>RED_EN_7</name>
11546                <description>1: Redundancy Enable for Sector 7</description>
11547                <bitRange>[24:24]</bitRange>
11548                <access>read-write</access>
11549              </field>
11550            </fields>
11551          </register>
11552          <register>
11553            <name>RED_CTL_SM01</name>
11554            <description>Redundancy Control special sectors 0,1</description>
11555            <addressOffset>0x90</addressOffset>
11556            <size>32</size>
11557            <access>read-write</access>
11558            <resetValue>0x0</resetValue>
11559            <resetMask>0x1FF01FF</resetMask>
11560            <fields>
11561              <field>
11562                <name>RED_ADDR_SM0</name>
11563                <description>Bad Row Pair Address for Special Sector 0</description>
11564                <bitRange>[7:0]</bitRange>
11565                <access>read-write</access>
11566              </field>
11567              <field>
11568                <name>RED_EN_SM0</name>
11569                <description>Redundancy Enable for Special Sector 0</description>
11570                <bitRange>[8:8]</bitRange>
11571                <access>read-write</access>
11572              </field>
11573              <field>
11574                <name>RED_ADDR_SM1</name>
11575                <description>Bad Row Pair Address for Special Sector 1</description>
11576                <bitRange>[23:16]</bitRange>
11577                <access>read-write</access>
11578              </field>
11579              <field>
11580                <name>RED_EN_SM1</name>
11581                <description>Redundancy Enable for Special Sector 1</description>
11582                <bitRange>[24:24]</bitRange>
11583                <access>read-write</access>
11584              </field>
11585            </fields>
11586          </register>
11587          <register>
11588            <name>RGRANT_DELAY_PRG</name>
11589            <description>R-grant delay for program</description>
11590            <addressOffset>0x98</addressOffset>
11591            <size>32</size>
11592            <access>read-write</access>
11593            <resetValue>0x1000000</resetValue>
11594            <resetMask>0x8FFFFFFF</resetMask>
11595            <fields>
11596              <field>
11597                <name>RGRANT_DELAY_PRG_SEQ12</name>
11598                <description>PROG&amp;PRE_PROG: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12
11599When = 0  R_GRANT_DELAY control is disabled
11600when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
11601                <bitRange>[7:0]</bitRange>
11602                <access>read-write</access>
11603              </field>
11604              <field>
11605                <name>RGRANT_DELAY_PRG_SEQ23</name>
11606                <description>PROG&amp;PRE_PROG: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23
11607When = 0  R_GRANT_DELAY control is disabled
11608when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
11609                <bitRange>[15:8]</bitRange>
11610                <access>read-write</access>
11611              </field>
11612              <field>
11613                <name>RGRANT_DELAY_SEQ30</name>
11614                <description>PROG&amp;PRE_PROG &amp; ERASE: R-grant blocking delay on seq3-seq0 transition. Scale = ANA_CTL0.SCALE_SEQ30
11615When = 0  R_GRANT_DELAY control is disabled
11616when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
11617                <bitRange>[23:16]</bitRange>
11618                <access>read-write</access>
11619              </field>
11620              <field>
11621                <name>RGRANT_DELAY_CLK</name>
11622                <description>Frequency divider from clk_t  to create the 8MHz reference clock for R_grant delay
11623The value of this field is the integer result of 'clk_t frequency / 8'.
11624Example: for clk_t=100 this field is INT(100/8) =12.
11625This field is updated at runtime with the  'SW_RGRANT_DELAY_CLK ' value from the HV parameters table</description>
11626                <bitRange>[27:24]</bitRange>
11627                <access>read-write</access>
11628              </field>
11629              <field>
11630                <name>HV_PARAMS_LOADED</name>
11631                <description>0: HV Pulse common params not loaded
116321: HV Pulse common params  loaded: r-grant delays, r-grant scale, prescaler, timer values for seq1,seq2_pre, seq2_post, seq3</description>
11633                <bitRange>[31:31]</bitRange>
11634                <access>read-write</access>
11635              </field>
11636            </fields>
11637          </register>
11638          <register>
11639            <name>PW_SEQ12</name>
11640            <description>HV Pulse Delay for seq 1&amp;2 pre</description>
11641            <addressOffset>0xA0</addressOffset>
11642            <size>32</size>
11643            <access>read-write</access>
11644            <resetValue>0x0</resetValue>
11645            <resetMask>0xFFFFFFFF</resetMask>
11646            <fields>
11647              <field>
11648                <name>PW_SEQ1</name>
11649                <description>Seq1 delay</description>
11650                <bitRange>[15:0]</bitRange>
11651                <access>read-write</access>
11652              </field>
11653              <field>
11654                <name>PW_SEQ2_PRE</name>
11655                <description>Seq2 pre delay</description>
11656                <bitRange>[31:16]</bitRange>
11657                <access>read-write</access>
11658              </field>
11659            </fields>
11660          </register>
11661          <register>
11662            <name>PW_SEQ23</name>
11663            <description>HV Pulse Delay for seq2 post &amp; seq3</description>
11664            <addressOffset>0xA4</addressOffset>
11665            <size>32</size>
11666            <access>read-write</access>
11667            <resetValue>0x0</resetValue>
11668            <resetMask>0xFFFFFFFF</resetMask>
11669            <fields>
11670              <field>
11671                <name>PW_SEQ2_POST</name>
11672                <description>Seq2 post  delay</description>
11673                <bitRange>[15:0]</bitRange>
11674                <access>read-write</access>
11675              </field>
11676              <field>
11677                <name>PW_SEQ3</name>
11678                <description>Seq3 delay</description>
11679                <bitRange>[31:16]</bitRange>
11680                <access>read-write</access>
11681              </field>
11682            </fields>
11683          </register>
11684          <register>
11685            <name>RGRANT_SCALE_ERS</name>
11686            <description>R-grant delay scale for erase</description>
11687            <addressOffset>0xA8</addressOffset>
11688            <size>32</size>
11689            <access>read-write</access>
11690            <resetValue>0x0</resetValue>
11691            <resetMask>0xFFFF03FF</resetMask>
11692            <fields>
11693              <field>
11694                <name>SCALE_ERS_SEQ01</name>
11695                <description>ERASE: Scale for R_GRANT_DELAY on seq0-seq1 transition:
1169600: 0.125uS
1169701: 1uS
1169810: 10uS
1169911: 100uS</description>
11700                <bitRange>[1:0]</bitRange>
11701                <access>read-write</access>
11702              </field>
11703              <field>
11704                <name>SCALE_ERS_SEQ12</name>
11705                <description>ERASE: Scale for R_GRANT_DELAY on seq1-seq2 transition:
1170600: 0.125uS
1170701: 1uS
1170810: 10uS
1170911: 100uS</description>
11710                <bitRange>[3:2]</bitRange>
11711                <access>read-write</access>
11712              </field>
11713              <field>
11714                <name>SCALE_ERS_SEQ23</name>
11715                <description>ERASE: Scale for R_GRANT_DELAY on seq2-seq3 transition:
1171600: 0.125uS
1171701: 1uS
1171810: 10uS
1171911: 100uS</description>
11720                <bitRange>[5:4]</bitRange>
11721                <access>read-write</access>
11722              </field>
11723              <field>
11724                <name>SCALE_ERS_PEON</name>
11725                <description>ERASE: Scale for R_GRANT_DELAY on PE On transition:
1172600: 0.125uS
1172701: 1uS
1172810: 10uS
1172911: 100uS</description>
11730                <bitRange>[7:6]</bitRange>
11731                <access>read-write</access>
11732              </field>
11733              <field>
11734                <name>SCALE_ERS_PEOFF</name>
11735                <description>ERASE: Scale for R_GRANT_DELAY on PE OFF transition:
1173600: 0.125uS
1173701: 1uS
1173810: 10uS
1173911: 100uS</description>
11740                <bitRange>[9:8]</bitRange>
11741                <access>read-write</access>
11742              </field>
11743              <field>
11744                <name>RGRANT_DELAY_ERS_PEON</name>
11745                <description>ERASE: R-grant blocking delay on PE ON. Scale = ANA_CTL0.SCALE_PEON
11746When = 0  R_GRANT_DELAY control is disabled
11747when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
11748                <bitRange>[23:16]</bitRange>
11749                <access>read-write</access>
11750              </field>
11751              <field>
11752                <name>RGRANT_DELAY_ERS_PEOFF</name>
11753                <description>ERASE: R-grant blocking delay on PE OFF. Scale = ANA_CTL0.SCALE_PEOFF
11754When = 0  R_GRANT_DELAY control is disabled
11755when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
11756                <bitRange>[31:24]</bitRange>
11757                <access>read-write</access>
11758              </field>
11759            </fields>
11760          </register>
11761          <register>
11762            <name>RGRANT_DELAY_ERS</name>
11763            <description>R-grant delay for erase</description>
11764            <addressOffset>0xAC</addressOffset>
11765            <size>32</size>
11766            <access>read-write</access>
11767            <resetValue>0x0</resetValue>
11768            <resetMask>0xFFFFFF</resetMask>
11769            <fields>
11770              <field>
11771                <name>RGRANT_DELAY_ERS_SEQ01</name>
11772                <description>ERASE: R-grant blocking delay on seq0-seq1 transition. Scale = ANA_CTL0.SCALE_SEQ01
11773When = 0  R_GRANT_DELAY control is disabled
11774when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
11775                <bitRange>[7:0]</bitRange>
11776                <access>read-write</access>
11777              </field>
11778              <field>
11779                <name>RGRANT_DELAY_ERS_SEQ12</name>
11780                <description>ERASE: R-grant blocking delay on seq1-seq2 transition. Scale = ANA_CTL0.SCALE_SEQ12
11781When = 0  R_GRANT_DELAY control is disabled
11782when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
11783                <bitRange>[15:8]</bitRange>
11784                <access>read-write</access>
11785              </field>
11786              <field>
11787                <name>RGRANT_DELAY_ERS_SEQ23</name>
11788                <description>ERASE: R-grant blocking delay on seq2-seq3 transition. Scale = ANA_CTL0.SCALE_SEQ23
11789When = 0  R_GRANT_DELAY control is disabled
11790when IF_SEL=1  R_GRANT_DELAY control is disabled</description>
11791                <bitRange>[23:16]</bitRange>
11792                <access>read-write</access>
11793              </field>
11794            </fields>
11795          </register>
11796          <register>
11797            <name>FM_PL_WRDATA_ALL</name>
11798            <description>Flash macro write page latches all</description>
11799            <addressOffset>0x7FC</addressOffset>
11800            <size>32</size>
11801            <access>read-write</access>
11802            <resetValue>0x0</resetValue>
11803            <resetMask>0xFFFFFFFF</resetMask>
11804            <fields>
11805              <field>
11806                <name>DATA32</name>
11807                <description>Write all high Voltage page latches with the same 32-bit data in a single write cycle
11808Read always returns 0.</description>
11809                <bitRange>[31:0]</bitRange>
11810                <access>read-write</access>
11811              </field>
11812            </fields>
11813          </register>
11814          <register>
11815            <dim>256</dim>
11816            <dimIncrement>4</dimIncrement>
11817            <name>FM_PL_DATA[%s]</name>
11818            <description>Flash macro Page Latches data</description>
11819            <addressOffset>0x800</addressOffset>
11820            <size>32</size>
11821            <access>read-write</access>
11822            <resetValue>0x0</resetValue>
11823            <resetMask>0xFFFFFFFF</resetMask>
11824            <fields>
11825              <field>
11826                <name>DATA32</name>
11827                <description>Four page latch Bytes
11828When reading the page latches it requires FM_CTL.IF_SEL to be '1'
11829Note: the high Voltage page latches are readable for test mode functionality.</description>
11830                <bitRange>[31:0]</bitRange>
11831                <access>read-write</access>
11832              </field>
11833            </fields>
11834          </register>
11835          <register>
11836            <dim>256</dim>
11837            <dimIncrement>4</dimIncrement>
11838            <name>FM_MEM_DATA[%s]</name>
11839            <description>Flash macro memory sense amplifier and column decoder data</description>
11840            <addressOffset>0xC00</addressOffset>
11841            <size>32</size>
11842            <access>read-only</access>
11843            <resetValue>0x0</resetValue>
11844            <resetMask>0xFFFFFFFF</resetMask>
11845            <fields>
11846              <field>
11847                <name>DATA32</name>
11848                <description>Sense amplifier and column multiplexer structure Bytes. The read data is dependent on FM_CTL.IF_SEL:
11849- IF_SEL is 0: data as specified by the R interface address
11850- IF_SEL is 1: data as specified by FM_MEM_ADDR and the offset of the accessed FM_MEM_DATA register.</description>
11851                <bitRange>[31:0]</bitRange>
11852                <access>read-only</access>
11853              </field>
11854            </fields>
11855          </register>
11856        </cluster>
11857      </registers>
11858    </peripheral>
11859    <peripheral>
11860      <name>SRSS</name>
11861      <description>SRSS Core Registers</description>
11862      <baseAddress>0x40260000</baseAddress>
11863      <addressBlock>
11864        <offset>0</offset>
11865        <size>65536</size>
11866        <usage>registers</usage>
11867      </addressBlock>
11868      <registers>
11869        <register>
11870          <name>PWR_CTL</name>
11871          <description>Power Mode Control</description>
11872          <addressOffset>0x0</addressOffset>
11873          <size>32</size>
11874          <access>read-write</access>
11875          <resetValue>0x0</resetValue>
11876          <resetMask>0xFFFC0033</resetMask>
11877          <fields>
11878            <field>
11879              <name>POWER_MODE</name>
11880              <description>Current power mode of the device.  Note that this field cannot be read in all power modes on actual silicon.</description>
11881              <bitRange>[1:0]</bitRange>
11882              <access>read-only</access>
11883              <enumeratedValues>
11884                <enumeratedValue>
11885                  <name>RESET</name>
11886                  <description>System is resetting.</description>
11887                  <value>0</value>
11888                </enumeratedValue>
11889                <enumeratedValue>
11890                  <name>ACTIVE</name>
11891                  <description>At least one CPU is running.</description>
11892                  <value>1</value>
11893                </enumeratedValue>
11894                <enumeratedValue>
11895                  <name>SLEEP</name>
11896                  <description>No CPUs are running.  Peripherals may be running.</description>
11897                  <value>2</value>
11898                </enumeratedValue>
11899                <enumeratedValue>
11900                  <name>DEEPSLEEP</name>
11901                  <description>Main high-frequency clock is off; low speed clocks are available.  Communication interface clocks may be present.</description>
11902                  <value>3</value>
11903                </enumeratedValue>
11904              </enumeratedValues>
11905            </field>
11906            <field>
11907              <name>DEBUG_SESSION</name>
11908              <description>Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)</description>
11909              <bitRange>[4:4]</bitRange>
11910              <access>read-only</access>
11911              <enumeratedValues>
11912                <enumeratedValue>
11913                  <name>NO_SESSION</name>
11914                  <description>No debug session active</description>
11915                  <value>0</value>
11916                </enumeratedValue>
11917                <enumeratedValue>
11918                  <name>SESSION_ACTIVE</name>
11919                  <description>Debug session is active.  Power modes behave differently to keep the debug session active.</description>
11920                  <value>1</value>
11921                </enumeratedValue>
11922              </enumeratedValues>
11923            </field>
11924            <field>
11925              <name>LPM_READY</name>
11926              <description>Indicates whether certain low power functions are ready.  The low current circuits take longer to startup after XRES/POR/BOD/HIBERNATE wakeup than the normal mode circuits.  HIBERNATE mode may be entered regardless of this bit.  This register is only reset by XRES/POR/BOD/HIBERNATE.
119270: If a low power circuit operation is requested, it will stay in its normal operating mode until it is ready.  If DEEPSLEEP is requested by all processors WFI/WFE, the device will instead enter SLEEP.  When low power circuits are ready, device will automatically enter the originally requested mode.
119281: Normal operation.  DEEPSLEEP and low power circuits operate as requested in other registers.</description>
11929              <bitRange>[5:5]</bitRange>
11930              <access>read-only</access>
11931            </field>
11932            <field>
11933              <name>IREF_LPMODE</name>
11934              <description>Control the power mode of the reference current generator.  The value in this register is ignored and normal mode is used until LPM_READY==1.  This register is only reset by XRES/POR/BOD/HIBERNATE.
119350: Current reference generator operates in normal mode.  It works for vddd ramp rates of 100mV/us or less.
119361: Current reference generator operates in low power mode.  Response time is reduced to save current, and it works for vddd ramp rates of 10mV/us or less.</description>
11937              <bitRange>[18:18]</bitRange>
11938              <access>read-write</access>
11939            </field>
11940            <field>
11941              <name>VREFBUF_OK</name>
11942              <description>Indicates that the voltage reference buffer is ready.  Due to synchronization delays, it may take two IMO clock cycles for hardware to clear this bit after asserting VREFBUF_DIS=1.</description>
11943              <bitRange>[19:19]</bitRange>
11944              <access>read-only</access>
11945            </field>
11946            <field>
11947              <name>DPSLP_REG_DIS</name>
11948              <description>Disable the DeepSleep regulator.  This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case.  This register is only reset by XRES/POR/BOD/HIBERNATE.
119490: DeepSleep Regulator is on.
119501: DeepSleep Regulator is off.</description>
11951              <bitRange>[20:20]</bitRange>
11952              <access>read-write</access>
11953            </field>
11954            <field>
11955              <name>RET_REG_DIS</name>
11956              <description>Disable the Retention regulator.  This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case.  This register is only reset by XRES/POR/BOD/HIBERNATE.
119570: Retention Regulator is on.
119581: Retention Regulator is off.</description>
11959              <bitRange>[21:21]</bitRange>
11960              <access>read-write</access>
11961            </field>
11962            <field>
11963              <name>NWELL_REG_DIS</name>
11964              <description>Disable the Nwell regulator.  This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case.  This register is only reset by XRES/POR/BOD/HIBERNATE.
119650: Nwell Regulator is on.
119661: Nwell Regulator is off.</description>
11967              <bitRange>[22:22]</bitRange>
11968              <access>read-write</access>
11969            </field>
11970            <field>
11971              <name>LINREG_DIS</name>
11972              <description>Disable the linear Core Regulator.  This is only legal when the on-chip buck regulator supplies vccd, but there is no hardware protection for this case.  This register is only reset by XRES/POR/BOD/HIBERNATE.
119730: Linear regulator is on.
119741: Linear regulator is off.</description>
11975              <bitRange>[23:23]</bitRange>
11976              <access>read-write</access>
11977            </field>
11978            <field>
11979              <name>LINREG_LPMODE</name>
11980              <description>Control the power mode of the Linear Regulator.  The value in this register is ignored and normal mode is used until LPM_READY==1.  This register is only reset by XRES/POR/BOD/HIBERNATE.
119810: Linear Regulator operates in normal mode.  Internal current consumption is 50uA and load current capability is 50mA to 300mA, depending on the number of regulator modules present in the product.
119821: Linear Regulator operates in low power mode.  Internal current consumption is 5uA and load current capability is 25mA.  Firmware must ensure the current is kept within the limit.</description>
11983              <bitRange>[24:24]</bitRange>
11984              <access>read-write</access>
11985            </field>
11986            <field>
11987              <name>PORBOD_LPMODE</name>
11988              <description>Control the power mode of the POR/BOD circuits.  The value in this register is ignored and normal mode is used until LPM_READY==1.  This register is only reset by XRES/POR/BOD/HIBERNATE.
119890: POR/BOD circuits operate in normal mode.  They work for vddd ramp rates of 100mV/us or less.
119901: POR/BOD circuits operate in low power mode.  Response time is reduced to save current, and they work for vddd ramp rates of 10mV/us or less.</description>
11991              <bitRange>[25:25]</bitRange>
11992              <access>read-write</access>
11993            </field>
11994            <field>
11995              <name>BGREF_LPMODE</name>
11996              <description>Control the power mode of the Bandgap Voltage and Current References.  This applies to voltage and current generation and is different than the reference voltage buffer.  The value in this register is ignored and normal mode is used until LPM_READY==1.  When lower power mode is used, the Active Reference circuit can be disabled to reduce current.  Firmware is responsible to ensure ACT_REF_OK==1 before changing back to normal mode.  This register is only reset by XRES/POR/BOD/HIBERNATE.
119970: Active Bandgap Voltage and Current Reference operates in normal mode.  They work for vddd ramp rates of 100mV/us or less.
119981: Active Bandgap Voltage and Current Reference operates in low power mode.  Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less.  The Active Reference may be disabled using ACT_REF_DIS=0.</description>
11999              <bitRange>[26:26]</bitRange>
12000              <access>read-write</access>
12001            </field>
12002            <field>
12003              <name>PLL_LS_BYPASS</name>
12004              <description>Bypass level shifter inside the PLL.
120050: Do not bypass the level shifter.  This setting is ok for all operational modes and vccd target voltage.
120061: Bypass the level shifter.  This may reduce jitter on the PLL output clock, but can only be used when vccd is targeted to 1.1V nominal.  Otherwise, it can result in clock degradation and static current.</description>
12007              <bitRange>[27:27]</bitRange>
12008              <access>read-write</access>
12009            </field>
12010            <field>
12011              <name>VREFBUF_LPMODE</name>
12012              <description>Control the power mode of the 800mV voltage reference buffer.  The value in this register is ignored and normal mode is used until LPM_READY==1.
120130: Voltage Reference Buffer operates in normal mode.  They work for vddd ramp rates of 100mV/us or less.  This register is only reset by XRES/POR/BOD/HIBERNATE.
120141: Voltage Reference Buffer operates in low power mode.  Power supply rejection is reduced to save current, and they work for vddd ramp rates of 10mV/us or less.</description>
12015              <bitRange>[28:28]</bitRange>
12016              <access>read-write</access>
12017            </field>
12018            <field>
12019              <name>VREFBUF_DIS</name>
12020              <description>Disable the 800mV voltage reference buffer.  Firmware should only disable the buffer when there is no connected circuit that is using it.  SRSS circuits that require it are the PLL and ECO.  A particular product may have circuits outside the SRSS that use the buffer.  This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
12021              <bitRange>[29:29]</bitRange>
12022              <access>read-write</access>
12023            </field>
12024            <field>
12025              <name>ACT_REF_DIS</name>
12026              <description>Disables the Active Reference.  Firmware must ensure that LPM_READY==1 and BGREF_LPMODE==1 for at least 1us before disabling the Active Reference.  When enabling the Active Reference, use ACT_REF_OK indicator to know when it is ready.  This register is only reset by XRES/POR/BOD/HIBERNATE.
120270: Active Reference is enabled
120281: Active Reference is disabled</description>
12029              <bitRange>[30:30]</bitRange>
12030              <access>read-write</access>
12031            </field>
12032            <field>
12033              <name>ACT_REF_OK</name>
12034              <description>Indicates that the normal mode of the Active Reference is ready.</description>
12035              <bitRange>[31:31]</bitRange>
12036              <access>read-only</access>
12037            </field>
12038          </fields>
12039        </register>
12040        <register>
12041          <name>PWR_HIBERNATE</name>
12042          <description>HIBERNATE Mode Register</description>
12043          <addressOffset>0x4</addressOffset>
12044          <size>32</size>
12045          <access>read-write</access>
12046          <resetValue>0x0</resetValue>
12047          <resetMask>0xCFFEFFFF</resetMask>
12048          <fields>
12049            <field>
12050              <name>TOKEN</name>
12051              <description>Contains a 8-bit token that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event.  Note that waking up from HIBERNATE using XRES will reset this register.</description>
12052              <bitRange>[7:0]</bitRange>
12053              <access>read-write</access>
12054            </field>
12055            <field>
12056              <name>UNLOCK</name>
12057              <description>This byte must be set to 0x3A for FREEZE or HIBERNATE fields to operate.  Any other value in this register will cause FREEZE/HIBERNATE to have no effect, except as noted in the FREEZE description.</description>
12058              <bitRange>[15:8]</bitRange>
12059              <access>read-write</access>
12060            </field>
12061            <field>
12062              <name>FREEZE</name>
12063              <description>Firmware sets this bit to freeze the configuration, mode and state of all GPIOs and SIOs in the system.  When entering HIBERNATE mode, the first write instructs DEEPSLEEP peripherals that they cannot ignore the upcoming freeze command.  This occurs even in the illegal condition where UNLOCK is not set.  If UNLOCK and HIBERNATE are properly set, the IOs actually freeze on the second write.</description>
12064              <bitRange>[17:17]</bitRange>
12065              <access>read-write</access>
12066            </field>
12067            <field>
12068              <name>MASK_HIBALARM</name>
12069              <description>When set, HIBERNATE will wakeup for a RTC interrupt</description>
12070              <bitRange>[18:18]</bitRange>
12071              <access>read-write</access>
12072            </field>
12073            <field>
12074              <name>MASK_HIBWDT</name>
12075              <description>When set, HIBERNATE will wakeup if WDT matches</description>
12076              <bitRange>[19:19]</bitRange>
12077              <access>read-write</access>
12078            </field>
12079            <field>
12080              <name>POLARITY_HIBPIN</name>
12081              <description>Each bit sets the active polarity of the corresponding wakeup pin.
120820: Pin input of 0 will wakeup the part from HIBERNATE
120831: Pin input of 1 will wakeup the part from HIBERNATE</description>
12084              <bitRange>[23:20]</bitRange>
12085              <access>read-write</access>
12086            </field>
12087            <field>
12088              <name>MASK_HIBPIN</name>
12089              <description>When set, HIBERNATE will wakeup if the corresponding pin input matches the POLARITY_HIBPIN setting.  Each bit corresponds to one of the wakeup pins.</description>
12090              <bitRange>[27:24]</bitRange>
12091              <access>read-write</access>
12092            </field>
12093            <field>
12094              <name>HIBERNATE_DISABLE</name>
12095              <description>Hibernate disable bit.
120960: Normal operation, HIBERNATE works as described
120971: Further writes to this register are ignored
12098Note: This bit is a write-once bit until the next reset.  Avoid changing any other bits in this register while disabling HIBERNATE mode.  Also, it is recommended to clear the UNLOCK code, if it was previously written..</description>
12099              <bitRange>[30:30]</bitRange>
12100              <access>read-write</access>
12101            </field>
12102            <field>
12103              <name>HIBERNATE</name>
12104              <description>Firmware sets this bit to enter HIBERNATE mode.  The system will enter HIBERNATE mode immediately after writing to this bit and will wakeup only in response to XRES or WAKEUP event.  Both UNLOCK and FREEZE must have been set correctly in a previous write operations.  Otherwise, it will not enter HIBERNATE.  External supplies must have been stable for 250us before entering HIBERNATE mode.</description>
12105              <bitRange>[31:31]</bitRange>
12106              <access>read-write</access>
12107            </field>
12108          </fields>
12109        </register>
12110        <register>
12111          <name>PWR_LVD_CTL</name>
12112          <description>Low Voltage Detector (LVD) Configuration Register</description>
12113          <addressOffset>0x8</addressOffset>
12114          <size>32</size>
12115          <access>read-write</access>
12116          <resetValue>0x0</resetValue>
12117          <resetMask>0xFF</resetMask>
12118          <fields>
12119            <field>
12120              <name>HVLVD1_TRIPSEL</name>
12121              <description>Threshold selection for HVLVD1.  Disable the LVD (HVLVD1_EN=0) before changing the threshold.
121220: rise=1.225V (nom), fall=1.2V (nom)
121231: rise=1.425V (nom), fall=1.4V (nom)
121242: rise=1.625V (nom), fall=1.6V (nom)
121253: rise=1.825V (nom), fall=1.8V (nom)
121264: rise=2.025V (nom), fall=2V (nom)
121275: rise=2.125V (nom), fall=2.1V (nom)
121286: rise=2.225V (nom), fall=2.2V (nom)
121297: rise=2.325V (nom), fall=2.3V (nom)
121308: rise=2.425V (nom), fall=2.4V (nom)
121319: rise=2.525V (nom), fall=2.5V (nom)
1213210: rise=2.625V (nom), fall=2.6V (nom)
1213311: rise=2.725V (nom), fall=2.7V (nom)
1213412: rise=2.825V (nom), fall=2.8V (nom)
1213513: rise=2.925V (nom), fall=2.9V (nom)
1213614: rise=3.025V (nom), fall=3.0V (nom)
1213715: rise=3.125V (nom), fall=3.1V (nom)</description>
12138              <bitRange>[3:0]</bitRange>
12139              <access>read-write</access>
12140            </field>
12141            <field>
12142              <name>HVLVD1_SRCSEL</name>
12143              <description>Source selection for HVLVD1</description>
12144              <bitRange>[6:4]</bitRange>
12145              <access>read-write</access>
12146              <enumeratedValues>
12147                <enumeratedValue>
12148                  <name>VDDD</name>
12149                  <description>Select VDDD</description>
12150                  <value>0</value>
12151                </enumeratedValue>
12152                <enumeratedValue>
12153                  <name>AMUXBUSA</name>
12154                  <description>Select AMUXBUSA (VDDD branch)</description>
12155                  <value>1</value>
12156                </enumeratedValue>
12157                <enumeratedValue>
12158                  <name>RSVD</name>
12159                  <description>N/A</description>
12160                  <value>2</value>
12161                </enumeratedValue>
12162                <enumeratedValue>
12163                  <name>VDDIO</name>
12164                  <description>N/A</description>
12165                  <value>3</value>
12166                </enumeratedValue>
12167                <enumeratedValue>
12168                  <name>AMUXBUSB</name>
12169                  <description>Select AMUXBUSB (VDDD branch)</description>
12170                  <value>4</value>
12171                </enumeratedValue>
12172              </enumeratedValues>
12173            </field>
12174            <field>
12175              <name>HVLVD1_EN</name>
12176              <description>Enable HVLVD1 voltage monitor.  When the LVD is enabled, it takes 20us for it to settle.  There is no hardware stabilization counter, and it may falsely trigger during settling.  It is recommended that firmware keep the interrupt masked for at least 8us, write a 1'b1 to the corresponding SRSS_INTR field to any falsely pended interrupt, and then optionally unmask the interrupt.  After enabling, it is further recommended to read the related PWR_LVD_STATUS field, since the interrupt only triggers on edges.  This bit is cleared (LVD is disabled) when entering DEEPSLEEP to prevent false interrupts during wakeup.</description>
12177              <bitRange>[7:7]</bitRange>
12178              <access>read-write</access>
12179            </field>
12180          </fields>
12181        </register>
12182        <register>
12183          <name>PWR_BUCK_CTL</name>
12184          <description>Buck Control Register</description>
12185          <addressOffset>0x14</addressOffset>
12186          <size>32</size>
12187          <access>read-write</access>
12188          <resetValue>0x5</resetValue>
12189          <resetMask>0xC0000007</resetMask>
12190          <fields>
12191            <field>
12192              <name>BUCK_OUT1_SEL</name>
12193              <description>Voltage output selection for vccbuck1 output.  This register is only reset by XRES/POR/BOD/HIBERNATE.  When increasing the voltage, it can take up to 200us for the output voltage to settle.  When decreasing the voltage, the settling time depends on the load current.
121940: 0.85V
121951: 0.875V
121962: 0.90V
121973: 0.95V
121984: 1.05V
121995: 1.10V
122006: 1.15V
122017: 1.20V</description>
12202              <bitRange>[2:0]</bitRange>
12203              <access>read-write</access>
12204            </field>
12205            <field>
12206              <name>BUCK_EN</name>
12207              <description>Master enable for buck converter.    This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
12208              <bitRange>[30:30]</bitRange>
12209              <access>read-write</access>
12210            </field>
12211            <field>
12212              <name>BUCK_OUT1_EN</name>
12213              <description>Enable for vccbuck1 output.  The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1.    This register is only reset by XRES/POR/BOD/HIBERNATE.  The regulator takes up to 600us to charge the external capacitor.  If there is additional load current while charging, this will increase the startup time.  The TRM specifies the required sequence when transitioning vccd from the LDO to SIMO Buck output #1.  TRM must follow the SAS.</description>
12214              <bitRange>[31:31]</bitRange>
12215              <access>read-write</access>
12216            </field>
12217          </fields>
12218        </register>
12219        <register>
12220          <name>PWR_BUCK_CTL2</name>
12221          <description>Buck Control Register 2</description>
12222          <addressOffset>0x18</addressOffset>
12223          <size>32</size>
12224          <access>read-write</access>
12225          <resetValue>0x0</resetValue>
12226          <resetMask>0xC0000007</resetMask>
12227          <fields>
12228            <field>
12229              <name>BUCK_OUT2_SEL</name>
12230              <description>Voltage output selection for vccbuck2 output.  When increasing the voltage, it can take up to 200us for the output voltage to settle.  When decreasing the voltage, the settling time depends on the load current.
122310: 1.15V
122321: 1.20V
122332: 1.25V
122343: 1.30V
122354: 1.35V
122365: 1.40V
122376: 1.45V
122387: 1.50V</description>
12239              <bitRange>[2:0]</bitRange>
12240              <access>read-write</access>
12241            </field>
12242            <field>
12243              <name>BUCK_OUT2_HW_SEL</name>
12244              <description>Hardware control for vccbuck2 output.  When this bit is set, the value in BUCK_OUT2_EN is ignored and a hardware signal is used instead.  If the product has supporting hardware, it can directly control the enable signal for vccbuck2.  The same charging time in BUCK_OUT2_EN applies.</description>
12245              <bitRange>[30:30]</bitRange>
12246              <access>read-write</access>
12247            </field>
12248            <field>
12249              <name>BUCK_OUT2_EN</name>
12250              <description>Enable for vccbuck2 output.  The value in this register is ignored unless PWR_BUCK_CTL.BUCK_EN==1.  The regulator takes up to 600us to charge the external capacitor.  If there is additional load current while charging, this will increase the startup time.</description>
12251              <bitRange>[31:31]</bitRange>
12252              <access>read-write</access>
12253            </field>
12254          </fields>
12255        </register>
12256        <register>
12257          <name>PWR_LVD_STATUS</name>
12258          <description>Low Voltage Detector (LVD) Status Register</description>
12259          <addressOffset>0x1C</addressOffset>
12260          <size>32</size>
12261          <access>read-only</access>
12262          <resetValue>0x0</resetValue>
12263          <resetMask>0x1</resetMask>
12264          <fields>
12265            <field>
12266              <name>HVLVD1_OK</name>
12267              <description>HVLVD1 output.
122680: below voltage threshold
122691: above voltage threshold</description>
12270              <bitRange>[0:0]</bitRange>
12271              <access>read-only</access>
12272            </field>
12273          </fields>
12274        </register>
12275        <register>
12276          <dim>16</dim>
12277          <dimIncrement>4</dimIncrement>
12278          <name>PWR_HIB_DATA[%s]</name>
12279          <description>HIBERNATE Data Register</description>
12280          <addressOffset>0x80</addressOffset>
12281          <size>32</size>
12282          <access>read-write</access>
12283          <resetValue>0x0</resetValue>
12284          <resetMask>0xFFFFFFFF</resetMask>
12285          <fields>
12286            <field>
12287              <name>HIB_DATA</name>
12288              <description>Additional data that is retained through a HIBERNATE/WAKEUP sequence that can be used by firmware for any application-specific purpose.  Note that waking up from HIBERNATE using XRES will reset this register.</description>
12289              <bitRange>[31:0]</bitRange>
12290              <access>read-write</access>
12291            </field>
12292          </fields>
12293        </register>
12294        <register>
12295          <name>WDT_CTL</name>
12296          <description>Watchdog Counter Control Register</description>
12297          <addressOffset>0x180</addressOffset>
12298          <size>32</size>
12299          <access>read-write</access>
12300          <resetValue>0xC0000001</resetValue>
12301          <resetMask>0xC0000001</resetMask>
12302          <fields>
12303            <field>
12304              <name>WDT_EN</name>
12305              <description>Enable this watchdog timer.  This field is retained during DEEPSLEEP and HIBERNATE modes.</description>
12306              <bitRange>[0:0]</bitRange>
12307              <access>read-write</access>
12308            </field>
12309            <field>
12310              <name>WDT_LOCK</name>
12311              <description>Prohibits writing to WDT_*, CLK_ILO_CONFIG, CLK_SELECT.LFCLK_SEL, and CLK_TRIM_ILO_CTL registers when not equal 0.  Requires at least two different writes to unlock.  A change in WDT_LOCK takes effect beginning with the next write cycle.
12312Note that this field is 2 bits to force multiple writes only.  It represents only a single write protect signal protecting all those registers at the same time.  WDT will lock on any reset.  This field is not retained during DEEPSLEEP or HIBERNATE mode, so the WDT will be locked after wakeup from these modes.</description>
12313              <bitRange>[31:30]</bitRange>
12314              <access>read-write</access>
12315              <enumeratedValues>
12316                <enumeratedValue>
12317                  <name>NO_CHG</name>
12318                  <description>No effect</description>
12319                  <value>0</value>
12320                </enumeratedValue>
12321                <enumeratedValue>
12322                  <name>CLR0</name>
12323                  <description>Clears bit 0</description>
12324                  <value>1</value>
12325                </enumeratedValue>
12326                <enumeratedValue>
12327                  <name>CLR1</name>
12328                  <description>Clears bit 1</description>
12329                  <value>2</value>
12330                </enumeratedValue>
12331                <enumeratedValue>
12332                  <name>SET01</name>
12333                  <description>Sets both bits 0 and 1</description>
12334                  <value>3</value>
12335                </enumeratedValue>
12336              </enumeratedValues>
12337            </field>
12338          </fields>
12339        </register>
12340        <register>
12341          <name>WDT_CNT</name>
12342          <description>Watchdog Counter Count Register</description>
12343          <addressOffset>0x184</addressOffset>
12344          <size>32</size>
12345          <access>read-write</access>
12346          <resetValue>0x0</resetValue>
12347          <resetMask>0xFFFF</resetMask>
12348          <fields>
12349            <field>
12350              <name>COUNTER</name>
12351              <description>Current value of WDT Counter.  The write feature of this register is for engineering use (DfV), have no synchronization, and can only be applied when the WDT is fully off.  When writing, the value is updated immediately in the WDT counter, but it will read back as the old value until this register resynchronizes just after the negedge of ILO.  Writes will be ignored if they occur when the WDT is enabled.</description>
12352              <bitRange>[15:0]</bitRange>
12353              <access>read-write</access>
12354            </field>
12355          </fields>
12356        </register>
12357        <register>
12358          <name>WDT_MATCH</name>
12359          <description>Watchdog Counter Match Register</description>
12360          <addressOffset>0x188</addressOffset>
12361          <size>32</size>
12362          <access>read-write</access>
12363          <resetValue>0x1000</resetValue>
12364          <resetMask>0xFFFFF</resetMask>
12365          <fields>
12366            <field>
12367              <name>MATCH</name>
12368              <description>Match value for Watchdog counter.  Every time WDT_COUNTER reaches MATCH an interrupt is generated.  Two unserviced interrupts will lead to a system reset (i.e. at the third match).</description>
12369              <bitRange>[15:0]</bitRange>
12370              <access>read-write</access>
12371            </field>
12372            <field>
12373              <name>IGNORE_BITS</name>
12374              <description>The number of MSB bits of the watchdog timer that are NOT checked against MATCH.  This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches).  Up to 12 MSB can be ignored.  Settings &gt;12 behave like a setting of 12.</description>
12375              <bitRange>[19:16]</bitRange>
12376              <access>read-write</access>
12377            </field>
12378          </fields>
12379        </register>
12380        <cluster>
12381          <dim>2</dim>
12382          <dimIncrement>64</dimIncrement>
12383          <name>MCWDT_STRUCT[%s]</name>
12384          <description>Multi-Counter Watchdog Timer</description>
12385          <headerStructName>MCWDT_STRUCT</headerStructName>
12386          <addressOffset>0x00000200</addressOffset>
12387          <register>
12388            <name>MCWDT_CNTLOW</name>
12389            <description>Multi-Counter Watchdog Sub-counters 0/1</description>
12390            <addressOffset>0x4</addressOffset>
12391            <size>32</size>
12392            <access>read-write</access>
12393            <resetValue>0x0</resetValue>
12394            <resetMask>0xFFFFFFFF</resetMask>
12395            <fields>
12396              <field>
12397                <name>WDT_CTR0</name>
12398                <description>Current value of sub-counter 0 for this MCWDT.  Software writes are ignored when the sub-counter is enabled.</description>
12399                <bitRange>[15:0]</bitRange>
12400                <access>read-write</access>
12401              </field>
12402              <field>
12403                <name>WDT_CTR1</name>
12404                <description>Current value of sub-counter 1 for this MCWDT.  Software writes are ignored when the sub-counter is enabled</description>
12405                <bitRange>[31:16]</bitRange>
12406                <access>read-write</access>
12407              </field>
12408            </fields>
12409          </register>
12410          <register>
12411            <name>MCWDT_CNTHIGH</name>
12412            <description>Multi-Counter Watchdog Sub-counter 2</description>
12413            <addressOffset>0x8</addressOffset>
12414            <size>32</size>
12415            <access>read-write</access>
12416            <resetValue>0x0</resetValue>
12417            <resetMask>0xFFFFFFFF</resetMask>
12418            <fields>
12419              <field>
12420                <name>WDT_CTR2</name>
12421                <description>Current value of sub-counter 2 for this MCWDT.  Software writes are ignored when the sub-counter is enabled</description>
12422                <bitRange>[31:0]</bitRange>
12423                <access>read-write</access>
12424              </field>
12425            </fields>
12426          </register>
12427          <register>
12428            <name>MCWDT_MATCH</name>
12429            <description>Multi-Counter Watchdog Counter Match Register</description>
12430            <addressOffset>0xC</addressOffset>
12431            <size>32</size>
12432            <access>read-write</access>
12433            <resetValue>0x0</resetValue>
12434            <resetMask>0xFFFFFFFF</resetMask>
12435            <fields>
12436              <field>
12437                <name>WDT_MATCH0</name>
12438                <description>Match value for sub-counter 0 of this MCWDT</description>
12439                <bitRange>[15:0]</bitRange>
12440                <access>read-write</access>
12441              </field>
12442              <field>
12443                <name>WDT_MATCH1</name>
12444                <description>Match value for sub-counter 1 of this MCWDT</description>
12445                <bitRange>[31:16]</bitRange>
12446                <access>read-write</access>
12447              </field>
12448            </fields>
12449          </register>
12450          <register>
12451            <name>MCWDT_CONFIG</name>
12452            <description>Multi-Counter Watchdog Counter Configuration</description>
12453            <addressOffset>0x10</addressOffset>
12454            <size>32</size>
12455            <access>read-write</access>
12456            <resetValue>0x0</resetValue>
12457            <resetMask>0x1F010F0F</resetMask>
12458            <fields>
12459              <field>
12460                <name>WDT_MODE0</name>
12461                <description>Watchdog Counter Action on Match.  Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0).</description>
12462                <bitRange>[1:0]</bitRange>
12463                <access>read-write</access>
12464                <enumeratedValues>
12465                  <enumeratedValue>
12466                    <name>NOTHING</name>
12467                    <description>Do nothing</description>
12468                    <value>0</value>
12469                  </enumeratedValue>
12470                  <enumeratedValue>
12471                    <name>INT</name>
12472                    <description>Assert WDT_INTx</description>
12473                    <value>1</value>
12474                  </enumeratedValue>
12475                  <enumeratedValue>
12476                    <name>RESET</name>
12477                    <description>Assert WDT Reset</description>
12478                    <value>2</value>
12479                  </enumeratedValue>
12480                  <enumeratedValue>
12481                    <name>INT_THEN_RESET</name>
12482                    <description>Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt</description>
12483                    <value>3</value>
12484                  </enumeratedValue>
12485                </enumeratedValues>
12486              </field>
12487              <field>
12488                <name>WDT_CLEAR0</name>
12489                <description>Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1).
124900: Free running counter
124911: Clear on match.  In this mode, the minimum legal setting of WDT_MATCH0 is 1.</description>
12492                <bitRange>[2:2]</bitRange>
12493                <access>read-write</access>
12494              </field>
12495              <field>
12496                <name>WDT_CASCADE0_1</name>
12497                <description>Cascade Watchdog Counters 0,1.  Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0.
124980: Independent counters
124991: Cascaded counters</description>
12500                <bitRange>[3:3]</bitRange>
12501                <access>read-write</access>
12502              </field>
12503              <field>
12504                <name>WDT_MODE1</name>
12505                <description>Watchdog Counter Action on Match.  Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1).</description>
12506                <bitRange>[9:8]</bitRange>
12507                <access>read-write</access>
12508                <enumeratedValues>
12509                  <enumeratedValue>
12510                    <name>NOTHING</name>
12511                    <description>Do nothing</description>
12512                    <value>0</value>
12513                  </enumeratedValue>
12514                  <enumeratedValue>
12515                    <name>INT</name>
12516                    <description>Assert WDT_INTx</description>
12517                    <value>1</value>
12518                  </enumeratedValue>
12519                  <enumeratedValue>
12520                    <name>RESET</name>
12521                    <description>Assert WDT Reset</description>
12522                    <value>2</value>
12523                  </enumeratedValue>
12524                  <enumeratedValue>
12525                    <name>INT_THEN_RESET</name>
12526                    <description>Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt</description>
12527                    <value>3</value>
12528                  </enumeratedValue>
12529                </enumeratedValues>
12530              </field>
12531              <field>
12532                <name>WDT_CLEAR1</name>
12533                <description>Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1).
125340: Free running counter
125351: Clear on match.  In this mode, the minimum legal setting of WDT_MATCH1 is 1.</description>
12536                <bitRange>[10:10]</bitRange>
12537                <access>read-write</access>
12538              </field>
12539              <field>
12540                <name>WDT_CASCADE1_2</name>
12541                <description>Cascade Watchdog Counters 1,2.  Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1.  It is allowed to cascade all three WDT counters.
125420: Independent counters
125431: Cascaded counters.  When cascading all three counters, WDT_CLEAR1 must be 1.</description>
12544                <bitRange>[11:11]</bitRange>
12545                <access>read-write</access>
12546              </field>
12547              <field>
12548                <name>WDT_MODE2</name>
12549                <description>Watchdog Counter 2 Mode.</description>
12550                <bitRange>[16:16]</bitRange>
12551                <access>read-write</access>
12552                <enumeratedValues>
12553                  <enumeratedValue>
12554                    <name>NOTHING</name>
12555                    <description>Free running counter with no interrupt requests</description>
12556                    <value>0</value>
12557                  </enumeratedValue>
12558                  <enumeratedValue>
12559                    <name>INT</name>
12560                    <description>Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2).</description>
12561                    <value>1</value>
12562                  </enumeratedValue>
12563                </enumeratedValues>
12564              </field>
12565              <field>
12566                <name>WDT_BITS2</name>
12567                <description>Bit to observe for WDT_INT2:
125680: Assert after bit0 of WDT_CTR2 toggles (one int every tick)
12569...
1257031: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks)</description>
12571                <bitRange>[28:24]</bitRange>
12572                <access>read-write</access>
12573              </field>
12574            </fields>
12575          </register>
12576          <register>
12577            <name>MCWDT_CTL</name>
12578            <description>Multi-Counter Watchdog Counter Control</description>
12579            <addressOffset>0x14</addressOffset>
12580            <size>32</size>
12581            <access>read-write</access>
12582            <resetValue>0x0</resetValue>
12583            <resetMask>0xB0B0B</resetMask>
12584            <fields>
12585              <field>
12586                <name>WDT_ENABLE0</name>
12587                <description>Enable subcounter 0.  May take up to 2 LFCLK cycles to take effect.
125880: Counter is disabled (not clocked)
125891: Counter is enabled (counting up)</description>
12590                <bitRange>[0:0]</bitRange>
12591                <access>read-write</access>
12592              </field>
12593              <field>
12594                <name>WDT_ENABLED0</name>
12595                <description>Indicates actual state of counter.  May lag WDT_ENABLE0 by up to two LFCLK cycles.</description>
12596                <bitRange>[1:1]</bitRange>
12597                <access>read-only</access>
12598              </field>
12599              <field>
12600                <name>WDT_RESET0</name>
12601                <description>Resets counter 0 back to 0000.  Hardware will reset this bit after counter was reset.  This will take up to one LFCLK cycle to take effect.</description>
12602                <bitRange>[3:3]</bitRange>
12603                <access>read-write</access>
12604              </field>
12605              <field>
12606                <name>WDT_ENABLE1</name>
12607                <description>Enable subcounter 1.  May take up to 2 LFCLK cycles to take effect.
126080: Counter is disabled (not clocked)
126091: Counter is enabled (counting up)</description>
12610                <bitRange>[8:8]</bitRange>
12611                <access>read-write</access>
12612              </field>
12613              <field>
12614                <name>WDT_ENABLED1</name>
12615                <description>Indicates actual state of counter.  May lag WDT_ENABLE1 by up to two LFCLK cycles.</description>
12616                <bitRange>[9:9]</bitRange>
12617                <access>read-only</access>
12618              </field>
12619              <field>
12620                <name>WDT_RESET1</name>
12621                <description>Resets counter 1 back to 0000.  Hardware will reset this bit after counter was reset.  This will take up to one LFCLK cycle to take effect.</description>
12622                <bitRange>[11:11]</bitRange>
12623                <access>read-write</access>
12624              </field>
12625              <field>
12626                <name>WDT_ENABLE2</name>
12627                <description>Enable subcounter 2.  May take up to 2 LFCLK cycles to take effect.
126280: Counter is disabled (not clocked)
126291: Counter is enabled (counting up)</description>
12630                <bitRange>[16:16]</bitRange>
12631                <access>read-write</access>
12632              </field>
12633              <field>
12634                <name>WDT_ENABLED2</name>
12635                <description>Indicates actual state of counter.  May lag WDT_ENABLE2 by up to two LFCLK cycles.</description>
12636                <bitRange>[17:17]</bitRange>
12637                <access>read-only</access>
12638              </field>
12639              <field>
12640                <name>WDT_RESET2</name>
12641                <description>Resets counter 2 back to 0000.  Hardware will reset this bit after counter was reset.  This will take up to one LFCLK cycle to take effect.</description>
12642                <bitRange>[19:19]</bitRange>
12643                <access>read-write</access>
12644              </field>
12645            </fields>
12646          </register>
12647          <register>
12648            <name>MCWDT_INTR</name>
12649            <description>Multi-Counter Watchdog Counter Interrupt Register</description>
12650            <addressOffset>0x18</addressOffset>
12651            <size>32</size>
12652            <access>read-write</access>
12653            <resetValue>0x0</resetValue>
12654            <resetMask>0x7</resetMask>
12655            <fields>
12656              <field>
12657                <name>MCWDT_INT0</name>
12658                <description>MCWDT Interrupt Request for sub-counter 0.  This bit is set by hardware as configured by this registers.  This bit must be cleared by firmware.  Clearing this bit also prevents Reset from happening when WDT_MODE0=3.</description>
12659                <bitRange>[0:0]</bitRange>
12660                <access>read-write</access>
12661              </field>
12662              <field>
12663                <name>MCWDT_INT1</name>
12664                <description>MCWDT Interrupt Request for sub-counter 1.  This bit is set by hardware as configured by this registers.  This bit must be cleared by firmware.  Clearing this bit also prevents Reset from happening when WDT_MODE1=3.</description>
12665                <bitRange>[1:1]</bitRange>
12666                <access>read-write</access>
12667              </field>
12668              <field>
12669                <name>MCWDT_INT2</name>
12670                <description>MCWDT Interrupt Request for sub-counter 2.  This bit is set by hardware as configured by this registers.  This bit must be cleared by firmware.  Clearing this bit also prevents Reset from happening when WDT_MODE2=3.</description>
12671                <bitRange>[2:2]</bitRange>
12672                <access>read-write</access>
12673              </field>
12674            </fields>
12675          </register>
12676          <register>
12677            <name>MCWDT_INTR_SET</name>
12678            <description>Multi-Counter Watchdog Counter Interrupt Set Register</description>
12679            <addressOffset>0x1C</addressOffset>
12680            <size>32</size>
12681            <access>read-write</access>
12682            <resetValue>0x0</resetValue>
12683            <resetMask>0x7</resetMask>
12684            <fields>
12685              <field>
12686                <name>MCWDT_INT0</name>
12687                <description>Set interrupt for MCWDT_INT0</description>
12688                <bitRange>[0:0]</bitRange>
12689                <access>read-write</access>
12690              </field>
12691              <field>
12692                <name>MCWDT_INT1</name>
12693                <description>Set interrupt for MCWDT_INT1</description>
12694                <bitRange>[1:1]</bitRange>
12695                <access>read-write</access>
12696              </field>
12697              <field>
12698                <name>MCWDT_INT2</name>
12699                <description>Set interrupt for MCWDT_INT2</description>
12700                <bitRange>[2:2]</bitRange>
12701                <access>read-write</access>
12702              </field>
12703            </fields>
12704          </register>
12705          <register>
12706            <name>MCWDT_INTR_MASK</name>
12707            <description>Multi-Counter Watchdog Counter Interrupt Mask Register</description>
12708            <addressOffset>0x20</addressOffset>
12709            <size>32</size>
12710            <access>read-write</access>
12711            <resetValue>0x0</resetValue>
12712            <resetMask>0x7</resetMask>
12713            <fields>
12714              <field>
12715                <name>MCWDT_INT0</name>
12716                <description>Mask for sub-counter 0</description>
12717                <bitRange>[0:0]</bitRange>
12718                <access>read-write</access>
12719              </field>
12720              <field>
12721                <name>MCWDT_INT1</name>
12722                <description>Mask for sub-counter 1</description>
12723                <bitRange>[1:1]</bitRange>
12724                <access>read-write</access>
12725              </field>
12726              <field>
12727                <name>MCWDT_INT2</name>
12728                <description>Mask for sub-counter 2</description>
12729                <bitRange>[2:2]</bitRange>
12730                <access>read-write</access>
12731              </field>
12732            </fields>
12733          </register>
12734          <register>
12735            <name>MCWDT_INTR_MASKED</name>
12736            <description>Multi-Counter Watchdog Counter Interrupt Masked Register</description>
12737            <addressOffset>0x24</addressOffset>
12738            <size>32</size>
12739            <access>read-only</access>
12740            <resetValue>0x0</resetValue>
12741            <resetMask>0x7</resetMask>
12742            <fields>
12743              <field>
12744                <name>MCWDT_INT0</name>
12745                <description>Logical and of corresponding request and mask bits.</description>
12746                <bitRange>[0:0]</bitRange>
12747                <access>read-only</access>
12748              </field>
12749              <field>
12750                <name>MCWDT_INT1</name>
12751                <description>Logical and of corresponding request and mask bits.</description>
12752                <bitRange>[1:1]</bitRange>
12753                <access>read-only</access>
12754              </field>
12755              <field>
12756                <name>MCWDT_INT2</name>
12757                <description>Logical and of corresponding request and mask bits.</description>
12758                <bitRange>[2:2]</bitRange>
12759                <access>read-only</access>
12760              </field>
12761            </fields>
12762          </register>
12763          <register>
12764            <name>MCWDT_LOCK</name>
12765            <description>Multi-Counter Watchdog Counter Lock Register</description>
12766            <addressOffset>0x28</addressOffset>
12767            <size>32</size>
12768            <access>read-write</access>
12769            <resetValue>0x0</resetValue>
12770            <resetMask>0xC0000000</resetMask>
12771            <fields>
12772              <field>
12773                <name>MCWDT_LOCK</name>
12774                <description>Prohibits writing control and configuration registers related to this MCWDT when not equal 0 (as specified in the other register descriptions).  Requires at least two different writes to unlock.
12775Note that this field is 2 bits to force multiple writes only.  Each MCWDT has a separate local lock.  LFCLK settings are locked by the global WDT_LOCK register, and this register has no effect on that.</description>
12776                <bitRange>[31:30]</bitRange>
12777                <access>read-write</access>
12778                <enumeratedValues>
12779                  <enumeratedValue>
12780                    <name>NO_CHG</name>
12781                    <description>No effect</description>
12782                    <value>0</value>
12783                  </enumeratedValue>
12784                  <enumeratedValue>
12785                    <name>CLR0</name>
12786                    <description>Clears bit 0</description>
12787                    <value>1</value>
12788                  </enumeratedValue>
12789                  <enumeratedValue>
12790                    <name>CLR1</name>
12791                    <description>Clears bit 1</description>
12792                    <value>2</value>
12793                  </enumeratedValue>
12794                  <enumeratedValue>
12795                    <name>SET01</name>
12796                    <description>Sets both bits 0 and 1</description>
12797                    <value>3</value>
12798                  </enumeratedValue>
12799                </enumeratedValues>
12800              </field>
12801            </fields>
12802          </register>
12803        </cluster>
12804        <register>
12805          <dim>16</dim>
12806          <dimIncrement>4</dimIncrement>
12807          <name>CLK_DSI_SELECT[%s]</name>
12808          <description>Clock DSI Select Register</description>
12809          <addressOffset>0x300</addressOffset>
12810          <size>32</size>
12811          <access>read-write</access>
12812          <resetValue>0x0</resetValue>
12813          <resetMask>0x1F</resetMask>
12814          <fields>
12815            <field>
12816              <name>DSI_MUX</name>
12817              <description>Selects a DSI source or low frequency clock for use in a clock path.  The output of this mux can be selected for clock PATH&lt;i&gt; using CLK_PATH_SELECT register.  Using the output of this mux as HFCLK source will result in undefined behavior.  It can be used to clocks to DSI or to the reference inputs of FLL/PLL, subject to the frequency limits of those circuits.  This mux is not glitch free, so do not change the selection while it is an actively selected clock.</description>
12818              <bitRange>[4:0]</bitRange>
12819              <access>read-write</access>
12820              <enumeratedValues>
12821                <enumeratedValue>
12822                  <name>DSI_OUT0</name>
12823                  <description>DSI0 - dsi_out[0]</description>
12824                  <value>0</value>
12825                </enumeratedValue>
12826                <enumeratedValue>
12827                  <name>DSI_OUT1</name>
12828                  <description>DSI1 - dsi_out[1]</description>
12829                  <value>1</value>
12830                </enumeratedValue>
12831                <enumeratedValue>
12832                  <name>DSI_OUT2</name>
12833                  <description>DSI2 - dsi_out[2]</description>
12834                  <value>2</value>
12835                </enumeratedValue>
12836                <enumeratedValue>
12837                  <name>DSI_OUT3</name>
12838                  <description>DSI3 - dsi_out[3]</description>
12839                  <value>3</value>
12840                </enumeratedValue>
12841                <enumeratedValue>
12842                  <name>DSI_OUT4</name>
12843                  <description>DSI4 - dsi_out[4]</description>
12844                  <value>4</value>
12845                </enumeratedValue>
12846                <enumeratedValue>
12847                  <name>DSI_OUT5</name>
12848                  <description>DSI5 - dsi_out[5]</description>
12849                  <value>5</value>
12850                </enumeratedValue>
12851                <enumeratedValue>
12852                  <name>DSI_OUT6</name>
12853                  <description>DSI6 - dsi_out[6]</description>
12854                  <value>6</value>
12855                </enumeratedValue>
12856                <enumeratedValue>
12857                  <name>DSI_OUT7</name>
12858                  <description>DSI7 - dsi_out[7]</description>
12859                  <value>7</value>
12860                </enumeratedValue>
12861                <enumeratedValue>
12862                  <name>DSI_OUT8</name>
12863                  <description>DSI8 - dsi_out[8]</description>
12864                  <value>8</value>
12865                </enumeratedValue>
12866                <enumeratedValue>
12867                  <name>DSI_OUT9</name>
12868                  <description>DSI9 - dsi_out[9]</description>
12869                  <value>9</value>
12870                </enumeratedValue>
12871                <enumeratedValue>
12872                  <name>DSI_OUT10</name>
12873                  <description>DSI10 - dsi_out[10]</description>
12874                  <value>10</value>
12875                </enumeratedValue>
12876                <enumeratedValue>
12877                  <name>DSI_OUT11</name>
12878                  <description>DSI11 - dsi_out[11]</description>
12879                  <value>11</value>
12880                </enumeratedValue>
12881                <enumeratedValue>
12882                  <name>DSI_OUT12</name>
12883                  <description>DSI12 - dsi_out[12]</description>
12884                  <value>12</value>
12885                </enumeratedValue>
12886                <enumeratedValue>
12887                  <name>DSI_OUT13</name>
12888                  <description>DSI13 - dsi_out[13]</description>
12889                  <value>13</value>
12890                </enumeratedValue>
12891                <enumeratedValue>
12892                  <name>DSI_OUT14</name>
12893                  <description>DSI14 - dsi_out[14]</description>
12894                  <value>14</value>
12895                </enumeratedValue>
12896                <enumeratedValue>
12897                  <name>DSI_OUT15</name>
12898                  <description>DSI15 - dsi_out[15]</description>
12899                  <value>15</value>
12900                </enumeratedValue>
12901                <enumeratedValue>
12902                  <name>ILO</name>
12903                  <description>ILO - Internal Low-speed Oscillator</description>
12904                  <value>16</value>
12905                </enumeratedValue>
12906                <enumeratedValue>
12907                  <name>WCO</name>
12908                  <description>WCO - Watch-Crystal Oscillator</description>
12909                  <value>17</value>
12910                </enumeratedValue>
12911                <enumeratedValue>
12912                  <name>ALTLF</name>
12913                  <description>ALTLF - Alternate Low-Frequency Clock</description>
12914                  <value>18</value>
12915                </enumeratedValue>
12916                <enumeratedValue>
12917                  <name>PILO</name>
12918                  <description>PILO - Precision Internal Low-speed Oscillator</description>
12919                  <value>19</value>
12920                </enumeratedValue>
12921              </enumeratedValues>
12922            </field>
12923          </fields>
12924        </register>
12925        <register>
12926          <dim>16</dim>
12927          <dimIncrement>4</dimIncrement>
12928          <name>CLK_PATH_SELECT[%s]</name>
12929          <description>Clock Path Select Register</description>
12930          <addressOffset>0x340</addressOffset>
12931          <size>32</size>
12932          <access>read-write</access>
12933          <resetValue>0x0</resetValue>
12934          <resetMask>0x7</resetMask>
12935          <fields>
12936            <field>
12937              <name>PATH_MUX</name>
12938              <description>Selects a source for clock PATH&lt;i&gt;.  Note that not all products support all clock sources.  Selecting a clock source that is not supported will result in undefined behavior.</description>
12939              <bitRange>[2:0]</bitRange>
12940              <access>read-write</access>
12941              <enumeratedValues>
12942                <enumeratedValue>
12943                  <name>IMO</name>
12944                  <description>IMO - Internal R/C Oscillator</description>
12945                  <value>0</value>
12946                </enumeratedValue>
12947                <enumeratedValue>
12948                  <name>EXTCLK</name>
12949                  <description>EXTCLK - External Clock Pin</description>
12950                  <value>1</value>
12951                </enumeratedValue>
12952                <enumeratedValue>
12953                  <name>ECO</name>
12954                  <description>ECO - External-Crystal Oscillator</description>
12955                  <value>2</value>
12956                </enumeratedValue>
12957                <enumeratedValue>
12958                  <name>ALTHF</name>
12959                  <description>ALTHF - Alternate High-Frequency clock input (product-specific clock)</description>
12960                  <value>3</value>
12961                </enumeratedValue>
12962                <enumeratedValue>
12963                  <name>DSI_MUX</name>
12964                  <description>DSI_MUX - Output of DSI mux for this path.  Using a DSI source directly as root of HFCLK will result in undefined behavior.</description>
12965                  <value>4</value>
12966                </enumeratedValue>
12967              </enumeratedValues>
12968            </field>
12969          </fields>
12970        </register>
12971        <register>
12972          <dim>16</dim>
12973          <dimIncrement>4</dimIncrement>
12974          <name>CLK_ROOT_SELECT[%s]</name>
12975          <description>Clock Root Select Register</description>
12976          <addressOffset>0x380</addressOffset>
12977          <size>32</size>
12978          <access>read-write</access>
12979          <resetValue>0x0</resetValue>
12980          <resetMask>0x8000003F</resetMask>
12981          <fields>
12982            <field>
12983              <name>ROOT_MUX</name>
12984              <description>Selects a clock path as the root of HFCLK&lt;k&gt; and for SRSS DSI input &lt;k&gt;.  Use CLK_PATH_SELECT[i] to configure the desired path.  Some paths may have FLL or PLL available (product-specific), and the control and bypass mux selections of these are in other registers.  Configure the FLL using CLK_FLL_CONFIG register.  Configure a PLL using the related CLK_PLL_CONFIG[k] register.  Note that not all products support all clock sources.  Selecting a clock source that is not supported will result in undefined behavior.</description>
12985              <bitRange>[3:0]</bitRange>
12986              <access>read-write</access>
12987              <enumeratedValues>
12988                <enumeratedValue>
12989                  <name>PATH0</name>
12990                  <description>Select PATH0 (can be configured for FLL)</description>
12991                  <value>0</value>
12992                </enumeratedValue>
12993                <enumeratedValue>
12994                  <name>PATH1</name>
12995                  <description>Select PATH1 (can be configured for PLL0, if available in the product)</description>
12996                  <value>1</value>
12997                </enumeratedValue>
12998                <enumeratedValue>
12999                  <name>PATH2</name>
13000                  <description>Select PATH2 (can be configured for PLL1, if available in the product)</description>
13001                  <value>2</value>
13002                </enumeratedValue>
13003                <enumeratedValue>
13004                  <name>PATH3</name>
13005                  <description>Select PATH3 (can be configured for PLL2, if available in the product)</description>
13006                  <value>3</value>
13007                </enumeratedValue>
13008                <enumeratedValue>
13009                  <name>PATH4</name>
13010                  <description>Select PATH4 (can be configured for PLL3, if available in the product)</description>
13011                  <value>4</value>
13012                </enumeratedValue>
13013                <enumeratedValue>
13014                  <name>PATH5</name>
13015                  <description>Select PATH5 (can be configured for PLL4, if available in the product)</description>
13016                  <value>5</value>
13017                </enumeratedValue>
13018                <enumeratedValue>
13019                  <name>PATH6</name>
13020                  <description>Select PATH6 (can be configured for PLL5, if available in the product)</description>
13021                  <value>6</value>
13022                </enumeratedValue>
13023                <enumeratedValue>
13024                  <name>PATH7</name>
13025                  <description>Select PATH7 (can be configured for PLL6, if available in the product)</description>
13026                  <value>7</value>
13027                </enumeratedValue>
13028                <enumeratedValue>
13029                  <name>PATH8</name>
13030                  <description>Select PATH8 (can be configured for PLL7, if available in the product)</description>
13031                  <value>8</value>
13032                </enumeratedValue>
13033                <enumeratedValue>
13034                  <name>PATH9</name>
13035                  <description>Select PATH9 (can be configured for PLL8, if available in the product)</description>
13036                  <value>9</value>
13037                </enumeratedValue>
13038                <enumeratedValue>
13039                  <name>PATH10</name>
13040                  <description>Select PATH10 (can be configured for PLL9, if available in the product)</description>
13041                  <value>10</value>
13042                </enumeratedValue>
13043                <enumeratedValue>
13044                  <name>PATH11</name>
13045                  <description>Select PATH11 (can be configured for PLL10, if available in the product)</description>
13046                  <value>11</value>
13047                </enumeratedValue>
13048                <enumeratedValue>
13049                  <name>PATH12</name>
13050                  <description>Select PATH12 (can be configured for PLL11, if available in the product)</description>
13051                  <value>12</value>
13052                </enumeratedValue>
13053                <enumeratedValue>
13054                  <name>PATH13</name>
13055                  <description>Select PATH13 (can be configured for PLL12, if available in the product)</description>
13056                  <value>13</value>
13057                </enumeratedValue>
13058                <enumeratedValue>
13059                  <name>PATH14</name>
13060                  <description>Select PATH14 (can be configured for PLL13, if available in the product)</description>
13061                  <value>14</value>
13062                </enumeratedValue>
13063                <enumeratedValue>
13064                  <name>PATH15</name>
13065                  <description>Select PATH15 (can be configured for PLL14, if available in the product)</description>
13066                  <value>15</value>
13067                </enumeratedValue>
13068              </enumeratedValues>
13069            </field>
13070            <field>
13071              <name>ROOT_DIV</name>
13072              <description>Selects predivider value for this clock root and DSI input.</description>
13073              <bitRange>[5:4]</bitRange>
13074              <access>read-write</access>
13075              <enumeratedValues>
13076                <enumeratedValue>
13077                  <name>NO_DIV</name>
13078                  <description>Transparent mode, feed through selected clock source w/o dividing.</description>
13079                  <value>0</value>
13080                </enumeratedValue>
13081                <enumeratedValue>
13082                  <name>DIV_BY_2</name>
13083                  <description>Divide selected clock source by 2</description>
13084                  <value>1</value>
13085                </enumeratedValue>
13086                <enumeratedValue>
13087                  <name>DIV_BY_4</name>
13088                  <description>Divide selected clock source by 4</description>
13089                  <value>2</value>
13090                </enumeratedValue>
13091                <enumeratedValue>
13092                  <name>DIV_BY_8</name>
13093                  <description>Divide selected clock source by 8</description>
13094                  <value>3</value>
13095                </enumeratedValue>
13096              </enumeratedValues>
13097            </field>
13098            <field>
13099              <name>ENABLE</name>
13100              <description>Enable for this clock root.  All clock roots default to disabled (ENABLE==0) except HFCLK0, which cannot be disabled.</description>
13101              <bitRange>[31:31]</bitRange>
13102              <access>read-write</access>
13103            </field>
13104          </fields>
13105        </register>
13106        <register>
13107          <name>CLK_SELECT</name>
13108          <description>Clock selection register</description>
13109          <addressOffset>0x500</addressOffset>
13110          <size>32</size>
13111          <access>read-write</access>
13112          <resetValue>0x0</resetValue>
13113          <resetMask>0xFF03</resetMask>
13114          <fields>
13115            <field>
13116              <name>LFCLK_SEL</name>
13117              <description>Select source for LFCLK.  Note that not all products support all clock sources.  Selecting a clock source that is not supported will result in undefined behavior.  Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.</description>
13118              <bitRange>[1:0]</bitRange>
13119              <access>read-write</access>
13120              <enumeratedValues>
13121                <enumeratedValue>
13122                  <name>ILO</name>
13123                  <description>ILO - Internal Low-speed Oscillator</description>
13124                  <value>0</value>
13125                </enumeratedValue>
13126                <enumeratedValue>
13127                  <name>WCO</name>
13128                  <description>WCO - Watch-Crystal Oscillator.  Requires Backup domain to be present and properly configured (including external watch crystal, if used).</description>
13129                  <value>1</value>
13130                </enumeratedValue>
13131                <enumeratedValue>
13132                  <name>ALTLF</name>
13133                  <description>ALTLF - Alternate Low-Frequency Clock.  Capability is product-specific</description>
13134                  <value>2</value>
13135                </enumeratedValue>
13136                <enumeratedValue>
13137                  <name>PILO</name>
13138                  <description>PILO - Precision ILO. If present, it works in DEEPSLEEP and higher modes.  Does not work in HIBERNATE mode.</description>
13139                  <value>3</value>
13140                </enumeratedValue>
13141              </enumeratedValues>
13142            </field>
13143            <field>
13144              <name>PUMP_SEL</name>
13145              <description>Selects clock PATH&lt;k&gt;, where k=PUMP_SEL.  The output of this mux goes to the PUMP_DIV to make PUMPCLK  Each product has a specific number of available clock paths.  Selecting a path that is not implemented on a product will result in undefined behavior.  Note that this is not a glitch free mux.</description>
13146              <bitRange>[11:8]</bitRange>
13147              <access>read-write</access>
13148            </field>
13149            <field>
13150              <name>PUMP_DIV</name>
13151              <description>Division ratio for PUMPCLK.  Uses selected PUMP_SEL clock as the source.</description>
13152              <bitRange>[14:12]</bitRange>
13153              <access>read-write</access>
13154              <enumeratedValues>
13155                <enumeratedValue>
13156                  <name>NO_DIV</name>
13157                  <description>Transparent mode, feed through selected clock source w/o dividing.</description>
13158                  <value>0</value>
13159                </enumeratedValue>
13160                <enumeratedValue>
13161                  <name>DIV_BY_2</name>
13162                  <description>Divide selected clock source by 2</description>
13163                  <value>1</value>
13164                </enumeratedValue>
13165                <enumeratedValue>
13166                  <name>DIV_BY_4</name>
13167                  <description>Divide selected clock source by 4</description>
13168                  <value>2</value>
13169                </enumeratedValue>
13170                <enumeratedValue>
13171                  <name>DIV_BY_8</name>
13172                  <description>Divide selected clock source by 8</description>
13173                  <value>3</value>
13174                </enumeratedValue>
13175                <enumeratedValue>
13176                  <name>DIV_BY_16</name>
13177                  <description>Divide selected clock source by 16</description>
13178                  <value>4</value>
13179                </enumeratedValue>
13180              </enumeratedValues>
13181            </field>
13182            <field>
13183              <name>PUMP_ENABLE</name>
13184              <description>Enable the pump clock.  PUMP_ENABLE and the PUMP_SEL mux are not glitch-free to minimize side-effects, avoid changing the PUMP_SEL and PUMP_DIV while changing PUMP_ENABLE.  To change the settings, do the following:
131851) If the pump clock is enabled, write PUMP_ENABLE=0 without changing PUMP_SEL and PUMP_DIV.
131862) Change PUMP_SEL and PUMP_DIV to desired settings with PUMP_ENABLE=0.
131873) Write PUMP_ENABLE=1 without changing PUMP_SEL and PUMP_DIV.</description>
13188              <bitRange>[15:15]</bitRange>
13189              <access>read-write</access>
13190            </field>
13191          </fields>
13192        </register>
13193        <register>
13194          <name>CLK_TIMER_CTL</name>
13195          <description>Timer Clock Control Register</description>
13196          <addressOffset>0x504</addressOffset>
13197          <size>32</size>
13198          <access>read-write</access>
13199          <resetValue>0x70000</resetValue>
13200          <resetMask>0x80FF0301</resetMask>
13201          <fields>
13202            <field>
13203              <name>TIMER_SEL</name>
13204              <description>Select source for TIMERCLK.  The output of this mux can be further divided using TIMER_DIV.</description>
13205              <bitRange>[0:0]</bitRange>
13206              <access>read-write</access>
13207              <enumeratedValues>
13208                <enumeratedValue>
13209                  <name>IMO</name>
13210                  <description>IMO - Internal Main Oscillator</description>
13211                  <value>0</value>
13212                </enumeratedValue>
13213                <enumeratedValue>
13214                  <name>HF0_DIV</name>
13215                  <description>Select the output of the predivider configured by TIMER_HF0_DIV.</description>
13216                  <value>1</value>
13217                </enumeratedValue>
13218              </enumeratedValues>
13219            </field>
13220            <field>
13221              <name>TIMER_HF0_DIV</name>
13222              <description>Predivider used when HF0_DIV is selected in TIMER_SEL.  If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV).  Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock.</description>
13223              <bitRange>[9:8]</bitRange>
13224              <access>read-write</access>
13225              <enumeratedValues>
13226                <enumeratedValue>
13227                  <name>NO_DIV</name>
13228                  <description>Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle.</description>
13229                  <value>0</value>
13230                </enumeratedValue>
13231                <enumeratedValue>
13232                  <name>DIV_BY_2</name>
13233                  <description>Divide HFCLK0 by 2.</description>
13234                  <value>1</value>
13235                </enumeratedValue>
13236                <enumeratedValue>
13237                  <name>DIV_BY_4</name>
13238                  <description>Divide HFCLK0 by 4.</description>
13239                  <value>2</value>
13240                </enumeratedValue>
13241                <enumeratedValue>
13242                  <name>DIV_BY_8</name>
13243                  <description>Divide HFCLK0 by 8.</description>
13244                  <value>3</value>
13245                </enumeratedValue>
13246              </enumeratedValues>
13247            </field>
13248            <field>
13249              <name>TIMER_DIV</name>
13250              <description>Divide selected timer clock source by (1+TIMER_DIV).  The output of this divider is TIMERCLK  Allows for integer divisions in the range [1, 256].  Do not change this setting while the timer is enabled.</description>
13251              <bitRange>[23:16]</bitRange>
13252              <access>read-write</access>
13253            </field>
13254            <field>
13255              <name>ENABLE</name>
13256              <description>Enable for TIMERCLK.
132570: TIMERCLK is off
132581: TIMERCLK is enabled</description>
13259              <bitRange>[31:31]</bitRange>
13260              <access>read-write</access>
13261            </field>
13262          </fields>
13263        </register>
13264        <register>
13265          <name>CLK_ILO_CONFIG</name>
13266          <description>ILO Configuration</description>
13267          <addressOffset>0x50C</addressOffset>
13268          <size>32</size>
13269          <access>read-write</access>
13270          <resetValue>0x80000000</resetValue>
13271          <resetMask>0x80000001</resetMask>
13272          <fields>
13273            <field>
13274              <name>ILO_BACKUP</name>
13275              <description>If backup domain is present on this product, this register indicates that ILO should stay enabled for use by backup domain during XRES, HIBERNATE mode, and through power-related resets like BOD on VDDD/VCCD.  Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.
132760: ILO turns off at XRES/BOD event or HIBERNATE entry.
132771: ILO remains on if backup domain is present and powered even for XRES/BOD or HIBERNATE entry.</description>
13278              <bitRange>[0:0]</bitRange>
13279              <access>read-write</access>
13280            </field>
13281            <field>
13282              <name>ENABLE</name>
13283              <description>Master enable for ILO.  Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register.  After enabling, it takes at most two cycles to reach the accuracy spec.</description>
13284              <bitRange>[31:31]</bitRange>
13285              <access>read-write</access>
13286            </field>
13287          </fields>
13288        </register>
13289        <register>
13290          <name>CLK_IMO_CONFIG</name>
13291          <description>IMO Configuration</description>
13292          <addressOffset>0x510</addressOffset>
13293          <size>32</size>
13294          <access>read-write</access>
13295          <resetValue>0x80000000</resetValue>
13296          <resetMask>0x80000000</resetMask>
13297          <fields>
13298            <field>
13299              <name>ENABLE</name>
13300              <description>Master enable for IMO oscillator.  This bit must be high at all times for all functions to work properly.  Hardware will automatically disable the IMO during HIBERNATE and XRES.  It will automatically disable during DEEPSLEEP if DPSLP_ENABLE==0.</description>
13301              <bitRange>[31:31]</bitRange>
13302              <access>read-write</access>
13303            </field>
13304          </fields>
13305        </register>
13306        <register>
13307          <name>CLK_OUTPUT_FAST</name>
13308          <description>Fast Clock Output Select Register</description>
13309          <addressOffset>0x514</addressOffset>
13310          <size>32</size>
13311          <access>read-write</access>
13312          <resetValue>0x0</resetValue>
13313          <resetMask>0xFFF0FFF</resetMask>
13314          <fields>
13315            <field>
13316              <name>FAST_SEL0</name>
13317              <description>Select signal for fast clock output #0</description>
13318              <bitRange>[3:0]</bitRange>
13319              <access>read-write</access>
13320              <enumeratedValues>
13321                <enumeratedValue>
13322                  <name>NC</name>
13323                  <description>Disabled - output is 0.  For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0.</description>
13324                  <value>0</value>
13325                </enumeratedValue>
13326                <enumeratedValue>
13327                  <name>ECO</name>
13328                  <description>External Crystal Oscillator (ECO)</description>
13329                  <value>1</value>
13330                </enumeratedValue>
13331                <enumeratedValue>
13332                  <name>EXTCLK</name>
13333                  <description>External clock input (EXTCLK)</description>
13334                  <value>2</value>
13335                </enumeratedValue>
13336                <enumeratedValue>
13337                  <name>ALTHF</name>
13338                  <description>Alternate High-Frequency (ALTHF) clock input to SRSS</description>
13339                  <value>3</value>
13340                </enumeratedValue>
13341                <enumeratedValue>
13342                  <name>TIMERCLK</name>
13343                  <description>Timer clock.  It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse.</description>
13344                  <value>4</value>
13345                </enumeratedValue>
13346                <enumeratedValue>
13347                  <name>PATH_SEL0</name>
13348                  <description>Selects the clock path chosen by PATH_SEL0 field</description>
13349                  <value>5</value>
13350                </enumeratedValue>
13351                <enumeratedValue>
13352                  <name>HFCLK_SEL0</name>
13353                  <description>Selects the output of the HFCLK_SEL0 mux</description>
13354                  <value>6</value>
13355                </enumeratedValue>
13356                <enumeratedValue>
13357                  <name>SLOW_SEL0</name>
13358                  <description>Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0</description>
13359                  <value>7</value>
13360                </enumeratedValue>
13361              </enumeratedValues>
13362            </field>
13363            <field>
13364              <name>PATH_SEL0</name>
13365              <description>Selects a clock path to use in fast clock output #0 logic.  0: FLL output
133661-15: PLL output on path1-path15 (if available)</description>
13367              <bitRange>[7:4]</bitRange>
13368              <access>read-write</access>
13369            </field>
13370            <field>
13371              <name>HFCLK_SEL0</name>
13372              <description>Selects a HFCLK tree for use in fast clock output #0</description>
13373              <bitRange>[11:8]</bitRange>
13374              <access>read-write</access>
13375            </field>
13376            <field>
13377              <name>FAST_SEL1</name>
13378              <description>Select signal for fast clock output #1</description>
13379              <bitRange>[19:16]</bitRange>
13380              <access>read-write</access>
13381              <enumeratedValues>
13382                <enumeratedValue>
13383                  <name>NC</name>
13384                  <description>Disabled - output is 0.  For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1.</description>
13385                  <value>0</value>
13386                </enumeratedValue>
13387                <enumeratedValue>
13388                  <name>ECO</name>
13389                  <description>External Crystal Oscillator (ECO)</description>
13390                  <value>1</value>
13391                </enumeratedValue>
13392                <enumeratedValue>
13393                  <name>EXTCLK</name>
13394                  <description>External clock input (EXTCLK)</description>
13395                  <value>2</value>
13396                </enumeratedValue>
13397                <enumeratedValue>
13398                  <name>ALTHF</name>
13399                  <description>Alternate High-Frequency (ALTHF) clock input to SRSS</description>
13400                  <value>3</value>
13401                </enumeratedValue>
13402                <enumeratedValue>
13403                  <name>TIMERCLK</name>
13404                  <description>Timer clock.  It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse.</description>
13405                  <value>4</value>
13406                </enumeratedValue>
13407                <enumeratedValue>
13408                  <name>PATH_SEL1</name>
13409                  <description>Selects the clock path chosen by PATH_SEL1 field</description>
13410                  <value>5</value>
13411                </enumeratedValue>
13412                <enumeratedValue>
13413                  <name>HFCLK_SEL1</name>
13414                  <description>Selects the output of the HFCLK_SEL1 mux</description>
13415                  <value>6</value>
13416                </enumeratedValue>
13417                <enumeratedValue>
13418                  <name>SLOW_SEL1</name>
13419                  <description>Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1</description>
13420                  <value>7</value>
13421                </enumeratedValue>
13422              </enumeratedValues>
13423            </field>
13424            <field>
13425              <name>PATH_SEL1</name>
13426              <description>Selects a clock path to use in fast clock output #1 logic.  0: FLL output
134271-15: PLL output on path1-path15 (if available)</description>
13428              <bitRange>[23:20]</bitRange>
13429              <access>read-write</access>
13430            </field>
13431            <field>
13432              <name>HFCLK_SEL1</name>
13433              <description>Selects a HFCLK tree for use in fast clock output #1 logic</description>
13434              <bitRange>[27:24]</bitRange>
13435              <access>read-write</access>
13436            </field>
13437          </fields>
13438        </register>
13439        <register>
13440          <name>CLK_OUTPUT_SLOW</name>
13441          <description>Slow Clock Output Select Register</description>
13442          <addressOffset>0x518</addressOffset>
13443          <size>32</size>
13444          <access>read-write</access>
13445          <resetValue>0x0</resetValue>
13446          <resetMask>0xFF</resetMask>
13447          <fields>
13448            <field>
13449              <name>SLOW_SEL0</name>
13450              <description>Select signal for slow clock output #0</description>
13451              <bitRange>[3:0]</bitRange>
13452              <access>read-write</access>
13453              <enumeratedValues>
13454                <enumeratedValue>
13455                  <name>NC</name>
13456                  <description>Disabled - output is 0.  For power savings, clocks are blocked before entering any muxes.</description>
13457                  <value>0</value>
13458                </enumeratedValue>
13459                <enumeratedValue>
13460                  <name>ILO</name>
13461                  <description>Internal Low Speed Oscillator (ILO)</description>
13462                  <value>1</value>
13463                </enumeratedValue>
13464                <enumeratedValue>
13465                  <name>WCO</name>
13466                  <description>Watch-Crystal Oscillator (WCO)</description>
13467                  <value>2</value>
13468                </enumeratedValue>
13469                <enumeratedValue>
13470                  <name>BAK</name>
13471                  <description>Root of the Backup domain clock tree (BAK)</description>
13472                  <value>3</value>
13473                </enumeratedValue>
13474                <enumeratedValue>
13475                  <name>ALTLF</name>
13476                  <description>Alternate low-frequency clock input to SRSS (ALTLF)</description>
13477                  <value>4</value>
13478                </enumeratedValue>
13479                <enumeratedValue>
13480                  <name>LFCLK</name>
13481                  <description>Root of the low-speed clock tree (LFCLK)</description>
13482                  <value>5</value>
13483                </enumeratedValue>
13484                <enumeratedValue>
13485                  <name>IMO</name>
13486                  <description>Internal Main Oscillator (IMO).  This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
13487                  <value>6</value>
13488                </enumeratedValue>
13489                <enumeratedValue>
13490                  <name>SLPCTRL</name>
13491                  <description>Sleep Controller clock (SLPCTRL).  This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
13492                  <value>7</value>
13493                </enumeratedValue>
13494                <enumeratedValue>
13495                  <name>PILO</name>
13496                  <description>Precision Internal Low Speed Oscillator (PILO)</description>
13497                  <value>8</value>
13498                </enumeratedValue>
13499              </enumeratedValues>
13500            </field>
13501            <field>
13502              <name>SLOW_SEL1</name>
13503              <description>Select signal for slow clock output #1</description>
13504              <bitRange>[7:4]</bitRange>
13505              <access>read-write</access>
13506              <enumeratedValues>
13507                <enumeratedValue>
13508                  <name>NC</name>
13509                  <description>Disabled - output is 0.  For power savings, clocks are blocked before entering any muxes.</description>
13510                  <value>0</value>
13511                </enumeratedValue>
13512                <enumeratedValue>
13513                  <name>ILO</name>
13514                  <description>Internal Low Speed Oscillator (ILO)</description>
13515                  <value>1</value>
13516                </enumeratedValue>
13517                <enumeratedValue>
13518                  <name>WCO</name>
13519                  <description>Watch-Crystal Oscillator (WCO)</description>
13520                  <value>2</value>
13521                </enumeratedValue>
13522                <enumeratedValue>
13523                  <name>BAK</name>
13524                  <description>Root of the Backup domain clock tree (BAK)</description>
13525                  <value>3</value>
13526                </enumeratedValue>
13527                <enumeratedValue>
13528                  <name>ALTLF</name>
13529                  <description>Alternate low-frequency clock input to SRSS (ALTLF)</description>
13530                  <value>4</value>
13531                </enumeratedValue>
13532                <enumeratedValue>
13533                  <name>LFCLK</name>
13534                  <description>Root of the low-speed clock tree (LFCLK)</description>
13535                  <value>5</value>
13536                </enumeratedValue>
13537                <enumeratedValue>
13538                  <name>IMO</name>
13539                  <description>Internal Main Oscillator (IMO).  This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
13540                  <value>6</value>
13541                </enumeratedValue>
13542                <enumeratedValue>
13543                  <name>SLPCTRL</name>
13544                  <description>Sleep Controller clock (SLPCTRL).  This is grouped with the slow clocks so it can be observed during DEEPSLEEP entry/exit.</description>
13545                  <value>7</value>
13546                </enumeratedValue>
13547                <enumeratedValue>
13548                  <name>PILO</name>
13549                  <description>Precision Internal Low Speed Oscillator (PILO)</description>
13550                  <value>8</value>
13551                </enumeratedValue>
13552              </enumeratedValues>
13553            </field>
13554          </fields>
13555        </register>
13556        <register>
13557          <name>CLK_CAL_CNT1</name>
13558          <description>Clock Calibration Counter 1</description>
13559          <addressOffset>0x51C</addressOffset>
13560          <size>32</size>
13561          <access>read-write</access>
13562          <resetValue>0x80000000</resetValue>
13563          <resetMask>0x80FFFFFF</resetMask>
13564          <fields>
13565            <field>
13566              <name>CAL_COUNTER1</name>
13567              <description>Down-counter clocked on fast clock output #0 (see CLK_OUTPUT_FAST). This register always reads as zero.  Counting starts internally when this register is written with a nonzero value.  CAL_COUNTER_DONE goes immediately low to indicate that the counter has started and will be asserted when the counters are done.  Do not write this field unless CAL_COUNTER_DONE==1.  Both clocks must be running or the measurement will not complete.  A stalled counter can be recovered by selecting valid clocks, waiting until the measurement completes, and discarding the first result.</description>
13568              <bitRange>[23:0]</bitRange>
13569              <access>read-write</access>
13570            </field>
13571            <field>
13572              <name>CAL_COUNTER_DONE</name>
13573              <description>Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up</description>
13574              <bitRange>[31:31]</bitRange>
13575              <access>read-only</access>
13576            </field>
13577          </fields>
13578        </register>
13579        <register>
13580          <name>CLK_CAL_CNT2</name>
13581          <description>Clock Calibration Counter 2</description>
13582          <addressOffset>0x520</addressOffset>
13583          <size>32</size>
13584          <access>read-only</access>
13585          <resetValue>0x0</resetValue>
13586          <resetMask>0xFFFFFF</resetMask>
13587          <fields>
13588            <field>
13589              <name>CAL_COUNTER2</name>
13590              <description>Up-counter clocked on fast clock output  #1 (see CLK_OUTPUT_FAST). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1, the counter is stopped and can be read by SW.  Do not read this value unless CAL_COUNTER_DONE==1.  The expected final value is related to the ratio of clock frequencies used for the two counters and the value loaded into counter 1: CLK_CAL_CNT2.COUNTER=(F_cnt2/F_cnt1)*(CLK_CAL_CNT1.COUNTER)</description>
13591              <bitRange>[23:0]</bitRange>
13592              <access>read-only</access>
13593            </field>
13594          </fields>
13595        </register>
13596        <register>
13597          <name>CLK_ECO_CONFIG</name>
13598          <description>ECO Configuration Register</description>
13599          <addressOffset>0x52C</addressOffset>
13600          <size>32</size>
13601          <access>read-write</access>
13602          <resetValue>0x2</resetValue>
13603          <resetMask>0x80000002</resetMask>
13604          <fields>
13605            <field>
13606              <name>AGC_EN</name>
13607              <description>Automatic Gain Control (AGC) enable.  When set, the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM.  When low, the amplitude is not explicitly controlled and can be as high as the vddd supply.  WARNING: use care when disabling AGC because driving a crystal beyond its rated limit can permanently damage the crystal.</description>
13608              <bitRange>[1:1]</bitRange>
13609              <access>read-write</access>
13610            </field>
13611            <field>
13612              <name>ECO_EN</name>
13613              <description>Master enable for ECO oscillator.</description>
13614              <bitRange>[31:31]</bitRange>
13615              <access>read-write</access>
13616            </field>
13617          </fields>
13618        </register>
13619        <register>
13620          <name>CLK_ECO_STATUS</name>
13621          <description>ECO Status Register</description>
13622          <addressOffset>0x530</addressOffset>
13623          <size>32</size>
13624          <access>read-only</access>
13625          <resetValue>0x0</resetValue>
13626          <resetMask>0x3</resetMask>
13627          <fields>
13628            <field>
13629              <name>ECO_OK</name>
13630              <description>Indicates the ECO internal oscillator circuit has sufficient amplitude.  It may not meet the PPM accuracy or duty cycle spec.</description>
13631              <bitRange>[0:0]</bitRange>
13632              <access>read-only</access>
13633            </field>
13634            <field>
13635              <name>ECO_READY</name>
13636              <description>Indicates the ECO internal oscillator circuit has had enough time to fully stabilize.  This is the output of a counter since ECO was enabled, and it does not check the ECO output.  It is recommended to also confirm ECO_OK==1.</description>
13637              <bitRange>[1:1]</bitRange>
13638              <access>read-only</access>
13639            </field>
13640          </fields>
13641        </register>
13642        <register>
13643          <name>CLK_PILO_CONFIG</name>
13644          <description>Precision ILO Configuration Register</description>
13645          <addressOffset>0x53C</addressOffset>
13646          <size>32</size>
13647          <access>read-write</access>
13648          <resetValue>0x80</resetValue>
13649          <resetMask>0xE00003FF</resetMask>
13650          <fields>
13651            <field>
13652              <name>PILO_FFREQ</name>
13653              <description>Fine frequency trim allowing +/-250ppm accuracy with periodic calibration.  The nominal step size of the LSB is 8Hz.</description>
13654              <bitRange>[9:0]</bitRange>
13655              <access>read-write</access>
13656            </field>
13657            <field>
13658              <name>PILO_CLK_EN</name>
13659              <description>Enable the PILO clock output.  See PILO_EN field for required sequencing.</description>
13660              <bitRange>[29:29]</bitRange>
13661              <access>read-write</access>
13662            </field>
13663            <field>
13664              <name>PILO_RESET_N</name>
13665              <description>Reset the PILO.  See PILO_EN field for required sequencing.</description>
13666              <bitRange>[30:30]</bitRange>
13667              <access>read-write</access>
13668            </field>
13669            <field>
13670              <name>PILO_EN</name>
13671              <description>Enable PILO.  When enabling PILO, set PILO_EN=1, wait 1ms, then PILO_RESET_N=1 and PILO_CLK_EN=1.  When disabling PILO, clear PILO_EN=0, PILO_RESET_N=0, and PLO_CLK_EN=0 in the same write cycle.</description>
13672              <bitRange>[31:31]</bitRange>
13673              <access>read-write</access>
13674            </field>
13675          </fields>
13676        </register>
13677        <register>
13678          <name>CLK_FLL_CONFIG</name>
13679          <description>FLL Configuration Register</description>
13680          <addressOffset>0x580</addressOffset>
13681          <size>32</size>
13682          <access>read-write</access>
13683          <resetValue>0x1000000</resetValue>
13684          <resetMask>0x8103FFFF</resetMask>
13685          <fields>
13686            <field>
13687              <name>FLL_MULT</name>
13688              <description>Multiplier to determine CCO frequency in multiples of the frequency of the selected reference clock (Fref).
13689
13690Ffll = (FLL_MULT)  * (Fref / REFERENCE_DIV) / (OUTPUT_DIV+1)</description>
13691              <bitRange>[17:0]</bitRange>
13692              <access>read-write</access>
13693            </field>
13694            <field>
13695              <name>FLL_OUTPUT_DIV</name>
13696              <description>Control bits for Output divider.  Set the divide value before enabling the FLL, and do not change it while FLL is enabled.
136970: no division
136981: divide by 2</description>
13699              <bitRange>[24:24]</bitRange>
13700              <access>read-write</access>
13701            </field>
13702            <field>
13703              <name>FLL_ENABLE</name>
13704              <description>Master enable for FLL.  The FLL requires firmware sequencing when enabling, disabling, and entering/exiting DEEPSLEEP.
13705
13706To enable the FLL, first enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=1 and wait until CLK_FLL_STATUS.CCO_READY==1.  Next, ensure the reference clock has stabilized and CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF.  Next, write FLL_ENABLE=1 and wait until CLK_FLL_STATUS.LOCKED==1.  Finally, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output.  It takes seven reference clock cycles plus four FLL output cycles to switch to the FLL output.  Do not disable the FLL before this time completes.
13707
13708To disable the FLL, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF and (optionally) read the same register to ensure the write completes.  Then, wait at least seven FLL reference clock cycles before disabling it with FLL_ENABLE=0.  Lastly, disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE=0.
13709
13710Before entering DEEPSLEEP, either disable the FLL using above sequence or use the following procedure to deselect/select it before/after DEEPSLEEP.  Before entering DEEPSLEEP, write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_REF to change the FLL to use its reference clock.  After DEEPSLEEP wakeup, wait until CLK_FLL_STATUS.LOCKED==1 and then write CLK_FLL_CONFIG3.BYPASS_SEL=FLL_OUT to switch to the FLL output.
13711
137120: Block is powered off
137131: Block is powered on</description>
13714              <bitRange>[31:31]</bitRange>
13715              <access>read-write</access>
13716            </field>
13717          </fields>
13718        </register>
13719        <register>
13720          <name>CLK_FLL_CONFIG2</name>
13721          <description>FLL Configuration Register 2</description>
13722          <addressOffset>0x584</addressOffset>
13723          <size>32</size>
13724          <access>read-write</access>
13725          <resetValue>0x20001</resetValue>
13726          <resetMask>0x1FF1FFF</resetMask>
13727          <fields>
13728            <field>
13729              <name>FLL_REF_DIV</name>
13730              <description>Control bits for reference divider.  Set the divide value before enabling the FLL, and do not change it while FLL is enabled.
137310: illegal (undefined behavior)
137321: divide by 1
13733...
137348191: divide by 8191</description>
13735              <bitRange>[12:0]</bitRange>
13736              <access>read-write</access>
13737            </field>
13738            <field>
13739              <name>LOCK_TOL</name>
13740              <description>Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input.  A high tolerance can be used to lock more quickly or to track a less accurate source.  The tolerance should be set so that the FLL does not unlock under normal conditions.  The tolerance is the allowed difference between the count value for the ideal formula and the measured value.
137410: tolerate error of 1 count value
137421: tolerate error of 2 count values
13743...
13744511: tolerate error of 512 count values</description>
13745              <bitRange>[24:16]</bitRange>
13746              <access>read-write</access>
13747            </field>
13748          </fields>
13749        </register>
13750        <register>
13751          <name>CLK_FLL_CONFIG3</name>
13752          <description>FLL Configuration Register 3</description>
13753          <addressOffset>0x588</addressOffset>
13754          <size>32</size>
13755          <access>read-write</access>
13756          <resetValue>0x2800</resetValue>
13757          <resetMask>0x301FFFFF</resetMask>
13758          <fields>
13759            <field>
13760              <name>FLL_LF_IGAIN</name>
13761              <description>FLL Loop Filter Gain Setting #1.  The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN.
137620: 1/256
137631: 1/128
137642: 1/64
137653: 1/32
137664: 1/16
137675: 1/8
137686: 1/4
137697: 1/2
137708: 1.0
137719: 2.0
1377210: 4.0
1377311: 8.0
13774&gt;=12: illegal</description>
13775              <bitRange>[3:0]</bitRange>
13776              <access>read-write</access>
13777            </field>
13778            <field>
13779              <name>FLL_LF_PGAIN</name>
13780              <description>FLL Loop Filter Gain Setting #2.  The proportional gain is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN.
137810: 1/256
137821: 1/128
137832: 1/64
137843: 1/32
137854: 1/16
137865: 1/8
137876: 1/4
137887: 1/2
137898: 1.0
137909: 2.0
1379110: 4.0
1379211: 8.0
13793&gt;=12: illegal</description>
13794              <bitRange>[7:4]</bitRange>
13795              <access>read-write</access>
13796            </field>
13797            <field>
13798              <name>SETTLING_COUNT</name>
13799              <description>Number of undivided reference clock cycles to wait after changing the CCO trim until the loop measurement restarts.  A delay allows the CCO output to settle and gives a more accurate measurement.  The default is tuned to an 8MHz reference clock since the IMO is expected to be the most common use case.
138000: no settling time
138011: wait one reference clock cycle
13802...
138038191: wait 8191 reference clock cycles</description>
13804              <bitRange>[20:8]</bitRange>
13805              <access>read-write</access>
13806            </field>
13807            <field>
13808              <name>BYPASS_SEL</name>
13809              <description>Bypass mux located just after FLL output.  See FLL_ENABLE description for instructions on how to use this field when enabling/disabling the FLL.</description>
13810              <bitRange>[29:28]</bitRange>
13811              <access>read-write</access>
13812              <enumeratedValues>
13813                <enumeratedValue>
13814                  <name>AUTO</name>
13815                  <description>N/A</description>
13816                  <value>0</value>
13817                </enumeratedValue>
13818                <enumeratedValue>
13819                  <name>AUTO1</name>
13820                  <description>N/A</description>
13821                  <value>1</value>
13822                </enumeratedValue>
13823                <enumeratedValue>
13824                  <name>FLL_REF</name>
13825                  <description>Select FLL reference input (bypass mode).  Ignores lock indicator</description>
13826                  <value>2</value>
13827                </enumeratedValue>
13828                <enumeratedValue>
13829                  <name>FLL_OUT</name>
13830                  <description>Select FLL output.  Ignores lock indicator.</description>
13831                  <value>3</value>
13832                </enumeratedValue>
13833              </enumeratedValues>
13834            </field>
13835          </fields>
13836        </register>
13837        <register>
13838          <name>CLK_FLL_CONFIG4</name>
13839          <description>FLL Configuration Register 4</description>
13840          <addressOffset>0x58C</addressOffset>
13841          <size>32</size>
13842          <access>read-write</access>
13843          <resetValue>0xFF</resetValue>
13844          <resetMask>0xC1FF07FF</resetMask>
13845          <fields>
13846            <field>
13847              <name>CCO_LIMIT</name>
13848              <description>Maximum CCO offset allowed (used to prevent FLL dynamics from selecting an CCO frequency that the logic cannot support)</description>
13849              <bitRange>[7:0]</bitRange>
13850              <access>read-write</access>
13851            </field>
13852            <field>
13853              <name>CCO_RANGE</name>
13854              <description>Frequency range of CCO</description>
13855              <bitRange>[10:8]</bitRange>
13856              <access>read-write</access>
13857              <enumeratedValues>
13858                <enumeratedValue>
13859                  <name>RANGE0</name>
13860                  <description>Target frequency is in range [48, 64) MHz</description>
13861                  <value>0</value>
13862                </enumeratedValue>
13863                <enumeratedValue>
13864                  <name>RANGE1</name>
13865                  <description>Target frequency is in range [64, 85) MHz</description>
13866                  <value>1</value>
13867                </enumeratedValue>
13868                <enumeratedValue>
13869                  <name>RANGE2</name>
13870                  <description>Target frequency is in range [85, 113) MHz</description>
13871                  <value>2</value>
13872                </enumeratedValue>
13873                <enumeratedValue>
13874                  <name>RANGE3</name>
13875                  <description>Target frequency is in range [113, 150) MHz</description>
13876                  <value>3</value>
13877                </enumeratedValue>
13878                <enumeratedValue>
13879                  <name>RANGE4</name>
13880                  <description>Target frequency is in range [150, 200] MHz</description>
13881                  <value>4</value>
13882                </enumeratedValue>
13883              </enumeratedValues>
13884            </field>
13885            <field>
13886              <name>CCO_FREQ</name>
13887              <description>CCO frequency code.  This is updated by HW when the FLL is enabled.  It can be manually updated to use the CCO in an open loop configuration.  The meaning of each frequency code depends on the range.</description>
13888              <bitRange>[24:16]</bitRange>
13889              <access>read-write</access>
13890            </field>
13891            <field>
13892              <name>CCO_HW_UPDATE_DIS</name>
13893              <description>Disable CCO frequency update by FLL hardware
138940: Hardware update of CCO settings is allowed.  Use this setting for normal FLL operation.
138951: Hardware update of CCO settings is disabled.  Use this setting for open-loop FLL operation.</description>
13896              <bitRange>[30:30]</bitRange>
13897              <access>read-write</access>
13898            </field>
13899            <field>
13900              <name>CCO_ENABLE</name>
13901              <description>Enable the CCO.  It is required to enable the CCO before using the FLL.
139020: Block is powered off
139031: Block is powered on</description>
13904              <bitRange>[31:31]</bitRange>
13905              <access>read-write</access>
13906            </field>
13907          </fields>
13908        </register>
13909        <register>
13910          <name>CLK_FLL_STATUS</name>
13911          <description>FLL Status Register</description>
13912          <addressOffset>0x590</addressOffset>
13913          <size>32</size>
13914          <access>read-write</access>
13915          <resetValue>0x0</resetValue>
13916          <resetMask>0x7</resetMask>
13917          <fields>
13918            <field>
13919              <name>LOCKED</name>
13920              <description>FLL Lock Indicator.  LOCKED is high when FLL is within CLK_FLL_CONFIG2.LOCK_TOL.  If FLL is outside LOCK_TOL, LOCKED goes low.  Note that this can happen during normal operation, if FLL needs to recalculate due to a change in the reference clock, change in voltage, or change in temperature.</description>
13921              <bitRange>[0:0]</bitRange>
13922              <access>read-only</access>
13923            </field>
13924            <field>
13925              <name>UNLOCK_OCCURRED</name>
13926              <description>N/A</description>
13927              <bitRange>[1:1]</bitRange>
13928              <access>read-write</access>
13929            </field>
13930            <field>
13931              <name>CCO_READY</name>
13932              <description>This indicates that the CCO is internally settled and ready to use.</description>
13933              <bitRange>[2:2]</bitRange>
13934              <access>read-only</access>
13935            </field>
13936          </fields>
13937        </register>
13938        <register>
13939          <dim>15</dim>
13940          <dimIncrement>4</dimIncrement>
13941          <name>CLK_PLL_CONFIG[%s]</name>
13942          <description>PLL Configuration Register</description>
13943          <addressOffset>0x600</addressOffset>
13944          <size>32</size>
13945          <access>read-write</access>
13946          <resetValue>0x20116</resetValue>
13947          <resetMask>0xB81F1F7F</resetMask>
13948          <fields>
13949            <field>
13950              <name>FEEDBACK_DIV</name>
13951              <description>Control bits for feedback divider.  Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
139520-21: illegal (undefined behavior)
1395322: divide by 22
13954...
13955112: divide by 112
13956&gt;112: illegal (undefined behavior)</description>
13957              <bitRange>[6:0]</bitRange>
13958              <access>read-write</access>
13959            </field>
13960            <field>
13961              <name>REFERENCE_DIV</name>
13962              <description>Control bits for reference divider.  Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
139630: illegal (undefined behavior)
139641: divide by 1
13965...
1396620: divide by 20
13967others: illegal (undefined behavior)</description>
13968              <bitRange>[12:8]</bitRange>
13969              <access>read-write</access>
13970            </field>
13971            <field>
13972              <name>OUTPUT_DIV</name>
13973              <description>Control bits for Output divider.  Set the divide value before enabling the PLL, and do not change it while PLL is enabled.
139740: illegal (undefined behavior)
139751: illegal (undefined behavior)
139762: divide by 2.  Suitable for direct usage as HFCLK source.
13977...
1397816: divide by 16.  Suitable for direct usage as HFCLK source.
13979&gt;16: illegal (undefined behavior)</description>
13980              <bitRange>[20:16]</bitRange>
13981              <access>read-write</access>
13982            </field>
13983            <field>
13984              <name>PLL_LF_MODE</name>
13985              <description>VCO frequency range selection.  Configure this bit according to the targeted VCO frequency.  Do not change this setting while the PLL is enabled.
139860: VCO frequency is [200MHz, 400MHz]
139871: VCO frequency is [170MHz, 200MHz)</description>
13988              <bitRange>[27:27]</bitRange>
13989              <access>read-write</access>
13990            </field>
13991            <field>
13992              <name>BYPASS_SEL</name>
13993              <description>Bypass mux located just after PLL output.  This selection is glitch-free and can be changed while the PLL is running.</description>
13994              <bitRange>[29:28]</bitRange>
13995              <access>read-write</access>
13996              <enumeratedValues>
13997                <enumeratedValue>
13998                  <name>AUTO</name>
13999                  <description>Automatic using lock indicator.  When unlocked, automatically selects PLL reference input (bypass mode).  When locked, automatically selects PLL output.</description>
14000                  <value>0</value>
14001                </enumeratedValue>
14002                <enumeratedValue>
14003                  <name>AUTO1</name>
14004                  <description>Same as AUTO</description>
14005                  <value>1</value>
14006                </enumeratedValue>
14007                <enumeratedValue>
14008                  <name>PLL_REF</name>
14009                  <description>Select PLL reference input (bypass mode).  Ignores lock indicator</description>
14010                  <value>2</value>
14011                </enumeratedValue>
14012                <enumeratedValue>
14013                  <name>PLL_OUT</name>
14014                  <description>Select PLL output.  Ignores lock indicator.</description>
14015                  <value>3</value>
14016                </enumeratedValue>
14017              </enumeratedValues>
14018            </field>
14019            <field>
14020              <name>ENABLE</name>
14021              <description>Master enable for PLL.  Setup FEEDBACK_DIV, REFERENCE_DIV, and OUTPUT_DIV at least one cycle before setting ENABLE=1.  To disable the PLL, first deselect it using .BYPASS_SEL=PLL_REF, wait at least six PLL clock cycles, and then disable it with .ENABLE=0.
14022
14023Fpll = (FEEDBACK_DIV)  * (Fref / REFERENCE_DIV) / (OUTPUT_DIV)
14024
140250: Block is disabled
140261: Block is enabled</description>
14027              <bitRange>[31:31]</bitRange>
14028              <access>read-write</access>
14029            </field>
14030          </fields>
14031        </register>
14032        <register>
14033          <dim>15</dim>
14034          <dimIncrement>4</dimIncrement>
14035          <name>CLK_PLL_STATUS[%s]</name>
14036          <description>PLL Status Register</description>
14037          <addressOffset>0x640</addressOffset>
14038          <size>32</size>
14039          <access>read-write</access>
14040          <resetValue>0x0</resetValue>
14041          <resetMask>0x3</resetMask>
14042          <fields>
14043            <field>
14044              <name>LOCKED</name>
14045              <description>PLL Lock Indicator</description>
14046              <bitRange>[0:0]</bitRange>
14047              <access>read-only</access>
14048            </field>
14049            <field>
14050              <name>UNLOCK_OCCURRED</name>
14051              <description>This bit sets whenever the PLL Lock bit goes low, and stays set until cleared by firmware.</description>
14052              <bitRange>[1:1]</bitRange>
14053              <access>read-write</access>
14054            </field>
14055          </fields>
14056        </register>
14057        <register>
14058          <name>SRSS_INTR</name>
14059          <description>SRSS Interrupt Register</description>
14060          <addressOffset>0x700</addressOffset>
14061          <size>32</size>
14062          <access>read-write</access>
14063          <resetValue>0x0</resetValue>
14064          <resetMask>0x23</resetMask>
14065          <fields>
14066            <field>
14067              <name>WDT_MATCH</name>
14068              <description>WDT Interrupt Request.  This bit is set each time WDT_COUNTR==WDT_MATCH.  W1C also feeds the watch dog.  Missing 2 interrupts in a row will generate a reset.  Due to internal synchronization, it takes 2 SYSCLK cycles to update after a W1C.</description>
14069              <bitRange>[0:0]</bitRange>
14070              <access>read-write</access>
14071            </field>
14072            <field>
14073              <name>HVLVD1</name>
14074              <description>Interrupt for low voltage detector HVLVD1</description>
14075              <bitRange>[1:1]</bitRange>
14076              <access>read-write</access>
14077            </field>
14078            <field>
14079              <name>CLK_CAL</name>
14080              <description>Clock calibration counter is done.  This field is reset during DEEPSLEEP mode.</description>
14081              <bitRange>[5:5]</bitRange>
14082              <access>read-write</access>
14083            </field>
14084          </fields>
14085        </register>
14086        <register>
14087          <name>SRSS_INTR_SET</name>
14088          <description>SRSS Interrupt Set Register</description>
14089          <addressOffset>0x704</addressOffset>
14090          <size>32</size>
14091          <access>read-write</access>
14092          <resetValue>0x0</resetValue>
14093          <resetMask>0x23</resetMask>
14094          <fields>
14095            <field>
14096              <name>WDT_MATCH</name>
14097              <description>Set interrupt for low voltage detector WDT_MATCH</description>
14098              <bitRange>[0:0]</bitRange>
14099              <access>read-write</access>
14100            </field>
14101            <field>
14102              <name>HVLVD1</name>
14103              <description>Set interrupt for low voltage detector HVLVD1</description>
14104              <bitRange>[1:1]</bitRange>
14105              <access>read-write</access>
14106            </field>
14107            <field>
14108              <name>CLK_CAL</name>
14109              <description>Set interrupt for clock calibration counter done.  This field is reset during DEEPSLEEP mode.</description>
14110              <bitRange>[5:5]</bitRange>
14111              <access>read-write</access>
14112            </field>
14113          </fields>
14114        </register>
14115        <register>
14116          <name>SRSS_INTR_MASK</name>
14117          <description>SRSS Interrupt Mask Register</description>
14118          <addressOffset>0x708</addressOffset>
14119          <size>32</size>
14120          <access>read-write</access>
14121          <resetValue>0x0</resetValue>
14122          <resetMask>0x23</resetMask>
14123          <fields>
14124            <field>
14125              <name>WDT_MATCH</name>
14126              <description>Mask for watchdog timer.  Clearing this bit will not forward the interrupt to the CPU.  It will not, however, disable the WDT reset generation on 2 missed interrupts.  When WDT resets the chip, it also internally pends an interrupt that survives the reset.  To prevent unintended ISR execution, clear SRSS_INTR.WDT_MATCH before setting this bit.</description>
14127              <bitRange>[0:0]</bitRange>
14128              <access>read-write</access>
14129            </field>
14130            <field>
14131              <name>HVLVD1</name>
14132              <description>Mask for low voltage detector HVLVD1</description>
14133              <bitRange>[1:1]</bitRange>
14134              <access>read-write</access>
14135            </field>
14136            <field>
14137              <name>CLK_CAL</name>
14138              <description>Mask for clock calibration done</description>
14139              <bitRange>[5:5]</bitRange>
14140              <access>read-write</access>
14141            </field>
14142          </fields>
14143        </register>
14144        <register>
14145          <name>SRSS_INTR_MASKED</name>
14146          <description>SRSS Interrupt Masked Register</description>
14147          <addressOffset>0x70C</addressOffset>
14148          <size>32</size>
14149          <access>read-only</access>
14150          <resetValue>0x0</resetValue>
14151          <resetMask>0x23</resetMask>
14152          <fields>
14153            <field>
14154              <name>WDT_MATCH</name>
14155              <description>Logical and of corresponding request and mask bits.</description>
14156              <bitRange>[0:0]</bitRange>
14157              <access>read-only</access>
14158            </field>
14159            <field>
14160              <name>HVLVD1</name>
14161              <description>Logical and of corresponding request and mask bits.</description>
14162              <bitRange>[1:1]</bitRange>
14163              <access>read-only</access>
14164            </field>
14165            <field>
14166              <name>CLK_CAL</name>
14167              <description>Logical and of corresponding request and mask bits.</description>
14168              <bitRange>[5:5]</bitRange>
14169              <access>read-only</access>
14170            </field>
14171          </fields>
14172        </register>
14173        <register>
14174          <name>SRSS_INTR_CFG</name>
14175          <description>SRSS Interrupt Configuration Register</description>
14176          <addressOffset>0x710</addressOffset>
14177          <size>32</size>
14178          <access>read-write</access>
14179          <resetValue>0x0</resetValue>
14180          <resetMask>0x3</resetMask>
14181          <fields>
14182            <field>
14183              <name>HVLVD1_EDGE_SEL</name>
14184              <description>Sets which edge(s) will trigger an IRQ for HVLVD1</description>
14185              <bitRange>[1:0]</bitRange>
14186              <access>read-write</access>
14187              <enumeratedValues>
14188                <enumeratedValue>
14189                  <name>DISABLE</name>
14190                  <description>Disabled</description>
14191                  <value>0</value>
14192                </enumeratedValue>
14193                <enumeratedValue>
14194                  <name>RISING</name>
14195                  <description>Rising edge</description>
14196                  <value>1</value>
14197                </enumeratedValue>
14198                <enumeratedValue>
14199                  <name>FALLING</name>
14200                  <description>Falling edge</description>
14201                  <value>2</value>
14202                </enumeratedValue>
14203                <enumeratedValue>
14204                  <name>BOTH</name>
14205                  <description>Both rising and falling edges</description>
14206                  <value>3</value>
14207                </enumeratedValue>
14208              </enumeratedValues>
14209            </field>
14210          </fields>
14211        </register>
14212        <register>
14213          <name>RES_CAUSE</name>
14214          <description>Reset Cause Observation Register</description>
14215          <addressOffset>0x800</addressOffset>
14216          <size>32</size>
14217          <access>read-write</access>
14218          <resetValue>0x0</resetValue>
14219          <resetMask>0x1FF</resetMask>
14220          <fields>
14221            <field>
14222              <name>RESET_WDT</name>
14223              <description>A basic WatchDog Timer (WDT) reset has occurred since last power cycle.</description>
14224              <bitRange>[0:0]</bitRange>
14225              <access>read-write</access>
14226            </field>
14227            <field>
14228              <name>RESET_ACT_FAULT</name>
14229              <description>Fault logging system requested a reset from its Active logic.</description>
14230              <bitRange>[1:1]</bitRange>
14231              <access>read-write</access>
14232            </field>
14233            <field>
14234              <name>RESET_DPSLP_FAULT</name>
14235              <description>Fault logging system requested a reset from its DeepSleep logic.</description>
14236              <bitRange>[2:2]</bitRange>
14237              <access>read-write</access>
14238            </field>
14239            <field>
14240              <name>RESET_CSV_WCO_LOSS</name>
14241              <description>Clock supervision logic requested a reset due to loss of a watch-crystal clock.</description>
14242              <bitRange>[3:3]</bitRange>
14243              <access>read-write</access>
14244            </field>
14245            <field>
14246              <name>RESET_SOFT</name>
14247              <description>A CPU requested a system reset through it's SYSRESETREQ.  This can be done via a debugger probe or in firmware.</description>
14248              <bitRange>[4:4]</bitRange>
14249              <access>read-write</access>
14250            </field>
14251            <field>
14252              <name>RESET_MCWDT0</name>
14253              <description>Multi-Counter Watchdog timer reset #0 has occurred since last power cycle.</description>
14254              <bitRange>[5:5]</bitRange>
14255              <access>read-write</access>
14256            </field>
14257            <field>
14258              <name>RESET_MCWDT1</name>
14259              <description>Multi-Counter Watchdog timer reset #1 has occurred since last power cycle.</description>
14260              <bitRange>[6:6]</bitRange>
14261              <access>read-write</access>
14262            </field>
14263            <field>
14264              <name>RESET_MCWDT2</name>
14265              <description>Multi-Counter Watchdog timer reset #2 has occurred since last power cycle.</description>
14266              <bitRange>[7:7]</bitRange>
14267              <access>read-write</access>
14268            </field>
14269            <field>
14270              <name>RESET_MCWDT3</name>
14271              <description>Multi-Counter Watchdog timer reset #3 has occurred since last power cycle.</description>
14272              <bitRange>[8:8]</bitRange>
14273              <access>read-write</access>
14274            </field>
14275          </fields>
14276        </register>
14277        <register>
14278          <name>RES_CAUSE2</name>
14279          <description>Reset Cause Observation Register 2</description>
14280          <addressOffset>0x804</addressOffset>
14281          <size>32</size>
14282          <access>read-write</access>
14283          <resetValue>0x0</resetValue>
14284          <resetMask>0xFFFFFFFF</resetMask>
14285          <fields>
14286            <field>
14287              <name>RESET_CSV_HF_LOSS</name>
14288              <description>Clock supervision logic requested a reset due to loss of a high-frequency clock.  Each bit index K corresponds to a HFCLK&lt;K&gt;.  Unimplemented clock bits return zero.</description>
14289              <bitRange>[15:0]</bitRange>
14290              <access>read-write</access>
14291            </field>
14292            <field>
14293              <name>RESET_CSV_HF_FREQ</name>
14294              <description>Clock supervision logic requested a reset due to frequency error of high-frequency clock.  Each bit index K corresponds to a HFCLK&lt;K&gt;.  Unimplemented clock bits return zero.</description>
14295              <bitRange>[31:16]</bitRange>
14296              <access>read-write</access>
14297            </field>
14298          </fields>
14299        </register>
14300        <register>
14301          <name>PWR_TRIM_REF_CTL</name>
14302          <description>Reference Trim Register</description>
14303          <addressOffset>0x7F00</addressOffset>
14304          <size>32</size>
14305          <access>read-write</access>
14306          <resetValue>0x70F00000</resetValue>
14307          <resetMask>0xF1FF5FFF</resetMask>
14308          <fields>
14309            <field>
14310              <name>ACT_REF_TCTRIM</name>
14311              <description>Active-Reference temperature trim.  This register is only reset by XRES/POR/BOD/HIBERNATE.
143120 -&gt; default setting at POR; not for trimming use
14313others -&gt; normal trim range</description>
14314              <bitRange>[3:0]</bitRange>
14315              <access>read-write</access>
14316            </field>
14317            <field>
14318              <name>ACT_REF_ITRIM</name>
14319              <description>Active-Reference current trim.   This register is only reset by XRES/POR/BOD/HIBERNATE.
143200 -&gt; default setting at POR; not for trimming use
14321others -&gt; normal trim range</description>
14322              <bitRange>[7:4]</bitRange>
14323              <access>read-write</access>
14324            </field>
14325            <field>
14326              <name>ACT_REF_ABSTRIM</name>
14327              <description>Active-Reference absolute voltage trim.  This register is only reset by XRES/POR/BOD/HIBERNATE.
143280 -&gt; default setting at POR; not for trimming use
14329others -&gt; normal trim range</description>
14330              <bitRange>[12:8]</bitRange>
14331              <access>read-write</access>
14332            </field>
14333            <field>
14334              <name>ACT_REF_IBOOST</name>
14335              <description>Active-Reference current boost.   This register is only reset by XRES/POR/BOD/HIBERNATE.
143360: normal operation
14337others: risk mitigation</description>
14338              <bitRange>[14:14]</bitRange>
14339              <access>read-write</access>
14340            </field>
14341            <field>
14342              <name>DPSLP_REF_TCTRIM</name>
14343              <description>DeepSleep-Reference temperature trim.  This register is only reset by XRES/POR/BOD/HIBERNATE.
143440 -&gt; default setting at POR; not for trimming use
14345others -&gt; normal trim range</description>
14346              <bitRange>[19:16]</bitRange>
14347              <access>read-write</access>
14348            </field>
14349            <field>
14350              <name>DPSLP_REF_ABSTRIM</name>
14351              <description>DeepSleep-Reference absolute voltage trim.  This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
14352              <bitRange>[24:20]</bitRange>
14353              <access>read-write</access>
14354            </field>
14355            <field>
14356              <name>DPSLP_REF_ITRIM</name>
14357              <description>DeepSleep current reference trim.   This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
14358              <bitRange>[31:28]</bitRange>
14359              <access>read-write</access>
14360            </field>
14361          </fields>
14362        </register>
14363        <register>
14364          <name>PWR_TRIM_BODOVP_CTL</name>
14365          <description>BOD/OVP Trim Register</description>
14366          <addressOffset>0x7F04</addressOffset>
14367          <size>32</size>
14368          <access>read-write</access>
14369          <resetValue>0x40D04</resetValue>
14370          <resetMask>0xFDFF7</resetMask>
14371          <fields>
14372            <field>
14373              <name>HVPORBOD_TRIPSEL</name>
14374              <description>HVPORBOD trip point selection.  Monitors vddd.  This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
14375              <bitRange>[2:0]</bitRange>
14376              <access>read-write</access>
14377            </field>
14378            <field>
14379              <name>HVPORBOD_OFSTRIM</name>
14380              <description>HVPORBOD offset trim.  This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
14381              <bitRange>[6:4]</bitRange>
14382              <access>read-write</access>
14383            </field>
14384            <field>
14385              <name>HVPORBOD_ITRIM</name>
14386              <description>HVPORBOD current trim.  This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
14387              <bitRange>[9:7]</bitRange>
14388              <access>read-write</access>
14389            </field>
14390            <field>
14391              <name>LVPORBOD_TRIPSEL</name>
14392              <description>LVPORBOD trip point selection.  Monitors vccd.  This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
14393              <bitRange>[12:10]</bitRange>
14394              <access>read-write</access>
14395            </field>
14396            <field>
14397              <name>LVPORBOD_OFSTRIM</name>
14398              <description>LVPORBOD offset trim.  This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
14399              <bitRange>[16:14]</bitRange>
14400              <access>read-write</access>
14401            </field>
14402            <field>
14403              <name>LVPORBOD_ITRIM</name>
14404              <description>LVPORBOD current trim.  This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
14405              <bitRange>[19:17]</bitRange>
14406              <access>read-write</access>
14407            </field>
14408          </fields>
14409        </register>
14410        <register>
14411          <name>CLK_TRIM_CCO_CTL</name>
14412          <description>CCO Trim Register</description>
14413          <addressOffset>0x7F08</addressOffset>
14414          <size>32</size>
14415          <access>read-write</access>
14416          <resetValue>0xA7000020</resetValue>
14417          <resetMask>0xBF00003F</resetMask>
14418          <fields>
14419            <field>
14420              <name>CCO_RCSTRIM</name>
14421              <description>CCO reference current source trim.</description>
14422              <bitRange>[5:0]</bitRange>
14423              <access>read-write</access>
14424            </field>
14425            <field>
14426              <name>CCO_STABLE_CNT</name>
14427              <description>Terminal count for the stabilization counter from CCO_ENABLE until stable.</description>
14428              <bitRange>[29:24]</bitRange>
14429              <access>read-write</access>
14430            </field>
14431            <field>
14432              <name>ENABLE_CNT</name>
14433              <description>Enables the automatic stabilization counter.</description>
14434              <bitRange>[31:31]</bitRange>
14435              <access>read-write</access>
14436            </field>
14437          </fields>
14438        </register>
14439        <register>
14440          <name>CLK_TRIM_CCO_CTL2</name>
14441          <description>CCO Trim Register 2</description>
14442          <addressOffset>0x7F0C</addressOffset>
14443          <size>32</size>
14444          <access>read-write</access>
14445          <resetValue>0x884110</resetValue>
14446          <resetMask>0x1FFFFFF</resetMask>
14447          <fields>
14448            <field>
14449              <name>CCO_FCTRIM1</name>
14450              <description>CCO frequency 1st range calibration</description>
14451              <bitRange>[4:0]</bitRange>
14452              <access>read-write</access>
14453            </field>
14454            <field>
14455              <name>CCO_FCTRIM2</name>
14456              <description>CCO frequency 2nd range calibration</description>
14457              <bitRange>[9:5]</bitRange>
14458              <access>read-write</access>
14459            </field>
14460            <field>
14461              <name>CCO_FCTRIM3</name>
14462              <description>CCO frequency 3rd range calibration</description>
14463              <bitRange>[14:10]</bitRange>
14464              <access>read-write</access>
14465            </field>
14466            <field>
14467              <name>CCO_FCTRIM4</name>
14468              <description>CCO frequency 4th range calibration</description>
14469              <bitRange>[19:15]</bitRange>
14470              <access>read-write</access>
14471            </field>
14472            <field>
14473              <name>CCO_FCTRIM5</name>
14474              <description>CCO frequency 5th range calibration</description>
14475              <bitRange>[24:20]</bitRange>
14476              <access>read-write</access>
14477            </field>
14478          </fields>
14479        </register>
14480        <register>
14481          <name>PWR_TRIM_WAKE_CTL</name>
14482          <description>Wakeup Trim Register</description>
14483          <addressOffset>0x7F30</addressOffset>
14484          <size>32</size>
14485          <access>read-write</access>
14486          <resetValue>0x0</resetValue>
14487          <resetMask>0xFF</resetMask>
14488          <fields>
14489            <field>
14490              <name>WAKE_DELAY</name>
14491              <description>Wakeup holdoff.  Spec (fastest) wake time is achieved with a setting of 0.  Additional delay can be added for debugging or workaround.  The delay is counted by the IMO.</description>
14492              <bitRange>[7:0]</bitRange>
14493              <access>read-write</access>
14494            </field>
14495          </fields>
14496        </register>
14497        <register>
14498          <name>PWR_TRIM_LVD_CTL</name>
14499          <description>LVD Trim Register</description>
14500          <addressOffset>0xFF10</addressOffset>
14501          <size>32</size>
14502          <access>read-write</access>
14503          <resetValue>0x20</resetValue>
14504          <resetMask>0x77</resetMask>
14505          <fields>
14506            <field>
14507              <name>HVLVD1_OFSTRIM</name>
14508              <description>HVLVD1 offset trim</description>
14509              <bitRange>[2:0]</bitRange>
14510              <access>read-write</access>
14511            </field>
14512            <field>
14513              <name>HVLVD1_ITRIM</name>
14514              <description>HVLVD1 current trim</description>
14515              <bitRange>[6:4]</bitRange>
14516              <access>read-write</access>
14517            </field>
14518          </fields>
14519        </register>
14520        <register>
14521          <name>CLK_TRIM_ILO_CTL</name>
14522          <description>ILO Trim Register</description>
14523          <addressOffset>0xFF18</addressOffset>
14524          <size>32</size>
14525          <access>read-write</access>
14526          <resetValue>0x2C</resetValue>
14527          <resetMask>0x3F</resetMask>
14528          <fields>
14529            <field>
14530              <name>ILO_FTRIM</name>
14531              <description>ILO frequency trims.  LSB step size is 1.5 percent (typical) of the frequency.</description>
14532              <bitRange>[5:0]</bitRange>
14533              <access>read-write</access>
14534            </field>
14535          </fields>
14536        </register>
14537        <register>
14538          <name>PWR_TRIM_PWRSYS_CTL</name>
14539          <description>Power System Trim Register</description>
14540          <addressOffset>0xFF1C</addressOffset>
14541          <size>32</size>
14542          <access>read-write</access>
14543          <resetValue>0x17</resetValue>
14544          <resetMask>0x1F</resetMask>
14545          <fields>
14546            <field>
14547              <name>ACT_REG_TRIM</name>
14548              <description>Trim for the Active-Regulator.  This sets the output voltage level.  This register is only reset by XRES/POR/BOD/HIBERNATE.  Two voltages are supported: 0.9V and 1.1V.  The codes for these are stored in SFLASH_LDO_0P9V_TRIM and SFLASH_LDO_1P1V_TRIM, respectively.</description>
14549              <bitRange>[4:0]</bitRange>
14550              <access>read-write</access>
14551            </field>
14552            <field>
14553              <name>ACT_REG_BOOST</name>
14554              <description>Controls the tradeoff between output current and internal operating current for the Active Regulator.  The maximum output current depends on the silicon implementation, but an application may limit its maximum current to less than that.  This may allow a reduction in the internal operating current of the regulator.  The regulator internal operating current depends on the boost setting:
145552'b00: 50uA
145562'b01: 100uA
145572'b10: 150uA
145582'b11: 200uA
14559
14560The allowed setting is a lookup table based on the chip-specific maximum (set in factory) and an application-specific maximum (set by customer).  The defaults are set assuming the application consumes the maximum allowed by the chip.
1456150mA chip: 2'b00 (default);
14562100mA chip: 2'b00 (default);
14563150mA chip: 50..100mA app =&gt; 2'b00, 150mA app =&gt; 2'b01 (default);
14564200mA chip: 50mA app =&gt; 2'b00, 100..150mA app =&gt; 2'b01,  200mA app =&gt; 2'b10 (default);
14565250mA chip: 50mA app =&gt; 2'b00, 100..150mA app =&gt; 2'b01,  200..250mA app =&gt; 2'b10 (default);
14566300mA chip: 50mA app =&gt; 2'b00, 100..150mA app =&gt; 2'b01, 200..250mA app =&gt; 2'b10, 300mA app =&gt; 2'b11 (default);
14567
14568This register is only reset by XRES/POR/BOD/HIBERNATE.</description>
14569              <bitRange>[31:30]</bitRange>
14570              <access>read-write</access>
14571            </field>
14572          </fields>
14573        </register>
14574        <register>
14575          <name>CLK_TRIM_ECO_CTL</name>
14576          <description>ECO Trim Register</description>
14577          <addressOffset>0xFF20</addressOffset>
14578          <size>32</size>
14579          <access>read-write</access>
14580          <resetValue>0x1F0003</resetValue>
14581          <resetMask>0x3F3FF7</resetMask>
14582          <fields>
14583            <field>
14584              <name>WDTRIM</name>
14585              <description>Watch Dog Trim -  Delta voltage below steady state level
145860x0 - 50mV
145870x1 - 75mV
145880x2 - 100mV
145890x3 - 125mV
145900x4 - 150mV
145910x5 - 175mV
145920x6 - 200mV
145930x7 - 225mV</description>
14594              <bitRange>[2:0]</bitRange>
14595              <access>read-write</access>
14596            </field>
14597            <field>
14598              <name>ATRIM</name>
14599              <description>Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1.  WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal.
146000x0 - 150mV
146010x1 - 175mV
146020x2 - 200mV
146030x3 - 225mV
146040x4 - 250mV
146050x5 - 275mV
146060x6 - 300mV
146070x7 - 325mV
146080x8 - 350mV
146090x9 - 375mV
146100xA - 400mV
146110xB - 425mV
146120xC - 450mV
146130xD - 475mV
146140xE - 500mV
146150xF - 525mV</description>
14616              <bitRange>[7:4]</bitRange>
14617              <access>read-write</access>
14618            </field>
14619            <field>
14620              <name>FTRIM</name>
14621              <description>Filter Trim - 3rd harmonic oscillation</description>
14622              <bitRange>[9:8]</bitRange>
14623              <access>read-write</access>
14624            </field>
14625            <field>
14626              <name>RTRIM</name>
14627              <description>Feedback resistor Trim</description>
14628              <bitRange>[11:10]</bitRange>
14629              <access>read-write</access>
14630            </field>
14631            <field>
14632              <name>GTRIM</name>
14633              <description>Gain Trim - Startup time</description>
14634              <bitRange>[13:12]</bitRange>
14635              <access>read-write</access>
14636            </field>
14637            <field>
14638              <name>ITRIM</name>
14639              <description>Current Trim</description>
14640              <bitRange>[21:16]</bitRange>
14641              <access>read-write</access>
14642            </field>
14643          </fields>
14644        </register>
14645        <register>
14646          <name>CLK_TRIM_PILO_CTL</name>
14647          <description>PILO Trim Register</description>
14648          <addressOffset>0xFF24</addressOffset>
14649          <size>32</size>
14650          <access>read-write</access>
14651          <resetValue>0x108500F</resetValue>
14652          <resetMask>0x7DFF703F</resetMask>
14653          <fields>
14654            <field>
14655              <name>PILO_CFREQ</name>
14656              <description>Coarse frequency trim to meet 32.768kHz +/-2 percent across PVT without calibration.  The nominal step size of the LSB is 1kHz.</description>
14657              <bitRange>[5:0]</bitRange>
14658              <access>read-write</access>
14659            </field>
14660            <field>
14661              <name>PILO_OSC_TRIM</name>
14662              <description>Trim for current in oscillator block.</description>
14663              <bitRange>[14:12]</bitRange>
14664              <access>read-write</access>
14665            </field>
14666            <field>
14667              <name>PILO_COMP_TRIM</name>
14668              <description>Trim for comparator bias current.</description>
14669              <bitRange>[17:16]</bitRange>
14670              <access>read-write</access>
14671            </field>
14672            <field>
14673              <name>PILO_NBIAS_TRIM</name>
14674              <description>Trim for biasn by trimming sub-Vth NMOS width in beta-multiplier</description>
14675              <bitRange>[19:18]</bitRange>
14676              <access>read-write</access>
14677            </field>
14678            <field>
14679              <name>PILO_RES_TRIM</name>
14680              <description>Trim for beta-multiplier branch current</description>
14681              <bitRange>[24:20]</bitRange>
14682              <access>read-write</access>
14683            </field>
14684            <field>
14685              <name>PILO_ISLOPE_TRIM</name>
14686              <description>Trim for beta-multiplier current slope</description>
14687              <bitRange>[27:26]</bitRange>
14688              <access>read-write</access>
14689            </field>
14690            <field>
14691              <name>PILO_VTDIFF_TRIM</name>
14692              <description>Trim for VT-DIFF output (internal power supply)</description>
14693              <bitRange>[30:28]</bitRange>
14694              <access>read-write</access>
14695            </field>
14696          </fields>
14697        </register>
14698        <register>
14699          <name>CLK_TRIM_PILO_CTL2</name>
14700          <description>PILO Trim Register 2</description>
14701          <addressOffset>0xFF28</addressOffset>
14702          <size>32</size>
14703          <access>read-write</access>
14704          <resetValue>0xDA10E0</resetValue>
14705          <resetMask>0xFF1FFF</resetMask>
14706          <fields>
14707            <field>
14708              <name>PILO_VREF_TRIM</name>
14709              <description>Trim for voltage reference</description>
14710              <bitRange>[7:0]</bitRange>
14711              <access>read-write</access>
14712            </field>
14713            <field>
14714              <name>PILO_IREFBM_TRIM</name>
14715              <description>Trim for beta-multiplier current reference</description>
14716              <bitRange>[12:8]</bitRange>
14717              <access>read-write</access>
14718            </field>
14719            <field>
14720              <name>PILO_IREF_TRIM</name>
14721              <description>Trim for current reference</description>
14722              <bitRange>[23:16]</bitRange>
14723              <access>read-write</access>
14724            </field>
14725          </fields>
14726        </register>
14727        <register>
14728          <name>CLK_TRIM_PILO_CTL3</name>
14729          <description>PILO Trim Register 3</description>
14730          <addressOffset>0xFF2C</addressOffset>
14731          <size>32</size>
14732          <access>read-write</access>
14733          <resetValue>0x4800</resetValue>
14734          <resetMask>0xFFFF</resetMask>
14735          <fields>
14736            <field>
14737              <name>PILO_ENGOPT</name>
14738              <description>Engineering options for PILO circuits
147390: Short vdda to vpwr
147401: Beta:mult current change
147412: Iref generation Ptat current addition
147423: Disable current path in secondary Beta:mult startup circuit
147434: Double oscillator current
147445: Switch between deep:sub:threshold and sub:threshold stacks in Vref generation block
147456: Spare
147467: Ptat component increase in Iref
147478: vpwr_rc and vpwr_dig_rc shorting testmode
147489: Switch b/w psub connection for cascode nfet for vref generation
1474910: Switch between sub:threshold and deep:sub:threshold stacks in comparator.
1475015-11: Frequency fine trim.  See AKK-444 for an overview of the trim strategy.</description>
14751              <bitRange>[15:0]</bitRange>
14752              <access>read-write</access>
14753            </field>
14754          </fields>
14755        </register>
14756      </registers>
14757    </peripheral>
14758    <peripheral>
14759      <name>BACKUP</name>
14760      <description>SRSS Backup Domain</description>
14761      <baseAddress>0x40270000</baseAddress>
14762      <addressBlock>
14763        <offset>0</offset>
14764        <size>65536</size>
14765        <usage>registers</usage>
14766      </addressBlock>
14767      <registers>
14768        <register>
14769          <name>CTL</name>
14770          <description>Control</description>
14771          <addressOffset>0x0</addressOffset>
14772          <size>32</size>
14773          <access>read-write</access>
14774          <resetValue>0x0</resetValue>
14775          <resetMask>0xFF0F3308</resetMask>
14776          <fields>
14777            <field>
14778              <name>WCO_EN</name>
14779              <description>Watch-crystal oscillator (WCO) enable.  If there is a write in progress when this bit is cleared, the WCO will be internally kept on until the write completes.
14780After enabling the WCO software must wait until STATUS.WCO_OK=1 before configuring any component that depends on clk_lf/clk_bak, like for example RTC or WDTs.  Follow the procedure in BACKUP_RTC_RW to access this bit.</description>
14781              <bitRange>[3:3]</bitRange>
14782              <access>read-write</access>
14783            </field>
14784            <field>
14785              <name>CLK_SEL</name>
14786              <description>Clock select for BAK clock</description>
14787              <bitRange>[9:8]</bitRange>
14788              <access>read-write</access>
14789              <enumeratedValues>
14790                <enumeratedValue>
14791                  <name>WCO</name>
14792                  <description>Watch-crystal oscillator input.</description>
14793                  <value>0</value>
14794                </enumeratedValue>
14795                <enumeratedValue>
14796                  <name>ALTBAK</name>
14797                  <description>This allows to use the LFCLK selection as an alternate backup domain clock.  Note that LFCLK is not available in all power modes, and clock glitches can propagate into the backup logic when the clock is stopped.  For this reason, if the WCO is intended as the clock source then choose it directly instead of routing through LFCLK.</description>
14798                  <value>1</value>
14799                </enumeratedValue>
14800              </enumeratedValues>
14801            </field>
14802            <field>
14803              <name>PRESCALER</name>
14804              <description>N/A</description>
14805              <bitRange>[13:12]</bitRange>
14806              <access>read-write</access>
14807            </field>
14808            <field>
14809              <name>WCO_BYPASS</name>
14810              <description>Configures the WCO for different board-level connections to the WCO pins.  For example, this can be used to connect an external watch crystal oscillator instead of a watch crystal.   In all cases, the two related GPIO pins (WCO input and output pins) must be configured as analog connections using GPIO registers, and they must be hooked at the board level as described below.  Configure this field before enabling the WCO, and do not change this setting when WCO_EN=1.
148110: Watch crystal.  Connect a 32.768 kHz watch crystal between WCO input and output pins.
148121: Clock signal, either a square wave or sine wave.  See PRESCALER field for connection information.</description>
14813              <bitRange>[16:16]</bitRange>
14814              <access>read-write</access>
14815            </field>
14816            <field>
14817              <name>VDDBAK_CTL</name>
14818              <description>Controls the behavior of the switch that generates vddbak from vbackup or vddd.
148190: automatically select vddd if its brownout detector says it is valid.  If the brownout says its not valid, then use vmax which is the highest of vddd or vbackup.
148201,2,3: force vddbak and vmax to select vbackup, regardless of its voltage.</description>
14821              <bitRange>[18:17]</bitRange>
14822              <access>read-write</access>
14823            </field>
14824            <field>
14825              <name>VBACKUP_MEAS</name>
14826              <description>Connect vbackup supply to the vbackup_meas output for measurement by an ADC attached to amuxbusa_adft_vddd.  The vbackup_meas signal is scaled to 10 percent of vbackup, so it is within the supply range of the ADC.</description>
14827              <bitRange>[19:19]</bitRange>
14828              <access>read-write</access>
14829            </field>
14830            <field>
14831              <name>EN_CHARGE_KEY</name>
14832              <description>When set to 3C, the supercap charger circuit is enabled.  Any other code disables the supercap charger.  THIS CHARGING CIRCUIT IS FOR A SUPERCAP ONLY AND CANNOT SAFELY CHARGE A BATTERY.  DO NOT WRITE THIS KEY WHEN VBACKUP IS CONNECTED TO A BATTERY.</description>
14833              <bitRange>[31:24]</bitRange>
14834              <access>read-write</access>
14835            </field>
14836          </fields>
14837        </register>
14838        <register>
14839          <name>RTC_RW</name>
14840          <description>RTC Read Write register</description>
14841          <addressOffset>0x8</addressOffset>
14842          <size>32</size>
14843          <access>read-write</access>
14844          <resetValue>0x0</resetValue>
14845          <resetMask>0x3</resetMask>
14846          <fields>
14847            <field>
14848              <name>READ</name>
14849              <description>Read bit
14850When this bit is set the RTC registers will be copied to user registers and frozen so that a coherent RTC value can safely be read. The RTC will keep on running.
14851Do not set the read bit if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Write bit is set. Do not set the Read bit at the same time that the Write bit is cleared.</description>
14852              <bitRange>[0:0]</bitRange>
14853              <access>read-write</access>
14854            </field>
14855            <field>
14856              <name>WRITE</name>
14857              <description>Write bit
14858Only when this bit is set can the RTC registers be written to (otherwise writes are ignored). This bit cannot be set if the RTC is still busy with a previous update (see RTC_BUSY bit) or if the Read bit is set or getting set.
14859The user writes to the RTC user registers, when the Write bit is cleared by the user then the user registers content is copied to the actual RTC registers.
14860Only user RTC registers that were written to will get copied, others will not be affected.
14861When the SECONDS field is updated then TICKS will also be reset (WDT is not affected).
14862When the Write bit is cleared by a reset (brown out/DeepSleep) then the RTC update will be ignored/lost.
14863Do not set the Write bit if the RTC if the RTC is still busy with a previous update (see RTC_BUSY).  Do not set the Write bit at the same time that the Read bit is cleared.</description>
14864              <bitRange>[1:1]</bitRange>
14865              <access>read-write</access>
14866            </field>
14867          </fields>
14868        </register>
14869        <register>
14870          <name>CAL_CTL</name>
14871          <description>Oscillator calibration for absolute frequency</description>
14872          <addressOffset>0xC</addressOffset>
14873          <size>32</size>
14874          <access>read-write</access>
14875          <resetValue>0x0</resetValue>
14876          <resetMask>0x8000007F</resetMask>
14877          <fields>
14878            <field>
14879              <name>CALIB_VAL</name>
14880              <description>Calibration value for absolute frequency (at a fixed temperature).  Each step causes 128 ticks to be added or removed each hour.  Effectively that means that each step is 1.085ppm (= 128/(60*60*32,768)).
14881Positive values 0x01-0x3c (1..60) add pulses, negative values remove pulses, thus giving a range of +/-65.1 ppm (limited by 60 minutes per hour, not the range of this field)
14882
14883Calibration is performed hourly, starting at 59 minutes and 59 seconds, and applied as 64 ticks every 30 seconds until there have been 2*CALIB_VAL adjustments.</description>
14884              <bitRange>[5:0]</bitRange>
14885              <access>read-write</access>
14886            </field>
14887            <field>
14888              <name>CALIB_SIGN</name>
14889              <description>Calibration sign:
148900= Negative sign: remove pulses (it takes more clock ticks to count one second)
148911= Positive sign: add pulses (it takes less clock ticks to count one second)</description>
14892              <bitRange>[6:6]</bitRange>
14893              <access>read-write</access>
14894            </field>
14895            <field>
14896              <name>CAL_OUT</name>
14897              <description>Output enable for 512Hz signal for calibration and allow CALIB_VAL to be written. Note that calibration does not affect the 512Hz output signal.</description>
14898              <bitRange>[31:31]</bitRange>
14899              <access>read-write</access>
14900            </field>
14901          </fields>
14902        </register>
14903        <register>
14904          <name>STATUS</name>
14905          <description>Status</description>
14906          <addressOffset>0x10</addressOffset>
14907          <size>32</size>
14908          <access>read-only</access>
14909          <resetValue>0x0</resetValue>
14910          <resetMask>0x5</resetMask>
14911          <fields>
14912            <field>
14913              <name>RTC_BUSY</name>
14914              <description>pending RTC write</description>
14915              <bitRange>[0:0]</bitRange>
14916              <access>read-only</access>
14917            </field>
14918            <field>
14919              <name>WCO_OK</name>
14920              <description>Indicates that output has transitioned.</description>
14921              <bitRange>[2:2]</bitRange>
14922              <access>read-only</access>
14923            </field>
14924          </fields>
14925        </register>
14926        <register>
14927          <name>RTC_TIME</name>
14928          <description>Calendar Seconds, Minutes, Hours, Day of Week</description>
14929          <addressOffset>0x14</addressOffset>
14930          <size>32</size>
14931          <access>read-write</access>
14932          <resetValue>0x0</resetValue>
14933          <resetMask>0x77F7F7F</resetMask>
14934          <fields>
14935            <field>
14936              <name>RTC_SEC</name>
14937              <description>Calendar seconds in BCD, 0-59</description>
14938              <bitRange>[6:0]</bitRange>
14939              <access>read-write</access>
14940            </field>
14941            <field>
14942              <name>RTC_MIN</name>
14943              <description>Calendar minutes in BCD, 0-59</description>
14944              <bitRange>[14:8]</bitRange>
14945              <access>read-write</access>
14946            </field>
14947            <field>
14948              <name>RTC_HOUR</name>
14949              <description>Calendar hours in BCD, value depending on 12/24HR mode
149500=24HR: [21:16]=0-23
149511=12HR: [21]:0=AM, 1=PM, [20:16]=1-12</description>
14952              <bitRange>[21:16]</bitRange>
14953              <access>read-write</access>
14954            </field>
14955            <field>
14956              <name>CTRL_12HR</name>
14957              <description>Select 12/24HR mode: 1=12HR, 0=24HR</description>
14958              <bitRange>[22:22]</bitRange>
14959              <access>read-write</access>
14960            </field>
14961            <field>
14962              <name>RTC_DAY</name>
14963              <description>Calendar Day of the week in BCD, 1-7
14964It is up to the user to define the meaning of the values, but 1=Monday is recommended</description>
14965              <bitRange>[26:24]</bitRange>
14966              <access>read-write</access>
14967            </field>
14968          </fields>
14969        </register>
14970        <register>
14971          <name>RTC_DATE</name>
14972          <description>Calendar Day of Month, Month,  Year</description>
14973          <addressOffset>0x18</addressOffset>
14974          <size>32</size>
14975          <access>read-write</access>
14976          <resetValue>0x0</resetValue>
14977          <resetMask>0xFF1F3F</resetMask>
14978          <fields>
14979            <field>
14980              <name>RTC_DATE</name>
14981              <description>Calendar Day of the Month in BCD, 1-31
14982Automatic Leap Year Correction</description>
14983              <bitRange>[5:0]</bitRange>
14984              <access>read-write</access>
14985            </field>
14986            <field>
14987              <name>RTC_MON</name>
14988              <description>Calendar Month in BCD, 1-12</description>
14989              <bitRange>[12:8]</bitRange>
14990              <access>read-write</access>
14991            </field>
14992            <field>
14993              <name>RTC_YEAR</name>
14994              <description>Calendar year in BCD, 0-99</description>
14995              <bitRange>[23:16]</bitRange>
14996              <access>read-write</access>
14997            </field>
14998          </fields>
14999        </register>
15000        <register>
15001          <name>ALM1_TIME</name>
15002          <description>Alarm 1 Seconds, Minute, Hours, Day of Week</description>
15003          <addressOffset>0x1C</addressOffset>
15004          <size>32</size>
15005          <access>read-write</access>
15006          <resetValue>0x1000000</resetValue>
15007          <resetMask>0x87BFFFFF</resetMask>
15008          <fields>
15009            <field>
15010              <name>ALM_SEC</name>
15011              <description>Alarm seconds in BCD, 0-59</description>
15012              <bitRange>[6:0]</bitRange>
15013              <access>read-write</access>
15014            </field>
15015            <field>
15016              <name>ALM_SEC_EN</name>
15017              <description>Alarm second enable: 0=ignore, 1=match</description>
15018              <bitRange>[7:7]</bitRange>
15019              <access>read-write</access>
15020            </field>
15021            <field>
15022              <name>ALM_MIN</name>
15023              <description>Alarm minutes in BCD, 0-59</description>
15024              <bitRange>[14:8]</bitRange>
15025              <access>read-write</access>
15026            </field>
15027            <field>
15028              <name>ALM_MIN_EN</name>
15029              <description>Alarm minutes enable: 0=ignore, 1=match</description>
15030              <bitRange>[15:15]</bitRange>
15031              <access>read-write</access>
15032            </field>
15033            <field>
15034              <name>ALM_HOUR</name>
15035              <description>Alarm hours in BCD, value depending on 12/24HR mode
1503612HR: [5]:0=AM, 1=PM, [4:0]=1-12
1503724HR: [5:0]=0-23</description>
15038              <bitRange>[21:16]</bitRange>
15039              <access>read-write</access>
15040            </field>
15041            <field>
15042              <name>ALM_HOUR_EN</name>
15043              <description>Alarm hour enable: 0=ignore, 1=match</description>
15044              <bitRange>[23:23]</bitRange>
15045              <access>read-write</access>
15046            </field>
15047            <field>
15048              <name>ALM_DAY</name>
15049              <description>Alarm Day of the week in BCD, 1-7
15050It is up to the user to define the meaning of the values, but 1=Monday is recommended</description>
15051              <bitRange>[26:24]</bitRange>
15052              <access>read-write</access>
15053            </field>
15054            <field>
15055              <name>ALM_DAY_EN</name>
15056              <description>Alarm Day of the Week enable: 0=ignore, 1=match</description>
15057              <bitRange>[31:31]</bitRange>
15058              <access>read-write</access>
15059            </field>
15060          </fields>
15061        </register>
15062        <register>
15063          <name>ALM1_DATE</name>
15064          <description>Alarm 1 Day of Month, Month</description>
15065          <addressOffset>0x20</addressOffset>
15066          <size>32</size>
15067          <access>read-write</access>
15068          <resetValue>0x101</resetValue>
15069          <resetMask>0x80009FBF</resetMask>
15070          <fields>
15071            <field>
15072              <name>ALM_DATE</name>
15073              <description>Alarm Day of the Month in BCD, 1-31
15074Leap Year corrected</description>
15075              <bitRange>[5:0]</bitRange>
15076              <access>read-write</access>
15077            </field>
15078            <field>
15079              <name>ALM_DATE_EN</name>
15080              <description>Alarm Day of the Month enable: 0=ignore, 1=match</description>
15081              <bitRange>[7:7]</bitRange>
15082              <access>read-write</access>
15083            </field>
15084            <field>
15085              <name>ALM_MON</name>
15086              <description>Alarm Month in BCD, 1-12</description>
15087              <bitRange>[12:8]</bitRange>
15088              <access>read-write</access>
15089            </field>
15090            <field>
15091              <name>ALM_MON_EN</name>
15092              <description>Alarm Month enable: 0=ignore, 1=match</description>
15093              <bitRange>[15:15]</bitRange>
15094              <access>read-write</access>
15095            </field>
15096            <field>
15097              <name>ALM_EN</name>
15098              <description>Master enable for alarm 1.
150990: Alarm 1 is disabled.  Fields for date and time are ignored.
151001: Alarm 1 is enabled.  Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration.  If none of the date and time fields are enabled, then this alarm triggers once every second.</description>
15101              <bitRange>[31:31]</bitRange>
15102              <access>read-write</access>
15103            </field>
15104          </fields>
15105        </register>
15106        <register>
15107          <name>ALM2_TIME</name>
15108          <description>Alarm 2 Seconds, Minute, Hours, Day of Week</description>
15109          <addressOffset>0x24</addressOffset>
15110          <size>32</size>
15111          <access>read-write</access>
15112          <resetValue>0x1000000</resetValue>
15113          <resetMask>0x87BFFFFF</resetMask>
15114          <fields>
15115            <field>
15116              <name>ALM_SEC</name>
15117              <description>Alarm seconds in BCD, 0-59</description>
15118              <bitRange>[6:0]</bitRange>
15119              <access>read-write</access>
15120            </field>
15121            <field>
15122              <name>ALM_SEC_EN</name>
15123              <description>Alarm second enable: 0=ignore, 1=match</description>
15124              <bitRange>[7:7]</bitRange>
15125              <access>read-write</access>
15126            </field>
15127            <field>
15128              <name>ALM_MIN</name>
15129              <description>Alarm minutes in BCD, 0-59</description>
15130              <bitRange>[14:8]</bitRange>
15131              <access>read-write</access>
15132            </field>
15133            <field>
15134              <name>ALM_MIN_EN</name>
15135              <description>Alarm minutes enable: 0=ignore, 1=match</description>
15136              <bitRange>[15:15]</bitRange>
15137              <access>read-write</access>
15138            </field>
15139            <field>
15140              <name>ALM_HOUR</name>
15141              <description>Alarm hours in BCD, value depending on 12/24HR mode
1514212HR: [5]:0=AM, 1=PM, [4:0]=1-12
1514324HR: [5:0]=0-23</description>
15144              <bitRange>[21:16]</bitRange>
15145              <access>read-write</access>
15146            </field>
15147            <field>
15148              <name>ALM_HOUR_EN</name>
15149              <description>Alarm hour enable: 0=ignore, 1=match</description>
15150              <bitRange>[23:23]</bitRange>
15151              <access>read-write</access>
15152            </field>
15153            <field>
15154              <name>ALM_DAY</name>
15155              <description>Alarm Day of the week in BCD, 1-7
15156It is up to the user to define the meaning of the values, but 1=Monday is recommended</description>
15157              <bitRange>[26:24]</bitRange>
15158              <access>read-write</access>
15159            </field>
15160            <field>
15161              <name>ALM_DAY_EN</name>
15162              <description>Alarm Day of the Week enable: 0=ignore, 1=match</description>
15163              <bitRange>[31:31]</bitRange>
15164              <access>read-write</access>
15165            </field>
15166          </fields>
15167        </register>
15168        <register>
15169          <name>ALM2_DATE</name>
15170          <description>Alarm 2 Day of Month, Month</description>
15171          <addressOffset>0x28</addressOffset>
15172          <size>32</size>
15173          <access>read-write</access>
15174          <resetValue>0x101</resetValue>
15175          <resetMask>0x80009FBF</resetMask>
15176          <fields>
15177            <field>
15178              <name>ALM_DATE</name>
15179              <description>Alarm Day of the Month in BCD, 1-31
15180Leap Year corrected</description>
15181              <bitRange>[5:0]</bitRange>
15182              <access>read-write</access>
15183            </field>
15184            <field>
15185              <name>ALM_DATE_EN</name>
15186              <description>Alarm Day of the Month enable: 0=ignore, 1=match</description>
15187              <bitRange>[7:7]</bitRange>
15188              <access>read-write</access>
15189            </field>
15190            <field>
15191              <name>ALM_MON</name>
15192              <description>Alarm Month in BCD, 1-12</description>
15193              <bitRange>[12:8]</bitRange>
15194              <access>read-write</access>
15195            </field>
15196            <field>
15197              <name>ALM_MON_EN</name>
15198              <description>Alarm Month enable: 0=ignore, 1=match</description>
15199              <bitRange>[15:15]</bitRange>
15200              <access>read-write</access>
15201            </field>
15202            <field>
15203              <name>ALM_EN</name>
15204              <description>Master enable for alarm 2.
152050: Alarm 2 is disabled.  Fields for date and time are ignored.
152061: Alarm 2 is enabled.  Alarm triggers whenever the new date and time matches all the enabled date and time fields, which can happen more than once depending on configuration.  If none of the date and time fields are enabled, then this alarm triggers once every second.</description>
15207              <bitRange>[31:31]</bitRange>
15208              <access>read-write</access>
15209            </field>
15210          </fields>
15211        </register>
15212        <register>
15213          <name>INTR</name>
15214          <description>Interrupt request register</description>
15215          <addressOffset>0x2C</addressOffset>
15216          <size>32</size>
15217          <access>read-write</access>
15218          <resetValue>0x0</resetValue>
15219          <resetMask>0x7</resetMask>
15220          <fields>
15221            <field>
15222              <name>ALARM1</name>
15223              <description>Alarm 1 Interrupt</description>
15224              <bitRange>[0:0]</bitRange>
15225              <access>read-write</access>
15226            </field>
15227            <field>
15228              <name>ALARM2</name>
15229              <description>Alarm 2 Interrupt</description>
15230              <bitRange>[1:1]</bitRange>
15231              <access>read-write</access>
15232            </field>
15233            <field>
15234              <name>CENTURY</name>
15235              <description>Century overflow interrupt</description>
15236              <bitRange>[2:2]</bitRange>
15237              <access>read-write</access>
15238            </field>
15239          </fields>
15240        </register>
15241        <register>
15242          <name>INTR_SET</name>
15243          <description>Interrupt set request register</description>
15244          <addressOffset>0x30</addressOffset>
15245          <size>32</size>
15246          <access>read-write</access>
15247          <resetValue>0x0</resetValue>
15248          <resetMask>0x7</resetMask>
15249          <fields>
15250            <field>
15251              <name>ALARM1</name>
15252              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
15253              <bitRange>[0:0]</bitRange>
15254              <access>read-write</access>
15255            </field>
15256            <field>
15257              <name>ALARM2</name>
15258              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
15259              <bitRange>[1:1]</bitRange>
15260              <access>read-write</access>
15261            </field>
15262            <field>
15263              <name>CENTURY</name>
15264              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
15265              <bitRange>[2:2]</bitRange>
15266              <access>read-write</access>
15267            </field>
15268          </fields>
15269        </register>
15270        <register>
15271          <name>INTR_MASK</name>
15272          <description>Interrupt mask register</description>
15273          <addressOffset>0x34</addressOffset>
15274          <size>32</size>
15275          <access>read-write</access>
15276          <resetValue>0x0</resetValue>
15277          <resetMask>0x7</resetMask>
15278          <fields>
15279            <field>
15280              <name>ALARM1</name>
15281              <description>Mask bit for corresponding bit in interrupt request register.</description>
15282              <bitRange>[0:0]</bitRange>
15283              <access>read-write</access>
15284            </field>
15285            <field>
15286              <name>ALARM2</name>
15287              <description>Mask bit for corresponding bit in interrupt request register.</description>
15288              <bitRange>[1:1]</bitRange>
15289              <access>read-write</access>
15290            </field>
15291            <field>
15292              <name>CENTURY</name>
15293              <description>Mask bit for corresponding bit in interrupt request register.</description>
15294              <bitRange>[2:2]</bitRange>
15295              <access>read-write</access>
15296            </field>
15297          </fields>
15298        </register>
15299        <register>
15300          <name>INTR_MASKED</name>
15301          <description>Interrupt masked request register</description>
15302          <addressOffset>0x38</addressOffset>
15303          <size>32</size>
15304          <access>read-only</access>
15305          <resetValue>0x0</resetValue>
15306          <resetMask>0x7</resetMask>
15307          <fields>
15308            <field>
15309              <name>ALARM1</name>
15310              <description>Logical and of corresponding request and mask bits.</description>
15311              <bitRange>[0:0]</bitRange>
15312              <access>read-only</access>
15313            </field>
15314            <field>
15315              <name>ALARM2</name>
15316              <description>Logical and of corresponding request and mask bits.</description>
15317              <bitRange>[1:1]</bitRange>
15318              <access>read-only</access>
15319            </field>
15320            <field>
15321              <name>CENTURY</name>
15322              <description>Logical and of corresponding request and mask bits.</description>
15323              <bitRange>[2:2]</bitRange>
15324              <access>read-only</access>
15325            </field>
15326          </fields>
15327        </register>
15328        <register>
15329          <name>OSCCNT</name>
15330          <description>32kHz oscillator counter</description>
15331          <addressOffset>0x3C</addressOffset>
15332          <size>32</size>
15333          <access>read-only</access>
15334          <resetValue>0x0</resetValue>
15335          <resetMask>0xFF</resetMask>
15336          <fields>
15337            <field>
15338              <name>CNT32KHZ</name>
15339              <description>32kHz oscillator count (msb=128Hz), calibration can cause bit 6 to skip.  Reset when RTC_TIME.RTC_SEC fields is written.</description>
15340              <bitRange>[7:0]</bitRange>
15341              <access>read-only</access>
15342            </field>
15343          </fields>
15344        </register>
15345        <register>
15346          <name>TICKS</name>
15347          <description>128Hz tick counter</description>
15348          <addressOffset>0x40</addressOffset>
15349          <size>32</size>
15350          <access>read-only</access>
15351          <resetValue>0x0</resetValue>
15352          <resetMask>0x3F</resetMask>
15353          <fields>
15354            <field>
15355              <name>CNT128HZ</name>
15356              <description>128Hz counter (msb=2Hz)
15357When SECONDS is written this field will be reset.</description>
15358              <bitRange>[5:0]</bitRange>
15359              <access>read-only</access>
15360            </field>
15361          </fields>
15362        </register>
15363        <register>
15364          <name>PMIC_CTL</name>
15365          <description>PMIC control register</description>
15366          <addressOffset>0x44</addressOffset>
15367          <size>32</size>
15368          <access>read-write</access>
15369          <resetValue>0xA0000000</resetValue>
15370          <resetMask>0xE001FF00</resetMask>
15371          <fields>
15372            <field>
15373              <name>UNLOCK</name>
15374              <description>This byte must be set to 0x3A for PMIC to be disabled.  When the UNLOCK code is not present: writes to PMIC_EN field are ignored and the hardware ignores the value in PMIC_EN.  Do not change PMIC_EN in the same write cycle as setting/clearing the UNLOCK code; do these in separate write cycles.</description>
15375              <bitRange>[15:8]</bitRange>
15376              <access>read-write</access>
15377            </field>
15378            <field>
15379              <name>POLARITY</name>
15380              <description>N/A</description>
15381              <bitRange>[16:16]</bitRange>
15382              <access>read-write</access>
15383            </field>
15384            <field>
15385              <name>PMIC_EN_OUTEN</name>
15386              <description>Output enable for the output driver in the PMIC_EN pad.
153870: Output pad is tristate for PMIC_EN pin.  This can allow this pin to be used for another purpose. Tristate condition is kept only if the UNLOCK key (0x3A) is present
153881: Output pad is enabled for PMIC_EN pin.</description>
15389              <bitRange>[29:29]</bitRange>
15390              <access>read-write</access>
15391            </field>
15392            <field>
15393              <name>PMIC_ALWAYSEN</name>
15394              <description>Override normal PMIC controls to prevent accidentally turning off the PMIC by errant firmware.
153950: Normal operation, PMIC_EN and PMIC_OUTEN work as described
153961: PMIC_EN and PMIC_OUTEN are ignored and the output pad is forced enabled.
15397Note: This bit is a write-once bit until the next backup reset.</description>
15398              <bitRange>[30:30]</bitRange>
15399              <access>read-write</access>
15400            </field>
15401            <field>
15402              <name>PMIC_EN</name>
15403              <description>Enable for external PMIC that supplies vddd (if present).  This bit will only clear if UNLOCK was written correctly in a previous write operation and PMIC_ALWAYSEN=0.  When PMIC_EN=0, the system functions normally until vddd is no longer present (OFF w/Backup mode).  Firmware can set this bit, if it does so before vddd is actually removed.  This bit is also set by any RTC alarm or PMIC pin wakeup event regardless of UNLOCK setting.</description>
15404              <bitRange>[31:31]</bitRange>
15405              <access>read-write</access>
15406            </field>
15407          </fields>
15408        </register>
15409        <register>
15410          <name>RESET</name>
15411          <description>Backup reset register</description>
15412          <addressOffset>0x48</addressOffset>
15413          <size>32</size>
15414          <access>read-write</access>
15415          <resetValue>0x0</resetValue>
15416          <resetMask>0x80000000</resetMask>
15417          <fields>
15418            <field>
15419              <name>RESET</name>
15420              <description>Writing 1 to this register resets the backup logic.  Hardware clears it when the reset is complete.  After setting this register, firmware should confirm it reads as 0 before attempting to write other backup registers.</description>
15421              <bitRange>[31:31]</bitRange>
15422              <access>read-write</access>
15423            </field>
15424          </fields>
15425        </register>
15426        <register>
15427          <dim>64</dim>
15428          <dimIncrement>4</dimIncrement>
15429          <name>BREG[%s]</name>
15430          <description>Backup register region</description>
15431          <addressOffset>0x1000</addressOffset>
15432          <size>32</size>
15433          <access>read-write</access>
15434          <resetValue>0x0</resetValue>
15435          <resetMask>0xFFFFFFFF</resetMask>
15436          <fields>
15437            <field>
15438              <name>BREG</name>
15439              <description>Backup memory that contains application-specific data.  Memory is retained on vbackup supply.</description>
15440              <bitRange>[31:0]</bitRange>
15441              <access>read-write</access>
15442            </field>
15443          </fields>
15444        </register>
15445        <register>
15446          <name>TRIM</name>
15447          <description>Trim Register</description>
15448          <addressOffset>0xFF00</addressOffset>
15449          <size>32</size>
15450          <access>read-write</access>
15451          <resetValue>0x0</resetValue>
15452          <resetMask>0x3F</resetMask>
15453          <fields>
15454            <field>
15455              <name>TRIM</name>
15456              <description>WCO trim</description>
15457              <bitRange>[5:0]</bitRange>
15458              <access>read-write</access>
15459            </field>
15460          </fields>
15461        </register>
15462      </registers>
15463    </peripheral>
15464    <peripheral>
15465      <name>DW0</name>
15466      <description>Datawire Controller</description>
15467      <headerStructName>DW</headerStructName>
15468      <baseAddress>0x40280000</baseAddress>
15469      <addressBlock>
15470        <offset>0</offset>
15471        <size>65536</size>
15472        <usage>registers</usage>
15473      </addressBlock>
15474      <registers>
15475        <register>
15476          <name>CTL</name>
15477          <description>Control</description>
15478          <addressOffset>0x0</addressOffset>
15479          <size>32</size>
15480          <access>read-write</access>
15481          <resetValue>0x1</resetValue>
15482          <resetMask>0x80000003</resetMask>
15483          <fields>
15484            <field>
15485              <name>ECC_EN</name>
15486              <description>Enable ECC checking:
15487'0': Disabled.
15488'1': Enabled.</description>
15489              <bitRange>[0:0]</bitRange>
15490              <access>read-write</access>
15491            </field>
15492            <field>
15493              <name>ECC_INJ_EN</name>
15494              <description>Enable parity injection for SRAM.
15495When '1', the parity (ECC_CTL.PARITY) is used when a full 32-bit write is done to the ECC_CTL.WORD_ADDR word address of the SRAM.</description>
15496              <bitRange>[1:1]</bitRange>
15497              <access>read-write</access>
15498            </field>
15499            <field>
15500              <name>ENABLED</name>
15501              <description>IP enable:
15502'0': Disabled. Disabling the IP activates the IP's Active logic reset: Active logic and non-retention MMIO registers are reset (retention MMIO registers are not affected).
15503'1': Enabled.</description>
15504              <bitRange>[31:31]</bitRange>
15505              <access>read-write</access>
15506            </field>
15507          </fields>
15508        </register>
15509        <register>
15510          <name>STATUS</name>
15511          <description>Status</description>
15512          <addressOffset>0x4</addressOffset>
15513          <size>32</size>
15514          <access>read-only</access>
15515          <resetValue>0x0</resetValue>
15516          <resetMask>0xF0000000</resetMask>
15517          <fields>
15518            <field>
15519              <name>P</name>
15520              <description>Active channel, user/privileged access control:
15521'0': user mode.
15522'1': privileged mode.</description>
15523              <bitRange>[0:0]</bitRange>
15524              <access>read-only</access>
15525            </field>
15526            <field>
15527              <name>NS</name>
15528              <description>Active channel, secure/non-secure access control:
15529'0': secure.
15530'1': non-secure.</description>
15531              <bitRange>[1:1]</bitRange>
15532              <access>read-only</access>
15533            </field>
15534            <field>
15535              <name>B</name>
15536              <description>Active channel, non-bufferable/bufferable access control:
15537'0': non-bufferable
15538'1': bufferable.</description>
15539              <bitRange>[2:2]</bitRange>
15540              <access>read-only</access>
15541            </field>
15542            <field>
15543              <name>PC</name>
15544              <description>Active channel protection context.</description>
15545              <bitRange>[7:4]</bitRange>
15546              <access>read-only</access>
15547            </field>
15548            <field>
15549              <name>PRIO</name>
15550              <description>Active channel priority.</description>
15551              <bitRange>[9:8]</bitRange>
15552              <access>read-only</access>
15553            </field>
15554            <field>
15555              <name>PREEMPTABLE</name>
15556              <description>Active channel preemptable.</description>
15557              <bitRange>[11:11]</bitRange>
15558              <access>read-only</access>
15559            </field>
15560            <field>
15561              <name>CH_IDX</name>
15562              <description>Active channel index.</description>
15563              <bitRange>[24:16]</bitRange>
15564              <access>read-only</access>
15565            </field>
15566            <field>
15567              <name>STATE</name>
15568              <description>State of the DW controller.
15569'0': Default/inactive state.
15570'1': Loading descriptor.
15571'2': Loading data element from source location.
15572'3': Storing data element to destination location.
15573'4': CRC functionality (only used for CRC transfer descriptor type).
15574'5': Update of active control information (e.g. source and destination addresses) and wait for trigger de-activation.
15575'6': Error.</description>
15576              <bitRange>[30:28]</bitRange>
15577              <access>read-only</access>
15578            </field>
15579            <field>
15580              <name>ACTIVE</name>
15581              <description>Active channel present:
15582'0': No.
15583'1': Yes.</description>
15584              <bitRange>[31:31]</bitRange>
15585              <access>read-only</access>
15586            </field>
15587          </fields>
15588        </register>
15589        <register>
15590          <name>ACT_DESCR_CTL</name>
15591          <description>Active descriptor control</description>
15592          <addressOffset>0x20</addressOffset>
15593          <size>32</size>
15594          <access>read-only</access>
15595          <resetValue>0x0</resetValue>
15596          <resetMask>0x0</resetMask>
15597          <fields>
15598            <field>
15599              <name>DATA</name>
15600              <description>N/A</description>
15601              <bitRange>[31:0]</bitRange>
15602              <access>read-only</access>
15603            </field>
15604          </fields>
15605        </register>
15606        <register>
15607          <name>ACT_DESCR_SRC</name>
15608          <description>Active descriptor source</description>
15609          <addressOffset>0x24</addressOffset>
15610          <size>32</size>
15611          <access>read-only</access>
15612          <resetValue>0x0</resetValue>
15613          <resetMask>0x0</resetMask>
15614          <fields>
15615            <field>
15616              <name>DATA</name>
15617              <description>Copy of DESCR_SRC of the currently active descriptor.
15618
15619Base address of source location.</description>
15620              <bitRange>[31:0]</bitRange>
15621              <access>read-only</access>
15622            </field>
15623          </fields>
15624        </register>
15625        <register>
15626          <name>ACT_DESCR_DST</name>
15627          <description>Active descriptor destination</description>
15628          <addressOffset>0x28</addressOffset>
15629          <size>32</size>
15630          <access>read-only</access>
15631          <resetValue>0x0</resetValue>
15632          <resetMask>0x0</resetMask>
15633          <fields>
15634            <field>
15635              <name>DATA</name>
15636              <description>Copy of DESCR_DST of the currently active descriptor.
15637
15638Base address of destination location.
15639
15640Note: For a CRC transfer descriptor, this field should be programmed with the address of the CRC_LFSR_CTL register. The calculated CRC LFSR state is written to this address (through the CRYPTO AHB-Lite master interface) when the input trigger is processed. The write transfer will be submitted to the CPUSS and PERI protection schemes.</description>
15641              <bitRange>[31:0]</bitRange>
15642              <access>read-only</access>
15643            </field>
15644          </fields>
15645        </register>
15646        <register>
15647          <name>ACT_DESCR_X_CTL</name>
15648          <description>Active descriptor X loop control</description>
15649          <addressOffset>0x30</addressOffset>
15650          <size>32</size>
15651          <access>read-only</access>
15652          <resetValue>0x0</resetValue>
15653          <resetMask>0x0</resetMask>
15654          <fields>
15655            <field>
15656              <name>DATA</name>
15657              <description>Copy of DESCR_X_CTL of the currently active descriptor.
15658
15659[11:0] SRC_X_INCR
15660Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures.
15661
15662[23:12] DST_X_INCR
15663Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures.
15664
15665Note: this field is not used for CRC transfer descriptors and must be set to '0'.
15666
15667[31:24] X_COUNT
15668Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations.
15669
15670For a single transfer descriptor type, descriptor will not have X_CTL.</description>
15671              <bitRange>[31:0]</bitRange>
15672              <access>read-only</access>
15673            </field>
15674          </fields>
15675        </register>
15676        <register>
15677          <name>ACT_DESCR_Y_CTL</name>
15678          <description>Active descriptor Y loop control</description>
15679          <addressOffset>0x34</addressOffset>
15680          <size>32</size>
15681          <access>read-only</access>
15682          <resetValue>0x0</resetValue>
15683          <resetMask>0x0</resetMask>
15684          <fields>
15685            <field>
15686              <name>DATA</name>
15687              <description>Copy of DESCR_Y_CTL of the currently active descriptor.
15688
15689[11:0] SRC_Y_INCR
15690Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047].
15691
15692[23:12] DST_Y_INCR
15693Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-2048, 2047].
15694
15695[31:24] Y_COUNT
15696Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 255], representing 1 through 256 iterations.
15697
15698For single, 1D and CRC transfer descriptor types, descriptor will not have Y_CTL.</description>
15699              <bitRange>[31:0]</bitRange>
15700              <access>read-only</access>
15701            </field>
15702          </fields>
15703        </register>
15704        <register>
15705          <name>ACT_DESCR_NEXT_PTR</name>
15706          <description>Active descriptor next pointer</description>
15707          <addressOffset>0x38</addressOffset>
15708          <size>32</size>
15709          <access>read-only</access>
15710          <resetValue>0x0</resetValue>
15711          <resetMask>0x0</resetMask>
15712          <fields>
15713            <field>
15714              <name>ADDR</name>
15715              <description>Copy of DESCR_NEXT_PTR of the currently active descriptor.
15716
15717[31:2] ADDR
15718Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list.</description>
15719              <bitRange>[31:2]</bitRange>
15720              <access>read-only</access>
15721            </field>
15722          </fields>
15723        </register>
15724        <register>
15725          <name>ACT_SRC</name>
15726          <description>Active source</description>
15727          <addressOffset>0x40</addressOffset>
15728          <size>32</size>
15729          <access>read-only</access>
15730          <resetValue>0x0</resetValue>
15731          <resetMask>0x0</resetMask>
15732          <fields>
15733            <field>
15734              <name>SRC_ADDR</name>
15735              <description>Current address of source location.</description>
15736              <bitRange>[31:0]</bitRange>
15737              <access>read-only</access>
15738            </field>
15739          </fields>
15740        </register>
15741        <register>
15742          <name>ACT_DST</name>
15743          <description>Active destination</description>
15744          <addressOffset>0x44</addressOffset>
15745          <size>32</size>
15746          <access>read-only</access>
15747          <resetValue>0x0</resetValue>
15748          <resetMask>0x0</resetMask>
15749          <fields>
15750            <field>
15751              <name>DST_ADDR</name>
15752              <description>Current address of destination location.</description>
15753              <bitRange>[31:0]</bitRange>
15754              <access>read-only</access>
15755            </field>
15756          </fields>
15757        </register>
15758        <register>
15759          <name>ECC_CTL</name>
15760          <description>ECC control</description>
15761          <addressOffset>0x80</addressOffset>
15762          <size>32</size>
15763          <access>read-write</access>
15764          <resetValue>0x0</resetValue>
15765          <resetMask>0xFE0003FF</resetMask>
15766          <fields>
15767            <field>
15768              <name>WORD_ADDR</name>
15769              <description>Specifies the word address where an error will be injected.
15770- On a write transfer to this SRAM word address and when CTL.ECC_INJ_EN bit is '1', the parity (PARITY) is injected.</description>
15771              <bitRange>[9:0]</bitRange>
15772              <access>read-write</access>
15773            </field>
15774            <field>
15775              <name>PARITY</name>
15776              <description>ECC parity to use for ECC error injection at address WORD_ADDR.</description>
15777              <bitRange>[31:25]</bitRange>
15778              <access>read-write</access>
15779            </field>
15780          </fields>
15781        </register>
15782        <register>
15783          <name>CRC_CTL</name>
15784          <description>CRC control</description>
15785          <addressOffset>0x100</addressOffset>
15786          <size>32</size>
15787          <access>read-write</access>
15788          <resetValue>0x0</resetValue>
15789          <resetMask>0x101</resetMask>
15790          <fields>
15791            <field>
15792              <name>DATA_REVERSE</name>
15793              <description>Specifies the bit order in which a data Byte is processed (reversal is performed after XORing):
15794'0': Most significant bit (bit 1) first.
15795'1': Least significant bit (bit 0) first.</description>
15796              <bitRange>[0:0]</bitRange>
15797              <access>read-write</access>
15798            </field>
15799            <field>
15800              <name>REM_REVERSE</name>
15801              <description>Specifies whether the remainder is bit reversed (reversal is performed after XORing):
15802'0': No.
15803'1': Yes.</description>
15804              <bitRange>[8:8]</bitRange>
15805              <access>read-write</access>
15806            </field>
15807          </fields>
15808        </register>
15809        <register>
15810          <name>CRC_DATA_CTL</name>
15811          <description>CRC data control</description>
15812          <addressOffset>0x110</addressOffset>
15813          <size>32</size>
15814          <access>read-write</access>
15815          <resetValue>0x0</resetValue>
15816          <resetMask>0xFF</resetMask>
15817          <fields>
15818            <field>
15819              <name>DATA_XOR</name>
15820              <description>Specifies a byte mask with which each data byte is XOR'd. The XOR is performed before data reversal.</description>
15821              <bitRange>[7:0]</bitRange>
15822              <access>read-write</access>
15823            </field>
15824          </fields>
15825        </register>
15826        <register>
15827          <name>CRC_POL_CTL</name>
15828          <description>CRC polynomial control</description>
15829          <addressOffset>0x120</addressOffset>
15830          <size>32</size>
15831          <access>read-write</access>
15832          <resetValue>0x0</resetValue>
15833          <resetMask>0xFFFFFFFF</resetMask>
15834          <fields>
15835            <field>
15836              <name>POLYNOMIAL</name>
15837              <description>CRC polynomial. The polynomial is represented WITHOUT the high order bit (this bit is always assumed '1'). The polynomial should be aligned/shifted such that the more significant bits (bit 31 and down) contain the polynomial and the less significant bits (bit 0 and up) contain padding '0's. Some frequently used polynomials:
15838- CRC32: POLYNOMIAL is 0x04c11db7 (x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1).
15839- CRC16: POLYNOMIAL is 0x80050000 (x^16 + x^15 + x^2 + 1, shifted by 16 bit positions).
15840- CRC16 CCITT: POLYNOMIAL is 0x10210000 (x^16 + x^12 + x^5 + 1, shifted by 16 bit positions).</description>
15841              <bitRange>[31:0]</bitRange>
15842              <access>read-write</access>
15843            </field>
15844          </fields>
15845        </register>
15846        <register>
15847          <name>CRC_LFSR_CTL</name>
15848          <description>CRC LFSR control</description>
15849          <addressOffset>0x130</addressOffset>
15850          <size>32</size>
15851          <access>read-write</access>
15852          <resetValue>0x0</resetValue>
15853          <resetMask>0xFFFFFFFF</resetMask>
15854          <fields>
15855            <field>
15856              <name>LFSR32</name>
15857              <description>State of a 32-bit Linear Feedback Shift Registers (LFSR) that is used to implement CRC. This register needs to be initialized by SW to provide the CRC seed value.
15858
15859The seed value should be aligned such that the more significant bits (bit 31 and down) contain the seed value and the less significant bits (bit 0 and up) contain padding '0's.
15860
15861Note that SW can write this field. This functionality can be used prevent information leakage (through either CRC_LFSR_CTL or CRC_REM_RESULT).</description>
15862              <bitRange>[31:0]</bitRange>
15863              <access>read-write</access>
15864            </field>
15865          </fields>
15866        </register>
15867        <register>
15868          <name>CRC_REM_CTL</name>
15869          <description>CRC remainder control</description>
15870          <addressOffset>0x140</addressOffset>
15871          <size>32</size>
15872          <access>read-write</access>
15873          <resetValue>0x0</resetValue>
15874          <resetMask>0xFFFFFFFF</resetMask>
15875          <fields>
15876            <field>
15877              <name>REM_XOR</name>
15878              <description>Specifies a mask with which the CRC_LFSR_CTL.LFSR32 register is XOR'd to produce a remainder. The XOR is performed before remainder reversal.</description>
15879              <bitRange>[31:0]</bitRange>
15880              <access>read-write</access>
15881            </field>
15882          </fields>
15883        </register>
15884        <register>
15885          <name>CRC_REM_RESULT</name>
15886          <description>CRC remainder result</description>
15887          <addressOffset>0x148</addressOffset>
15888          <size>32</size>
15889          <access>read-only</access>
15890          <resetValue>0x0</resetValue>
15891          <resetMask>0xFFFFFFFF</resetMask>
15892          <fields>
15893            <field>
15894              <name>REM</name>
15895              <description>Remainder value. The alignment of the remainder depends on CRC_REM_CTL0.REM_REVERSE:
15896'0': the more significant bits (bit 31 and down) contain the remainder.
15897'1': the less significant bits (bit 0 and up) contain the remainder.
15898
15899Note: This field is combinatorially derived from CRC_LFSR_CTL.LFSR32, CRC_CTL.REM_REVERSE and CRC_REM_CTL.REM_XOR.</description>
15900              <bitRange>[31:0]</bitRange>
15901              <access>read-only</access>
15902            </field>
15903          </fields>
15904        </register>
15905        <cluster>
15906          <dim>29</dim>
15907          <dimIncrement>64</dimIncrement>
15908          <name>CH_STRUCT[%s]</name>
15909          <description>DW channel structure</description>
15910          <addressOffset>0x00008000</addressOffset>
15911          <register>
15912            <name>CH_CTL</name>
15913            <description>Channel control</description>
15914            <addressOffset>0x0</addressOffset>
15915            <size>32</size>
15916            <access>read-write</access>
15917            <resetValue>0x0</resetValue>
15918            <resetMask>0x80000300</resetMask>
15919            <fields>
15920              <field>
15921                <name>P</name>
15922                <description>User/privileged access control:
15923'0': user mode.
15924'1': privileged mode.
15925
15926This field is set with the user/privileged access control of the transaction that writes this register; i.e.  the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R).
15927
15928All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').</description>
15929                <bitRange>[0:0]</bitRange>
15930                <access>read-write</access>
15931              </field>
15932              <field>
15933                <name>NS</name>
15934                <description>Secure/on-secure access control:
15935'0': secure.
15936'1': non-secure.
15937
15938This field is set with the secure/non-secure access control of the transaction that writes this register; i.e.  the 'write data' is ignored and instead the access control is inherited from the write transaction (note the field attributes should be HW:RW, SW:R).
15939
15940All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').</description>
15941                <bitRange>[1:1]</bitRange>
15942                <access>read-write</access>
15943              </field>
15944              <field>
15945                <name>B</name>
15946                <description>Non-bufferable/bufferable access control:
15947'0': non-bufferable.
15948'1': bufferable.
15949
15950This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data.
15951
15952All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').</description>
15953                <bitRange>[2:2]</bitRange>
15954                <access>read-write</access>
15955              </field>
15956              <field>
15957                <name>PC</name>
15958                <description>Protection context.
15959
15960This field is set with the protection context of the transaction that writes this register;  i.e.  the 'write data' is ignored and instead the context is inherited from the write transaction (note the field attributes should be HW:RW, SW:R).
15961
15962All transactions for this channel uses the PC field for the protection context.</description>
15963                <bitRange>[7:4]</bitRange>
15964                <access>read-write</access>
15965              </field>
15966              <field>
15967                <name>PRIO</name>
15968                <description>Channel priority:
15969'0': highest priority.
15970'1'
15971'2'
15972'3': lowest priority.
15973
15974Channels with the same priority constitute a priority group. Priority decoding determines the highest priority pending channel. This channel is determined as follows. First, the highest priority group with pending channels is identified. Second, within this priority group, round robin arbitration is applied. Round robin arbitration (within a priority group) gives the highest priority to the lower channel indices (within the priority group).</description>
15975                <bitRange>[9:8]</bitRange>
15976                <access>read-write</access>
15977              </field>
15978              <field>
15979                <name>PREEMPTABLE</name>
15980                <description>Specifies if the channel is preemptable.
15981'0': Not preemptable.
15982'1': Preemptable. This field allows higher priority pending channels (from a higher priority group; i.e. an active channel can NOT be preempted by a pending channel in the same priority group) to preempt the active channel in between 'single transfers' (a 1D transfer consists out of X_COUNT single transfers; a 2D transfer consists out of X_COUNT*Y_COUNT single transfers). Preemption will NOT affect the pending status of channel. As a result, after completion of a higher priority activated channel, the current channel may be reactivated.</description>
15983                <bitRange>[11:11]</bitRange>
15984                <access>read-write</access>
15985              </field>
15986              <field>
15987                <name>ENABLED</name>
15988                <description>Channel enable:
15989'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed).
15990'1': Enabled.
15991
15992SW sets this field to '1' to enable a specific channel.
15993
15994HW sets this field to '0' on an error interrupt cause (the specific error is specified by CH_STATUS.INTR_CAUSE).</description>
15995                <bitRange>[31:31]</bitRange>
15996                <access>read-write</access>
15997              </field>
15998            </fields>
15999          </register>
16000          <register>
16001            <name>CH_STATUS</name>
16002            <description>Channel status</description>
16003            <addressOffset>0x4</addressOffset>
16004            <size>32</size>
16005            <access>read-only</access>
16006            <resetValue>0x0</resetValue>
16007            <resetMask>0x80000000</resetMask>
16008            <fields>
16009              <field>
16010                <name>INTR_CAUSE</name>
16011                <description>Specifies the source of the interrupt cause:
16012'0': No interrupt generated
16013'1': Interrupt based on transfer complettion configuration based on INTR_TYPE
16014'2': Source transfer bus error
16015'3': Destination transfer bus error
16016'4': Source address misalignment
16017'5': Destination address misalignment
16018'6': Current descriptor pointer is null
16019'7': Active channel is disabled
16020'8': Descriptor bus error
16021'9'-'15': Not used.
16022
16023For error related interrupt causes (INTR_CAUSE is '2', '3', ..., '8'), the channel is disabled (HW sets CH_CTL.ENABLED to '0').</description>
16024                <bitRange>[3:0]</bitRange>
16025                <access>read-only</access>
16026              </field>
16027              <field>
16028                <name>PENDING</name>
16029                <description>Specifies pending DW channels; i.e. enabled channels whose trigger got activated. This field includes all channels that are in the pending state (not scheduled) or active state (scheduled and performing data transfer(s)).</description>
16030                <bitRange>[31:31]</bitRange>
16031                <access>read-only</access>
16032              </field>
16033            </fields>
16034          </register>
16035          <register>
16036            <name>CH_IDX</name>
16037            <description>Channel current indices</description>
16038            <addressOffset>0x8</addressOffset>
16039            <size>32</size>
16040            <access>read-write</access>
16041            <resetValue>0x0</resetValue>
16042            <resetMask>0x0</resetMask>
16043            <fields>
16044              <field>
16045                <name>X_IDX</name>
16046                <description>Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor.
16047
16048Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.
16049
16050Note: SW should set this field to '0' when it updates CH_CURR_PTR.</description>
16051                <bitRange>[7:0]</bitRange>
16052                <access>read-write</access>
16053              </field>
16054              <field>
16055                <name>Y_IDX</name>
16056                <description>Specifies the Y loop index, with X_COUNT taken from the current descriptor.
16057
16058Note: HW sets this field to '0' when it updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.
16059
16060Note: SW should set this field to '0' when it updates CH_CURR_PTR.</description>
16061                <bitRange>[15:8]</bitRange>
16062                <access>read-write</access>
16063              </field>
16064            </fields>
16065          </register>
16066          <register>
16067            <name>CH_CURR_PTR</name>
16068            <description>Channel current descriptor pointer</description>
16069            <addressOffset>0xC</addressOffset>
16070            <size>32</size>
16071            <access>read-write</access>
16072            <resetValue>0x0</resetValue>
16073            <resetMask>0x0</resetMask>
16074            <fields>
16075              <field>
16076                <name>ADDR</name>
16077                <description>Address of current descriptor. When this field is '0', there is no valid descriptor.
16078
16079Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.
16080
16081Note: Typically, when SW updates the current descriptor pointer CH_CURR_PTR, it also sets CH_IDX.X_IDX and CH_IDX.Y_IDX to '0'.</description>
16082                <bitRange>[31:2]</bitRange>
16083                <access>read-write</access>
16084              </field>
16085            </fields>
16086          </register>
16087          <register>
16088            <name>INTR</name>
16089            <description>Interrupt</description>
16090            <addressOffset>0x10</addressOffset>
16091            <size>32</size>
16092            <access>read-write</access>
16093            <resetValue>0x0</resetValue>
16094            <resetMask>0x1</resetMask>
16095            <fields>
16096              <field>
16097                <name>CH</name>
16098                <description>Set to '1', when event (as specified by CH_STATUS.INTR_CAUSE) is detected. Write INTR.CH field with '1', to clear bit. Write INTR_SET.CH field with '1', to set bit.</description>
16099                <bitRange>[0:0]</bitRange>
16100                <access>read-write</access>
16101              </field>
16102            </fields>
16103          </register>
16104          <register>
16105            <name>INTR_SET</name>
16106            <description>Interrupt set</description>
16107            <addressOffset>0x14</addressOffset>
16108            <size>32</size>
16109            <access>read-write</access>
16110            <resetValue>0x0</resetValue>
16111            <resetMask>0x1</resetMask>
16112            <fields>
16113              <field>
16114                <name>CH</name>
16115                <description>Write INTR_SET field with '1' to set corresponding INTR.CH field (a write of '0' has no effect).</description>
16116                <bitRange>[0:0]</bitRange>
16117                <access>read-write</access>
16118              </field>
16119            </fields>
16120          </register>
16121          <register>
16122            <name>INTR_MASK</name>
16123            <description>Interrupt mask</description>
16124            <addressOffset>0x18</addressOffset>
16125            <size>32</size>
16126            <access>read-write</access>
16127            <resetValue>0x0</resetValue>
16128            <resetMask>0x1</resetMask>
16129            <fields>
16130              <field>
16131                <name>CH</name>
16132                <description>Mask for corresponding field in INTR register.</description>
16133                <bitRange>[0:0]</bitRange>
16134                <access>read-write</access>
16135              </field>
16136            </fields>
16137          </register>
16138          <register>
16139            <name>INTR_MASKED</name>
16140            <description>Interrupt masked</description>
16141            <addressOffset>0x1C</addressOffset>
16142            <size>32</size>
16143            <access>read-only</access>
16144            <resetValue>0x0</resetValue>
16145            <resetMask>0x1</resetMask>
16146            <fields>
16147              <field>
16148                <name>CH</name>
16149                <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
16150                <bitRange>[0:0]</bitRange>
16151                <access>read-only</access>
16152              </field>
16153            </fields>
16154          </register>
16155          <register>
16156            <name>SRAM_DATA0</name>
16157            <description>SRAM data 0</description>
16158            <addressOffset>0x20</addressOffset>
16159            <size>32</size>
16160            <access>read-write</access>
16161            <resetValue>0x0</resetValue>
16162            <resetMask>0x0</resetMask>
16163            <fields>
16164              <field>
16165                <name>DATA</name>
16166                <description>N/A</description>
16167                <bitRange>[31:0]</bitRange>
16168                <access>read-write</access>
16169              </field>
16170            </fields>
16171          </register>
16172          <register>
16173            <name>SRAM_DATA1</name>
16174            <description>SRAM data 1</description>
16175            <addressOffset>0x24</addressOffset>
16176            <size>32</size>
16177            <access>read-write</access>
16178            <resetValue>0x0</resetValue>
16179            <resetMask>0x0</resetMask>
16180            <fields>
16181              <field>
16182                <name>DATA</name>
16183                <description>N/A</description>
16184                <bitRange>[31:0]</bitRange>
16185                <access>read-write</access>
16186              </field>
16187            </fields>
16188          </register>
16189          <register>
16190            <name>TR_CMD</name>
16191            <description>Channel software trigger</description>
16192            <addressOffset>0x28</addressOffset>
16193            <size>32</size>
16194            <access>read-write</access>
16195            <resetValue>0x0</resetValue>
16196            <resetMask>0x1</resetMask>
16197            <fields>
16198              <field>
16199                <name>ACTIVATE</name>
16200                <description>Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0.</description>
16201                <bitRange>[0:0]</bitRange>
16202                <access>read-write</access>
16203              </field>
16204            </fields>
16205          </register>
16206        </cluster>
16207      </registers>
16208    </peripheral>
16209    <peripheral derivedFrom="DW0">
16210      <name>DW1</name>
16211      <baseAddress>0x40290000</baseAddress>
16212    </peripheral>
16213    <peripheral>
16214      <name>DMAC</name>
16215      <description>DMAC</description>
16216      <baseAddress>0x402A0000</baseAddress>
16217      <addressBlock>
16218        <offset>0</offset>
16219        <size>65536</size>
16220        <usage>registers</usage>
16221      </addressBlock>
16222      <registers>
16223        <register>
16224          <name>CTL</name>
16225          <description>Control</description>
16226          <addressOffset>0x0</addressOffset>
16227          <size>32</size>
16228          <access>read-write</access>
16229          <resetValue>0x0</resetValue>
16230          <resetMask>0x80000000</resetMask>
16231          <fields>
16232            <field>
16233              <name>ENABLED</name>
16234              <description>IP enable:
16235'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled.
16236'1': Enabled.</description>
16237              <bitRange>[31:31]</bitRange>
16238              <access>read-write</access>
16239              <enumeratedValues>
16240                <enumeratedValue>
16241                  <name>DISABLED</name>
16242                  <description>N/A</description>
16243                  <value>0</value>
16244                </enumeratedValue>
16245                <enumeratedValue>
16246                  <name>ENABLED</name>
16247                  <description>N/A</description>
16248                  <value>1</value>
16249                </enumeratedValue>
16250              </enumeratedValues>
16251            </field>
16252          </fields>
16253        </register>
16254        <register>
16255          <name>ACTIVE</name>
16256          <description>Active channels</description>
16257          <addressOffset>0x8</addressOffset>
16258          <size>32</size>
16259          <access>read-only</access>
16260          <resetValue>0x0</resetValue>
16261          <resetMask>0xFF</resetMask>
16262          <fields>
16263            <field>
16264              <name>ACTIVE</name>
16265              <description>Specifies active channels; i.e. enabled channels whose trigger got activated.</description>
16266              <bitRange>[7:0]</bitRange>
16267              <access>read-only</access>
16268            </field>
16269          </fields>
16270        </register>
16271        <cluster>
16272          <dim>4</dim>
16273          <dimIncrement>256</dimIncrement>
16274          <name>CH[%s]</name>
16275          <description>DMA controller channel</description>
16276          <addressOffset>0x00001000</addressOffset>
16277          <register>
16278            <name>CTL</name>
16279            <description>Channel control</description>
16280            <addressOffset>0x0</addressOffset>
16281            <size>32</size>
16282            <access>read-write</access>
16283            <resetValue>0x2</resetValue>
16284            <resetMask>0x800003F7</resetMask>
16285            <fields>
16286              <field>
16287                <name>P</name>
16288                <description>User/privileged access control:
16289'0': user mode.
16290'1': privileged mode.
16291
16292This field is set with the user/privileged access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data.
16293
16294All transactions for this channel use the P field for the user/privileged access control ('hprot[1]').</description>
16295                <bitRange>[0:0]</bitRange>
16296                <access>read-write</access>
16297              </field>
16298              <field>
16299                <name>NS</name>
16300                <description>Secure/on-secure access control:
16301'0': secure.
16302'1': non-secure.
16303
16304This field is set with the secure/non-secure access control of the transaction that writes this register; i.e. the access control is inherited from the write transaction and not specified by the transaction write data.
16305
16306All transactions for this channel use the NS field for the secure/non-secure access control ('hprot[4]').</description>
16307                <bitRange>[1:1]</bitRange>
16308                <access>read-write</access>
16309              </field>
16310              <field>
16311                <name>B</name>
16312                <description>Non-bufferable/bufferable access control:
16313'0': non-bufferable.
16314'1': bufferable.
16315
16316This field is used to indicate to an AMBA bridge that a write transaction can complete without waiting for the destination to accept the write transaction data.
16317
16318All transactions for this channel uses the B field for the non-bufferable/bufferable access control ('hprot[2]').</description>
16319                <bitRange>[2:2]</bitRange>
16320                <access>read-write</access>
16321              </field>
16322              <field>
16323                <name>PC</name>
16324                <description>Protection context.
16325
16326This field is set with the protection context of the transaction that writes this register; i.e. the context is inherited from the write transaction and not specified by the transaction write data.
16327
16328All transactions for this channel uses the PC field for the protection context.</description>
16329                <bitRange>[7:4]</bitRange>
16330                <access>read-write</access>
16331              </field>
16332              <field>
16333                <name>PRIO</name>
16334                <description>Channel priority:
16335'0': highest priority.
16336'1'
16337'2'
16338'3': lowest priority.
16339
16340Channels with the same priority constitute a priority group and within this priority group, the following 'roundrobin' arbitration is applied.
16341A 'round' consists of a contiguous sequence of channel activations, within this priority group, without any repetition. Within a round, higher priority is given to the lower channel indices. The notion of a round guarantees that within a group, higher channel indices do not yield to lower indices indefinitely.</description>
16342                <bitRange>[9:8]</bitRange>
16343                <access>read-write</access>
16344              </field>
16345              <field>
16346                <name>ENABLED</name>
16347                <description>Channel enable:
16348'0': Disabled. The channel's trigger is ignored and the channel cannot be made pending and therefore cannot be made active. If a pending channel is disabled, the channel is made non pending. If the activate channel is disabled, the channel is de-activated (bus transactions are completed).
16349'1': Enabled.
16350
16351SW sets this field to '1' to enable a specific channel.
16352
16353HW sets this field to '0' when an error interrupt cause is activated.</description>
16354                <bitRange>[31:31]</bitRange>
16355                <access>read-write</access>
16356              </field>
16357            </fields>
16358          </register>
16359          <register>
16360            <name>IDX</name>
16361            <description>Channel current indices</description>
16362            <addressOffset>0x10</addressOffset>
16363            <size>32</size>
16364            <access>read-only</access>
16365            <resetValue>0x0</resetValue>
16366            <resetMask>0x0</resetMask>
16367            <fields>
16368              <field>
16369                <name>X</name>
16370                <description>Specifies the X loop index. In the range of [0, X_COUNT], with X_COUNT taken from the current descriptor.
16371
16372Note: HW sets this field to '0' when it loads a descriptor.</description>
16373                <bitRange>[15:0]</bitRange>
16374                <access>read-only</access>
16375              </field>
16376              <field>
16377                <name>Y</name>
16378                <description>Specifies the Y loop index, with Y_COUNT taken from the current descriptor.
16379
16380Note: HW sets this field to '0' when it loads a descriptor..</description>
16381                <bitRange>[31:16]</bitRange>
16382                <access>read-only</access>
16383              </field>
16384            </fields>
16385          </register>
16386          <register>
16387            <name>SRC</name>
16388            <description>Channel current source address</description>
16389            <addressOffset>0x14</addressOffset>
16390            <size>32</size>
16391            <access>read-only</access>
16392            <resetValue>0x0</resetValue>
16393            <resetMask>0x0</resetMask>
16394            <fields>
16395              <field>
16396                <name>ADDR</name>
16397                <description>Current address of source location.</description>
16398                <bitRange>[31:0]</bitRange>
16399                <access>read-only</access>
16400              </field>
16401            </fields>
16402          </register>
16403          <register>
16404            <name>DST</name>
16405            <description>Channel current destination address</description>
16406            <addressOffset>0x18</addressOffset>
16407            <size>32</size>
16408            <access>read-only</access>
16409            <resetValue>0x0</resetValue>
16410            <resetMask>0x0</resetMask>
16411            <fields>
16412              <field>
16413                <name>ADDR</name>
16414                <description>Current address of destination location.</description>
16415                <bitRange>[31:0]</bitRange>
16416                <access>read-only</access>
16417              </field>
16418            </fields>
16419          </register>
16420          <register>
16421            <name>CURR</name>
16422            <description>Channel current descriptor pointer</description>
16423            <addressOffset>0x20</addressOffset>
16424            <size>32</size>
16425            <access>read-write</access>
16426            <resetValue>0x0</resetValue>
16427            <resetMask>0x0</resetMask>
16428            <fields>
16429              <field>
16430                <name>PTR</name>
16431                <description>Address of current descriptor. When this field is '0', there is no valid descriptor.
16432
16433Note: HW updates the current descriptor pointer CH_CURR_PTR with DESCR_NEXT_PTR after execution of the current descriptor.</description>
16434                <bitRange>[31:2]</bitRange>
16435                <access>read-write</access>
16436              </field>
16437            </fields>
16438          </register>
16439          <register>
16440            <name>TR_CMD</name>
16441            <description>Channle software trigger</description>
16442            <addressOffset>0x28</addressOffset>
16443            <size>32</size>
16444            <access>read-write</access>
16445            <resetValue>0x0</resetValue>
16446            <resetMask>0x1</resetMask>
16447            <fields>
16448              <field>
16449                <name>ACTIVATE</name>
16450                <description>Software trigger. When written with '1', a trigger is generated which sets 'trigger pending' (only if the channel is enabled). A read always returns a 0.</description>
16451                <bitRange>[0:0]</bitRange>
16452                <access>read-write</access>
16453              </field>
16454            </fields>
16455          </register>
16456          <register>
16457            <name>DESCR_STATUS</name>
16458            <description>Channel descriptor status</description>
16459            <addressOffset>0x40</addressOffset>
16460            <size>32</size>
16461            <access>read-only</access>
16462            <resetValue>0x0</resetValue>
16463            <resetMask>0x80000000</resetMask>
16464            <fields>
16465              <field>
16466                <name>VALID</name>
16467                <description>Indicates whether the descriptor information present in DESCR_CTL, DESCR_SRC, DESCR_DST, DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE, DESCR_Y_INCR, DESCR_NEXT status registers is valid or not.</description>
16468                <bitRange>[31:31]</bitRange>
16469                <access>read-only</access>
16470              </field>
16471            </fields>
16472          </register>
16473          <register>
16474            <name>DESCR_CTL</name>
16475            <description>Channel descriptor control</description>
16476            <addressOffset>0x60</addressOffset>
16477            <size>32</size>
16478            <access>read-only</access>
16479            <resetValue>0x0</resetValue>
16480            <resetMask>0x0</resetMask>
16481            <fields>
16482              <field>
16483                <name>WAIT_FOR_DEACT</name>
16484                <description>Specifies whether the controller should wait for the input trigger to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller with the agent that generated the trigger. This field is ONLY used at the completion of the transfer as specified by TR_IN. E.g., a TX FIFO indicates that it is empty and it needs a new data sample. The agent removes the trigger ONLY when the data sample has been written by the controller AND received by the agent.  Furthermore, the agent's trigger may be delayed by a few cycles before it reaches the controller. This field is used for level sensitive trigger, which reflect state (pulse sensitive triggers should have this field set to '0'). The wait cycles incurred by this field reduce DW controller performance.
16485'0': Do not wait for trigger de-activation (for pulse sensitive triggers).
16486'1': Wait for up to 4 cycles.
16487'2': Wait for up to 16 cycles.
16488'3': Wait indefinitely. This option may result in controller lockup if the trigger is not de-activated.</description>
16489                <bitRange>[1:0]</bitRange>
16490                <access>read-only</access>
16491              </field>
16492              <field>
16493                <name>INTR_TYPE</name>
16494                <description>Specifies when a completion interrupt is generated (CH_STATUS.INTR_CAUSE is set to COMPLETION):
16495'0': An interrupt is generated after a single transfer.
16496'1': An interrupt is generated after a single 1D transfer or a memory copy transfer
16497- If the descriptor type is 'single', the interrupt is generated after a single transfer.
16498- If the descriptor type is '1D' or '2D', the interrupt is generated after the execution of a 1D transfer.
16499- If the descriptor type is 'memory copy', the interrupt is generated after the execution of a memory copy transfer.
16500- If the descriptor type is 'scatter' the interrupt is generated after the execution of a scatter transfer.
16501'2': An interrupt is generated after the execution of the current descriptor (independent of the value of DESCR_NEXT_PTR.ADDR of the current descriptor).
16502'3': An interrupt is generated after the execution of the current descriptor and the current descriptor's DESCR_NEXT_PTR.ADDR is '0'.</description>
16503                <bitRange>[3:2]</bitRange>
16504                <access>read-only</access>
16505              </field>
16506              <field>
16507                <name>TR_OUT_TYPE</name>
16508                <description>Specifies when an output trigger is generated:
16509'0': An output trigger is generated after a single transfer.
16510'1': An output trigger is generated after a single 1D transfer or a memory copy transfer.
16511- If the descriptor type is 'single', the output trigger is generated after a single transfer.
16512- If the descriptor type is '1D' or '2D', the output trigger is generated after the execution of a 1D transfer.
16513- If the descriptor type is 'memory copy', the output trigger is generated after the execution of a memory copy transfer.
16514- If the descriptor type is 'scatter', the output trigger is generated after the execution of a scatter transfer.
16515'2': An output trigger is generated after the execution of the current descriptor.
16516'3': An output trigger is generated after the execution of a descriptor list: after the execution of the current descriptor AND the current descriptor's DESCR_NEXT_PTR.ADDR is '0'.</description>
16517                <bitRange>[5:4]</bitRange>
16518                <access>read-only</access>
16519              </field>
16520              <field>
16521                <name>TR_IN_TYPE</name>
16522                <description>Specifies the input trigger type (not to be confused with the descriptor type):
16523'0': A trigger results in the execution of a single transfer. The descriptor type can be single, 1D or 2D.
16524'1': A trigger results in the execution of a single 1D transfer.
16525- If the descriptor type is 'single', the trigger results in the execution of a single transfer.
16526- If the descriptor type is '1D' or '2D', the trigger results in the execution of a 1D transfer.
16527- If the descriptor type is 'memory copy', the trigger results in the execution of a memory copy transfer.
16528- If the descriptor type is 'scatter', the trigger results in the execution of an scatter transfer.
16529'2': A trigger results in the execution of the current descriptor.
16530'3': A trigger results in the execution of the current descriptor and continues (without requiring another input trigger) with the execution of the next descriptor using the next descriptor's information.</description>
16531                <bitRange>[7:6]</bitRange>
16532                <access>read-only</access>
16533              </field>
16534              <field>
16535                <name>DATA_PREFETCH</name>
16536                <description>Source data prefetch:
16537'0': No source data prefetch. Source data transfers are only initiated AFTER the input trigger is activated.
16538'1': Source data prefetch. Source data transfers are initiated as soon as the channel is enabled, the current descriptor pointer is NOT '0' and there is space available in the channel's data FIFO. When the input trigger is activated, the trigger can initiate destination data transfers with data that is already in the channel's data FIFO. This effectively shortens the initial delay of the data transfer.
16539
16540Note: data prefetch should be used with care, to ensure that data coherency is guaranteed and that prefetches do not cause undesired side effects.</description>
16541                <bitRange>[8:8]</bitRange>
16542                <access>read-only</access>
16543              </field>
16544              <field>
16545                <name>DATA_SIZE</name>
16546                <description>Specifies the data element size:
16547'0': Byte (8 bits).
16548'1': Halfword (16 bits).
16549'2': Word (32 bits).
16550DATA_SIZE, SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE together determine how data elements are transferred. The following are the 9 legal settings:
16551- DATA is 8 bit, SRC is 8 bit, DST is 8 bit.
16552- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 8 bit.
16553- DATA is 8 bit, SRC is 8 bit, DST is 32 bit (higher 24 bits are made '0').
16554- DATA is 8 bit, SRC is 32 bit (higher 24 bits are dropped), DST is 32 bit (higher 24 bits are made '0').
16555- DATA is 16 bit, SRC is 16 bit, DST is 16 bit.
16556- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 16 bit.
16557- DATA is 16 bit, SRC is 16 bit, DST is 32 bit (higher 16 bits are made '0').
16558- DATA is 16 bit, SRC is 32 bit (higher 16 bits are dropped), DST is 32 bit (higher 16 bits are made '0').
16559- DATA is 32 bit, SRC is 32 bit, DST is 32 bit.
16560
16561Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '2' for a 'initialization' descriptor type.</description>
16562                <bitRange>[17:16]</bitRange>
16563                <access>read-only</access>
16564              </field>
16565              <field>
16566                <name>CH_DISABLE</name>
16567                <description>Specifies whether the channel is disabled or not after completion of the current descriptor (independent of the value of the DESCR_NEXT_PTR value):
16568'0': Channel is not disabled.
16569'1': Channel is disabled.</description>
16570                <bitRange>[24:24]</bitRange>
16571                <access>read-only</access>
16572              </field>
16573              <field>
16574                <name>SRC_TRANSFER_SIZE</name>
16575                <description>Specifies the bus transfer size to the source location:
16576'0': As specified by DATA_SIZE.
16577'1': Word (32 bits).
16578Distinguishing bus transfer size from data element size allows for source components with data elements that are smaller than their 32-bit bus interface width. E.g., an ADC source has a 32-bit bus transfer size, but only provides a 16-bit data element.
16579
16580Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type.</description>
16581                <bitRange>[26:26]</bitRange>
16582                <access>read-only</access>
16583              </field>
16584              <field>
16585                <name>DST_TRANSFER_SIZE</name>
16586                <description>Specifies the bus transfer size to the destination location:
16587'0': As specified by DATA_SIZE.
16588'1': Word (32 bits).
16589Distinguishing bus transfer size from data element size allows for destination components with data elements that are smaller than their 32-bit bus interface width. E.g., a DAC destination has a 32-bit bus transfer size, but only requires a 16-bit data element.
16590
16591Note: this field is not used for a 'memory copy' descriptor type. Note: this field must be set to '1' for a 'scatter' descriptor type.</description>
16592                <bitRange>[27:27]</bitRange>
16593                <access>read-only</access>
16594              </field>
16595              <field>
16596                <name>DESCR_TYPE</name>
16597                <description>Specifies the descriptor type (not to be confused with the trigger type):
16598'0': Single transfer.
16599The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are NOT present. The DESCR_NEXT_PTR is at offset 0x0c.
16600'1': 1D transfer.
16601The DESCR_X_SIZE and DESCR_X_INCR registers are present, the DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A 1D transfer consists out of DESCR_X_SIZE.X_COUNT+1 single transfers. The DESCR_NEXT_PTR is at offset 0x14.
16602'2': 2D transfer.
16603The DESCR_X_SIZE, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR registers are present. A 2D transfer consists of (DESCR_X_SIZE.X_COUNT+1)*(DESCR_Y_SIZE.Y_COUNT+1) single transfers. The DESCR_NEXT_PTR is at offset 0x1c.
16604'3': Memory copy.
16605The DESCR_X_SIZE register is present, the DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present. A memory copy transfer copies DESCR_X_SIZE.X_COUNT+1 Bytes and may use Byte, halfword and word transfers. The DESCR_NEXT_PTR is at offset 0x10.
16606'4': Scatter transfer. The DESCR_X_SIZE register is present, the DESCR_DST, DESCR_X_INCR, DESCR_Y_SIZE and DESCR_Y_INCR are NOT present.
16607'5'-'7': Undefined.
16608
16609After the execution of the current descriptor, the DESCR_NEXT_PTR address is copied to the channel's CH_CURR_PTR address and CH_STATUS.X_IDX and CH_STATUS.Y_IDX are set to '0'.</description>
16610                <bitRange>[30:28]</bitRange>
16611                <access>read-only</access>
16612              </field>
16613            </fields>
16614          </register>
16615          <register>
16616            <name>DESCR_SRC</name>
16617            <description>Channel descriptor source</description>
16618            <addressOffset>0x64</addressOffset>
16619            <size>32</size>
16620            <access>read-only</access>
16621            <resetValue>0x0</resetValue>
16622            <resetMask>0x0</resetMask>
16623            <fields>
16624              <field>
16625                <name>ADDR</name>
16626                <description>Base address of source location.</description>
16627                <bitRange>[31:0]</bitRange>
16628                <access>read-only</access>
16629              </field>
16630            </fields>
16631          </register>
16632          <register>
16633            <name>DESCR_DST</name>
16634            <description>Channel descriptor destination</description>
16635            <addressOffset>0x68</addressOffset>
16636            <size>32</size>
16637            <access>read-only</access>
16638            <resetValue>0x0</resetValue>
16639            <resetMask>0x0</resetMask>
16640            <fields>
16641              <field>
16642                <name>ADDR</name>
16643                <description>Base address of destination location.</description>
16644                <bitRange>[31:0]</bitRange>
16645                <access>read-only</access>
16646              </field>
16647            </fields>
16648          </register>
16649          <register>
16650            <name>DESCR_X_SIZE</name>
16651            <description>Channel descriptor X size</description>
16652            <addressOffset>0x6C</addressOffset>
16653            <size>32</size>
16654            <access>read-only</access>
16655            <resetValue>0x0</resetValue>
16656            <resetMask>0x0</resetMask>
16657            <fields>
16658              <field>
16659                <name>X_COUNT</name>
16660                <description>Number of iterations (minus 1) of the 'X loop' (X_COUNT+1 is the number of single transfers in a 1D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations.
16661
16662For the 'memory copy' descriptor type, (X_COUNT + 1) is the number of transferred Bytes. For the 'scatter' descriptor type, ceiling(X_COUNT/2) is the number of (address, write data) initialization pairs processed.</description>
16663                <bitRange>[15:0]</bitRange>
16664                <access>read-only</access>
16665              </field>
16666            </fields>
16667          </register>
16668          <register>
16669            <name>DESCR_X_INCR</name>
16670            <description>Channel descriptor X increment</description>
16671            <addressOffset>0x70</addressOffset>
16672            <size>32</size>
16673            <access>read-only</access>
16674            <resetValue>0x0</resetValue>
16675            <resetMask>0x0</resetMask>
16676            <fields>
16677              <field>
16678                <name>SRC_X</name>
16679                <description>Specifies increment of source address for each X loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the source address is not incremented. This is useful for reading from RX FIFO structures.</description>
16680                <bitRange>[15:0]</bitRange>
16681                <access>read-only</access>
16682              </field>
16683              <field>
16684                <name>DST_X</name>
16685                <description>Specifies increment of destination address for each X loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number (sign-magnitude format) in the range [-32768, 32767]. If this field is '0', the destination address is not incremented. This is useful for writing to TX FIFO structures.</description>
16686                <bitRange>[31:16]</bitRange>
16687                <access>read-only</access>
16688              </field>
16689            </fields>
16690          </register>
16691          <register>
16692            <name>DESCR_Y_SIZE</name>
16693            <description>Channel descriptor Y size</description>
16694            <addressOffset>0x74</addressOffset>
16695            <size>32</size>
16696            <access>read-only</access>
16697            <resetValue>0x0</resetValue>
16698            <resetMask>0x0</resetMask>
16699            <fields>
16700              <field>
16701                <name>Y_COUNT</name>
16702                <description>Number of iterations (minus 1) of the 'Y loop' (X_COUNT+1)*(Y_COUNT+1) is the number of single transfers in a 2D transfer). This field is an unsigned number in the range [0, 65535], representing 1 through 65536 iterations.</description>
16703                <bitRange>[15:0]</bitRange>
16704                <access>read-only</access>
16705              </field>
16706            </fields>
16707          </register>
16708          <register>
16709            <name>DESCR_Y_INCR</name>
16710            <description>Channel descriptor Y increment</description>
16711            <addressOffset>0x78</addressOffset>
16712            <size>32</size>
16713            <access>read-only</access>
16714            <resetValue>0x0</resetValue>
16715            <resetMask>0x0</resetMask>
16716            <fields>
16717              <field>
16718                <name>SRC_Y</name>
16719                <description>Specifies increment of source address for each Y loop iteration (in multiples of SRC_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767].</description>
16720                <bitRange>[15:0]</bitRange>
16721                <access>read-only</access>
16722              </field>
16723              <field>
16724                <name>DST_Y</name>
16725                <description>Specifies increment of destination address for each Y loop iteration (in multiples of DST_TRANSFER_SIZE). This field is a signed number in the range [-32768, 32767].</description>
16726                <bitRange>[31:16]</bitRange>
16727                <access>read-only</access>
16728              </field>
16729            </fields>
16730          </register>
16731          <register>
16732            <name>DESCR_NEXT</name>
16733            <description>Channel descriptor next pointer</description>
16734            <addressOffset>0x7C</addressOffset>
16735            <size>32</size>
16736            <access>read-only</access>
16737            <resetValue>0x0</resetValue>
16738            <resetMask>0x0</resetMask>
16739            <fields>
16740              <field>
16741                <name>PTR</name>
16742                <description>Address of next descriptor in descriptor list. When this field is '0', this is the last descriptor in the descriptor list.</description>
16743                <bitRange>[31:2]</bitRange>
16744                <access>read-only</access>
16745              </field>
16746            </fields>
16747          </register>
16748          <register>
16749            <name>INTR</name>
16750            <description>Interrupt</description>
16751            <addressOffset>0x80</addressOffset>
16752            <size>32</size>
16753            <access>read-write</access>
16754            <resetValue>0x0</resetValue>
16755            <resetMask>0xFF</resetMask>
16756            <fields>
16757              <field>
16758                <name>COMPLETION</name>
16759                <description>Activated (set to '1') on completion of data transfer(s) as specified by the descriptor's CH_DESCR_CTL.INTR_TYPE.</description>
16760                <bitRange>[0:0]</bitRange>
16761                <access>read-write</access>
16762              </field>
16763              <field>
16764                <name>SRC_BUS_ERROR</name>
16765                <description>Activated (set to '1') on a bus error for a load from the source.</description>
16766                <bitRange>[1:1]</bitRange>
16767                <access>read-write</access>
16768              </field>
16769              <field>
16770                <name>DST_BUS_ERROR</name>
16771                <description>Activated (set to '1') on a bus error for a store to the destination.</description>
16772                <bitRange>[2:2]</bitRange>
16773                <access>read-write</access>
16774              </field>
16775              <field>
16776                <name>SRC_MISAL</name>
16777                <description>Activated (set to '1') on a misalignment of the source address.</description>
16778                <bitRange>[3:3]</bitRange>
16779                <access>read-write</access>
16780              </field>
16781              <field>
16782                <name>DST_MISAL</name>
16783                <description>Activated (set to '1') on a misalignment of the destination address.</description>
16784                <bitRange>[4:4]</bitRange>
16785                <access>read-write</access>
16786              </field>
16787              <field>
16788                <name>CURR_PTR_NULL</name>
16789                <description>Activated (set to '1') when the channel is enabled (CH_CTL.ENABLED is '1') and CH_CURR_PTR is '0'.</description>
16790                <bitRange>[5:5]</bitRange>
16791                <access>read-write</access>
16792              </field>
16793              <field>
16794                <name>ACTIVE_CH_DISABLED</name>
16795                <description>Activated (set to '1') if the channel is disabled by SW (accidentally/incorrectly) when the data transfer engine is busy.</description>
16796                <bitRange>[6:6]</bitRange>
16797                <access>read-write</access>
16798              </field>
16799              <field>
16800                <name>DESCR_BUS_ERROR</name>
16801                <description>Activated (set to '1') on a bus error for a load of the descriptor.</description>
16802                <bitRange>[7:7]</bitRange>
16803                <access>read-write</access>
16804              </field>
16805            </fields>
16806          </register>
16807          <register>
16808            <name>INTR_SET</name>
16809            <description>Interrupt set</description>
16810            <addressOffset>0x84</addressOffset>
16811            <size>32</size>
16812            <access>read-write</access>
16813            <resetValue>0x0</resetValue>
16814            <resetMask>0xFF</resetMask>
16815            <fields>
16816              <field>
16817                <name>COMPLETION</name>
16818                <description>Write this field with '1' to set INTR.COMPLETION field to '1' (a write of '0' has no effect).</description>
16819                <bitRange>[0:0]</bitRange>
16820                <access>read-write</access>
16821              </field>
16822              <field>
16823                <name>SRC_BUS_ERROR</name>
16824                <description>Write this field with '1' to set INTR.SRC_BUS_ERROR field to '1' (a write of '0' has no effect).</description>
16825                <bitRange>[1:1]</bitRange>
16826                <access>read-write</access>
16827              </field>
16828              <field>
16829                <name>DST_BUS_ERROR</name>
16830                <description>Write this field with '1' to set INTR.DST_BUS_ERROR field to '1' (a write of '0' has no effect).</description>
16831                <bitRange>[2:2]</bitRange>
16832                <access>read-write</access>
16833              </field>
16834              <field>
16835                <name>SRC_MISAL</name>
16836                <description>Write this field with '1' to set INTR.SRC_MISAL field to '1' (a write of '0' has no effect).</description>
16837                <bitRange>[3:3]</bitRange>
16838                <access>read-write</access>
16839              </field>
16840              <field>
16841                <name>DST_MISAL</name>
16842                <description>Write this field with '1' to set INTR.DST_MISAL field to '1' (a write of '0' has no effect).</description>
16843                <bitRange>[4:4]</bitRange>
16844                <access>read-write</access>
16845              </field>
16846              <field>
16847                <name>CURR_PTR_NULL</name>
16848                <description>Write this field with '1' to set INTR.CURR_PTR_NULL field to '1' (a write of '0' has no effect).</description>
16849                <bitRange>[5:5]</bitRange>
16850                <access>read-write</access>
16851              </field>
16852              <field>
16853                <name>ACTIVE_CH_DISABLED</name>
16854                <description>Write this field with '1' to set INTR.ACT_CH_DISABLED field to '1' (a write of '0' has no effect).</description>
16855                <bitRange>[6:6]</bitRange>
16856                <access>read-write</access>
16857              </field>
16858              <field>
16859                <name>DESCR_BUS_ERROR</name>
16860                <description>Write this field with '1' to set INTR.DESCR_BUS_ERROR field to '1' (a write of '0' has no effect).</description>
16861                <bitRange>[7:7]</bitRange>
16862                <access>read-write</access>
16863              </field>
16864            </fields>
16865          </register>
16866          <register>
16867            <name>INTR_MASK</name>
16868            <description>Interrupt mask</description>
16869            <addressOffset>0x88</addressOffset>
16870            <size>32</size>
16871            <access>read-write</access>
16872            <resetValue>0x0</resetValue>
16873            <resetMask>0xFF</resetMask>
16874            <fields>
16875              <field>
16876                <name>COMPLETION</name>
16877                <description>Mask for INTR.COMPLETION interrupt.</description>
16878                <bitRange>[0:0]</bitRange>
16879                <access>read-write</access>
16880              </field>
16881              <field>
16882                <name>SRC_BUS_ERROR</name>
16883                <description>Mask for INTR.SRC_BUS_ERROR interrupt.</description>
16884                <bitRange>[1:1]</bitRange>
16885                <access>read-write</access>
16886              </field>
16887              <field>
16888                <name>DST_BUS_ERROR</name>
16889                <description>Mask for INTR.DST_BUS_ERROR interrupt.</description>
16890                <bitRange>[2:2]</bitRange>
16891                <access>read-write</access>
16892              </field>
16893              <field>
16894                <name>SRC_MISAL</name>
16895                <description>Mask for INTR.SRC_MISAL interrupt.</description>
16896                <bitRange>[3:3]</bitRange>
16897                <access>read-write</access>
16898              </field>
16899              <field>
16900                <name>DST_MISAL</name>
16901                <description>Mask for INTR.DST_MISAL interrupt.</description>
16902                <bitRange>[4:4]</bitRange>
16903                <access>read-write</access>
16904              </field>
16905              <field>
16906                <name>CURR_PTR_NULL</name>
16907                <description>Mask for INTR.CURR_PTR_NULL interrupt.</description>
16908                <bitRange>[5:5]</bitRange>
16909                <access>read-write</access>
16910              </field>
16911              <field>
16912                <name>ACTIVE_CH_DISABLED</name>
16913                <description>Mask for INTR.ACTIVE_CH_DISABLED interrupt.</description>
16914                <bitRange>[6:6]</bitRange>
16915                <access>read-write</access>
16916              </field>
16917              <field>
16918                <name>DESCR_BUS_ERROR</name>
16919                <description>Mask for INTR.DESCR_BUS_ERROR interrupt.</description>
16920                <bitRange>[7:7]</bitRange>
16921                <access>read-write</access>
16922              </field>
16923            </fields>
16924          </register>
16925          <register>
16926            <name>INTR_MASKED</name>
16927            <description>Interrupt masked</description>
16928            <addressOffset>0x8C</addressOffset>
16929            <size>32</size>
16930            <access>read-only</access>
16931            <resetValue>0x0</resetValue>
16932            <resetMask>0xFF</resetMask>
16933            <fields>
16934              <field>
16935                <name>COMPLETION</name>
16936                <description>Logical and of corresponding INTR.COMPLETION and INTR_MASK.COMPLETION fields.</description>
16937                <bitRange>[0:0]</bitRange>
16938                <access>read-only</access>
16939              </field>
16940              <field>
16941                <name>SRC_BUS_ERROR</name>
16942                <description>Logical and of corresponding INTR.SRC_BUS_ERROR and INTR_MASK.SRC_BUS_ERROR fields.</description>
16943                <bitRange>[1:1]</bitRange>
16944                <access>read-only</access>
16945              </field>
16946              <field>
16947                <name>DST_BUS_ERROR</name>
16948                <description>Logical and of corresponding INTR.DST_BUS_ERROR and INTR_MASK.DST_BUS_ERROR fields.</description>
16949                <bitRange>[2:2]</bitRange>
16950                <access>read-only</access>
16951              </field>
16952              <field>
16953                <name>SRC_MISAL</name>
16954                <description>Logical and of corresponding INTR.SRC_MISAL and INTR_MASK.SRC_MISAL fields.</description>
16955                <bitRange>[3:3]</bitRange>
16956                <access>read-only</access>
16957              </field>
16958              <field>
16959                <name>DST_MISAL</name>
16960                <description>Logical and of corresponding INTR.DST_MISAL and INTR_MASK.DST_MISAL fields.</description>
16961                <bitRange>[4:4]</bitRange>
16962                <access>read-only</access>
16963              </field>
16964              <field>
16965                <name>CURR_PTR_NULL</name>
16966                <description>Logical and of corresponding INTR.CURR_PTR_NULL and INTR_MASK.CURR_PTR_NULL fields.</description>
16967                <bitRange>[5:5]</bitRange>
16968                <access>read-only</access>
16969              </field>
16970              <field>
16971                <name>ACTIVE_CH_DISABLED</name>
16972                <description>Logical and of corresponding INTR.ACTIVE_CH_DISABLED and INTR_MASK.ACTIVE_CH_DISABLED fields.</description>
16973                <bitRange>[6:6]</bitRange>
16974                <access>read-only</access>
16975              </field>
16976              <field>
16977                <name>DESCR_BUS_ERROR</name>
16978                <description>Logical and of corresponding INTR.DESCR_BUS_ERROR and INTR_MASK.DESCR_BUS_ERROR fields.</description>
16979                <bitRange>[7:7]</bitRange>
16980                <access>read-only</access>
16981              </field>
16982            </fields>
16983          </register>
16984        </cluster>
16985      </registers>
16986    </peripheral>
16987    <peripheral>
16988      <name>EFUSE</name>
16989      <description>EFUSE MXS40 registers</description>
16990      <baseAddress>0x402C0000</baseAddress>
16991      <addressBlock>
16992        <offset>0</offset>
16993        <size>128</size>
16994        <usage>registers</usage>
16995      </addressBlock>
16996      <registers>
16997        <register>
16998          <name>CTL</name>
16999          <description>Control</description>
17000          <addressOffset>0x0</addressOffset>
17001          <size>32</size>
17002          <access>read-write</access>
17003          <resetValue>0x0</resetValue>
17004          <resetMask>0x80000000</resetMask>
17005          <fields>
17006            <field>
17007              <name>ENABLED</name>
17008              <description>IP enable:
17009'0': Disabled. All non-retention registers (command and status registers) are reset to their default value when the IP is disabled. All retention registers retain their value when the IP is disabled.
17010'1': Enabled.</description>
17011              <bitRange>[31:31]</bitRange>
17012              <access>read-write</access>
17013            </field>
17014          </fields>
17015        </register>
17016        <register>
17017          <name>CMD</name>
17018          <description>Command</description>
17019          <addressOffset>0x10</addressOffset>
17020          <size>32</size>
17021          <access>read-write</access>
17022          <resetValue>0x1</resetValue>
17023          <resetMask>0x800F1F71</resetMask>
17024          <fields>
17025            <field>
17026              <name>BIT_DATA</name>
17027              <description>Bit data. This field specifies the bit value that is to be programmed into the eFUSE macro array. The address of the bit is specified by the BIT_ADDR, BYTE_ADDR, and MACRO_ADDR fields. This bit is a don't care for the MXS40 Macro.</description>
17028              <bitRange>[0:0]</bitRange>
17029              <access>read-write</access>
17030            </field>
17031            <field>
17032              <name>BIT_ADDR</name>
17033              <description>Bit address. This field specifies a bit within a Byte.</description>
17034              <bitRange>[6:4]</bitRange>
17035              <access>read-write</access>
17036            </field>
17037            <field>
17038              <name>BYTE_ADDR</name>
17039              <description>Byte address. This field specifies a Byte within a eFUSE macro (each macro has 32 B).</description>
17040              <bitRange>[12:8]</bitRange>
17041              <access>read-write</access>
17042            </field>
17043            <field>
17044              <name>MACRO_ADDR</name>
17045              <description>Macro address. This field specifies an eFUSE macro.</description>
17046              <bitRange>[19:16]</bitRange>
17047              <access>read-write</access>
17048            </field>
17049            <field>
17050              <name>START</name>
17051              <description>FW sets this field to '1' to start a program operation. HW sets this field to '0' to indicate that the operation has completed.
17052
17053Note: it is good practice to verify the result of a program operation by reading back a programmed eFUSE memory location. Programming can only change an eFUSE memory bit from '0' to '1'; i.e. a programming operation is a 'one-off' operation for each eFUSE memory bit: once a bit is changed to '1', it can NEVER be changed back to '0' as a hardware fuse is blown.
17054
17055Programming a memory bit to '1' requires blowing a fuse and requires an eFUSE macro operation. Therefore, this programmiong operation takes time (as specified by the SEQ_PROGRAM_CTL reguisters). Programming amemory bit to '0' does not require an eFUSE macro operation (it is the default eFUSE macro state). Therefore, this programming operation is almost instantaneous.
17056
17057Note: during a program operation, a read operation can not be performed. An AHB-Lite read transfer to the eFUSE memory during a program operation results in an AHB-Lite bus error.</description>
17058              <bitRange>[31:31]</bitRange>
17059              <access>read-write</access>
17060            </field>
17061          </fields>
17062        </register>
17063        <register>
17064          <name>SEQ_DEFAULT</name>
17065          <description>Sequencer Default value</description>
17066          <addressOffset>0x20</addressOffset>
17067          <size>32</size>
17068          <access>read-write</access>
17069          <resetValue>0x1D0000</resetValue>
17070          <resetMask>0x7F0000</resetMask>
17071          <fields>
17072            <field>
17073              <name>STROBE_A</name>
17074              <description>Specifies value of eFUSE control signal strobe_f</description>
17075              <bitRange>[16:16]</bitRange>
17076              <access>read-write</access>
17077            </field>
17078            <field>
17079              <name>STROBE_B</name>
17080              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
17081              <bitRange>[17:17]</bitRange>
17082              <access>read-write</access>
17083            </field>
17084            <field>
17085              <name>STROBE_C</name>
17086              <description>Specifies value of eFUSE control signal strobe_c</description>
17087              <bitRange>[18:18]</bitRange>
17088              <access>read-write</access>
17089            </field>
17090            <field>
17091              <name>STROBE_D</name>
17092              <description>Specifies value of eFUSE control signal strobe_d</description>
17093              <bitRange>[19:19]</bitRange>
17094              <access>read-write</access>
17095            </field>
17096            <field>
17097              <name>STROBE_E</name>
17098              <description>Specifies value of eFUSE control signal strobe_e</description>
17099              <bitRange>[20:20]</bitRange>
17100              <access>read-write</access>
17101            </field>
17102            <field>
17103              <name>STROBE_F</name>
17104              <description>Specifies value of eFUSE control signal strobe_f</description>
17105              <bitRange>[21:21]</bitRange>
17106              <access>read-write</access>
17107            </field>
17108            <field>
17109              <name>STROBE_G</name>
17110              <description>Specifies value of eFUSE control signal strobe_g</description>
17111              <bitRange>[22:22]</bitRange>
17112              <access>read-write</access>
17113            </field>
17114          </fields>
17115        </register>
17116        <register>
17117          <name>SEQ_READ_CTL_0</name>
17118          <description>Sequencer read control 0</description>
17119          <addressOffset>0x40</addressOffset>
17120          <size>32</size>
17121          <access>read-write</access>
17122          <resetValue>0x80560001</resetValue>
17123          <resetMask>0x807F03FF</resetMask>
17124          <fields>
17125            <field>
17126              <name>CYCLES</name>
17127              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
17128              <bitRange>[9:0]</bitRange>
17129              <access>read-write</access>
17130            </field>
17131            <field>
17132              <name>STROBE_A</name>
17133              <description>Specifies value of eFUSE control signal strobe_f</description>
17134              <bitRange>[16:16]</bitRange>
17135              <access>read-write</access>
17136            </field>
17137            <field>
17138              <name>STROBE_B</name>
17139              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
17140              <bitRange>[17:17]</bitRange>
17141              <access>read-write</access>
17142            </field>
17143            <field>
17144              <name>STROBE_C</name>
17145              <description>Specifies value of eFUSE control signal strobe_c</description>
17146              <bitRange>[18:18]</bitRange>
17147              <access>read-write</access>
17148            </field>
17149            <field>
17150              <name>STROBE_D</name>
17151              <description>Specifies value of eFUSE control signal strobe_d</description>
17152              <bitRange>[19:19]</bitRange>
17153              <access>read-write</access>
17154            </field>
17155            <field>
17156              <name>STROBE_E</name>
17157              <description>Specifies value of eFUSE control signal strobe_e</description>
17158              <bitRange>[20:20]</bitRange>
17159              <access>read-write</access>
17160            </field>
17161            <field>
17162              <name>STROBE_F</name>
17163              <description>Specifies value of eFUSE control signal strobe_f</description>
17164              <bitRange>[21:21]</bitRange>
17165              <access>read-write</access>
17166            </field>
17167            <field>
17168              <name>STROBE_G</name>
17169              <description>Specifies value of eFUSE control signal strobe_g</description>
17170              <bitRange>[22:22]</bitRange>
17171              <access>read-write</access>
17172            </field>
17173            <field>
17174              <name>DONE</name>
17175              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
17176              <bitRange>[31:31]</bitRange>
17177              <access>read-write</access>
17178            </field>
17179          </fields>
17180        </register>
17181        <register>
17182          <name>SEQ_READ_CTL_1</name>
17183          <description>Sequencer read control 1</description>
17184          <addressOffset>0x44</addressOffset>
17185          <size>32</size>
17186          <access>read-write</access>
17187          <resetValue>0x540004</resetValue>
17188          <resetMask>0x807F03FF</resetMask>
17189          <fields>
17190            <field>
17191              <name>CYCLES</name>
17192              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
17193              <bitRange>[9:0]</bitRange>
17194              <access>read-write</access>
17195            </field>
17196            <field>
17197              <name>STROBE_A</name>
17198              <description>Specifies value of eFUSE control signal strobe_f</description>
17199              <bitRange>[16:16]</bitRange>
17200              <access>read-write</access>
17201            </field>
17202            <field>
17203              <name>STROBE_B</name>
17204              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
17205              <bitRange>[17:17]</bitRange>
17206              <access>read-write</access>
17207            </field>
17208            <field>
17209              <name>STROBE_C</name>
17210              <description>Specifies value of eFUSE control signal strobe_c</description>
17211              <bitRange>[18:18]</bitRange>
17212              <access>read-write</access>
17213            </field>
17214            <field>
17215              <name>STROBE_D</name>
17216              <description>Specifies value of eFUSE control signal strobe_d</description>
17217              <bitRange>[19:19]</bitRange>
17218              <access>read-write</access>
17219            </field>
17220            <field>
17221              <name>STROBE_E</name>
17222              <description>Specifies value of eFUSE control signal strobe_e</description>
17223              <bitRange>[20:20]</bitRange>
17224              <access>read-write</access>
17225            </field>
17226            <field>
17227              <name>STROBE_F</name>
17228              <description>Specifies value of eFUSE control signal strobe_f</description>
17229              <bitRange>[21:21]</bitRange>
17230              <access>read-write</access>
17231            </field>
17232            <field>
17233              <name>STROBE_G</name>
17234              <description>Specifies value of eFUSE control signal strobe_g</description>
17235              <bitRange>[22:22]</bitRange>
17236              <access>read-write</access>
17237            </field>
17238            <field>
17239              <name>DONE</name>
17240              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
17241              <bitRange>[31:31]</bitRange>
17242              <access>read-write</access>
17243            </field>
17244          </fields>
17245        </register>
17246        <register>
17247          <name>SEQ_READ_CTL_2</name>
17248          <description>Sequencer read control 2</description>
17249          <addressOffset>0x48</addressOffset>
17250          <size>32</size>
17251          <access>read-write</access>
17252          <resetValue>0x560001</resetValue>
17253          <resetMask>0x807F03FF</resetMask>
17254          <fields>
17255            <field>
17256              <name>CYCLES</name>
17257              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
17258              <bitRange>[9:0]</bitRange>
17259              <access>read-write</access>
17260            </field>
17261            <field>
17262              <name>STROBE_A</name>
17263              <description>Specifies value of eFUSE control signal strobe_f</description>
17264              <bitRange>[16:16]</bitRange>
17265              <access>read-write</access>
17266            </field>
17267            <field>
17268              <name>STROBE_B</name>
17269              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
17270              <bitRange>[17:17]</bitRange>
17271              <access>read-write</access>
17272            </field>
17273            <field>
17274              <name>STROBE_C</name>
17275              <description>Specifies value of eFUSE control signal strobe_c</description>
17276              <bitRange>[18:18]</bitRange>
17277              <access>read-write</access>
17278            </field>
17279            <field>
17280              <name>STROBE_D</name>
17281              <description>Specifies value of eFUSE control signal strobe_d</description>
17282              <bitRange>[19:19]</bitRange>
17283              <access>read-write</access>
17284            </field>
17285            <field>
17286              <name>STROBE_E</name>
17287              <description>Specifies value of eFUSE control signal strobe_e</description>
17288              <bitRange>[20:20]</bitRange>
17289              <access>read-write</access>
17290            </field>
17291            <field>
17292              <name>STROBE_F</name>
17293              <description>Specifies value of eFUSE control signal strobe_f</description>
17294              <bitRange>[21:21]</bitRange>
17295              <access>read-write</access>
17296            </field>
17297            <field>
17298              <name>STROBE_G</name>
17299              <description>Specifies value of eFUSE control signal strobe_g</description>
17300              <bitRange>[22:22]</bitRange>
17301              <access>read-write</access>
17302            </field>
17303            <field>
17304              <name>DONE</name>
17305              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
17306              <bitRange>[31:31]</bitRange>
17307              <access>read-write</access>
17308            </field>
17309          </fields>
17310        </register>
17311        <register>
17312          <name>SEQ_READ_CTL_3</name>
17313          <description>Sequencer read control 3</description>
17314          <addressOffset>0x4C</addressOffset>
17315          <size>32</size>
17316          <access>read-write</access>
17317          <resetValue>0x540003</resetValue>
17318          <resetMask>0x807F03FF</resetMask>
17319          <fields>
17320            <field>
17321              <name>CYCLES</name>
17322              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
17323              <bitRange>[9:0]</bitRange>
17324              <access>read-write</access>
17325            </field>
17326            <field>
17327              <name>STROBE_A</name>
17328              <description>Specifies value of eFUSE control signal strobe_f</description>
17329              <bitRange>[16:16]</bitRange>
17330              <access>read-write</access>
17331            </field>
17332            <field>
17333              <name>STROBE_B</name>
17334              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
17335              <bitRange>[17:17]</bitRange>
17336              <access>read-write</access>
17337            </field>
17338            <field>
17339              <name>STROBE_C</name>
17340              <description>Specifies value of eFUSE control signal strobe_c</description>
17341              <bitRange>[18:18]</bitRange>
17342              <access>read-write</access>
17343            </field>
17344            <field>
17345              <name>STROBE_D</name>
17346              <description>Specifies value of eFUSE control signal strobe_d</description>
17347              <bitRange>[19:19]</bitRange>
17348              <access>read-write</access>
17349            </field>
17350            <field>
17351              <name>STROBE_E</name>
17352              <description>Specifies value of eFUSE control signal strobe_e</description>
17353              <bitRange>[20:20]</bitRange>
17354              <access>read-write</access>
17355            </field>
17356            <field>
17357              <name>STROBE_F</name>
17358              <description>Specifies value of eFUSE control signal strobe_f</description>
17359              <bitRange>[21:21]</bitRange>
17360              <access>read-write</access>
17361            </field>
17362            <field>
17363              <name>STROBE_G</name>
17364              <description>Specifies value of eFUSE control signal strobe_g</description>
17365              <bitRange>[22:22]</bitRange>
17366              <access>read-write</access>
17367            </field>
17368            <field>
17369              <name>DONE</name>
17370              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
17371              <bitRange>[31:31]</bitRange>
17372              <access>read-write</access>
17373            </field>
17374          </fields>
17375        </register>
17376        <register>
17377          <name>SEQ_READ_CTL_4</name>
17378          <description>Sequencer read control 4</description>
17379          <addressOffset>0x50</addressOffset>
17380          <size>32</size>
17381          <access>read-write</access>
17382          <resetValue>0x80150001</resetValue>
17383          <resetMask>0x807F03FF</resetMask>
17384          <fields>
17385            <field>
17386              <name>CYCLES</name>
17387              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
17388              <bitRange>[9:0]</bitRange>
17389              <access>read-write</access>
17390            </field>
17391            <field>
17392              <name>STROBE_A</name>
17393              <description>Specifies value of eFUSE control signal strobe_f</description>
17394              <bitRange>[16:16]</bitRange>
17395              <access>read-write</access>
17396            </field>
17397            <field>
17398              <name>STROBE_B</name>
17399              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
17400              <bitRange>[17:17]</bitRange>
17401              <access>read-write</access>
17402            </field>
17403            <field>
17404              <name>STROBE_C</name>
17405              <description>Specifies value of eFUSE control signal strobe_c</description>
17406              <bitRange>[18:18]</bitRange>
17407              <access>read-write</access>
17408            </field>
17409            <field>
17410              <name>STROBE_D</name>
17411              <description>Specifies value of eFUSE control signal strobe_d</description>
17412              <bitRange>[19:19]</bitRange>
17413              <access>read-write</access>
17414            </field>
17415            <field>
17416              <name>STROBE_E</name>
17417              <description>Specifies value of eFUSE control signal strobe_e</description>
17418              <bitRange>[20:20]</bitRange>
17419              <access>read-write</access>
17420            </field>
17421            <field>
17422              <name>STROBE_F</name>
17423              <description>Specifies value of eFUSE control signal strobe_f</description>
17424              <bitRange>[21:21]</bitRange>
17425              <access>read-write</access>
17426            </field>
17427            <field>
17428              <name>STROBE_G</name>
17429              <description>Specifies value of eFUSE control signal strobe_g</description>
17430              <bitRange>[22:22]</bitRange>
17431              <access>read-write</access>
17432            </field>
17433            <field>
17434              <name>DONE</name>
17435              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
17436              <bitRange>[31:31]</bitRange>
17437              <access>read-write</access>
17438            </field>
17439          </fields>
17440        </register>
17441        <register>
17442          <name>SEQ_READ_CTL_5</name>
17443          <description>Sequencer read control 5</description>
17444          <addressOffset>0x54</addressOffset>
17445          <size>32</size>
17446          <access>read-write</access>
17447          <resetValue>0x310004</resetValue>
17448          <resetMask>0x807F03FF</resetMask>
17449          <fields>
17450            <field>
17451              <name>CYCLES</name>
17452              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
17453              <bitRange>[9:0]</bitRange>
17454              <access>read-write</access>
17455            </field>
17456            <field>
17457              <name>STROBE_A</name>
17458              <description>Specifies value of eFUSE control signal strobe_f</description>
17459              <bitRange>[16:16]</bitRange>
17460              <access>read-write</access>
17461            </field>
17462            <field>
17463              <name>STROBE_B</name>
17464              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
17465              <bitRange>[17:17]</bitRange>
17466              <access>read-write</access>
17467            </field>
17468            <field>
17469              <name>STROBE_C</name>
17470              <description>Specifies value of eFUSE control signal strobe_c</description>
17471              <bitRange>[18:18]</bitRange>
17472              <access>read-write</access>
17473            </field>
17474            <field>
17475              <name>STROBE_D</name>
17476              <description>Specifies value of eFUSE control signal strobe_d</description>
17477              <bitRange>[19:19]</bitRange>
17478              <access>read-write</access>
17479            </field>
17480            <field>
17481              <name>STROBE_E</name>
17482              <description>Specifies value of eFUSE control signal strobe_e</description>
17483              <bitRange>[20:20]</bitRange>
17484              <access>read-write</access>
17485            </field>
17486            <field>
17487              <name>STROBE_F</name>
17488              <description>Specifies value of eFUSE control signal strobe_f</description>
17489              <bitRange>[21:21]</bitRange>
17490              <access>read-write</access>
17491            </field>
17492            <field>
17493              <name>STROBE_G</name>
17494              <description>Specifies value of eFUSE control signal strobe_g</description>
17495              <bitRange>[22:22]</bitRange>
17496              <access>read-write</access>
17497            </field>
17498            <field>
17499              <name>DONE</name>
17500              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
17501              <bitRange>[31:31]</bitRange>
17502              <access>read-write</access>
17503            </field>
17504          </fields>
17505        </register>
17506        <register>
17507          <name>SEQ_PROGRAM_CTL_0</name>
17508          <description>Sequencer program control 0</description>
17509          <addressOffset>0x60</addressOffset>
17510          <size>32</size>
17511          <access>read-write</access>
17512          <resetValue>0x200001</resetValue>
17513          <resetMask>0x807F03FF</resetMask>
17514          <fields>
17515            <field>
17516              <name>CYCLES</name>
17517              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
17518              <bitRange>[9:0]</bitRange>
17519              <access>read-write</access>
17520            </field>
17521            <field>
17522              <name>STROBE_A</name>
17523              <description>Specifies value of eFUSE control signal strobe_a</description>
17524              <bitRange>[16:16]</bitRange>
17525              <access>read-write</access>
17526            </field>
17527            <field>
17528              <name>STROBE_B</name>
17529              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
17530              <bitRange>[17:17]</bitRange>
17531              <access>read-write</access>
17532            </field>
17533            <field>
17534              <name>STROBE_C</name>
17535              <description>Specifies value of eFUSE control signal strobe_c</description>
17536              <bitRange>[18:18]</bitRange>
17537              <access>read-write</access>
17538            </field>
17539            <field>
17540              <name>STROBE_D</name>
17541              <description>Specifies value of eFUSE control signal strobe_d</description>
17542              <bitRange>[19:19]</bitRange>
17543              <access>read-write</access>
17544            </field>
17545            <field>
17546              <name>STROBE_E</name>
17547              <description>Specifies value of eFUSE control signal strobe_e</description>
17548              <bitRange>[20:20]</bitRange>
17549              <access>read-write</access>
17550            </field>
17551            <field>
17552              <name>STROBE_F</name>
17553              <description>Specifies value of eFUSE control signal strobe_f</description>
17554              <bitRange>[21:21]</bitRange>
17555              <access>read-write</access>
17556            </field>
17557            <field>
17558              <name>STROBE_G</name>
17559              <description>Specifies value of eFUSE control signal strobe_g</description>
17560              <bitRange>[22:22]</bitRange>
17561              <access>read-write</access>
17562            </field>
17563            <field>
17564              <name>DONE</name>
17565              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
17566              <bitRange>[31:31]</bitRange>
17567              <access>read-write</access>
17568            </field>
17569          </fields>
17570        </register>
17571        <register>
17572          <name>SEQ_PROGRAM_CTL_1</name>
17573          <description>Sequencer program control 1</description>
17574          <addressOffset>0x64</addressOffset>
17575          <size>32</size>
17576          <access>read-write</access>
17577          <resetValue>0x220020</resetValue>
17578          <resetMask>0x807F03FF</resetMask>
17579          <fields>
17580            <field>
17581              <name>CYCLES</name>
17582              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
17583              <bitRange>[9:0]</bitRange>
17584              <access>read-write</access>
17585            </field>
17586            <field>
17587              <name>STROBE_A</name>
17588              <description>Specifies value of eFUSE control signal strobe_a</description>
17589              <bitRange>[16:16]</bitRange>
17590              <access>read-write</access>
17591            </field>
17592            <field>
17593              <name>STROBE_B</name>
17594              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
17595              <bitRange>[17:17]</bitRange>
17596              <access>read-write</access>
17597            </field>
17598            <field>
17599              <name>STROBE_C</name>
17600              <description>Specifies value of eFUSE control signal strobe_c</description>
17601              <bitRange>[18:18]</bitRange>
17602              <access>read-write</access>
17603            </field>
17604            <field>
17605              <name>STROBE_D</name>
17606              <description>Specifies value of eFUSE control signal strobe_d</description>
17607              <bitRange>[19:19]</bitRange>
17608              <access>read-write</access>
17609            </field>
17610            <field>
17611              <name>STROBE_E</name>
17612              <description>Specifies value of eFUSE control signal strobe_e</description>
17613              <bitRange>[20:20]</bitRange>
17614              <access>read-write</access>
17615            </field>
17616            <field>
17617              <name>STROBE_F</name>
17618              <description>Specifies value of eFUSE control signal strobe_f</description>
17619              <bitRange>[21:21]</bitRange>
17620              <access>read-write</access>
17621            </field>
17622            <field>
17623              <name>STROBE_G</name>
17624              <description>Specifies value of eFUSE control signal strobe_g</description>
17625              <bitRange>[22:22]</bitRange>
17626              <access>read-write</access>
17627            </field>
17628            <field>
17629              <name>DONE</name>
17630              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
17631              <bitRange>[31:31]</bitRange>
17632              <access>read-write</access>
17633            </field>
17634          </fields>
17635        </register>
17636        <register>
17637          <name>SEQ_PROGRAM_CTL_2</name>
17638          <description>Sequencer program control 2</description>
17639          <addressOffset>0x68</addressOffset>
17640          <size>32</size>
17641          <access>read-write</access>
17642          <resetValue>0x200001</resetValue>
17643          <resetMask>0x807F03FF</resetMask>
17644          <fields>
17645            <field>
17646              <name>CYCLES</name>
17647              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
17648              <bitRange>[9:0]</bitRange>
17649              <access>read-write</access>
17650            </field>
17651            <field>
17652              <name>STROBE_A</name>
17653              <description>Specifies value of eFUSE control signal strobe_a</description>
17654              <bitRange>[16:16]</bitRange>
17655              <access>read-write</access>
17656            </field>
17657            <field>
17658              <name>STROBE_B</name>
17659              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
17660              <bitRange>[17:17]</bitRange>
17661              <access>read-write</access>
17662            </field>
17663            <field>
17664              <name>STROBE_C</name>
17665              <description>Specifies value of eFUSE control signal strobe_c</description>
17666              <bitRange>[18:18]</bitRange>
17667              <access>read-write</access>
17668            </field>
17669            <field>
17670              <name>STROBE_D</name>
17671              <description>Specifies value of eFUSE control signal strobe_d</description>
17672              <bitRange>[19:19]</bitRange>
17673              <access>read-write</access>
17674            </field>
17675            <field>
17676              <name>STROBE_E</name>
17677              <description>Specifies value of eFUSE control signal strobe_e</description>
17678              <bitRange>[20:20]</bitRange>
17679              <access>read-write</access>
17680            </field>
17681            <field>
17682              <name>STROBE_F</name>
17683              <description>Specifies value of eFUSE control signal strobe_f</description>
17684              <bitRange>[21:21]</bitRange>
17685              <access>read-write</access>
17686            </field>
17687            <field>
17688              <name>STROBE_G</name>
17689              <description>Specifies value of eFUSE control signal strobe_g</description>
17690              <bitRange>[22:22]</bitRange>
17691              <access>read-write</access>
17692            </field>
17693            <field>
17694              <name>DONE</name>
17695              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
17696              <bitRange>[31:31]</bitRange>
17697              <access>read-write</access>
17698            </field>
17699          </fields>
17700        </register>
17701        <register>
17702          <name>SEQ_PROGRAM_CTL_3</name>
17703          <description>Sequencer program control 3</description>
17704          <addressOffset>0x6C</addressOffset>
17705          <size>32</size>
17706          <access>read-write</access>
17707          <resetValue>0x310005</resetValue>
17708          <resetMask>0x807F03FF</resetMask>
17709          <fields>
17710            <field>
17711              <name>CYCLES</name>
17712              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
17713              <bitRange>[9:0]</bitRange>
17714              <access>read-write</access>
17715            </field>
17716            <field>
17717              <name>STROBE_A</name>
17718              <description>Specifies value of eFUSE control signal strobe_a</description>
17719              <bitRange>[16:16]</bitRange>
17720              <access>read-write</access>
17721            </field>
17722            <field>
17723              <name>STROBE_B</name>
17724              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
17725              <bitRange>[17:17]</bitRange>
17726              <access>read-write</access>
17727            </field>
17728            <field>
17729              <name>STROBE_C</name>
17730              <description>Specifies value of eFUSE control signal strobe_c</description>
17731              <bitRange>[18:18]</bitRange>
17732              <access>read-write</access>
17733            </field>
17734            <field>
17735              <name>STROBE_D</name>
17736              <description>Specifies value of eFUSE control signal strobe_d</description>
17737              <bitRange>[19:19]</bitRange>
17738              <access>read-write</access>
17739            </field>
17740            <field>
17741              <name>STROBE_E</name>
17742              <description>Specifies value of eFUSE control signal strobe_e</description>
17743              <bitRange>[20:20]</bitRange>
17744              <access>read-write</access>
17745            </field>
17746            <field>
17747              <name>STROBE_F</name>
17748              <description>Specifies value of eFUSE control signal strobe_f</description>
17749              <bitRange>[21:21]</bitRange>
17750              <access>read-write</access>
17751            </field>
17752            <field>
17753              <name>STROBE_G</name>
17754              <description>Specifies value of eFUSE control signal strobe_g</description>
17755              <bitRange>[22:22]</bitRange>
17756              <access>read-write</access>
17757            </field>
17758            <field>
17759              <name>DONE</name>
17760              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
17761              <bitRange>[31:31]</bitRange>
17762              <access>read-write</access>
17763            </field>
17764          </fields>
17765        </register>
17766        <register>
17767          <name>SEQ_PROGRAM_CTL_4</name>
17768          <description>Sequencer program control 4</description>
17769          <addressOffset>0x70</addressOffset>
17770          <size>32</size>
17771          <access>read-write</access>
17772          <resetValue>0x80350006</resetValue>
17773          <resetMask>0x807F03FF</resetMask>
17774          <fields>
17775            <field>
17776              <name>CYCLES</name>
17777              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
17778              <bitRange>[9:0]</bitRange>
17779              <access>read-write</access>
17780            </field>
17781            <field>
17782              <name>STROBE_A</name>
17783              <description>Specifies value of eFUSE control signal strobe_a</description>
17784              <bitRange>[16:16]</bitRange>
17785              <access>read-write</access>
17786            </field>
17787            <field>
17788              <name>STROBE_B</name>
17789              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
17790              <bitRange>[17:17]</bitRange>
17791              <access>read-write</access>
17792            </field>
17793            <field>
17794              <name>STROBE_C</name>
17795              <description>Specifies value of eFUSE control signal strobe_c</description>
17796              <bitRange>[18:18]</bitRange>
17797              <access>read-write</access>
17798            </field>
17799            <field>
17800              <name>STROBE_D</name>
17801              <description>Specifies value of eFUSE control signal strobe_d</description>
17802              <bitRange>[19:19]</bitRange>
17803              <access>read-write</access>
17804            </field>
17805            <field>
17806              <name>STROBE_E</name>
17807              <description>Specifies value of eFUSE control signal strobe_e</description>
17808              <bitRange>[20:20]</bitRange>
17809              <access>read-write</access>
17810            </field>
17811            <field>
17812              <name>STROBE_F</name>
17813              <description>Specifies value of eFUSE control signal strobe_f</description>
17814              <bitRange>[21:21]</bitRange>
17815              <access>read-write</access>
17816            </field>
17817            <field>
17818              <name>STROBE_G</name>
17819              <description>Specifies value of eFUSE control signal strobe_g</description>
17820              <bitRange>[22:22]</bitRange>
17821              <access>read-write</access>
17822            </field>
17823            <field>
17824              <name>DONE</name>
17825              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
17826              <bitRange>[31:31]</bitRange>
17827              <access>read-write</access>
17828            </field>
17829          </fields>
17830        </register>
17831        <register>
17832          <name>SEQ_PROGRAM_CTL_5</name>
17833          <description>Sequencer program control 5</description>
17834          <addressOffset>0x74</addressOffset>
17835          <size>32</size>
17836          <access>read-write</access>
17837          <resetValue>0x803D0019</resetValue>
17838          <resetMask>0x807F03FF</resetMask>
17839          <fields>
17840            <field>
17841              <name>CYCLES</name>
17842              <description>Number of IP clock cycles (minus 1). This field is in the range of [0, 1023], allowing for a time of [1, 1024] IP clock cycles.</description>
17843              <bitRange>[9:0]</bitRange>
17844              <access>read-write</access>
17845            </field>
17846            <field>
17847              <name>STROBE_A</name>
17848              <description>Specifies value of eFUSE control signal strobe_a</description>
17849              <bitRange>[16:16]</bitRange>
17850              <access>read-write</access>
17851            </field>
17852            <field>
17853              <name>STROBE_B</name>
17854              <description>Specifies value of eFUSEcontrol signal strobe_b</description>
17855              <bitRange>[17:17]</bitRange>
17856              <access>read-write</access>
17857            </field>
17858            <field>
17859              <name>STROBE_C</name>
17860              <description>Specifies value of eFUSE control signal strobe_c</description>
17861              <bitRange>[18:18]</bitRange>
17862              <access>read-write</access>
17863            </field>
17864            <field>
17865              <name>STROBE_D</name>
17866              <description>Specifies value of eFUSE control signal strobe_d</description>
17867              <bitRange>[19:19]</bitRange>
17868              <access>read-write</access>
17869            </field>
17870            <field>
17871              <name>STROBE_E</name>
17872              <description>Specifies value of eFUSE control signal strobe_e</description>
17873              <bitRange>[20:20]</bitRange>
17874              <access>read-write</access>
17875            </field>
17876            <field>
17877              <name>STROBE_F</name>
17878              <description>Specifies value of eFUSE control signal strobe_f</description>
17879              <bitRange>[21:21]</bitRange>
17880              <access>read-write</access>
17881            </field>
17882            <field>
17883              <name>STROBE_G</name>
17884              <description>Specifies value of eFUSE control signal strobe_g</description>
17885              <bitRange>[22:22]</bitRange>
17886              <access>read-write</access>
17887            </field>
17888            <field>
17889              <name>DONE</name>
17890              <description>When set to 1 indicates that the Read cycle ends when the current cycle count reaches 0.</description>
17891              <bitRange>[31:31]</bitRange>
17892              <access>read-write</access>
17893            </field>
17894          </fields>
17895        </register>
17896      </registers>
17897    </peripheral>
17898    <peripheral>
17899      <name>PROFILE</name>
17900      <description>Energy Profiler IP</description>
17901      <baseAddress>0x402D0000</baseAddress>
17902      <addressBlock>
17903        <offset>0</offset>
17904        <size>65536</size>
17905        <usage>registers</usage>
17906      </addressBlock>
17907      <registers>
17908        <register>
17909          <name>CTL</name>
17910          <description>Profile control</description>
17911          <addressOffset>0x0</addressOffset>
17912          <size>32</size>
17913          <access>read-write</access>
17914          <resetValue>0x0</resetValue>
17915          <resetMask>0x80000001</resetMask>
17916          <fields>
17917            <field>
17918              <name>WIN_MODE</name>
17919              <description>Specifies the profiling time window mode:
17920'0': Start / stop mode. The profiling time window is started when a rising edge of the start trigger signal occurs and stopped when a rising edge of the stop trigger signal occurs.
17921In case both rising edges (of start and stop trigger signals) occur in the same cycle, the profiling time window is stopped.
17922'1': Enable mode. The profiling time window is active as long as the start 'trigger' signal is active. The stop trigger signal has no effect.</description>
17923              <bitRange>[0:0]</bitRange>
17924              <access>read-write</access>
17925            </field>
17926            <field>
17927              <name>ENABLED</name>
17928              <description>Enables the profiling block:
17929'0': Disabled.
17930'1': Enabled.</description>
17931              <bitRange>[31:31]</bitRange>
17932              <access>read-write</access>
17933            </field>
17934          </fields>
17935        </register>
17936        <register>
17937          <name>STATUS</name>
17938          <description>Profile status</description>
17939          <addressOffset>0x4</addressOffset>
17940          <size>32</size>
17941          <access>read-only</access>
17942          <resetValue>0x0</resetValue>
17943          <resetMask>0x1</resetMask>
17944          <fields>
17945            <field>
17946              <name>WIN_ACTIVE</name>
17947              <description>Indicates if the profiling time window is active.
17948'0': Not active.
17949'1': Active.</description>
17950              <bitRange>[0:0]</bitRange>
17951              <access>read-only</access>
17952            </field>
17953          </fields>
17954        </register>
17955        <register>
17956          <name>CMD</name>
17957          <description>Profile command</description>
17958          <addressOffset>0x10</addressOffset>
17959          <size>32</size>
17960          <access>read-write</access>
17961          <resetValue>0x0</resetValue>
17962          <resetMask>0x103</resetMask>
17963          <fields>
17964            <field>
17965              <name>START_TR</name>
17966              <description>Software start trigger for the profiling time window. When written with '1', the profiling time window is started.
17967Can only be used in start / stop mode (PROFILE_WIN_MODE=0).
17968Has no effect in enable mode (PROFILE_WIN_MODE=1).</description>
17969              <bitRange>[0:0]</bitRange>
17970              <access>read-write</access>
17971            </field>
17972            <field>
17973              <name>STOP_TR</name>
17974              <description>Software stop trigger for the profiling time window. When written with '1', the profiling time window is stopped.
17975Can only be used in start / stop mode (PROFILE_WIN_MODE=0).
17976Has no effect in enable mode (PROFILE_WIN_MODE=1).</description>
17977              <bitRange>[1:1]</bitRange>
17978              <access>read-write</access>
17979            </field>
17980            <field>
17981              <name>CLR_ALL_CNT</name>
17982              <description>Counter clear. When written with '1', all profiling counter registers are cleared to 0x00.</description>
17983              <bitRange>[8:8]</bitRange>
17984              <access>read-write</access>
17985            </field>
17986          </fields>
17987        </register>
17988        <register>
17989          <name>INTR</name>
17990          <description>Profile interrupt</description>
17991          <addressOffset>0x7C0</addressOffset>
17992          <size>32</size>
17993          <access>read-write</access>
17994          <resetValue>0x0</resetValue>
17995          <resetMask>0xFFFFFFFF</resetMask>
17996          <fields>
17997            <field>
17998              <name>CNT_OVFLW</name>
17999              <description>This interrupt cause field is activated (HW sets the field to '1') when an profiling counter overflow (from 0xFFFFFFFF to 0x00000000) is captured. There is one bit per profling counter.
18000
18001SW writes a '1' to a bit of this field to clear this bit to '0' (writing 0xFFFFFFFF clears all interrupt causes to '0').</description>
18002              <bitRange>[31:0]</bitRange>
18003              <access>read-write</access>
18004            </field>
18005          </fields>
18006        </register>
18007        <register>
18008          <name>INTR_SET</name>
18009          <description>Profile interrupt set</description>
18010          <addressOffset>0x7C4</addressOffset>
18011          <size>32</size>
18012          <access>read-write</access>
18013          <resetValue>0x0</resetValue>
18014          <resetMask>0xFFFFFFFF</resetMask>
18015          <fields>
18016            <field>
18017              <name>CNT_OVFLW</name>
18018              <description>SW writes a '1' to a bit of this field to set the corresponding bit in the INTR register.</description>
18019              <bitRange>[31:0]</bitRange>
18020              <access>read-write</access>
18021            </field>
18022          </fields>
18023        </register>
18024        <register>
18025          <name>INTR_MASK</name>
18026          <description>Profile interrupt mask</description>
18027          <addressOffset>0x7C8</addressOffset>
18028          <size>32</size>
18029          <access>read-write</access>
18030          <resetValue>0x0</resetValue>
18031          <resetMask>0xFFFFFFFF</resetMask>
18032          <fields>
18033            <field>
18034              <name>CNT_OVFLW</name>
18035              <description>Mask bit for corresponding field in the INTR register.</description>
18036              <bitRange>[31:0]</bitRange>
18037              <access>read-write</access>
18038            </field>
18039          </fields>
18040        </register>
18041        <register>
18042          <name>INTR_MASKED</name>
18043          <description>Profile interrupt masked</description>
18044          <addressOffset>0x7CC</addressOffset>
18045          <size>32</size>
18046          <access>read-only</access>
18047          <resetValue>0x0</resetValue>
18048          <resetMask>0xFFFFFFFF</resetMask>
18049          <fields>
18050            <field>
18051              <name>CNT_OVFLW</name>
18052              <description>Logical and of corresponding INTR and INTR_MASK fields.</description>
18053              <bitRange>[31:0]</bitRange>
18054              <access>read-only</access>
18055            </field>
18056          </fields>
18057        </register>
18058        <cluster>
18059          <dim>8</dim>
18060          <dimIncrement>16</dimIncrement>
18061          <name>CNT_STRUCT[%s]</name>
18062          <description>Profile counter structure</description>
18063          <addressOffset>0x00000800</addressOffset>
18064          <register>
18065            <name>CTL</name>
18066            <description>Profile counter configuration</description>
18067            <addressOffset>0x0</addressOffset>
18068            <size>32</size>
18069            <access>read-write</access>
18070            <resetValue>0x0</resetValue>
18071            <resetMask>0x807F0071</resetMask>
18072            <fields>
18073              <field>
18074                <name>CNT_DURATION</name>
18075                <description>This field specifies if events (edges) or a duration of the monitor signal is counted.
18076'0': Events are monitored. An edge detection is done. All edges of the selected monitor signal are counted.
18077'1': A duration is monitored. No edge detection is done. The monitored signal is taken as a (high active) level signal for enabling the profiling counter.
18078
18079Note: All monitor signals which only can represent events are edge encoded in hardware, therefore a selection of CTL.CNT_DURATION=1 will not produce meaningful results.</description>
18080                <bitRange>[0:0]</bitRange>
18081                <access>read-write</access>
18082              </field>
18083              <field>
18084                <name>REF_CLK_SEL</name>
18085                <description>This field specifies the reference clock used for a counting time base when counting durations. Has no effect when CTL.CNT_DURATION=0.</description>
18086                <bitRange>[6:4]</bitRange>
18087                <access>read-write</access>
18088                <enumeratedValues>
18089                  <enumeratedValue>
18090                    <name>CLK_TIMER</name>
18091                    <description>Timer clock (divided or undivided high frequency clock, e.g. from IMO). Selection is done in SRSS register CLK_TIMER_CTL.TIMER_SEL.</description>
18092                    <value>0</value>
18093                  </enumeratedValue>
18094                  <enumeratedValue>
18095                    <name>CLK_IMO</name>
18096                    <description>IMO - Internal Main Oscillator</description>
18097                    <value>1</value>
18098                  </enumeratedValue>
18099                  <enumeratedValue>
18100                    <name>CLK_ECO</name>
18101                    <description>ECO - External-Crystal Oscillator</description>
18102                    <value>2</value>
18103                  </enumeratedValue>
18104                  <enumeratedValue>
18105                    <name>CLK_LF</name>
18106                    <description>Low frequency clock (ILO, WCO or ALTLF).
18107Selection is done in SRSS register CLK_SELECT.LFCLK_SEL.</description>
18108                    <value>3</value>
18109                  </enumeratedValue>
18110                  <enumeratedValue>
18111                    <name>CLK_HF</name>
18112                    <description>High frequuency clock ('clk_hfx').</description>
18113                    <value>4</value>
18114                  </enumeratedValue>
18115                  <enumeratedValue>
18116                    <name>CLK_PERI</name>
18117                    <description>Peripheral clock ('clk_peri').</description>
18118                    <value>5</value>
18119                  </enumeratedValue>
18120                  <enumeratedValue>
18121                    <name>RSVD_6</name>
18122                    <description>N/A</description>
18123                    <value>6</value>
18124                  </enumeratedValue>
18125                  <enumeratedValue>
18126                    <name>RSVD_7</name>
18127                    <description>N/A</description>
18128                    <value>7</value>
18129                  </enumeratedValue>
18130                </enumeratedValues>
18131              </field>
18132              <field>
18133                <name>MON_SEL</name>
18134                <description>This field specifies the montior input signal to be observed by the profiling counter.
18135The monitor signals are product specific, see product definition spreadsheet tab 'Monitor' for details.</description>
18136                <bitRange>[22:16]</bitRange>
18137                <access>read-write</access>
18138              </field>
18139              <field>
18140                <name>ENABLED</name>
18141                <description>Enables the profiling counter:
18142'0': Disabled.
18143'1': Enabled.</description>
18144                <bitRange>[31:31]</bitRange>
18145                <access>read-write</access>
18146              </field>
18147            </fields>
18148          </register>
18149          <register>
18150            <name>CNT</name>
18151            <description>Profile counter value</description>
18152            <addressOffset>0x8</addressOffset>
18153            <size>32</size>
18154            <access>read-write</access>
18155            <resetValue>0x0</resetValue>
18156            <resetMask>0xFFFFFFFF</resetMask>
18157            <fields>
18158              <field>
18159                <name>CNT</name>
18160                <description>This field shows / specifies the actual value of the profiling counter. It allows reading as well as writing the profiling counter.</description>
18161                <bitRange>[31:0]</bitRange>
18162                <access>read-write</access>
18163              </field>
18164            </fields>
18165          </register>
18166        </cluster>
18167      </registers>
18168    </peripheral>
18169    <peripheral>
18170      <name>HSIOM</name>
18171      <description>High Speed IO Matrix (HSIOM)</description>
18172      <baseAddress>0x40300000</baseAddress>
18173      <addressBlock>
18174        <offset>0</offset>
18175        <size>16384</size>
18176        <usage>registers</usage>
18177      </addressBlock>
18178      <registers>
18179        <cluster>
18180          <dim>15</dim>
18181          <dimIncrement>16</dimIncrement>
18182          <name>PRT[%s]</name>
18183          <description>HSIOM port registers</description>
18184          <addressOffset>0x00000000</addressOffset>
18185          <register>
18186            <name>PORT_SEL0</name>
18187            <description>Port selection 0</description>
18188            <addressOffset>0x0</addressOffset>
18189            <size>32</size>
18190            <access>read-write</access>
18191            <resetValue>0x0</resetValue>
18192            <resetMask>0x1F1F1F1F</resetMask>
18193            <fields>
18194              <field>
18195                <name>IO0_SEL</name>
18196                <description>Selects connection for IO pin 0 route.</description>
18197                <bitRange>[4:0]</bitRange>
18198                <access>read-write</access>
18199                <enumeratedValues>
18200                  <enumeratedValue>
18201                    <name>GPIO</name>
18202                    <description>GPIO controls 'out'</description>
18203                    <value>0</value>
18204                  </enumeratedValue>
18205                  <enumeratedValue>
18206                    <name>GPIO_DSI</name>
18207                    <description>GPIO controls 'out', DSI controls 'output enable'</description>
18208                    <value>1</value>
18209                  </enumeratedValue>
18210                  <enumeratedValue>
18211                    <name>DSI_DSI</name>
18212                    <description>DSI controls 'out' and 'output enable'</description>
18213                    <value>2</value>
18214                  </enumeratedValue>
18215                  <enumeratedValue>
18216                    <name>DSI_GPIO</name>
18217                    <description>DSI controls 'out', GPIO controls 'output enable'</description>
18218                    <value>3</value>
18219                  </enumeratedValue>
18220                  <enumeratedValue>
18221                    <name>AMUXA</name>
18222                    <description>Analog mux bus A</description>
18223                    <value>4</value>
18224                  </enumeratedValue>
18225                  <enumeratedValue>
18226                    <name>AMUXB</name>
18227                    <description>Analog mux bus B</description>
18228                    <value>5</value>
18229                  </enumeratedValue>
18230                  <enumeratedValue>
18231                    <name>AMUXA_DSI</name>
18232                    <description>Analog mux bus A, DSI control</description>
18233                    <value>6</value>
18234                  </enumeratedValue>
18235                  <enumeratedValue>
18236                    <name>AMUXB_DSI</name>
18237                    <description>Analog mux bus B, DSI control</description>
18238                    <value>7</value>
18239                  </enumeratedValue>
18240                  <enumeratedValue>
18241                    <name>ACT_0</name>
18242                    <description>Active functionality 0</description>
18243                    <value>8</value>
18244                  </enumeratedValue>
18245                  <enumeratedValue>
18246                    <name>ACT_1</name>
18247                    <description>Active functionality 1</description>
18248                    <value>9</value>
18249                  </enumeratedValue>
18250                  <enumeratedValue>
18251                    <name>ACT_2</name>
18252                    <description>Active functionality 2</description>
18253                    <value>10</value>
18254                  </enumeratedValue>
18255                  <enumeratedValue>
18256                    <name>ACT_3</name>
18257                    <description>Active functionality 3</description>
18258                    <value>11</value>
18259                  </enumeratedValue>
18260                  <enumeratedValue>
18261                    <name>DS_0</name>
18262                    <description>DeepSleep functionality 0</description>
18263                    <value>12</value>
18264                  </enumeratedValue>
18265                  <enumeratedValue>
18266                    <name>DS_1</name>
18267                    <description>DeepSleep functionality 1</description>
18268                    <value>13</value>
18269                  </enumeratedValue>
18270                  <enumeratedValue>
18271                    <name>DS_2</name>
18272                    <description>DeepSleep functionality 2</description>
18273                    <value>14</value>
18274                  </enumeratedValue>
18275                  <enumeratedValue>
18276                    <name>DS_3</name>
18277                    <description>DeepSleep functionality 3</description>
18278                    <value>15</value>
18279                  </enumeratedValue>
18280                  <enumeratedValue>
18281                    <name>ACT_4</name>
18282                    <description>Active functionality 4</description>
18283                    <value>16</value>
18284                  </enumeratedValue>
18285                  <enumeratedValue>
18286                    <name>ACT_5</name>
18287                    <description>Active functionality 5</description>
18288                    <value>17</value>
18289                  </enumeratedValue>
18290                  <enumeratedValue>
18291                    <name>ACT_6</name>
18292                    <description>Active functionality 6</description>
18293                    <value>18</value>
18294                  </enumeratedValue>
18295                  <enumeratedValue>
18296                    <name>ACT_7</name>
18297                    <description>Active functionality 7</description>
18298                    <value>19</value>
18299                  </enumeratedValue>
18300                  <enumeratedValue>
18301                    <name>ACT_8</name>
18302                    <description>Active functionality 8</description>
18303                    <value>20</value>
18304                  </enumeratedValue>
18305                  <enumeratedValue>
18306                    <name>ACT_9</name>
18307                    <description>Active functionality 9</description>
18308                    <value>21</value>
18309                  </enumeratedValue>
18310                  <enumeratedValue>
18311                    <name>ACT_10</name>
18312                    <description>Active functionality 10</description>
18313                    <value>22</value>
18314                  </enumeratedValue>
18315                  <enumeratedValue>
18316                    <name>ACT_11</name>
18317                    <description>Active functionality 11</description>
18318                    <value>23</value>
18319                  </enumeratedValue>
18320                  <enumeratedValue>
18321                    <name>ACT_12</name>
18322                    <description>Active functionality 12</description>
18323                    <value>24</value>
18324                  </enumeratedValue>
18325                  <enumeratedValue>
18326                    <name>ACT_13</name>
18327                    <description>Active functionality 13</description>
18328                    <value>25</value>
18329                  </enumeratedValue>
18330                  <enumeratedValue>
18331                    <name>ACT_14</name>
18332                    <description>Active functionality 14</description>
18333                    <value>26</value>
18334                  </enumeratedValue>
18335                  <enumeratedValue>
18336                    <name>ACT_15</name>
18337                    <description>Active functionality 15</description>
18338                    <value>27</value>
18339                  </enumeratedValue>
18340                  <enumeratedValue>
18341                    <name>DS_4</name>
18342                    <description>DeepSleep functionality 4</description>
18343                    <value>28</value>
18344                  </enumeratedValue>
18345                  <enumeratedValue>
18346                    <name>DS_5</name>
18347                    <description>DeepSleep functionality 5</description>
18348                    <value>29</value>
18349                  </enumeratedValue>
18350                  <enumeratedValue>
18351                    <name>DS_6</name>
18352                    <description>DeepSleep functionality 6</description>
18353                    <value>30</value>
18354                  </enumeratedValue>
18355                  <enumeratedValue>
18356                    <name>DS_7</name>
18357                    <description>DeepSleep functionality 7</description>
18358                    <value>31</value>
18359                  </enumeratedValue>
18360                </enumeratedValues>
18361              </field>
18362              <field>
18363                <name>IO1_SEL</name>
18364                <description>Selects connection for IO pin 1 route.</description>
18365                <bitRange>[12:8]</bitRange>
18366                <access>read-write</access>
18367              </field>
18368              <field>
18369                <name>IO2_SEL</name>
18370                <description>Selects connection for IO pin 2 route.</description>
18371                <bitRange>[20:16]</bitRange>
18372                <access>read-write</access>
18373              </field>
18374              <field>
18375                <name>IO3_SEL</name>
18376                <description>Selects connection for IO pin 3 route.</description>
18377                <bitRange>[28:24]</bitRange>
18378                <access>read-write</access>
18379              </field>
18380            </fields>
18381          </register>
18382          <register>
18383            <name>PORT_SEL1</name>
18384            <description>Port selection 1</description>
18385            <addressOffset>0x4</addressOffset>
18386            <size>32</size>
18387            <access>read-write</access>
18388            <resetValue>0x0</resetValue>
18389            <resetMask>0x1F1F1F1F</resetMask>
18390            <fields>
18391              <field>
18392                <name>IO4_SEL</name>
18393                <description>Selects connection for IO pin 4 route.
18394See PORT_SEL0 for connection details.</description>
18395                <bitRange>[4:0]</bitRange>
18396                <access>read-write</access>
18397              </field>
18398              <field>
18399                <name>IO5_SEL</name>
18400                <description>Selects connection for IO pin 5 route.</description>
18401                <bitRange>[12:8]</bitRange>
18402                <access>read-write</access>
18403              </field>
18404              <field>
18405                <name>IO6_SEL</name>
18406                <description>Selects connection for IO pin 6 route.</description>
18407                <bitRange>[20:16]</bitRange>
18408                <access>read-write</access>
18409              </field>
18410              <field>
18411                <name>IO7_SEL</name>
18412                <description>Selects connection for IO pin 7 route.</description>
18413                <bitRange>[28:24]</bitRange>
18414                <access>read-write</access>
18415              </field>
18416            </fields>
18417          </register>
18418        </cluster>
18419        <register>
18420          <dim>64</dim>
18421          <dimIncrement>4</dimIncrement>
18422          <name>AMUX_SPLIT_CTL[%s]</name>
18423          <description>AMUX splitter cell control</description>
18424          <addressOffset>0x2000</addressOffset>
18425          <size>32</size>
18426          <access>read-write</access>
18427          <resetValue>0x0</resetValue>
18428          <resetMask>0x77</resetMask>
18429          <fields>
18430            <field>
18431              <name>SWITCH_AA_SL</name>
18432              <description>T-switch control for Left AMUXBUSA switch:
18433'0': switch open.
18434'1': switch closed.</description>
18435              <bitRange>[0:0]</bitRange>
18436              <access>read-write</access>
18437            </field>
18438            <field>
18439              <name>SWITCH_AA_SR</name>
18440              <description>T-switch control for Right AMUXBUSA switch:
18441'0': switch open.
18442'1': switch closed.</description>
18443              <bitRange>[1:1]</bitRange>
18444              <access>read-write</access>
18445            </field>
18446            <field>
18447              <name>SWITCH_AA_S0</name>
18448              <description>T-switch control for AMUXBUSA vssa/ground switch:
18449'0': switch open.
18450'1': switch closed.</description>
18451              <bitRange>[2:2]</bitRange>
18452              <access>read-write</access>
18453            </field>
18454            <field>
18455              <name>SWITCH_BB_SL</name>
18456              <description>T-switch control for Left AMUXBUSB switch.</description>
18457              <bitRange>[4:4]</bitRange>
18458              <access>read-write</access>
18459            </field>
18460            <field>
18461              <name>SWITCH_BB_SR</name>
18462              <description>T-switch control for Right AMUXBUSB switch.</description>
18463              <bitRange>[5:5]</bitRange>
18464              <access>read-write</access>
18465            </field>
18466            <field>
18467              <name>SWITCH_BB_S0</name>
18468              <description>T-switch control for AMUXBUSB vssa/ground switch.</description>
18469              <bitRange>[6:6]</bitRange>
18470              <access>read-write</access>
18471            </field>
18472          </fields>
18473        </register>
18474        <register>
18475          <name>MONITOR_CTL_0</name>
18476          <description>Power/Ground Monitor cell control 0</description>
18477          <addressOffset>0x2200</addressOffset>
18478          <size>32</size>
18479          <access>read-write</access>
18480          <resetValue>0x0</resetValue>
18481          <resetMask>0xFFFFFFFF</resetMask>
18482          <fields>
18483            <field>
18484              <name>MONITOR_EN</name>
18485              <description>control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:
18486'0': switch open.
18487'1': switch closed.</description>
18488              <bitRange>[31:0]</bitRange>
18489              <access>read-write</access>
18490            </field>
18491          </fields>
18492        </register>
18493        <register>
18494          <name>MONITOR_CTL_1</name>
18495          <description>Power/Ground Monitor cell control 1</description>
18496          <addressOffset>0x2204</addressOffset>
18497          <size>32</size>
18498          <access>read-write</access>
18499          <resetValue>0x0</resetValue>
18500          <resetMask>0xFFFFFFFF</resetMask>
18501          <fields>
18502            <field>
18503              <name>MONITOR_EN</name>
18504              <description>control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:
18505'0': switch open.
18506'1': switch closed.</description>
18507              <bitRange>[31:0]</bitRange>
18508              <access>read-write</access>
18509            </field>
18510          </fields>
18511        </register>
18512        <register>
18513          <name>MONITOR_CTL_2</name>
18514          <description>Power/Ground Monitor cell control 2</description>
18515          <addressOffset>0x2208</addressOffset>
18516          <size>32</size>
18517          <access>read-write</access>
18518          <resetValue>0x0</resetValue>
18519          <resetMask>0xFFFFFFFF</resetMask>
18520          <fields>
18521            <field>
18522              <name>MONITOR_EN</name>
18523              <description>control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:
18524'0': switch open.
18525'1': switch closed.</description>
18526              <bitRange>[31:0]</bitRange>
18527              <access>read-write</access>
18528            </field>
18529          </fields>
18530        </register>
18531        <register>
18532          <name>MONITOR_CTL_3</name>
18533          <description>Power/Ground Monitor cell control 3</description>
18534          <addressOffset>0x220C</addressOffset>
18535          <size>32</size>
18536          <access>read-write</access>
18537          <resetValue>0x0</resetValue>
18538          <resetMask>0xFFFFFFFF</resetMask>
18539          <fields>
18540            <field>
18541              <name>MONITOR_EN</name>
18542              <description>control for switch, which connects the power/ground supply to AMUXBUS_A/B respectively when switch is closed:
18543'0': switch open.
18544'1': switch closed.</description>
18545              <bitRange>[31:0]</bitRange>
18546              <access>read-write</access>
18547            </field>
18548          </fields>
18549        </register>
18550        <register>
18551          <name>ALT_JTAG_EN</name>
18552          <description>Alternate JTAG IF selection register</description>
18553          <addressOffset>0x2240</addressOffset>
18554          <size>32</size>
18555          <access>read-write</access>
18556          <resetValue>0x0</resetValue>
18557          <resetMask>0x80000000</resetMask>
18558          <fields>
18559            <field>
18560              <name>ENABLE</name>
18561              <description>Provides the selection for alternate JTAG IF connectivity.
185620: Primary JTAG interface is selected
185631: Secondary (alternate) JTAG interface is selected.
18564
18565This connectivity works ONLY in ACTIVE mode.</description>
18566              <bitRange>[31:31]</bitRange>
18567              <access>read-write</access>
18568            </field>
18569          </fields>
18570        </register>
18571      </registers>
18572    </peripheral>
18573    <peripheral>
18574      <name>GPIO</name>
18575      <description>GPIO port control/configuration</description>
18576      <baseAddress>0x40310000</baseAddress>
18577      <addressBlock>
18578        <offset>0</offset>
18579        <size>65536</size>
18580        <usage>registers</usage>
18581      </addressBlock>
18582      <registers>
18583        <cluster>
18584          <dim>15</dim>
18585          <dimIncrement>128</dimIncrement>
18586          <name>PRT[%s]</name>
18587          <description>GPIO port registers</description>
18588          <addressOffset>0x00000000</addressOffset>
18589          <register>
18590            <name>OUT</name>
18591            <description>Port output data register</description>
18592            <addressOffset>0x0</addressOffset>
18593            <size>32</size>
18594            <access>read-write</access>
18595            <resetValue>0x0</resetValue>
18596            <resetMask>0xFF</resetMask>
18597            <fields>
18598              <field>
18599                <name>OUT0</name>
18600                <description>IO output data for pin 0
18601'0': Output state set to '0'
18602'1': Output state set to '1'</description>
18603                <bitRange>[0:0]</bitRange>
18604                <access>read-write</access>
18605              </field>
18606              <field>
18607                <name>OUT1</name>
18608                <description>IO output data for pin 1</description>
18609                <bitRange>[1:1]</bitRange>
18610                <access>read-write</access>
18611              </field>
18612              <field>
18613                <name>OUT2</name>
18614                <description>IO output data for pin 2</description>
18615                <bitRange>[2:2]</bitRange>
18616                <access>read-write</access>
18617              </field>
18618              <field>
18619                <name>OUT3</name>
18620                <description>IO output data for pin 3</description>
18621                <bitRange>[3:3]</bitRange>
18622                <access>read-write</access>
18623              </field>
18624              <field>
18625                <name>OUT4</name>
18626                <description>IO output data for pin 4</description>
18627                <bitRange>[4:4]</bitRange>
18628                <access>read-write</access>
18629              </field>
18630              <field>
18631                <name>OUT5</name>
18632                <description>IO output data for pin 5</description>
18633                <bitRange>[5:5]</bitRange>
18634                <access>read-write</access>
18635              </field>
18636              <field>
18637                <name>OUT6</name>
18638                <description>IO output data for pin 6</description>
18639                <bitRange>[6:6]</bitRange>
18640                <access>read-write</access>
18641              </field>
18642              <field>
18643                <name>OUT7</name>
18644                <description>IO output data for pin 7</description>
18645                <bitRange>[7:7]</bitRange>
18646                <access>read-write</access>
18647              </field>
18648            </fields>
18649          </register>
18650          <register>
18651            <name>OUT_CLR</name>
18652            <description>Port output data clear register</description>
18653            <addressOffset>0x4</addressOffset>
18654            <size>32</size>
18655            <access>read-write</access>
18656            <resetValue>0x0</resetValue>
18657            <resetMask>0xFF</resetMask>
18658            <fields>
18659              <field>
18660                <name>OUT0</name>
18661                <description>IO clear output for pin 0:
18662'0': Output state not affected.
18663'1': Output state set to '0'.</description>
18664                <bitRange>[0:0]</bitRange>
18665                <access>read-write</access>
18666              </field>
18667              <field>
18668                <name>OUT1</name>
18669                <description>IO clear output for pin 1</description>
18670                <bitRange>[1:1]</bitRange>
18671                <access>read-write</access>
18672              </field>
18673              <field>
18674                <name>OUT2</name>
18675                <description>IO clear output for pin 2</description>
18676                <bitRange>[2:2]</bitRange>
18677                <access>read-write</access>
18678              </field>
18679              <field>
18680                <name>OUT3</name>
18681                <description>IO clear output for pin 3</description>
18682                <bitRange>[3:3]</bitRange>
18683                <access>read-write</access>
18684              </field>
18685              <field>
18686                <name>OUT4</name>
18687                <description>IO clear output for pin 4</description>
18688                <bitRange>[4:4]</bitRange>
18689                <access>read-write</access>
18690              </field>
18691              <field>
18692                <name>OUT5</name>
18693                <description>IO clear output for pin 5</description>
18694                <bitRange>[5:5]</bitRange>
18695                <access>read-write</access>
18696              </field>
18697              <field>
18698                <name>OUT6</name>
18699                <description>IO clear output for pin 6</description>
18700                <bitRange>[6:6]</bitRange>
18701                <access>read-write</access>
18702              </field>
18703              <field>
18704                <name>OUT7</name>
18705                <description>IO clear output for pin 7</description>
18706                <bitRange>[7:7]</bitRange>
18707                <access>read-write</access>
18708              </field>
18709            </fields>
18710          </register>
18711          <register>
18712            <name>OUT_SET</name>
18713            <description>Port output data set register</description>
18714            <addressOffset>0x8</addressOffset>
18715            <size>32</size>
18716            <access>read-write</access>
18717            <resetValue>0x0</resetValue>
18718            <resetMask>0xFF</resetMask>
18719            <fields>
18720              <field>
18721                <name>OUT0</name>
18722                <description>IO set output for pin 0:
18723'0': Output state not affected.
18724'1': Output state set to '1'.</description>
18725                <bitRange>[0:0]</bitRange>
18726                <access>read-write</access>
18727              </field>
18728              <field>
18729                <name>OUT1</name>
18730                <description>IO set output for pin 1</description>
18731                <bitRange>[1:1]</bitRange>
18732                <access>read-write</access>
18733              </field>
18734              <field>
18735                <name>OUT2</name>
18736                <description>IO set output for pin 2</description>
18737                <bitRange>[2:2]</bitRange>
18738                <access>read-write</access>
18739              </field>
18740              <field>
18741                <name>OUT3</name>
18742                <description>IO set output for pin 3</description>
18743                <bitRange>[3:3]</bitRange>
18744                <access>read-write</access>
18745              </field>
18746              <field>
18747                <name>OUT4</name>
18748                <description>IO set output for pin 4</description>
18749                <bitRange>[4:4]</bitRange>
18750                <access>read-write</access>
18751              </field>
18752              <field>
18753                <name>OUT5</name>
18754                <description>IO set output for pin 5</description>
18755                <bitRange>[5:5]</bitRange>
18756                <access>read-write</access>
18757              </field>
18758              <field>
18759                <name>OUT6</name>
18760                <description>IO set output for pin 6</description>
18761                <bitRange>[6:6]</bitRange>
18762                <access>read-write</access>
18763              </field>
18764              <field>
18765                <name>OUT7</name>
18766                <description>IO set output for pin 7</description>
18767                <bitRange>[7:7]</bitRange>
18768                <access>read-write</access>
18769              </field>
18770            </fields>
18771          </register>
18772          <register>
18773            <name>OUT_INV</name>
18774            <description>Port output data invert register</description>
18775            <addressOffset>0xC</addressOffset>
18776            <size>32</size>
18777            <access>read-write</access>
18778            <resetValue>0x0</resetValue>
18779            <resetMask>0xFF</resetMask>
18780            <fields>
18781              <field>
18782                <name>OUT0</name>
18783                <description>IO invert output for pin 0:
18784'0': Output state not affected.
18785'1': Output state inverted ('0' =&gt; '1', '1' =&gt; '0').</description>
18786                <bitRange>[0:0]</bitRange>
18787                <access>read-write</access>
18788              </field>
18789              <field>
18790                <name>OUT1</name>
18791                <description>IO invert output for pin 1</description>
18792                <bitRange>[1:1]</bitRange>
18793                <access>read-write</access>
18794              </field>
18795              <field>
18796                <name>OUT2</name>
18797                <description>IO invert output for pin 2</description>
18798                <bitRange>[2:2]</bitRange>
18799                <access>read-write</access>
18800              </field>
18801              <field>
18802                <name>OUT3</name>
18803                <description>IO invert output for pin 3</description>
18804                <bitRange>[3:3]</bitRange>
18805                <access>read-write</access>
18806              </field>
18807              <field>
18808                <name>OUT4</name>
18809                <description>IO invert output for pin 4</description>
18810                <bitRange>[4:4]</bitRange>
18811                <access>read-write</access>
18812              </field>
18813              <field>
18814                <name>OUT5</name>
18815                <description>IO invert output for pin 5</description>
18816                <bitRange>[5:5]</bitRange>
18817                <access>read-write</access>
18818              </field>
18819              <field>
18820                <name>OUT6</name>
18821                <description>IO invert output for pin 6</description>
18822                <bitRange>[6:6]</bitRange>
18823                <access>read-write</access>
18824              </field>
18825              <field>
18826                <name>OUT7</name>
18827                <description>IO invert output for pin 7</description>
18828                <bitRange>[7:7]</bitRange>
18829                <access>read-write</access>
18830              </field>
18831            </fields>
18832          </register>
18833          <register>
18834            <name>IN</name>
18835            <description>Port input state register</description>
18836            <addressOffset>0x10</addressOffset>
18837            <size>32</size>
18838            <access>read-only</access>
18839            <resetValue>0x0</resetValue>
18840            <resetMask>0x1FF</resetMask>
18841            <fields>
18842              <field>
18843                <name>IN0</name>
18844                <description>IO pin state for pin 0
18845'0': Low logic level present on pin.
18846'1': High logic level present on pin.
18847On reset assertion , IN register will get reset. The Pad value takes 2 clock cycles to be reflected into IN Register.  It's value then depends on the external pin value.</description>
18848                <bitRange>[0:0]</bitRange>
18849                <access>read-only</access>
18850              </field>
18851              <field>
18852                <name>IN1</name>
18853                <description>IO pin state for pin 1</description>
18854                <bitRange>[1:1]</bitRange>
18855                <access>read-only</access>
18856              </field>
18857              <field>
18858                <name>IN2</name>
18859                <description>IO pin state for pin 2</description>
18860                <bitRange>[2:2]</bitRange>
18861                <access>read-only</access>
18862              </field>
18863              <field>
18864                <name>IN3</name>
18865                <description>IO pin state for pin 3</description>
18866                <bitRange>[3:3]</bitRange>
18867                <access>read-only</access>
18868              </field>
18869              <field>
18870                <name>IN4</name>
18871                <description>IO pin state for pin 4</description>
18872                <bitRange>[4:4]</bitRange>
18873                <access>read-only</access>
18874              </field>
18875              <field>
18876                <name>IN5</name>
18877                <description>IO pin state for pin 5</description>
18878                <bitRange>[5:5]</bitRange>
18879                <access>read-only</access>
18880              </field>
18881              <field>
18882                <name>IN6</name>
18883                <description>IO pin state for pin 6</description>
18884                <bitRange>[6:6]</bitRange>
18885                <access>read-only</access>
18886              </field>
18887              <field>
18888                <name>IN7</name>
18889                <description>IO pin state for pin 7</description>
18890                <bitRange>[7:7]</bitRange>
18891                <access>read-only</access>
18892              </field>
18893              <field>
18894                <name>FLT_IN</name>
18895                <description>Reads of this register return the logical state of the filtered pin as selected in the INTR_CFG.FLT_SEL register.</description>
18896                <bitRange>[8:8]</bitRange>
18897                <access>read-only</access>
18898              </field>
18899            </fields>
18900          </register>
18901          <register>
18902            <name>INTR</name>
18903            <description>Port interrupt status register</description>
18904            <addressOffset>0x14</addressOffset>
18905            <size>32</size>
18906            <access>read-write</access>
18907            <resetValue>0x0</resetValue>
18908            <resetMask>0x1FF01FF</resetMask>
18909            <fields>
18910              <field>
18911                <name>EDGE0</name>
18912                <description>Edge detect for IO pin 0
18913'0': No edge was detected on pin.
18914'1': An edge was detected on pin.</description>
18915                <bitRange>[0:0]</bitRange>
18916                <access>read-write</access>
18917              </field>
18918              <field>
18919                <name>EDGE1</name>
18920                <description>Edge detect for IO pin 1</description>
18921                <bitRange>[1:1]</bitRange>
18922                <access>read-write</access>
18923              </field>
18924              <field>
18925                <name>EDGE2</name>
18926                <description>Edge detect for IO pin 2</description>
18927                <bitRange>[2:2]</bitRange>
18928                <access>read-write</access>
18929              </field>
18930              <field>
18931                <name>EDGE3</name>
18932                <description>Edge detect for IO pin 3</description>
18933                <bitRange>[3:3]</bitRange>
18934                <access>read-write</access>
18935              </field>
18936              <field>
18937                <name>EDGE4</name>
18938                <description>Edge detect for IO pin 4</description>
18939                <bitRange>[4:4]</bitRange>
18940                <access>read-write</access>
18941              </field>
18942              <field>
18943                <name>EDGE5</name>
18944                <description>Edge detect for IO pin 5</description>
18945                <bitRange>[5:5]</bitRange>
18946                <access>read-write</access>
18947              </field>
18948              <field>
18949                <name>EDGE6</name>
18950                <description>Edge detect for IO pin 6</description>
18951                <bitRange>[6:6]</bitRange>
18952                <access>read-write</access>
18953              </field>
18954              <field>
18955                <name>EDGE7</name>
18956                <description>Edge detect for IO pin 7</description>
18957                <bitRange>[7:7]</bitRange>
18958                <access>read-write</access>
18959              </field>
18960              <field>
18961                <name>FLT_EDGE</name>
18962                <description>Edge detected on filtered pin selected by INTR_CFG.FLT_SEL</description>
18963                <bitRange>[8:8]</bitRange>
18964                <access>read-write</access>
18965              </field>
18966              <field>
18967                <name>IN_IN0</name>
18968                <description>IO pin state for pin 0</description>
18969                <bitRange>[16:16]</bitRange>
18970                <access>read-only</access>
18971              </field>
18972              <field>
18973                <name>IN_IN1</name>
18974                <description>IO pin state for pin 1</description>
18975                <bitRange>[17:17]</bitRange>
18976                <access>read-only</access>
18977              </field>
18978              <field>
18979                <name>IN_IN2</name>
18980                <description>IO pin state for pin 2</description>
18981                <bitRange>[18:18]</bitRange>
18982                <access>read-only</access>
18983              </field>
18984              <field>
18985                <name>IN_IN3</name>
18986                <description>IO pin state for pin 3</description>
18987                <bitRange>[19:19]</bitRange>
18988                <access>read-only</access>
18989              </field>
18990              <field>
18991                <name>IN_IN4</name>
18992                <description>IO pin state for pin 4</description>
18993                <bitRange>[20:20]</bitRange>
18994                <access>read-only</access>
18995              </field>
18996              <field>
18997                <name>IN_IN5</name>
18998                <description>IO pin state for pin 5</description>
18999                <bitRange>[21:21]</bitRange>
19000                <access>read-only</access>
19001              </field>
19002              <field>
19003                <name>IN_IN6</name>
19004                <description>IO pin state for pin 6</description>
19005                <bitRange>[22:22]</bitRange>
19006                <access>read-only</access>
19007              </field>
19008              <field>
19009                <name>IN_IN7</name>
19010                <description>IO pin state for pin 7</description>
19011                <bitRange>[23:23]</bitRange>
19012                <access>read-only</access>
19013              </field>
19014              <field>
19015                <name>FLT_IN_IN</name>
19016                <description>Filtered pin state for pin selected by INTR_CFG.FLT_SEL</description>
19017                <bitRange>[24:24]</bitRange>
19018                <access>read-only</access>
19019              </field>
19020            </fields>
19021          </register>
19022          <register>
19023            <name>INTR_MASK</name>
19024            <description>Port interrupt mask register</description>
19025            <addressOffset>0x18</addressOffset>
19026            <size>32</size>
19027            <access>read-write</access>
19028            <resetValue>0x0</resetValue>
19029            <resetMask>0x1FF</resetMask>
19030            <fields>
19031              <field>
19032                <name>EDGE0</name>
19033                <description>Masks edge interrupt on IO pin 0
19034'0': Pin interrupt forwarding disabled
19035'1': Pin interrupt forwarding enabled</description>
19036                <bitRange>[0:0]</bitRange>
19037                <access>read-write</access>
19038              </field>
19039              <field>
19040                <name>EDGE1</name>
19041                <description>Masks edge interrupt on IO pin 1</description>
19042                <bitRange>[1:1]</bitRange>
19043                <access>read-write</access>
19044              </field>
19045              <field>
19046                <name>EDGE2</name>
19047                <description>Masks edge interrupt on IO pin 2</description>
19048                <bitRange>[2:2]</bitRange>
19049                <access>read-write</access>
19050              </field>
19051              <field>
19052                <name>EDGE3</name>
19053                <description>Masks edge interrupt on IO pin 3</description>
19054                <bitRange>[3:3]</bitRange>
19055                <access>read-write</access>
19056              </field>
19057              <field>
19058                <name>EDGE4</name>
19059                <description>Masks edge interrupt on IO pin 4</description>
19060                <bitRange>[4:4]</bitRange>
19061                <access>read-write</access>
19062              </field>
19063              <field>
19064                <name>EDGE5</name>
19065                <description>Masks edge interrupt on IO pin 5</description>
19066                <bitRange>[5:5]</bitRange>
19067                <access>read-write</access>
19068              </field>
19069              <field>
19070                <name>EDGE6</name>
19071                <description>Masks edge interrupt on IO pin 6</description>
19072                <bitRange>[6:6]</bitRange>
19073                <access>read-write</access>
19074              </field>
19075              <field>
19076                <name>EDGE7</name>
19077                <description>Masks edge interrupt on IO pin 7</description>
19078                <bitRange>[7:7]</bitRange>
19079                <access>read-write</access>
19080              </field>
19081              <field>
19082                <name>FLT_EDGE</name>
19083                <description>Masks edge interrupt on filtered pin selected by INTR_CFG.FLT_SEL</description>
19084                <bitRange>[8:8]</bitRange>
19085                <access>read-write</access>
19086              </field>
19087            </fields>
19088          </register>
19089          <register>
19090            <name>INTR_MASKED</name>
19091            <description>Port interrupt masked status register</description>
19092            <addressOffset>0x1C</addressOffset>
19093            <size>32</size>
19094            <access>read-only</access>
19095            <resetValue>0x0</resetValue>
19096            <resetMask>0x1FF</resetMask>
19097            <fields>
19098              <field>
19099                <name>EDGE0</name>
19100                <description>Edge detected AND masked on IO pin 0
19101'0': Interrupt was not forwarded to CPU
19102'1': Interrupt occurred and was forwarded to CPU</description>
19103                <bitRange>[0:0]</bitRange>
19104                <access>read-only</access>
19105              </field>
19106              <field>
19107                <name>EDGE1</name>
19108                <description>Edge detected and masked on IO pin 1</description>
19109                <bitRange>[1:1]</bitRange>
19110                <access>read-only</access>
19111              </field>
19112              <field>
19113                <name>EDGE2</name>
19114                <description>Edge detected and masked on IO pin 2</description>
19115                <bitRange>[2:2]</bitRange>
19116                <access>read-only</access>
19117              </field>
19118              <field>
19119                <name>EDGE3</name>
19120                <description>Edge detected and masked on IO pin 3</description>
19121                <bitRange>[3:3]</bitRange>
19122                <access>read-only</access>
19123              </field>
19124              <field>
19125                <name>EDGE4</name>
19126                <description>Edge detected and masked on IO pin 4</description>
19127                <bitRange>[4:4]</bitRange>
19128                <access>read-only</access>
19129              </field>
19130              <field>
19131                <name>EDGE5</name>
19132                <description>Edge detected and masked on IO pin 5</description>
19133                <bitRange>[5:5]</bitRange>
19134                <access>read-only</access>
19135              </field>
19136              <field>
19137                <name>EDGE6</name>
19138                <description>Edge detected and masked on IO pin 6</description>
19139                <bitRange>[6:6]</bitRange>
19140                <access>read-only</access>
19141              </field>
19142              <field>
19143                <name>EDGE7</name>
19144                <description>Edge detected and masked on IO pin 7</description>
19145                <bitRange>[7:7]</bitRange>
19146                <access>read-only</access>
19147              </field>
19148              <field>
19149                <name>FLT_EDGE</name>
19150                <description>Edge detected and masked on filtered pin selected by INTR_CFG.FLT_SEL</description>
19151                <bitRange>[8:8]</bitRange>
19152                <access>read-only</access>
19153              </field>
19154            </fields>
19155          </register>
19156          <register>
19157            <name>INTR_SET</name>
19158            <description>Port interrupt set register</description>
19159            <addressOffset>0x20</addressOffset>
19160            <size>32</size>
19161            <access>read-write</access>
19162            <resetValue>0x0</resetValue>
19163            <resetMask>0x1FF</resetMask>
19164            <fields>
19165              <field>
19166                <name>EDGE0</name>
19167                <description>Sets edge detect interrupt for IO pin 0
19168'0': Interrupt state not affected
19169'1': Interrupt set</description>
19170                <bitRange>[0:0]</bitRange>
19171                <access>read-write</access>
19172              </field>
19173              <field>
19174                <name>EDGE1</name>
19175                <description>Sets edge detect interrupt for IO pin 1</description>
19176                <bitRange>[1:1]</bitRange>
19177                <access>read-write</access>
19178              </field>
19179              <field>
19180                <name>EDGE2</name>
19181                <description>Sets edge detect interrupt for IO pin 2</description>
19182                <bitRange>[2:2]</bitRange>
19183                <access>read-write</access>
19184              </field>
19185              <field>
19186                <name>EDGE3</name>
19187                <description>Sets edge detect interrupt for IO pin 3</description>
19188                <bitRange>[3:3]</bitRange>
19189                <access>read-write</access>
19190              </field>
19191              <field>
19192                <name>EDGE4</name>
19193                <description>Sets edge detect interrupt for IO pin 4</description>
19194                <bitRange>[4:4]</bitRange>
19195                <access>read-write</access>
19196              </field>
19197              <field>
19198                <name>EDGE5</name>
19199                <description>Sets edge detect interrupt for IO pin 5</description>
19200                <bitRange>[5:5]</bitRange>
19201                <access>read-write</access>
19202              </field>
19203              <field>
19204                <name>EDGE6</name>
19205                <description>Sets edge detect interrupt for IO pin 6</description>
19206                <bitRange>[6:6]</bitRange>
19207                <access>read-write</access>
19208              </field>
19209              <field>
19210                <name>EDGE7</name>
19211                <description>Sets edge detect interrupt for IO pin 7</description>
19212                <bitRange>[7:7]</bitRange>
19213                <access>read-write</access>
19214              </field>
19215              <field>
19216                <name>FLT_EDGE</name>
19217                <description>Sets edge detect interrupt for filtered pin selected by INTR_CFG.FLT_SEL</description>
19218                <bitRange>[8:8]</bitRange>
19219                <access>read-write</access>
19220              </field>
19221            </fields>
19222          </register>
19223          <register>
19224            <name>INTR_CFG</name>
19225            <description>Port interrupt configuration register</description>
19226            <addressOffset>0x40</addressOffset>
19227            <size>32</size>
19228            <access>read-write</access>
19229            <resetValue>0x0</resetValue>
19230            <resetMask>0x1FFFFF</resetMask>
19231            <fields>
19232              <field>
19233                <name>EDGE0_SEL</name>
19234                <description>Sets which edge will trigger an IRQ for IO pin 0</description>
19235                <bitRange>[1:0]</bitRange>
19236                <access>read-write</access>
19237                <enumeratedValues>
19238                  <enumeratedValue>
19239                    <name>DISABLE</name>
19240                    <description>Disabled</description>
19241                    <value>0</value>
19242                  </enumeratedValue>
19243                  <enumeratedValue>
19244                    <name>RISING</name>
19245                    <description>Rising edge</description>
19246                    <value>1</value>
19247                  </enumeratedValue>
19248                  <enumeratedValue>
19249                    <name>FALLING</name>
19250                    <description>Falling edge</description>
19251                    <value>2</value>
19252                  </enumeratedValue>
19253                  <enumeratedValue>
19254                    <name>BOTH</name>
19255                    <description>Both rising and falling edges</description>
19256                    <value>3</value>
19257                  </enumeratedValue>
19258                </enumeratedValues>
19259              </field>
19260              <field>
19261                <name>EDGE1_SEL</name>
19262                <description>Sets which edge will trigger an IRQ for IO pin 1</description>
19263                <bitRange>[3:2]</bitRange>
19264                <access>read-write</access>
19265              </field>
19266              <field>
19267                <name>EDGE2_SEL</name>
19268                <description>Sets which edge will trigger an IRQ for IO pin 2</description>
19269                <bitRange>[5:4]</bitRange>
19270                <access>read-write</access>
19271              </field>
19272              <field>
19273                <name>EDGE3_SEL</name>
19274                <description>Sets which edge will trigger an IRQ for IO pin 3</description>
19275                <bitRange>[7:6]</bitRange>
19276                <access>read-write</access>
19277              </field>
19278              <field>
19279                <name>EDGE4_SEL</name>
19280                <description>Sets which edge will trigger an IRQ for IO pin 4</description>
19281                <bitRange>[9:8]</bitRange>
19282                <access>read-write</access>
19283              </field>
19284              <field>
19285                <name>EDGE5_SEL</name>
19286                <description>Sets which edge will trigger an IRQ for IO pin 5</description>
19287                <bitRange>[11:10]</bitRange>
19288                <access>read-write</access>
19289              </field>
19290              <field>
19291                <name>EDGE6_SEL</name>
19292                <description>Sets which edge will trigger an IRQ for IO pin 6</description>
19293                <bitRange>[13:12]</bitRange>
19294                <access>read-write</access>
19295              </field>
19296              <field>
19297                <name>EDGE7_SEL</name>
19298                <description>Sets which edge will trigger an IRQ for IO pin 7</description>
19299                <bitRange>[15:14]</bitRange>
19300                <access>read-write</access>
19301              </field>
19302              <field>
19303                <name>FLT_EDGE_SEL</name>
19304                <description>Sets which edge will trigger an IRQ for the glitch filtered pin (selected by INTR_CFG.FLT_SEL</description>
19305                <bitRange>[17:16]</bitRange>
19306                <access>read-write</access>
19307                <enumeratedValues>
19308                  <enumeratedValue>
19309                    <name>DISABLE</name>
19310                    <description>Disabled</description>
19311                    <value>0</value>
19312                  </enumeratedValue>
19313                  <enumeratedValue>
19314                    <name>RISING</name>
19315                    <description>Rising edge</description>
19316                    <value>1</value>
19317                  </enumeratedValue>
19318                  <enumeratedValue>
19319                    <name>FALLING</name>
19320                    <description>Falling edge</description>
19321                    <value>2</value>
19322                  </enumeratedValue>
19323                  <enumeratedValue>
19324                    <name>BOTH</name>
19325                    <description>Both rising and falling edges</description>
19326                    <value>3</value>
19327                  </enumeratedValue>
19328                </enumeratedValues>
19329              </field>
19330              <field>
19331                <name>FLT_SEL</name>
19332                <description>Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt.</description>
19333                <bitRange>[20:18]</bitRange>
19334                <access>read-write</access>
19335              </field>
19336            </fields>
19337          </register>
19338          <register>
19339            <name>CFG</name>
19340            <description>Port configuration register</description>
19341            <addressOffset>0x44</addressOffset>
19342            <size>32</size>
19343            <access>read-write</access>
19344            <resetValue>0x0</resetValue>
19345            <resetMask>0xFFFFFFFF</resetMask>
19346            <fields>
19347              <field>
19348                <name>DRIVE_MODE0</name>
19349                <description>The GPIO drive mode for IO pin 0. Resistive pull-up and pull-down is selected in the drive mode.
19350Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the peripheral and HSIOM (HSIOM_PRT_SELx) is properly configured  before turning the IO on here to avoid producing glitches on the bus.
19351Note: that peripherals other than GPIO &amp; UDB/DSI directly control both the output and output-enable of the output buffer (peripherals can drive strong 0 or strong 1 in any mode except OFF='0').
19352Note: D_OUT, D_OUT_EN are pins of GPIO cell.</description>
19353                <bitRange>[2:0]</bitRange>
19354                <access>read-write</access>
19355                <enumeratedValues>
19356                  <enumeratedValue>
19357                    <name>HIGHZ</name>
19358                    <description>Output buffer is off creating a high impedance input
19359D_OUT = '0': High Impedance
19360D_OUT = '1': High Impedance</description>
19361                    <value>0</value>
19362                  </enumeratedValue>
19363                  <enumeratedValue>
19364                    <name>RSVD</name>
19365                    <description>N/A</description>
19366                    <value>1</value>
19367                  </enumeratedValue>
19368                  <enumeratedValue>
19369                    <name>PULLUP</name>
19370                    <description>Resistive pull up
19371
19372For GPIO &amp; UDB/DSI peripherals:
19373When D_OUT_EN = 1:
19374   D_OUT = '0': Strong pull down
19375   D_OUT = '1': Weak/resistive pull up
19376When D_OUT_EN = 0:
19377   D_OUT = '0': High impedance
19378   D_OUT = '1': High impedance
19379
19380For peripherals other than GPIO &amp; UDB/DSI:
19381When D_OUT_EN = 1:
19382   D_OUT = '0': Strong pull down
19383   D_OUT = '1': Strong pull up
19384When D_OUT_EN = 0:
19385   D_OUT = '0': Weak/resistive pull up
19386   D_OUT = '1': Weak/resistive pull up</description>
19387                    <value>2</value>
19388                  </enumeratedValue>
19389                  <enumeratedValue>
19390                    <name>PULLDOWN</name>
19391                    <description>Resistive pull down
19392
19393For GPIO &amp; UDB/DSI peripherals:
19394When D_OUT_EN = 1:
19395   D_OUT = '0': Weak/resistive pull down
19396   D_OUT = '1': Strong pull up
19397When D_OUT_EN = 0:
19398   D_OUT = '0': High impedance
19399   D_OUT = '1': High impedance
19400
19401For peripherals other than GPIO &amp; UDB/DSI:
19402When D_OUT_EN = 1:
19403   D_OUT = '0': Strong pull down
19404   D_OUT = '1': Strong pull up
19405When D_OUT_EN = 0:
19406   D_OUT = '0': Weak/resistive pull down
19407   D_OUT = '1': Weak/resistive pull down</description>
19408                    <value>3</value>
19409                  </enumeratedValue>
19410                  <enumeratedValue>
19411                    <name>OD_DRIVESLOW</name>
19412                    <description>Open drain, drives low
19413
19414For GPIO &amp; UDB/DSI peripherals:
19415When D_OUT_EN = 1:
19416   D_OUT = '0': Strong pull down
19417   D_OUT = '1': High Impedance
19418When D_OUT_EN = 0:
19419   D_OUT = '0': High impedance
19420   D_OUT = '1': High impedance
19421
19422For peripherals other than GPIO &amp; UDB/DSI:
19423When D_OUT_EN = 1:
19424   D_OUT = '0': Strong pull down
19425   D_OUT = '1': Strong pull up
19426When D_OUT_EN = 0:
19427   D_OUT = '0': High Impedance
19428   D_OUT = '1': High Impedance</description>
19429                    <value>4</value>
19430                  </enumeratedValue>
19431                  <enumeratedValue>
19432                    <name>OD_DRIVESHIGH</name>
19433                    <description>Open drain, drives high
19434
19435For GPIO &amp; UDB/DSI peripherals:
19436When D_OUT_EN = 1:
19437   D_OUT = '0': High Impedance
19438   D_OUT = '1': Strong pull up
19439When D_OUT_EN = 0:
19440   D_OUT = '0': High impedance
19441   D_OUT = '1': High impedance
19442
19443For peripherals other than GPIO &amp; UDB/DSI:
19444When D_OUT_EN = 1:
19445   D_OUT = '0': Strong pull down
19446   D_OUT = '1': Strong pull up
19447When D_OUT_EN = 0:
19448   D_OUT = '0': High Impedance
19449   D_OUT = '1': High Impedance</description>
19450                    <value>5</value>
19451                  </enumeratedValue>
19452                  <enumeratedValue>
19453                    <name>STRONG</name>
19454                    <description>Strong D_OUTput buffer
19455
19456For GPIO &amp; UDB/DSI peripherals:
19457When D_OUT_EN = 1:
19458   D_OUT = '0': Strong pull down
19459   D_OUT = '1': Strong pull up
19460When D_OUT_EN = 0:
19461   D_OUT = '0': High impedance
19462   D_OUT = '1': High impedance
19463
19464For peripherals other than GPIO &amp; UDB/DSI:
19465When D_OUT_EN = 1:
19466   D_OUT = '0': Strong pull down
19467   D_OUT = '1': Strong pull up
19468When D_OUT_EN = 0:
19469   D_OUT = '0': High Impedance
19470   D_OUT = '1': High Impedance</description>
19471                    <value>6</value>
19472                  </enumeratedValue>
19473                  <enumeratedValue>
19474                    <name>PULLUP_DOWN</name>
19475                    <description>Pull up or pull down
19476
19477For GPIO &amp; UDB/DSI peripherals:
19478When D_OUT_EN = '0':
19479    GPIO_DSI_OUT = '0': Weak/resistive pull down
19480    GPIO_DSI_OUT = '1': Weak/resistive pull up
19481where 'GPIO_DSI_OUT' is a function of PORT_SEL, OUT &amp; DSI_DATA_OUT.
19482
19483For peripherals other than GPIO &amp; UDB/DSI:
19484When D_OUT_EN = 1:
19485   D_OUT = '0': Strong pull down
19486   D_OUT = '1': Strong pull up
19487When D_OUT_EN = 0:
19488    D_OUT = '0': Weak/resistive pull down
19489    D_OUT = '1': Weak/resistive pull up</description>
19490                    <value>7</value>
19491                  </enumeratedValue>
19492                </enumeratedValues>
19493              </field>
19494              <field>
19495                <name>IN_EN0</name>
19496                <description>Enables the input buffer for IO pin 0.  This bit should be cleared when analog signals are present on the pin to avoid crowbar currents.  The output buffer can be used to drive analog signals high or low without issue.
19497'0': Input buffer disabled
19498'1': Input buffer enabled</description>
19499                <bitRange>[3:3]</bitRange>
19500                <access>read-write</access>
19501              </field>
19502              <field>
19503                <name>DRIVE_MODE1</name>
19504                <description>The GPIO drive mode for IO pin 1</description>
19505                <bitRange>[6:4]</bitRange>
19506                <access>read-write</access>
19507              </field>
19508              <field>
19509                <name>IN_EN1</name>
19510                <description>Enables the input buffer for IO pin 1</description>
19511                <bitRange>[7:7]</bitRange>
19512                <access>read-write</access>
19513              </field>
19514              <field>
19515                <name>DRIVE_MODE2</name>
19516                <description>The GPIO drive mode for IO pin 2</description>
19517                <bitRange>[10:8]</bitRange>
19518                <access>read-write</access>
19519              </field>
19520              <field>
19521                <name>IN_EN2</name>
19522                <description>Enables the input buffer for IO pin 2</description>
19523                <bitRange>[11:11]</bitRange>
19524                <access>read-write</access>
19525              </field>
19526              <field>
19527                <name>DRIVE_MODE3</name>
19528                <description>The GPIO drive mode for IO pin 3</description>
19529                <bitRange>[14:12]</bitRange>
19530                <access>read-write</access>
19531              </field>
19532              <field>
19533                <name>IN_EN3</name>
19534                <description>Enables the input buffer for IO pin 3</description>
19535                <bitRange>[15:15]</bitRange>
19536                <access>read-write</access>
19537              </field>
19538              <field>
19539                <name>DRIVE_MODE4</name>
19540                <description>The GPIO drive mode for IO pin4</description>
19541                <bitRange>[18:16]</bitRange>
19542                <access>read-write</access>
19543              </field>
19544              <field>
19545                <name>IN_EN4</name>
19546                <description>Enables the input buffer for IO pin 4</description>
19547                <bitRange>[19:19]</bitRange>
19548                <access>read-write</access>
19549              </field>
19550              <field>
19551                <name>DRIVE_MODE5</name>
19552                <description>The GPIO drive mode for IO pin 5</description>
19553                <bitRange>[22:20]</bitRange>
19554                <access>read-write</access>
19555              </field>
19556              <field>
19557                <name>IN_EN5</name>
19558                <description>Enables the input buffer for IO pin 5</description>
19559                <bitRange>[23:23]</bitRange>
19560                <access>read-write</access>
19561              </field>
19562              <field>
19563                <name>DRIVE_MODE6</name>
19564                <description>The GPIO drive mode for IO pin 6</description>
19565                <bitRange>[26:24]</bitRange>
19566                <access>read-write</access>
19567              </field>
19568              <field>
19569                <name>IN_EN6</name>
19570                <description>Enables the input buffer for IO pin 6</description>
19571                <bitRange>[27:27]</bitRange>
19572                <access>read-write</access>
19573              </field>
19574              <field>
19575                <name>DRIVE_MODE7</name>
19576                <description>The GPIO drive mode for IO pin 7</description>
19577                <bitRange>[30:28]</bitRange>
19578                <access>read-write</access>
19579              </field>
19580              <field>
19581                <name>IN_EN7</name>
19582                <description>Enables the input buffer for IO pin 7</description>
19583                <bitRange>[31:31]</bitRange>
19584                <access>read-write</access>
19585              </field>
19586            </fields>
19587          </register>
19588          <register>
19589            <name>CFG_IN</name>
19590            <description>Port input buffer configuration register</description>
19591            <addressOffset>0x48</addressOffset>
19592            <size>32</size>
19593            <access>read-write</access>
19594            <resetValue>0x0</resetValue>
19595            <resetMask>0xFF</resetMask>
19596            <fields>
19597              <field>
19598                <name>VTRIP_SEL0_0</name>
19599                <description>Configures the pin 0 input buffer mode (trip points and hysteresis)</description>
19600                <bitRange>[0:0]</bitRange>
19601                <access>read-write</access>
19602                <enumeratedValues>
19603                  <enumeratedValue>
19604                    <name>CMOS</name>
19605                    <description>PSoC 6:: Input buffer compatible with CMOS and I2C interfaces
19606Traveo II: Full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1</description>
19607                    <value>0</value>
19608                  </enumeratedValue>
19609                  <enumeratedValue>
19610                    <name>TTL</name>
19611                    <description>PSoC 6:: Input buffer compatible with TTL and MediaLB interfaces
19612Traveo II: full encoding is shown in CFG_IN_AUTOLVL.VTRIP_SEL0_1</description>
19613                    <value>1</value>
19614                  </enumeratedValue>
19615                </enumeratedValues>
19616              </field>
19617              <field>
19618                <name>VTRIP_SEL1_0</name>
19619                <description>Configures the pin 1 input buffer mode (trip points and hysteresis)</description>
19620                <bitRange>[1:1]</bitRange>
19621                <access>read-write</access>
19622              </field>
19623              <field>
19624                <name>VTRIP_SEL2_0</name>
19625                <description>Configures the pin 2 input buffer mode (trip points and hysteresis)</description>
19626                <bitRange>[2:2]</bitRange>
19627                <access>read-write</access>
19628              </field>
19629              <field>
19630                <name>VTRIP_SEL3_0</name>
19631                <description>Configures the pin 3 input buffer mode (trip points and hysteresis)</description>
19632                <bitRange>[3:3]</bitRange>
19633                <access>read-write</access>
19634              </field>
19635              <field>
19636                <name>VTRIP_SEL4_0</name>
19637                <description>Configures the pin 4 input buffer mode (trip points and hysteresis)</description>
19638                <bitRange>[4:4]</bitRange>
19639                <access>read-write</access>
19640              </field>
19641              <field>
19642                <name>VTRIP_SEL5_0</name>
19643                <description>Configures the pin 5 input buffer mode (trip points and hysteresis)</description>
19644                <bitRange>[5:5]</bitRange>
19645                <access>read-write</access>
19646              </field>
19647              <field>
19648                <name>VTRIP_SEL6_0</name>
19649                <description>Configures the pin 6 input buffer mode (trip points and hysteresis)</description>
19650                <bitRange>[6:6]</bitRange>
19651                <access>read-write</access>
19652              </field>
19653              <field>
19654                <name>VTRIP_SEL7_0</name>
19655                <description>Configures the pin 7 input buffer mode (trip points and hysteresis)</description>
19656                <bitRange>[7:7]</bitRange>
19657                <access>read-write</access>
19658              </field>
19659            </fields>
19660          </register>
19661          <register>
19662            <name>CFG_OUT</name>
19663            <description>Port output buffer configuration register</description>
19664            <addressOffset>0x4C</addressOffset>
19665            <size>32</size>
19666            <access>read-write</access>
19667            <resetValue>0x0</resetValue>
19668            <resetMask>0xFFFF00FF</resetMask>
19669            <fields>
19670              <field>
19671                <name>SLOW0</name>
19672                <description>Enables slow slew rate for IO pin 0
19673'0': Fast slew rate
19674'1': Slow slew rate</description>
19675                <bitRange>[0:0]</bitRange>
19676                <access>read-write</access>
19677              </field>
19678              <field>
19679                <name>SLOW1</name>
19680                <description>Enables slow slew rate for IO pin 1</description>
19681                <bitRange>[1:1]</bitRange>
19682                <access>read-write</access>
19683              </field>
19684              <field>
19685                <name>SLOW2</name>
19686                <description>Enables slow slew rate for IO pin 2</description>
19687                <bitRange>[2:2]</bitRange>
19688                <access>read-write</access>
19689              </field>
19690              <field>
19691                <name>SLOW3</name>
19692                <description>Enables slow slew rate for IO pin 3</description>
19693                <bitRange>[3:3]</bitRange>
19694                <access>read-write</access>
19695              </field>
19696              <field>
19697                <name>SLOW4</name>
19698                <description>Enables slow slew rate for IO pin 4</description>
19699                <bitRange>[4:4]</bitRange>
19700                <access>read-write</access>
19701              </field>
19702              <field>
19703                <name>SLOW5</name>
19704                <description>Enables slow slew rate for IO pin 5</description>
19705                <bitRange>[5:5]</bitRange>
19706                <access>read-write</access>
19707              </field>
19708              <field>
19709                <name>SLOW6</name>
19710                <description>Enables slow slew rate for IO pin 6</description>
19711                <bitRange>[6:6]</bitRange>
19712                <access>read-write</access>
19713              </field>
19714              <field>
19715                <name>SLOW7</name>
19716                <description>Enables slow slew rate for IO pin 7</description>
19717                <bitRange>[7:7]</bitRange>
19718                <access>read-write</access>
19719              </field>
19720              <field>
19721                <name>DRIVE_SEL0</name>
19722                <description>Sets the GPIO drive strength for IO pin 0</description>
19723                <bitRange>[17:16]</bitRange>
19724                <access>read-write</access>
19725                <enumeratedValues>
19726                  <enumeratedValue>
19727                    <name>DRIVE_SEL_ZERO</name>
19728                    <description>Please refer to architecture TRM section I/O System</description>
19729                    <value>0</value>
19730                  </enumeratedValue>
19731                  <enumeratedValue>
19732                    <name>DRIVE_SEL_ONE</name>
19733                    <description>Please refer to architecture TRM section I/O System</description>
19734                    <value>1</value>
19735                  </enumeratedValue>
19736                  <enumeratedValue>
19737                    <name>DRIVE_SEL_TWO</name>
19738                    <description>Please refer to architecture TRM section I/O System</description>
19739                    <value>2</value>
19740                  </enumeratedValue>
19741                  <enumeratedValue>
19742                    <name>DRIVE_SEL_THREE</name>
19743                    <description>Please refer to architecture TRM section I/O System</description>
19744                    <value>3</value>
19745                  </enumeratedValue>
19746                </enumeratedValues>
19747              </field>
19748              <field>
19749                <name>DRIVE_SEL1</name>
19750                <description>Sets the GPIO drive strength for IO pin 1</description>
19751                <bitRange>[19:18]</bitRange>
19752                <access>read-write</access>
19753              </field>
19754              <field>
19755                <name>DRIVE_SEL2</name>
19756                <description>Sets the GPIO drive strength for IO pin 2</description>
19757                <bitRange>[21:20]</bitRange>
19758                <access>read-write</access>
19759              </field>
19760              <field>
19761                <name>DRIVE_SEL3</name>
19762                <description>Sets the GPIO drive strength for IO pin 3</description>
19763                <bitRange>[23:22]</bitRange>
19764                <access>read-write</access>
19765              </field>
19766              <field>
19767                <name>DRIVE_SEL4</name>
19768                <description>Sets the GPIO drive strength for IO pin 4</description>
19769                <bitRange>[25:24]</bitRange>
19770                <access>read-write</access>
19771              </field>
19772              <field>
19773                <name>DRIVE_SEL5</name>
19774                <description>Sets the GPIO drive strength for IO pin 5</description>
19775                <bitRange>[27:26]</bitRange>
19776                <access>read-write</access>
19777              </field>
19778              <field>
19779                <name>DRIVE_SEL6</name>
19780                <description>Sets the GPIO drive strength for IO pin 6</description>
19781                <bitRange>[29:28]</bitRange>
19782                <access>read-write</access>
19783              </field>
19784              <field>
19785                <name>DRIVE_SEL7</name>
19786                <description>Sets the GPIO drive strength for IO pin 7</description>
19787                <bitRange>[31:30]</bitRange>
19788                <access>read-write</access>
19789              </field>
19790            </fields>
19791          </register>
19792          <register>
19793            <name>CFG_SIO</name>
19794            <description>Port SIO configuration register</description>
19795            <addressOffset>0x50</addressOffset>
19796            <size>32</size>
19797            <access>read-write</access>
19798            <resetValue>0x0</resetValue>
19799            <resetMask>0xFFFFFFFF</resetMask>
19800            <fields>
19801              <field>
19802                <name>VREG_EN01</name>
19803                <description>Selects the output buffer mode:
19804'0': Unregulated output buffer
19805'1': Regulated output buffer
19806The regulated output mode is selected ONLY if the CFG.DRIVE_MODE bits are set to the strong pull up (Z_1 = '5') mode. If the CFG.DRIVE_MODE bits are set to any other mode the regulated output buffer will be disabled and the standard CMOS output buffer is used.</description>
19807                <bitRange>[0:0]</bitRange>
19808                <access>read-write</access>
19809              </field>
19810              <field>
19811                <name>IBUF_SEL01</name>
19812                <description>Selects the input buffer mode:
198130: Singled ended input buffer
198141: Differential input buffer</description>
19815                <bitRange>[1:1]</bitRange>
19816                <access>read-write</access>
19817              </field>
19818              <field>
19819                <name>VTRIP_SEL01</name>
19820                <description>Selects the input buffer trip-point in single ended input buffer mode (IBUF_SEL = '0'):
19821'0': Input buffer functions as a CMOS input buffer.
19822'1': Input buffer functions as a TTL input buffer.
19823In differential input buffer mode (IBUF_SEL = '1')
19824'0': Trip-point is 0.5*Vddio or 0.5*Voh (depends on VREF_SEL/VOH_SEL)
19825'1': Trip-point is 0.4*Vddio or 1.0*Vref  (depends on VREF_SEL)</description>
19826                <bitRange>[2:2]</bitRange>
19827                <access>read-write</access>
19828              </field>
19829              <field>
19830                <name>VREF_SEL01</name>
19831                <description>Selects reference voltage (Vref) trip-point of the input buffer:
19832'0': Trip-point reference from pin_ref
19833'1': Trip-point reference of SRSS internal reference Vref (1.2 V)
19834'2': Trip-point reference of AMUXBUS_A
19835'3': Trip-point reference of AMUXBUS_B</description>
19836                <bitRange>[4:3]</bitRange>
19837                <access>read-write</access>
19838              </field>
19839              <field>
19840                <name>VOH_SEL01</name>
19841                <description>Selects the regulated Voh output level and trip point of the input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL).
19842'0': Voh = 1*reference; e.g. reference at 1.2V -&gt; Voh = 1.2V
19843'1': Voh = 1.25*reference; e.g. reference at 1.2V -&gt; Voh = 1.5V
19844'2': Voh = 1.49*reference; e.g. reference at 1.2V -&gt; Voh = ~1.8V
19845'3': Voh = 1.67*reference; e.g. reference at 1.2V -&gt; Voh = 2V
19846'4': Voh = 2.08*reference; e.g. reference at 1.2V -&gt; Voh = 2.5V
19847'5': Voh = 2.5*reference; e.g. reference at 1.2V -&gt; Voh = 3V
19848'6': Voh = 2.78*reference; e.g. reference at 1.2V -&gt; Voh = ~3.3V
19849'7': Voh = 4.16*reference; e.g. reference at 1.2V -&gt; Voh = 5.0V
19850Note: The upper value on Voh is limited to Vddio - 400mV</description>
19851                <bitRange>[7:5]</bitRange>
19852                <access>read-write</access>
19853              </field>
19854              <field>
19855                <name>VREG_EN23</name>
19856                <description>See corresponding definition for IO pins 0 and 1</description>
19857                <bitRange>[8:8]</bitRange>
19858                <access>read-write</access>
19859              </field>
19860              <field>
19861                <name>IBUF_SEL23</name>
19862                <description>See corresponding definition for IO pins 0 and 1</description>
19863                <bitRange>[9:9]</bitRange>
19864                <access>read-write</access>
19865              </field>
19866              <field>
19867                <name>VTRIP_SEL23</name>
19868                <description>See corresponding definition for IO pins 0 and 1</description>
19869                <bitRange>[10:10]</bitRange>
19870                <access>read-write</access>
19871              </field>
19872              <field>
19873                <name>VREF_SEL23</name>
19874                <description>See corresponding definition for IO pins 0 and 1</description>
19875                <bitRange>[12:11]</bitRange>
19876                <access>read-write</access>
19877              </field>
19878              <field>
19879                <name>VOH_SEL23</name>
19880                <description>See corresponding definition for IO pins 0 and 1</description>
19881                <bitRange>[15:13]</bitRange>
19882                <access>read-write</access>
19883              </field>
19884              <field>
19885                <name>VREG_EN45</name>
19886                <description>See corresponding definition for IO pins 0 and 1</description>
19887                <bitRange>[16:16]</bitRange>
19888                <access>read-write</access>
19889              </field>
19890              <field>
19891                <name>IBUF_SEL45</name>
19892                <description>See corresponding definition for IO pins 0 and 1</description>
19893                <bitRange>[17:17]</bitRange>
19894                <access>read-write</access>
19895              </field>
19896              <field>
19897                <name>VTRIP_SEL45</name>
19898                <description>See corresponding definition for IO pins 0 and 1</description>
19899                <bitRange>[18:18]</bitRange>
19900                <access>read-write</access>
19901              </field>
19902              <field>
19903                <name>VREF_SEL45</name>
19904                <description>See corresponding definition for IO pins 0 and 1</description>
19905                <bitRange>[20:19]</bitRange>
19906                <access>read-write</access>
19907              </field>
19908              <field>
19909                <name>VOH_SEL45</name>
19910                <description>See corresponding definition for IO pins 0 and 1</description>
19911                <bitRange>[23:21]</bitRange>
19912                <access>read-write</access>
19913              </field>
19914              <field>
19915                <name>VREG_EN67</name>
19916                <description>See corresponding definition for IO pins 0 and 1</description>
19917                <bitRange>[24:24]</bitRange>
19918                <access>read-write</access>
19919              </field>
19920              <field>
19921                <name>IBUF_SEL67</name>
19922                <description>See corresponding definition for IO pins 0 and 1</description>
19923                <bitRange>[25:25]</bitRange>
19924                <access>read-write</access>
19925              </field>
19926              <field>
19927                <name>VTRIP_SEL67</name>
19928                <description>See corresponding definition for IO pins 0 and 1</description>
19929                <bitRange>[26:26]</bitRange>
19930                <access>read-write</access>
19931              </field>
19932              <field>
19933                <name>VREF_SEL67</name>
19934                <description>See corresponding definition for IO pins 0 and 1</description>
19935                <bitRange>[28:27]</bitRange>
19936                <access>read-write</access>
19937              </field>
19938              <field>
19939                <name>VOH_SEL67</name>
19940                <description>See corresponding definition for IO pins 0 and 1</description>
19941                <bitRange>[31:29]</bitRange>
19942                <access>read-write</access>
19943              </field>
19944            </fields>
19945          </register>
19946          <register>
19947            <name>CFG_IN_AUTOLVL</name>
19948            <description>Port input buffer AUTOLVL configuration register</description>
19949            <addressOffset>0x58</addressOffset>
19950            <size>32</size>
19951            <access>read-write</access>
19952            <resetValue>0x0</resetValue>
19953            <resetMask>0xFF</resetMask>
19954            <fields>
19955              <field>
19956                <name>VTRIP_SEL0_1</name>
19957                <description>Configures the input buffer mode (trip points and hysteresis) for GPIO upper bit.  Lower bit is still selected by CFG_IN.VTRIP_SEL0_0 field.  This field is used along with CFG_IN.VTRIP_SEL0_0 field as below:
19958{CFG_IN_AUTOLVL.VTRIP_SEL0_1,CFG_IN.VTRIP_SEL0_0}:
199590,0: CMOS
199600,1: TTL
199611,0: input buffer is compatible with automotive.
199621,1: input buffer is compatible with automotvie</description>
19963                <bitRange>[0:0]</bitRange>
19964                <access>read-write</access>
19965                <enumeratedValues>
19966                  <enumeratedValue>
19967                    <name>CMOS_OR_TTL</name>
19968                    <description>Input buffer compatible with CMOS/TTL interfaces as described in CFG_IN.VTRIP_SEL0_0.</description>
19969                    <value>0</value>
19970                  </enumeratedValue>
19971                  <enumeratedValue>
19972                    <name>AUTO</name>
19973                    <description>Input buffer compatible with AUTO (elevated Vil) interfaces when used along with CFG_IN.VTRIP_SEL0_0.</description>
19974                    <value>1</value>
19975                  </enumeratedValue>
19976                </enumeratedValues>
19977              </field>
19978              <field>
19979                <name>VTRIP_SEL1_1</name>
19980                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
19981                <bitRange>[1:1]</bitRange>
19982                <access>read-write</access>
19983              </field>
19984              <field>
19985                <name>VTRIP_SEL2_1</name>
19986                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
19987                <bitRange>[2:2]</bitRange>
19988                <access>read-write</access>
19989              </field>
19990              <field>
19991                <name>VTRIP_SEL3_1</name>
19992                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
19993                <bitRange>[3:3]</bitRange>
19994                <access>read-write</access>
19995              </field>
19996              <field>
19997                <name>VTRIP_SEL4_1</name>
19998                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
19999                <bitRange>[4:4]</bitRange>
20000                <access>read-write</access>
20001              </field>
20002              <field>
20003                <name>VTRIP_SEL5_1</name>
20004                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
20005                <bitRange>[5:5]</bitRange>
20006                <access>read-write</access>
20007              </field>
20008              <field>
20009                <name>VTRIP_SEL6_1</name>
20010                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
20011                <bitRange>[6:6]</bitRange>
20012                <access>read-write</access>
20013              </field>
20014              <field>
20015                <name>VTRIP_SEL7_1</name>
20016                <description>Input buffer compatible with automotive (elevated Vil) interfaces.</description>
20017                <bitRange>[7:7]</bitRange>
20018                <access>read-write</access>
20019              </field>
20020            </fields>
20021          </register>
20022        </cluster>
20023        <register>
20024          <name>INTR_CAUSE0</name>
20025          <description>Interrupt port cause register 0</description>
20026          <addressOffset>0x4000</addressOffset>
20027          <size>32</size>
20028          <access>read-only</access>
20029          <resetValue>0x0</resetValue>
20030          <resetMask>0xFFFFFFFF</resetMask>
20031          <fields>
20032            <field>
20033              <name>PORT_INT</name>
20034              <description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PRT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
20035'0': Port has no pending interrupt
20036'1': Port has pending interrupt</description>
20037              <bitRange>[31:0]</bitRange>
20038              <access>read-only</access>
20039            </field>
20040          </fields>
20041        </register>
20042        <register>
20043          <name>INTR_CAUSE1</name>
20044          <description>Interrupt port cause register 1</description>
20045          <addressOffset>0x4004</addressOffset>
20046          <size>32</size>
20047          <access>read-only</access>
20048          <resetValue>0x0</resetValue>
20049          <resetMask>0xFFFFFFFF</resetMask>
20050          <fields>
20051            <field>
20052              <name>PORT_INT</name>
20053              <description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
20054'0': Port has no pending interrupt
20055'1': Port has pending interrupt</description>
20056              <bitRange>[31:0]</bitRange>
20057              <access>read-only</access>
20058            </field>
20059          </fields>
20060        </register>
20061        <register>
20062          <name>INTR_CAUSE2</name>
20063          <description>Interrupt port cause register 2</description>
20064          <addressOffset>0x4008</addressOffset>
20065          <size>32</size>
20066          <access>read-only</access>
20067          <resetValue>0x0</resetValue>
20068          <resetMask>0xFFFFFFFF</resetMask>
20069          <fields>
20070            <field>
20071              <name>PORT_INT</name>
20072              <description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
20073'0': Port has no pending interrupt
20074'1': Port has pending interrupt</description>
20075              <bitRange>[31:0]</bitRange>
20076              <access>read-only</access>
20077            </field>
20078          </fields>
20079        </register>
20080        <register>
20081          <name>INTR_CAUSE3</name>
20082          <description>Interrupt port cause register 3</description>
20083          <addressOffset>0x400C</addressOffset>
20084          <size>32</size>
20085          <access>read-only</access>
20086          <resetValue>0x0</resetValue>
20087          <resetMask>0xFFFFFFFF</resetMask>
20088          <fields>
20089            <field>
20090              <name>PORT_INT</name>
20091              <description>Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a combined interrupt line 'gpio_interrupt'. The software ISR reads the register to determine which IO port(s) is responsible for the combined interrupt line. Once, the IO port(s) is determined, the IO port's GPIO_PORT_INTR register is read to determine the IO pin(s) in the IO port that caused the interrupt.
20092'0': Port has no pending interrupt
20093'1': Port has pending interrupt</description>
20094              <bitRange>[31:0]</bitRange>
20095              <access>read-only</access>
20096            </field>
20097          </fields>
20098        </register>
20099        <register>
20100          <name>VDD_ACTIVE</name>
20101          <description>Extern power supply detection register</description>
20102          <addressOffset>0x4010</addressOffset>
20103          <size>32</size>
20104          <access>read-only</access>
20105          <resetValue>0x0</resetValue>
20106          <resetMask>0xC000FFFF</resetMask>
20107          <fields>
20108            <field>
20109              <name>VDDIO_ACTIVE</name>
20110              <description>Indicates presence or absence of VDDIO supplies (i.e. other than VDDD, VDDA) on the device (supplies are numbered 0..n-1).  Note that VDDIO supplies have basic (crude) supply detectors only.  If separate, robust, brown-out detection is desired on IO supplies, on-chip or off-chip analog resources need to provide it.  For these bits to work reliable, the supply must be within valid spec range (per datasheet) or held at ground.  Any in-between voltage has an undefined result.
20111'0': Supply is not present
20112'1': Supply is present
20113
20114When multiple VDDIO supplies are present, they will be assigned in alphanumeric ascending order to these bits during implementation.
20115For example 'vddusb, vddio_0, vddio_a, vbackup, vddio_r, vddio_1' are present then they will be assigned to these bits as below:
201160: vbackup,
201171: vddio_0,
201182: vddio_1,
201193: vddio_a,
201204: vddio_r,
201215: vddusb'</description>
20122              <bitRange>[15:0]</bitRange>
20123              <access>read-only</access>
20124            </field>
20125            <field>
20126              <name>VDDA_ACTIVE</name>
20127              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
20128              <bitRange>[30:30]</bitRange>
20129              <access>read-only</access>
20130            </field>
20131            <field>
20132              <name>VDDD_ACTIVE</name>
20133              <description>This bit indicates presence of the VDDD supply.  This bit will always read-back 1.  The VDDD supply has robust brown-out protection monitoring and it is not possible to read back this register without a valid supply. (This bit is used in certain test-modes to observe the brown-out detector status.)</description>
20134              <bitRange>[31:31]</bitRange>
20135              <access>read-only</access>
20136            </field>
20137          </fields>
20138        </register>
20139        <register>
20140          <name>VDD_INTR</name>
20141          <description>Supply detection interrupt register</description>
20142          <addressOffset>0x4014</addressOffset>
20143          <size>32</size>
20144          <access>read-write</access>
20145          <resetValue>0x0</resetValue>
20146          <resetMask>0xC000FFFF</resetMask>
20147          <fields>
20148            <field>
20149              <name>VDDIO_ACTIVE</name>
20150              <description>Supply state change detected.
20151'0': No change to supply detected
20152'1': Change to supply detected</description>
20153              <bitRange>[15:0]</bitRange>
20154              <access>read-write</access>
20155            </field>
20156            <field>
20157              <name>VDDA_ACTIVE</name>
20158              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
20159              <bitRange>[30:30]</bitRange>
20160              <access>read-write</access>
20161            </field>
20162            <field>
20163              <name>VDDD_ACTIVE</name>
20164              <description>The VDDD supply is always present during operation so a supply transition can not occur. This bit will always read back '1'.</description>
20165              <bitRange>[31:31]</bitRange>
20166              <access>read-write</access>
20167            </field>
20168          </fields>
20169        </register>
20170        <register>
20171          <name>VDD_INTR_MASK</name>
20172          <description>Supply detection interrupt mask register</description>
20173          <addressOffset>0x4018</addressOffset>
20174          <size>32</size>
20175          <access>read-write</access>
20176          <resetValue>0x0</resetValue>
20177          <resetMask>0xC000FFFF</resetMask>
20178          <fields>
20179            <field>
20180              <name>VDDIO_ACTIVE</name>
20181              <description>Masks supply interrupt on VDDIO.
20182'0': VDDIO interrupt forwarding disabled
20183'1': VDDIO interrupt forwarding enabled</description>
20184              <bitRange>[15:0]</bitRange>
20185              <access>read-write</access>
20186            </field>
20187            <field>
20188              <name>VDDA_ACTIVE</name>
20189              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
20190              <bitRange>[30:30]</bitRange>
20191              <access>read-write</access>
20192            </field>
20193            <field>
20194              <name>VDDD_ACTIVE</name>
20195              <description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
20196              <bitRange>[31:31]</bitRange>
20197              <access>read-write</access>
20198            </field>
20199          </fields>
20200        </register>
20201        <register>
20202          <name>VDD_INTR_MASKED</name>
20203          <description>Supply detection interrupt masked register</description>
20204          <addressOffset>0x401C</addressOffset>
20205          <size>32</size>
20206          <access>read-only</access>
20207          <resetValue>0x0</resetValue>
20208          <resetMask>0xC000FFFF</resetMask>
20209          <fields>
20210            <field>
20211              <name>VDDIO_ACTIVE</name>
20212              <description>Supply transition detected AND masked
20213'0': Interrupt was not forwarded to CPU
20214'1': Interrupt occurred and was forwarded to CPU</description>
20215              <bitRange>[15:0]</bitRange>
20216              <access>read-only</access>
20217            </field>
20218            <field>
20219              <name>VDDA_ACTIVE</name>
20220              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
20221              <bitRange>[30:30]</bitRange>
20222              <access>read-only</access>
20223            </field>
20224            <field>
20225              <name>VDDD_ACTIVE</name>
20226              <description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
20227              <bitRange>[31:31]</bitRange>
20228              <access>read-only</access>
20229            </field>
20230          </fields>
20231        </register>
20232        <register>
20233          <name>VDD_INTR_SET</name>
20234          <description>Supply detection interrupt set register</description>
20235          <addressOffset>0x4020</addressOffset>
20236          <size>32</size>
20237          <access>read-write</access>
20238          <resetValue>0x0</resetValue>
20239          <resetMask>0xC000FFFF</resetMask>
20240          <fields>
20241            <field>
20242              <name>VDDIO_ACTIVE</name>
20243              <description>Sets supply interrupt.
20244'0': Interrupt state not affected
20245'1': Interrupt set</description>
20246              <bitRange>[15:0]</bitRange>
20247              <access>read-write</access>
20248            </field>
20249            <field>
20250              <name>VDDA_ACTIVE</name>
20251              <description>Same as VDDIO_ACTIVE for the analog supply VDDA.</description>
20252              <bitRange>[30:30]</bitRange>
20253              <access>read-write</access>
20254            </field>
20255            <field>
20256              <name>VDDD_ACTIVE</name>
20257              <description>Same as VDDIO_ACTIVE for the digital supply VDDD.</description>
20258              <bitRange>[31:31]</bitRange>
20259              <access>read-write</access>
20260            </field>
20261          </fields>
20262        </register>
20263      </registers>
20264    </peripheral>
20265    <peripheral>
20266      <name>SMARTIO</name>
20267      <description>Programmable IO configuration</description>
20268      <baseAddress>0x40320000</baseAddress>
20269      <addressBlock>
20270        <offset>0</offset>
20271        <size>65536</size>
20272        <usage>registers</usage>
20273      </addressBlock>
20274      <registers>
20275        <cluster>
20276          <dim>10</dim>
20277          <dimIncrement>256</dimIncrement>
20278          <name>PRT[%s]</name>
20279          <description>Programmable IO port registers</description>
20280          <addressOffset>0x00000000</addressOffset>
20281          <register>
20282            <name>CTL</name>
20283            <description>Control register</description>
20284            <addressOffset>0x0</addressOffset>
20285            <size>32</size>
20286            <access>read-write</access>
20287            <resetValue>0x2001400</resetValue>
20288            <resetMask>0x82001F00</resetMask>
20289            <fields>
20290              <field>
20291                <name>BYPASS</name>
20292                <description>Bypass of the programmable IO, one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1', this field is used. When ENABLED is '0', this field is NOT used and SMARTIO fabric is always bypassed.
20293'0': No bypass (programmable SMARTIO fabric is exposed).
20294'1': Bypass (programmable SMARTIOIO fabric is hidden).</description>
20295                <bitRange>[7:0]</bitRange>
20296                <access>read-write</access>
20297              </field>
20298              <field>
20299                <name>CLOCK_SRC</name>
20300                <description>Clock ('clk_fabric') and reset ('rst_fabric_n') source selection:
20301'0': io_data_in[0]/'1'.
20302...
20303'7': io_data_in[7]/'1'.
20304'8': chip_data[0]/'1'.
20305...
20306'15': chip_data[7]/'1'.
20307'16': clk_smartio/rst_sys_act_n. Used for both Active functionality synchronous logic on 'clk_smartio'. This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'.
20308'17': clk_smartio/rst_sys_dpslp_n. Used for both DeepSleep functionality synchronous logic on 'clk_smartio' (note that 'clk_smartio' is NOT available in DeepSleep and Hibernate power modes).  This selection is intended for synchronous operation on a PCLK specified clock frequency ('clock_smartio_pos_en'). Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to 'clk_sys'.
20309'18': Same as '17'. Note that the M0S8 SMARTIO version used the Hibernate reset for this value, but the MXS40 SMARTIO version does not support Hibernate functionality.
20310'19': clk_lf/rst_lf_dpslp_n (note that 'clk_lf' is available in DeepSleep power mode). This selection is intended for synchronous operation on'clk_lf'. Note that the fabric's clocked elements are frequency aligned, but NOT phase aligned to other 'clk_lf' clocked elements.
20311'20'-'30': Clock source is constant '0'. Any of these clock sources should be selected when the IP is disabled to ensure low power consumption.
20312'31': asynchronous mode/'1'.  Select this when clockless operation is configured.
20313
20314NOTE: Two positive edges of the selected clock are required for the block to be enabled (to deactivate reset).  In asynchronous (clockless) mode clk_sys is used to enable the block, but is not available for clocking.</description>
20315                <bitRange>[12:8]</bitRange>
20316                <access>read-write</access>
20317              </field>
20318              <field>
20319                <name>HLD_OVR</name>
20320                <description>IO cell hold override functionality. In DeepSleep power mode, the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the SMARTIO is supposed to deliver DeepSleep output functionality on these IO pads. This field is used to control the hold override functionality from the SMARTIO:
20321'0': The HSIOM controls the IO cell hold override functionality ('hsiom_hld_ovr').
20322'1': The SMARTIO controls the IO cel hold override functionality:
20323- In bypass mode (ENABLED is '0' or BYPASS[i] is '1'), the HSIOM control is used.
20324- In NON bypass mode (ENABLED is '1' and BYPASS[i] is '0'), the SMARTIO sets hold override to 'pwr_hld_ovr_hib' to enable SMARTIO functionality in DeepSleep power mode (but disables it in Hibernate or Stop power mode).</description>
20325                <bitRange>[24:24]</bitRange>
20326                <access>read-write</access>
20327              </field>
20328              <field>
20329                <name>PIPELINE_EN</name>
20330                <description>Enable for pipeline register:
20331'0': Disabled (register is bypassed).
20332'1': Enabled.</description>
20333                <bitRange>[25:25]</bitRange>
20334                <access>read-write</access>
20335              </field>
20336              <field>
20337                <name>ENABLED</name>
20338                <description>Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured:
20339'0': Disabled (signals are bypassed; behavior as if BYPASS is 0xFF). When disabled, the fabric (data unit and LUTs) reset is activated.
20340
20341If the IP is disabled:
20342- The PIPELINE_EN register field should be set to '1', to ensure low power consumption by preventing combinatorial loops.
20343- The CLOCK_SRC register field should be set to '20'-'30' (clock is constant '0'), to ensure low power consumption.
20344
20345'1': Enabled. Once enabled, it takes 3 'clk_fabric' clock cycles till the fabric reset is de-activated and the fabric becomes fully functional. This ensures that the IO pins' input synchronizer states are flushed when the fabric is fully functional.</description>
20346                <bitRange>[31:31]</bitRange>
20347                <access>read-write</access>
20348              </field>
20349            </fields>
20350          </register>
20351          <register>
20352            <name>SYNC_CTL</name>
20353            <description>Synchronization control register</description>
20354            <addressOffset>0x10</addressOffset>
20355            <size>32</size>
20356            <access>read-write</access>
20357            <resetValue>0x0</resetValue>
20358            <resetMask>0x0</resetMask>
20359            <fields>
20360              <field>
20361                <name>IO_SYNC_EN</name>
20362                <description>Synchronization of the IO pin input signals to 'clk_fabric', one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i.
20363'0': No synchronization.
20364'1': Synchronization.</description>
20365                <bitRange>[7:0]</bitRange>
20366                <access>read-write</access>
20367              </field>
20368              <field>
20369                <name>CHIP_SYNC_EN</name>
20370                <description>Synchronization of the chip input signals to 'clk_fabric', one bit for each input: CHIP_SYNC_EN[i] is for input i.
20371'0': No synchronization.
20372'1': Synchronization.</description>
20373                <bitRange>[15:8]</bitRange>
20374                <access>read-write</access>
20375              </field>
20376            </fields>
20377          </register>
20378          <register>
20379            <dim>8</dim>
20380            <dimIncrement>4</dimIncrement>
20381            <name>LUT_SEL[%s]</name>
20382            <description>LUT component input selection</description>
20383            <addressOffset>0x20</addressOffset>
20384            <size>32</size>
20385            <access>read-write</access>
20386            <resetValue>0x0</resetValue>
20387            <resetMask>0x0</resetMask>
20388            <fields>
20389              <field>
20390                <name>LUT_TR0_SEL</name>
20391                <description>LUT input signal 'tr0_in' source selection:
20392'0': Data unit output.
20393'1': LUT 1 output.
20394'2': LUT 2 output.
20395'3': LUT 3 output.
20396'4': LUT 4 output.
20397'5': LUT 5 output.
20398'6': LUT 6 output.
20399'7': LUT 7 output.
20400'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7).
20401'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7).
20402'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7).
20403'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7).
20404'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7).
20405'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7).
20406'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7).
20407'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7).</description>
20408                <bitRange>[3:0]</bitRange>
20409                <access>read-write</access>
20410              </field>
20411              <field>
20412                <name>LUT_TR1_SEL</name>
20413                <description>LUT input signal 'tr1_in' source selection:
20414'0': LUT 0 output.
20415'1': LUT 1 output.
20416'2': LUT 2 output.
20417'3': LUT 3 output.
20418'4': LUT 4 output.
20419'5': LUT 5 output.
20420'6': LUT 6 output.
20421'7': LUT 7 output.
20422'8': chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7).
20423'9': chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7).
20424'10': chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7).
20425'11': chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7).
20426'12': io_data_in[0] (for LUTs 0, 1, 2, 3); io_data_in[4] (for LUTs 4, 5, 6, 7).
20427'13': io_data_in[1] (for LUTs 0, 1, 2, 3); io_data_in[5] (for LUTs 4, 5, 6, 7).
20428'14': io_data_in[2] (for LUTs 0, 1, 2, 3); io_data_in[6] (for LUTs 4, 5, 6, 7).
20429'15': io_data_in[3] (for LUTs 0, 1, 2, 3); io_data_in[7] (for LUTs 4, 5, 6, 7).</description>
20430                <bitRange>[11:8]</bitRange>
20431                <access>read-write</access>
20432              </field>
20433              <field>
20434                <name>LUT_TR2_SEL</name>
20435                <description>LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL.</description>
20436                <bitRange>[19:16]</bitRange>
20437                <access>read-write</access>
20438              </field>
20439            </fields>
20440          </register>
20441          <register>
20442            <dim>8</dim>
20443            <dimIncrement>4</dimIncrement>
20444            <name>LUT_CTL[%s]</name>
20445            <description>LUT component control register</description>
20446            <addressOffset>0x40</addressOffset>
20447            <size>32</size>
20448            <access>read-write</access>
20449            <resetValue>0x0</resetValue>
20450            <resetMask>0x0</resetMask>
20451            <fields>
20452              <field>
20453                <name>LUT</name>
20454                <description>LUT configuration. Depending on the LUT opcode LUT_OPC, the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in, tr1_in, tr2_in, the LUT configuration is used to determine the LUT output signal and the next sequential state (lut_reg).</description>
20455                <bitRange>[7:0]</bitRange>
20456                <access>read-write</access>
20457              </field>
20458              <field>
20459                <name>LUT_OPC</name>
20460                <description>LUT opcode specifies the LUT operation:
20461'0': Combinatoral output, no feedback.
20462   tr_out   = LUT[{tr2_in, tr1_in, tr0_in}].
20463'1': Combinatorial output, feedback.
20464   tr_out   = LUT[{lut_reg, tr1_in, tr0_in}].
20465On clock:
20466    lut_reg &lt;= tr_in2.
20467'2': Sequential output, no feedback.
20468   temp    = LUT[{tr2_in, tr1_in, tr0_in}].
20469   tr_out   = lut_reg.
20470On clock:
20471   lut_reg &lt;= temp.
20472'3': Register with asynchronous set and reset.
20473   tr_out           = lut_reg.
20474   enable          = (tr2_in ^ LUT[4]) | LUT[5].
20475   set               = enable &amp; (tr1_in ^ LUT[2]) &amp; LUT[3].
20476   clr                = enable &amp; (tr0_in ^ LUT[0]) &amp; LUT[1].
20477Asynchronously (no clock required):
20478   lut_reg         &lt;= if (clr) '0' else if (set) '1'</description>
20479                <bitRange>[9:8]</bitRange>
20480                <access>read-write</access>
20481              </field>
20482            </fields>
20483          </register>
20484          <register>
20485            <name>DU_SEL</name>
20486            <description>Data unit component input selection</description>
20487            <addressOffset>0xC0</addressOffset>
20488            <size>32</size>
20489            <access>read-write</access>
20490            <resetValue>0x0</resetValue>
20491            <resetMask>0x0</resetMask>
20492            <fields>
20493              <field>
20494                <name>DU_TR0_SEL</name>
20495                <description>Data unit input signal 'tr0_in' source selection:
20496'0': Constant '0'.
20497'1': Constant '1'.
20498'2': Data unit output.
20499'10-3': LUT 7 - 0 outputs.
20500Otherwise: Undefined.</description>
20501                <bitRange>[3:0]</bitRange>
20502                <access>read-write</access>
20503              </field>
20504              <field>
20505                <name>DU_TR1_SEL</name>
20506                <description>Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL.</description>
20507                <bitRange>[11:8]</bitRange>
20508                <access>read-write</access>
20509              </field>
20510              <field>
20511                <name>DU_TR2_SEL</name>
20512                <description>Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL.</description>
20513                <bitRange>[19:16]</bitRange>
20514                <access>read-write</access>
20515              </field>
20516              <field>
20517                <name>DU_DATA0_SEL</name>
20518                <description>Data unit input data 'data0_in' source selection:
20519'0': Constant '0'.
20520'1': chip_data[7:0].
20521'2': io_data_in[7:0].
20522'3': DATA.DATA MMIO register field.</description>
20523                <bitRange>[25:24]</bitRange>
20524                <access>read-write</access>
20525              </field>
20526              <field>
20527                <name>DU_DATA1_SEL</name>
20528                <description>Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL.</description>
20529                <bitRange>[29:28]</bitRange>
20530                <access>read-write</access>
20531              </field>
20532            </fields>
20533          </register>
20534          <register>
20535            <name>DU_CTL</name>
20536            <description>Data unit component control register</description>
20537            <addressOffset>0xC4</addressOffset>
20538            <size>32</size>
20539            <access>read-write</access>
20540            <resetValue>0x0</resetValue>
20541            <resetMask>0x0</resetMask>
20542            <fields>
20543              <field>
20544                <name>DU_SIZE</name>
20545                <description>Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g., if DU_SIZE is 7, the width is 8 bits.</description>
20546                <bitRange>[2:0]</bitRange>
20547                <access>read-write</access>
20548              </field>
20549              <field>
20550                <name>DU_OPC</name>
20551                <description>Data unit opcode specifies the data unit operation:
20552'1': INCR
20553'2': DECR
20554'3': INCR_WRAP
20555'4': DECR_WRAP
20556'5': INCR_DECR
20557'6': INCR_DECR_WRAP
20558'7': ROR
20559'8': SHR
20560'9': AND_OR
20561'10': SHR_MAJ3
20562'11': SHR_EQL.
20563Otherwise: Undefined.</description>
20564                <bitRange>[11:8]</bitRange>
20565                <access>read-write</access>
20566              </field>
20567            </fields>
20568          </register>
20569          <register>
20570            <name>DATA</name>
20571            <description>Data register</description>
20572            <addressOffset>0xF0</addressOffset>
20573            <size>32</size>
20574            <access>read-write</access>
20575            <resetValue>0x0</resetValue>
20576            <resetMask>0x0</resetMask>
20577            <fields>
20578              <field>
20579                <name>DATA</name>
20580                <description>Data unit input data source.</description>
20581                <bitRange>[7:0]</bitRange>
20582                <access>read-write</access>
20583              </field>
20584            </fields>
20585          </register>
20586        </cluster>
20587      </registers>
20588    </peripheral>
20589    <peripheral>
20590      <name>LPCOMP</name>
20591      <description>Low Power Comparators</description>
20592      <baseAddress>0x40350000</baseAddress>
20593      <addressBlock>
20594        <offset>0</offset>
20595        <size>65536</size>
20596        <usage>registers</usage>
20597      </addressBlock>
20598      <registers>
20599        <register>
20600          <name>CONFIG</name>
20601          <description>LPCOMP Configuration Register</description>
20602          <addressOffset>0x0</addressOffset>
20603          <size>32</size>
20604          <access>read-write</access>
20605          <resetValue>0x0</resetValue>
20606          <resetMask>0xC0000000</resetMask>
20607          <fields>
20608            <field>
20609              <name>LPREF_EN</name>
20610              <description>Enable the local reference generator circuit to generate the local Vref and ibias. This bit must be set for DeepSleep or Hibernate operation.</description>
20611              <bitRange>[30:30]</bitRange>
20612              <access>read-write</access>
20613            </field>
20614            <field>
20615              <name>ENABLED</name>
20616              <description>- 0: IP disabled (put analog in power down, open all switches, all clocks off, leakage power only)
20617- 1: IP enabled</description>
20618              <bitRange>[31:31]</bitRange>
20619              <access>read-write</access>
20620            </field>
20621          </fields>
20622        </register>
20623        <register>
20624          <name>STATUS</name>
20625          <description>LPCOMP Status Register</description>
20626          <addressOffset>0x4</addressOffset>
20627          <size>32</size>
20628          <access>read-only</access>
20629          <resetValue>0x0</resetValue>
20630          <resetMask>0x10001</resetMask>
20631          <fields>
20632            <field>
20633              <name>OUT0</name>
20634              <description>Current output value of the comparator 0.</description>
20635              <bitRange>[0:0]</bitRange>
20636              <access>read-only</access>
20637            </field>
20638            <field>
20639              <name>OUT1</name>
20640              <description>Current output value of the comparator 1.</description>
20641              <bitRange>[16:16]</bitRange>
20642              <access>read-only</access>
20643            </field>
20644          </fields>
20645        </register>
20646        <register>
20647          <name>INTR</name>
20648          <description>LPCOMP Interrupt request register</description>
20649          <addressOffset>0x10</addressOffset>
20650          <size>32</size>
20651          <access>read-write</access>
20652          <resetValue>0x0</resetValue>
20653          <resetMask>0x3</resetMask>
20654          <fields>
20655            <field>
20656              <name>COMP0</name>
20657              <description>Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit.</description>
20658              <bitRange>[0:0]</bitRange>
20659              <access>read-write</access>
20660            </field>
20661            <field>
20662              <name>COMP1</name>
20663              <description>Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit.</description>
20664              <bitRange>[1:1]</bitRange>
20665              <access>read-write</access>
20666            </field>
20667          </fields>
20668        </register>
20669        <register>
20670          <name>INTR_SET</name>
20671          <description>LPCOMP Interrupt set register</description>
20672          <addressOffset>0x14</addressOffset>
20673          <size>32</size>
20674          <access>read-write</access>
20675          <resetValue>0x0</resetValue>
20676          <resetMask>0x3</resetMask>
20677          <fields>
20678            <field>
20679              <name>COMP0</name>
20680              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
20681              <bitRange>[0:0]</bitRange>
20682              <access>read-write</access>
20683            </field>
20684            <field>
20685              <name>COMP1</name>
20686              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
20687              <bitRange>[1:1]</bitRange>
20688              <access>read-write</access>
20689            </field>
20690          </fields>
20691        </register>
20692        <register>
20693          <name>INTR_MASK</name>
20694          <description>LPCOMP Interrupt request mask</description>
20695          <addressOffset>0x18</addressOffset>
20696          <size>32</size>
20697          <access>read-write</access>
20698          <resetValue>0x0</resetValue>
20699          <resetMask>0x3</resetMask>
20700          <fields>
20701            <field>
20702              <name>COMP0_MASK</name>
20703              <description>Mask bit for corresponding bit in interrupt request register.</description>
20704              <bitRange>[0:0]</bitRange>
20705              <access>read-write</access>
20706            </field>
20707            <field>
20708              <name>COMP1_MASK</name>
20709              <description>Mask bit for corresponding bit in interrupt request register.</description>
20710              <bitRange>[1:1]</bitRange>
20711              <access>read-write</access>
20712            </field>
20713          </fields>
20714        </register>
20715        <register>
20716          <name>INTR_MASKED</name>
20717          <description>LPCOMP Interrupt request masked</description>
20718          <addressOffset>0x1C</addressOffset>
20719          <size>32</size>
20720          <access>read-only</access>
20721          <resetValue>0x0</resetValue>
20722          <resetMask>0x3</resetMask>
20723          <fields>
20724            <field>
20725              <name>COMP0_MASKED</name>
20726              <description>Logical and of corresponding request and mask bits.</description>
20727              <bitRange>[0:0]</bitRange>
20728              <access>read-only</access>
20729            </field>
20730            <field>
20731              <name>COMP1_MASKED</name>
20732              <description>Logical and of corresponding request and mask bits.</description>
20733              <bitRange>[1:1]</bitRange>
20734              <access>read-only</access>
20735            </field>
20736          </fields>
20737        </register>
20738        <register>
20739          <name>CMP0_CTRL</name>
20740          <description>Comparator 0 control Register</description>
20741          <addressOffset>0x40</addressOffset>
20742          <size>32</size>
20743          <access>read-write</access>
20744          <resetValue>0x0</resetValue>
20745          <resetMask>0xCE3</resetMask>
20746          <fields>
20747            <field>
20748              <name>MODE0</name>
20749              <description>Operating mode for the comparator</description>
20750              <bitRange>[1:0]</bitRange>
20751              <access>read-write</access>
20752              <enumeratedValues>
20753                <enumeratedValue>
20754                  <name>OFF</name>
20755                  <description>Off</description>
20756                  <value>0</value>
20757                </enumeratedValue>
20758                <enumeratedValue>
20759                  <name>ULP</name>
20760                  <description>Ultra lowpower operating mode (uses less power, &lt; 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used.</description>
20761                  <value>1</value>
20762                </enumeratedValue>
20763                <enumeratedValue>
20764                  <name>LP</name>
20765                  <description>Low Power operating mode (uses more power, &lt;10uA @@@ TBD). In this mode the iref from SRSS will be used.</description>
20766                  <value>2</value>
20767                </enumeratedValue>
20768                <enumeratedValue>
20769                  <name>NORMAL</name>
20770                  <description>Normal, full speed power operating mode (uses &lt;150uA). In this mode the iref from SRSS will be used.</description>
20771                  <value>3</value>
20772                </enumeratedValue>
20773              </enumeratedValues>
20774            </field>
20775            <field>
20776              <name>HYST0</name>
20777              <description>Add 30mV hysteresis to the comparator
207780= Disable Hysteresis
207791= Enable Hysteresis</description>
20780              <bitRange>[5:5]</bitRange>
20781              <access>read-write</access>
20782            </field>
20783            <field>
20784              <name>INTTYPE0</name>
20785              <description>Sets which edge will trigger an IRQ</description>
20786              <bitRange>[7:6]</bitRange>
20787              <access>read-write</access>
20788              <enumeratedValues>
20789                <enumeratedValue>
20790                  <name>DISABLE</name>
20791                  <description>Disabled, no interrupts will be detected</description>
20792                  <value>0</value>
20793                </enumeratedValue>
20794                <enumeratedValue>
20795                  <name>RISING</name>
20796                  <description>Rising edge</description>
20797                  <value>1</value>
20798                </enumeratedValue>
20799                <enumeratedValue>
20800                  <name>FALLING</name>
20801                  <description>Falling edge</description>
20802                  <value>2</value>
20803                </enumeratedValue>
20804                <enumeratedValue>
20805                  <name>BOTH</name>
20806                  <description>Both rising and falling edges</description>
20807                  <value>3</value>
20808                </enumeratedValue>
20809              </enumeratedValues>
20810            </field>
20811            <field>
20812              <name>DSI_BYPASS0</name>
20813              <description>Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async).
20814Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin.</description>
20815              <bitRange>[10:10]</bitRange>
20816              <access>read-write</access>
20817            </field>
20818            <field>
20819              <name>DSI_LEVEL0</name>
20820              <description>Synchronous comparator DSI (trigger) output  : 0=pulse, 1=level</description>
20821              <bitRange>[11:11]</bitRange>
20822              <access>read-write</access>
20823            </field>
20824          </fields>
20825        </register>
20826        <register>
20827          <name>CMP0_SW</name>
20828          <description>Comparator 0 switch control</description>
20829          <addressOffset>0x50</addressOffset>
20830          <size>32</size>
20831          <access>read-write</access>
20832          <resetValue>0x0</resetValue>
20833          <resetMask>0xF7</resetMask>
20834          <fields>
20835            <field>
20836              <name>CMP0_IP0</name>
20837              <description>Comparator 0 positive terminal isolation switch to GPIO</description>
20838              <bitRange>[0:0]</bitRange>
20839              <access>read-write</access>
20840            </field>
20841            <field>
20842              <name>CMP0_AP0</name>
20843              <description>Comparator 0 positive terminal  switch to amuxbusA</description>
20844              <bitRange>[1:1]</bitRange>
20845              <access>read-write</access>
20846            </field>
20847            <field>
20848              <name>CMP0_BP0</name>
20849              <description>Comparator 0 positive terminal  switch to amuxbusB</description>
20850              <bitRange>[2:2]</bitRange>
20851              <access>read-write</access>
20852            </field>
20853            <field>
20854              <name>CMP0_IN0</name>
20855              <description>Comparator 0 negative terminal isolation switch to GPIO</description>
20856              <bitRange>[4:4]</bitRange>
20857              <access>read-write</access>
20858            </field>
20859            <field>
20860              <name>CMP0_AN0</name>
20861              <description>Comparator 0 negative terminal  switch to amuxbusA</description>
20862              <bitRange>[5:5]</bitRange>
20863              <access>read-write</access>
20864            </field>
20865            <field>
20866              <name>CMP0_BN0</name>
20867              <description>Comparator 0 negative terminal  switch to amuxbusB</description>
20868              <bitRange>[6:6]</bitRange>
20869              <access>read-write</access>
20870            </field>
20871            <field>
20872              <name>CMP0_VN0</name>
20873              <description>Comparator 0 negative terminal  switch to local Vref  (LPREF_EN must be set)</description>
20874              <bitRange>[7:7]</bitRange>
20875              <access>read-write</access>
20876            </field>
20877          </fields>
20878        </register>
20879        <register>
20880          <name>CMP0_SW_CLEAR</name>
20881          <description>Comparator 0 switch control clear</description>
20882          <addressOffset>0x54</addressOffset>
20883          <size>32</size>
20884          <access>read-write</access>
20885          <resetValue>0x0</resetValue>
20886          <resetMask>0xF7</resetMask>
20887          <fields>
20888            <field>
20889              <name>CMP0_IP0</name>
20890              <description>see corresponding bit in CMP0_SW</description>
20891              <bitRange>[0:0]</bitRange>
20892              <access>read-write</access>
20893            </field>
20894            <field>
20895              <name>CMP0_AP0</name>
20896              <description>see corresponding bit in CMP0_SW</description>
20897              <bitRange>[1:1]</bitRange>
20898              <access>read-write</access>
20899            </field>
20900            <field>
20901              <name>CMP0_BP0</name>
20902              <description>see corresponding bit in CMP0_SW</description>
20903              <bitRange>[2:2]</bitRange>
20904              <access>read-write</access>
20905            </field>
20906            <field>
20907              <name>CMP0_IN0</name>
20908              <description>see corresponding bit in CMP0_SW</description>
20909              <bitRange>[4:4]</bitRange>
20910              <access>read-write</access>
20911            </field>
20912            <field>
20913              <name>CMP0_AN0</name>
20914              <description>see corresponding bit in CMP0_SW</description>
20915              <bitRange>[5:5]</bitRange>
20916              <access>read-write</access>
20917            </field>
20918            <field>
20919              <name>CMP0_BN0</name>
20920              <description>see corresponding bit in CMP0_SW</description>
20921              <bitRange>[6:6]</bitRange>
20922              <access>read-write</access>
20923            </field>
20924            <field>
20925              <name>CMP0_VN0</name>
20926              <description>see corresponding bit in CMP0_SW</description>
20927              <bitRange>[7:7]</bitRange>
20928              <access>read-write</access>
20929            </field>
20930          </fields>
20931        </register>
20932        <register>
20933          <name>CMP1_CTRL</name>
20934          <description>Comparator 1 control Register</description>
20935          <addressOffset>0x80</addressOffset>
20936          <size>32</size>
20937          <access>read-write</access>
20938          <resetValue>0x0</resetValue>
20939          <resetMask>0xCE3</resetMask>
20940          <fields>
20941            <field>
20942              <name>MODE1</name>
20943              <description>Operating mode for the comparator</description>
20944              <bitRange>[1:0]</bitRange>
20945              <access>read-write</access>
20946              <enumeratedValues>
20947                <enumeratedValue>
20948                  <name>OFF</name>
20949                  <description>Off</description>
20950                  <value>0</value>
20951                </enumeratedValue>
20952                <enumeratedValue>
20953                  <name>ULP</name>
20954                  <description>Ultra lowpower operating mode (uses less power, &lt; 300nA), must be used for DeepSleep or Hibernate. Only in this mode a local iref will be used.</description>
20955                  <value>1</value>
20956                </enumeratedValue>
20957                <enumeratedValue>
20958                  <name>LP</name>
20959                  <description>Low Power operating mode (uses more power, &lt;10uA @@@ TBD). In this mode the iref from SRSS will be used.</description>
20960                  <value>2</value>
20961                </enumeratedValue>
20962                <enumeratedValue>
20963                  <name>NORMAL</name>
20964                  <description>Normal, full speed power operating mode (uses &lt;150uA). In this mode the iref from SRSS will be used.</description>
20965                  <value>3</value>
20966                </enumeratedValue>
20967              </enumeratedValues>
20968            </field>
20969            <field>
20970              <name>HYST1</name>
20971              <description>Add 30mV hysteresis to the comparator
209720= Disable Hysteresis
209731= Enable Hysteresis</description>
20974              <bitRange>[5:5]</bitRange>
20975              <access>read-write</access>
20976            </field>
20977            <field>
20978              <name>INTTYPE1</name>
20979              <description>Sets which edge will trigger an IRQ</description>
20980              <bitRange>[7:6]</bitRange>
20981              <access>read-write</access>
20982              <enumeratedValues>
20983                <enumeratedValue>
20984                  <name>DISABLE</name>
20985                  <description>Disabled, no interrupts will be detected</description>
20986                  <value>0</value>
20987                </enumeratedValue>
20988                <enumeratedValue>
20989                  <name>RISING</name>
20990                  <description>Rising edge</description>
20991                  <value>1</value>
20992                </enumeratedValue>
20993                <enumeratedValue>
20994                  <name>FALLING</name>
20995                  <description>Falling edge</description>
20996                  <value>2</value>
20997                </enumeratedValue>
20998                <enumeratedValue>
20999                  <name>BOTH</name>
21000                  <description>Both rising and falling edges</description>
21001                  <value>3</value>
21002                </enumeratedValue>
21003              </enumeratedValues>
21004            </field>
21005            <field>
21006              <name>DSI_BYPASS1</name>
21007              <description>Asynchronous: bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse), 1=bypass (output async).
21008Note that in DeepSleep mode this bit needs to be set to observe the DSI output on the dedicated pin.</description>
21009              <bitRange>[10:10]</bitRange>
21010              <access>read-write</access>
21011            </field>
21012            <field>
21013              <name>DSI_LEVEL1</name>
21014              <description>Synchronous comparator DSI (trigger) output  : 0=pulse, 1=level</description>
21015              <bitRange>[11:11]</bitRange>
21016              <access>read-write</access>
21017            </field>
21018          </fields>
21019        </register>
21020        <register>
21021          <name>CMP1_SW</name>
21022          <description>Comparator 1 switch control</description>
21023          <addressOffset>0x90</addressOffset>
21024          <size>32</size>
21025          <access>read-write</access>
21026          <resetValue>0x0</resetValue>
21027          <resetMask>0xF7</resetMask>
21028          <fields>
21029            <field>
21030              <name>CMP1_IP1</name>
21031              <description>Comparator 1 positive terminal isolation switch to GPIO</description>
21032              <bitRange>[0:0]</bitRange>
21033              <access>read-write</access>
21034            </field>
21035            <field>
21036              <name>CMP1_AP1</name>
21037              <description>Comparator 1 positive terminal  switch to amuxbusA</description>
21038              <bitRange>[1:1]</bitRange>
21039              <access>read-write</access>
21040            </field>
21041            <field>
21042              <name>CMP1_BP1</name>
21043              <description>Comparator 1 positive terminal  switch to amuxbusB</description>
21044              <bitRange>[2:2]</bitRange>
21045              <access>read-write</access>
21046            </field>
21047            <field>
21048              <name>CMP1_IN1</name>
21049              <description>Comparator 1 negative terminal isolation switch to GPIO</description>
21050              <bitRange>[4:4]</bitRange>
21051              <access>read-write</access>
21052            </field>
21053            <field>
21054              <name>CMP1_AN1</name>
21055              <description>Comparator 1 negative terminal  switch to amuxbusA</description>
21056              <bitRange>[5:5]</bitRange>
21057              <access>read-write</access>
21058            </field>
21059            <field>
21060              <name>CMP1_BN1</name>
21061              <description>Comparator 1 negative terminal  switch to amuxbusB</description>
21062              <bitRange>[6:6]</bitRange>
21063              <access>read-write</access>
21064            </field>
21065            <field>
21066              <name>CMP1_VN1</name>
21067              <description>Comparator 1 negative terminal  switch to local Vref  (LPREF_EN must be set)</description>
21068              <bitRange>[7:7]</bitRange>
21069              <access>read-write</access>
21070            </field>
21071          </fields>
21072        </register>
21073        <register>
21074          <name>CMP1_SW_CLEAR</name>
21075          <description>Comparator 1 switch control clear</description>
21076          <addressOffset>0x94</addressOffset>
21077          <size>32</size>
21078          <access>read-write</access>
21079          <resetValue>0x0</resetValue>
21080          <resetMask>0xF7</resetMask>
21081          <fields>
21082            <field>
21083              <name>CMP1_IP1</name>
21084              <description>see corresponding bit in CMP1_SW</description>
21085              <bitRange>[0:0]</bitRange>
21086              <access>read-write</access>
21087            </field>
21088            <field>
21089              <name>CMP1_AP1</name>
21090              <description>see corresponding bit in CMP1_SW</description>
21091              <bitRange>[1:1]</bitRange>
21092              <access>read-write</access>
21093            </field>
21094            <field>
21095              <name>CMP1_BP1</name>
21096              <description>see corresponding bit in CMP1_SW</description>
21097              <bitRange>[2:2]</bitRange>
21098              <access>read-write</access>
21099            </field>
21100            <field>
21101              <name>CMP1_IN1</name>
21102              <description>see corresponding bit in CMP1_SW</description>
21103              <bitRange>[4:4]</bitRange>
21104              <access>read-write</access>
21105            </field>
21106            <field>
21107              <name>CMP1_AN1</name>
21108              <description>see corresponding bit in CMP1_SW</description>
21109              <bitRange>[5:5]</bitRange>
21110              <access>read-write</access>
21111            </field>
21112            <field>
21113              <name>CMP1_BN1</name>
21114              <description>see corresponding bit in CMP1_SW</description>
21115              <bitRange>[6:6]</bitRange>
21116              <access>read-write</access>
21117            </field>
21118            <field>
21119              <name>CMP1_VN1</name>
21120              <description>see corresponding bit in CMP1_SW</description>
21121              <bitRange>[7:7]</bitRange>
21122              <access>read-write</access>
21123            </field>
21124          </fields>
21125        </register>
21126      </registers>
21127    </peripheral>
21128    <peripheral>
21129      <name>CSD0</name>
21130      <description>Capsense Controller</description>
21131      <headerStructName>CSD</headerStructName>
21132      <baseAddress>0x40360000</baseAddress>
21133      <addressBlock>
21134        <offset>0</offset>
21135        <size>4096</size>
21136        <usage>registers</usage>
21137      </addressBlock>
21138      <registers>
21139        <register>
21140          <name>CONFIG</name>
21141          <description>Configuration and Control</description>
21142          <addressOffset>0x0</addressOffset>
21143          <size>32</size>
21144          <access>read-write</access>
21145          <resetValue>0x4000000</resetValue>
21146          <resetMask>0xCF0E1DF1</resetMask>
21147          <fields>
21148            <field>
21149              <name>IREF_SEL</name>
21150              <description>Select Iref supply.</description>
21151              <bitRange>[0:0]</bitRange>
21152              <access>read-write</access>
21153              <enumeratedValues>
21154                <enumeratedValue>
21155                  <name>IREF_SRSS</name>
21156                  <description>select SRSS Iref (default)</description>
21157                  <value>0</value>
21158                </enumeratedValue>
21159                <enumeratedValue>
21160                  <name>IREF_PASS</name>
21161                  <description>select PASS.AREF Iref, only available if PASS IP is on the chip.</description>
21162                  <value>1</value>
21163                </enumeratedValue>
21164              </enumeratedValues>
21165            </field>
21166            <field>
21167              <name>FILTER_DELAY</name>
21168              <description>This value determines the number of cycles that the digital filter makes the CSDCMP output ignored while the counter counts and IDAC is on.
21169When set to 0 the digital filter is off. When set to any other value the ignoring will last for FILTER_DELAY clk_csd cycles after the start of each measurement and from the first comparator trip to the end of each measurement.</description>
21170              <bitRange>[8:4]</bitRange>
21171              <access>read-write</access>
21172            </field>
21173            <field>
21174              <name>SHIELD_DELAY</name>
21175              <description>Selects the delay by which csd_shield is delayed relative to csd_sense.</description>
21176              <bitRange>[11:10]</bitRange>
21177              <access>read-write</access>
21178              <enumeratedValues>
21179                <enumeratedValue>
21180                  <name>OFF</name>
21181                  <description>Delay line is off, csd_shield=csd_sense</description>
21182                  <value>0</value>
21183                </enumeratedValue>
21184                <enumeratedValue>
21185                  <name>D5NS</name>
21186                  <description>Introduces a 5ns delay (typ)</description>
21187                  <value>1</value>
21188                </enumeratedValue>
21189                <enumeratedValue>
21190                  <name>D10NS</name>
21191                  <description>Introduces a 10ns delay (typ)</description>
21192                  <value>2</value>
21193                </enumeratedValue>
21194                <enumeratedValue>
21195                  <name>D20NS</name>
21196                  <description>Introduces a 20ns delay (typ)</description>
21197                  <value>3</value>
21198                </enumeratedValue>
21199              </enumeratedValues>
21200            </field>
21201            <field>
21202              <name>SENSE_EN</name>
21203              <description>Enables the sense modulator output.
212040: all switches, static or dynamic, are open and IDAC in CSD mode is off
212051: switches and IDAC can be closed/on as per MMIO setting and CSD sequencer.</description>
21206              <bitRange>[12:12]</bitRange>
21207              <access>read-write</access>
21208            </field>
21209            <field>
21210              <name>FULL_WAVE</name>
21211              <description>Enables full wave cap sensing mode</description>
21212              <bitRange>[17:17]</bitRange>
21213              <access>read-write</access>
21214              <enumeratedValues>
21215                <enumeratedValue>
21216                  <name>HALFWAVE</name>
21217                  <description>Half Wave mode (normal).
21218In this mode the comparator always trips in the same direction (positive or negative edge) and the same Vref, i.e. no polarity change.</description>
21219                  <value>0</value>
21220                </enumeratedValue>
21221                <enumeratedValue>
21222                  <name>FULLWAVE</name>
21223                  <description>Full Wave mode.
21224In this mode the comparator trips in opposite direction and with different Vref in each phase, i.e. the polarity flips.</description>
21225                  <value>1</value>
21226                </enumeratedValue>
21227              </enumeratedValues>
21228            </field>
21229            <field>
21230              <name>MUTUAL_CAP</name>
21231              <description>Enables mutual cap sensing mode</description>
21232              <bitRange>[18:18]</bitRange>
21233              <access>read-write</access>
21234              <enumeratedValues>
21235                <enumeratedValue>
21236                  <name>SELFCAP</name>
21237                  <description>Self-cap mode (configure sense line as CSD_SENSE)</description>
21238                  <value>0</value>
21239                </enumeratedValue>
21240                <enumeratedValue>
21241                  <name>MUTUALCAP</name>
21242                  <description>Mutual-cap mode (configure Tx line as CSD_SENSE, inverted Tx line as CSD_SHIELD and Rx Line as AMUXA). In this mode the polarity bit of the IDAC is controlled by csd_sense.</description>
21243                  <value>1</value>
21244                </enumeratedValue>
21245              </enumeratedValues>
21246            </field>
21247            <field>
21248              <name>CSX_DUAL_CNT</name>
21249              <description>Enable the use of two counters for MUTUAL cap sensing mode (CSX), do not use when MUTUAL_CAP=0</description>
21250              <bitRange>[19:19]</bitRange>
21251              <access>read-write</access>
21252              <enumeratedValues>
21253                <enumeratedValue>
21254                  <name>ONE</name>
21255                  <description>Use one counter for both phases (source and sink).</description>
21256                  <value>0</value>
21257                </enumeratedValue>
21258                <enumeratedValue>
21259                  <name>TWO</name>
21260                  <description>Use two counters, separate count for when csd_sense is high and when csd_sense is low.</description>
21261                  <value>1</value>
21262                </enumeratedValue>
21263              </enumeratedValues>
21264            </field>
21265            <field>
21266              <name>DSI_COUNT_SEL</name>
21267              <description>Select what to output  on the dsi_count bus.</description>
21268              <bitRange>[24:24]</bitRange>
21269              <access>read-write</access>
21270              <enumeratedValues>
21271                <enumeratedValue>
21272                  <name>CSD_RESULT</name>
21273                  <description>depending on the dsi_count_val_sel input either output  RESULT_VAL1.VALUE (0) or RESULT_VAL2.VALUE (1) on the dsi_count bus. Note that dsi_count_val_sel is not synchronized, i.e. it controls the mux combinatorially.</description>
21274                  <value>0</value>
21275                </enumeratedValue>
21276                <enumeratedValue>
21277                  <name>ADC_RESULT</name>
21278                  <description>output ADC_RES.VIN_CNT on the dsi_count bus</description>
21279                  <value>1</value>
21280                </enumeratedValue>
21281              </enumeratedValues>
21282            </field>
21283            <field>
21284              <name>DSI_SAMPLE_EN</name>
21285              <description>Enables the use of the dsi_sample_in input instead of the comparator output to strobe COUNTER.</description>
21286              <bitRange>[25:25]</bitRange>
21287              <access>read-write</access>
21288            </field>
21289            <field>
21290              <name>SAMPLE_SYNC</name>
21291              <description>Enables double synchronizing of sample input from DSI (only relevant when DSI_SAMPLE_EN=1).</description>
21292              <bitRange>[26:26]</bitRange>
21293              <access>read-write</access>
21294            </field>
21295            <field>
21296              <name>DSI_SENSE_EN</name>
21297              <description>Enables the use of the dsi_sense_in input instead of the internally generated modulation signal to drive csd_sense and csd_shield signals.</description>
21298              <bitRange>[27:27]</bitRange>
21299              <access>read-write</access>
21300            </field>
21301            <field>
21302              <name>LP_MODE</name>
21303              <description>Select the power mode for the CSD components (REFGEN, AMBUF, CSDCMP, HSCMP):
213040: High Power mode
213051: Low Power mode</description>
21306              <bitRange>[30:30]</bitRange>
21307              <access>read-write</access>
21308            </field>
21309            <field>
21310              <name>ENABLE</name>
21311              <description>Master enable of the CSDv2 IP.  Must be set to 1 for any CSDv2, ADC or IDAC operation to function.
21312When 0 all analog components will be off and all switches will be open.</description>
21313              <bitRange>[31:31]</bitRange>
21314              <access>read-write</access>
21315            </field>
21316          </fields>
21317        </register>
21318        <register>
21319          <name>SPARE</name>
21320          <description>Spare MMIO</description>
21321          <addressOffset>0x4</addressOffset>
21322          <size>32</size>
21323          <access>read-write</access>
21324          <resetValue>0x0</resetValue>
21325          <resetMask>0xF</resetMask>
21326          <fields>
21327            <field>
21328              <name>SPARE</name>
21329              <description>Spare MMIO</description>
21330              <bitRange>[3:0]</bitRange>
21331              <access>read-write</access>
21332            </field>
21333          </fields>
21334        </register>
21335        <register>
21336          <name>STATUS</name>
21337          <description>Status Register</description>
21338          <addressOffset>0x80</addressOffset>
21339          <size>32</size>
21340          <access>read-only</access>
21341          <resetValue>0x0</resetValue>
21342          <resetMask>0xE</resetMask>
21343          <fields>
21344            <field>
21345              <name>CSD_SENSE</name>
21346              <description>Signal used to drive the Cs switches.</description>
21347              <bitRange>[1:1]</bitRange>
21348              <access>read-only</access>
21349            </field>
21350            <field>
21351              <name>HSCMP_OUT</name>
21352              <description>Output of reference buffer comparator used to charge up Cmod and/or Csh_tank (synchronized)</description>
21353              <bitRange>[2:2]</bitRange>
21354              <access>read-only</access>
21355              <enumeratedValues>
21356                <enumeratedValue>
21357                  <name>C_LT_VREF</name>
21358                  <description>Vin &lt; Vref</description>
21359                  <value>0</value>
21360                </enumeratedValue>
21361                <enumeratedValue>
21362                  <name>C_GT_VREF</name>
21363                  <description>Vin &gt; Vref</description>
21364                  <value>1</value>
21365                </enumeratedValue>
21366              </enumeratedValues>
21367            </field>
21368            <field>
21369              <name>CSDCMP_OUT</name>
21370              <description>Output of main sensing comparator (synchronized)</description>
21371              <bitRange>[3:3]</bitRange>
21372              <access>read-only</access>
21373            </field>
21374          </fields>
21375        </register>
21376        <register>
21377          <name>STAT_SEQ</name>
21378          <description>Current Sequencer status</description>
21379          <addressOffset>0x84</addressOffset>
21380          <size>32</size>
21381          <access>read-only</access>
21382          <resetValue>0x0</resetValue>
21383          <resetMask>0x70007</resetMask>
21384          <fields>
21385            <field>
21386              <name>SEQ_STATE</name>
21387              <description>CSD sequencer state</description>
21388              <bitRange>[2:0]</bitRange>
21389              <access>read-only</access>
21390            </field>
21391            <field>
21392              <name>ADC_STATE</name>
21393              <description>ADC sequencer state (only relevant after SEQ_STATE has reached SAMPLE_NORM and ADC sequencer has started)</description>
21394              <bitRange>[18:16]</bitRange>
21395              <access>read-only</access>
21396            </field>
21397          </fields>
21398        </register>
21399        <register>
21400          <name>STAT_CNTS</name>
21401          <description>Current status counts</description>
21402          <addressOffset>0x88</addressOffset>
21403          <size>32</size>
21404          <access>read-only</access>
21405          <resetValue>0x0</resetValue>
21406          <resetMask>0xFFFF</resetMask>
21407          <fields>
21408            <field>
21409              <name>NUM_CONV</name>
21410              <description>Current number of conversions remaining when in Sample_* states (note that in AutoZero* states the same down counter is reused to count the cycles)</description>
21411              <bitRange>[15:0]</bitRange>
21412              <access>read-only</access>
21413            </field>
21414          </fields>
21415        </register>
21416        <register>
21417          <name>STAT_HCNT</name>
21418          <description>Current count of the HSCMP counter</description>
21419          <addressOffset>0x8C</addressOffset>
21420          <size>32</size>
21421          <access>read-only</access>
21422          <resetValue>0x0</resetValue>
21423          <resetMask>0xFFFF</resetMask>
21424          <fields>
21425            <field>
21426              <name>CNT</name>
21427              <description>Current value of HSCMP counter</description>
21428              <bitRange>[15:0]</bitRange>
21429              <access>read-only</access>
21430            </field>
21431          </fields>
21432        </register>
21433        <register>
21434          <name>RESULT_VAL1</name>
21435          <description>Result CSD/CSX accumulation counter value 1</description>
21436          <addressOffset>0xD0</addressOffset>
21437          <size>32</size>
21438          <access>read-only</access>
21439          <resetValue>0x0</resetValue>
21440          <resetMask>0xFFFFFF</resetMask>
21441          <fields>
21442            <field>
21443              <name>VALUE</name>
21444              <description>Accumulated counter value for this result. In case of Mutual cap with two counters (CSX = config.mutual_cap &amp; config.csx_dual_cnt) this counter counts when csd_sense is high.</description>
21445              <bitRange>[15:0]</bitRange>
21446              <access>read-only</access>
21447            </field>
21448            <field>
21449              <name>BAD_CONVS</name>
21450              <description>Number of 'bad' conversion for which the CSD comparator did not trigger within the normal time window, either because Vref was not crossed at all, or if the Vref was already crossed before the window started. This counter is reset when the sequencer is started and will saturate at 255 when more than 255 conversions are bad.</description>
21451              <bitRange>[23:16]</bitRange>
21452              <access>read-only</access>
21453            </field>
21454          </fields>
21455        </register>
21456        <register>
21457          <name>RESULT_VAL2</name>
21458          <description>Result CSX accumulation counter value 2</description>
21459          <addressOffset>0xD4</addressOffset>
21460          <size>32</size>
21461          <access>read-only</access>
21462          <resetValue>0x0</resetValue>
21463          <resetMask>0xFFFF</resetMask>
21464          <fields>
21465            <field>
21466              <name>VALUE</name>
21467              <description>Only used in case of Mutual cap with two counters (CSX = config.mutual_cap &amp; config.csx_dual_cnt), this counter counts when csd_sense is low.</description>
21468              <bitRange>[15:0]</bitRange>
21469              <access>read-only</access>
21470            </field>
21471          </fields>
21472        </register>
21473        <register>
21474          <name>ADC_RES</name>
21475          <description>ADC measurement</description>
21476          <addressOffset>0xE0</addressOffset>
21477          <size>32</size>
21478          <access>read-only</access>
21479          <resetValue>0x0</resetValue>
21480          <resetMask>0xC001FFFF</resetMask>
21481          <fields>
21482            <field>
21483              <name>VIN_CNT</name>
21484              <description>Count to source/sink Cref1 + Cref2 from Vin to Vrefhi.</description>
21485              <bitRange>[15:0]</bitRange>
21486              <access>read-only</access>
21487            </field>
21488            <field>
21489              <name>HSCMP_POL</name>
21490              <description>Polarity used for IDACB for this last ADC result, 0= source, 1= sink</description>
21491              <bitRange>[16:16]</bitRange>
21492              <access>read-only</access>
21493            </field>
21494            <field>
21495              <name>ADC_OVERFLOW</name>
21496              <description>This flag is set when the ADC counter overflows. This is an indication to the firmware that the IDACB current level is too low.</description>
21497              <bitRange>[30:30]</bitRange>
21498              <access>read-only</access>
21499            </field>
21500            <field>
21501              <name>ADC_ABORT</name>
21502              <description>This flag is set when the ADC sequencer was aborted before tripping HSCMP.</description>
21503              <bitRange>[31:31]</bitRange>
21504              <access>read-only</access>
21505            </field>
21506          </fields>
21507        </register>
21508        <register>
21509          <name>INTR</name>
21510          <description>CSD Interrupt Request Register</description>
21511          <addressOffset>0xF0</addressOffset>
21512          <size>32</size>
21513          <access>read-write</access>
21514          <resetValue>0x0</resetValue>
21515          <resetMask>0x106</resetMask>
21516          <fields>
21517            <field>
21518              <name>SAMPLE</name>
21519              <description>A normal sample is complete</description>
21520              <bitRange>[1:1]</bitRange>
21521              <access>read-write</access>
21522            </field>
21523            <field>
21524              <name>INIT</name>
21525              <description>Coarse initialization complete or Sample initialization complete (the latter is typically ignored)</description>
21526              <bitRange>[2:2]</bitRange>
21527              <access>read-write</access>
21528            </field>
21529            <field>
21530              <name>ADC_RES</name>
21531              <description>ADC Result ready</description>
21532              <bitRange>[8:8]</bitRange>
21533              <access>read-write</access>
21534            </field>
21535          </fields>
21536        </register>
21537        <register>
21538          <name>INTR_SET</name>
21539          <description>CSD Interrupt set register</description>
21540          <addressOffset>0xF4</addressOffset>
21541          <size>32</size>
21542          <access>read-write</access>
21543          <resetValue>0x0</resetValue>
21544          <resetMask>0x106</resetMask>
21545          <fields>
21546            <field>
21547              <name>SAMPLE</name>
21548              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
21549              <bitRange>[1:1]</bitRange>
21550              <access>read-write</access>
21551            </field>
21552            <field>
21553              <name>INIT</name>
21554              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
21555              <bitRange>[2:2]</bitRange>
21556              <access>read-write</access>
21557            </field>
21558            <field>
21559              <name>ADC_RES</name>
21560              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
21561              <bitRange>[8:8]</bitRange>
21562              <access>read-write</access>
21563            </field>
21564          </fields>
21565        </register>
21566        <register>
21567          <name>INTR_MASK</name>
21568          <description>CSD Interrupt mask register</description>
21569          <addressOffset>0xF8</addressOffset>
21570          <size>32</size>
21571          <access>read-write</access>
21572          <resetValue>0x0</resetValue>
21573          <resetMask>0x106</resetMask>
21574          <fields>
21575            <field>
21576              <name>SAMPLE</name>
21577              <description>Mask bit for corresponding bit in interrupt request register.</description>
21578              <bitRange>[1:1]</bitRange>
21579              <access>read-write</access>
21580            </field>
21581            <field>
21582              <name>INIT</name>
21583              <description>Mask bit for corresponding bit in interrupt request register.</description>
21584              <bitRange>[2:2]</bitRange>
21585              <access>read-write</access>
21586            </field>
21587            <field>
21588              <name>ADC_RES</name>
21589              <description>Mask bit for corresponding bit in interrupt request register.</description>
21590              <bitRange>[8:8]</bitRange>
21591              <access>read-write</access>
21592            </field>
21593          </fields>
21594        </register>
21595        <register>
21596          <name>INTR_MASKED</name>
21597          <description>CSD Interrupt masked register</description>
21598          <addressOffset>0xFC</addressOffset>
21599          <size>32</size>
21600          <access>read-only</access>
21601          <resetValue>0x0</resetValue>
21602          <resetMask>0x106</resetMask>
21603          <fields>
21604            <field>
21605              <name>SAMPLE</name>
21606              <description>Logical and of corresponding request and mask bits.</description>
21607              <bitRange>[1:1]</bitRange>
21608              <access>read-only</access>
21609            </field>
21610            <field>
21611              <name>INIT</name>
21612              <description>Logical and of corresponding request and mask bits.</description>
21613              <bitRange>[2:2]</bitRange>
21614              <access>read-only</access>
21615            </field>
21616            <field>
21617              <name>ADC_RES</name>
21618              <description>Logical and of corresponding request and mask bits.</description>
21619              <bitRange>[8:8]</bitRange>
21620              <access>read-only</access>
21621            </field>
21622          </fields>
21623        </register>
21624        <register>
21625          <name>HSCMP</name>
21626          <description>High Speed Comparator configuration</description>
21627          <addressOffset>0x180</addressOffset>
21628          <size>32</size>
21629          <access>read-write</access>
21630          <resetValue>0x0</resetValue>
21631          <resetMask>0x80000011</resetMask>
21632          <fields>
21633            <field>
21634              <name>HSCMP_EN</name>
21635              <description>High Speed Comparator enable</description>
21636              <bitRange>[0:0]</bitRange>
21637              <access>read-write</access>
21638              <enumeratedValues>
21639                <enumeratedValue>
21640                  <name>OFF</name>
21641                  <description>Disable comparator, output is zero</description>
21642                  <value>0</value>
21643                </enumeratedValue>
21644                <enumeratedValue>
21645                  <name>ON</name>
21646                  <description>On, regular operation. Note that CONFIG.LP_MODE determines the power mode level</description>
21647                  <value>1</value>
21648                </enumeratedValue>
21649              </enumeratedValues>
21650            </field>
21651            <field>
21652              <name>HSCMP_INVERT</name>
21653              <description>Invert the HSCMP output before it is used to control switches and the CSD sequencer. This bit does not affect the ADC sequencer or the STATUS.HSCMP_OUT</description>
21654              <bitRange>[4:4]</bitRange>
21655              <access>read-write</access>
21656            </field>
21657            <field>
21658              <name>AZ_EN</name>
21659              <description>Auto-Zero enable, allow the Sequencer to Auto-Zero this component</description>
21660              <bitRange>[31:31]</bitRange>
21661              <access>read-write</access>
21662            </field>
21663          </fields>
21664        </register>
21665        <register>
21666          <name>AMBUF</name>
21667          <description>Reference Generator configuration</description>
21668          <addressOffset>0x184</addressOffset>
21669          <size>32</size>
21670          <access>read-write</access>
21671          <resetValue>0x0</resetValue>
21672          <resetMask>0x3</resetMask>
21673          <fields>
21674            <field>
21675              <name>PWR_MODE</name>
21676              <description>Amux buffer power level</description>
21677              <bitRange>[1:0]</bitRange>
21678              <access>read-write</access>
21679              <enumeratedValues>
21680                <enumeratedValue>
21681                  <name>OFF</name>
21682                  <description>Disable buffer</description>
21683                  <value>0</value>
21684                </enumeratedValue>
21685                <enumeratedValue>
21686                  <name>NORM</name>
21687                  <description>On, normal or low power level depending on CONFIG.LP_MODE.</description>
21688                  <value>1</value>
21689                </enumeratedValue>
21690                <enumeratedValue>
21691                  <name>HI</name>
21692                  <description>On, high or low power level depending on CONFIG.LP_MODE.</description>
21693                  <value>2</value>
21694                </enumeratedValue>
21695              </enumeratedValues>
21696            </field>
21697          </fields>
21698        </register>
21699        <register>
21700          <name>REFGEN</name>
21701          <description>Reference Generator configuration</description>
21702          <addressOffset>0x188</addressOffset>
21703          <size>32</size>
21704          <access>read-write</access>
21705          <resetValue>0x0</resetValue>
21706          <resetMask>0x9F1F71</resetMask>
21707          <fields>
21708            <field>
21709              <name>REFGEN_EN</name>
21710              <description>Reference Generator Enable</description>
21711              <bitRange>[0:0]</bitRange>
21712              <access>read-write</access>
21713              <enumeratedValues>
21714                <enumeratedValue>
21715                  <name>OFF</name>
21716                  <description>Disable Reference Generator</description>
21717                  <value>0</value>
21718                </enumeratedValue>
21719                <enumeratedValue>
21720                  <name>ON</name>
21721                  <description>On, regular operation. Note that CONFIG.LP_MODE determines the power mode level</description>
21722                  <value>1</value>
21723                </enumeratedValue>
21724              </enumeratedValues>
21725            </field>
21726            <field>
21727              <name>BYPASS</name>
21728              <description>Bypass selected input reference unbuffered to Vrefhi</description>
21729              <bitRange>[4:4]</bitRange>
21730              <access>read-write</access>
21731            </field>
21732            <field>
21733              <name>VDDA_EN</name>
21734              <description>Close Vdda switch to top of resistor string (or Vrefhi?)</description>
21735              <bitRange>[5:5]</bitRange>
21736              <access>read-write</access>
21737            </field>
21738            <field>
21739              <name>RES_EN</name>
21740              <description>Resistor string enable; 0= open switch on top of the resistor string (Vreflo=Vssa)</description>
21741              <bitRange>[6:6]</bitRange>
21742              <access>read-write</access>
21743            </field>
21744            <field>
21745              <name>GAIN</name>
21746              <description>Select resistor string tap for feedback, 0= minimum vout, 31= maximum vout = vrefhi -&gt; gain=1  (only works if the resistor string is enabled; RES_EN=1)</description>
21747              <bitRange>[12:8]</bitRange>
21748              <access>read-write</access>
21749            </field>
21750            <field>
21751              <name>VREFLO_SEL</name>
21752              <description>Select resistor string tap for Vreflo/Vreflo_int, 0= minimum vout, 31= maximum vout = vrefhi (only works if the resistor string is enabled; RES_EN=1)</description>
21753              <bitRange>[20:16]</bitRange>
21754              <access>read-write</access>
21755            </field>
21756            <field>
21757              <name>VREFLO_INT</name>
21758              <description>Ouput the resistor string tap either to Vreflo (0) or Vreflo_int (1).</description>
21759              <bitRange>[23:23]</bitRange>
21760              <access>read-write</access>
21761            </field>
21762          </fields>
21763        </register>
21764        <register>
21765          <name>CSDCMP</name>
21766          <description>CSD Comparator configuration</description>
21767          <addressOffset>0x18C</addressOffset>
21768          <size>32</size>
21769          <access>read-write</access>
21770          <resetValue>0x0</resetValue>
21771          <resetMask>0xB0000331</resetMask>
21772          <fields>
21773            <field>
21774              <name>CSDCMP_EN</name>
21775              <description>CSD Comparator Enable</description>
21776              <bitRange>[0:0]</bitRange>
21777              <access>read-write</access>
21778              <enumeratedValues>
21779                <enumeratedValue>
21780                  <name>OFF</name>
21781                  <description>Disable comparator, output is zero</description>
21782                  <value>0</value>
21783                </enumeratedValue>
21784                <enumeratedValue>
21785                  <name>ON</name>
21786                  <description>On, regular operation. Note that CONFIG.LP_MODE determines the power mode level</description>
21787                  <value>1</value>
21788                </enumeratedValue>
21789              </enumeratedValues>
21790            </field>
21791            <field>
21792              <name>POLARITY_SEL</name>
21793              <description>Select which IDAC polarity to use to detect CSDCMP triggering</description>
21794              <bitRange>[5:4]</bitRange>
21795              <access>read-write</access>
21796              <enumeratedValues>
21797                <enumeratedValue>
21798                  <name>IDACA_POL</name>
21799                  <description>Use idaca_pol (firmware setting with CSX and optionally DSI mixed in) to determine the direction, this is the most common use-case, used for normal CSD and normal CSX</description>
21800                  <value>0</value>
21801                </enumeratedValue>
21802                <enumeratedValue>
21803                  <name>IDACB_POL</name>
21804                  <description>Use idacb_pol (firmware setting with optional DSI mixed in) to determine the direction, this is only used for normal CSD if IDACB is used i.s.o. IDACA (not common)</description>
21805                  <value>1</value>
21806                </enumeratedValue>
21807                <enumeratedValue>
21808                  <name>DUAL_POL</name>
21809                  <description>Use the expression (csd_sense ? idaca_pol : idacb_pol)  to determine the direction, this is only useful for the CSX with DUAL_IDAC use-case</description>
21810                  <value>2</value>
21811                </enumeratedValue>
21812              </enumeratedValues>
21813            </field>
21814            <field>
21815              <name>CMP_PHASE</name>
21816              <description>Select in what phase(s) the comparator is active, typically set to match the BAL_MODE of the used IDAC. Note, this also determines when a bad conversion is detected, namely at the beginning and end of the comparator active phase (also taking into account FILTER_DELAY and non-overlap).</description>
21817              <bitRange>[9:8]</bitRange>
21818              <access>read-write</access>
21819              <enumeratedValues>
21820                <enumeratedValue>
21821                  <name>FULL</name>
21822                  <description>Comparator is active from start of Phi2 and kept active into Phi1. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off)</description>
21823                  <value>0</value>
21824                </enumeratedValue>
21825                <enumeratedValue>
21826                  <name>PHI1</name>
21827                  <description>Comparator is active during Phi1 only. Currently no known use-case.</description>
21828                  <value>1</value>
21829                </enumeratedValue>
21830                <enumeratedValue>
21831                  <name>PHI2</name>
21832                  <description>Comparator is active during Phi2 only. Intended usage: CSD Low EMI.</description>
21833                  <value>2</value>
21834                </enumeratedValue>
21835                <enumeratedValue>
21836                  <name>PHI1_2</name>
21837                  <description>Comparator is activated at the start of both Phi1 and Phi2 (non-overlap should be enabled). Intended usage: CSX, or Full-Wave.</description>
21838                  <value>3</value>
21839                </enumeratedValue>
21840              </enumeratedValues>
21841            </field>
21842            <field>
21843              <name>CMP_MODE</name>
21844              <description>Select which signal to output on dsi_sample_out.</description>
21845              <bitRange>[28:28]</bitRange>
21846              <access>read-write</access>
21847              <enumeratedValues>
21848                <enumeratedValue>
21849                  <name>CSD</name>
21850                  <description>CSD mode: output the filtered sample signal on dsi_sample_out</description>
21851                  <value>0</value>
21852                </enumeratedValue>
21853                <enumeratedValue>
21854                  <name>GP</name>
21855                  <description>General Purpose mode: output the unfiltered sample unfiltered comparator output, either asynchronous or flopped.</description>
21856                  <value>1</value>
21857                </enumeratedValue>
21858              </enumeratedValues>
21859            </field>
21860            <field>
21861              <name>FEEDBACK_MODE</name>
21862              <description>This bit controls whether the output directly from the comparator (csdcmp_out) or the flopped version (csdcmp_out_ff) is used. For CSD operation, the selected signal controls the IDAC(s), in GP mode the signal goes out on dsi_sample_out.</description>
21863              <bitRange>[29:29]</bitRange>
21864              <access>read-write</access>
21865              <enumeratedValues>
21866                <enumeratedValue>
21867                  <name>FLOP</name>
21868                  <description>Use feedback from sampling flip-flop (used in most modes).</description>
21869                  <value>0</value>
21870                </enumeratedValue>
21871                <enumeratedValue>
21872                  <name>COMP</name>
21873                  <description>Use feedback from comparator directly (used in single Cmod mutual cap sensing only)</description>
21874                  <value>1</value>
21875                </enumeratedValue>
21876              </enumeratedValues>
21877            </field>
21878            <field>
21879              <name>AZ_EN</name>
21880              <description>Auto-Zero enable, allow the Sequencer to Auto-Zero this component</description>
21881              <bitRange>[31:31]</bitRange>
21882              <access>read-write</access>
21883            </field>
21884          </fields>
21885        </register>
21886        <register>
21887          <name>SW_RES</name>
21888          <description>Switch Resistance configuration</description>
21889          <addressOffset>0x1F0</addressOffset>
21890          <size>32</size>
21891          <access>read-write</access>
21892          <resetValue>0x0</resetValue>
21893          <resetMask>0xF00FF</resetMask>
21894          <fields>
21895            <field>
21896              <name>RES_HCAV</name>
21897              <description>Select resistance or low EMI (slow ramp) for the HCAV switch</description>
21898              <bitRange>[1:0]</bitRange>
21899              <access>read-write</access>
21900              <enumeratedValues>
21901                <enumeratedValue>
21902                  <name>LOW</name>
21903                  <description>Low</description>
21904                  <value>0</value>
21905                </enumeratedValue>
21906                <enumeratedValue>
21907                  <name>MED</name>
21908                  <description>Medium</description>
21909                  <value>1</value>
21910                </enumeratedValue>
21911                <enumeratedValue>
21912                  <name>HIGH</name>
21913                  <description>High</description>
21914                  <value>2</value>
21915                </enumeratedValue>
21916                <enumeratedValue>
21917                  <name>LOWEMI</name>
21918                  <description>Low EMI (slow ramp: 3 switches closed by fixed delay line)</description>
21919                  <value>3</value>
21920                </enumeratedValue>
21921              </enumeratedValues>
21922            </field>
21923            <field>
21924              <name>RES_HCAG</name>
21925              <description>Select resistance or low EMI for the corresponding switch</description>
21926              <bitRange>[3:2]</bitRange>
21927              <access>read-write</access>
21928            </field>
21929            <field>
21930              <name>RES_HCBV</name>
21931              <description>Select resistance or low EMI for the corresponding switch</description>
21932              <bitRange>[5:4]</bitRange>
21933              <access>read-write</access>
21934            </field>
21935            <field>
21936              <name>RES_HCBG</name>
21937              <description>Select resistance or low EMI for the corresponding switch</description>
21938              <bitRange>[7:6]</bitRange>
21939              <access>read-write</access>
21940            </field>
21941            <field>
21942              <name>RES_F1PM</name>
21943              <description>Select resistance for the corresponding  switch</description>
21944              <bitRange>[17:16]</bitRange>
21945              <access>read-write</access>
21946              <enumeratedValues>
21947                <enumeratedValue>
21948                  <name>LOW</name>
21949                  <description>Low</description>
21950                  <value>0</value>
21951                </enumeratedValue>
21952                <enumeratedValue>
21953                  <name>MED</name>
21954                  <description>Medium</description>
21955                  <value>1</value>
21956                </enumeratedValue>
21957                <enumeratedValue>
21958                  <name>HIGH</name>
21959                  <description>High</description>
21960                  <value>2</value>
21961                </enumeratedValue>
21962                <enumeratedValue>
21963                  <name>RSVD</name>
21964                  <description>N/A</description>
21965                  <value>3</value>
21966                </enumeratedValue>
21967              </enumeratedValues>
21968            </field>
21969            <field>
21970              <name>RES_F2PT</name>
21971              <description>Select resistance for the corresponding  switch</description>
21972              <bitRange>[19:18]</bitRange>
21973              <access>read-write</access>
21974            </field>
21975          </fields>
21976        </register>
21977        <register>
21978          <name>SENSE_PERIOD</name>
21979          <description>Sense clock period</description>
21980          <addressOffset>0x200</addressOffset>
21981          <size>32</size>
21982          <access>read-write</access>
21983          <resetValue>0xC000000</resetValue>
21984          <resetMask>0xFF70FFF</resetMask>
21985          <fields>
21986            <field>
21987              <name>SENSE_DIV</name>
21988              <description>The length-1 of the Sense modulation 'clock' period in clk_csd cycles. For regular CSD one sense clock cycle = one conversion (=phi1+phi2) .
21989Note this is the base divider, clock dithering may change the actual period length.
21990Note that SENSE_DIV must be at least 1 and additionally also allow for one clk_hf of non overlap (if OVERLAP_HI1/2 is set) on both phases, i.e. if clk_csd=clk_hf then SENSE_DIV must be &gt;=3.
21991In addition the FILTER_DELAY needs to be added to the minimum allowed SENSE_DIV value.</description>
21992              <bitRange>[11:0]</bitRange>
21993              <access>read-write</access>
21994            </field>
21995            <field>
21996              <name>LFSR_SIZE</name>
21997              <description>Selects the length of the LFSR which determines the LFSR repeat period. LFSR_BITS LSB of the LFSR are used  for the clock dithering variation on the base period (was PRS in CSDv1). Whenever the LFSR is used (non zero value in this field) the LFSR_CLEAR bit should also be set.</description>
21998              <bitRange>[18:16]</bitRange>
21999              <access>read-write</access>
22000              <enumeratedValues>
22001                <enumeratedValue>
22002                  <name>OFF</name>
22003                  <description>Don't use clock dithering (=spreadspectrum) (LFSR output value is zero)</description>
22004                  <value>0</value>
22005                </enumeratedValue>
22006                <enumeratedValue>
22007                  <name>6B</name>
22008                  <description>6-bit LFSR (G(x)=X^6  +X^4+X^3+    X+1, period= 63)</description>
22009                  <value>1</value>
22010                </enumeratedValue>
22011                <enumeratedValue>
22012                  <name>7B</name>
22013                  <description>7-bit LFSR (G(x)=X^7  +X^4+X^3+X^2+1, period= 127)</description>
22014                  <value>2</value>
22015                </enumeratedValue>
22016                <enumeratedValue>
22017                  <name>9B</name>
22018                  <description>9-bit LFSR (G(x)=X^9  +X^4+X^3+    X+1, period= 511)</description>
22019                  <value>3</value>
22020                </enumeratedValue>
22021                <enumeratedValue>
22022                  <name>10B</name>
22023                  <description>10-bit LFSR (G(x)=X^10+X^4+X^3+    X+1, period= 1023)</description>
22024                  <value>4</value>
22025                </enumeratedValue>
22026                <enumeratedValue>
22027                  <name>8B</name>
22028                  <description>8-bit LFSR (G(x)=X^8+X^4+X^3+X^2+1, period= 255)</description>
22029                  <value>5</value>
22030                </enumeratedValue>
22031                <enumeratedValue>
22032                  <name>12B</name>
22033                  <description>12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1, period= 4095)</description>
22034                  <value>6</value>
22035                </enumeratedValue>
22036              </enumeratedValues>
22037            </field>
22038            <field>
22039              <name>LFSR_SCALE</name>
22040              <description>Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This dithering is disabled when SEL_LSFR_MSB is set.
22041The clock divider to be used = (SENSE_DIV+1) + (SEL_LSFR_MSB ? 0 : (LFSR_OUT&lt;&lt;LFSR_SCALE)).
22042Note that the clock divider including the dithering term must fit in 12 bits, otherwise the result is undefined.</description>
22043              <bitRange>[23:20]</bitRange>
22044              <access>read-write</access>
22045            </field>
22046            <field>
22047              <name>LFSR_CLEAR</name>
22048              <description>When set, forces the LFSR to it's initial state (all ones).  This bit is automatically cleared by hardware after the LFSR is cleared, which is at the next clk_csd positive edge. This bit should be set whenever this register is written and the LFSR is used.
22049Note that the LFSR will also get reset to all ones during the AutoZero_1/2 states.</description>
22050              <bitRange>[24:24]</bitRange>
22051              <access>read-write</access>
22052            </field>
22053            <field>
22054              <name>SEL_LFSR_MSB</name>
22055              <description>Use the MSB of configured LSFR size as csd_sense signal. Intended to be used only with bit 8 or 12-bit LFSR size for CSDv1 backward compatibility (PRS). When this bit is set then clock divider dithering is disabled and SENSE_WIDTH is disabled.</description>
22056              <bitRange>[25:25]</bitRange>
22057              <access>read-write</access>
22058            </field>
22059            <field>
22060              <name>LFSR_BITS</name>
22061              <description>Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period.
22062Caveat make sure that SENSE_DIV &gt; the maximum absolute range (e.g. for 4B  SENSE_DIV &gt; 8), otherwise results are undefined.</description>
22063              <bitRange>[27:26]</bitRange>
22064              <access>read-write</access>
22065              <enumeratedValues>
22066                <enumeratedValue>
22067                  <name>2B</name>
22068                  <description>use 2 bits: range = [-2,1]</description>
22069                  <value>0</value>
22070                </enumeratedValue>
22071                <enumeratedValue>
22072                  <name>3B</name>
22073                  <description>use 3 bits: range = [-4,3]</description>
22074                  <value>1</value>
22075                </enumeratedValue>
22076                <enumeratedValue>
22077                  <name>4B</name>
22078                  <description>use 4 bits: range = [-8,7]</description>
22079                  <value>2</value>
22080                </enumeratedValue>
22081                <enumeratedValue>
22082                  <name>5B</name>
22083                  <description>use 5 bits: range = [-16,15] (default)</description>
22084                  <value>3</value>
22085                </enumeratedValue>
22086              </enumeratedValues>
22087            </field>
22088          </fields>
22089        </register>
22090        <register>
22091          <name>SENSE_DUTY</name>
22092          <description>Sense clock duty cycle</description>
22093          <addressOffset>0x204</addressOffset>
22094          <size>32</size>
22095          <access>read-write</access>
22096          <resetValue>0x0</resetValue>
22097          <resetMask>0xD0FFF</resetMask>
22098          <fields>
22099            <field>
22100              <name>SENSE_WIDTH</name>
22101              <description>Defines the length of the first phase of the sense clock in clk_csd cycles.
22102A value of 0 disables this feature and the duty cycle of csd_sense will be 50 percent, which is equal to SENSE_WIDTH = (SENSE_DIV+1)/2, or when clock dithering is used that becomes [(SENSE_DIV+1) + (LFSR_OUT &lt;&lt; LSFR_SCALE)]/2.  At all times it must be assured that the phases are at least 2 clk_csd cycles (1 for non overlap, if used), if this rule is violated the result is undefined.
22103Note that this feature is not available when SEL_LFSR_MSB (PRS) is selected.</description>
22104              <bitRange>[11:0]</bitRange>
22105              <access>read-write</access>
22106            </field>
22107            <field>
22108              <name>SENSE_POL</name>
22109              <description>Polarity of the sense clock
221100 = start with low phase (typical for regular negative transfer CSD)
221111 = start with high phase</description>
22112              <bitRange>[16:16]</bitRange>
22113              <access>read-write</access>
22114            </field>
22115            <field>
22116              <name>OVERLAP_PHI1</name>
22117              <description>NonOverlap or not for Phi1 (csd_sense=0).
221180 = Non-overlap for Phi1, the Phi1 signal is  csd_sense inverted except that the signal goes low 1 clk_sample before csd_sense goes high. Intended usage: new low EMI CSD/CSX with static GPIO.
221191 = 'Overlap' (= not non-overlap) for Phi1, the Phi1 signal is  csd_sense inverted. Intended usage: legacy CSD with GPIO switching, the GPIO internal circuit ensures that the switches are non-overlapping.</description>
22120              <bitRange>[18:18]</bitRange>
22121              <access>read-write</access>
22122            </field>
22123            <field>
22124              <name>OVERLAP_PHI2</name>
22125              <description>Same as OVERLAP_PHI1 but for Phi2 (csd_sense=1).</description>
22126              <bitRange>[19:19]</bitRange>
22127              <access>read-write</access>
22128            </field>
22129          </fields>
22130        </register>
22131        <register>
22132          <name>SW_HS_P_SEL</name>
22133          <description>HSCMP Pos input switch Waveform selection</description>
22134          <addressOffset>0x280</addressOffset>
22135          <size>32</size>
22136          <access>read-write</access>
22137          <resetValue>0x0</resetValue>
22138          <resetMask>0x11111111</resetMask>
22139          <fields>
22140            <field>
22141              <name>SW_HMPM</name>
22142              <description>Set HMPM switch
221430: static open
221441: static closed</description>
22145              <bitRange>[0:0]</bitRange>
22146              <access>read-write</access>
22147            </field>
22148            <field>
22149              <name>SW_HMPT</name>
22150              <description>Set corresponding switch</description>
22151              <bitRange>[4:4]</bitRange>
22152              <access>read-write</access>
22153            </field>
22154            <field>
22155              <name>SW_HMPS</name>
22156              <description>Set corresponding switch</description>
22157              <bitRange>[8:8]</bitRange>
22158              <access>read-write</access>
22159            </field>
22160            <field>
22161              <name>SW_HMMA</name>
22162              <description>Set corresponding switch</description>
22163              <bitRange>[12:12]</bitRange>
22164              <access>read-write</access>
22165            </field>
22166            <field>
22167              <name>SW_HMMB</name>
22168              <description>Set corresponding switch</description>
22169              <bitRange>[16:16]</bitRange>
22170              <access>read-write</access>
22171            </field>
22172            <field>
22173              <name>SW_HMCA</name>
22174              <description>Set corresponding switch</description>
22175              <bitRange>[20:20]</bitRange>
22176              <access>read-write</access>
22177            </field>
22178            <field>
22179              <name>SW_HMCB</name>
22180              <description>Set corresponding switch</description>
22181              <bitRange>[24:24]</bitRange>
22182              <access>read-write</access>
22183            </field>
22184            <field>
22185              <name>SW_HMRH</name>
22186              <description>Set corresponding switch</description>
22187              <bitRange>[28:28]</bitRange>
22188              <access>read-write</access>
22189            </field>
22190          </fields>
22191        </register>
22192        <register>
22193          <name>SW_HS_N_SEL</name>
22194          <description>HSCMP Neg input switch Waveform selection</description>
22195          <addressOffset>0x284</addressOffset>
22196          <size>32</size>
22197          <access>read-write</access>
22198          <resetValue>0x0</resetValue>
22199          <resetMask>0x77110000</resetMask>
22200          <fields>
22201            <field>
22202              <name>SW_HCCC</name>
22203              <description>Set corresponding switch</description>
22204              <bitRange>[16:16]</bitRange>
22205              <access>read-write</access>
22206            </field>
22207            <field>
22208              <name>SW_HCCD</name>
22209              <description>Set corresponding switch</description>
22210              <bitRange>[20:20]</bitRange>
22211              <access>read-write</access>
22212            </field>
22213            <field>
22214              <name>SW_HCRH</name>
22215              <description>Select waveform for corresponding switch</description>
22216              <bitRange>[26:24]</bitRange>
22217              <access>read-write</access>
22218            </field>
22219            <field>
22220              <name>SW_HCRL</name>
22221              <description>Select waveform for corresponding switch</description>
22222              <bitRange>[30:28]</bitRange>
22223              <access>read-write</access>
22224            </field>
22225          </fields>
22226        </register>
22227        <register>
22228          <name>SW_SHIELD_SEL</name>
22229          <description>Shielding switches Waveform selection</description>
22230          <addressOffset>0x288</addressOffset>
22231          <size>32</size>
22232          <access>read-write</access>
22233          <resetValue>0x0</resetValue>
22234          <resetMask>0x117777</resetMask>
22235          <fields>
22236            <field>
22237              <name>SW_HCAV</name>
22238              <description>N/A</description>
22239              <bitRange>[2:0]</bitRange>
22240              <access>read-write</access>
22241            </field>
22242            <field>
22243              <name>SW_HCAG</name>
22244              <description>Select waveform for corresponding switch</description>
22245              <bitRange>[6:4]</bitRange>
22246              <access>read-write</access>
22247            </field>
22248            <field>
22249              <name>SW_HCBV</name>
22250              <description>N/A</description>
22251              <bitRange>[10:8]</bitRange>
22252              <access>read-write</access>
22253            </field>
22254            <field>
22255              <name>SW_HCBG</name>
22256              <description>Select waveform for corresponding switch, using csd_shield as base</description>
22257              <bitRange>[14:12]</bitRange>
22258              <access>read-write</access>
22259            </field>
22260            <field>
22261              <name>SW_HCCV</name>
22262              <description>Set corresponding switch</description>
22263              <bitRange>[16:16]</bitRange>
22264              <access>read-write</access>
22265            </field>
22266            <field>
22267              <name>SW_HCCG</name>
22268              <description>Set corresponding switch
22269If the ADC is enabled then this switch is directly controlled by the ADC sequencer.</description>
22270              <bitRange>[20:20]</bitRange>
22271              <access>read-write</access>
22272            </field>
22273          </fields>
22274        </register>
22275        <register>
22276          <name>SW_AMUXBUF_SEL</name>
22277          <description>Amuxbuffer switches Waveform selection</description>
22278          <addressOffset>0x290</addressOffset>
22279          <size>32</size>
22280          <access>read-write</access>
22281          <resetValue>0x0</resetValue>
22282          <resetMask>0x11171110</resetMask>
22283          <fields>
22284            <field>
22285              <name>SW_IRBY</name>
22286              <description>Set corresponding switch</description>
22287              <bitRange>[4:4]</bitRange>
22288              <access>read-write</access>
22289            </field>
22290            <field>
22291              <name>SW_IRLB</name>
22292              <description>Set corresponding switch</description>
22293              <bitRange>[8:8]</bitRange>
22294              <access>read-write</access>
22295            </field>
22296            <field>
22297              <name>SW_ICA</name>
22298              <description>Set corresponding switch</description>
22299              <bitRange>[12:12]</bitRange>
22300              <access>read-write</access>
22301            </field>
22302            <field>
22303              <name>SW_ICB</name>
22304              <description>Select waveform for corresponding switch</description>
22305              <bitRange>[18:16]</bitRange>
22306              <access>read-write</access>
22307            </field>
22308            <field>
22309              <name>SW_IRLI</name>
22310              <description>Set corresponding switch</description>
22311              <bitRange>[20:20]</bitRange>
22312              <access>read-write</access>
22313            </field>
22314            <field>
22315              <name>SW_IRH</name>
22316              <description>Set corresponding switch</description>
22317              <bitRange>[24:24]</bitRange>
22318              <access>read-write</access>
22319            </field>
22320            <field>
22321              <name>SW_IRL</name>
22322              <description>Set corresponding switch</description>
22323              <bitRange>[28:28]</bitRange>
22324              <access>read-write</access>
22325            </field>
22326          </fields>
22327        </register>
22328        <register>
22329          <name>SW_BYP_SEL</name>
22330          <description>AMUXBUS bypass switches Waveform selection</description>
22331          <addressOffset>0x294</addressOffset>
22332          <size>32</size>
22333          <access>read-write</access>
22334          <resetValue>0x0</resetValue>
22335          <resetMask>0x111000</resetMask>
22336          <fields>
22337            <field>
22338              <name>SW_BYA</name>
22339              <description>Set corresponding switch</description>
22340              <bitRange>[12:12]</bitRange>
22341              <access>read-write</access>
22342            </field>
22343            <field>
22344              <name>SW_BYB</name>
22345              <description>Set corresponding switch</description>
22346              <bitRange>[16:16]</bitRange>
22347              <access>read-write</access>
22348            </field>
22349            <field>
22350              <name>SW_CBCC</name>
22351              <description>Set corresponding switch
22352If the ADC is enabled then this switch is directly controlled by the ADC sequencer.</description>
22353              <bitRange>[20:20]</bitRange>
22354              <access>read-write</access>
22355            </field>
22356          </fields>
22357        </register>
22358        <register>
22359          <name>SW_CMP_P_SEL</name>
22360          <description>CSDCMP Pos Switch Waveform selection</description>
22361          <addressOffset>0x2A0</addressOffset>
22362          <size>32</size>
22363          <access>read-write</access>
22364          <resetValue>0x0</resetValue>
22365          <resetMask>0x1111777</resetMask>
22366          <fields>
22367            <field>
22368              <name>SW_SFPM</name>
22369              <description>Select waveform for corresponding switch</description>
22370              <bitRange>[2:0]</bitRange>
22371              <access>read-write</access>
22372            </field>
22373            <field>
22374              <name>SW_SFPT</name>
22375              <description>Select waveform for corresponding switch</description>
22376              <bitRange>[6:4]</bitRange>
22377              <access>read-write</access>
22378            </field>
22379            <field>
22380              <name>SW_SFPS</name>
22381              <description>Select waveform for corresponding switch</description>
22382              <bitRange>[10:8]</bitRange>
22383              <access>read-write</access>
22384            </field>
22385            <field>
22386              <name>SW_SFMA</name>
22387              <description>Set corresponding switch</description>
22388              <bitRange>[12:12]</bitRange>
22389              <access>read-write</access>
22390            </field>
22391            <field>
22392              <name>SW_SFMB</name>
22393              <description>Set corresponding switch</description>
22394              <bitRange>[16:16]</bitRange>
22395              <access>read-write</access>
22396            </field>
22397            <field>
22398              <name>SW_SFCA</name>
22399              <description>Set corresponding switch</description>
22400              <bitRange>[20:20]</bitRange>
22401              <access>read-write</access>
22402            </field>
22403            <field>
22404              <name>SW_SFCB</name>
22405              <description>Set corresponding switch</description>
22406              <bitRange>[24:24]</bitRange>
22407              <access>read-write</access>
22408            </field>
22409          </fields>
22410        </register>
22411        <register>
22412          <name>SW_CMP_N_SEL</name>
22413          <description>CSDCMP Neg Switch Waveform selection</description>
22414          <addressOffset>0x2A4</addressOffset>
22415          <size>32</size>
22416          <access>read-write</access>
22417          <resetValue>0x0</resetValue>
22418          <resetMask>0x77000000</resetMask>
22419          <fields>
22420            <field>
22421              <name>SW_SCRH</name>
22422              <description>Select waveform for corresponding switch</description>
22423              <bitRange>[26:24]</bitRange>
22424              <access>read-write</access>
22425            </field>
22426            <field>
22427              <name>SW_SCRL</name>
22428              <description>Select waveform for corresponding switch</description>
22429              <bitRange>[30:28]</bitRange>
22430              <access>read-write</access>
22431            </field>
22432          </fields>
22433        </register>
22434        <register>
22435          <name>SW_REFGEN_SEL</name>
22436          <description>Reference Generator Switch Waveform selection</description>
22437          <addressOffset>0x2A8</addressOffset>
22438          <size>32</size>
22439          <access>read-write</access>
22440          <resetValue>0x0</resetValue>
22441          <resetMask>0x11110011</resetMask>
22442          <fields>
22443            <field>
22444              <name>SW_IAIB</name>
22445              <description>Set corresponding switch</description>
22446              <bitRange>[0:0]</bitRange>
22447              <access>read-write</access>
22448            </field>
22449            <field>
22450              <name>SW_IBCB</name>
22451              <description>Set corresponding switch</description>
22452              <bitRange>[4:4]</bitRange>
22453              <access>read-write</access>
22454            </field>
22455            <field>
22456              <name>SW_SGMB</name>
22457              <description>Set corresponding switch</description>
22458              <bitRange>[16:16]</bitRange>
22459              <access>read-write</access>
22460            </field>
22461            <field>
22462              <name>SW_SGRP</name>
22463              <description>Set corresponding switch</description>
22464              <bitRange>[20:20]</bitRange>
22465              <access>read-write</access>
22466            </field>
22467            <field>
22468              <name>SW_SGRE</name>
22469              <description>Set corresponding switch</description>
22470              <bitRange>[24:24]</bitRange>
22471              <access>read-write</access>
22472            </field>
22473            <field>
22474              <name>SW_SGR</name>
22475              <description>Set corresponding switch</description>
22476              <bitRange>[28:28]</bitRange>
22477              <access>read-write</access>
22478            </field>
22479          </fields>
22480        </register>
22481        <register>
22482          <name>SW_FW_MOD_SEL</name>
22483          <description>Full Wave Cmod Switch Waveform selection</description>
22484          <addressOffset>0x2B0</addressOffset>
22485          <size>32</size>
22486          <access>read-write</access>
22487          <resetValue>0x0</resetValue>
22488          <resetMask>0x11170701</resetMask>
22489          <fields>
22490            <field>
22491              <name>SW_F1PM</name>
22492              <description>Set corresponding switch</description>
22493              <bitRange>[0:0]</bitRange>
22494              <access>read-write</access>
22495            </field>
22496            <field>
22497              <name>SW_F1MA</name>
22498              <description>Select waveform for corresponding switch</description>
22499              <bitRange>[10:8]</bitRange>
22500              <access>read-write</access>
22501            </field>
22502            <field>
22503              <name>SW_F1CA</name>
22504              <description>Select waveform for corresponding switch</description>
22505              <bitRange>[18:16]</bitRange>
22506              <access>read-write</access>
22507            </field>
22508            <field>
22509              <name>SW_C1CC</name>
22510              <description>Set corresponding switch</description>
22511              <bitRange>[20:20]</bitRange>
22512              <access>read-write</access>
22513            </field>
22514            <field>
22515              <name>SW_C1CD</name>
22516              <description>Set corresponding switch</description>
22517              <bitRange>[24:24]</bitRange>
22518              <access>read-write</access>
22519            </field>
22520            <field>
22521              <name>SW_C1F1</name>
22522              <description>Set corresponding switch</description>
22523              <bitRange>[28:28]</bitRange>
22524              <access>read-write</access>
22525            </field>
22526          </fields>
22527        </register>
22528        <register>
22529          <name>SW_FW_TANK_SEL</name>
22530          <description>Full Wave Csh_tank Switch Waveform selection</description>
22531          <addressOffset>0x2B4</addressOffset>
22532          <size>32</size>
22533          <access>read-write</access>
22534          <resetValue>0x0</resetValue>
22535          <resetMask>0x11177710</resetMask>
22536          <fields>
22537            <field>
22538              <name>SW_F2PT</name>
22539              <description>Set corresponding switch</description>
22540              <bitRange>[4:4]</bitRange>
22541              <access>read-write</access>
22542            </field>
22543            <field>
22544              <name>SW_F2MA</name>
22545              <description>Select waveform for corresponding switch</description>
22546              <bitRange>[10:8]</bitRange>
22547              <access>read-write</access>
22548            </field>
22549            <field>
22550              <name>SW_F2CA</name>
22551              <description>Select waveform for corresponding switch</description>
22552              <bitRange>[14:12]</bitRange>
22553              <access>read-write</access>
22554            </field>
22555            <field>
22556              <name>SW_F2CB</name>
22557              <description>Select waveform for corresponding switch</description>
22558              <bitRange>[18:16]</bitRange>
22559              <access>read-write</access>
22560            </field>
22561            <field>
22562              <name>SW_C2CC</name>
22563              <description>Set corresponding switch</description>
22564              <bitRange>[20:20]</bitRange>
22565              <access>read-write</access>
22566            </field>
22567            <field>
22568              <name>SW_C2CD</name>
22569              <description>Set corresponding switch</description>
22570              <bitRange>[24:24]</bitRange>
22571              <access>read-write</access>
22572            </field>
22573            <field>
22574              <name>SW_C2F2</name>
22575              <description>Set corresponding switch</description>
22576              <bitRange>[28:28]</bitRange>
22577              <access>read-write</access>
22578            </field>
22579          </fields>
22580        </register>
22581        <register>
22582          <name>SW_DSI_SEL</name>
22583          <description>DSI output switch control Waveform selection</description>
22584          <addressOffset>0x2C0</addressOffset>
22585          <size>32</size>
22586          <access>read-write</access>
22587          <resetValue>0x0</resetValue>
22588          <resetMask>0xFF</resetMask>
22589          <fields>
22590            <field>
22591              <name>DSI_CSH_TANK</name>
22592              <description>Select waveform for dsi_csh_tank output signal
225930: static open
225941: static closed
225952: phi1
225963: phi2
225974: phi1 &amp; HSCMP
225985: phi2 &amp; HSCMP
225996: HSCMP                       // ignores phi1/2
226007: !sense                        // = phi1 but ignores OVERLAP_PHI1
22601
226028: phi1_delay              // phi1 delayed with shield delay
226039: phi2_delay              // phi2 delayed with shield delay
22604
2260510: !phi1
2260611: !phi2
2260712: !(phi1 &amp; HSCMP)
2260813: !(phi2 &amp; HSCMP)
2260914: !HSCMP                   // ignores phi1/2
2261015: sense                       // = phi2 but ignores OVERLAP_PHI2</description>
22611              <bitRange>[3:0]</bitRange>
22612              <access>read-write</access>
22613            </field>
22614            <field>
22615              <name>DSI_CMOD</name>
22616              <description>Select waveform for dsi_cmod output signal</description>
22617              <bitRange>[7:4]</bitRange>
22618              <access>read-write</access>
22619            </field>
22620          </fields>
22621        </register>
22622        <register>
22623          <name>IO_SEL</name>
22624          <description>IO output control Waveform selection</description>
22625          <addressOffset>0x2D0</addressOffset>
22626          <size>32</size>
22627          <access>read-write</access>
22628          <resetValue>0x0</resetValue>
22629          <resetMask>0xFFFF0FF</resetMask>
22630          <fields>
22631            <field>
22632              <name>CSD_TX_OUT</name>
22633              <description>Select waveform for csd_tx_out output signal</description>
22634              <bitRange>[3:0]</bitRange>
22635              <access>read-write</access>
22636            </field>
22637            <field>
22638              <name>CSD_TX_OUT_EN</name>
22639              <description>Select waveform for csd_tx_out_en output signal</description>
22640              <bitRange>[7:4]</bitRange>
22641              <access>read-write</access>
22642            </field>
22643            <field>
22644              <name>CSD_TX_AMUXB_EN</name>
22645              <description>Select waveform for csd_tx_amuxb_en output signal</description>
22646              <bitRange>[15:12]</bitRange>
22647              <access>read-write</access>
22648            </field>
22649            <field>
22650              <name>CSD_TX_N_OUT</name>
22651              <description>Select waveform for csd_tx_n_out output signal</description>
22652              <bitRange>[19:16]</bitRange>
22653              <access>read-write</access>
22654            </field>
22655            <field>
22656              <name>CSD_TX_N_OUT_EN</name>
22657              <description>Select waveform for csd_tx_n_out_en output signal</description>
22658              <bitRange>[23:20]</bitRange>
22659              <access>read-write</access>
22660            </field>
22661            <field>
22662              <name>CSD_TX_N_AMUXA_EN</name>
22663              <description>Select waveform for csd_tx_n_amuxa_en output signal</description>
22664              <bitRange>[27:24]</bitRange>
22665              <access>read-write</access>
22666            </field>
22667          </fields>
22668        </register>
22669        <register>
22670          <name>SEQ_TIME</name>
22671          <description>Sequencer Timing</description>
22672          <addressOffset>0x300</addressOffset>
22673          <size>32</size>
22674          <access>read-write</access>
22675          <resetValue>0x0</resetValue>
22676          <resetMask>0xFF</resetMask>
22677          <fields>
22678            <field>
22679              <name>AZ_TIME</name>
22680              <description>Define Auto-Zero time in csd_sense cycles -1.</description>
22681              <bitRange>[7:0]</bitRange>
22682              <access>read-write</access>
22683            </field>
22684          </fields>
22685        </register>
22686        <register>
22687          <name>SEQ_INIT_CNT</name>
22688          <description>Sequencer Initial conversion and sample counts</description>
22689          <addressOffset>0x310</addressOffset>
22690          <size>32</size>
22691          <access>read-write</access>
22692          <resetValue>0x0</resetValue>
22693          <resetMask>0xFFFF</resetMask>
22694          <fields>
22695            <field>
22696              <name>CONV_CNT</name>
22697              <description>Number of conversion per Initialization sample, if set to 0 the Sample_init state will be skipped.</description>
22698              <bitRange>[15:0]</bitRange>
22699              <access>read-write</access>
22700            </field>
22701          </fields>
22702        </register>
22703        <register>
22704          <name>SEQ_NORM_CNT</name>
22705          <description>Sequencer Normal conversion and sample counts</description>
22706          <addressOffset>0x314</addressOffset>
22707          <size>32</size>
22708          <access>read-write</access>
22709          <resetValue>0x0</resetValue>
22710          <resetMask>0xFFFF</resetMask>
22711          <fields>
22712            <field>
22713              <name>CONV_CNT</name>
22714              <description>Number of conversion per sample, if set to 0 the Sample_norm state will be skipped.
22715Sample window size = SEQ_NORM_CNT.CONV_CNT * (SENSE_PERIOD.SENSE_DIV+1).
22716Note for CSDv1 Sample window size = PERIOD</description>
22717              <bitRange>[15:0]</bitRange>
22718              <access>read-write</access>
22719            </field>
22720          </fields>
22721        </register>
22722        <register>
22723          <name>ADC_CTL</name>
22724          <description>ADC Control</description>
22725          <addressOffset>0x320</addressOffset>
22726          <size>32</size>
22727          <access>read-write</access>
22728          <resetValue>0x0</resetValue>
22729          <resetMask>0x300FF</resetMask>
22730          <fields>
22731            <field>
22732              <name>ADC_TIME</name>
22733              <description>ADC timing -1 in csd_sense clock cycles (actual time is ADC_TIME+1 cycles), either used to discharge Cref1&amp;2, or as the aperture to capture the input voltage on Cref1&amp;2</description>
22734              <bitRange>[7:0]</bitRange>
22735              <access>read-write</access>
22736            </field>
22737            <field>
22738              <name>ADC_MODE</name>
22739              <description>Enable ADC measurement. When enabled the ADC sequencer will be started when the main sequencer goes to the SAMPLE_NORM state</description>
22740              <bitRange>[17:16]</bitRange>
22741              <access>read-write</access>
22742              <enumeratedValues>
22743                <enumeratedValue>
22744                  <name>OFF</name>
22745                  <description>No ADC measurement</description>
22746                  <value>0</value>
22747                </enumeratedValue>
22748                <enumeratedValue>
22749                  <name>VREF_CNT</name>
22750                  <description>Count time A to bring Cref1 + Cref2 up from Vssa to Vrefhi with IDACB</description>
22751                  <value>1</value>
22752                </enumeratedValue>
22753                <enumeratedValue>
22754                  <name>VREF_BY2_CNT</name>
22755                  <description>Count time B to bring Cref1 + Cref2 back up to Vrefhi with IDACB (after bringing them down for time A/2 cycles with IDACB sinking)</description>
22756                  <value>2</value>
22757                </enumeratedValue>
22758                <enumeratedValue>
22759                  <name>VIN_CNT</name>
22760                  <description>Determine HSCMP polarity and count time C to source/sink Cref1 + Cref2 from Vin to Vrefhi.</description>
22761                  <value>3</value>
22762                </enumeratedValue>
22763              </enumeratedValues>
22764            </field>
22765          </fields>
22766        </register>
22767        <register>
22768          <name>SEQ_START</name>
22769          <description>Sequencer start</description>
22770          <addressOffset>0x340</addressOffset>
22771          <size>32</size>
22772          <access>read-write</access>
22773          <resetValue>0x0</resetValue>
22774          <resetMask>0x31B</resetMask>
22775          <fields>
22776            <field>
22777              <name>START</name>
22778              <description>Start the CSD sequencer. The sequencer will clear this bit when it is done. Depending on the mode the sequencer is done when a sample has been accumulated, when the high speed comparator trips or if the sequencer is aborted. When the ADC is enabled the ADC sequencer will start when the CSD sequencer reaches the Sample_norm state (only with the regular CSD scan mode).</description>
22779              <bitRange>[0:0]</bitRange>
22780              <access>read-write</access>
22781            </field>
22782            <field>
22783              <name>SEQ_MODE</name>
22784              <description>0 = regular CSD scan + optional ADC
227851 = coarse initialization, the Sequencer will go to the INIT_COARSE state.</description>
22786              <bitRange>[1:1]</bitRange>
22787              <access>read-write</access>
22788            </field>
22789            <field>
22790              <name>ABORT</name>
22791              <description>When a 1 is written the CSD and ADC sequencers will be aborted (if they are running) and the START bit will be cleared. This bit always read as 0.</description>
22792              <bitRange>[3:3]</bitRange>
22793              <access>read-write</access>
22794            </field>
22795            <field>
22796              <name>DSI_START_EN</name>
22797              <description>When this bit is set a positive edge on dsi_start will start the CSD sequencer and if enabled also the ADC sequencer.</description>
22798              <bitRange>[4:4]</bitRange>
22799              <access>read-write</access>
22800            </field>
22801            <field>
22802              <name>AZ0_SKIP</name>
22803              <description>When set the AutoZero_0 state will be skipped</description>
22804              <bitRange>[8:8]</bitRange>
22805              <access>read-write</access>
22806            </field>
22807            <field>
22808              <name>AZ1_SKIP</name>
22809              <description>When set the AutoZero_1 state will be skipped</description>
22810              <bitRange>[9:9]</bitRange>
22811              <access>read-write</access>
22812            </field>
22813          </fields>
22814        </register>
22815        <register>
22816          <name>IDACA</name>
22817          <description>IDACA Configuration</description>
22818          <addressOffset>0x400</addressOffset>
22819          <size>32</size>
22820          <access>read-write</access>
22821          <resetValue>0x0</resetValue>
22822          <resetMask>0x3EF0FFF</resetMask>
22823          <fields>
22824            <field>
22825              <name>VAL</name>
22826              <description>Current value setting for this IDAC (7 bits).</description>
22827              <bitRange>[6:0]</bitRange>
22828              <access>read-write</access>
22829            </field>
22830            <field>
22831              <name>POL_DYN</name>
22832              <description>Polarity is dynamic, this bit does not influence the logic in the SoftIP, it only goes to the HardIP.</description>
22833              <bitRange>[7:7]</bitRange>
22834              <access>read-write</access>
22835              <enumeratedValues>
22836                <enumeratedValue>
22837                  <name>STATIC</name>
22838                  <description>Static polarity. Polarity is expected to be stable, so to save power this avoids the shunting of the unused polarity, at the expense of response time.</description>
22839                  <value>0</value>
22840                </enumeratedValue>
22841                <enumeratedValue>
22842                  <name>DYNAMIC</name>
22843                  <description>Dynamic polarity. Polarity is expected to change frequently (e.g. invert after every csd_sense phase), so to improve response time this keeps the shunt of the unused polarity on at the expense of power.</description>
22844                  <value>1</value>
22845                </enumeratedValue>
22846              </enumeratedValues>
22847            </field>
22848            <field>
22849              <name>POLARITY</name>
22850              <description>Selects the polarity of the IDAC (sensing operation). Normally the actual polarity depends on this bit, optionally mixed with DSI (see DSI_CTRL_EN) and if LEG1_MODE==CSD also mixed with the CSD configuration and operation. However in mutual cap mode with one IDAC (config.mutual_cap=1 &amp; config.csx_dual_idac=0) the polarity of the IDAC is controlled by csd_sense.</description>
22851              <bitRange>[9:8]</bitRange>
22852              <access>read-write</access>
22853              <enumeratedValues>
22854                <enumeratedValue>
22855                  <name>VSSA_SRC</name>
22856                  <description>Normal: switch between Vssa and Cmod.  For non-CSD application, IDAC will source current.</description>
22857                  <value>0</value>
22858                </enumeratedValue>
22859                <enumeratedValue>
22860                  <name>VDDA_SNK</name>
22861                  <description>Inverted: switch between Vdda and Cmod. For non-CSD application, IDAC will sink current.</description>
22862                  <value>1</value>
22863                </enumeratedValue>
22864                <enumeratedValue>
22865                  <name>SENSE</name>
22866                  <description>The polarity of the IDAC will follow the csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC.</description>
22867                  <value>2</value>
22868                </enumeratedValue>
22869                <enumeratedValue>
22870                  <name>SENSE_INV</name>
22871                  <description>The polarity of the IDAC will follow the inverted csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC.</description>
22872                  <value>3</value>
22873                </enumeratedValue>
22874              </enumeratedValues>
22875            </field>
22876            <field>
22877              <name>BAL_MODE</name>
22878              <description>Balancing mode: only applies to legs configured as CSD.</description>
22879              <bitRange>[11:10]</bitRange>
22880              <access>read-write</access>
22881              <enumeratedValues>
22882                <enumeratedValue>
22883                  <name>FULL</name>
22884                  <description>enabled from start of Phi2 until disabled by CSDCMP. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off)</description>
22885                  <value>0</value>
22886                </enumeratedValue>
22887                <enumeratedValue>
22888                  <name>PHI1</name>
22889                  <description>enabled from start of Phi1 and disabled by CSDCMP or at end of Phi1. Enables dual IDAC CSX or Full-Wave, one for sourcing and the other for sinking.</description>
22890                  <value>1</value>
22891                </enumeratedValue>
22892                <enumeratedValue>
22893                  <name>PHI2</name>
22894                  <description>enabled from start of Phi2 and disabled by CSDCMP or at end of Phi2. Intended usage: CSD Low EMI or  dual IDAC CSX or Full-Wave.</description>
22895                  <value>2</value>
22896                </enumeratedValue>
22897                <enumeratedValue>
22898                  <name>PHI1_2</name>
22899                  <description>enabled from start of both Phi1 and Phi2 and disabled by CSDCMP or at end of Phi1 or Phi2 (if non-overlap enabled). Intended usage: single IDAC CSX, or Full-Wave.</description>
22900                  <value>3</value>
22901                </enumeratedValue>
22902              </enumeratedValues>
22903            </field>
22904            <field>
22905              <name>LEG1_MODE</name>
22906              <description>Controls the usage mode of LEG1 and the Polarity bit</description>
22907              <bitRange>[17:16]</bitRange>
22908              <access>read-write</access>
22909              <enumeratedValues>
22910                <enumeratedValue>
22911                  <name>GP_STATIC</name>
22912                  <description>General Purpose static mode: LEG1 and POLARITY are controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer.</description>
22913                  <value>0</value>
22914                </enumeratedValue>
22915                <enumeratedValue>
22916                  <name>GP</name>
22917                  <description>General Purpose dynamic mode: LEG1 and POLARITY are controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled.</description>
22918                  <value>1</value>
22919                </enumeratedValue>
22920                <enumeratedValue>
22921                  <name>CSD_STATIC</name>
22922                  <description>CSD static mode: LEG1 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG1 is controlled by LEG1_EN, csd_sense and the CSD configuration. Polarity is controlled by the CSD configuration and operation. In addition leg1 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer.</description>
22923                  <value>2</value>
22924                </enumeratedValue>
22925                <enumeratedValue>
22926                  <name>CSD</name>
22927                  <description>CSD dynamic mode: LEG1 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In thoses states LEG1 is controlled by LEG1_EN, the CSD configuration, csd_sense and the flopped CSDCMP output (CSDCMP_OUT_FF). Polarity is controlled by the CSD configuration and operation. In addition leg1 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled.</description>
22928                  <value>3</value>
22929                </enumeratedValue>
22930              </enumeratedValues>
22931            </field>
22932            <field>
22933              <name>LEG2_MODE</name>
22934              <description>Controls the usage mode of LEG2</description>
22935              <bitRange>[19:18]</bitRange>
22936              <access>read-write</access>
22937              <enumeratedValues>
22938                <enumeratedValue>
22939                  <name>GP_STATIC</name>
22940                  <description>General Purpose static mode: LEG2 is controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN).  No shunting is used, this saves power when off but also any on/off switching will take longer.</description>
22941                  <value>0</value>
22942                </enumeratedValue>
22943                <enumeratedValue>
22944                  <name>GP</name>
22945                  <description>General Purpose dynamic mode: LEG2 is controlled by MMIO and optionally mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled.</description>
22946                  <value>1</value>
22947                </enumeratedValue>
22948                <enumeratedValue>
22949                  <name>CSD_STATIC</name>
22950                  <description>CSD static mode: LEG2 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG2 is controlled by LEG2_EN, csd_sense and the CSD configuration. Polarity is controlled by the CSD configuration and operation. In addition leg2 enable and polarity can optionally be mixed with DSI (see DSI_CTRL_EN). No shunting is used, this saves power when off but also any on/off switching will take longer.</description>
22951                  <value>2</value>
22952                </enumeratedValue>
22953                <enumeratedValue>
22954                  <name>CSD</name>
22955                  <description>CSD dynamic mode: LEG2 can only be on when the CSD Sequencer is in the Sample_init or Sample_norm state. In those states LEG2 is controlled by LEG2_EN, the CSD configuration, csd_sense and the flopped CSDCMP output (CSDCMP_OUT_FF). In addition leg2 enable can optionally be mixed with DSI (see DSI_CTRL_EN). Shunting is used, so on/off switching is faster, but power is wasted when the leg is disabled.</description>
22956                  <value>3</value>
22957                </enumeratedValue>
22958              </enumeratedValues>
22959            </field>
22960            <field>
22961              <name>DSI_CTRL_EN</name>
22962              <description>Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled).
229630: no DSI control
22964     IDACA_POLARITY = IDACA.POLARITY
22965     IDACA_LEG1_EN =  IDACA.LEG1_EN
22966     IDACA_LEG2_EN = IDACA.LEG2_EN
229671: Mix MMIO with DSI control
22968     IDACA_POLARITY = IDACA.POLARITY EXOR dsi_idaca_pol
22969     IDACA_LEG1_EN =  IDACA.LEG1_EN AND dsi_idaca_leg1_en
22970     IDACA_LEG2_EN = IDACA.LEG2_EN AND dsi_idaca_leg2_en</description>
22971              <bitRange>[21:21]</bitRange>
22972              <access>read-write</access>
22973            </field>
22974            <field>
22975              <name>RANGE</name>
22976              <description>IDAC multiplier</description>
22977              <bitRange>[23:22]</bitRange>
22978              <access>read-write</access>
22979              <enumeratedValues>
22980                <enumeratedValue>
22981                  <name>IDAC_LO</name>
22982                  <description>1 LSB =   37.5 nA</description>
22983                  <value>0</value>
22984                </enumeratedValue>
22985                <enumeratedValue>
22986                  <name>IDAC_MED</name>
22987                  <description>1 LSB =  300 nA</description>
22988                  <value>1</value>
22989                </enumeratedValue>
22990                <enumeratedValue>
22991                  <name>IDAC_HI</name>
22992                  <description>1 LSB = 2400 nA</description>
22993                  <value>2</value>
22994                </enumeratedValue>
22995              </enumeratedValues>
22996            </field>
22997            <field>
22998              <name>LEG1_EN</name>
22999              <description>output enable for leg 1 to CSDBUSA</description>
23000              <bitRange>[24:24]</bitRange>
23001              <access>read-write</access>
23002            </field>
23003            <field>
23004              <name>LEG2_EN</name>
23005              <description>output enable for leg 2 to CSDBUSA</description>
23006              <bitRange>[25:25]</bitRange>
23007              <access>read-write</access>
23008            </field>
23009          </fields>
23010        </register>
23011        <register>
23012          <name>IDACB</name>
23013          <description>IDACB Configuration</description>
23014          <addressOffset>0x500</addressOffset>
23015          <size>32</size>
23016          <access>read-write</access>
23017          <resetValue>0x0</resetValue>
23018          <resetMask>0x7EF0FFF</resetMask>
23019          <fields>
23020            <field>
23021              <name>VAL</name>
23022              <description>Current value setting for this IDAC (7 bits).</description>
23023              <bitRange>[6:0]</bitRange>
23024              <access>read-write</access>
23025            </field>
23026            <field>
23027              <name>POL_DYN</name>
23028              <description>Polarity is dynamic, this bit does not influence the logic in the SoftIP, it only goes to the HardIP.</description>
23029              <bitRange>[7:7]</bitRange>
23030              <access>read-write</access>
23031              <enumeratedValues>
23032                <enumeratedValue>
23033                  <name>STATIC</name>
23034                  <description>Static polarity. Polarity is expected to be stable, so to save power this avoids the shunting of the unused polarity, at the expense of response time.</description>
23035                  <value>0</value>
23036                </enumeratedValue>
23037                <enumeratedValue>
23038                  <name>DYNAMIC</name>
23039                  <description>Dynamic polarity. Polarity is expected to change frequently (e.g. invert after every csd_sense phase), so to improve response time this keeps the shunt of the unused polarity on at the expense of power.</description>
23040                  <value>1</value>
23041                </enumeratedValue>
23042              </enumeratedValues>
23043            </field>
23044            <field>
23045              <name>POLARITY</name>
23046              <description>Selects the polarity of the IDAC (sensing operation). Normally the actual polarity depends on this bit, optionally mixed with DSI (see DSI_CTRL_EN) and if LEG1_EN==1 and LEG1_MODE==CSD also mixed with the CSD configuration and operation. In mutual cap mode however (see config.mutual_cap) the polarity of the IDAC is controlled by csd_sense. If LEG3_EN=1 (the other two legs must be off) then the ADC sequencer controls the IDACB polarity, optionally mixed with DSI.</description>
23047              <bitRange>[9:8]</bitRange>
23048              <access>read-write</access>
23049              <enumeratedValues>
23050                <enumeratedValue>
23051                  <name>VSSA_SRC</name>
23052                  <description>Normal: switch between Vssa and Cmod.  For non-CSD application, IDAC will source current.</description>
23053                  <value>0</value>
23054                </enumeratedValue>
23055                <enumeratedValue>
23056                  <name>VDDA_SNK</name>
23057                  <description>Inverted: switch between Vdda and Cmod. For non-CSD application, IDAC will sink current.</description>
23058                  <value>1</value>
23059                </enumeratedValue>
23060                <enumeratedValue>
23061                  <name>SENSE</name>
23062                  <description>The polarity of the IDAC will follow the csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC.</description>
23063                  <value>2</value>
23064                </enumeratedValue>
23065                <enumeratedValue>
23066                  <name>SENSE_INV</name>
23067                  <description>The polarity of the IDAC will follow the inverted csd_sense signal (POL_DYN bit should be set too). The intended usage is for CSX using a single IDAC.</description>
23068                  <value>3</value>
23069                </enumeratedValue>
23070              </enumeratedValues>
23071            </field>
23072            <field>
23073              <name>BAL_MODE</name>
23074              <description>same as corresponding IDACA Balancing mode</description>
23075              <bitRange>[11:10]</bitRange>
23076              <access>read-write</access>
23077              <enumeratedValues>
23078                <enumeratedValue>
23079                  <name>FULL</name>
23080                  <description>same as corresponding IDACA Balancing mode</description>
23081                  <value>0</value>
23082                </enumeratedValue>
23083                <enumeratedValue>
23084                  <name>PHI1</name>
23085                  <description>same as corresponding IDACA Balancing mode</description>
23086                  <value>1</value>
23087                </enumeratedValue>
23088                <enumeratedValue>
23089                  <name>PHI2</name>
23090                  <description>same as corresponding IDACA Balancing mode</description>
23091                  <value>2</value>
23092                </enumeratedValue>
23093                <enumeratedValue>
23094                  <name>PHI1_2</name>
23095                  <description>same as corresponding IDACA Balancing mode</description>
23096                  <value>3</value>
23097                </enumeratedValue>
23098              </enumeratedValues>
23099            </field>
23100            <field>
23101              <name>LEG1_MODE</name>
23102              <description>Controls the usage mode of LEG1 and the Polarity bit</description>
23103              <bitRange>[17:16]</bitRange>
23104              <access>read-write</access>
23105              <enumeratedValues>
23106                <enumeratedValue>
23107                  <name>GP_STATIC</name>
23108                  <description>same as corresponding IDACA.LEG1_MODE</description>
23109                  <value>0</value>
23110                </enumeratedValue>
23111                <enumeratedValue>
23112                  <name>GP</name>
23113                  <description>same as corresponding IDACA.LEG1_MODE</description>
23114                  <value>1</value>
23115                </enumeratedValue>
23116                <enumeratedValue>
23117                  <name>CSD_STATIC</name>
23118                  <description>same as corresponding IDACA.LEG1_MODE</description>
23119                  <value>2</value>
23120                </enumeratedValue>
23121                <enumeratedValue>
23122                  <name>CSD</name>
23123                  <description>same as corresponding IDACA.LEG1_MODE</description>
23124                  <value>3</value>
23125                </enumeratedValue>
23126              </enumeratedValues>
23127            </field>
23128            <field>
23129              <name>LEG2_MODE</name>
23130              <description>Controls the usage mode of LEG2</description>
23131              <bitRange>[19:18]</bitRange>
23132              <access>read-write</access>
23133              <enumeratedValues>
23134                <enumeratedValue>
23135                  <name>GP_STATIC</name>
23136                  <description>same as corresponding IDACA.LEG2_MODE</description>
23137                  <value>0</value>
23138                </enumeratedValue>
23139                <enumeratedValue>
23140                  <name>GP</name>
23141                  <description>same as corresponding IDACA.LEG2_MODE</description>
23142                  <value>1</value>
23143                </enumeratedValue>
23144                <enumeratedValue>
23145                  <name>CSD_STATIC</name>
23146                  <description>same as corresponding IDACA.LEG2_MODE</description>
23147                  <value>2</value>
23148                </enumeratedValue>
23149                <enumeratedValue>
23150                  <name>CSD</name>
23151                  <description>same as corresponding IDACA.LEG2_MODE</description>
23152                  <value>3</value>
23153                </enumeratedValue>
23154              </enumeratedValues>
23155            </field>
23156            <field>
23157              <name>DSI_CTRL_EN</name>
23158              <description>Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled)
231590: no DSI control
23160     IDACB_POLARITY = IDACB.POLARITY
23161     IDACB_LEG1_EN =  IDACB.LEG1_EN
23162     IDACB_LEG2_EN = IDACB.LEG2_EN
23163     IDACB_LEG3_EN = IDACB.LEG3_EN
231641: Mix MMIO with DSI control
23165     IDACB_POLARITY = IDACB.POLARITY EXOR dsi_idacb_pol
23166     IDACB_LEG1_EN =  IDACB.LEG1_EN AND dsi_idacb_leg1_en
23167     IDACB_LEG2_EN = IDACB.LEG2_EN AND dsi_idacb_leg2_en
23168     IDACB_LEG3_EN = IDACB.LEG3_EN AND dsi_idacb_leg3_en</description>
23169              <bitRange>[21:21]</bitRange>
23170              <access>read-write</access>
23171            </field>
23172            <field>
23173              <name>RANGE</name>
23174              <description>IDAC multiplier</description>
23175              <bitRange>[23:22]</bitRange>
23176              <access>read-write</access>
23177              <enumeratedValues>
23178                <enumeratedValue>
23179                  <name>IDAC_LO</name>
23180                  <description>1 LSB =   37.5 nA</description>
23181                  <value>0</value>
23182                </enumeratedValue>
23183                <enumeratedValue>
23184                  <name>IDAC_MED</name>
23185                  <description>1 LSB =  300 nA</description>
23186                  <value>1</value>
23187                </enumeratedValue>
23188                <enumeratedValue>
23189                  <name>IDAC_HI</name>
23190                  <description>1 LSB = 2400 nA</description>
23191                  <value>2</value>
23192                </enumeratedValue>
23193              </enumeratedValues>
23194            </field>
23195            <field>
23196              <name>LEG1_EN</name>
23197              <description>output enable for leg 1 to CSDBUSB or CSDBUSA</description>
23198              <bitRange>[24:24]</bitRange>
23199              <access>read-write</access>
23200            </field>
23201            <field>
23202              <name>LEG2_EN</name>
23203              <description>output enable for leg 2 to CSDBUSB or CSDBUSA</description>
23204              <bitRange>[25:25]</bitRange>
23205              <access>read-write</access>
23206            </field>
23207            <field>
23208              <name>LEG3_EN</name>
23209              <description>output enable for leg3 to CSDBUSC, only allowed when RANGE = IDAC_LO. When this bit is set both other legs should be off.
23210Note that leg3 can only be used for ADC mode, not GP mode. Which means that leg3 can only be on when the ADC Sequencer is in the ADC_measure or Calib_measure state. In those states  leg3 is controlled by the ADC configuration and the HSCMP output. In addition this leg3 enable bit can optionally be mixed with DSI (see DSI_CTRL_EN).
23211When LEG3_EN=1 also the IDACB polarity is controlled by the ADC sequencer.</description>
23212              <bitRange>[26:26]</bitRange>
23213              <access>read-write</access>
23214            </field>
23215          </fields>
23216        </register>
23217      </registers>
23218    </peripheral>
23219    <peripheral>
23220      <name>TCPWM0</name>
23221      <description>Timer/Counter/PWM</description>
23222      <headerStructName>TCPWM</headerStructName>
23223      <baseAddress>0x40380000</baseAddress>
23224      <addressBlock>
23225        <offset>0</offset>
23226        <size>65536</size>
23227        <usage>registers</usage>
23228      </addressBlock>
23229      <registers>
23230        <register>
23231          <name>CTRL</name>
23232          <description>TCPWM control register</description>
23233          <addressOffset>0x0</addressOffset>
23234          <size>32</size>
23235          <access>read-write</access>
23236          <resetValue>0x0</resetValue>
23237          <resetMask>0xFFFFFFFF</resetMask>
23238          <fields>
23239            <field>
23240              <name>COUNTER_ENABLED</name>
23241              <description>Counter enables for counters 0 up to CNT_NR-1.
23242'0': counter disabled.
23243'1': counter enabled.
23244Counter static configuration information (e.g. CTRL.MODE, all TR_CTRL0, TR_CTRL1, and TR_CTRL2 register fields) should only be modified when the counter is disabled. When a counter is disabled, command and status information associated to the counter is cleared by HW, this includes:
23245- the associated counter triggers in the CMD register are set to '0'.
23246- the counter's interrupt cause fields in counter's INTR register.
23247- the counter's status fields in counter's STATUS register..
23248- the counter's trigger outputs ('tr_overflow', 'tr_underflow' and 'tr_compare_match').
23249- the counter's line outputs ('line_out' and 'line_compl_out').
23250In multi-core environments, use the CTRL_SET/CTRL_CLR registers to avoid race-conditions on read-modify-write attempts to this register.</description>
23251              <bitRange>[31:0]</bitRange>
23252              <access>read-write</access>
23253            </field>
23254          </fields>
23255        </register>
23256        <register>
23257          <name>CTRL_CLR</name>
23258          <description>TCPWM control clear register</description>
23259          <addressOffset>0x4</addressOffset>
23260          <size>32</size>
23261          <access>read-write</access>
23262          <resetValue>0x0</resetValue>
23263          <resetMask>0xFFFFFFFF</resetMask>
23264          <fields>
23265            <field>
23266              <name>COUNTER_ENABLED</name>
23267              <description>Alias of CTRL that only allows disabling of counters. A write access:
23268'0': Does nothing.
23269'1': Clears respective COUNTER_ENABLED field.
23270
23271A read access returns CTRL.COUNTER_ENABLED.</description>
23272              <bitRange>[31:0]</bitRange>
23273              <access>read-write</access>
23274            </field>
23275          </fields>
23276        </register>
23277        <register>
23278          <name>CTRL_SET</name>
23279          <description>TCPWM control set register</description>
23280          <addressOffset>0x8</addressOffset>
23281          <size>32</size>
23282          <access>read-write</access>
23283          <resetValue>0x0</resetValue>
23284          <resetMask>0xFFFFFFFF</resetMask>
23285          <fields>
23286            <field>
23287              <name>COUNTER_ENABLED</name>
23288              <description>Alias of CTRL that only allows enabling of counters. A write access:
23289'0': Does nothing.
23290'1': Sets respective COUNTER_ENABLED field.
23291
23292A read access returns CTRL.COUNTER_ENABLED.</description>
23293              <bitRange>[31:0]</bitRange>
23294              <access>read-write</access>
23295            </field>
23296          </fields>
23297        </register>
23298        <register>
23299          <name>CMD_CAPTURE</name>
23300          <description>TCPWM capture command register</description>
23301          <addressOffset>0xC</addressOffset>
23302          <size>32</size>
23303          <access>read-write</access>
23304          <resetValue>0x0</resetValue>
23305          <resetMask>0xFFFFFFFF</resetMask>
23306          <fields>
23307            <field>
23308              <name>COUNTER_CAPTURE</name>
23309              <description>Counters SW capture trigger. When written with '1', a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is disabled through CTRL.COUNTER_ENABLED, the field is immediately set to '0'.</description>
23310              <bitRange>[31:0]</bitRange>
23311              <access>read-write</access>
23312            </field>
23313          </fields>
23314        </register>
23315        <register>
23316          <name>CMD_RELOAD</name>
23317          <description>TCPWM reload command register</description>
23318          <addressOffset>0x10</addressOffset>
23319          <size>32</size>
23320          <access>read-write</access>
23321          <resetValue>0x0</resetValue>
23322          <resetMask>0xFFFFFFFF</resetMask>
23323          <fields>
23324            <field>
23325              <name>COUNTER_RELOAD</name>
23326              <description>Counters SW reload trigger. For HW behavior, see COUNTER_CAPTURE field.</description>
23327              <bitRange>[31:0]</bitRange>
23328              <access>read-write</access>
23329            </field>
23330          </fields>
23331        </register>
23332        <register>
23333          <name>CMD_STOP</name>
23334          <description>TCPWM stop command register</description>
23335          <addressOffset>0x14</addressOffset>
23336          <size>32</size>
23337          <access>read-write</access>
23338          <resetValue>0x0</resetValue>
23339          <resetMask>0xFFFFFFFF</resetMask>
23340          <fields>
23341            <field>
23342              <name>COUNTER_STOP</name>
23343              <description>Counters SW stop trigger. For HW behavior, see COUNTER_CAPTURE field.</description>
23344              <bitRange>[31:0]</bitRange>
23345              <access>read-write</access>
23346            </field>
23347          </fields>
23348        </register>
23349        <register>
23350          <name>CMD_START</name>
23351          <description>TCPWM start command register</description>
23352          <addressOffset>0x18</addressOffset>
23353          <size>32</size>
23354          <access>read-write</access>
23355          <resetValue>0x0</resetValue>
23356          <resetMask>0xFFFFFFFF</resetMask>
23357          <fields>
23358            <field>
23359              <name>COUNTER_START</name>
23360              <description>Counters SW start trigger. For HW behavior, see COUNTER_CAPTURE field.</description>
23361              <bitRange>[31:0]</bitRange>
23362              <access>read-write</access>
23363            </field>
23364          </fields>
23365        </register>
23366        <register>
23367          <name>INTR_CAUSE</name>
23368          <description>TCPWM Counter interrupt cause register</description>
23369          <addressOffset>0x1C</addressOffset>
23370          <size>32</size>
23371          <access>read-only</access>
23372          <resetValue>0x0</resetValue>
23373          <resetMask>0xFFFFFFFF</resetMask>
23374          <fields>
23375            <field>
23376              <name>COUNTER_INT</name>
23377              <description>Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED, the associated interrupt field is immediately set to '0'.</description>
23378              <bitRange>[31:0]</bitRange>
23379              <access>read-only</access>
23380            </field>
23381          </fields>
23382        </register>
23383        <cluster>
23384          <dim>24</dim>
23385          <dimIncrement>64</dimIncrement>
23386          <name>CNT[%s]</name>
23387          <description>Timer/Counter/PWM Counter Module</description>
23388          <addressOffset>0x00000100</addressOffset>
23389          <register>
23390            <name>CTRL</name>
23391            <description>Counter control register</description>
23392            <addressOffset>0x0</addressOffset>
23393            <size>32</size>
23394            <access>read-write</access>
23395            <resetValue>0x0</resetValue>
23396            <resetMask>0x737FF0F</resetMask>
23397            <fields>
23398              <field>
23399                <name>AUTO_RELOAD_CC</name>
23400                <description>Specifies switching of the CC and buffered CC values. This field has a function in TIMER, PWM, PWM_DT and PWM_PR modes.
23401Timer mode:
23402'0': never switch.
23403'1': switch on a compare match event.
23404PWM, PWM_DT, PWM_PR modes:
23405'0: never switch.
23406'1': switch on a terminal count event with an actively pending switch event.</description>
23407                <bitRange>[0:0]</bitRange>
23408                <access>read-write</access>
23409              </field>
23410              <field>
23411                <name>AUTO_RELOAD_PERIOD</name>
23412                <description>Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM, PWM_DT and PWM_PR modes.
23413'0': never switch.
23414'1': switch on a terminal count event with and actively pending switch event.</description>
23415                <bitRange>[1:1]</bitRange>
23416                <access>read-write</access>
23417              </field>
23418              <field>
23419                <name>PWM_SYNC_KILL</name>
23420                <description>Specifies asynchronous/synchronous kill behavior:
23421'1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill). In synchronous kill mode, STOP_EDGE should  be RISING_EDGE.
23422'0': asynchronous kill mode: the kill event only disables the 'dt_line_out' and 'dt_line_compl_out' signals when present. In asynchronous kill mode, STOP_EDGE should be NO_EDGE_DET.
23423
23424This field has a function in PWM and PWM_DT modes only. This field is only used when PWM_STOP_ON_KILL is '0'.</description>
23425                <bitRange>[2:2]</bitRange>
23426                <access>read-write</access>
23427              </field>
23428              <field>
23429                <name>PWM_STOP_ON_KILL</name>
23430                <description>Specifies whether the counter stops on a kill events:
23431'0': kill event does NOT stop counter.
23432'1': kill event stops counter.
23433
23434This field has a function in PWM, PWM_DT and PWM_PR modes only.</description>
23435                <bitRange>[3:3]</bitRange>
23436                <access>read-write</access>
23437              </field>
23438              <field>
23439                <name>GENERIC</name>
23440                <description>Generic 8-bit control field. In PWM_DT mode, this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes, the lower 3 bits of this field determine pre-scaling of the selected counter clock.</description>
23441                <bitRange>[15:8]</bitRange>
23442                <access>read-write</access>
23443              </field>
23444              <field>
23445                <name>UP_DOWN_MODE</name>
23446                <description>Determines counter direction.</description>
23447                <bitRange>[17:16]</bitRange>
23448                <access>read-write</access>
23449                <enumeratedValues>
23450                  <enumeratedValue>
23451                    <name>COUNT_UP</name>
23452                    <description>Count up (to PERIOD). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. A terminal count event is generated when the counter changes from a state in which COUNTER equals PERIOD.</description>
23453                    <value>0</value>
23454                  </enumeratedValue>
23455                  <enumeratedValue>
23456                    <name>COUNT_DOWN</name>
23457                    <description>Count down (to '0'). An underflow event is generated when  the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.</description>
23458                    <value>1</value>
23459                  </enumeratedValue>
23460                  <enumeratedValue>
23461                    <name>COUNT_UPDN1</name>
23462                    <description>Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0'.</description>
23463                    <value>2</value>
23464                  </enumeratedValue>
23465                  <enumeratedValue>
23466                    <name>COUNT_UPDN2</name>
23467                    <description>Count up (to PERIOD), then count down (to '0'). An overflow event is generated when the counter changes from a state in which COUNTER equals PERIOD. An underflow event is generated when the counter changes from a state in which COUNTER equals '0'. A terminal count event is generated when the counter changes from a state in which COUNTER equals '0' AND when the counter changes from a state in which COUNTER equals PERIOD (this counter direction can be used for PWM functionality with asymmetrical updates).</description>
23468                    <value>3</value>
23469                  </enumeratedValue>
23470                </enumeratedValues>
23471              </field>
23472              <field>
23473                <name>ONE_SHOT</name>
23474                <description>When '0', counter runs continuous. When '1', counter is turned off by hardware when a terminal count event is generated.</description>
23475                <bitRange>[18:18]</bitRange>
23476                <access>read-write</access>
23477              </field>
23478              <field>
23479                <name>QUADRATURE_MODE</name>
23480                <description>In QUAD mode selects quadrature encoding mode (X1/X2/X4).
23481In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert 'dt_line_out' and 'dt_line_compl_out'.  Inversion is the last step in generation of 'dt_line_out' and 'dt_line_compl_out'; i.e. a disabled output line 'dt_line_out' has the value QUADRATURE_MODE[0] and a disabled output line 'dt_line_compl_out' has the value QUADRATURE_MODE[1].</description>
23482                <bitRange>[21:20]</bitRange>
23483                <access>read-write</access>
23484                <enumeratedValues>
23485                  <enumeratedValue>
23486                    <name>X1</name>
23487                    <description>X1 encoding (QUAD mode)</description>
23488                    <value>0</value>
23489                  </enumeratedValue>
23490                  <enumeratedValue>
23491                    <name>X2</name>
23492                    <description>X2 encoding (QUAD mode)</description>
23493                    <value>1</value>
23494                  </enumeratedValue>
23495                  <enumeratedValue>
23496                    <name>X4</name>
23497                    <description>X4 encoding (QUAD mode)</description>
23498                    <value>2</value>
23499                  </enumeratedValue>
23500                </enumeratedValues>
23501              </field>
23502              <field>
23503                <name>MODE</name>
23504                <description>Counter mode.</description>
23505                <bitRange>[26:24]</bitRange>
23506                <access>read-write</access>
23507                <enumeratedValues>
23508                  <enumeratedValue>
23509                    <name>TIMER</name>
23510                    <description>Timer mode</description>
23511                    <value>0</value>
23512                  </enumeratedValue>
23513                  <enumeratedValue>
23514                    <name>CAPTURE</name>
23515                    <description>Capture mode</description>
23516                    <value>2</value>
23517                  </enumeratedValue>
23518                  <enumeratedValue>
23519                    <name>QUAD</name>
23520                    <description>Quadrature encoding mode</description>
23521                    <value>3</value>
23522                  </enumeratedValue>
23523                  <enumeratedValue>
23524                    <name>PWM</name>
23525                    <description>Pulse width modulation (PWM) mode</description>
23526                    <value>4</value>
23527                  </enumeratedValue>
23528                  <enumeratedValue>
23529                    <name>PWM_DT</name>
23530                    <description>PWM with deadtime insertion mode</description>
23531                    <value>5</value>
23532                  </enumeratedValue>
23533                  <enumeratedValue>
23534                    <name>PWM_PR</name>
23535                    <description>Pseudo random pulse width modulation</description>
23536                    <value>6</value>
23537                  </enumeratedValue>
23538                </enumeratedValues>
23539              </field>
23540            </fields>
23541          </register>
23542          <register>
23543            <name>STATUS</name>
23544            <description>Counter status register</description>
23545            <addressOffset>0x4</addressOffset>
23546            <size>32</size>
23547            <access>read-only</access>
23548            <resetValue>0x0</resetValue>
23549            <resetMask>0x8000FF01</resetMask>
23550            <fields>
23551              <field>
23552                <name>DOWN</name>
23553                <description>When '0', counter is counting up. When '1', counter is counting down. In QUAD mode, this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented.</description>
23554                <bitRange>[0:0]</bitRange>
23555                <access>read-only</access>
23556              </field>
23557              <field>
23558                <name>GENERIC</name>
23559                <description>Generic 8-bit counter field. In PWM_DT mode, this counter is used for dead time insertion. In all other modes, this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality.</description>
23560                <bitRange>[15:8]</bitRange>
23561                <access>read-only</access>
23562              </field>
23563              <field>
23564                <name>RUNNING</name>
23565                <description>When '0', the counter is NOT running. When '1', the counter is running.</description>
23566                <bitRange>[31:31]</bitRange>
23567                <access>read-only</access>
23568              </field>
23569            </fields>
23570          </register>
23571          <register>
23572            <name>COUNTER</name>
23573            <description>Counter count register</description>
23574            <addressOffset>0x8</addressOffset>
23575            <size>32</size>
23576            <access>read-write</access>
23577            <resetValue>0x0</resetValue>
23578            <resetMask>0xFFFFFFFF</resetMask>
23579            <fields>
23580              <field>
23581                <name>COUNTER</name>
23582                <description>16-bit / 32-bit counter value. It is advised to not write to this field when the counter is running.</description>
23583                <bitRange>[31:0]</bitRange>
23584                <access>read-write</access>
23585              </field>
23586            </fields>
23587          </register>
23588          <register>
23589            <name>CC</name>
23590            <description>Counter compare/capture register</description>
23591            <addressOffset>0xC</addressOffset>
23592            <size>32</size>
23593            <access>read-write</access>
23594            <resetValue>0xFFFFFFFF</resetValue>
23595            <resetMask>0xFFFFFFFF</resetMask>
23596            <fields>
23597              <field>
23598                <name>CC</name>
23599                <description>In CAPTURE mode, captures the counter value. In other modes, compared to counter value.</description>
23600                <bitRange>[31:0]</bitRange>
23601                <access>read-write</access>
23602              </field>
23603            </fields>
23604          </register>
23605          <register>
23606            <name>CC_BUFF</name>
23607            <description>Counter buffered compare/capture register</description>
23608            <addressOffset>0x10</addressOffset>
23609            <size>32</size>
23610            <access>read-write</access>
23611            <resetValue>0xFFFFFFFF</resetValue>
23612            <resetMask>0xFFFFFFFF</resetMask>
23613            <fields>
23614              <field>
23615                <name>CC</name>
23616                <description>Additional buffer for counter CC register.</description>
23617                <bitRange>[31:0]</bitRange>
23618                <access>read-write</access>
23619              </field>
23620            </fields>
23621          </register>
23622          <register>
23623            <name>PERIOD</name>
23624            <description>Counter period register</description>
23625            <addressOffset>0x14</addressOffset>
23626            <size>32</size>
23627            <access>read-write</access>
23628            <resetValue>0xFFFFFFFF</resetValue>
23629            <resetMask>0xFFFFFFFF</resetMask>
23630            <fields>
23631              <field>
23632                <name>PERIOD</name>
23633                <description>Period value: upper value of the counter. When the counter should count for n cycles, this field should be set to n-1.</description>
23634                <bitRange>[31:0]</bitRange>
23635                <access>read-write</access>
23636              </field>
23637            </fields>
23638          </register>
23639          <register>
23640            <name>PERIOD_BUFF</name>
23641            <description>Counter buffered period register</description>
23642            <addressOffset>0x18</addressOffset>
23643            <size>32</size>
23644            <access>read-write</access>
23645            <resetValue>0xFFFFFFFF</resetValue>
23646            <resetMask>0xFFFFFFFF</resetMask>
23647            <fields>
23648              <field>
23649                <name>PERIOD</name>
23650                <description>Additional buffer for counter PERIOD register.</description>
23651                <bitRange>[31:0]</bitRange>
23652                <access>read-write</access>
23653              </field>
23654            </fields>
23655          </register>
23656          <register>
23657            <name>TR_CTRL0</name>
23658            <description>Counter trigger control register 0</description>
23659            <addressOffset>0x20</addressOffset>
23660            <size>32</size>
23661            <access>read-write</access>
23662            <resetValue>0x10</resetValue>
23663            <resetMask>0xFFFFF</resetMask>
23664            <fields>
23665              <field>
23666                <name>CAPTURE_SEL</name>
23667                <description>Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.</description>
23668                <bitRange>[3:0]</bitRange>
23669                <access>read-write</access>
23670              </field>
23671              <field>
23672                <name>COUNT_SEL</name>
23673                <description>Selects one of the 16 input triggers as a count trigger. In QUAD mode, this is the first phase (phi A). Default setting selects input trigger 1, which is always '1'.</description>
23674                <bitRange>[7:4]</bitRange>
23675                <access>read-write</access>
23676              </field>
23677              <field>
23678                <name>RELOAD_SEL</name>
23679                <description>Selects one of the 16 input triggers as a reload trigger. In QUAD mode, this is the index or revolution pulse. In this mode, it will update the counter with 0x8000 (counter midpoint).</description>
23680                <bitRange>[11:8]</bitRange>
23681                <access>read-write</access>
23682              </field>
23683              <field>
23684                <name>STOP_SEL</name>
23685                <description>Selects one of the 16 input triggers as a stop trigger. In PWM, PWM_DT and PWM_PR modes, this is the kill trigger. In these modes, the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the functionality (PWM_STOP_ON_KILL is '1'). For the PWM and PWM_DT modes, the blocking of the output signals can be  asynchronous (STOP_EDGE should be NO_EDGE_DET) in which case the blocking is as long as the trigger is '1' or synchronous (STOP_EDGE should be RISING_EDGE) in which case it extends till the next terminal count event.</description>
23686                <bitRange>[15:12]</bitRange>
23687                <access>read-write</access>
23688              </field>
23689              <field>
23690                <name>START_SEL</name>
23691                <description>Selects one of the 16 input triggers as a start trigger. In QUAD mode, this is the second phase (phi B).</description>
23692                <bitRange>[19:16]</bitRange>
23693                <access>read-write</access>
23694              </field>
23695            </fields>
23696          </register>
23697          <register>
23698            <name>TR_CTRL1</name>
23699            <description>Counter trigger control register 1</description>
23700            <addressOffset>0x24</addressOffset>
23701            <size>32</size>
23702            <access>read-write</access>
23703            <resetValue>0x3FF</resetValue>
23704            <resetMask>0x3FF</resetMask>
23705            <fields>
23706              <field>
23707                <name>CAPTURE_EDGE</name>
23708                <description>A capture event will copy the counter value into the CC register.</description>
23709                <bitRange>[1:0]</bitRange>
23710                <access>read-write</access>
23711                <enumeratedValues>
23712                  <enumeratedValue>
23713                    <name>RISING_EDGE</name>
23714                    <description>Rising edge. Any rising edge generates an event.</description>
23715                    <value>0</value>
23716                  </enumeratedValue>
23717                  <enumeratedValue>
23718                    <name>FALLING_EDGE</name>
23719                    <description>Falling edge. Any falling edge generates an event.</description>
23720                    <value>1</value>
23721                  </enumeratedValue>
23722                  <enumeratedValue>
23723                    <name>BOTH_EDGES</name>
23724                    <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
23725                    <value>2</value>
23726                  </enumeratedValue>
23727                  <enumeratedValue>
23728                    <name>NO_EDGE_DET</name>
23729                    <description>No edge detection, use trigger as is.</description>
23730                    <value>3</value>
23731                  </enumeratedValue>
23732                </enumeratedValues>
23733              </field>
23734              <field>
23735                <name>COUNT_EDGE</name>
23736                <description>A counter event will increase or decrease the counter by '1'.</description>
23737                <bitRange>[3:2]</bitRange>
23738                <access>read-write</access>
23739                <enumeratedValues>
23740                  <enumeratedValue>
23741                    <name>RISING_EDGE</name>
23742                    <description>Rising edge. Any rising edge generates an event.</description>
23743                    <value>0</value>
23744                  </enumeratedValue>
23745                  <enumeratedValue>
23746                    <name>FALLING_EDGE</name>
23747                    <description>Falling edge. Any falling edge generates an event.</description>
23748                    <value>1</value>
23749                  </enumeratedValue>
23750                  <enumeratedValue>
23751                    <name>BOTH_EDGES</name>
23752                    <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
23753                    <value>2</value>
23754                  </enumeratedValue>
23755                  <enumeratedValue>
23756                    <name>NO_EDGE_DET</name>
23757                    <description>No edge detection, use trigger as is.</description>
23758                    <value>3</value>
23759                  </enumeratedValue>
23760                </enumeratedValues>
23761              </field>
23762              <field>
23763                <name>RELOAD_EDGE</name>
23764                <description>A reload event will initialize the counter. When counting up, the counter is initialized to '0'. When counting down, the counter is initialized with PERIOD.</description>
23765                <bitRange>[5:4]</bitRange>
23766                <access>read-write</access>
23767                <enumeratedValues>
23768                  <enumeratedValue>
23769                    <name>RISING_EDGE</name>
23770                    <description>Rising edge. Any rising edge generates an event.</description>
23771                    <value>0</value>
23772                  </enumeratedValue>
23773                  <enumeratedValue>
23774                    <name>FALLING_EDGE</name>
23775                    <description>Falling edge. Any falling edge generates an event.</description>
23776                    <value>1</value>
23777                  </enumeratedValue>
23778                  <enumeratedValue>
23779                    <name>BOTH_EDGES</name>
23780                    <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
23781                    <value>2</value>
23782                  </enumeratedValue>
23783                  <enumeratedValue>
23784                    <name>NO_EDGE_DET</name>
23785                    <description>No edge detection, use trigger as is.</description>
23786                    <value>3</value>
23787                  </enumeratedValue>
23788                </enumeratedValues>
23789              </field>
23790              <field>
23791                <name>STOP_EDGE</name>
23792                <description>A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter.</description>
23793                <bitRange>[7:6]</bitRange>
23794                <access>read-write</access>
23795                <enumeratedValues>
23796                  <enumeratedValue>
23797                    <name>RISING_EDGE</name>
23798                    <description>Rising edge. Any rising edge generates an event.</description>
23799                    <value>0</value>
23800                  </enumeratedValue>
23801                  <enumeratedValue>
23802                    <name>FALLING_EDGE</name>
23803                    <description>Falling edge. Any falling edge generates an event.</description>
23804                    <value>1</value>
23805                  </enumeratedValue>
23806                  <enumeratedValue>
23807                    <name>BOTH_EDGES</name>
23808                    <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
23809                    <value>2</value>
23810                  </enumeratedValue>
23811                  <enumeratedValue>
23812                    <name>NO_EDGE_DET</name>
23813                    <description>No edge detection, use trigger as is.</description>
23814                    <value>3</value>
23815                  </enumeratedValue>
23816                </enumeratedValues>
23817              </field>
23818              <field>
23819                <name>START_EDGE</name>
23820                <description>A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does.</description>
23821                <bitRange>[9:8]</bitRange>
23822                <access>read-write</access>
23823                <enumeratedValues>
23824                  <enumeratedValue>
23825                    <name>RISING_EDGE</name>
23826                    <description>Rising edge. Any rising edge generates an event.</description>
23827                    <value>0</value>
23828                  </enumeratedValue>
23829                  <enumeratedValue>
23830                    <name>FALLING_EDGE</name>
23831                    <description>Falling edge. Any falling edge generates an event.</description>
23832                    <value>1</value>
23833                  </enumeratedValue>
23834                  <enumeratedValue>
23835                    <name>BOTH_EDGES</name>
23836                    <description>Rising AND falling edge. Any odd amount of edges generates an event.</description>
23837                    <value>2</value>
23838                  </enumeratedValue>
23839                  <enumeratedValue>
23840                    <name>NO_EDGE_DET</name>
23841                    <description>No edge detection, use trigger as is.</description>
23842                    <value>3</value>
23843                  </enumeratedValue>
23844                </enumeratedValues>
23845              </field>
23846            </fields>
23847          </register>
23848          <register>
23849            <name>TR_CTRL2</name>
23850            <description>Counter trigger control register 2</description>
23851            <addressOffset>0x28</addressOffset>
23852            <size>32</size>
23853            <access>read-write</access>
23854            <resetValue>0x3F</resetValue>
23855            <resetMask>0x3F</resetMask>
23856            <fields>
23857              <field>
23858                <name>CC_MATCH_MODE</name>
23859                <description>Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals.  Note that INVERT is especially useful for center aligned pulse width modulation.
23860To generate a duty cycle of 0 percent, the counter CC register should be set to '0'. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register.</description>
23861                <bitRange>[1:0]</bitRange>
23862                <access>read-write</access>
23863                <enumeratedValues>
23864                  <enumeratedValue>
23865                    <name>SET</name>
23866                    <description>Set to '1'</description>
23867                    <value>0</value>
23868                  </enumeratedValue>
23869                  <enumeratedValue>
23870                    <name>CLEAR</name>
23871                    <description>Set to '0'</description>
23872                    <value>1</value>
23873                  </enumeratedValue>
23874                  <enumeratedValue>
23875                    <name>INVERT</name>
23876                    <description>Invert</description>
23877                    <value>2</value>
23878                  </enumeratedValue>
23879                  <enumeratedValue>
23880                    <name>NO_CHANGE</name>
23881                    <description>No Change</description>
23882                    <value>3</value>
23883                  </enumeratedValue>
23884                </enumeratedValues>
23885              </field>
23886              <field>
23887                <name>OVERFLOW_MODE</name>
23888                <description>Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals.</description>
23889                <bitRange>[3:2]</bitRange>
23890                <access>read-write</access>
23891                <enumeratedValues>
23892                  <enumeratedValue>
23893                    <name>SET</name>
23894                    <description>Set to '1'</description>
23895                    <value>0</value>
23896                  </enumeratedValue>
23897                  <enumeratedValue>
23898                    <name>CLEAR</name>
23899                    <description>Set to '0'</description>
23900                    <value>1</value>
23901                  </enumeratedValue>
23902                  <enumeratedValue>
23903                    <name>INVERT</name>
23904                    <description>Invert</description>
23905                    <value>2</value>
23906                  </enumeratedValue>
23907                  <enumeratedValue>
23908                    <name>NO_CHANGE</name>
23909                    <description>No Change</description>
23910                    <value>3</value>
23911                  </enumeratedValue>
23912                </enumeratedValues>
23913              </field>
23914              <field>
23915                <name>UNDERFLOW_MODE</name>
23916                <description>Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals.</description>
23917                <bitRange>[5:4]</bitRange>
23918                <access>read-write</access>
23919                <enumeratedValues>
23920                  <enumeratedValue>
23921                    <name>SET</name>
23922                    <description>Set to '1'</description>
23923                    <value>0</value>
23924                  </enumeratedValue>
23925                  <enumeratedValue>
23926                    <name>CLEAR</name>
23927                    <description>Set to '0'</description>
23928                    <value>1</value>
23929                  </enumeratedValue>
23930                  <enumeratedValue>
23931                    <name>INVERT</name>
23932                    <description>Invert</description>
23933                    <value>2</value>
23934                  </enumeratedValue>
23935                  <enumeratedValue>
23936                    <name>NO_CHANGE</name>
23937                    <description>No Change</description>
23938                    <value>3</value>
23939                  </enumeratedValue>
23940                </enumeratedValues>
23941              </field>
23942            </fields>
23943          </register>
23944          <register>
23945            <name>INTR</name>
23946            <description>Interrupt request register</description>
23947            <addressOffset>0x30</addressOffset>
23948            <size>32</size>
23949            <access>read-write</access>
23950            <resetValue>0x0</resetValue>
23951            <resetMask>0x3</resetMask>
23952            <fields>
23953              <field>
23954                <name>TC</name>
23955                <description>Terminal count event. Set to '1', when event is detected. Write with '1' to clear bit.</description>
23956                <bitRange>[0:0]</bitRange>
23957                <access>read-write</access>
23958              </field>
23959              <field>
23960                <name>CC_MATCH</name>
23961                <description>Counter matches CC register event. Set to '1', when event is detected. Write with '1' to clear bit.</description>
23962                <bitRange>[1:1]</bitRange>
23963                <access>read-write</access>
23964              </field>
23965            </fields>
23966          </register>
23967          <register>
23968            <name>INTR_SET</name>
23969            <description>Interrupt set request register</description>
23970            <addressOffset>0x34</addressOffset>
23971            <size>32</size>
23972            <access>read-write</access>
23973            <resetValue>0x0</resetValue>
23974            <resetMask>0x3</resetMask>
23975            <fields>
23976              <field>
23977                <name>TC</name>
23978                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
23979                <bitRange>[0:0]</bitRange>
23980                <access>read-write</access>
23981              </field>
23982              <field>
23983                <name>CC_MATCH</name>
23984                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
23985                <bitRange>[1:1]</bitRange>
23986                <access>read-write</access>
23987              </field>
23988            </fields>
23989          </register>
23990          <register>
23991            <name>INTR_MASK</name>
23992            <description>Interrupt mask register</description>
23993            <addressOffset>0x38</addressOffset>
23994            <size>32</size>
23995            <access>read-write</access>
23996            <resetValue>0x0</resetValue>
23997            <resetMask>0x3</resetMask>
23998            <fields>
23999              <field>
24000                <name>TC</name>
24001                <description>Mask bit for corresponding bit in interrupt request register.</description>
24002                <bitRange>[0:0]</bitRange>
24003                <access>read-write</access>
24004              </field>
24005              <field>
24006                <name>CC_MATCH</name>
24007                <description>Mask bit for corresponding bit in interrupt request register.</description>
24008                <bitRange>[1:1]</bitRange>
24009                <access>read-write</access>
24010              </field>
24011            </fields>
24012          </register>
24013          <register>
24014            <name>INTR_MASKED</name>
24015            <description>Interrupt masked request register</description>
24016            <addressOffset>0x3C</addressOffset>
24017            <size>32</size>
24018            <access>read-only</access>
24019            <resetValue>0x0</resetValue>
24020            <resetMask>0x3</resetMask>
24021            <fields>
24022              <field>
24023                <name>TC</name>
24024                <description>Logical and of corresponding request and mask bits.</description>
24025                <bitRange>[0:0]</bitRange>
24026                <access>read-only</access>
24027              </field>
24028              <field>
24029                <name>CC_MATCH</name>
24030                <description>Logical and of corresponding request and mask bits.</description>
24031                <bitRange>[1:1]</bitRange>
24032                <access>read-only</access>
24033              </field>
24034            </fields>
24035          </register>
24036        </cluster>
24037      </registers>
24038    </peripheral>
24039    <peripheral derivedFrom="TCPWM0">
24040      <name>TCPWM1</name>
24041      <baseAddress>0x40390000</baseAddress>
24042    </peripheral>
24043    <peripheral>
24044      <name>LCD0</name>
24045      <description>LCD Controller Block</description>
24046      <headerStructName>LCD</headerStructName>
24047      <baseAddress>0x403B0000</baseAddress>
24048      <addressBlock>
24049        <offset>0</offset>
24050        <size>65536</size>
24051        <usage>registers</usage>
24052      </addressBlock>
24053      <registers>
24054        <register>
24055          <name>ID</name>
24056          <description>ID &amp; Revision</description>
24057          <addressOffset>0x0</addressOffset>
24058          <size>32</size>
24059          <access>read-only</access>
24060          <resetValue>0x1F0F0</resetValue>
24061          <resetMask>0xFFFFFFFF</resetMask>
24062          <fields>
24063            <field>
24064              <name>ID</name>
24065              <description>the ID of LCD controller peripheral is 0xF0F0</description>
24066              <bitRange>[15:0]</bitRange>
24067              <access>read-only</access>
24068            </field>
24069            <field>
24070              <name>REVISION</name>
24071              <description>the version number is 0x0001</description>
24072              <bitRange>[31:16]</bitRange>
24073              <access>read-only</access>
24074            </field>
24075          </fields>
24076        </register>
24077        <register>
24078          <name>DIVIDER</name>
24079          <description>LCD Divider Register</description>
24080          <addressOffset>0x4</addressOffset>
24081          <size>32</size>
24082          <access>read-write</access>
24083          <resetValue>0x0</resetValue>
24084          <resetMask>0xFFFFFFFF</resetMask>
24085          <fields>
24086            <field>
24087              <name>SUBFR_DIV</name>
24088              <description>Input clock frequency divide value, to generate the 1/4 sub-frame period. The sub-frame period is  4*(SUBFR_DIV+1) cycles long.</description>
24089              <bitRange>[15:0]</bitRange>
24090              <access>read-write</access>
24091            </field>
24092            <field>
24093              <name>DEAD_DIV</name>
24094              <description>Length of the dead time period in cycles.  When set to  zero, no dead time period exists.</description>
24095              <bitRange>[31:16]</bitRange>
24096              <access>read-write</access>
24097            </field>
24098          </fields>
24099        </register>
24100        <register>
24101          <name>CONTROL</name>
24102          <description>LCD Configuration Register</description>
24103          <addressOffset>0x8</addressOffset>
24104          <size>32</size>
24105          <access>read-write</access>
24106          <resetValue>0x0</resetValue>
24107          <resetMask>0x80000F7F</resetMask>
24108          <fields>
24109            <field>
24110              <name>LS_EN</name>
24111              <description>Low speed (LS) generator enable
241121: enable
241130: disable</description>
24114              <bitRange>[0:0]</bitRange>
24115              <access>read-write</access>
24116            </field>
24117            <field>
24118              <name>HS_EN</name>
24119              <description>High speed (HS) generator enable
241201: enable
241210: disable</description>
24122              <bitRange>[1:1]</bitRange>
24123              <access>read-write</access>
24124            </field>
24125            <field>
24126              <name>LCD_MODE</name>
24127              <description>HS/LS Mode selection</description>
24128              <bitRange>[2:2]</bitRange>
24129              <access>read-write</access>
24130              <enumeratedValues>
24131                <enumeratedValue>
24132                  <name>LS</name>
24133                  <description>Select Low Speed (32kHz) Generator (Works in Active, Sleep and DeepSleep power modes).</description>
24134                  <value>0</value>
24135                </enumeratedValue>
24136                <enumeratedValue>
24137                  <name>HS</name>
24138                  <description>Select High Speed (system clock) Generator (Works in Active and Sleep power modes only).</description>
24139                  <value>1</value>
24140                </enumeratedValue>
24141              </enumeratedValues>
24142            </field>
24143            <field>
24144              <name>TYPE</name>
24145              <description>LCD driving waveform type configuration.</description>
24146              <bitRange>[3:3]</bitRange>
24147              <access>read-write</access>
24148              <enumeratedValues>
24149                <enumeratedValue>
24150                  <name>TYPE_A</name>
24151                  <description>Type A - Each frame addresses each COM pin only once with a balanced (DC=0) waveform.</description>
24152                  <value>0</value>
24153                </enumeratedValue>
24154                <enumeratedValue>
24155                  <name>TYPE_B</name>
24156                  <description>Type B - Each frame addresses each COM pin twice in sequence with a positive and negative waveform that together are balanced (DC=0).</description>
24157                  <value>1</value>
24158                </enumeratedValue>
24159              </enumeratedValues>
24160            </field>
24161            <field>
24162              <name>OP_MODE</name>
24163              <description>Driving mode configuration</description>
24164              <bitRange>[4:4]</bitRange>
24165              <access>read-write</access>
24166              <enumeratedValues>
24167                <enumeratedValue>
24168                  <name>PWM</name>
24169                  <description>PWM Mode</description>
24170                  <value>0</value>
24171                </enumeratedValue>
24172                <enumeratedValue>
24173                  <name>CORRELATION</name>
24174                  <description>Digital Correlation Mode</description>
24175                  <value>1</value>
24176                </enumeratedValue>
24177              </enumeratedValues>
24178            </field>
24179            <field>
24180              <name>BIAS</name>
24181              <description>PWM bias selection</description>
24182              <bitRange>[6:5]</bitRange>
24183              <access>read-write</access>
24184              <enumeratedValues>
24185                <enumeratedValue>
24186                  <name>HALF</name>
24187                  <description>1/2 Bias</description>
24188                  <value>0</value>
24189                </enumeratedValue>
24190                <enumeratedValue>
24191                  <name>THIRD</name>
24192                  <description>1/3 Bias</description>
24193                  <value>1</value>
24194                </enumeratedValue>
24195                <enumeratedValue>
24196                  <name>FOURTH</name>
24197                  <description>1/4 Bias (not supported by LS generator)</description>
24198                  <value>2</value>
24199                </enumeratedValue>
24200                <enumeratedValue>
24201                  <name>FIFTH</name>
24202                  <description>1/5 Bias (not supported by LS generator)</description>
24203                  <value>3</value>
24204                </enumeratedValue>
24205              </enumeratedValues>
24206            </field>
24207            <field>
24208              <name>COM_NUM</name>
24209              <description>The number of COM connections minus 2. So:
242100: 2 COM's
242111: 3 COM's
24212...
2421313: 15 COM's
2421414: 16 COM's
2421515: undefined</description>
24216              <bitRange>[11:8]</bitRange>
24217              <access>read-write</access>
24218            </field>
24219            <field>
24220              <name>LS_EN_STAT</name>
24221              <description>LS enable status bit.  This bit is a copy of LS_EN that is synchronized to the low speed clock domain and back to the system clock domain. Firmware can use this bit to observe whether LS_EN has taken effect in the low speed clock domain.  Firmware should never change the configuration for the LS generator without ensuring this bit is 0.
24222The following procedure should be followed to disable the LS generator:
242231. If LS_EN=0 we are done.  Exit the procedure.
242242. Check that LS_EN_STAT=1.  If not, wait until it is. This will catch the case of a recent enable (LS_EN=1) that has not taken effect yet.
242253. Set LS_EN=0.
242264. Wait until LS_EN_STAT=0.</description>
24227              <bitRange>[31:31]</bitRange>
24228              <access>read-only</access>
24229            </field>
24230          </fields>
24231        </register>
24232        <register>
24233          <dim>8</dim>
24234          <dimIncrement>4</dimIncrement>
24235          <name>DATA0[%s]</name>
24236          <description>LCD Pin Data Registers</description>
24237          <addressOffset>0x100</addressOffset>
24238          <size>32</size>
24239          <access>read-write</access>
24240          <resetValue>0x0</resetValue>
24241          <resetMask>0xFFFFFFFF</resetMask>
24242          <fields>
24243            <field>
24244              <name>DATA</name>
24245              <description>Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb).</description>
24246              <bitRange>[31:0]</bitRange>
24247              <access>read-write</access>
24248            </field>
24249          </fields>
24250        </register>
24251        <register>
24252          <dim>8</dim>
24253          <dimIncrement>4</dimIncrement>
24254          <name>DATA1[%s]</name>
24255          <description>LCD Pin Data Registers</description>
24256          <addressOffset>0x200</addressOffset>
24257          <size>32</size>
24258          <access>read-write</access>
24259          <resetValue>0x0</resetValue>
24260          <resetMask>0xFFFFFFFF</resetMask>
24261          <fields>
24262            <field>
24263              <name>DATA</name>
24264              <description>Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb).</description>
24265              <bitRange>[31:0]</bitRange>
24266              <access>read-write</access>
24267            </field>
24268          </fields>
24269        </register>
24270        <register>
24271          <dim>8</dim>
24272          <dimIncrement>4</dimIncrement>
24273          <name>DATA2[%s]</name>
24274          <description>LCD Pin Data Registers</description>
24275          <addressOffset>0x300</addressOffset>
24276          <size>32</size>
24277          <access>read-write</access>
24278          <resetValue>0x0</resetValue>
24279          <resetMask>0xFFFFFFFF</resetMask>
24280          <fields>
24281            <field>
24282              <name>DATA</name>
24283              <description>Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb).</description>
24284              <bitRange>[31:0]</bitRange>
24285              <access>read-write</access>
24286            </field>
24287          </fields>
24288        </register>
24289        <register>
24290          <dim>8</dim>
24291          <dimIncrement>4</dimIncrement>
24292          <name>DATA3[%s]</name>
24293          <description>LCD Pin Data Registers</description>
24294          <addressOffset>0x400</addressOffset>
24295          <size>32</size>
24296          <access>read-write</access>
24297          <resetValue>0x0</resetValue>
24298          <resetMask>0xFFFFFFFF</resetMask>
24299          <fields>
24300            <field>
24301              <name>DATA</name>
24302              <description>Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb).</description>
24303              <bitRange>[31:0]</bitRange>
24304              <access>read-write</access>
24305            </field>
24306          </fields>
24307        </register>
24308      </registers>
24309    </peripheral>
24310    <peripheral>
24311      <name>USBFS0</name>
24312      <description>USB Host and Device Controller</description>
24313      <headerStructName>USBFS</headerStructName>
24314      <baseAddress>0x403F0000</baseAddress>
24315      <addressBlock>
24316        <offset>0</offset>
24317        <size>65536</size>
24318        <usage>registers</usage>
24319      </addressBlock>
24320      <registers>
24321        <cluster>
24322          <name>USBDEV</name>
24323          <description>USB Device</description>
24324          <addressOffset>0x00000000</addressOffset>
24325          <register>
24326            <dim>8</dim>
24327            <dimIncrement>4</dimIncrement>
24328            <name>EP0_DR[%s]</name>
24329            <description>Control End point EP0 Data Register</description>
24330            <addressOffset>0x0</addressOffset>
24331            <size>32</size>
24332            <access>read-write</access>
24333            <resetValue>0x0</resetValue>
24334            <resetMask>0xFF</resetMask>
24335            <fields>
24336              <field>
24337                <name>DATA_BYTE</name>
24338                <description>This register is shared for both transmit and receive. The count in the EP0_CNT register determines the number of bytes received or to be transferred.</description>
24339                <bitRange>[7:0]</bitRange>
24340                <access>read-write</access>
24341              </field>
24342            </fields>
24343          </register>
24344          <register>
24345            <name>CR0</name>
24346            <description>USB control 0 Register</description>
24347            <addressOffset>0x20</addressOffset>
24348            <size>32</size>
24349            <access>read-write</access>
24350            <resetValue>0x0</resetValue>
24351            <resetMask>0xFF</resetMask>
24352            <fields>
24353              <field>
24354                <name>DEVICE_ADDRESS</name>
24355                <description>These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware.
24356If USB bus reset is detected, these bits are initialized.</description>
24357                <bitRange>[6:0]</bitRange>
24358                <access>read-write</access>
24359              </field>
24360              <field>
24361                <name>USB_ENABLE</name>
24362                <description>This bit enables the device to respond to USB traffic.
24363If USB bus reset is detected, this bit is cleared.
24364Note:
24365When USB PHY is GPIO mode(USBIO_CR1.IOMODE=0), USB bus reset is detected. Therefore, when USB PHY is GPIO mode, this bit is cleared even if this bit is set to 1. If this bit is set to 1, write this bit upon USB bus reset interrupt, and do not write to this bit during initialization steps.</description>
24366                <bitRange>[7:7]</bitRange>
24367                <access>read-write</access>
24368              </field>
24369            </fields>
24370          </register>
24371          <register>
24372            <name>CR1</name>
24373            <description>USB control 1 Register</description>
24374            <addressOffset>0x24</addressOffset>
24375            <size>32</size>
24376            <access>read-write</access>
24377            <resetValue>0x0</resetValue>
24378            <resetMask>0xF</resetMask>
24379            <fields>
24380              <field>
24381                <name>REG_ENABLE</name>
24382                <description>This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply.</description>
24383                <bitRange>[0:0]</bitRange>
24384                <access>read-write</access>
24385              </field>
24386              <field>
24387                <name>ENABLE_LOCK</name>
24388                <description>This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic.  Unless an external clock is being provided this bit should remain set for proper USB operation.</description>
24389                <bitRange>[1:1]</bitRange>
24390                <access>read-write</access>
24391              </field>
24392              <field>
24393                <name>BUS_ACTIVITY</name>
24394                <description>The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High
24395value until firmware clears it.</description>
24396                <bitRange>[2:2]</bitRange>
24397                <access>read-write</access>
24398              </field>
24399              <field>
24400                <name>RSVD_3</name>
24401                <description>N/A</description>
24402                <bitRange>[3:3]</bitRange>
24403                <access>read-write</access>
24404              </field>
24405            </fields>
24406          </register>
24407          <register>
24408            <name>SIE_EP_INT_EN</name>
24409            <description>USB SIE Data Endpoints Interrupt Enable Register</description>
24410            <addressOffset>0x28</addressOffset>
24411            <size>32</size>
24412            <access>read-write</access>
24413            <resetValue>0x0</resetValue>
24414            <resetMask>0xFF</resetMask>
24415            <fields>
24416              <field>
24417                <name>EP1_INTR_EN</name>
24418                <description>Enables interrupt for EP1</description>
24419                <bitRange>[0:0]</bitRange>
24420                <access>read-write</access>
24421              </field>
24422              <field>
24423                <name>EP2_INTR_EN</name>
24424                <description>Enables interrupt for EP2</description>
24425                <bitRange>[1:1]</bitRange>
24426                <access>read-write</access>
24427              </field>
24428              <field>
24429                <name>EP3_INTR_EN</name>
24430                <description>Enables interrupt for EP3</description>
24431                <bitRange>[2:2]</bitRange>
24432                <access>read-write</access>
24433              </field>
24434              <field>
24435                <name>EP4_INTR_EN</name>
24436                <description>Enables interrupt for EP4</description>
24437                <bitRange>[3:3]</bitRange>
24438                <access>read-write</access>
24439              </field>
24440              <field>
24441                <name>EP5_INTR_EN</name>
24442                <description>Enables interrupt for EP5</description>
24443                <bitRange>[4:4]</bitRange>
24444                <access>read-write</access>
24445              </field>
24446              <field>
24447                <name>EP6_INTR_EN</name>
24448                <description>Enables interrupt for EP6</description>
24449                <bitRange>[5:5]</bitRange>
24450                <access>read-write</access>
24451              </field>
24452              <field>
24453                <name>EP7_INTR_EN</name>
24454                <description>Enables interrupt for EP7</description>
24455                <bitRange>[6:6]</bitRange>
24456                <access>read-write</access>
24457              </field>
24458              <field>
24459                <name>EP8_INTR_EN</name>
24460                <description>Enables interrupt for EP8</description>
24461                <bitRange>[7:7]</bitRange>
24462                <access>read-write</access>
24463              </field>
24464            </fields>
24465          </register>
24466          <register>
24467            <name>SIE_EP_INT_SR</name>
24468            <description>USB SIE Data Endpoint Interrupt Status</description>
24469            <addressOffset>0x2C</addressOffset>
24470            <size>32</size>
24471            <access>read-write</access>
24472            <resetValue>0x0</resetValue>
24473            <resetMask>0xFF</resetMask>
24474            <fields>
24475              <field>
24476                <name>EP1_INTR</name>
24477                <description>Interrupt status for EP1</description>
24478                <bitRange>[0:0]</bitRange>
24479                <access>read-write</access>
24480              </field>
24481              <field>
24482                <name>EP2_INTR</name>
24483                <description>Interrupt status for EP2</description>
24484                <bitRange>[1:1]</bitRange>
24485                <access>read-write</access>
24486              </field>
24487              <field>
24488                <name>EP3_INTR</name>
24489                <description>Interrupt status for EP3</description>
24490                <bitRange>[2:2]</bitRange>
24491                <access>read-write</access>
24492              </field>
24493              <field>
24494                <name>EP4_INTR</name>
24495                <description>Interrupt status for EP4</description>
24496                <bitRange>[3:3]</bitRange>
24497                <access>read-write</access>
24498              </field>
24499              <field>
24500                <name>EP5_INTR</name>
24501                <description>Interrupt status for EP5</description>
24502                <bitRange>[4:4]</bitRange>
24503                <access>read-write</access>
24504              </field>
24505              <field>
24506                <name>EP6_INTR</name>
24507                <description>Interrupt status for EP6</description>
24508                <bitRange>[5:5]</bitRange>
24509                <access>read-write</access>
24510              </field>
24511              <field>
24512                <name>EP7_INTR</name>
24513                <description>Interrupt status for EP7</description>
24514                <bitRange>[6:6]</bitRange>
24515                <access>read-write</access>
24516              </field>
24517              <field>
24518                <name>EP8_INTR</name>
24519                <description>Interrupt status for EP8</description>
24520                <bitRange>[7:7]</bitRange>
24521                <access>read-write</access>
24522              </field>
24523            </fields>
24524          </register>
24525          <register>
24526            <name>SIE_EP1_CNT0</name>
24527            <description>Non-control endpoint count register</description>
24528            <addressOffset>0x30</addressOffset>
24529            <size>32</size>
24530            <access>read-write</access>
24531            <resetValue>0x0</resetValue>
24532            <resetMask>0xC7</resetMask>
24533            <fields>
24534              <field>
24535                <name>DATA_COUNT_MSB</name>
24536                <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
24537                <bitRange>[2:0]</bitRange>
24538                <access>read-write</access>
24539              </field>
24540              <field>
24541                <name>DATA_VALID</name>
24542                <description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
24543                <bitRange>[6:6]</bitRange>
24544                <access>read-write</access>
24545                <enumeratedValues>
24546                  <enumeratedValue>
24547                    <name>DATA_ERROR</name>
24548                    <description>No ACK'd transactions since bit was last cleared.</description>
24549                    <value>0</value>
24550                  </enumeratedValue>
24551                  <enumeratedValue>
24552                    <name>DATA_VALID</name>
24553                    <description>Indicates a transaction ended with an ACK.</description>
24554                    <value>1</value>
24555                  </enumeratedValue>
24556                </enumeratedValues>
24557              </field>
24558              <field>
24559                <name>DATA_TOGGLE</name>
24560                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
24561                <bitRange>[7:7]</bitRange>
24562                <access>read-write</access>
24563              </field>
24564            </fields>
24565          </register>
24566          <register>
24567            <name>SIE_EP1_CNT1</name>
24568            <description>Non-control endpoint count register</description>
24569            <addressOffset>0x34</addressOffset>
24570            <size>32</size>
24571            <access>read-write</access>
24572            <resetValue>0x0</resetValue>
24573            <resetMask>0xFF</resetMask>
24574            <fields>
24575              <field>
24576                <name>DATA_COUNT</name>
24577                <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
24578                <bitRange>[7:0]</bitRange>
24579                <access>read-write</access>
24580              </field>
24581            </fields>
24582          </register>
24583          <register>
24584            <name>SIE_EP1_CR0</name>
24585            <description>Non-control endpoint's control Register</description>
24586            <addressOffset>0x38</addressOffset>
24587            <size>32</size>
24588            <access>read-write</access>
24589            <resetValue>0x0</resetValue>
24590            <resetMask>0xFF</resetMask>
24591            <fields>
24592              <field>
24593                <name>MODE</name>
24594                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
24595                <bitRange>[3:0]</bitRange>
24596                <access>read-write</access>
24597                <enumeratedValues>
24598                  <enumeratedValue>
24599                    <name>DISABLE</name>
24600                    <description>Ignore all USB traffic to this endpoint</description>
24601                    <value>0</value>
24602                  </enumeratedValue>
24603                  <enumeratedValue>
24604                    <name>NAK_INOUT</name>
24605                    <description>SETUP: Accept
24606IN: NAK
24607OUT:  NAK</description>
24608                    <value>1</value>
24609                  </enumeratedValue>
24610                  <enumeratedValue>
24611                    <name>STATUS_OUT_ONLY</name>
24612                    <description>SETUP: Accept
24613IN: STALL
24614OUT:  ACK 0B tokens, NAK others</description>
24615                    <value>2</value>
24616                  </enumeratedValue>
24617                  <enumeratedValue>
24618                    <name>STALL_INOUT</name>
24619                    <description>SETUP: Accept
24620IN: STALL
24621OUT:  STALL</description>
24622                    <value>3</value>
24623                  </enumeratedValue>
24624                  <enumeratedValue>
24625                    <name>ISO_OUT</name>
24626                    <description>SETUP: Ignore
24627IN: Ignore
24628OUT:  Accept Isochronous OUT token</description>
24629                    <value>5</value>
24630                  </enumeratedValue>
24631                  <enumeratedValue>
24632                    <name>STATUS_IN_ONLY</name>
24633                    <description>SETUP: Accept
24634IN: Respond with 0B data
24635OUT:  Stall</description>
24636                    <value>6</value>
24637                  </enumeratedValue>
24638                  <enumeratedValue>
24639                    <name>ISO_IN</name>
24640                    <description>SETUP: Ignore
24641IN: Accept Isochronous IN token
24642OUT:  Ignore</description>
24643                    <value>7</value>
24644                  </enumeratedValue>
24645                  <enumeratedValue>
24646                    <name>NAK_OUT</name>
24647                    <description>SETUP: Ignore
24648IN: Ignore
24649OUT:  NAK</description>
24650                    <value>8</value>
24651                  </enumeratedValue>
24652                  <enumeratedValue>
24653                    <name>ACK_OUT</name>
24654                    <description>SETUP: Ignore
24655IN: Ignore
24656OUT:  Accept data and ACK if STALL=0, STALL otherwise.
24657Change to MODE=8 after one succesfull OUT token.</description>
24658                    <value>9</value>
24659                  </enumeratedValue>
24660                  <enumeratedValue>
24661                    <name>ACK_OUT_STATUS_IN</name>
24662                    <description>SETUP: Accept
24663IN: Respond with 0B data
24664OUT:  Accept data</description>
24665                    <value>11</value>
24666                  </enumeratedValue>
24667                  <enumeratedValue>
24668                    <name>NAK_IN</name>
24669                    <description>SETUP: Ignore
24670IN: NAK
24671OUT:  Ignore</description>
24672                    <value>12</value>
24673                  </enumeratedValue>
24674                  <enumeratedValue>
24675                    <name>ACK_IN</name>
24676                    <description>SETUP: Ignore
24677IN: Respond to IN with data if STALL=0, STALL otherwise
24678OUT:  Ignore</description>
24679                    <value>13</value>
24680                  </enumeratedValue>
24681                  <enumeratedValue>
24682                    <name>ACK_IN_STATUS_OUT</name>
24683                    <description>SETUP: Accept
24684IN: Respond to IN with data
24685OUT:  ACK 0B tokens, NAK others</description>
24686                    <value>15</value>
24687                  </enumeratedValue>
24688                </enumeratedValues>
24689              </field>
24690              <field>
24691                <name>ACKED_TXN</name>
24692                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
24693                <bitRange>[4:4]</bitRange>
24694                <access>read-write</access>
24695                <enumeratedValues>
24696                  <enumeratedValue>
24697                    <name>ACKED_NO</name>
24698                    <description>No ACK'd transactions since bit was last cleared.</description>
24699                    <value>0</value>
24700                  </enumeratedValue>
24701                  <enumeratedValue>
24702                    <name>ACKED_YES</name>
24703                    <description>Indicates a transaction ended with an ACK.</description>
24704                    <value>1</value>
24705                  </enumeratedValue>
24706                </enumeratedValues>
24707              </field>
24708              <field>
24709                <name>NAK_INT_EN</name>
24710                <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
24711                <bitRange>[5:5]</bitRange>
24712                <access>read-write</access>
24713              </field>
24714              <field>
24715                <name>ERR_IN_TXN</name>
24716                <description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
24717error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
24718                <bitRange>[6:6]</bitRange>
24719                <access>read-write</access>
24720              </field>
24721              <field>
24722                <name>STALL</name>
24723                <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
24724                <bitRange>[7:7]</bitRange>
24725                <access>read-write</access>
24726              </field>
24727            </fields>
24728          </register>
24729          <register>
24730            <name>USBIO_CR0</name>
24731            <description>USBIO Control 0 Register</description>
24732            <addressOffset>0x40</addressOffset>
24733            <size>32</size>
24734            <access>read-write</access>
24735            <resetValue>0x0</resetValue>
24736            <resetMask>0xE0</resetMask>
24737            <fields>
24738              <field>
24739                <name>RD</name>
24740                <description>Received Data. This read only bit gives the state of the USB differential receiver when IOMODE bit is '0'  and USB doesn't transmit. This bit is valid if USB Device.
24741If D+=D- (SE0), this value is undefined.</description>
24742                <bitRange>[0:0]</bitRange>
24743                <access>read-only</access>
24744                <enumeratedValues>
24745                  <enumeratedValue>
24746                    <name>DIFF_LOW</name>
24747                    <description>D+ &lt; D- (K state)</description>
24748                    <value>0</value>
24749                  </enumeratedValue>
24750                  <enumeratedValue>
24751                    <name>DIFF_HIGH</name>
24752                    <description>D+ &gt; D- (J state)</description>
24753                    <value>1</value>
24754                  </enumeratedValue>
24755                </enumeratedValues>
24756              </field>
24757              <field>
24758                <name>TD</name>
24759                <description>Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1.</description>
24760                <bitRange>[5:5]</bitRange>
24761                <access>read-write</access>
24762                <enumeratedValues>
24763                  <enumeratedValue>
24764                    <name>DIFF_K</name>
24765                    <description>Force USB K state (D+ is low D- is high).</description>
24766                    <value>0</value>
24767                  </enumeratedValue>
24768                  <enumeratedValue>
24769                    <name>DIFF_J</name>
24770                    <description>Force USB J state (D+ is high D- is low).</description>
24771                    <value>1</value>
24772                  </enumeratedValue>
24773                </enumeratedValues>
24774              </field>
24775              <field>
24776                <name>TSE0</name>
24777                <description>Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0.</description>
24778                <bitRange>[6:6]</bitRange>
24779                <access>read-write</access>
24780              </field>
24781              <field>
24782                <name>TEN</name>
24783                <description>USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually
24784transmitting is to force a resume state on the bus.</description>
24785                <bitRange>[7:7]</bitRange>
24786                <access>read-write</access>
24787              </field>
24788            </fields>
24789          </register>
24790          <register>
24791            <name>USBIO_CR2</name>
24792            <description>USBIO control 2 Register</description>
24793            <addressOffset>0x44</addressOffset>
24794            <size>32</size>
24795            <access>read-write</access>
24796            <resetValue>0x0</resetValue>
24797            <resetMask>0xFF</resetMask>
24798            <fields>
24799              <field>
24800                <name>RSVD_5_0</name>
24801                <description>N/A</description>
24802                <bitRange>[5:0]</bitRange>
24803                <access>read-only</access>
24804              </field>
24805              <field>
24806                <name>TEST_PKT</name>
24807                <description>This bit enables the device to transmit a packet in response to an internally generated IN packet.  When set, one packet will be generated.</description>
24808                <bitRange>[6:6]</bitRange>
24809                <access>read-write</access>
24810              </field>
24811              <field>
24812                <name>RSVD_7</name>
24813                <description>N/A</description>
24814                <bitRange>[7:7]</bitRange>
24815                <access>read-write</access>
24816              </field>
24817            </fields>
24818          </register>
24819          <register>
24820            <name>USBIO_CR1</name>
24821            <description>USBIO control 1 Register</description>
24822            <addressOffset>0x48</addressOffset>
24823            <size>32</size>
24824            <access>read-write</access>
24825            <resetValue>0x20</resetValue>
24826            <resetMask>0x20</resetMask>
24827            <fields>
24828              <field>
24829                <name>DMO</name>
24830                <description>This read only bit gives the state of the D- pin when IOMODE bit is '0'  and USB doesn't transmit.
24831This bit is '0' when USB transmits SE0, and this bit is '1' when USB transmits other than SE0.
24832This bit is valid if USB Device.</description>
24833                <bitRange>[0:0]</bitRange>
24834                <access>read-only</access>
24835              </field>
24836              <field>
24837                <name>DPO</name>
24838                <description>This read only bit gives the state of the D+ pin when IOMODE bit is '0' and USB doesn't transmit.
24839This bit displays the output value of D+ pin when USB transmits SE0 or data.
24840This bit is valid if USB Device.</description>
24841                <bitRange>[1:1]</bitRange>
24842                <access>read-only</access>
24843              </field>
24844              <field>
24845                <name>RSVD_2</name>
24846                <description>N/A</description>
24847                <bitRange>[2:2]</bitRange>
24848                <access>read-write</access>
24849              </field>
24850              <field>
24851                <name>IOMODE</name>
24852                <description>This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins.</description>
24853                <bitRange>[5:5]</bitRange>
24854                <access>read-write</access>
24855              </field>
24856            </fields>
24857          </register>
24858          <register>
24859            <name>DYN_RECONFIG</name>
24860            <description>USB Dynamic reconfiguration register</description>
24861            <addressOffset>0x50</addressOffset>
24862            <size>32</size>
24863            <access>read-write</access>
24864            <resetValue>0x0</resetValue>
24865            <resetMask>0x1F</resetMask>
24866            <fields>
24867              <field>
24868                <name>DYN_CONFIG_EN</name>
24869                <description>This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP.
24870Use 0 for EP1, 1 for EP2, etc.</description>
24871                <bitRange>[0:0]</bitRange>
24872                <access>read-write</access>
24873              </field>
24874              <field>
24875                <name>DYN_RECONFIG_EPNO</name>
24876                <description>These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1.</description>
24877                <bitRange>[3:1]</bitRange>
24878                <access>read-write</access>
24879              </field>
24880              <field>
24881                <name>DYN_RECONFIG_RDY_STS</name>
24882                <description>This bit indicates the ready status for the dynamic reconfiguration, when set to 1, indicates the block is ready for reconfiguration.</description>
24883                <bitRange>[4:4]</bitRange>
24884                <access>read-only</access>
24885              </field>
24886            </fields>
24887          </register>
24888          <register>
24889            <name>SOF0</name>
24890            <description>Start Of Frame Register</description>
24891            <addressOffset>0x60</addressOffset>
24892            <size>32</size>
24893            <access>read-only</access>
24894            <resetValue>0x0</resetValue>
24895            <resetMask>0xFF</resetMask>
24896            <fields>
24897              <field>
24898                <name>FRAME_NUMBER</name>
24899                <description>It has the lower 8 bits [7:0] of the SOF frame number.</description>
24900                <bitRange>[7:0]</bitRange>
24901                <access>read-only</access>
24902              </field>
24903            </fields>
24904          </register>
24905          <register>
24906            <name>SOF1</name>
24907            <description>Start Of Frame Register</description>
24908            <addressOffset>0x64</addressOffset>
24909            <size>32</size>
24910            <access>read-only</access>
24911            <resetValue>0x0</resetValue>
24912            <resetMask>0x7</resetMask>
24913            <fields>
24914              <field>
24915                <name>FRAME_NUMBER_MSB</name>
24916                <description>It has the upper 3 bits [10:8] of the SOF frame number.</description>
24917                <bitRange>[2:0]</bitRange>
24918                <access>read-only</access>
24919              </field>
24920            </fields>
24921          </register>
24922          <register>
24923            <name>SIE_EP2_CNT0</name>
24924            <description>Non-control endpoint count register</description>
24925            <addressOffset>0x70</addressOffset>
24926            <size>32</size>
24927            <access>read-write</access>
24928            <resetValue>0x0</resetValue>
24929            <resetMask>0xC7</resetMask>
24930            <fields>
24931              <field>
24932                <name>DATA_COUNT_MSB</name>
24933                <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
24934                <bitRange>[2:0]</bitRange>
24935                <access>read-write</access>
24936              </field>
24937              <field>
24938                <name>DATA_VALID</name>
24939                <description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
24940                <bitRange>[6:6]</bitRange>
24941                <access>read-write</access>
24942                <enumeratedValues>
24943                  <enumeratedValue>
24944                    <name>DATA_ERROR</name>
24945                    <description>No ACK'd transactions since bit was last cleared.</description>
24946                    <value>0</value>
24947                  </enumeratedValue>
24948                  <enumeratedValue>
24949                    <name>DATA_VALID</name>
24950                    <description>Indicates a transaction ended with an ACK.</description>
24951                    <value>1</value>
24952                  </enumeratedValue>
24953                </enumeratedValues>
24954              </field>
24955              <field>
24956                <name>DATA_TOGGLE</name>
24957                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
24958                <bitRange>[7:7]</bitRange>
24959                <access>read-write</access>
24960              </field>
24961            </fields>
24962          </register>
24963          <register>
24964            <name>SIE_EP2_CNT1</name>
24965            <description>Non-control endpoint count register</description>
24966            <addressOffset>0x74</addressOffset>
24967            <size>32</size>
24968            <access>read-write</access>
24969            <resetValue>0x0</resetValue>
24970            <resetMask>0xFF</resetMask>
24971            <fields>
24972              <field>
24973                <name>DATA_COUNT</name>
24974                <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
24975                <bitRange>[7:0]</bitRange>
24976                <access>read-write</access>
24977              </field>
24978            </fields>
24979          </register>
24980          <register>
24981            <name>SIE_EP2_CR0</name>
24982            <description>Non-control endpoint's control Register</description>
24983            <addressOffset>0x78</addressOffset>
24984            <size>32</size>
24985            <access>read-write</access>
24986            <resetValue>0x0</resetValue>
24987            <resetMask>0xFF</resetMask>
24988            <fields>
24989              <field>
24990                <name>MODE</name>
24991                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
24992                <bitRange>[3:0]</bitRange>
24993                <access>read-write</access>
24994                <enumeratedValues>
24995                  <enumeratedValue>
24996                    <name>DISABLE</name>
24997                    <description>Ignore all USB traffic to this endpoint</description>
24998                    <value>0</value>
24999                  </enumeratedValue>
25000                  <enumeratedValue>
25001                    <name>NAK_INOUT</name>
25002                    <description>SETUP: Accept
25003IN: NAK
25004OUT:  NAK</description>
25005                    <value>1</value>
25006                  </enumeratedValue>
25007                  <enumeratedValue>
25008                    <name>STATUS_OUT_ONLY</name>
25009                    <description>SETUP: Accept
25010IN: STALL
25011OUT:  ACK 0B tokens, NAK others</description>
25012                    <value>2</value>
25013                  </enumeratedValue>
25014                  <enumeratedValue>
25015                    <name>STALL_INOUT</name>
25016                    <description>SETUP: Accept
25017IN: STALL
25018OUT:  STALL</description>
25019                    <value>3</value>
25020                  </enumeratedValue>
25021                  <enumeratedValue>
25022                    <name>ISO_OUT</name>
25023                    <description>SETUP: Ignore
25024IN: Ignore
25025OUT:  Accept Isochronous OUT token</description>
25026                    <value>5</value>
25027                  </enumeratedValue>
25028                  <enumeratedValue>
25029                    <name>STATUS_IN_ONLY</name>
25030                    <description>SETUP: Accept
25031IN: Respond with 0B data
25032OUT:  Stall</description>
25033                    <value>6</value>
25034                  </enumeratedValue>
25035                  <enumeratedValue>
25036                    <name>ISO_IN</name>
25037                    <description>SETUP: Ignore
25038IN: Accept Isochronous IN token
25039OUT:  Ignore</description>
25040                    <value>7</value>
25041                  </enumeratedValue>
25042                  <enumeratedValue>
25043                    <name>NAK_OUT</name>
25044                    <description>SETUP: Ignore
25045IN: Ignore
25046OUT:  NAK</description>
25047                    <value>8</value>
25048                  </enumeratedValue>
25049                  <enumeratedValue>
25050                    <name>ACK_OUT</name>
25051                    <description>SETUP: Ignore
25052IN: Ignore
25053OUT:  Accept data and ACK if STALL=0, STALL otherwise.
25054Change to MODE=8 after one succesfull OUT token.</description>
25055                    <value>9</value>
25056                  </enumeratedValue>
25057                  <enumeratedValue>
25058                    <name>ACK_OUT_STATUS_IN</name>
25059                    <description>SETUP: Accept
25060IN: Respond with 0B data
25061OUT:  Accept data</description>
25062                    <value>11</value>
25063                  </enumeratedValue>
25064                  <enumeratedValue>
25065                    <name>NAK_IN</name>
25066                    <description>SETUP: Ignore
25067IN: NAK
25068OUT:  Ignore</description>
25069                    <value>12</value>
25070                  </enumeratedValue>
25071                  <enumeratedValue>
25072                    <name>ACK_IN</name>
25073                    <description>SETUP: Ignore
25074IN: Respond to IN with data if STALL=0, STALL otherwise
25075OUT:  Ignore</description>
25076                    <value>13</value>
25077                  </enumeratedValue>
25078                  <enumeratedValue>
25079                    <name>ACK_IN_STATUS_OUT</name>
25080                    <description>SETUP: Accept
25081IN: Respond to IN with data
25082OUT:  ACK 0B tokens, NAK others</description>
25083                    <value>15</value>
25084                  </enumeratedValue>
25085                </enumeratedValues>
25086              </field>
25087              <field>
25088                <name>ACKED_TXN</name>
25089                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
25090                <bitRange>[4:4]</bitRange>
25091                <access>read-write</access>
25092                <enumeratedValues>
25093                  <enumeratedValue>
25094                    <name>ACKED_NO</name>
25095                    <description>No ACK'd transactions since bit was last cleared.</description>
25096                    <value>0</value>
25097                  </enumeratedValue>
25098                  <enumeratedValue>
25099                    <name>ACKED_YES</name>
25100                    <description>Indicates a transaction ended with an ACK.</description>
25101                    <value>1</value>
25102                  </enumeratedValue>
25103                </enumeratedValues>
25104              </field>
25105              <field>
25106                <name>NAK_INT_EN</name>
25107                <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
25108                <bitRange>[5:5]</bitRange>
25109                <access>read-write</access>
25110              </field>
25111              <field>
25112                <name>ERR_IN_TXN</name>
25113                <description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
25114error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
25115                <bitRange>[6:6]</bitRange>
25116                <access>read-write</access>
25117              </field>
25118              <field>
25119                <name>STALL</name>
25120                <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
25121                <bitRange>[7:7]</bitRange>
25122                <access>read-write</access>
25123              </field>
25124            </fields>
25125          </register>
25126          <register>
25127            <name>OSCLK_DR0</name>
25128            <description>Oscillator lock data register 0</description>
25129            <addressOffset>0x80</addressOffset>
25130            <size>32</size>
25131            <access>read-only</access>
25132            <resetValue>0x0</resetValue>
25133            <resetMask>0x0</resetMask>
25134            <fields>
25135              <field>
25136                <name>ADDER</name>
25137                <description>These bits return the lower 8 bits of the oscillator locking circuits adder output.</description>
25138                <bitRange>[7:0]</bitRange>
25139                <access>read-only</access>
25140              </field>
25141            </fields>
25142          </register>
25143          <register>
25144            <name>OSCLK_DR1</name>
25145            <description>Oscillator lock data register 1</description>
25146            <addressOffset>0x84</addressOffset>
25147            <size>32</size>
25148            <access>read-only</access>
25149            <resetValue>0x0</resetValue>
25150            <resetMask>0x0</resetMask>
25151            <fields>
25152              <field>
25153                <name>ADDER_MSB</name>
25154                <description>These bits return the upper 7 bits of the oscillator locking circuits adder output.</description>
25155                <bitRange>[6:0]</bitRange>
25156                <access>read-only</access>
25157              </field>
25158            </fields>
25159          </register>
25160          <register>
25161            <name>EP0_CR</name>
25162            <description>Endpoint0 control Register</description>
25163            <addressOffset>0xA0</addressOffset>
25164            <size>32</size>
25165            <access>read-write</access>
25166            <resetValue>0x0</resetValue>
25167            <resetMask>0xFF</resetMask>
25168            <fields>
25169              <field>
25170                <name>MODE</name>
25171                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
25172                <bitRange>[3:0]</bitRange>
25173                <access>read-write</access>
25174                <enumeratedValues>
25175                  <enumeratedValue>
25176                    <name>DISABLE</name>
25177                    <description>Ignore all USB traffic to this endpoint</description>
25178                    <value>0</value>
25179                  </enumeratedValue>
25180                  <enumeratedValue>
25181                    <name>NAK_INOUT</name>
25182                    <description>SETUP: Accept
25183IN: NAK
25184OUT:  NAK</description>
25185                    <value>1</value>
25186                  </enumeratedValue>
25187                  <enumeratedValue>
25188                    <name>STATUS_OUT_ONLY</name>
25189                    <description>SETUP: Accept
25190IN: STALL
25191OUT:  ACK 0B tokens, NAK others</description>
25192                    <value>2</value>
25193                  </enumeratedValue>
25194                  <enumeratedValue>
25195                    <name>STALL_INOUT</name>
25196                    <description>SETUP: Accept
25197IN: STALL
25198OUT:  STALL</description>
25199                    <value>3</value>
25200                  </enumeratedValue>
25201                  <enumeratedValue>
25202                    <name>ISO_OUT</name>
25203                    <description>SETUP: Ignore
25204IN: Ignore
25205OUT:  Accept Isochronous OUT token</description>
25206                    <value>5</value>
25207                  </enumeratedValue>
25208                  <enumeratedValue>
25209                    <name>STATUS_IN_ONLY</name>
25210                    <description>SETUP: Accept
25211IN: Respond with 0B data
25212OUT:  Stall</description>
25213                    <value>6</value>
25214                  </enumeratedValue>
25215                  <enumeratedValue>
25216                    <name>ISO_IN</name>
25217                    <description>SETUP: Ignore
25218IN: Accept Isochronous IN token
25219OUT:  Ignore</description>
25220                    <value>7</value>
25221                  </enumeratedValue>
25222                  <enumeratedValue>
25223                    <name>NAK_OUT</name>
25224                    <description>SETUP: Ignore
25225IN: Ignore
25226OUT:  NAK</description>
25227                    <value>8</value>
25228                  </enumeratedValue>
25229                  <enumeratedValue>
25230                    <name>ACK_OUT</name>
25231                    <description>SETUP: Ignore
25232IN: Ignore
25233OUT:  Accept data and ACK if STALL=0, STALL otherwise.
25234Change to MODE=8 after one succesfull OUT token.</description>
25235                    <value>9</value>
25236                  </enumeratedValue>
25237                  <enumeratedValue>
25238                    <name>ACK_OUT_STATUS_IN</name>
25239                    <description>SETUP: Accept
25240IN: Respond with 0B data
25241OUT:  Accept data</description>
25242                    <value>11</value>
25243                  </enumeratedValue>
25244                  <enumeratedValue>
25245                    <name>NAK_IN</name>
25246                    <description>SETUP: Ignore
25247IN: NAK
25248OUT:  Ignore</description>
25249                    <value>12</value>
25250                  </enumeratedValue>
25251                  <enumeratedValue>
25252                    <name>ACK_IN</name>
25253                    <description>SETUP: Ignore
25254IN: Respond to IN with data if STALL=0, STALL otherwise
25255OUT:  Ignore</description>
25256                    <value>13</value>
25257                  </enumeratedValue>
25258                  <enumeratedValue>
25259                    <name>ACK_IN_STATUS_OUT</name>
25260                    <description>SETUP: Accept
25261IN: Respond to IN with data
25262OUT:  ACK 0B tokens, NAK others</description>
25263                    <value>15</value>
25264                  </enumeratedValue>
25265                </enumeratedValues>
25266              </field>
25267              <field>
25268                <name>ACKED_TXN</name>
25269                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
25270                <bitRange>[4:4]</bitRange>
25271                <access>read-write</access>
25272                <enumeratedValues>
25273                  <enumeratedValue>
25274                    <name>ACKED_NO</name>
25275                    <description>No ACK'd transactions since bit was last cleared.</description>
25276                    <value>0</value>
25277                  </enumeratedValue>
25278                  <enumeratedValue>
25279                    <name>ACKED_YES</name>
25280                    <description>Indicates a transaction ended with an ACK.</description>
25281                    <value>1</value>
25282                  </enumeratedValue>
25283                </enumeratedValues>
25284              </field>
25285              <field>
25286                <name>OUT_RCVD</name>
25287                <description>When set this bit indicates a valid OUT packet has been received and ACKed. This bit is updated to '1' after the last received packet in an OUT transaction. When clear this bit indicates no OUT received. It is cleared by any writes to the register.</description>
25288                <bitRange>[5:5]</bitRange>
25289                <access>read-write</access>
25290              </field>
25291              <field>
25292                <name>IN_RCVD</name>
25293                <description>When set this bit indicates a valid IN packet has been received. This bit is updated to '1' after the host acknowledges an IN data packet. When clear this bit indicates either no IN has been received or that the host did not acknowledge the IN data by sending ACK handshake. It is cleared by any writes to the register.</description>
25294                <bitRange>[6:6]</bitRange>
25295                <access>read-write</access>
25296              </field>
25297              <field>
25298                <name>SETUP_RCVD</name>
25299                <description>When set this bit indicates a valid SETUP packet was received and ACKed. This bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval. After this interval the bit will remain set until cleared by firmware. While this bit is set to '1' the CPU cannot write to the EP0_DRx registers. This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data. This bit is cleared by any non-locked writes to the register.</description>
25300                <bitRange>[7:7]</bitRange>
25301                <access>read-write</access>
25302              </field>
25303            </fields>
25304          </register>
25305          <register>
25306            <name>EP0_CNT</name>
25307            <description>Endpoint0 count Register</description>
25308            <addressOffset>0xA4</addressOffset>
25309            <size>32</size>
25310            <access>read-write</access>
25311            <resetValue>0x0</resetValue>
25312            <resetMask>0xCF</resetMask>
25313            <fields>
25314              <field>
25315                <name>BYTE_COUNT</name>
25316                <description>These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10.</description>
25317                <bitRange>[3:0]</bitRange>
25318                <access>read-write</access>
25319              </field>
25320              <field>
25321                <name>DATA_VALID</name>
25322                <description>This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
25323                <bitRange>[6:6]</bitRange>
25324                <access>read-write</access>
25325                <enumeratedValues>
25326                  <enumeratedValue>
25327                    <name>DATA_ERROR</name>
25328                    <description>No ACK'd transactions since bit was last cleared.</description>
25329                    <value>0</value>
25330                  </enumeratedValue>
25331                  <enumeratedValue>
25332                    <name>DATA_VALID</name>
25333                    <description>Indicates a transaction ended with an ACK.</description>
25334                    <value>1</value>
25335                  </enumeratedValue>
25336                </enumeratedValues>
25337              </field>
25338              <field>
25339                <name>DATA_TOGGLE</name>
25340                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
25341                <bitRange>[7:7]</bitRange>
25342                <access>read-write</access>
25343              </field>
25344            </fields>
25345          </register>
25346          <register>
25347            <name>SIE_EP3_CNT0</name>
25348            <description>Non-control endpoint count register</description>
25349            <addressOffset>0xB0</addressOffset>
25350            <size>32</size>
25351            <access>read-write</access>
25352            <resetValue>0x0</resetValue>
25353            <resetMask>0xC7</resetMask>
25354            <fields>
25355              <field>
25356                <name>DATA_COUNT_MSB</name>
25357                <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
25358                <bitRange>[2:0]</bitRange>
25359                <access>read-write</access>
25360              </field>
25361              <field>
25362                <name>DATA_VALID</name>
25363                <description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
25364                <bitRange>[6:6]</bitRange>
25365                <access>read-write</access>
25366                <enumeratedValues>
25367                  <enumeratedValue>
25368                    <name>DATA_ERROR</name>
25369                    <description>No ACK'd transactions since bit was last cleared.</description>
25370                    <value>0</value>
25371                  </enumeratedValue>
25372                  <enumeratedValue>
25373                    <name>DATA_VALID</name>
25374                    <description>Indicates a transaction ended with an ACK.</description>
25375                    <value>1</value>
25376                  </enumeratedValue>
25377                </enumeratedValues>
25378              </field>
25379              <field>
25380                <name>DATA_TOGGLE</name>
25381                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
25382                <bitRange>[7:7]</bitRange>
25383                <access>read-write</access>
25384              </field>
25385            </fields>
25386          </register>
25387          <register>
25388            <name>SIE_EP3_CNT1</name>
25389            <description>Non-control endpoint count register</description>
25390            <addressOffset>0xB4</addressOffset>
25391            <size>32</size>
25392            <access>read-write</access>
25393            <resetValue>0x0</resetValue>
25394            <resetMask>0xFF</resetMask>
25395            <fields>
25396              <field>
25397                <name>DATA_COUNT</name>
25398                <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
25399                <bitRange>[7:0]</bitRange>
25400                <access>read-write</access>
25401              </field>
25402            </fields>
25403          </register>
25404          <register>
25405            <name>SIE_EP3_CR0</name>
25406            <description>Non-control endpoint's control Register</description>
25407            <addressOffset>0xB8</addressOffset>
25408            <size>32</size>
25409            <access>read-write</access>
25410            <resetValue>0x0</resetValue>
25411            <resetMask>0xFF</resetMask>
25412            <fields>
25413              <field>
25414                <name>MODE</name>
25415                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
25416                <bitRange>[3:0]</bitRange>
25417                <access>read-write</access>
25418                <enumeratedValues>
25419                  <enumeratedValue>
25420                    <name>DISABLE</name>
25421                    <description>Ignore all USB traffic to this endpoint</description>
25422                    <value>0</value>
25423                  </enumeratedValue>
25424                  <enumeratedValue>
25425                    <name>NAK_INOUT</name>
25426                    <description>SETUP: Accept
25427IN: NAK
25428OUT:  NAK</description>
25429                    <value>1</value>
25430                  </enumeratedValue>
25431                  <enumeratedValue>
25432                    <name>STATUS_OUT_ONLY</name>
25433                    <description>SETUP: Accept
25434IN: STALL
25435OUT:  ACK 0B tokens, NAK others</description>
25436                    <value>2</value>
25437                  </enumeratedValue>
25438                  <enumeratedValue>
25439                    <name>STALL_INOUT</name>
25440                    <description>SETUP: Accept
25441IN: STALL
25442OUT:  STALL</description>
25443                    <value>3</value>
25444                  </enumeratedValue>
25445                  <enumeratedValue>
25446                    <name>ISO_OUT</name>
25447                    <description>SETUP: Ignore
25448IN: Ignore
25449OUT:  Accept Isochronous OUT token</description>
25450                    <value>5</value>
25451                  </enumeratedValue>
25452                  <enumeratedValue>
25453                    <name>STATUS_IN_ONLY</name>
25454                    <description>SETUP: Accept
25455IN: Respond with 0B data
25456OUT:  Stall</description>
25457                    <value>6</value>
25458                  </enumeratedValue>
25459                  <enumeratedValue>
25460                    <name>ISO_IN</name>
25461                    <description>SETUP: Ignore
25462IN: Accept Isochronous IN token
25463OUT:  Ignore</description>
25464                    <value>7</value>
25465                  </enumeratedValue>
25466                  <enumeratedValue>
25467                    <name>NAK_OUT</name>
25468                    <description>SETUP: Ignore
25469IN: Ignore
25470OUT:  NAK</description>
25471                    <value>8</value>
25472                  </enumeratedValue>
25473                  <enumeratedValue>
25474                    <name>ACK_OUT</name>
25475                    <description>SETUP: Ignore
25476IN: Ignore
25477OUT:  Accept data and ACK if STALL=0, STALL otherwise.
25478Change to MODE=8 after one succesfull OUT token.</description>
25479                    <value>9</value>
25480                  </enumeratedValue>
25481                  <enumeratedValue>
25482                    <name>ACK_OUT_STATUS_IN</name>
25483                    <description>SETUP: Accept
25484IN: Respond with 0B data
25485OUT:  Accept data</description>
25486                    <value>11</value>
25487                  </enumeratedValue>
25488                  <enumeratedValue>
25489                    <name>NAK_IN</name>
25490                    <description>SETUP: Ignore
25491IN: NAK
25492OUT:  Ignore</description>
25493                    <value>12</value>
25494                  </enumeratedValue>
25495                  <enumeratedValue>
25496                    <name>ACK_IN</name>
25497                    <description>SETUP: Ignore
25498IN: Respond to IN with data if STALL=0, STALL otherwise
25499OUT:  Ignore</description>
25500                    <value>13</value>
25501                  </enumeratedValue>
25502                  <enumeratedValue>
25503                    <name>ACK_IN_STATUS_OUT</name>
25504                    <description>SETUP: Accept
25505IN: Respond to IN with data
25506OUT:  ACK 0B tokens, NAK others</description>
25507                    <value>15</value>
25508                  </enumeratedValue>
25509                </enumeratedValues>
25510              </field>
25511              <field>
25512                <name>ACKED_TXN</name>
25513                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
25514                <bitRange>[4:4]</bitRange>
25515                <access>read-write</access>
25516                <enumeratedValues>
25517                  <enumeratedValue>
25518                    <name>ACKED_NO</name>
25519                    <description>No ACK'd transactions since bit was last cleared.</description>
25520                    <value>0</value>
25521                  </enumeratedValue>
25522                  <enumeratedValue>
25523                    <name>ACKED_YES</name>
25524                    <description>Indicates a transaction ended with an ACK.</description>
25525                    <value>1</value>
25526                  </enumeratedValue>
25527                </enumeratedValues>
25528              </field>
25529              <field>
25530                <name>NAK_INT_EN</name>
25531                <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
25532                <bitRange>[5:5]</bitRange>
25533                <access>read-write</access>
25534              </field>
25535              <field>
25536                <name>ERR_IN_TXN</name>
25537                <description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
25538error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
25539                <bitRange>[6:6]</bitRange>
25540                <access>read-write</access>
25541              </field>
25542              <field>
25543                <name>STALL</name>
25544                <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
25545                <bitRange>[7:7]</bitRange>
25546                <access>read-write</access>
25547              </field>
25548            </fields>
25549          </register>
25550          <register>
25551            <name>SIE_EP4_CNT0</name>
25552            <description>Non-control endpoint count register</description>
25553            <addressOffset>0xF0</addressOffset>
25554            <size>32</size>
25555            <access>read-write</access>
25556            <resetValue>0x0</resetValue>
25557            <resetMask>0xC7</resetMask>
25558            <fields>
25559              <field>
25560                <name>DATA_COUNT_MSB</name>
25561                <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
25562                <bitRange>[2:0]</bitRange>
25563                <access>read-write</access>
25564              </field>
25565              <field>
25566                <name>DATA_VALID</name>
25567                <description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
25568                <bitRange>[6:6]</bitRange>
25569                <access>read-write</access>
25570                <enumeratedValues>
25571                  <enumeratedValue>
25572                    <name>DATA_ERROR</name>
25573                    <description>No ACK'd transactions since bit was last cleared.</description>
25574                    <value>0</value>
25575                  </enumeratedValue>
25576                  <enumeratedValue>
25577                    <name>DATA_VALID</name>
25578                    <description>Indicates a transaction ended with an ACK.</description>
25579                    <value>1</value>
25580                  </enumeratedValue>
25581                </enumeratedValues>
25582              </field>
25583              <field>
25584                <name>DATA_TOGGLE</name>
25585                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
25586                <bitRange>[7:7]</bitRange>
25587                <access>read-write</access>
25588              </field>
25589            </fields>
25590          </register>
25591          <register>
25592            <name>SIE_EP4_CNT1</name>
25593            <description>Non-control endpoint count register</description>
25594            <addressOffset>0xF4</addressOffset>
25595            <size>32</size>
25596            <access>read-write</access>
25597            <resetValue>0x0</resetValue>
25598            <resetMask>0xFF</resetMask>
25599            <fields>
25600              <field>
25601                <name>DATA_COUNT</name>
25602                <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
25603                <bitRange>[7:0]</bitRange>
25604                <access>read-write</access>
25605              </field>
25606            </fields>
25607          </register>
25608          <register>
25609            <name>SIE_EP4_CR0</name>
25610            <description>Non-control endpoint's control Register</description>
25611            <addressOffset>0xF8</addressOffset>
25612            <size>32</size>
25613            <access>read-write</access>
25614            <resetValue>0x0</resetValue>
25615            <resetMask>0xFF</resetMask>
25616            <fields>
25617              <field>
25618                <name>MODE</name>
25619                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
25620                <bitRange>[3:0]</bitRange>
25621                <access>read-write</access>
25622                <enumeratedValues>
25623                  <enumeratedValue>
25624                    <name>DISABLE</name>
25625                    <description>Ignore all USB traffic to this endpoint</description>
25626                    <value>0</value>
25627                  </enumeratedValue>
25628                  <enumeratedValue>
25629                    <name>NAK_INOUT</name>
25630                    <description>SETUP: Accept
25631IN: NAK
25632OUT:  NAK</description>
25633                    <value>1</value>
25634                  </enumeratedValue>
25635                  <enumeratedValue>
25636                    <name>STATUS_OUT_ONLY</name>
25637                    <description>SETUP: Accept
25638IN: STALL
25639OUT:  ACK 0B tokens, NAK others</description>
25640                    <value>2</value>
25641                  </enumeratedValue>
25642                  <enumeratedValue>
25643                    <name>STALL_INOUT</name>
25644                    <description>SETUP: Accept
25645IN: STALL
25646OUT:  STALL</description>
25647                    <value>3</value>
25648                  </enumeratedValue>
25649                  <enumeratedValue>
25650                    <name>ISO_OUT</name>
25651                    <description>SETUP: Ignore
25652IN: Ignore
25653OUT:  Accept Isochronous OUT token</description>
25654                    <value>5</value>
25655                  </enumeratedValue>
25656                  <enumeratedValue>
25657                    <name>STATUS_IN_ONLY</name>
25658                    <description>SETUP: Accept
25659IN: Respond with 0B data
25660OUT:  Stall</description>
25661                    <value>6</value>
25662                  </enumeratedValue>
25663                  <enumeratedValue>
25664                    <name>ISO_IN</name>
25665                    <description>SETUP: Ignore
25666IN: Accept Isochronous IN token
25667OUT:  Ignore</description>
25668                    <value>7</value>
25669                  </enumeratedValue>
25670                  <enumeratedValue>
25671                    <name>NAK_OUT</name>
25672                    <description>SETUP: Ignore
25673IN: Ignore
25674OUT:  NAK</description>
25675                    <value>8</value>
25676                  </enumeratedValue>
25677                  <enumeratedValue>
25678                    <name>ACK_OUT</name>
25679                    <description>SETUP: Ignore
25680IN: Ignore
25681OUT:  Accept data and ACK if STALL=0, STALL otherwise.
25682Change to MODE=8 after one succesfull OUT token.</description>
25683                    <value>9</value>
25684                  </enumeratedValue>
25685                  <enumeratedValue>
25686                    <name>ACK_OUT_STATUS_IN</name>
25687                    <description>SETUP: Accept
25688IN: Respond with 0B data
25689OUT:  Accept data</description>
25690                    <value>11</value>
25691                  </enumeratedValue>
25692                  <enumeratedValue>
25693                    <name>NAK_IN</name>
25694                    <description>SETUP: Ignore
25695IN: NAK
25696OUT:  Ignore</description>
25697                    <value>12</value>
25698                  </enumeratedValue>
25699                  <enumeratedValue>
25700                    <name>ACK_IN</name>
25701                    <description>SETUP: Ignore
25702IN: Respond to IN with data if STALL=0, STALL otherwise
25703OUT:  Ignore</description>
25704                    <value>13</value>
25705                  </enumeratedValue>
25706                  <enumeratedValue>
25707                    <name>ACK_IN_STATUS_OUT</name>
25708                    <description>SETUP: Accept
25709IN: Respond to IN with data
25710OUT:  ACK 0B tokens, NAK others</description>
25711                    <value>15</value>
25712                  </enumeratedValue>
25713                </enumeratedValues>
25714              </field>
25715              <field>
25716                <name>ACKED_TXN</name>
25717                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
25718                <bitRange>[4:4]</bitRange>
25719                <access>read-write</access>
25720                <enumeratedValues>
25721                  <enumeratedValue>
25722                    <name>ACKED_NO</name>
25723                    <description>No ACK'd transactions since bit was last cleared.</description>
25724                    <value>0</value>
25725                  </enumeratedValue>
25726                  <enumeratedValue>
25727                    <name>ACKED_YES</name>
25728                    <description>Indicates a transaction ended with an ACK.</description>
25729                    <value>1</value>
25730                  </enumeratedValue>
25731                </enumeratedValues>
25732              </field>
25733              <field>
25734                <name>NAK_INT_EN</name>
25735                <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
25736                <bitRange>[5:5]</bitRange>
25737                <access>read-write</access>
25738              </field>
25739              <field>
25740                <name>ERR_IN_TXN</name>
25741                <description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
25742error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
25743                <bitRange>[6:6]</bitRange>
25744                <access>read-write</access>
25745              </field>
25746              <field>
25747                <name>STALL</name>
25748                <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
25749                <bitRange>[7:7]</bitRange>
25750                <access>read-write</access>
25751              </field>
25752            </fields>
25753          </register>
25754          <register>
25755            <name>SIE_EP5_CNT0</name>
25756            <description>Non-control endpoint count register</description>
25757            <addressOffset>0x130</addressOffset>
25758            <size>32</size>
25759            <access>read-write</access>
25760            <resetValue>0x0</resetValue>
25761            <resetMask>0xC7</resetMask>
25762            <fields>
25763              <field>
25764                <name>DATA_COUNT_MSB</name>
25765                <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
25766                <bitRange>[2:0]</bitRange>
25767                <access>read-write</access>
25768              </field>
25769              <field>
25770                <name>DATA_VALID</name>
25771                <description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
25772                <bitRange>[6:6]</bitRange>
25773                <access>read-write</access>
25774                <enumeratedValues>
25775                  <enumeratedValue>
25776                    <name>DATA_ERROR</name>
25777                    <description>No ACK'd transactions since bit was last cleared.</description>
25778                    <value>0</value>
25779                  </enumeratedValue>
25780                  <enumeratedValue>
25781                    <name>DATA_VALID</name>
25782                    <description>Indicates a transaction ended with an ACK.</description>
25783                    <value>1</value>
25784                  </enumeratedValue>
25785                </enumeratedValues>
25786              </field>
25787              <field>
25788                <name>DATA_TOGGLE</name>
25789                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
25790                <bitRange>[7:7]</bitRange>
25791                <access>read-write</access>
25792              </field>
25793            </fields>
25794          </register>
25795          <register>
25796            <name>SIE_EP5_CNT1</name>
25797            <description>Non-control endpoint count register</description>
25798            <addressOffset>0x134</addressOffset>
25799            <size>32</size>
25800            <access>read-write</access>
25801            <resetValue>0x0</resetValue>
25802            <resetMask>0xFF</resetMask>
25803            <fields>
25804              <field>
25805                <name>DATA_COUNT</name>
25806                <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
25807                <bitRange>[7:0]</bitRange>
25808                <access>read-write</access>
25809              </field>
25810            </fields>
25811          </register>
25812          <register>
25813            <name>SIE_EP5_CR0</name>
25814            <description>Non-control endpoint's control Register</description>
25815            <addressOffset>0x138</addressOffset>
25816            <size>32</size>
25817            <access>read-write</access>
25818            <resetValue>0x0</resetValue>
25819            <resetMask>0xFF</resetMask>
25820            <fields>
25821              <field>
25822                <name>MODE</name>
25823                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
25824                <bitRange>[3:0]</bitRange>
25825                <access>read-write</access>
25826                <enumeratedValues>
25827                  <enumeratedValue>
25828                    <name>DISABLE</name>
25829                    <description>Ignore all USB traffic to this endpoint</description>
25830                    <value>0</value>
25831                  </enumeratedValue>
25832                  <enumeratedValue>
25833                    <name>NAK_INOUT</name>
25834                    <description>SETUP: Accept
25835IN: NAK
25836OUT:  NAK</description>
25837                    <value>1</value>
25838                  </enumeratedValue>
25839                  <enumeratedValue>
25840                    <name>STATUS_OUT_ONLY</name>
25841                    <description>SETUP: Accept
25842IN: STALL
25843OUT:  ACK 0B tokens, NAK others</description>
25844                    <value>2</value>
25845                  </enumeratedValue>
25846                  <enumeratedValue>
25847                    <name>STALL_INOUT</name>
25848                    <description>SETUP: Accept
25849IN: STALL
25850OUT:  STALL</description>
25851                    <value>3</value>
25852                  </enumeratedValue>
25853                  <enumeratedValue>
25854                    <name>ISO_OUT</name>
25855                    <description>SETUP: Ignore
25856IN: Ignore
25857OUT:  Accept Isochronous OUT token</description>
25858                    <value>5</value>
25859                  </enumeratedValue>
25860                  <enumeratedValue>
25861                    <name>STATUS_IN_ONLY</name>
25862                    <description>SETUP: Accept
25863IN: Respond with 0B data
25864OUT:  Stall</description>
25865                    <value>6</value>
25866                  </enumeratedValue>
25867                  <enumeratedValue>
25868                    <name>ISO_IN</name>
25869                    <description>SETUP: Ignore
25870IN: Accept Isochronous IN token
25871OUT:  Ignore</description>
25872                    <value>7</value>
25873                  </enumeratedValue>
25874                  <enumeratedValue>
25875                    <name>NAK_OUT</name>
25876                    <description>SETUP: Ignore
25877IN: Ignore
25878OUT:  NAK</description>
25879                    <value>8</value>
25880                  </enumeratedValue>
25881                  <enumeratedValue>
25882                    <name>ACK_OUT</name>
25883                    <description>SETUP: Ignore
25884IN: Ignore
25885OUT:  Accept data and ACK if STALL=0, STALL otherwise.
25886Change to MODE=8 after one succesfull OUT token.</description>
25887                    <value>9</value>
25888                  </enumeratedValue>
25889                  <enumeratedValue>
25890                    <name>ACK_OUT_STATUS_IN</name>
25891                    <description>SETUP: Accept
25892IN: Respond with 0B data
25893OUT:  Accept data</description>
25894                    <value>11</value>
25895                  </enumeratedValue>
25896                  <enumeratedValue>
25897                    <name>NAK_IN</name>
25898                    <description>SETUP: Ignore
25899IN: NAK
25900OUT:  Ignore</description>
25901                    <value>12</value>
25902                  </enumeratedValue>
25903                  <enumeratedValue>
25904                    <name>ACK_IN</name>
25905                    <description>SETUP: Ignore
25906IN: Respond to IN with data if STALL=0, STALL otherwise
25907OUT:  Ignore</description>
25908                    <value>13</value>
25909                  </enumeratedValue>
25910                  <enumeratedValue>
25911                    <name>ACK_IN_STATUS_OUT</name>
25912                    <description>SETUP: Accept
25913IN: Respond to IN with data
25914OUT:  ACK 0B tokens, NAK others</description>
25915                    <value>15</value>
25916                  </enumeratedValue>
25917                </enumeratedValues>
25918              </field>
25919              <field>
25920                <name>ACKED_TXN</name>
25921                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
25922                <bitRange>[4:4]</bitRange>
25923                <access>read-write</access>
25924                <enumeratedValues>
25925                  <enumeratedValue>
25926                    <name>ACKED_NO</name>
25927                    <description>No ACK'd transactions since bit was last cleared.</description>
25928                    <value>0</value>
25929                  </enumeratedValue>
25930                  <enumeratedValue>
25931                    <name>ACKED_YES</name>
25932                    <description>Indicates a transaction ended with an ACK.</description>
25933                    <value>1</value>
25934                  </enumeratedValue>
25935                </enumeratedValues>
25936              </field>
25937              <field>
25938                <name>NAK_INT_EN</name>
25939                <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
25940                <bitRange>[5:5]</bitRange>
25941                <access>read-write</access>
25942              </field>
25943              <field>
25944                <name>ERR_IN_TXN</name>
25945                <description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
25946error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
25947                <bitRange>[6:6]</bitRange>
25948                <access>read-write</access>
25949              </field>
25950              <field>
25951                <name>STALL</name>
25952                <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
25953                <bitRange>[7:7]</bitRange>
25954                <access>read-write</access>
25955              </field>
25956            </fields>
25957          </register>
25958          <register>
25959            <name>SIE_EP6_CNT0</name>
25960            <description>Non-control endpoint count register</description>
25961            <addressOffset>0x170</addressOffset>
25962            <size>32</size>
25963            <access>read-write</access>
25964            <resetValue>0x0</resetValue>
25965            <resetMask>0xC7</resetMask>
25966            <fields>
25967              <field>
25968                <name>DATA_COUNT_MSB</name>
25969                <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
25970                <bitRange>[2:0]</bitRange>
25971                <access>read-write</access>
25972              </field>
25973              <field>
25974                <name>DATA_VALID</name>
25975                <description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
25976                <bitRange>[6:6]</bitRange>
25977                <access>read-write</access>
25978                <enumeratedValues>
25979                  <enumeratedValue>
25980                    <name>DATA_ERROR</name>
25981                    <description>No ACK'd transactions since bit was last cleared.</description>
25982                    <value>0</value>
25983                  </enumeratedValue>
25984                  <enumeratedValue>
25985                    <name>DATA_VALID</name>
25986                    <description>Indicates a transaction ended with an ACK.</description>
25987                    <value>1</value>
25988                  </enumeratedValue>
25989                </enumeratedValues>
25990              </field>
25991              <field>
25992                <name>DATA_TOGGLE</name>
25993                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
25994                <bitRange>[7:7]</bitRange>
25995                <access>read-write</access>
25996              </field>
25997            </fields>
25998          </register>
25999          <register>
26000            <name>SIE_EP6_CNT1</name>
26001            <description>Non-control endpoint count register</description>
26002            <addressOffset>0x174</addressOffset>
26003            <size>32</size>
26004            <access>read-write</access>
26005            <resetValue>0x0</resetValue>
26006            <resetMask>0xFF</resetMask>
26007            <fields>
26008              <field>
26009                <name>DATA_COUNT</name>
26010                <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
26011                <bitRange>[7:0]</bitRange>
26012                <access>read-write</access>
26013              </field>
26014            </fields>
26015          </register>
26016          <register>
26017            <name>SIE_EP6_CR0</name>
26018            <description>Non-control endpoint's control Register</description>
26019            <addressOffset>0x178</addressOffset>
26020            <size>32</size>
26021            <access>read-write</access>
26022            <resetValue>0x0</resetValue>
26023            <resetMask>0xFF</resetMask>
26024            <fields>
26025              <field>
26026                <name>MODE</name>
26027                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
26028                <bitRange>[3:0]</bitRange>
26029                <access>read-write</access>
26030                <enumeratedValues>
26031                  <enumeratedValue>
26032                    <name>DISABLE</name>
26033                    <description>Ignore all USB traffic to this endpoint</description>
26034                    <value>0</value>
26035                  </enumeratedValue>
26036                  <enumeratedValue>
26037                    <name>NAK_INOUT</name>
26038                    <description>SETUP: Accept
26039IN: NAK
26040OUT:  NAK</description>
26041                    <value>1</value>
26042                  </enumeratedValue>
26043                  <enumeratedValue>
26044                    <name>STATUS_OUT_ONLY</name>
26045                    <description>SETUP: Accept
26046IN: STALL
26047OUT:  ACK 0B tokens, NAK others</description>
26048                    <value>2</value>
26049                  </enumeratedValue>
26050                  <enumeratedValue>
26051                    <name>STALL_INOUT</name>
26052                    <description>SETUP: Accept
26053IN: STALL
26054OUT:  STALL</description>
26055                    <value>3</value>
26056                  </enumeratedValue>
26057                  <enumeratedValue>
26058                    <name>ISO_OUT</name>
26059                    <description>SETUP: Ignore
26060IN: Ignore
26061OUT:  Accept Isochronous OUT token</description>
26062                    <value>5</value>
26063                  </enumeratedValue>
26064                  <enumeratedValue>
26065                    <name>STATUS_IN_ONLY</name>
26066                    <description>SETUP: Accept
26067IN: Respond with 0B data
26068OUT:  Stall</description>
26069                    <value>6</value>
26070                  </enumeratedValue>
26071                  <enumeratedValue>
26072                    <name>ISO_IN</name>
26073                    <description>SETUP: Ignore
26074IN: Accept Isochronous IN token
26075OUT:  Ignore</description>
26076                    <value>7</value>
26077                  </enumeratedValue>
26078                  <enumeratedValue>
26079                    <name>NAK_OUT</name>
26080                    <description>SETUP: Ignore
26081IN: Ignore
26082OUT:  NAK</description>
26083                    <value>8</value>
26084                  </enumeratedValue>
26085                  <enumeratedValue>
26086                    <name>ACK_OUT</name>
26087                    <description>SETUP: Ignore
26088IN: Ignore
26089OUT:  Accept data and ACK if STALL=0, STALL otherwise.
26090Change to MODE=8 after one succesfull OUT token.</description>
26091                    <value>9</value>
26092                  </enumeratedValue>
26093                  <enumeratedValue>
26094                    <name>ACK_OUT_STATUS_IN</name>
26095                    <description>SETUP: Accept
26096IN: Respond with 0B data
26097OUT:  Accept data</description>
26098                    <value>11</value>
26099                  </enumeratedValue>
26100                  <enumeratedValue>
26101                    <name>NAK_IN</name>
26102                    <description>SETUP: Ignore
26103IN: NAK
26104OUT:  Ignore</description>
26105                    <value>12</value>
26106                  </enumeratedValue>
26107                  <enumeratedValue>
26108                    <name>ACK_IN</name>
26109                    <description>SETUP: Ignore
26110IN: Respond to IN with data if STALL=0, STALL otherwise
26111OUT:  Ignore</description>
26112                    <value>13</value>
26113                  </enumeratedValue>
26114                  <enumeratedValue>
26115                    <name>ACK_IN_STATUS_OUT</name>
26116                    <description>SETUP: Accept
26117IN: Respond to IN with data
26118OUT:  ACK 0B tokens, NAK others</description>
26119                    <value>15</value>
26120                  </enumeratedValue>
26121                </enumeratedValues>
26122              </field>
26123              <field>
26124                <name>ACKED_TXN</name>
26125                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
26126                <bitRange>[4:4]</bitRange>
26127                <access>read-write</access>
26128                <enumeratedValues>
26129                  <enumeratedValue>
26130                    <name>ACKED_NO</name>
26131                    <description>No ACK'd transactions since bit was last cleared.</description>
26132                    <value>0</value>
26133                  </enumeratedValue>
26134                  <enumeratedValue>
26135                    <name>ACKED_YES</name>
26136                    <description>Indicates a transaction ended with an ACK.</description>
26137                    <value>1</value>
26138                  </enumeratedValue>
26139                </enumeratedValues>
26140              </field>
26141              <field>
26142                <name>NAK_INT_EN</name>
26143                <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
26144                <bitRange>[5:5]</bitRange>
26145                <access>read-write</access>
26146              </field>
26147              <field>
26148                <name>ERR_IN_TXN</name>
26149                <description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
26150error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
26151                <bitRange>[6:6]</bitRange>
26152                <access>read-write</access>
26153              </field>
26154              <field>
26155                <name>STALL</name>
26156                <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
26157                <bitRange>[7:7]</bitRange>
26158                <access>read-write</access>
26159              </field>
26160            </fields>
26161          </register>
26162          <register>
26163            <name>SIE_EP7_CNT0</name>
26164            <description>Non-control endpoint count register</description>
26165            <addressOffset>0x1B0</addressOffset>
26166            <size>32</size>
26167            <access>read-write</access>
26168            <resetValue>0x0</resetValue>
26169            <resetMask>0xC7</resetMask>
26170            <fields>
26171              <field>
26172                <name>DATA_COUNT_MSB</name>
26173                <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
26174                <bitRange>[2:0]</bitRange>
26175                <access>read-write</access>
26176              </field>
26177              <field>
26178                <name>DATA_VALID</name>
26179                <description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
26180                <bitRange>[6:6]</bitRange>
26181                <access>read-write</access>
26182                <enumeratedValues>
26183                  <enumeratedValue>
26184                    <name>DATA_ERROR</name>
26185                    <description>No ACK'd transactions since bit was last cleared.</description>
26186                    <value>0</value>
26187                  </enumeratedValue>
26188                  <enumeratedValue>
26189                    <name>DATA_VALID</name>
26190                    <description>Indicates a transaction ended with an ACK.</description>
26191                    <value>1</value>
26192                  </enumeratedValue>
26193                </enumeratedValues>
26194              </field>
26195              <field>
26196                <name>DATA_TOGGLE</name>
26197                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
26198                <bitRange>[7:7]</bitRange>
26199                <access>read-write</access>
26200              </field>
26201            </fields>
26202          </register>
26203          <register>
26204            <name>SIE_EP7_CNT1</name>
26205            <description>Non-control endpoint count register</description>
26206            <addressOffset>0x1B4</addressOffset>
26207            <size>32</size>
26208            <access>read-write</access>
26209            <resetValue>0x0</resetValue>
26210            <resetMask>0xFF</resetMask>
26211            <fields>
26212              <field>
26213                <name>DATA_COUNT</name>
26214                <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
26215                <bitRange>[7:0]</bitRange>
26216                <access>read-write</access>
26217              </field>
26218            </fields>
26219          </register>
26220          <register>
26221            <name>SIE_EP7_CR0</name>
26222            <description>Non-control endpoint's control Register</description>
26223            <addressOffset>0x1B8</addressOffset>
26224            <size>32</size>
26225            <access>read-write</access>
26226            <resetValue>0x0</resetValue>
26227            <resetMask>0xFF</resetMask>
26228            <fields>
26229              <field>
26230                <name>MODE</name>
26231                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
26232                <bitRange>[3:0]</bitRange>
26233                <access>read-write</access>
26234                <enumeratedValues>
26235                  <enumeratedValue>
26236                    <name>DISABLE</name>
26237                    <description>Ignore all USB traffic to this endpoint</description>
26238                    <value>0</value>
26239                  </enumeratedValue>
26240                  <enumeratedValue>
26241                    <name>NAK_INOUT</name>
26242                    <description>SETUP: Accept
26243IN: NAK
26244OUT:  NAK</description>
26245                    <value>1</value>
26246                  </enumeratedValue>
26247                  <enumeratedValue>
26248                    <name>STATUS_OUT_ONLY</name>
26249                    <description>SETUP: Accept
26250IN: STALL
26251OUT:  ACK 0B tokens, NAK others</description>
26252                    <value>2</value>
26253                  </enumeratedValue>
26254                  <enumeratedValue>
26255                    <name>STALL_INOUT</name>
26256                    <description>SETUP: Accept
26257IN: STALL
26258OUT:  STALL</description>
26259                    <value>3</value>
26260                  </enumeratedValue>
26261                  <enumeratedValue>
26262                    <name>ISO_OUT</name>
26263                    <description>SETUP: Ignore
26264IN: Ignore
26265OUT:  Accept Isochronous OUT token</description>
26266                    <value>5</value>
26267                  </enumeratedValue>
26268                  <enumeratedValue>
26269                    <name>STATUS_IN_ONLY</name>
26270                    <description>SETUP: Accept
26271IN: Respond with 0B data
26272OUT:  Stall</description>
26273                    <value>6</value>
26274                  </enumeratedValue>
26275                  <enumeratedValue>
26276                    <name>ISO_IN</name>
26277                    <description>SETUP: Ignore
26278IN: Accept Isochronous IN token
26279OUT:  Ignore</description>
26280                    <value>7</value>
26281                  </enumeratedValue>
26282                  <enumeratedValue>
26283                    <name>NAK_OUT</name>
26284                    <description>SETUP: Ignore
26285IN: Ignore
26286OUT:  NAK</description>
26287                    <value>8</value>
26288                  </enumeratedValue>
26289                  <enumeratedValue>
26290                    <name>ACK_OUT</name>
26291                    <description>SETUP: Ignore
26292IN: Ignore
26293OUT:  Accept data and ACK if STALL=0, STALL otherwise.
26294Change to MODE=8 after one succesfull OUT token.</description>
26295                    <value>9</value>
26296                  </enumeratedValue>
26297                  <enumeratedValue>
26298                    <name>ACK_OUT_STATUS_IN</name>
26299                    <description>SETUP: Accept
26300IN: Respond with 0B data
26301OUT:  Accept data</description>
26302                    <value>11</value>
26303                  </enumeratedValue>
26304                  <enumeratedValue>
26305                    <name>NAK_IN</name>
26306                    <description>SETUP: Ignore
26307IN: NAK
26308OUT:  Ignore</description>
26309                    <value>12</value>
26310                  </enumeratedValue>
26311                  <enumeratedValue>
26312                    <name>ACK_IN</name>
26313                    <description>SETUP: Ignore
26314IN: Respond to IN with data if STALL=0, STALL otherwise
26315OUT:  Ignore</description>
26316                    <value>13</value>
26317                  </enumeratedValue>
26318                  <enumeratedValue>
26319                    <name>ACK_IN_STATUS_OUT</name>
26320                    <description>SETUP: Accept
26321IN: Respond to IN with data
26322OUT:  ACK 0B tokens, NAK others</description>
26323                    <value>15</value>
26324                  </enumeratedValue>
26325                </enumeratedValues>
26326              </field>
26327              <field>
26328                <name>ACKED_TXN</name>
26329                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
26330                <bitRange>[4:4]</bitRange>
26331                <access>read-write</access>
26332                <enumeratedValues>
26333                  <enumeratedValue>
26334                    <name>ACKED_NO</name>
26335                    <description>No ACK'd transactions since bit was last cleared.</description>
26336                    <value>0</value>
26337                  </enumeratedValue>
26338                  <enumeratedValue>
26339                    <name>ACKED_YES</name>
26340                    <description>Indicates a transaction ended with an ACK.</description>
26341                    <value>1</value>
26342                  </enumeratedValue>
26343                </enumeratedValues>
26344              </field>
26345              <field>
26346                <name>NAK_INT_EN</name>
26347                <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
26348                <bitRange>[5:5]</bitRange>
26349                <access>read-write</access>
26350              </field>
26351              <field>
26352                <name>ERR_IN_TXN</name>
26353                <description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
26354error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
26355                <bitRange>[6:6]</bitRange>
26356                <access>read-write</access>
26357              </field>
26358              <field>
26359                <name>STALL</name>
26360                <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
26361                <bitRange>[7:7]</bitRange>
26362                <access>read-write</access>
26363              </field>
26364            </fields>
26365          </register>
26366          <register>
26367            <name>SIE_EP8_CNT0</name>
26368            <description>Non-control endpoint count register</description>
26369            <addressOffset>0x1F0</addressOffset>
26370            <size>32</size>
26371            <access>read-write</access>
26372            <resetValue>0x0</resetValue>
26373            <resetMask>0xC7</resetMask>
26374            <fields>
26375              <field>
26376                <name>DATA_COUNT_MSB</name>
26377                <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
26378                <bitRange>[2:0]</bitRange>
26379                <access>read-write</access>
26380              </field>
26381              <field>
26382                <name>DATA_VALID</name>
26383                <description>This bit is used for OUT transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>
26384                <bitRange>[6:6]</bitRange>
26385                <access>read-write</access>
26386                <enumeratedValues>
26387                  <enumeratedValue>
26388                    <name>DATA_ERROR</name>
26389                    <description>No ACK'd transactions since bit was last cleared.</description>
26390                    <value>0</value>
26391                  </enumeratedValue>
26392                  <enumeratedValue>
26393                    <name>DATA_VALID</name>
26394                    <description>Indicates a transaction ended with an ACK.</description>
26395                    <value>1</value>
26396                  </enumeratedValue>
26397                </enumeratedValues>
26398              </field>
26399              <field>
26400                <name>DATA_TOGGLE</name>
26401                <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>
26402                <bitRange>[7:7]</bitRange>
26403                <access>read-write</access>
26404              </field>
26405            </fields>
26406          </register>
26407          <register>
26408            <name>SIE_EP8_CNT1</name>
26409            <description>Non-control endpoint count register</description>
26410            <addressOffset>0x1F4</addressOffset>
26411            <size>32</size>
26412            <access>read-write</access>
26413            <resetValue>0x0</resetValue>
26414            <resetMask>0xFF</resetMask>
26415            <fields>
26416              <field>
26417                <name>DATA_COUNT</name>
26418                <description>These bits are the 8 LSb of a 11-bit counter.  The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>
26419                <bitRange>[7:0]</bitRange>
26420                <access>read-write</access>
26421              </field>
26422            </fields>
26423          </register>
26424          <register>
26425            <name>SIE_EP8_CR0</name>
26426            <description>Non-control endpoint's control Register</description>
26427            <addressOffset>0x1F8</addressOffset>
26428            <size>32</size>
26429            <access>read-write</access>
26430            <resetValue>0x0</resetValue>
26431            <resetMask>0xFF</resetMask>
26432            <fields>
26433              <field>
26434                <name>MODE</name>
26435                <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>
26436                <bitRange>[3:0]</bitRange>
26437                <access>read-write</access>
26438                <enumeratedValues>
26439                  <enumeratedValue>
26440                    <name>DISABLE</name>
26441                    <description>Ignore all USB traffic to this endpoint</description>
26442                    <value>0</value>
26443                  </enumeratedValue>
26444                  <enumeratedValue>
26445                    <name>NAK_INOUT</name>
26446                    <description>SETUP: Accept
26447IN: NAK
26448OUT:  NAK</description>
26449                    <value>1</value>
26450                  </enumeratedValue>
26451                  <enumeratedValue>
26452                    <name>STATUS_OUT_ONLY</name>
26453                    <description>SETUP: Accept
26454IN: STALL
26455OUT:  ACK 0B tokens, NAK others</description>
26456                    <value>2</value>
26457                  </enumeratedValue>
26458                  <enumeratedValue>
26459                    <name>STALL_INOUT</name>
26460                    <description>SETUP: Accept
26461IN: STALL
26462OUT:  STALL</description>
26463                    <value>3</value>
26464                  </enumeratedValue>
26465                  <enumeratedValue>
26466                    <name>ISO_OUT</name>
26467                    <description>SETUP: Ignore
26468IN: Ignore
26469OUT:  Accept Isochronous OUT token</description>
26470                    <value>5</value>
26471                  </enumeratedValue>
26472                  <enumeratedValue>
26473                    <name>STATUS_IN_ONLY</name>
26474                    <description>SETUP: Accept
26475IN: Respond with 0B data
26476OUT:  Stall</description>
26477                    <value>6</value>
26478                  </enumeratedValue>
26479                  <enumeratedValue>
26480                    <name>ISO_IN</name>
26481                    <description>SETUP: Ignore
26482IN: Accept Isochronous IN token
26483OUT:  Ignore</description>
26484                    <value>7</value>
26485                  </enumeratedValue>
26486                  <enumeratedValue>
26487                    <name>NAK_OUT</name>
26488                    <description>SETUP: Ignore
26489IN: Ignore
26490OUT:  NAK</description>
26491                    <value>8</value>
26492                  </enumeratedValue>
26493                  <enumeratedValue>
26494                    <name>ACK_OUT</name>
26495                    <description>SETUP: Ignore
26496IN: Ignore
26497OUT:  Accept data and ACK if STALL=0, STALL otherwise.
26498Change to MODE=8 after one succesfull OUT token.</description>
26499                    <value>9</value>
26500                  </enumeratedValue>
26501                  <enumeratedValue>
26502                    <name>ACK_OUT_STATUS_IN</name>
26503                    <description>SETUP: Accept
26504IN: Respond with 0B data
26505OUT:  Accept data</description>
26506                    <value>11</value>
26507                  </enumeratedValue>
26508                  <enumeratedValue>
26509                    <name>NAK_IN</name>
26510                    <description>SETUP: Ignore
26511IN: NAK
26512OUT:  Ignore</description>
26513                    <value>12</value>
26514                  </enumeratedValue>
26515                  <enumeratedValue>
26516                    <name>ACK_IN</name>
26517                    <description>SETUP: Ignore
26518IN: Respond to IN with data if STALL=0, STALL otherwise
26519OUT:  Ignore</description>
26520                    <value>13</value>
26521                  </enumeratedValue>
26522                  <enumeratedValue>
26523                    <name>ACK_IN_STATUS_OUT</name>
26524                    <description>SETUP: Accept
26525IN: Respond to IN with data
26526OUT:  ACK 0B tokens, NAK others</description>
26527                    <value>15</value>
26528                  </enumeratedValue>
26529                </enumeratedValues>
26530              </field>
26531              <field>
26532                <name>ACKED_TXN</name>
26533                <description>The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet. This bit is cleared by any writes to the register.</description>
26534                <bitRange>[4:4]</bitRange>
26535                <access>read-write</access>
26536                <enumeratedValues>
26537                  <enumeratedValue>
26538                    <name>ACKED_NO</name>
26539                    <description>No ACK'd transactions since bit was last cleared.</description>
26540                    <value>0</value>
26541                  </enumeratedValue>
26542                  <enumeratedValue>
26543                    <name>ACKED_YES</name>
26544                    <description>Indicates a transaction ended with an ACK.</description>
26545                    <value>1</value>
26546                  </enumeratedValue>
26547                </enumeratedValues>
26548              </field>
26549              <field>
26550                <name>NAK_INT_EN</name>
26551                <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>
26552                <bitRange>[5:5]</bitRange>
26553                <access>read-write</access>
26554              </field>
26555              <field>
26556                <name>ERR_IN_TXN</name>
26557                <description>The Error in transaction bit is set whenever an error is detected. For an IN transaction, this indicates a no response from HOST scenario. For an OUT transaction, this represents an RxErr (PID
26558error/ CRC error/ bit-stuff error scenario). This bit is cleared by any writes to the register.</description>
26559                <bitRange>[6:6]</bitRange>
26560                <access>read-write</access>
26561              </field>
26562              <field>
26563                <name>STALL</name>
26564                <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>
26565                <bitRange>[7:7]</bitRange>
26566                <access>read-write</access>
26567              </field>
26568            </fields>
26569          </register>
26570          <register>
26571            <name>ARB_EP1_CFG</name>
26572            <description>Endpoint Configuration Register  *1</description>
26573            <addressOffset>0x200</addressOffset>
26574            <size>32</size>
26575            <access>read-write</access>
26576            <resetValue>0x0</resetValue>
26577            <resetMask>0xF</resetMask>
26578            <fields>
26579              <field>
26580                <name>IN_DATA_RDY</name>
26581                <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
26582                <bitRange>[0:0]</bitRange>
26583                <access>read-write</access>
26584              </field>
26585              <field>
26586                <name>DMA_REQ</name>
26587                <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
26588                <bitRange>[1:1]</bitRange>
26589                <access>read-write</access>
26590              </field>
26591              <field>
26592                <name>CRC_BYPASS</name>
26593                <description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
26594                <bitRange>[2:2]</bitRange>
26595                <access>read-write</access>
26596                <enumeratedValues>
26597                  <enumeratedValue>
26598                    <name>CRC_NORMAL</name>
26599                    <description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
26600                    <value>0</value>
26601                  </enumeratedValue>
26602                  <enumeratedValue>
26603                    <name>CRC_BYPASS</name>
26604                    <description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
26605                    <value>1</value>
26606                  </enumeratedValue>
26607                </enumeratedValues>
26608              </field>
26609              <field>
26610                <name>RESET_PTR</name>
26611                <description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
26612                <bitRange>[3:3]</bitRange>
26613                <access>read-write</access>
26614                <enumeratedValues>
26615                  <enumeratedValue>
26616                    <name>RESET_KRYPTON</name>
26617                    <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
26618                    <value>0</value>
26619                  </enumeratedValue>
26620                  <enumeratedValue>
26621                    <name>RESET_NORMAL</name>
26622                    <description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
26623                    <value>1</value>
26624                  </enumeratedValue>
26625                </enumeratedValues>
26626              </field>
26627            </fields>
26628          </register>
26629          <register>
26630            <name>ARB_EP1_INT_EN</name>
26631            <description>Endpoint Interrupt Enable Register  *1</description>
26632            <addressOffset>0x204</addressOffset>
26633            <size>32</size>
26634            <access>read-write</access>
26635            <resetValue>0x0</resetValue>
26636            <resetMask>0x3F</resetMask>
26637            <fields>
26638              <field>
26639                <name>IN_BUF_FULL_EN</name>
26640                <description>IN Endpoint Local Buffer Full Enable</description>
26641                <bitRange>[0:0]</bitRange>
26642                <access>read-write</access>
26643              </field>
26644              <field>
26645                <name>DMA_GNT_EN</name>
26646                <description>Endpoint DMA Grant Enable</description>
26647                <bitRange>[1:1]</bitRange>
26648                <access>read-write</access>
26649              </field>
26650              <field>
26651                <name>BUF_OVER_EN</name>
26652                <description>Endpoint Buffer Overflow Enable</description>
26653                <bitRange>[2:2]</bitRange>
26654                <access>read-write</access>
26655              </field>
26656              <field>
26657                <name>BUF_UNDER_EN</name>
26658                <description>Endpoint Buffer Underflow Enable</description>
26659                <bitRange>[3:3]</bitRange>
26660                <access>read-write</access>
26661              </field>
26662              <field>
26663                <name>ERR_INT_EN</name>
26664                <description>Endpoint Error in Transaction Interrupt Enable</description>
26665                <bitRange>[4:4]</bitRange>
26666                <access>read-write</access>
26667              </field>
26668              <field>
26669                <name>DMA_TERMIN_EN</name>
26670                <description>Endpoint DMA Terminated Enable</description>
26671                <bitRange>[5:5]</bitRange>
26672                <access>read-write</access>
26673              </field>
26674            </fields>
26675          </register>
26676          <register>
26677            <name>ARB_EP1_SR</name>
26678            <description>Endpoint Interrupt Enable Register  *1</description>
26679            <addressOffset>0x208</addressOffset>
26680            <size>32</size>
26681            <access>read-write</access>
26682            <resetValue>0x0</resetValue>
26683            <resetMask>0x2F</resetMask>
26684            <fields>
26685              <field>
26686                <name>IN_BUF_FULL</name>
26687                <description>IN Endpoint Local Buffer Full Interrupt</description>
26688                <bitRange>[0:0]</bitRange>
26689                <access>read-write</access>
26690              </field>
26691              <field>
26692                <name>DMA_GNT</name>
26693                <description>Endpoint DMA Grant Interrupt</description>
26694                <bitRange>[1:1]</bitRange>
26695                <access>read-write</access>
26696              </field>
26697              <field>
26698                <name>BUF_OVER</name>
26699                <description>Endpoint Buffer Overflow Interrupt</description>
26700                <bitRange>[2:2]</bitRange>
26701                <access>read-write</access>
26702              </field>
26703              <field>
26704                <name>BUF_UNDER</name>
26705                <description>Endpoint Buffer Underflow Interrupt</description>
26706                <bitRange>[3:3]</bitRange>
26707                <access>read-write</access>
26708              </field>
26709              <field>
26710                <name>DMA_TERMIN</name>
26711                <description>Endpoint DMA Terminated Interrupt</description>
26712                <bitRange>[5:5]</bitRange>
26713                <access>read-write</access>
26714              </field>
26715            </fields>
26716          </register>
26717          <register>
26718            <name>ARB_RW1_WA</name>
26719            <description>Endpoint Write Address value  *1, *2</description>
26720            <addressOffset>0x210</addressOffset>
26721            <size>32</size>
26722            <access>read-write</access>
26723            <resetValue>0x0</resetValue>
26724            <resetMask>0xFF</resetMask>
26725            <fields>
26726              <field>
26727                <name>WA</name>
26728                <description>Write Address for EP</description>
26729                <bitRange>[7:0]</bitRange>
26730                <access>read-write</access>
26731              </field>
26732            </fields>
26733          </register>
26734          <register>
26735            <name>ARB_RW1_WA_MSB</name>
26736            <description>Endpoint Write Address value  *1, *2</description>
26737            <addressOffset>0x214</addressOffset>
26738            <size>32</size>
26739            <access>read-write</access>
26740            <resetValue>0x0</resetValue>
26741            <resetMask>0x1</resetMask>
26742            <fields>
26743              <field>
26744                <name>WA_MSB</name>
26745                <description>Write Address for EP</description>
26746                <bitRange>[0:0]</bitRange>
26747                <access>read-write</access>
26748              </field>
26749            </fields>
26750          </register>
26751          <register>
26752            <name>ARB_RW1_RA</name>
26753            <description>Endpoint Read Address value  *1, *2</description>
26754            <addressOffset>0x218</addressOffset>
26755            <size>32</size>
26756            <access>read-write</access>
26757            <resetValue>0x0</resetValue>
26758            <resetMask>0xFF</resetMask>
26759            <fields>
26760              <field>
26761                <name>RA</name>
26762                <description>Read Address for EP</description>
26763                <bitRange>[7:0]</bitRange>
26764                <access>read-write</access>
26765              </field>
26766            </fields>
26767          </register>
26768          <register>
26769            <name>ARB_RW1_RA_MSB</name>
26770            <description>Endpoint Read Address value  *1, *2</description>
26771            <addressOffset>0x21C</addressOffset>
26772            <size>32</size>
26773            <access>read-write</access>
26774            <resetValue>0x0</resetValue>
26775            <resetMask>0x1</resetMask>
26776            <fields>
26777              <field>
26778                <name>RA_MSB</name>
26779                <description>Read Address for EP</description>
26780                <bitRange>[0:0]</bitRange>
26781                <access>read-write</access>
26782              </field>
26783            </fields>
26784          </register>
26785          <register>
26786            <name>ARB_RW1_DR</name>
26787            <description>Endpoint Data Register</description>
26788            <addressOffset>0x220</addressOffset>
26789            <size>32</size>
26790            <access>read-write</access>
26791            <resetValue>0x0</resetValue>
26792            <resetMask>0x0</resetMask>
26793            <fields>
26794              <field>
26795                <name>DR</name>
26796                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
26797                <bitRange>[7:0]</bitRange>
26798                <access>read-write</access>
26799              </field>
26800            </fields>
26801          </register>
26802          <register>
26803            <name>BUF_SIZE</name>
26804            <description>Dedicated Endpoint Buffer Size Register  *1</description>
26805            <addressOffset>0x230</addressOffset>
26806            <size>32</size>
26807            <access>read-write</access>
26808            <resetValue>0x0</resetValue>
26809            <resetMask>0xFF</resetMask>
26810            <fields>
26811              <field>
26812                <name>IN_BUF</name>
26813                <description>Buffer size for IN Endpoints.</description>
26814                <bitRange>[3:0]</bitRange>
26815                <access>read-write</access>
26816              </field>
26817              <field>
26818                <name>OUT_BUF</name>
26819                <description>Buffer size for OUT Endpoints.</description>
26820                <bitRange>[7:4]</bitRange>
26821                <access>read-write</access>
26822              </field>
26823            </fields>
26824          </register>
26825          <register>
26826            <name>EP_ACTIVE</name>
26827            <description>Endpoint Active Indication Register  *1</description>
26828            <addressOffset>0x238</addressOffset>
26829            <size>32</size>
26830            <access>read-write</access>
26831            <resetValue>0x0</resetValue>
26832            <resetMask>0xFF</resetMask>
26833            <fields>
26834              <field>
26835                <name>EP1_ACT</name>
26836                <description>Indicates that Endpoint is currently active.</description>
26837                <bitRange>[0:0]</bitRange>
26838                <access>read-write</access>
26839              </field>
26840              <field>
26841                <name>EP2_ACT</name>
26842                <description>Indicates that Endpoint is currently active.</description>
26843                <bitRange>[1:1]</bitRange>
26844                <access>read-write</access>
26845              </field>
26846              <field>
26847                <name>EP3_ACT</name>
26848                <description>Indicates that Endpoint is currently active.</description>
26849                <bitRange>[2:2]</bitRange>
26850                <access>read-write</access>
26851              </field>
26852              <field>
26853                <name>EP4_ACT</name>
26854                <description>Indicates that Endpoint is currently active.</description>
26855                <bitRange>[3:3]</bitRange>
26856                <access>read-write</access>
26857              </field>
26858              <field>
26859                <name>EP5_ACT</name>
26860                <description>Indicates that Endpoint is currently active.</description>
26861                <bitRange>[4:4]</bitRange>
26862                <access>read-write</access>
26863              </field>
26864              <field>
26865                <name>EP6_ACT</name>
26866                <description>Indicates that Endpoint is currently active.</description>
26867                <bitRange>[5:5]</bitRange>
26868                <access>read-write</access>
26869              </field>
26870              <field>
26871                <name>EP7_ACT</name>
26872                <description>Indicates that Endpoint is currently active.</description>
26873                <bitRange>[6:6]</bitRange>
26874                <access>read-write</access>
26875              </field>
26876              <field>
26877                <name>EP8_ACT</name>
26878                <description>Indicates that Endpoint is currently active.</description>
26879                <bitRange>[7:7]</bitRange>
26880                <access>read-write</access>
26881              </field>
26882            </fields>
26883          </register>
26884          <register>
26885            <name>EP_TYPE</name>
26886            <description>Endpoint Type (IN/OUT) Indication  *1</description>
26887            <addressOffset>0x23C</addressOffset>
26888            <size>32</size>
26889            <access>read-write</access>
26890            <resetValue>0x0</resetValue>
26891            <resetMask>0xFF</resetMask>
26892            <fields>
26893              <field>
26894                <name>EP1_TYP</name>
26895                <description>Endpoint Type Indication.</description>
26896                <bitRange>[0:0]</bitRange>
26897                <access>read-write</access>
26898                <enumeratedValues>
26899                  <enumeratedValue>
26900                    <name>EP_IN</name>
26901                    <description>IN outpoint</description>
26902                    <value>0</value>
26903                  </enumeratedValue>
26904                  <enumeratedValue>
26905                    <name>EP_OUT</name>
26906                    <description>OUT outpoint</description>
26907                    <value>1</value>
26908                  </enumeratedValue>
26909                </enumeratedValues>
26910              </field>
26911              <field>
26912                <name>EP2_TYP</name>
26913                <description>Endpoint Type Indication.</description>
26914                <bitRange>[1:1]</bitRange>
26915                <access>read-write</access>
26916                <enumeratedValues>
26917                  <enumeratedValue>
26918                    <name>EP_IN</name>
26919                    <description>IN outpoint</description>
26920                    <value>0</value>
26921                  </enumeratedValue>
26922                  <enumeratedValue>
26923                    <name>EP_OUT</name>
26924                    <description>OUT outpoint</description>
26925                    <value>1</value>
26926                  </enumeratedValue>
26927                </enumeratedValues>
26928              </field>
26929              <field>
26930                <name>EP3_TYP</name>
26931                <description>Endpoint Type Indication.</description>
26932                <bitRange>[2:2]</bitRange>
26933                <access>read-write</access>
26934                <enumeratedValues>
26935                  <enumeratedValue>
26936                    <name>EP_IN</name>
26937                    <description>IN outpoint</description>
26938                    <value>0</value>
26939                  </enumeratedValue>
26940                  <enumeratedValue>
26941                    <name>EP_OUT</name>
26942                    <description>OUT outpoint</description>
26943                    <value>1</value>
26944                  </enumeratedValue>
26945                </enumeratedValues>
26946              </field>
26947              <field>
26948                <name>EP4_TYP</name>
26949                <description>Endpoint Type Indication.</description>
26950                <bitRange>[3:3]</bitRange>
26951                <access>read-write</access>
26952                <enumeratedValues>
26953                  <enumeratedValue>
26954                    <name>EP_IN</name>
26955                    <description>IN outpoint</description>
26956                    <value>0</value>
26957                  </enumeratedValue>
26958                  <enumeratedValue>
26959                    <name>EP_OUT</name>
26960                    <description>OUT outpoint</description>
26961                    <value>1</value>
26962                  </enumeratedValue>
26963                </enumeratedValues>
26964              </field>
26965              <field>
26966                <name>EP5_TYP</name>
26967                <description>Endpoint Type Indication.</description>
26968                <bitRange>[4:4]</bitRange>
26969                <access>read-write</access>
26970                <enumeratedValues>
26971                  <enumeratedValue>
26972                    <name>EP_IN</name>
26973                    <description>IN outpoint</description>
26974                    <value>0</value>
26975                  </enumeratedValue>
26976                  <enumeratedValue>
26977                    <name>EP_OUT</name>
26978                    <description>OUT outpoint</description>
26979                    <value>1</value>
26980                  </enumeratedValue>
26981                </enumeratedValues>
26982              </field>
26983              <field>
26984                <name>EP6_TYP</name>
26985                <description>Endpoint Type Indication.</description>
26986                <bitRange>[5:5]</bitRange>
26987                <access>read-write</access>
26988                <enumeratedValues>
26989                  <enumeratedValue>
26990                    <name>EP_IN</name>
26991                    <description>IN outpoint</description>
26992                    <value>0</value>
26993                  </enumeratedValue>
26994                  <enumeratedValue>
26995                    <name>EP_OUT</name>
26996                    <description>OUT outpoint</description>
26997                    <value>1</value>
26998                  </enumeratedValue>
26999                </enumeratedValues>
27000              </field>
27001              <field>
27002                <name>EP7_TYP</name>
27003                <description>Endpoint Type Indication.</description>
27004                <bitRange>[6:6]</bitRange>
27005                <access>read-write</access>
27006                <enumeratedValues>
27007                  <enumeratedValue>
27008                    <name>EP_IN</name>
27009                    <description>IN outpoint</description>
27010                    <value>0</value>
27011                  </enumeratedValue>
27012                  <enumeratedValue>
27013                    <name>EP_OUT</name>
27014                    <description>OUT outpoint</description>
27015                    <value>1</value>
27016                  </enumeratedValue>
27017                </enumeratedValues>
27018              </field>
27019              <field>
27020                <name>EP8_TYP</name>
27021                <description>Endpoint Type Indication.</description>
27022                <bitRange>[7:7]</bitRange>
27023                <access>read-write</access>
27024                <enumeratedValues>
27025                  <enumeratedValue>
27026                    <name>EP_IN</name>
27027                    <description>IN outpoint</description>
27028                    <value>0</value>
27029                  </enumeratedValue>
27030                  <enumeratedValue>
27031                    <name>EP_OUT</name>
27032                    <description>OUT outpoint</description>
27033                    <value>1</value>
27034                  </enumeratedValue>
27035                </enumeratedValues>
27036              </field>
27037            </fields>
27038          </register>
27039          <register>
27040            <name>ARB_EP2_CFG</name>
27041            <description>Endpoint Configuration Register  *1</description>
27042            <addressOffset>0x240</addressOffset>
27043            <size>32</size>
27044            <access>read-write</access>
27045            <resetValue>0x0</resetValue>
27046            <resetMask>0xF</resetMask>
27047            <fields>
27048              <field>
27049                <name>IN_DATA_RDY</name>
27050                <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
27051                <bitRange>[0:0]</bitRange>
27052                <access>read-write</access>
27053              </field>
27054              <field>
27055                <name>DMA_REQ</name>
27056                <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
27057                <bitRange>[1:1]</bitRange>
27058                <access>read-write</access>
27059              </field>
27060              <field>
27061                <name>CRC_BYPASS</name>
27062                <description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
27063                <bitRange>[2:2]</bitRange>
27064                <access>read-write</access>
27065                <enumeratedValues>
27066                  <enumeratedValue>
27067                    <name>CRC_NORMAL</name>
27068                    <description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
27069                    <value>0</value>
27070                  </enumeratedValue>
27071                  <enumeratedValue>
27072                    <name>CRC_BYPASS</name>
27073                    <description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
27074                    <value>1</value>
27075                  </enumeratedValue>
27076                </enumeratedValues>
27077              </field>
27078              <field>
27079                <name>RESET_PTR</name>
27080                <description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
27081                <bitRange>[3:3]</bitRange>
27082                <access>read-write</access>
27083                <enumeratedValues>
27084                  <enumeratedValue>
27085                    <name>RESET_KRYPTON</name>
27086                    <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
27087                    <value>0</value>
27088                  </enumeratedValue>
27089                  <enumeratedValue>
27090                    <name>RESET_NORMAL</name>
27091                    <description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
27092                    <value>1</value>
27093                  </enumeratedValue>
27094                </enumeratedValues>
27095              </field>
27096            </fields>
27097          </register>
27098          <register>
27099            <name>ARB_EP2_INT_EN</name>
27100            <description>Endpoint Interrupt Enable Register  *1</description>
27101            <addressOffset>0x244</addressOffset>
27102            <size>32</size>
27103            <access>read-write</access>
27104            <resetValue>0x0</resetValue>
27105            <resetMask>0x3F</resetMask>
27106            <fields>
27107              <field>
27108                <name>IN_BUF_FULL_EN</name>
27109                <description>IN Endpoint Local Buffer Full Enable</description>
27110                <bitRange>[0:0]</bitRange>
27111                <access>read-write</access>
27112              </field>
27113              <field>
27114                <name>DMA_GNT_EN</name>
27115                <description>Endpoint DMA Grant Enable</description>
27116                <bitRange>[1:1]</bitRange>
27117                <access>read-write</access>
27118              </field>
27119              <field>
27120                <name>BUF_OVER_EN</name>
27121                <description>Endpoint Buffer Overflow Enable</description>
27122                <bitRange>[2:2]</bitRange>
27123                <access>read-write</access>
27124              </field>
27125              <field>
27126                <name>BUF_UNDER_EN</name>
27127                <description>Endpoint Buffer Underflow Enable</description>
27128                <bitRange>[3:3]</bitRange>
27129                <access>read-write</access>
27130              </field>
27131              <field>
27132                <name>ERR_INT_EN</name>
27133                <description>Endpoint Error in Transaction Interrupt Enable</description>
27134                <bitRange>[4:4]</bitRange>
27135                <access>read-write</access>
27136              </field>
27137              <field>
27138                <name>DMA_TERMIN_EN</name>
27139                <description>Endpoint DMA Terminated Enable</description>
27140                <bitRange>[5:5]</bitRange>
27141                <access>read-write</access>
27142              </field>
27143            </fields>
27144          </register>
27145          <register>
27146            <name>ARB_EP2_SR</name>
27147            <description>Endpoint Interrupt Enable Register  *1</description>
27148            <addressOffset>0x248</addressOffset>
27149            <size>32</size>
27150            <access>read-write</access>
27151            <resetValue>0x0</resetValue>
27152            <resetMask>0x2F</resetMask>
27153            <fields>
27154              <field>
27155                <name>IN_BUF_FULL</name>
27156                <description>IN Endpoint Local Buffer Full Interrupt</description>
27157                <bitRange>[0:0]</bitRange>
27158                <access>read-write</access>
27159              </field>
27160              <field>
27161                <name>DMA_GNT</name>
27162                <description>Endpoint DMA Grant Interrupt</description>
27163                <bitRange>[1:1]</bitRange>
27164                <access>read-write</access>
27165              </field>
27166              <field>
27167                <name>BUF_OVER</name>
27168                <description>Endpoint Buffer Overflow Interrupt</description>
27169                <bitRange>[2:2]</bitRange>
27170                <access>read-write</access>
27171              </field>
27172              <field>
27173                <name>BUF_UNDER</name>
27174                <description>Endpoint Buffer Underflow Interrupt</description>
27175                <bitRange>[3:3]</bitRange>
27176                <access>read-write</access>
27177              </field>
27178              <field>
27179                <name>DMA_TERMIN</name>
27180                <description>Endpoint DMA Terminated Interrupt</description>
27181                <bitRange>[5:5]</bitRange>
27182                <access>read-write</access>
27183              </field>
27184            </fields>
27185          </register>
27186          <register>
27187            <name>ARB_RW2_WA</name>
27188            <description>Endpoint Write Address value  *1, *2</description>
27189            <addressOffset>0x250</addressOffset>
27190            <size>32</size>
27191            <access>read-write</access>
27192            <resetValue>0x0</resetValue>
27193            <resetMask>0xFF</resetMask>
27194            <fields>
27195              <field>
27196                <name>WA</name>
27197                <description>Write Address for EP</description>
27198                <bitRange>[7:0]</bitRange>
27199                <access>read-write</access>
27200              </field>
27201            </fields>
27202          </register>
27203          <register>
27204            <name>ARB_RW2_WA_MSB</name>
27205            <description>Endpoint Write Address value  *1, *2</description>
27206            <addressOffset>0x254</addressOffset>
27207            <size>32</size>
27208            <access>read-write</access>
27209            <resetValue>0x0</resetValue>
27210            <resetMask>0x1</resetMask>
27211            <fields>
27212              <field>
27213                <name>WA_MSB</name>
27214                <description>Write Address for EP</description>
27215                <bitRange>[0:0]</bitRange>
27216                <access>read-write</access>
27217              </field>
27218            </fields>
27219          </register>
27220          <register>
27221            <name>ARB_RW2_RA</name>
27222            <description>Endpoint Read Address value  *1, *2</description>
27223            <addressOffset>0x258</addressOffset>
27224            <size>32</size>
27225            <access>read-write</access>
27226            <resetValue>0x0</resetValue>
27227            <resetMask>0xFF</resetMask>
27228            <fields>
27229              <field>
27230                <name>RA</name>
27231                <description>Read Address for EP</description>
27232                <bitRange>[7:0]</bitRange>
27233                <access>read-write</access>
27234              </field>
27235            </fields>
27236          </register>
27237          <register>
27238            <name>ARB_RW2_RA_MSB</name>
27239            <description>Endpoint Read Address value  *1, *2</description>
27240            <addressOffset>0x25C</addressOffset>
27241            <size>32</size>
27242            <access>read-write</access>
27243            <resetValue>0x0</resetValue>
27244            <resetMask>0x1</resetMask>
27245            <fields>
27246              <field>
27247                <name>RA_MSB</name>
27248                <description>Read Address for EP</description>
27249                <bitRange>[0:0]</bitRange>
27250                <access>read-write</access>
27251              </field>
27252            </fields>
27253          </register>
27254          <register>
27255            <name>ARB_RW2_DR</name>
27256            <description>Endpoint Data Register</description>
27257            <addressOffset>0x260</addressOffset>
27258            <size>32</size>
27259            <access>read-write</access>
27260            <resetValue>0x0</resetValue>
27261            <resetMask>0x0</resetMask>
27262            <fields>
27263              <field>
27264                <name>DR</name>
27265                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
27266                <bitRange>[7:0]</bitRange>
27267                <access>read-write</access>
27268              </field>
27269            </fields>
27270          </register>
27271          <register>
27272            <name>ARB_CFG</name>
27273            <description>Arbiter Configuration Register  *1</description>
27274            <addressOffset>0x270</addressOffset>
27275            <size>32</size>
27276            <access>read-write</access>
27277            <resetValue>0x0</resetValue>
27278            <resetMask>0xF0</resetMask>
27279            <fields>
27280              <field>
27281                <name>AUTO_MEM</name>
27282                <description>Enables Auto Memory Configuration.  Manual memory configuration by default.</description>
27283                <bitRange>[4:4]</bitRange>
27284                <access>read-write</access>
27285              </field>
27286              <field>
27287                <name>DMA_CFG</name>
27288                <description>DMA Access Configuration.</description>
27289                <bitRange>[6:5]</bitRange>
27290                <access>read-write</access>
27291                <enumeratedValues>
27292                  <enumeratedValue>
27293                    <name>DMA_NONE</name>
27294                    <description>No DMA</description>
27295                    <value>0</value>
27296                  </enumeratedValue>
27297                  <enumeratedValue>
27298                    <name>DMA_MANUAL</name>
27299                    <description>Manual DMA</description>
27300                    <value>1</value>
27301                  </enumeratedValue>
27302                  <enumeratedValue>
27303                    <name>DMA_AUTO</name>
27304                    <description>Auto DMA</description>
27305                    <value>2</value>
27306                  </enumeratedValue>
27307                </enumeratedValues>
27308              </field>
27309              <field>
27310                <name>CFG_CMP</name>
27311                <description>Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required.</description>
27312                <bitRange>[7:7]</bitRange>
27313                <access>read-write</access>
27314              </field>
27315            </fields>
27316          </register>
27317          <register>
27318            <name>USB_CLK_EN</name>
27319            <description>USB Block Clock Enable Register</description>
27320            <addressOffset>0x274</addressOffset>
27321            <size>32</size>
27322            <access>read-write</access>
27323            <resetValue>0x0</resetValue>
27324            <resetMask>0x1</resetMask>
27325            <fields>
27326              <field>
27327                <name>CSR_CLK_EN</name>
27328                <description>Clock Enable for Core Logic clocked by AHB bus clock</description>
27329                <bitRange>[0:0]</bitRange>
27330                <access>read-write</access>
27331              </field>
27332            </fields>
27333          </register>
27334          <register>
27335            <name>ARB_INT_EN</name>
27336            <description>Arbiter Interrupt Enable  *1</description>
27337            <addressOffset>0x278</addressOffset>
27338            <size>32</size>
27339            <access>read-write</access>
27340            <resetValue>0x0</resetValue>
27341            <resetMask>0xFF</resetMask>
27342            <fields>
27343              <field>
27344                <name>EP1_INTR_EN</name>
27345                <description>Enables interrupt for EP1</description>
27346                <bitRange>[0:0]</bitRange>
27347                <access>read-write</access>
27348              </field>
27349              <field>
27350                <name>EP2_INTR_EN</name>
27351                <description>Enables interrupt for EP2</description>
27352                <bitRange>[1:1]</bitRange>
27353                <access>read-write</access>
27354              </field>
27355              <field>
27356                <name>EP3_INTR_EN</name>
27357                <description>Enables interrupt for EP3</description>
27358                <bitRange>[2:2]</bitRange>
27359                <access>read-write</access>
27360              </field>
27361              <field>
27362                <name>EP4_INTR_EN</name>
27363                <description>Enables interrupt for EP4</description>
27364                <bitRange>[3:3]</bitRange>
27365                <access>read-write</access>
27366              </field>
27367              <field>
27368                <name>EP5_INTR_EN</name>
27369                <description>Enables interrupt for EP5</description>
27370                <bitRange>[4:4]</bitRange>
27371                <access>read-write</access>
27372              </field>
27373              <field>
27374                <name>EP6_INTR_EN</name>
27375                <description>Enables interrupt for EP6</description>
27376                <bitRange>[5:5]</bitRange>
27377                <access>read-write</access>
27378              </field>
27379              <field>
27380                <name>EP7_INTR_EN</name>
27381                <description>Enables interrupt for EP7</description>
27382                <bitRange>[6:6]</bitRange>
27383                <access>read-write</access>
27384              </field>
27385              <field>
27386                <name>EP8_INTR_EN</name>
27387                <description>Enables interrupt for EP8</description>
27388                <bitRange>[7:7]</bitRange>
27389                <access>read-write</access>
27390              </field>
27391            </fields>
27392          </register>
27393          <register>
27394            <name>ARB_INT_SR</name>
27395            <description>Arbiter Interrupt Status  *1</description>
27396            <addressOffset>0x27C</addressOffset>
27397            <size>32</size>
27398            <access>read-only</access>
27399            <resetValue>0x0</resetValue>
27400            <resetMask>0xFF</resetMask>
27401            <fields>
27402              <field>
27403                <name>EP1_INTR</name>
27404                <description>Interrupt status for EP1</description>
27405                <bitRange>[0:0]</bitRange>
27406                <access>read-only</access>
27407              </field>
27408              <field>
27409                <name>EP2_INTR</name>
27410                <description>Interrupt status for EP2</description>
27411                <bitRange>[1:1]</bitRange>
27412                <access>read-only</access>
27413              </field>
27414              <field>
27415                <name>EP3_INTR</name>
27416                <description>Interrupt status for EP3</description>
27417                <bitRange>[2:2]</bitRange>
27418                <access>read-only</access>
27419              </field>
27420              <field>
27421                <name>EP4_INTR</name>
27422                <description>Interrupt status for EP4</description>
27423                <bitRange>[3:3]</bitRange>
27424                <access>read-only</access>
27425              </field>
27426              <field>
27427                <name>EP5_INTR</name>
27428                <description>Interrupt status for EP5</description>
27429                <bitRange>[4:4]</bitRange>
27430                <access>read-only</access>
27431              </field>
27432              <field>
27433                <name>EP6_INTR</name>
27434                <description>Interrupt status for EP6</description>
27435                <bitRange>[5:5]</bitRange>
27436                <access>read-only</access>
27437              </field>
27438              <field>
27439                <name>EP7_INTR</name>
27440                <description>Interrupt status for EP7</description>
27441                <bitRange>[6:6]</bitRange>
27442                <access>read-only</access>
27443              </field>
27444              <field>
27445                <name>EP8_INTR</name>
27446                <description>Interrupt status for EP8</description>
27447                <bitRange>[7:7]</bitRange>
27448                <access>read-only</access>
27449              </field>
27450            </fields>
27451          </register>
27452          <register>
27453            <name>ARB_EP3_CFG</name>
27454            <description>Endpoint Configuration Register  *1</description>
27455            <addressOffset>0x280</addressOffset>
27456            <size>32</size>
27457            <access>read-write</access>
27458            <resetValue>0x0</resetValue>
27459            <resetMask>0xF</resetMask>
27460            <fields>
27461              <field>
27462                <name>IN_DATA_RDY</name>
27463                <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
27464                <bitRange>[0:0]</bitRange>
27465                <access>read-write</access>
27466              </field>
27467              <field>
27468                <name>DMA_REQ</name>
27469                <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
27470                <bitRange>[1:1]</bitRange>
27471                <access>read-write</access>
27472              </field>
27473              <field>
27474                <name>CRC_BYPASS</name>
27475                <description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
27476                <bitRange>[2:2]</bitRange>
27477                <access>read-write</access>
27478                <enumeratedValues>
27479                  <enumeratedValue>
27480                    <name>CRC_NORMAL</name>
27481                    <description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
27482                    <value>0</value>
27483                  </enumeratedValue>
27484                  <enumeratedValue>
27485                    <name>CRC_BYPASS</name>
27486                    <description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
27487                    <value>1</value>
27488                  </enumeratedValue>
27489                </enumeratedValues>
27490              </field>
27491              <field>
27492                <name>RESET_PTR</name>
27493                <description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
27494                <bitRange>[3:3]</bitRange>
27495                <access>read-write</access>
27496                <enumeratedValues>
27497                  <enumeratedValue>
27498                    <name>RESET_KRYPTON</name>
27499                    <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
27500                    <value>0</value>
27501                  </enumeratedValue>
27502                  <enumeratedValue>
27503                    <name>RESET_NORMAL</name>
27504                    <description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
27505                    <value>1</value>
27506                  </enumeratedValue>
27507                </enumeratedValues>
27508              </field>
27509            </fields>
27510          </register>
27511          <register>
27512            <name>ARB_EP3_INT_EN</name>
27513            <description>Endpoint Interrupt Enable Register  *1</description>
27514            <addressOffset>0x284</addressOffset>
27515            <size>32</size>
27516            <access>read-write</access>
27517            <resetValue>0x0</resetValue>
27518            <resetMask>0x3F</resetMask>
27519            <fields>
27520              <field>
27521                <name>IN_BUF_FULL_EN</name>
27522                <description>IN Endpoint Local Buffer Full Enable</description>
27523                <bitRange>[0:0]</bitRange>
27524                <access>read-write</access>
27525              </field>
27526              <field>
27527                <name>DMA_GNT_EN</name>
27528                <description>Endpoint DMA Grant Enable</description>
27529                <bitRange>[1:1]</bitRange>
27530                <access>read-write</access>
27531              </field>
27532              <field>
27533                <name>BUF_OVER_EN</name>
27534                <description>Endpoint Buffer Overflow Enable</description>
27535                <bitRange>[2:2]</bitRange>
27536                <access>read-write</access>
27537              </field>
27538              <field>
27539                <name>BUF_UNDER_EN</name>
27540                <description>Endpoint Buffer Underflow Enable</description>
27541                <bitRange>[3:3]</bitRange>
27542                <access>read-write</access>
27543              </field>
27544              <field>
27545                <name>ERR_INT_EN</name>
27546                <description>Endpoint Error in Transaction Interrupt Enable</description>
27547                <bitRange>[4:4]</bitRange>
27548                <access>read-write</access>
27549              </field>
27550              <field>
27551                <name>DMA_TERMIN_EN</name>
27552                <description>Endpoint DMA Terminated Enable</description>
27553                <bitRange>[5:5]</bitRange>
27554                <access>read-write</access>
27555              </field>
27556            </fields>
27557          </register>
27558          <register>
27559            <name>ARB_EP3_SR</name>
27560            <description>Endpoint Interrupt Enable Register  *1</description>
27561            <addressOffset>0x288</addressOffset>
27562            <size>32</size>
27563            <access>read-write</access>
27564            <resetValue>0x0</resetValue>
27565            <resetMask>0x2F</resetMask>
27566            <fields>
27567              <field>
27568                <name>IN_BUF_FULL</name>
27569                <description>IN Endpoint Local Buffer Full Interrupt</description>
27570                <bitRange>[0:0]</bitRange>
27571                <access>read-write</access>
27572              </field>
27573              <field>
27574                <name>DMA_GNT</name>
27575                <description>Endpoint DMA Grant Interrupt</description>
27576                <bitRange>[1:1]</bitRange>
27577                <access>read-write</access>
27578              </field>
27579              <field>
27580                <name>BUF_OVER</name>
27581                <description>Endpoint Buffer Overflow Interrupt</description>
27582                <bitRange>[2:2]</bitRange>
27583                <access>read-write</access>
27584              </field>
27585              <field>
27586                <name>BUF_UNDER</name>
27587                <description>Endpoint Buffer Underflow Interrupt</description>
27588                <bitRange>[3:3]</bitRange>
27589                <access>read-write</access>
27590              </field>
27591              <field>
27592                <name>DMA_TERMIN</name>
27593                <description>Endpoint DMA Terminated Interrupt</description>
27594                <bitRange>[5:5]</bitRange>
27595                <access>read-write</access>
27596              </field>
27597            </fields>
27598          </register>
27599          <register>
27600            <name>ARB_RW3_WA</name>
27601            <description>Endpoint Write Address value  *1, *2</description>
27602            <addressOffset>0x290</addressOffset>
27603            <size>32</size>
27604            <access>read-write</access>
27605            <resetValue>0x0</resetValue>
27606            <resetMask>0xFF</resetMask>
27607            <fields>
27608              <field>
27609                <name>WA</name>
27610                <description>Write Address for EP</description>
27611                <bitRange>[7:0]</bitRange>
27612                <access>read-write</access>
27613              </field>
27614            </fields>
27615          </register>
27616          <register>
27617            <name>ARB_RW3_WA_MSB</name>
27618            <description>Endpoint Write Address value  *1, *2</description>
27619            <addressOffset>0x294</addressOffset>
27620            <size>32</size>
27621            <access>read-write</access>
27622            <resetValue>0x0</resetValue>
27623            <resetMask>0x1</resetMask>
27624            <fields>
27625              <field>
27626                <name>WA_MSB</name>
27627                <description>Write Address for EP</description>
27628                <bitRange>[0:0]</bitRange>
27629                <access>read-write</access>
27630              </field>
27631            </fields>
27632          </register>
27633          <register>
27634            <name>ARB_RW3_RA</name>
27635            <description>Endpoint Read Address value  *1, *2</description>
27636            <addressOffset>0x298</addressOffset>
27637            <size>32</size>
27638            <access>read-write</access>
27639            <resetValue>0x0</resetValue>
27640            <resetMask>0xFF</resetMask>
27641            <fields>
27642              <field>
27643                <name>RA</name>
27644                <description>Read Address for EP</description>
27645                <bitRange>[7:0]</bitRange>
27646                <access>read-write</access>
27647              </field>
27648            </fields>
27649          </register>
27650          <register>
27651            <name>ARB_RW3_RA_MSB</name>
27652            <description>Endpoint Read Address value  *1, *2</description>
27653            <addressOffset>0x29C</addressOffset>
27654            <size>32</size>
27655            <access>read-write</access>
27656            <resetValue>0x0</resetValue>
27657            <resetMask>0x1</resetMask>
27658            <fields>
27659              <field>
27660                <name>RA_MSB</name>
27661                <description>Read Address for EP</description>
27662                <bitRange>[0:0]</bitRange>
27663                <access>read-write</access>
27664              </field>
27665            </fields>
27666          </register>
27667          <register>
27668            <name>ARB_RW3_DR</name>
27669            <description>Endpoint Data Register</description>
27670            <addressOffset>0x2A0</addressOffset>
27671            <size>32</size>
27672            <access>read-write</access>
27673            <resetValue>0x0</resetValue>
27674            <resetMask>0x0</resetMask>
27675            <fields>
27676              <field>
27677                <name>DR</name>
27678                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
27679                <bitRange>[7:0]</bitRange>
27680                <access>read-write</access>
27681              </field>
27682            </fields>
27683          </register>
27684          <register>
27685            <name>CWA</name>
27686            <description>Common Area Write Address  *1</description>
27687            <addressOffset>0x2B0</addressOffset>
27688            <size>32</size>
27689            <access>read-write</access>
27690            <resetValue>0x0</resetValue>
27691            <resetMask>0xFF</resetMask>
27692            <fields>
27693              <field>
27694                <name>CWA</name>
27695                <description>Write Address for Common Area</description>
27696                <bitRange>[7:0]</bitRange>
27697                <access>read-write</access>
27698              </field>
27699            </fields>
27700          </register>
27701          <register>
27702            <name>CWA_MSB</name>
27703            <description>Endpoint Read Address value  *1</description>
27704            <addressOffset>0x2B4</addressOffset>
27705            <size>32</size>
27706            <access>read-write</access>
27707            <resetValue>0x0</resetValue>
27708            <resetMask>0x1</resetMask>
27709            <fields>
27710              <field>
27711                <name>CWA_MSB</name>
27712                <description>Write Address for Common Area</description>
27713                <bitRange>[0:0]</bitRange>
27714                <access>read-write</access>
27715              </field>
27716            </fields>
27717          </register>
27718          <register>
27719            <name>ARB_EP4_CFG</name>
27720            <description>Endpoint Configuration Register  *1</description>
27721            <addressOffset>0x2C0</addressOffset>
27722            <size>32</size>
27723            <access>read-write</access>
27724            <resetValue>0x0</resetValue>
27725            <resetMask>0xF</resetMask>
27726            <fields>
27727              <field>
27728                <name>IN_DATA_RDY</name>
27729                <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
27730                <bitRange>[0:0]</bitRange>
27731                <access>read-write</access>
27732              </field>
27733              <field>
27734                <name>DMA_REQ</name>
27735                <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
27736                <bitRange>[1:1]</bitRange>
27737                <access>read-write</access>
27738              </field>
27739              <field>
27740                <name>CRC_BYPASS</name>
27741                <description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
27742                <bitRange>[2:2]</bitRange>
27743                <access>read-write</access>
27744                <enumeratedValues>
27745                  <enumeratedValue>
27746                    <name>CRC_NORMAL</name>
27747                    <description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
27748                    <value>0</value>
27749                  </enumeratedValue>
27750                  <enumeratedValue>
27751                    <name>CRC_BYPASS</name>
27752                    <description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
27753                    <value>1</value>
27754                  </enumeratedValue>
27755                </enumeratedValues>
27756              </field>
27757              <field>
27758                <name>RESET_PTR</name>
27759                <description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
27760                <bitRange>[3:3]</bitRange>
27761                <access>read-write</access>
27762                <enumeratedValues>
27763                  <enumeratedValue>
27764                    <name>RESET_KRYPTON</name>
27765                    <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
27766                    <value>0</value>
27767                  </enumeratedValue>
27768                  <enumeratedValue>
27769                    <name>RESET_NORMAL</name>
27770                    <description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
27771                    <value>1</value>
27772                  </enumeratedValue>
27773                </enumeratedValues>
27774              </field>
27775            </fields>
27776          </register>
27777          <register>
27778            <name>ARB_EP4_INT_EN</name>
27779            <description>Endpoint Interrupt Enable Register  *1</description>
27780            <addressOffset>0x2C4</addressOffset>
27781            <size>32</size>
27782            <access>read-write</access>
27783            <resetValue>0x0</resetValue>
27784            <resetMask>0x3F</resetMask>
27785            <fields>
27786              <field>
27787                <name>IN_BUF_FULL_EN</name>
27788                <description>IN Endpoint Local Buffer Full Enable</description>
27789                <bitRange>[0:0]</bitRange>
27790                <access>read-write</access>
27791              </field>
27792              <field>
27793                <name>DMA_GNT_EN</name>
27794                <description>Endpoint DMA Grant Enable</description>
27795                <bitRange>[1:1]</bitRange>
27796                <access>read-write</access>
27797              </field>
27798              <field>
27799                <name>BUF_OVER_EN</name>
27800                <description>Endpoint Buffer Overflow Enable</description>
27801                <bitRange>[2:2]</bitRange>
27802                <access>read-write</access>
27803              </field>
27804              <field>
27805                <name>BUF_UNDER_EN</name>
27806                <description>Endpoint Buffer Underflow Enable</description>
27807                <bitRange>[3:3]</bitRange>
27808                <access>read-write</access>
27809              </field>
27810              <field>
27811                <name>ERR_INT_EN</name>
27812                <description>Endpoint Error in Transaction Interrupt Enable</description>
27813                <bitRange>[4:4]</bitRange>
27814                <access>read-write</access>
27815              </field>
27816              <field>
27817                <name>DMA_TERMIN_EN</name>
27818                <description>Endpoint DMA Terminated Enable</description>
27819                <bitRange>[5:5]</bitRange>
27820                <access>read-write</access>
27821              </field>
27822            </fields>
27823          </register>
27824          <register>
27825            <name>ARB_EP4_SR</name>
27826            <description>Endpoint Interrupt Enable Register  *1</description>
27827            <addressOffset>0x2C8</addressOffset>
27828            <size>32</size>
27829            <access>read-write</access>
27830            <resetValue>0x0</resetValue>
27831            <resetMask>0x2F</resetMask>
27832            <fields>
27833              <field>
27834                <name>IN_BUF_FULL</name>
27835                <description>IN Endpoint Local Buffer Full Interrupt</description>
27836                <bitRange>[0:0]</bitRange>
27837                <access>read-write</access>
27838              </field>
27839              <field>
27840                <name>DMA_GNT</name>
27841                <description>Endpoint DMA Grant Interrupt</description>
27842                <bitRange>[1:1]</bitRange>
27843                <access>read-write</access>
27844              </field>
27845              <field>
27846                <name>BUF_OVER</name>
27847                <description>Endpoint Buffer Overflow Interrupt</description>
27848                <bitRange>[2:2]</bitRange>
27849                <access>read-write</access>
27850              </field>
27851              <field>
27852                <name>BUF_UNDER</name>
27853                <description>Endpoint Buffer Underflow Interrupt</description>
27854                <bitRange>[3:3]</bitRange>
27855                <access>read-write</access>
27856              </field>
27857              <field>
27858                <name>DMA_TERMIN</name>
27859                <description>Endpoint DMA Terminated Interrupt</description>
27860                <bitRange>[5:5]</bitRange>
27861                <access>read-write</access>
27862              </field>
27863            </fields>
27864          </register>
27865          <register>
27866            <name>ARB_RW4_WA</name>
27867            <description>Endpoint Write Address value  *1, *2</description>
27868            <addressOffset>0x2D0</addressOffset>
27869            <size>32</size>
27870            <access>read-write</access>
27871            <resetValue>0x0</resetValue>
27872            <resetMask>0xFF</resetMask>
27873            <fields>
27874              <field>
27875                <name>WA</name>
27876                <description>Write Address for EP</description>
27877                <bitRange>[7:0]</bitRange>
27878                <access>read-write</access>
27879              </field>
27880            </fields>
27881          </register>
27882          <register>
27883            <name>ARB_RW4_WA_MSB</name>
27884            <description>Endpoint Write Address value  *1, *2</description>
27885            <addressOffset>0x2D4</addressOffset>
27886            <size>32</size>
27887            <access>read-write</access>
27888            <resetValue>0x0</resetValue>
27889            <resetMask>0x1</resetMask>
27890            <fields>
27891              <field>
27892                <name>WA_MSB</name>
27893                <description>Write Address for EP</description>
27894                <bitRange>[0:0]</bitRange>
27895                <access>read-write</access>
27896              </field>
27897            </fields>
27898          </register>
27899          <register>
27900            <name>ARB_RW4_RA</name>
27901            <description>Endpoint Read Address value  *1, *2</description>
27902            <addressOffset>0x2D8</addressOffset>
27903            <size>32</size>
27904            <access>read-write</access>
27905            <resetValue>0x0</resetValue>
27906            <resetMask>0xFF</resetMask>
27907            <fields>
27908              <field>
27909                <name>RA</name>
27910                <description>Read Address for EP</description>
27911                <bitRange>[7:0]</bitRange>
27912                <access>read-write</access>
27913              </field>
27914            </fields>
27915          </register>
27916          <register>
27917            <name>ARB_RW4_RA_MSB</name>
27918            <description>Endpoint Read Address value  *1, *2</description>
27919            <addressOffset>0x2DC</addressOffset>
27920            <size>32</size>
27921            <access>read-write</access>
27922            <resetValue>0x0</resetValue>
27923            <resetMask>0x1</resetMask>
27924            <fields>
27925              <field>
27926                <name>RA_MSB</name>
27927                <description>Read Address for EP</description>
27928                <bitRange>[0:0]</bitRange>
27929                <access>read-write</access>
27930              </field>
27931            </fields>
27932          </register>
27933          <register>
27934            <name>ARB_RW4_DR</name>
27935            <description>Endpoint Data Register</description>
27936            <addressOffset>0x2E0</addressOffset>
27937            <size>32</size>
27938            <access>read-write</access>
27939            <resetValue>0x0</resetValue>
27940            <resetMask>0x0</resetMask>
27941            <fields>
27942              <field>
27943                <name>DR</name>
27944                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
27945                <bitRange>[7:0]</bitRange>
27946                <access>read-write</access>
27947              </field>
27948            </fields>
27949          </register>
27950          <register>
27951            <name>DMA_THRES</name>
27952            <description>DMA Burst / Threshold Configuration</description>
27953            <addressOffset>0x2F0</addressOffset>
27954            <size>32</size>
27955            <access>read-write</access>
27956            <resetValue>0x0</resetValue>
27957            <resetMask>0xFF</resetMask>
27958            <fields>
27959              <field>
27960                <name>DMA_THS</name>
27961                <description>DMA Threshold count</description>
27962                <bitRange>[7:0]</bitRange>
27963                <access>read-write</access>
27964              </field>
27965            </fields>
27966          </register>
27967          <register>
27968            <name>DMA_THRES_MSB</name>
27969            <description>DMA Burst / Threshold Configuration</description>
27970            <addressOffset>0x2F4</addressOffset>
27971            <size>32</size>
27972            <access>read-write</access>
27973            <resetValue>0x0</resetValue>
27974            <resetMask>0x1</resetMask>
27975            <fields>
27976              <field>
27977                <name>DMA_THS_MSB</name>
27978                <description>DMA Threshold count</description>
27979                <bitRange>[0:0]</bitRange>
27980                <access>read-write</access>
27981              </field>
27982            </fields>
27983          </register>
27984          <register>
27985            <name>ARB_EP5_CFG</name>
27986            <description>Endpoint Configuration Register  *1</description>
27987            <addressOffset>0x300</addressOffset>
27988            <size>32</size>
27989            <access>read-write</access>
27990            <resetValue>0x0</resetValue>
27991            <resetMask>0xF</resetMask>
27992            <fields>
27993              <field>
27994                <name>IN_DATA_RDY</name>
27995                <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
27996                <bitRange>[0:0]</bitRange>
27997                <access>read-write</access>
27998              </field>
27999              <field>
28000                <name>DMA_REQ</name>
28001                <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
28002                <bitRange>[1:1]</bitRange>
28003                <access>read-write</access>
28004              </field>
28005              <field>
28006                <name>CRC_BYPASS</name>
28007                <description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
28008                <bitRange>[2:2]</bitRange>
28009                <access>read-write</access>
28010                <enumeratedValues>
28011                  <enumeratedValue>
28012                    <name>CRC_NORMAL</name>
28013                    <description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
28014                    <value>0</value>
28015                  </enumeratedValue>
28016                  <enumeratedValue>
28017                    <name>CRC_BYPASS</name>
28018                    <description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
28019                    <value>1</value>
28020                  </enumeratedValue>
28021                </enumeratedValues>
28022              </field>
28023              <field>
28024                <name>RESET_PTR</name>
28025                <description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
28026                <bitRange>[3:3]</bitRange>
28027                <access>read-write</access>
28028                <enumeratedValues>
28029                  <enumeratedValue>
28030                    <name>RESET_KRYPTON</name>
28031                    <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
28032                    <value>0</value>
28033                  </enumeratedValue>
28034                  <enumeratedValue>
28035                    <name>RESET_NORMAL</name>
28036                    <description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
28037                    <value>1</value>
28038                  </enumeratedValue>
28039                </enumeratedValues>
28040              </field>
28041            </fields>
28042          </register>
28043          <register>
28044            <name>ARB_EP5_INT_EN</name>
28045            <description>Endpoint Interrupt Enable Register  *1</description>
28046            <addressOffset>0x304</addressOffset>
28047            <size>32</size>
28048            <access>read-write</access>
28049            <resetValue>0x0</resetValue>
28050            <resetMask>0x3F</resetMask>
28051            <fields>
28052              <field>
28053                <name>IN_BUF_FULL_EN</name>
28054                <description>IN Endpoint Local Buffer Full Enable</description>
28055                <bitRange>[0:0]</bitRange>
28056                <access>read-write</access>
28057              </field>
28058              <field>
28059                <name>DMA_GNT_EN</name>
28060                <description>Endpoint DMA Grant Enable</description>
28061                <bitRange>[1:1]</bitRange>
28062                <access>read-write</access>
28063              </field>
28064              <field>
28065                <name>BUF_OVER_EN</name>
28066                <description>Endpoint Buffer Overflow Enable</description>
28067                <bitRange>[2:2]</bitRange>
28068                <access>read-write</access>
28069              </field>
28070              <field>
28071                <name>BUF_UNDER_EN</name>
28072                <description>Endpoint Buffer Underflow Enable</description>
28073                <bitRange>[3:3]</bitRange>
28074                <access>read-write</access>
28075              </field>
28076              <field>
28077                <name>ERR_INT_EN</name>
28078                <description>Endpoint Error in Transaction Interrupt Enable</description>
28079                <bitRange>[4:4]</bitRange>
28080                <access>read-write</access>
28081              </field>
28082              <field>
28083                <name>DMA_TERMIN_EN</name>
28084                <description>Endpoint DMA Terminated Enable</description>
28085                <bitRange>[5:5]</bitRange>
28086                <access>read-write</access>
28087              </field>
28088            </fields>
28089          </register>
28090          <register>
28091            <name>ARB_EP5_SR</name>
28092            <description>Endpoint Interrupt Enable Register  *1</description>
28093            <addressOffset>0x308</addressOffset>
28094            <size>32</size>
28095            <access>read-write</access>
28096            <resetValue>0x0</resetValue>
28097            <resetMask>0x2F</resetMask>
28098            <fields>
28099              <field>
28100                <name>IN_BUF_FULL</name>
28101                <description>IN Endpoint Local Buffer Full Interrupt</description>
28102                <bitRange>[0:0]</bitRange>
28103                <access>read-write</access>
28104              </field>
28105              <field>
28106                <name>DMA_GNT</name>
28107                <description>Endpoint DMA Grant Interrupt</description>
28108                <bitRange>[1:1]</bitRange>
28109                <access>read-write</access>
28110              </field>
28111              <field>
28112                <name>BUF_OVER</name>
28113                <description>Endpoint Buffer Overflow Interrupt</description>
28114                <bitRange>[2:2]</bitRange>
28115                <access>read-write</access>
28116              </field>
28117              <field>
28118                <name>BUF_UNDER</name>
28119                <description>Endpoint Buffer Underflow Interrupt</description>
28120                <bitRange>[3:3]</bitRange>
28121                <access>read-write</access>
28122              </field>
28123              <field>
28124                <name>DMA_TERMIN</name>
28125                <description>Endpoint DMA Terminated Interrupt</description>
28126                <bitRange>[5:5]</bitRange>
28127                <access>read-write</access>
28128              </field>
28129            </fields>
28130          </register>
28131          <register>
28132            <name>ARB_RW5_WA</name>
28133            <description>Endpoint Write Address value  *1, *2</description>
28134            <addressOffset>0x310</addressOffset>
28135            <size>32</size>
28136            <access>read-write</access>
28137            <resetValue>0x0</resetValue>
28138            <resetMask>0xFF</resetMask>
28139            <fields>
28140              <field>
28141                <name>WA</name>
28142                <description>Write Address for EP</description>
28143                <bitRange>[7:0]</bitRange>
28144                <access>read-write</access>
28145              </field>
28146            </fields>
28147          </register>
28148          <register>
28149            <name>ARB_RW5_WA_MSB</name>
28150            <description>Endpoint Write Address value  *1, *2</description>
28151            <addressOffset>0x314</addressOffset>
28152            <size>32</size>
28153            <access>read-write</access>
28154            <resetValue>0x0</resetValue>
28155            <resetMask>0x1</resetMask>
28156            <fields>
28157              <field>
28158                <name>WA_MSB</name>
28159                <description>Write Address for EP</description>
28160                <bitRange>[0:0]</bitRange>
28161                <access>read-write</access>
28162              </field>
28163            </fields>
28164          </register>
28165          <register>
28166            <name>ARB_RW5_RA</name>
28167            <description>Endpoint Read Address value  *1, *2</description>
28168            <addressOffset>0x318</addressOffset>
28169            <size>32</size>
28170            <access>read-write</access>
28171            <resetValue>0x0</resetValue>
28172            <resetMask>0xFF</resetMask>
28173            <fields>
28174              <field>
28175                <name>RA</name>
28176                <description>Read Address for EP</description>
28177                <bitRange>[7:0]</bitRange>
28178                <access>read-write</access>
28179              </field>
28180            </fields>
28181          </register>
28182          <register>
28183            <name>ARB_RW5_RA_MSB</name>
28184            <description>Endpoint Read Address value  *1, *2</description>
28185            <addressOffset>0x31C</addressOffset>
28186            <size>32</size>
28187            <access>read-write</access>
28188            <resetValue>0x0</resetValue>
28189            <resetMask>0x1</resetMask>
28190            <fields>
28191              <field>
28192                <name>RA_MSB</name>
28193                <description>Read Address for EP</description>
28194                <bitRange>[0:0]</bitRange>
28195                <access>read-write</access>
28196              </field>
28197            </fields>
28198          </register>
28199          <register>
28200            <name>ARB_RW5_DR</name>
28201            <description>Endpoint Data Register</description>
28202            <addressOffset>0x320</addressOffset>
28203            <size>32</size>
28204            <access>read-write</access>
28205            <resetValue>0x0</resetValue>
28206            <resetMask>0x0</resetMask>
28207            <fields>
28208              <field>
28209                <name>DR</name>
28210                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
28211                <bitRange>[7:0]</bitRange>
28212                <access>read-write</access>
28213              </field>
28214            </fields>
28215          </register>
28216          <register>
28217            <name>BUS_RST_CNT</name>
28218            <description>Bus Reset Count Register</description>
28219            <addressOffset>0x330</addressOffset>
28220            <size>32</size>
28221            <access>read-write</access>
28222            <resetValue>0xA</resetValue>
28223            <resetMask>0xF</resetMask>
28224            <fields>
28225              <field>
28226                <name>BUS_RST_CNT</name>
28227                <description>Bus Reset Count Length</description>
28228                <bitRange>[3:0]</bitRange>
28229                <access>read-write</access>
28230              </field>
28231            </fields>
28232          </register>
28233          <register>
28234            <name>ARB_EP6_CFG</name>
28235            <description>Endpoint Configuration Register  *1</description>
28236            <addressOffset>0x340</addressOffset>
28237            <size>32</size>
28238            <access>read-write</access>
28239            <resetValue>0x0</resetValue>
28240            <resetMask>0xF</resetMask>
28241            <fields>
28242              <field>
28243                <name>IN_DATA_RDY</name>
28244                <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
28245                <bitRange>[0:0]</bitRange>
28246                <access>read-write</access>
28247              </field>
28248              <field>
28249                <name>DMA_REQ</name>
28250                <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
28251                <bitRange>[1:1]</bitRange>
28252                <access>read-write</access>
28253              </field>
28254              <field>
28255                <name>CRC_BYPASS</name>
28256                <description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
28257                <bitRange>[2:2]</bitRange>
28258                <access>read-write</access>
28259                <enumeratedValues>
28260                  <enumeratedValue>
28261                    <name>CRC_NORMAL</name>
28262                    <description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
28263                    <value>0</value>
28264                  </enumeratedValue>
28265                  <enumeratedValue>
28266                    <name>CRC_BYPASS</name>
28267                    <description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
28268                    <value>1</value>
28269                  </enumeratedValue>
28270                </enumeratedValues>
28271              </field>
28272              <field>
28273                <name>RESET_PTR</name>
28274                <description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
28275                <bitRange>[3:3]</bitRange>
28276                <access>read-write</access>
28277                <enumeratedValues>
28278                  <enumeratedValue>
28279                    <name>RESET_KRYPTON</name>
28280                    <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
28281                    <value>0</value>
28282                  </enumeratedValue>
28283                  <enumeratedValue>
28284                    <name>RESET_NORMAL</name>
28285                    <description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
28286                    <value>1</value>
28287                  </enumeratedValue>
28288                </enumeratedValues>
28289              </field>
28290            </fields>
28291          </register>
28292          <register>
28293            <name>ARB_EP6_INT_EN</name>
28294            <description>Endpoint Interrupt Enable Register  *1</description>
28295            <addressOffset>0x344</addressOffset>
28296            <size>32</size>
28297            <access>read-write</access>
28298            <resetValue>0x0</resetValue>
28299            <resetMask>0x3F</resetMask>
28300            <fields>
28301              <field>
28302                <name>IN_BUF_FULL_EN</name>
28303                <description>IN Endpoint Local Buffer Full Enable</description>
28304                <bitRange>[0:0]</bitRange>
28305                <access>read-write</access>
28306              </field>
28307              <field>
28308                <name>DMA_GNT_EN</name>
28309                <description>Endpoint DMA Grant Enable</description>
28310                <bitRange>[1:1]</bitRange>
28311                <access>read-write</access>
28312              </field>
28313              <field>
28314                <name>BUF_OVER_EN</name>
28315                <description>Endpoint Buffer Overflow Enable</description>
28316                <bitRange>[2:2]</bitRange>
28317                <access>read-write</access>
28318              </field>
28319              <field>
28320                <name>BUF_UNDER_EN</name>
28321                <description>Endpoint Buffer Underflow Enable</description>
28322                <bitRange>[3:3]</bitRange>
28323                <access>read-write</access>
28324              </field>
28325              <field>
28326                <name>ERR_INT_EN</name>
28327                <description>Endpoint Error in Transaction Interrupt Enable</description>
28328                <bitRange>[4:4]</bitRange>
28329                <access>read-write</access>
28330              </field>
28331              <field>
28332                <name>DMA_TERMIN_EN</name>
28333                <description>Endpoint DMA Terminated Enable</description>
28334                <bitRange>[5:5]</bitRange>
28335                <access>read-write</access>
28336              </field>
28337            </fields>
28338          </register>
28339          <register>
28340            <name>ARB_EP6_SR</name>
28341            <description>Endpoint Interrupt Enable Register  *1</description>
28342            <addressOffset>0x348</addressOffset>
28343            <size>32</size>
28344            <access>read-write</access>
28345            <resetValue>0x0</resetValue>
28346            <resetMask>0x2F</resetMask>
28347            <fields>
28348              <field>
28349                <name>IN_BUF_FULL</name>
28350                <description>IN Endpoint Local Buffer Full Interrupt</description>
28351                <bitRange>[0:0]</bitRange>
28352                <access>read-write</access>
28353              </field>
28354              <field>
28355                <name>DMA_GNT</name>
28356                <description>Endpoint DMA Grant Interrupt</description>
28357                <bitRange>[1:1]</bitRange>
28358                <access>read-write</access>
28359              </field>
28360              <field>
28361                <name>BUF_OVER</name>
28362                <description>Endpoint Buffer Overflow Interrupt</description>
28363                <bitRange>[2:2]</bitRange>
28364                <access>read-write</access>
28365              </field>
28366              <field>
28367                <name>BUF_UNDER</name>
28368                <description>Endpoint Buffer Underflow Interrupt</description>
28369                <bitRange>[3:3]</bitRange>
28370                <access>read-write</access>
28371              </field>
28372              <field>
28373                <name>DMA_TERMIN</name>
28374                <description>Endpoint DMA Terminated Interrupt</description>
28375                <bitRange>[5:5]</bitRange>
28376                <access>read-write</access>
28377              </field>
28378            </fields>
28379          </register>
28380          <register>
28381            <name>ARB_RW6_WA</name>
28382            <description>Endpoint Write Address value  *1, *2</description>
28383            <addressOffset>0x350</addressOffset>
28384            <size>32</size>
28385            <access>read-write</access>
28386            <resetValue>0x0</resetValue>
28387            <resetMask>0xFF</resetMask>
28388            <fields>
28389              <field>
28390                <name>WA</name>
28391                <description>Write Address for EP</description>
28392                <bitRange>[7:0]</bitRange>
28393                <access>read-write</access>
28394              </field>
28395            </fields>
28396          </register>
28397          <register>
28398            <name>ARB_RW6_WA_MSB</name>
28399            <description>Endpoint Write Address value  *1, *2</description>
28400            <addressOffset>0x354</addressOffset>
28401            <size>32</size>
28402            <access>read-write</access>
28403            <resetValue>0x0</resetValue>
28404            <resetMask>0x1</resetMask>
28405            <fields>
28406              <field>
28407                <name>WA_MSB</name>
28408                <description>Write Address for EP</description>
28409                <bitRange>[0:0]</bitRange>
28410                <access>read-write</access>
28411              </field>
28412            </fields>
28413          </register>
28414          <register>
28415            <name>ARB_RW6_RA</name>
28416            <description>Endpoint Read Address value  *1, *2</description>
28417            <addressOffset>0x358</addressOffset>
28418            <size>32</size>
28419            <access>read-write</access>
28420            <resetValue>0x0</resetValue>
28421            <resetMask>0xFF</resetMask>
28422            <fields>
28423              <field>
28424                <name>RA</name>
28425                <description>Read Address for EP</description>
28426                <bitRange>[7:0]</bitRange>
28427                <access>read-write</access>
28428              </field>
28429            </fields>
28430          </register>
28431          <register>
28432            <name>ARB_RW6_RA_MSB</name>
28433            <description>Endpoint Read Address value  *1, *2</description>
28434            <addressOffset>0x35C</addressOffset>
28435            <size>32</size>
28436            <access>read-write</access>
28437            <resetValue>0x0</resetValue>
28438            <resetMask>0x1</resetMask>
28439            <fields>
28440              <field>
28441                <name>RA_MSB</name>
28442                <description>Read Address for EP</description>
28443                <bitRange>[0:0]</bitRange>
28444                <access>read-write</access>
28445              </field>
28446            </fields>
28447          </register>
28448          <register>
28449            <name>ARB_RW6_DR</name>
28450            <description>Endpoint Data Register</description>
28451            <addressOffset>0x360</addressOffset>
28452            <size>32</size>
28453            <access>read-write</access>
28454            <resetValue>0x0</resetValue>
28455            <resetMask>0x0</resetMask>
28456            <fields>
28457              <field>
28458                <name>DR</name>
28459                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
28460                <bitRange>[7:0]</bitRange>
28461                <access>read-write</access>
28462              </field>
28463            </fields>
28464          </register>
28465          <register>
28466            <name>ARB_EP7_CFG</name>
28467            <description>Endpoint Configuration Register  *1</description>
28468            <addressOffset>0x380</addressOffset>
28469            <size>32</size>
28470            <access>read-write</access>
28471            <resetValue>0x0</resetValue>
28472            <resetMask>0xF</resetMask>
28473            <fields>
28474              <field>
28475                <name>IN_DATA_RDY</name>
28476                <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
28477                <bitRange>[0:0]</bitRange>
28478                <access>read-write</access>
28479              </field>
28480              <field>
28481                <name>DMA_REQ</name>
28482                <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
28483                <bitRange>[1:1]</bitRange>
28484                <access>read-write</access>
28485              </field>
28486              <field>
28487                <name>CRC_BYPASS</name>
28488                <description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
28489                <bitRange>[2:2]</bitRange>
28490                <access>read-write</access>
28491                <enumeratedValues>
28492                  <enumeratedValue>
28493                    <name>CRC_NORMAL</name>
28494                    <description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
28495                    <value>0</value>
28496                  </enumeratedValue>
28497                  <enumeratedValue>
28498                    <name>CRC_BYPASS</name>
28499                    <description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
28500                    <value>1</value>
28501                  </enumeratedValue>
28502                </enumeratedValues>
28503              </field>
28504              <field>
28505                <name>RESET_PTR</name>
28506                <description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
28507                <bitRange>[3:3]</bitRange>
28508                <access>read-write</access>
28509                <enumeratedValues>
28510                  <enumeratedValue>
28511                    <name>RESET_KRYPTON</name>
28512                    <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
28513                    <value>0</value>
28514                  </enumeratedValue>
28515                  <enumeratedValue>
28516                    <name>RESET_NORMAL</name>
28517                    <description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
28518                    <value>1</value>
28519                  </enumeratedValue>
28520                </enumeratedValues>
28521              </field>
28522            </fields>
28523          </register>
28524          <register>
28525            <name>ARB_EP7_INT_EN</name>
28526            <description>Endpoint Interrupt Enable Register  *1</description>
28527            <addressOffset>0x384</addressOffset>
28528            <size>32</size>
28529            <access>read-write</access>
28530            <resetValue>0x0</resetValue>
28531            <resetMask>0x3F</resetMask>
28532            <fields>
28533              <field>
28534                <name>IN_BUF_FULL_EN</name>
28535                <description>IN Endpoint Local Buffer Full Enable</description>
28536                <bitRange>[0:0]</bitRange>
28537                <access>read-write</access>
28538              </field>
28539              <field>
28540                <name>DMA_GNT_EN</name>
28541                <description>Endpoint DMA Grant Enable</description>
28542                <bitRange>[1:1]</bitRange>
28543                <access>read-write</access>
28544              </field>
28545              <field>
28546                <name>BUF_OVER_EN</name>
28547                <description>Endpoint Buffer Overflow Enable</description>
28548                <bitRange>[2:2]</bitRange>
28549                <access>read-write</access>
28550              </field>
28551              <field>
28552                <name>BUF_UNDER_EN</name>
28553                <description>Endpoint Buffer Underflow Enable</description>
28554                <bitRange>[3:3]</bitRange>
28555                <access>read-write</access>
28556              </field>
28557              <field>
28558                <name>ERR_INT_EN</name>
28559                <description>Endpoint Error in Transaction Interrupt Enable</description>
28560                <bitRange>[4:4]</bitRange>
28561                <access>read-write</access>
28562              </field>
28563              <field>
28564                <name>DMA_TERMIN_EN</name>
28565                <description>Endpoint DMA Terminated Enable</description>
28566                <bitRange>[5:5]</bitRange>
28567                <access>read-write</access>
28568              </field>
28569            </fields>
28570          </register>
28571          <register>
28572            <name>ARB_EP7_SR</name>
28573            <description>Endpoint Interrupt Enable Register  *1</description>
28574            <addressOffset>0x388</addressOffset>
28575            <size>32</size>
28576            <access>read-write</access>
28577            <resetValue>0x0</resetValue>
28578            <resetMask>0x2F</resetMask>
28579            <fields>
28580              <field>
28581                <name>IN_BUF_FULL</name>
28582                <description>IN Endpoint Local Buffer Full Interrupt</description>
28583                <bitRange>[0:0]</bitRange>
28584                <access>read-write</access>
28585              </field>
28586              <field>
28587                <name>DMA_GNT</name>
28588                <description>Endpoint DMA Grant Interrupt</description>
28589                <bitRange>[1:1]</bitRange>
28590                <access>read-write</access>
28591              </field>
28592              <field>
28593                <name>BUF_OVER</name>
28594                <description>Endpoint Buffer Overflow Interrupt</description>
28595                <bitRange>[2:2]</bitRange>
28596                <access>read-write</access>
28597              </field>
28598              <field>
28599                <name>BUF_UNDER</name>
28600                <description>Endpoint Buffer Underflow Interrupt</description>
28601                <bitRange>[3:3]</bitRange>
28602                <access>read-write</access>
28603              </field>
28604              <field>
28605                <name>DMA_TERMIN</name>
28606                <description>Endpoint DMA Terminated Interrupt</description>
28607                <bitRange>[5:5]</bitRange>
28608                <access>read-write</access>
28609              </field>
28610            </fields>
28611          </register>
28612          <register>
28613            <name>ARB_RW7_WA</name>
28614            <description>Endpoint Write Address value  *1, *2</description>
28615            <addressOffset>0x390</addressOffset>
28616            <size>32</size>
28617            <access>read-write</access>
28618            <resetValue>0x0</resetValue>
28619            <resetMask>0xFF</resetMask>
28620            <fields>
28621              <field>
28622                <name>WA</name>
28623                <description>Write Address for EP</description>
28624                <bitRange>[7:0]</bitRange>
28625                <access>read-write</access>
28626              </field>
28627            </fields>
28628          </register>
28629          <register>
28630            <name>ARB_RW7_WA_MSB</name>
28631            <description>Endpoint Write Address value  *1, *2</description>
28632            <addressOffset>0x394</addressOffset>
28633            <size>32</size>
28634            <access>read-write</access>
28635            <resetValue>0x0</resetValue>
28636            <resetMask>0x1</resetMask>
28637            <fields>
28638              <field>
28639                <name>WA_MSB</name>
28640                <description>Write Address for EP</description>
28641                <bitRange>[0:0]</bitRange>
28642                <access>read-write</access>
28643              </field>
28644            </fields>
28645          </register>
28646          <register>
28647            <name>ARB_RW7_RA</name>
28648            <description>Endpoint Read Address value  *1, *2</description>
28649            <addressOffset>0x398</addressOffset>
28650            <size>32</size>
28651            <access>read-write</access>
28652            <resetValue>0x0</resetValue>
28653            <resetMask>0xFF</resetMask>
28654            <fields>
28655              <field>
28656                <name>RA</name>
28657                <description>Read Address for EP</description>
28658                <bitRange>[7:0]</bitRange>
28659                <access>read-write</access>
28660              </field>
28661            </fields>
28662          </register>
28663          <register>
28664            <name>ARB_RW7_RA_MSB</name>
28665            <description>Endpoint Read Address value  *1, *2</description>
28666            <addressOffset>0x39C</addressOffset>
28667            <size>32</size>
28668            <access>read-write</access>
28669            <resetValue>0x0</resetValue>
28670            <resetMask>0x1</resetMask>
28671            <fields>
28672              <field>
28673                <name>RA_MSB</name>
28674                <description>Read Address for EP</description>
28675                <bitRange>[0:0]</bitRange>
28676                <access>read-write</access>
28677              </field>
28678            </fields>
28679          </register>
28680          <register>
28681            <name>ARB_RW7_DR</name>
28682            <description>Endpoint Data Register</description>
28683            <addressOffset>0x3A0</addressOffset>
28684            <size>32</size>
28685            <access>read-write</access>
28686            <resetValue>0x0</resetValue>
28687            <resetMask>0x0</resetMask>
28688            <fields>
28689              <field>
28690                <name>DR</name>
28691                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
28692                <bitRange>[7:0]</bitRange>
28693                <access>read-write</access>
28694              </field>
28695            </fields>
28696          </register>
28697          <register>
28698            <name>ARB_EP8_CFG</name>
28699            <description>Endpoint Configuration Register  *1</description>
28700            <addressOffset>0x3C0</addressOffset>
28701            <size>32</size>
28702            <access>read-write</access>
28703            <resetValue>0x0</resetValue>
28704            <resetMask>0xF</resetMask>
28705            <fields>
28706              <field>
28707                <name>IN_DATA_RDY</name>
28708                <description>Indication that Endpoint Packet Data is Ready in Main memory</description>
28709                <bitRange>[0:0]</bitRange>
28710                <access>read-write</access>
28711              </field>
28712              <field>
28713                <name>DMA_REQ</name>
28714                <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>
28715                <bitRange>[1:1]</bitRange>
28716                <access>read-write</access>
28717              </field>
28718              <field>
28719                <name>CRC_BYPASS</name>
28720                <description>Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware</description>
28721                <bitRange>[2:2]</bitRange>
28722                <access>read-write</access>
28723                <enumeratedValues>
28724                  <enumeratedValue>
28725                    <name>CRC_NORMAL</name>
28726                    <description>No CRC bypass; CRC bytes will be written to memory and Termin will be generated for the CRC byte/s</description>
28727                    <value>0</value>
28728                  </enumeratedValue>
28729                  <enumeratedValue>
28730                    <name>CRC_BYPASS</name>
28731                    <description>CRC Bypass Set; CRC bytes will not be written into memory and Termin will be generated for the last data byte/s</description>
28732                    <value>1</value>
28733                  </enumeratedValue>
28734                </enumeratedValues>
28735              </field>
28736              <field>
28737                <name>RESET_PTR</name>
28738                <description>Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction.</description>
28739                <bitRange>[3:3]</bitRange>
28740                <access>read-write</access>
28741                <enumeratedValues>
28742                  <enumeratedValue>
28743                    <name>RESET_KRYPTON</name>
28744                    <description>Do not Reset Pointer; Krypton Backward compatibility mode</description>
28745                    <value>0</value>
28746                  </enumeratedValue>
28747                  <enumeratedValue>
28748                    <name>RESET_NORMAL</name>
28749                    <description>Reset Pointer; recommended value for reduction of CPU Configuration Writes.</description>
28750                    <value>1</value>
28751                  </enumeratedValue>
28752                </enumeratedValues>
28753              </field>
28754            </fields>
28755          </register>
28756          <register>
28757            <name>ARB_EP8_INT_EN</name>
28758            <description>Endpoint Interrupt Enable Register  *1</description>
28759            <addressOffset>0x3C4</addressOffset>
28760            <size>32</size>
28761            <access>read-write</access>
28762            <resetValue>0x0</resetValue>
28763            <resetMask>0x3F</resetMask>
28764            <fields>
28765              <field>
28766                <name>IN_BUF_FULL_EN</name>
28767                <description>IN Endpoint Local Buffer Full Enable</description>
28768                <bitRange>[0:0]</bitRange>
28769                <access>read-write</access>
28770              </field>
28771              <field>
28772                <name>DMA_GNT_EN</name>
28773                <description>Endpoint DMA Grant Enable</description>
28774                <bitRange>[1:1]</bitRange>
28775                <access>read-write</access>
28776              </field>
28777              <field>
28778                <name>BUF_OVER_EN</name>
28779                <description>Endpoint Buffer Overflow Enable</description>
28780                <bitRange>[2:2]</bitRange>
28781                <access>read-write</access>
28782              </field>
28783              <field>
28784                <name>BUF_UNDER_EN</name>
28785                <description>Endpoint Buffer Underflow Enable</description>
28786                <bitRange>[3:3]</bitRange>
28787                <access>read-write</access>
28788              </field>
28789              <field>
28790                <name>ERR_INT_EN</name>
28791                <description>Endpoint Error in Transaction Interrupt Enable</description>
28792                <bitRange>[4:4]</bitRange>
28793                <access>read-write</access>
28794              </field>
28795              <field>
28796                <name>DMA_TERMIN_EN</name>
28797                <description>Endpoint DMA Terminated Enable</description>
28798                <bitRange>[5:5]</bitRange>
28799                <access>read-write</access>
28800              </field>
28801            </fields>
28802          </register>
28803          <register>
28804            <name>ARB_EP8_SR</name>
28805            <description>Endpoint Interrupt Enable Register  *1</description>
28806            <addressOffset>0x3C8</addressOffset>
28807            <size>32</size>
28808            <access>read-write</access>
28809            <resetValue>0x0</resetValue>
28810            <resetMask>0x2F</resetMask>
28811            <fields>
28812              <field>
28813                <name>IN_BUF_FULL</name>
28814                <description>IN Endpoint Local Buffer Full Interrupt</description>
28815                <bitRange>[0:0]</bitRange>
28816                <access>read-write</access>
28817              </field>
28818              <field>
28819                <name>DMA_GNT</name>
28820                <description>Endpoint DMA Grant Interrupt</description>
28821                <bitRange>[1:1]</bitRange>
28822                <access>read-write</access>
28823              </field>
28824              <field>
28825                <name>BUF_OVER</name>
28826                <description>Endpoint Buffer Overflow Interrupt</description>
28827                <bitRange>[2:2]</bitRange>
28828                <access>read-write</access>
28829              </field>
28830              <field>
28831                <name>BUF_UNDER</name>
28832                <description>Endpoint Buffer Underflow Interrupt</description>
28833                <bitRange>[3:3]</bitRange>
28834                <access>read-write</access>
28835              </field>
28836              <field>
28837                <name>DMA_TERMIN</name>
28838                <description>Endpoint DMA Terminated Interrupt</description>
28839                <bitRange>[5:5]</bitRange>
28840                <access>read-write</access>
28841              </field>
28842            </fields>
28843          </register>
28844          <register>
28845            <name>ARB_RW8_WA</name>
28846            <description>Endpoint Write Address value  *1, *2</description>
28847            <addressOffset>0x3D0</addressOffset>
28848            <size>32</size>
28849            <access>read-write</access>
28850            <resetValue>0x0</resetValue>
28851            <resetMask>0xFF</resetMask>
28852            <fields>
28853              <field>
28854                <name>WA</name>
28855                <description>Write Address for EP</description>
28856                <bitRange>[7:0]</bitRange>
28857                <access>read-write</access>
28858              </field>
28859            </fields>
28860          </register>
28861          <register>
28862            <name>ARB_RW8_WA_MSB</name>
28863            <description>Endpoint Write Address value  *1, *2</description>
28864            <addressOffset>0x3D4</addressOffset>
28865            <size>32</size>
28866            <access>read-write</access>
28867            <resetValue>0x0</resetValue>
28868            <resetMask>0x1</resetMask>
28869            <fields>
28870              <field>
28871                <name>WA_MSB</name>
28872                <description>Write Address for EP</description>
28873                <bitRange>[0:0]</bitRange>
28874                <access>read-write</access>
28875              </field>
28876            </fields>
28877          </register>
28878          <register>
28879            <name>ARB_RW8_RA</name>
28880            <description>Endpoint Read Address value  *1, *2</description>
28881            <addressOffset>0x3D8</addressOffset>
28882            <size>32</size>
28883            <access>read-write</access>
28884            <resetValue>0x0</resetValue>
28885            <resetMask>0xFF</resetMask>
28886            <fields>
28887              <field>
28888                <name>RA</name>
28889                <description>Read Address for EP</description>
28890                <bitRange>[7:0]</bitRange>
28891                <access>read-write</access>
28892              </field>
28893            </fields>
28894          </register>
28895          <register>
28896            <name>ARB_RW8_RA_MSB</name>
28897            <description>Endpoint Read Address value  *1, *2</description>
28898            <addressOffset>0x3DC</addressOffset>
28899            <size>32</size>
28900            <access>read-write</access>
28901            <resetValue>0x0</resetValue>
28902            <resetMask>0x1</resetMask>
28903            <fields>
28904              <field>
28905                <name>RA_MSB</name>
28906                <description>Read Address for EP</description>
28907                <bitRange>[0:0]</bitRange>
28908                <access>read-write</access>
28909              </field>
28910            </fields>
28911          </register>
28912          <register>
28913            <name>ARB_RW8_DR</name>
28914            <description>Endpoint Data Register</description>
28915            <addressOffset>0x3E0</addressOffset>
28916            <size>32</size>
28917            <access>read-write</access>
28918            <resetValue>0x0</resetValue>
28919            <resetMask>0x0</resetMask>
28920            <fields>
28921              <field>
28922                <name>DR</name>
28923                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
28924                <bitRange>[7:0]</bitRange>
28925                <access>read-write</access>
28926              </field>
28927            </fields>
28928          </register>
28929          <register>
28930            <dim>512</dim>
28931            <dimIncrement>4</dimIncrement>
28932            <name>MEM_DATA[%s]</name>
28933            <description>DATA</description>
28934            <addressOffset>0x400</addressOffset>
28935            <size>32</size>
28936            <access>read-write</access>
28937            <resetValue>0x0</resetValue>
28938            <resetMask>0x0</resetMask>
28939            <fields>
28940              <field>
28941                <name>DR</name>
28942                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
28943                <bitRange>[7:0]</bitRange>
28944                <access>read-write</access>
28945              </field>
28946            </fields>
28947          </register>
28948          <register>
28949            <name>SOF16</name>
28950            <description>Start Of Frame Register</description>
28951            <addressOffset>0x1060</addressOffset>
28952            <size>32</size>
28953            <access>read-only</access>
28954            <resetValue>0x0</resetValue>
28955            <resetMask>0x7FF</resetMask>
28956            <fields>
28957              <field>
28958                <name>FRAME_NUMBER16</name>
28959                <description>The frame number (11b)</description>
28960                <bitRange>[10:0]</bitRange>
28961                <access>read-only</access>
28962              </field>
28963            </fields>
28964          </register>
28965          <register>
28966            <name>OSCLK_DR16</name>
28967            <description>Oscillator lock data register</description>
28968            <addressOffset>0x1080</addressOffset>
28969            <size>32</size>
28970            <access>read-only</access>
28971            <resetValue>0x0</resetValue>
28972            <resetMask>0x0</resetMask>
28973            <fields>
28974              <field>
28975                <name>ADDER16</name>
28976                <description>These bits return the oscillator locking circuits adder output.</description>
28977                <bitRange>[14:0]</bitRange>
28978                <access>read-only</access>
28979              </field>
28980            </fields>
28981          </register>
28982          <register>
28983            <name>ARB_RW1_WA16</name>
28984            <description>Endpoint Write Address value  *3</description>
28985            <addressOffset>0x1210</addressOffset>
28986            <size>32</size>
28987            <access>read-write</access>
28988            <resetValue>0x0</resetValue>
28989            <resetMask>0x1FF</resetMask>
28990            <fields>
28991              <field>
28992                <name>WA16</name>
28993                <description>Write Address for EP</description>
28994                <bitRange>[8:0]</bitRange>
28995                <access>read-write</access>
28996              </field>
28997            </fields>
28998          </register>
28999          <register>
29000            <name>ARB_RW1_RA16</name>
29001            <description>Endpoint Read Address value  *3</description>
29002            <addressOffset>0x1218</addressOffset>
29003            <size>32</size>
29004            <access>read-write</access>
29005            <resetValue>0x0</resetValue>
29006            <resetMask>0x1FF</resetMask>
29007            <fields>
29008              <field>
29009                <name>RA16</name>
29010                <description>Read Address for EP</description>
29011                <bitRange>[8:0]</bitRange>
29012                <access>read-write</access>
29013              </field>
29014            </fields>
29015          </register>
29016          <register>
29017            <name>ARB_RW1_DR16</name>
29018            <description>Endpoint Data Register</description>
29019            <addressOffset>0x1220</addressOffset>
29020            <size>32</size>
29021            <access>read-write</access>
29022            <resetValue>0x0</resetValue>
29023            <resetMask>0x0</resetMask>
29024            <fields>
29025              <field>
29026                <name>DR16</name>
29027                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
29028                <bitRange>[15:0]</bitRange>
29029                <access>read-write</access>
29030              </field>
29031            </fields>
29032          </register>
29033          <register>
29034            <name>ARB_RW2_WA16</name>
29035            <description>Endpoint Write Address value  *3</description>
29036            <addressOffset>0x1250</addressOffset>
29037            <size>32</size>
29038            <access>read-write</access>
29039            <resetValue>0x0</resetValue>
29040            <resetMask>0x1FF</resetMask>
29041            <fields>
29042              <field>
29043                <name>WA16</name>
29044                <description>Write Address for EP</description>
29045                <bitRange>[8:0]</bitRange>
29046                <access>read-write</access>
29047              </field>
29048            </fields>
29049          </register>
29050          <register>
29051            <name>ARB_RW2_RA16</name>
29052            <description>Endpoint Read Address value  *3</description>
29053            <addressOffset>0x1258</addressOffset>
29054            <size>32</size>
29055            <access>read-write</access>
29056            <resetValue>0x0</resetValue>
29057            <resetMask>0x1FF</resetMask>
29058            <fields>
29059              <field>
29060                <name>RA16</name>
29061                <description>Read Address for EP</description>
29062                <bitRange>[8:0]</bitRange>
29063                <access>read-write</access>
29064              </field>
29065            </fields>
29066          </register>
29067          <register>
29068            <name>ARB_RW2_DR16</name>
29069            <description>Endpoint Data Register</description>
29070            <addressOffset>0x1260</addressOffset>
29071            <size>32</size>
29072            <access>read-write</access>
29073            <resetValue>0x0</resetValue>
29074            <resetMask>0x0</resetMask>
29075            <fields>
29076              <field>
29077                <name>DR16</name>
29078                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
29079                <bitRange>[15:0]</bitRange>
29080                <access>read-write</access>
29081              </field>
29082            </fields>
29083          </register>
29084          <register>
29085            <name>ARB_RW3_WA16</name>
29086            <description>Endpoint Write Address value  *3</description>
29087            <addressOffset>0x1290</addressOffset>
29088            <size>32</size>
29089            <access>read-write</access>
29090            <resetValue>0x0</resetValue>
29091            <resetMask>0x1FF</resetMask>
29092            <fields>
29093              <field>
29094                <name>WA16</name>
29095                <description>Write Address for EP</description>
29096                <bitRange>[8:0]</bitRange>
29097                <access>read-write</access>
29098              </field>
29099            </fields>
29100          </register>
29101          <register>
29102            <name>ARB_RW3_RA16</name>
29103            <description>Endpoint Read Address value  *3</description>
29104            <addressOffset>0x1298</addressOffset>
29105            <size>32</size>
29106            <access>read-write</access>
29107            <resetValue>0x0</resetValue>
29108            <resetMask>0x1FF</resetMask>
29109            <fields>
29110              <field>
29111                <name>RA16</name>
29112                <description>Read Address for EP</description>
29113                <bitRange>[8:0]</bitRange>
29114                <access>read-write</access>
29115              </field>
29116            </fields>
29117          </register>
29118          <register>
29119            <name>ARB_RW3_DR16</name>
29120            <description>Endpoint Data Register</description>
29121            <addressOffset>0x12A0</addressOffset>
29122            <size>32</size>
29123            <access>read-write</access>
29124            <resetValue>0x0</resetValue>
29125            <resetMask>0x0</resetMask>
29126            <fields>
29127              <field>
29128                <name>DR16</name>
29129                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
29130                <bitRange>[15:0]</bitRange>
29131                <access>read-write</access>
29132              </field>
29133            </fields>
29134          </register>
29135          <register>
29136            <name>CWA16</name>
29137            <description>Common Area Write Address</description>
29138            <addressOffset>0x12B0</addressOffset>
29139            <size>32</size>
29140            <access>read-write</access>
29141            <resetValue>0x0</resetValue>
29142            <resetMask>0x1FF</resetMask>
29143            <fields>
29144              <field>
29145                <name>CWA16</name>
29146                <description>Write Address for Common Area</description>
29147                <bitRange>[8:0]</bitRange>
29148                <access>read-write</access>
29149              </field>
29150            </fields>
29151          </register>
29152          <register>
29153            <name>ARB_RW4_WA16</name>
29154            <description>Endpoint Write Address value  *3</description>
29155            <addressOffset>0x12D0</addressOffset>
29156            <size>32</size>
29157            <access>read-write</access>
29158            <resetValue>0x0</resetValue>
29159            <resetMask>0x1FF</resetMask>
29160            <fields>
29161              <field>
29162                <name>WA16</name>
29163                <description>Write Address for EP</description>
29164                <bitRange>[8:0]</bitRange>
29165                <access>read-write</access>
29166              </field>
29167            </fields>
29168          </register>
29169          <register>
29170            <name>ARB_RW4_RA16</name>
29171            <description>Endpoint Read Address value  *3</description>
29172            <addressOffset>0x12D8</addressOffset>
29173            <size>32</size>
29174            <access>read-write</access>
29175            <resetValue>0x0</resetValue>
29176            <resetMask>0x1FF</resetMask>
29177            <fields>
29178              <field>
29179                <name>RA16</name>
29180                <description>Read Address for EP</description>
29181                <bitRange>[8:0]</bitRange>
29182                <access>read-write</access>
29183              </field>
29184            </fields>
29185          </register>
29186          <register>
29187            <name>ARB_RW4_DR16</name>
29188            <description>Endpoint Data Register</description>
29189            <addressOffset>0x12E0</addressOffset>
29190            <size>32</size>
29191            <access>read-write</access>
29192            <resetValue>0x0</resetValue>
29193            <resetMask>0x0</resetMask>
29194            <fields>
29195              <field>
29196                <name>DR16</name>
29197                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
29198                <bitRange>[15:0]</bitRange>
29199                <access>read-write</access>
29200              </field>
29201            </fields>
29202          </register>
29203          <register>
29204            <name>DMA_THRES16</name>
29205            <description>DMA Burst / Threshold Configuration</description>
29206            <addressOffset>0x12F0</addressOffset>
29207            <size>32</size>
29208            <access>read-write</access>
29209            <resetValue>0x0</resetValue>
29210            <resetMask>0x1FF</resetMask>
29211            <fields>
29212              <field>
29213                <name>DMA_THS16</name>
29214                <description>DMA Threshold count</description>
29215                <bitRange>[8:0]</bitRange>
29216                <access>read-write</access>
29217              </field>
29218            </fields>
29219          </register>
29220          <register>
29221            <name>ARB_RW5_WA16</name>
29222            <description>Endpoint Write Address value  *3</description>
29223            <addressOffset>0x1310</addressOffset>
29224            <size>32</size>
29225            <access>read-write</access>
29226            <resetValue>0x0</resetValue>
29227            <resetMask>0x1FF</resetMask>
29228            <fields>
29229              <field>
29230                <name>WA16</name>
29231                <description>Write Address for EP</description>
29232                <bitRange>[8:0]</bitRange>
29233                <access>read-write</access>
29234              </field>
29235            </fields>
29236          </register>
29237          <register>
29238            <name>ARB_RW5_RA16</name>
29239            <description>Endpoint Read Address value  *3</description>
29240            <addressOffset>0x1318</addressOffset>
29241            <size>32</size>
29242            <access>read-write</access>
29243            <resetValue>0x0</resetValue>
29244            <resetMask>0x1FF</resetMask>
29245            <fields>
29246              <field>
29247                <name>RA16</name>
29248                <description>Read Address for EP</description>
29249                <bitRange>[8:0]</bitRange>
29250                <access>read-write</access>
29251              </field>
29252            </fields>
29253          </register>
29254          <register>
29255            <name>ARB_RW5_DR16</name>
29256            <description>Endpoint Data Register</description>
29257            <addressOffset>0x1320</addressOffset>
29258            <size>32</size>
29259            <access>read-write</access>
29260            <resetValue>0x0</resetValue>
29261            <resetMask>0x0</resetMask>
29262            <fields>
29263              <field>
29264                <name>DR16</name>
29265                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
29266                <bitRange>[15:0]</bitRange>
29267                <access>read-write</access>
29268              </field>
29269            </fields>
29270          </register>
29271          <register>
29272            <name>ARB_RW6_WA16</name>
29273            <description>Endpoint Write Address value  *3</description>
29274            <addressOffset>0x1350</addressOffset>
29275            <size>32</size>
29276            <access>read-write</access>
29277            <resetValue>0x0</resetValue>
29278            <resetMask>0x1FF</resetMask>
29279            <fields>
29280              <field>
29281                <name>WA16</name>
29282                <description>Write Address for EP</description>
29283                <bitRange>[8:0]</bitRange>
29284                <access>read-write</access>
29285              </field>
29286            </fields>
29287          </register>
29288          <register>
29289            <name>ARB_RW6_RA16</name>
29290            <description>Endpoint Read Address value  *3</description>
29291            <addressOffset>0x1358</addressOffset>
29292            <size>32</size>
29293            <access>read-write</access>
29294            <resetValue>0x0</resetValue>
29295            <resetMask>0x1FF</resetMask>
29296            <fields>
29297              <field>
29298                <name>RA16</name>
29299                <description>Read Address for EP</description>
29300                <bitRange>[8:0]</bitRange>
29301                <access>read-write</access>
29302              </field>
29303            </fields>
29304          </register>
29305          <register>
29306            <name>ARB_RW6_DR16</name>
29307            <description>Endpoint Data Register</description>
29308            <addressOffset>0x1360</addressOffset>
29309            <size>32</size>
29310            <access>read-write</access>
29311            <resetValue>0x0</resetValue>
29312            <resetMask>0x0</resetMask>
29313            <fields>
29314              <field>
29315                <name>DR16</name>
29316                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
29317                <bitRange>[15:0]</bitRange>
29318                <access>read-write</access>
29319              </field>
29320            </fields>
29321          </register>
29322          <register>
29323            <name>ARB_RW7_WA16</name>
29324            <description>Endpoint Write Address value  *3</description>
29325            <addressOffset>0x1390</addressOffset>
29326            <size>32</size>
29327            <access>read-write</access>
29328            <resetValue>0x0</resetValue>
29329            <resetMask>0x1FF</resetMask>
29330            <fields>
29331              <field>
29332                <name>WA16</name>
29333                <description>Write Address for EP</description>
29334                <bitRange>[8:0]</bitRange>
29335                <access>read-write</access>
29336              </field>
29337            </fields>
29338          </register>
29339          <register>
29340            <name>ARB_RW7_RA16</name>
29341            <description>Endpoint Read Address value  *3</description>
29342            <addressOffset>0x1398</addressOffset>
29343            <size>32</size>
29344            <access>read-write</access>
29345            <resetValue>0x0</resetValue>
29346            <resetMask>0x1FF</resetMask>
29347            <fields>
29348              <field>
29349                <name>RA16</name>
29350                <description>Read Address for EP</description>
29351                <bitRange>[8:0]</bitRange>
29352                <access>read-write</access>
29353              </field>
29354            </fields>
29355          </register>
29356          <register>
29357            <name>ARB_RW7_DR16</name>
29358            <description>Endpoint Data Register</description>
29359            <addressOffset>0x13A0</addressOffset>
29360            <size>32</size>
29361            <access>read-write</access>
29362            <resetValue>0x0</resetValue>
29363            <resetMask>0x0</resetMask>
29364            <fields>
29365              <field>
29366                <name>DR16</name>
29367                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
29368                <bitRange>[15:0]</bitRange>
29369                <access>read-write</access>
29370              </field>
29371            </fields>
29372          </register>
29373          <register>
29374            <name>ARB_RW8_WA16</name>
29375            <description>Endpoint Write Address value  *3</description>
29376            <addressOffset>0x13D0</addressOffset>
29377            <size>32</size>
29378            <access>read-write</access>
29379            <resetValue>0x0</resetValue>
29380            <resetMask>0x1FF</resetMask>
29381            <fields>
29382              <field>
29383                <name>WA16</name>
29384                <description>Write Address for EP</description>
29385                <bitRange>[8:0]</bitRange>
29386                <access>read-write</access>
29387              </field>
29388            </fields>
29389          </register>
29390          <register>
29391            <name>ARB_RW8_RA16</name>
29392            <description>Endpoint Read Address value  *3</description>
29393            <addressOffset>0x13D8</addressOffset>
29394            <size>32</size>
29395            <access>read-write</access>
29396            <resetValue>0x0</resetValue>
29397            <resetMask>0x1FF</resetMask>
29398            <fields>
29399              <field>
29400                <name>RA16</name>
29401                <description>Read Address for EP</description>
29402                <bitRange>[8:0]</bitRange>
29403                <access>read-write</access>
29404              </field>
29405            </fields>
29406          </register>
29407          <register>
29408            <name>ARB_RW8_DR16</name>
29409            <description>Endpoint Data Register</description>
29410            <addressOffset>0x13E0</addressOffset>
29411            <size>32</size>
29412            <access>read-write</access>
29413            <resetValue>0x0</resetValue>
29414            <resetMask>0x0</resetMask>
29415            <fields>
29416              <field>
29417                <name>DR16</name>
29418                <description>Data Register for EP ; This register is linked to the memory, hence reset value is undefined</description>
29419                <bitRange>[15:0]</bitRange>
29420                <access>read-write</access>
29421              </field>
29422            </fields>
29423          </register>
29424        </cluster>
29425        <cluster>
29426          <name>USBLPM</name>
29427          <description>USB Device LPM and PHY Test</description>
29428          <addressOffset>0x00002000</addressOffset>
29429          <register>
29430            <name>POWER_CTL</name>
29431            <description>Power Control Register</description>
29432            <addressOffset>0x0</addressOffset>
29433            <size>32</size>
29434            <access>read-write</access>
29435            <resetValue>0x0</resetValue>
29436            <resetMask>0x303F0004</resetMask>
29437            <fields>
29438              <field>
29439                <name>SUSPEND</name>
29440                <description>Put PHY into Suspend mode.  If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep).
29441Note:
29442- This bit is invalid if the HOST bit of the Host Control 0 Register (HOST_CTL0) is '1'.</description>
29443                <bitRange>[2:2]</bitRange>
29444                <access>read-write</access>
29445              </field>
29446              <field>
29447                <name>DP_UP_EN</name>
29448                <description>Enables the pull up on the DP.
29449'0' : Disable.
29450'1' : Enable.</description>
29451                <bitRange>[16:16]</bitRange>
29452                <access>read-write</access>
29453              </field>
29454              <field>
29455                <name>DP_BIG</name>
29456                <description>Select the resister value if POWER_CTL.DP_EN='1'. This bit is valid in GPIO.
29457'0' : The resister value is from 900 to1575Ohmpull up on the DP.
29458'1' : The resister value is from 1425 to 3090Ohmpull up on the DP</description>
29459                <bitRange>[17:17]</bitRange>
29460                <access>read-write</access>
29461              </field>
29462              <field>
29463                <name>DP_DOWN_EN</name>
29464                <description>Enables the ~15k pull down on the DP.</description>
29465                <bitRange>[18:18]</bitRange>
29466                <access>read-write</access>
29467              </field>
29468              <field>
29469                <name>DM_UP_EN</name>
29470                <description>Enables the pull up on the DM. The bit is valid in GPIO. The pull up resistor is disabled in not GPIO.
29471'0' : Disable.
29472'1' : Enable.</description>
29473                <bitRange>[19:19]</bitRange>
29474                <access>read-write</access>
29475              </field>
29476              <field>
29477                <name>DM_BIG</name>
29478                <description>Select the resister value if POWER_CTL.DM_EN='1'. This bit is valid in GPIO.
29479'0' : The resister value is from 900 to1575Ohmpull up on the DM.
29480'1' : The resister value is from 1425 to 3090Ohmpull up on the DM</description>
29481                <bitRange>[20:20]</bitRange>
29482                <access>read-write</access>
29483              </field>
29484              <field>
29485                <name>DM_DOWN_EN</name>
29486                <description>Enables the ~15k pull down on the DP.</description>
29487                <bitRange>[21:21]</bitRange>
29488                <access>read-write</access>
29489              </field>
29490              <field>
29491                <name>ENABLE_DPO</name>
29492                <description>Enables the single ended receiver on D+.</description>
29493                <bitRange>[28:28]</bitRange>
29494                <access>read-write</access>
29495              </field>
29496              <field>
29497                <name>ENABLE_DMO</name>
29498                <description>Enables the signle ended receiver on D-.</description>
29499                <bitRange>[29:29]</bitRange>
29500                <access>read-write</access>
29501              </field>
29502            </fields>
29503          </register>
29504          <register>
29505            <name>USBIO_CTL</name>
29506            <description>USB IO Control Register</description>
29507            <addressOffset>0x8</addressOffset>
29508            <size>32</size>
29509            <access>read-write</access>
29510            <resetValue>0x0</resetValue>
29511            <resetMask>0x3F</resetMask>
29512            <fields>
29513              <field>
29514                <name>DM_P</name>
29515                <description>The GPIO Drive Mode for DP IO pad. This field only applies if USBIO_CR1.IOMODE =1. Data comes from the corresponding GPIO.DR register.</description>
29516                <bitRange>[2:0]</bitRange>
29517                <access>read-write</access>
29518                <enumeratedValues>
29519                  <enumeratedValue>
29520                    <name>OFF</name>
29521                    <description>Mode 0: Output buffer off (high Z). Input buffer off.</description>
29522                    <value>0</value>
29523                  </enumeratedValue>
29524                  <enumeratedValue>
29525                    <name>INPUT</name>
29526                    <description>Mode 1: Output buffer off (high Z). Input buffer on.
29527
29528Other values, not supported.</description>
29529                    <value>1</value>
29530                  </enumeratedValue>
29531                </enumeratedValues>
29532              </field>
29533              <field>
29534                <name>DM_M</name>
29535                <description>The GPIO Drive Mode for DM IO pad.</description>
29536                <bitRange>[5:3]</bitRange>
29537                <access>read-write</access>
29538              </field>
29539            </fields>
29540          </register>
29541          <register>
29542            <name>FLOW_CTL</name>
29543            <description>Flow Control Register</description>
29544            <addressOffset>0xC</addressOffset>
29545            <size>32</size>
29546            <access>read-write</access>
29547            <resetValue>0x0</resetValue>
29548            <resetMask>0xFF</resetMask>
29549            <fields>
29550              <field>
29551                <name>EP1_ERR_RESP</name>
29552                <description>End Point 1 error response
295530: do nothing (backward compatibility mode)
295541: if this is an IN EP and an underflow occurs then cause a CRC error, if this is an OUT EP and an overflow occurs then send a NAK</description>
29555                <bitRange>[0:0]</bitRange>
29556                <access>read-write</access>
29557              </field>
29558              <field>
29559                <name>EP2_ERR_RESP</name>
29560                <description>End Point 2 error response</description>
29561                <bitRange>[1:1]</bitRange>
29562                <access>read-write</access>
29563              </field>
29564              <field>
29565                <name>EP3_ERR_RESP</name>
29566                <description>End Point 3 error response</description>
29567                <bitRange>[2:2]</bitRange>
29568                <access>read-write</access>
29569              </field>
29570              <field>
29571                <name>EP4_ERR_RESP</name>
29572                <description>End Point 4 error response</description>
29573                <bitRange>[3:3]</bitRange>
29574                <access>read-write</access>
29575              </field>
29576              <field>
29577                <name>EP5_ERR_RESP</name>
29578                <description>End Point 5 error response</description>
29579                <bitRange>[4:4]</bitRange>
29580                <access>read-write</access>
29581              </field>
29582              <field>
29583                <name>EP6_ERR_RESP</name>
29584                <description>End Point 6 error response</description>
29585                <bitRange>[5:5]</bitRange>
29586                <access>read-write</access>
29587              </field>
29588              <field>
29589                <name>EP7_ERR_RESP</name>
29590                <description>End Point 7 error response</description>
29591                <bitRange>[6:6]</bitRange>
29592                <access>read-write</access>
29593              </field>
29594              <field>
29595                <name>EP8_ERR_RESP</name>
29596                <description>End Point 8 error response</description>
29597                <bitRange>[7:7]</bitRange>
29598                <access>read-write</access>
29599              </field>
29600            </fields>
29601          </register>
29602          <register>
29603            <name>LPM_CTL</name>
29604            <description>LPM Control Register</description>
29605            <addressOffset>0x10</addressOffset>
29606            <size>32</size>
29607            <access>read-write</access>
29608            <resetValue>0x0</resetValue>
29609            <resetMask>0x17</resetMask>
29610            <fields>
29611              <field>
29612                <name>LPM_EN</name>
29613                <description>LPM enable
296140: Disabled, LPM token will not get a response (backward compatibility mode)
296151: Enable, LPM token will get a handshake response (ACK, STALL, NYET or NAK)
29616       A STALL will be sent if the bLinkState is not 0001b
29617       A NYET, NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below</description>
29618                <bitRange>[0:0]</bitRange>
29619                <access>read-write</access>
29620              </field>
29621              <field>
29622                <name>LPM_ACK_RESP</name>
29623                <description>LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request
296240: a LPM token will get a NYET or NAK (depending on NYET_EN bit below) response and the device will NOT go to a low power mode
296251: a LPM token will get an ACK response and the device will go to the requested low power mode</description>
29626                <bitRange>[1:1]</bitRange>
29627                <access>read-write</access>
29628              </field>
29629              <field>
29630                <name>NYET_EN</name>
29631                <description>Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0).
296320: a LPM token will get an NAK response (indicating a CRC error),  the host is expected to repeat the LPM token.
296331: a LPM token will get a NYET response</description>
29634                <bitRange>[2:2]</bitRange>
29635                <access>read-write</access>
29636              </field>
29637              <field>
29638                <name>SUB_RESP</name>
29639                <description>Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs.</description>
29640                <bitRange>[4:4]</bitRange>
29641                <access>read-write</access>
29642              </field>
29643            </fields>
29644          </register>
29645          <register>
29646            <name>LPM_STAT</name>
29647            <description>LPM Status register</description>
29648            <addressOffset>0x14</addressOffset>
29649            <size>32</size>
29650            <access>read-only</access>
29651            <resetValue>0x0</resetValue>
29652            <resetMask>0x1F</resetMask>
29653            <fields>
29654              <field>
29655                <name>LPM_BESL</name>
29656                <description>Best Effort Service Latency
29657This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor.</description>
29658                <bitRange>[3:0]</bitRange>
29659                <access>read-only</access>
29660              </field>
29661              <field>
29662                <name>LPM_REMOTEWAKE</name>
29663                <description>0: Device is prohibited from initiating a remote wake
296641: Device is allow to wake the host</description>
29665                <bitRange>[4:4]</bitRange>
29666                <access>read-only</access>
29667              </field>
29668            </fields>
29669          </register>
29670          <register>
29671            <name>INTR_SIE</name>
29672            <description>USB SOF, BUS RESET and EP0 Interrupt Status</description>
29673            <addressOffset>0x20</addressOffset>
29674            <size>32</size>
29675            <access>read-write</access>
29676            <resetValue>0x0</resetValue>
29677            <resetMask>0x1F</resetMask>
29678            <fields>
29679              <field>
29680                <name>SOF_INTR</name>
29681                <description>Interrupt status for USB SOF</description>
29682                <bitRange>[0:0]</bitRange>
29683                <access>read-write</access>
29684              </field>
29685              <field>
29686                <name>BUS_RESET_INTR</name>
29687                <description>Interrupt status for BUS RESET</description>
29688                <bitRange>[1:1]</bitRange>
29689                <access>read-write</access>
29690              </field>
29691              <field>
29692                <name>EP0_INTR</name>
29693                <description>Interrupt status for EP0</description>
29694                <bitRange>[2:2]</bitRange>
29695                <access>read-write</access>
29696              </field>
29697              <field>
29698                <name>LPM_INTR</name>
29699                <description>Interrupt status for LPM  (Link Power Management, L1 entry)</description>
29700                <bitRange>[3:3]</bitRange>
29701                <access>read-write</access>
29702              </field>
29703              <field>
29704                <name>RESUME_INTR</name>
29705                <description>Interrupt status for Resume</description>
29706                <bitRange>[4:4]</bitRange>
29707                <access>read-write</access>
29708              </field>
29709            </fields>
29710          </register>
29711          <register>
29712            <name>INTR_SIE_SET</name>
29713            <description>USB SOF, BUS RESET and EP0 Interrupt Set</description>
29714            <addressOffset>0x24</addressOffset>
29715            <size>32</size>
29716            <access>read-write</access>
29717            <resetValue>0x0</resetValue>
29718            <resetMask>0x1F</resetMask>
29719            <fields>
29720              <field>
29721                <name>SOF_INTR_SET</name>
29722                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
29723                <bitRange>[0:0]</bitRange>
29724                <access>read-write</access>
29725              </field>
29726              <field>
29727                <name>BUS_RESET_INTR_SET</name>
29728                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
29729                <bitRange>[1:1]</bitRange>
29730                <access>read-write</access>
29731              </field>
29732              <field>
29733                <name>EP0_INTR_SET</name>
29734                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
29735                <bitRange>[2:2]</bitRange>
29736                <access>read-write</access>
29737              </field>
29738              <field>
29739                <name>LPM_INTR_SET</name>
29740                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
29741                <bitRange>[3:3]</bitRange>
29742                <access>read-write</access>
29743              </field>
29744              <field>
29745                <name>RESUME_INTR_SET</name>
29746                <description>Write with '1' to set corresponding bit in interrupt request register.</description>
29747                <bitRange>[4:4]</bitRange>
29748                <access>read-write</access>
29749              </field>
29750            </fields>
29751          </register>
29752          <register>
29753            <name>INTR_SIE_MASK</name>
29754            <description>USB SOF, BUS RESET and EP0 Interrupt Mask</description>
29755            <addressOffset>0x28</addressOffset>
29756            <size>32</size>
29757            <access>read-write</access>
29758            <resetValue>0x0</resetValue>
29759            <resetMask>0x1F</resetMask>
29760            <fields>
29761              <field>
29762                <name>SOF_INTR_MASK</name>
29763                <description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
29764                <bitRange>[0:0]</bitRange>
29765                <access>read-write</access>
29766              </field>
29767              <field>
29768                <name>BUS_RESET_INTR_MASK</name>
29769                <description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
29770                <bitRange>[1:1]</bitRange>
29771                <access>read-write</access>
29772              </field>
29773              <field>
29774                <name>EP0_INTR_MASK</name>
29775                <description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
29776                <bitRange>[2:2]</bitRange>
29777                <access>read-write</access>
29778              </field>
29779              <field>
29780                <name>LPM_INTR_MASK</name>
29781                <description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
29782                <bitRange>[3:3]</bitRange>
29783                <access>read-write</access>
29784              </field>
29785              <field>
29786                <name>RESUME_INTR_MASK</name>
29787                <description>Set to 1 to enable interrupt corresponding to interrupt request register</description>
29788                <bitRange>[4:4]</bitRange>
29789                <access>read-write</access>
29790              </field>
29791            </fields>
29792          </register>
29793          <register>
29794            <name>INTR_SIE_MASKED</name>
29795            <description>USB SOF, BUS RESET and EP0 Interrupt Masked</description>
29796            <addressOffset>0x2C</addressOffset>
29797            <size>32</size>
29798            <access>read-only</access>
29799            <resetValue>0x0</resetValue>
29800            <resetMask>0x1F</resetMask>
29801            <fields>
29802              <field>
29803                <name>SOF_INTR_MASKED</name>
29804                <description>Logical and of corresponding request and mask bits.</description>
29805                <bitRange>[0:0]</bitRange>
29806                <access>read-only</access>
29807              </field>
29808              <field>
29809                <name>BUS_RESET_INTR_MASKED</name>
29810                <description>Logical and of corresponding request and mask bits.</description>
29811                <bitRange>[1:1]</bitRange>
29812                <access>read-only</access>
29813              </field>
29814              <field>
29815                <name>EP0_INTR_MASKED</name>
29816                <description>Logical and of corresponding request and mask bits.</description>
29817                <bitRange>[2:2]</bitRange>
29818                <access>read-only</access>
29819              </field>
29820              <field>
29821                <name>LPM_INTR_MASKED</name>
29822                <description>Logical and of corresponding request and mask bits.</description>
29823                <bitRange>[3:3]</bitRange>
29824                <access>read-only</access>
29825              </field>
29826              <field>
29827                <name>RESUME_INTR_MASKED</name>
29828                <description>Logical and of corresponding request and mask bits.</description>
29829                <bitRange>[4:4]</bitRange>
29830                <access>read-only</access>
29831              </field>
29832            </fields>
29833          </register>
29834          <register>
29835            <name>INTR_LVL_SEL</name>
29836            <description>Select interrupt level for each interrupt source</description>
29837            <addressOffset>0x30</addressOffset>
29838            <size>32</size>
29839            <access>read-write</access>
29840            <resetValue>0x0</resetValue>
29841            <resetMask>0xFFFFC3FF</resetMask>
29842            <fields>
29843              <field>
29844                <name>SOF_LVL_SEL</name>
29845                <description>USB SOF Interrupt level select</description>
29846                <bitRange>[1:0]</bitRange>
29847                <access>read-write</access>
29848                <enumeratedValues>
29849                  <enumeratedValue>
29850                    <name>HI</name>
29851                    <description>High priority interrupt</description>
29852                    <value>0</value>
29853                  </enumeratedValue>
29854                  <enumeratedValue>
29855                    <name>MED</name>
29856                    <description>Medium priority interrupt</description>
29857                    <value>1</value>
29858                  </enumeratedValue>
29859                  <enumeratedValue>
29860                    <name>LO</name>
29861                    <description>Low priority interrupt</description>
29862                    <value>2</value>
29863                  </enumeratedValue>
29864                  <enumeratedValue>
29865                    <name>RSVD</name>
29866                    <description>illegal</description>
29867                    <value>3</value>
29868                  </enumeratedValue>
29869                </enumeratedValues>
29870              </field>
29871              <field>
29872                <name>BUS_RESET_LVL_SEL</name>
29873                <description>BUS RESET Interrupt level select</description>
29874                <bitRange>[3:2]</bitRange>
29875                <access>read-write</access>
29876              </field>
29877              <field>
29878                <name>EP0_LVL_SEL</name>
29879                <description>EP0 Interrupt level select</description>
29880                <bitRange>[5:4]</bitRange>
29881                <access>read-write</access>
29882              </field>
29883              <field>
29884                <name>LPM_LVL_SEL</name>
29885                <description>LPM Interrupt level select</description>
29886                <bitRange>[7:6]</bitRange>
29887                <access>read-write</access>
29888              </field>
29889              <field>
29890                <name>RESUME_LVL_SEL</name>
29891                <description>Resume Interrupt level select</description>
29892                <bitRange>[9:8]</bitRange>
29893                <access>read-write</access>
29894              </field>
29895              <field>
29896                <name>ARB_EP_LVL_SEL</name>
29897                <description>Arbiter Endpoint Interrupt level select</description>
29898                <bitRange>[15:14]</bitRange>
29899                <access>read-write</access>
29900              </field>
29901              <field>
29902                <name>EP1_LVL_SEL</name>
29903                <description>EP1 Interrupt level select</description>
29904                <bitRange>[17:16]</bitRange>
29905                <access>read-write</access>
29906              </field>
29907              <field>
29908                <name>EP2_LVL_SEL</name>
29909                <description>EP2 Interrupt level select</description>
29910                <bitRange>[19:18]</bitRange>
29911                <access>read-write</access>
29912              </field>
29913              <field>
29914                <name>EP3_LVL_SEL</name>
29915                <description>EP3 Interrupt level select</description>
29916                <bitRange>[21:20]</bitRange>
29917                <access>read-write</access>
29918              </field>
29919              <field>
29920                <name>EP4_LVL_SEL</name>
29921                <description>EP4 Interrupt level select</description>
29922                <bitRange>[23:22]</bitRange>
29923                <access>read-write</access>
29924              </field>
29925              <field>
29926                <name>EP5_LVL_SEL</name>
29927                <description>EP5 Interrupt level select</description>
29928                <bitRange>[25:24]</bitRange>
29929                <access>read-write</access>
29930              </field>
29931              <field>
29932                <name>EP6_LVL_SEL</name>
29933                <description>EP6 Interrupt level select</description>
29934                <bitRange>[27:26]</bitRange>
29935                <access>read-write</access>
29936              </field>
29937              <field>
29938                <name>EP7_LVL_SEL</name>
29939                <description>EP7 Interrupt level select</description>
29940                <bitRange>[29:28]</bitRange>
29941                <access>read-write</access>
29942              </field>
29943              <field>
29944                <name>EP8_LVL_SEL</name>
29945                <description>EP8 Interrupt level select</description>
29946                <bitRange>[31:30]</bitRange>
29947                <access>read-write</access>
29948              </field>
29949            </fields>
29950          </register>
29951          <register>
29952            <name>INTR_CAUSE_HI</name>
29953            <description>High priority interrupt Cause register</description>
29954            <addressOffset>0x34</addressOffset>
29955            <size>32</size>
29956            <access>read-only</access>
29957            <resetValue>0x0</resetValue>
29958            <resetMask>0xFF9F</resetMask>
29959            <fields>
29960              <field>
29961                <name>SOF_INTR</name>
29962                <description>USB SOF Interrupt</description>
29963                <bitRange>[0:0]</bitRange>
29964                <access>read-only</access>
29965              </field>
29966              <field>
29967                <name>BUS_RESET_INTR</name>
29968                <description>BUS RESET Interrupt</description>
29969                <bitRange>[1:1]</bitRange>
29970                <access>read-only</access>
29971              </field>
29972              <field>
29973                <name>EP0_INTR</name>
29974                <description>EP0 Interrupt</description>
29975                <bitRange>[2:2]</bitRange>
29976                <access>read-only</access>
29977              </field>
29978              <field>
29979                <name>LPM_INTR</name>
29980                <description>LPM Interrupt</description>
29981                <bitRange>[3:3]</bitRange>
29982                <access>read-only</access>
29983              </field>
29984              <field>
29985                <name>RESUME_INTR</name>
29986                <description>Resume Interrupt</description>
29987                <bitRange>[4:4]</bitRange>
29988                <access>read-only</access>
29989              </field>
29990              <field>
29991                <name>ARB_EP_INTR</name>
29992                <description>Arbiter Endpoint Interrupt</description>
29993                <bitRange>[7:7]</bitRange>
29994                <access>read-only</access>
29995              </field>
29996              <field>
29997                <name>EP1_INTR</name>
29998                <description>EP1 Interrupt</description>
29999                <bitRange>[8:8]</bitRange>
30000                <access>read-only</access>
30001              </field>
30002              <field>
30003                <name>EP2_INTR</name>
30004                <description>EP2 Interrupt</description>
30005                <bitRange>[9:9]</bitRange>
30006                <access>read-only</access>
30007              </field>
30008              <field>
30009                <name>EP3_INTR</name>
30010                <description>EP3 Interrupt</description>
30011                <bitRange>[10:10]</bitRange>
30012                <access>read-only</access>
30013              </field>
30014              <field>
30015                <name>EP4_INTR</name>
30016                <description>EP4 Interrupt</description>
30017                <bitRange>[11:11]</bitRange>
30018                <access>read-only</access>
30019              </field>
30020              <field>
30021                <name>EP5_INTR</name>
30022                <description>EP5 Interrupt</description>
30023                <bitRange>[12:12]</bitRange>
30024                <access>read-only</access>
30025              </field>
30026              <field>
30027                <name>EP6_INTR</name>
30028                <description>EP6 Interrupt</description>
30029                <bitRange>[13:13]</bitRange>
30030                <access>read-only</access>
30031              </field>
30032              <field>
30033                <name>EP7_INTR</name>
30034                <description>EP7 Interrupt</description>
30035                <bitRange>[14:14]</bitRange>
30036                <access>read-only</access>
30037              </field>
30038              <field>
30039                <name>EP8_INTR</name>
30040                <description>EP8 Interrupt</description>
30041                <bitRange>[15:15]</bitRange>
30042                <access>read-only</access>
30043              </field>
30044            </fields>
30045          </register>
30046          <register>
30047            <name>INTR_CAUSE_MED</name>
30048            <description>Medium priority interrupt Cause register</description>
30049            <addressOffset>0x38</addressOffset>
30050            <size>32</size>
30051            <access>read-only</access>
30052            <resetValue>0x0</resetValue>
30053            <resetMask>0xFF9F</resetMask>
30054            <fields>
30055              <field>
30056                <name>SOF_INTR</name>
30057                <description>USB SOF Interrupt</description>
30058                <bitRange>[0:0]</bitRange>
30059                <access>read-only</access>
30060              </field>
30061              <field>
30062                <name>BUS_RESET_INTR</name>
30063                <description>BUS RESET Interrupt</description>
30064                <bitRange>[1:1]</bitRange>
30065                <access>read-only</access>
30066              </field>
30067              <field>
30068                <name>EP0_INTR</name>
30069                <description>EP0 Interrupt</description>
30070                <bitRange>[2:2]</bitRange>
30071                <access>read-only</access>
30072              </field>
30073              <field>
30074                <name>LPM_INTR</name>
30075                <description>LPM Interrupt</description>
30076                <bitRange>[3:3]</bitRange>
30077                <access>read-only</access>
30078              </field>
30079              <field>
30080                <name>RESUME_INTR</name>
30081                <description>Resume Interrupt</description>
30082                <bitRange>[4:4]</bitRange>
30083                <access>read-only</access>
30084              </field>
30085              <field>
30086                <name>ARB_EP_INTR</name>
30087                <description>Arbiter Endpoint Interrupt</description>
30088                <bitRange>[7:7]</bitRange>
30089                <access>read-only</access>
30090              </field>
30091              <field>
30092                <name>EP1_INTR</name>
30093                <description>EP1 Interrupt</description>
30094                <bitRange>[8:8]</bitRange>
30095                <access>read-only</access>
30096              </field>
30097              <field>
30098                <name>EP2_INTR</name>
30099                <description>EP2 Interrupt</description>
30100                <bitRange>[9:9]</bitRange>
30101                <access>read-only</access>
30102              </field>
30103              <field>
30104                <name>EP3_INTR</name>
30105                <description>EP3 Interrupt</description>
30106                <bitRange>[10:10]</bitRange>
30107                <access>read-only</access>
30108              </field>
30109              <field>
30110                <name>EP4_INTR</name>
30111                <description>EP4 Interrupt</description>
30112                <bitRange>[11:11]</bitRange>
30113                <access>read-only</access>
30114              </field>
30115              <field>
30116                <name>EP5_INTR</name>
30117                <description>EP5 Interrupt</description>
30118                <bitRange>[12:12]</bitRange>
30119                <access>read-only</access>
30120              </field>
30121              <field>
30122                <name>EP6_INTR</name>
30123                <description>EP6 Interrupt</description>
30124                <bitRange>[13:13]</bitRange>
30125                <access>read-only</access>
30126              </field>
30127              <field>
30128                <name>EP7_INTR</name>
30129                <description>EP7 Interrupt</description>
30130                <bitRange>[14:14]</bitRange>
30131                <access>read-only</access>
30132              </field>
30133              <field>
30134                <name>EP8_INTR</name>
30135                <description>EP8 Interrupt</description>
30136                <bitRange>[15:15]</bitRange>
30137                <access>read-only</access>
30138              </field>
30139            </fields>
30140          </register>
30141          <register>
30142            <name>INTR_CAUSE_LO</name>
30143            <description>Low priority interrupt Cause register</description>
30144            <addressOffset>0x3C</addressOffset>
30145            <size>32</size>
30146            <access>read-only</access>
30147            <resetValue>0x0</resetValue>
30148            <resetMask>0xFF9F</resetMask>
30149            <fields>
30150              <field>
30151                <name>SOF_INTR</name>
30152                <description>USB SOF Interrupt</description>
30153                <bitRange>[0:0]</bitRange>
30154                <access>read-only</access>
30155              </field>
30156              <field>
30157                <name>BUS_RESET_INTR</name>
30158                <description>BUS RESET Interrupt</description>
30159                <bitRange>[1:1]</bitRange>
30160                <access>read-only</access>
30161              </field>
30162              <field>
30163                <name>EP0_INTR</name>
30164                <description>EP0 Interrupt</description>
30165                <bitRange>[2:2]</bitRange>
30166                <access>read-only</access>
30167              </field>
30168              <field>
30169                <name>LPM_INTR</name>
30170                <description>LPM Interrupt</description>
30171                <bitRange>[3:3]</bitRange>
30172                <access>read-only</access>
30173              </field>
30174              <field>
30175                <name>RESUME_INTR</name>
30176                <description>Resume Interrupt</description>
30177                <bitRange>[4:4]</bitRange>
30178                <access>read-only</access>
30179              </field>
30180              <field>
30181                <name>ARB_EP_INTR</name>
30182                <description>Arbiter Endpoint Interrupt</description>
30183                <bitRange>[7:7]</bitRange>
30184                <access>read-only</access>
30185              </field>
30186              <field>
30187                <name>EP1_INTR</name>
30188                <description>EP1 Interrupt</description>
30189                <bitRange>[8:8]</bitRange>
30190                <access>read-only</access>
30191              </field>
30192              <field>
30193                <name>EP2_INTR</name>
30194                <description>EP2 Interrupt</description>
30195                <bitRange>[9:9]</bitRange>
30196                <access>read-only</access>
30197              </field>
30198              <field>
30199                <name>EP3_INTR</name>
30200                <description>EP3 Interrupt</description>
30201                <bitRange>[10:10]</bitRange>
30202                <access>read-only</access>
30203              </field>
30204              <field>
30205                <name>EP4_INTR</name>
30206                <description>EP4 Interrupt</description>
30207                <bitRange>[11:11]</bitRange>
30208                <access>read-only</access>
30209              </field>
30210              <field>
30211                <name>EP5_INTR</name>
30212                <description>EP5 Interrupt</description>
30213                <bitRange>[12:12]</bitRange>
30214                <access>read-only</access>
30215              </field>
30216              <field>
30217                <name>EP6_INTR</name>
30218                <description>EP6 Interrupt</description>
30219                <bitRange>[13:13]</bitRange>
30220                <access>read-only</access>
30221              </field>
30222              <field>
30223                <name>EP7_INTR</name>
30224                <description>EP7 Interrupt</description>
30225                <bitRange>[14:14]</bitRange>
30226                <access>read-only</access>
30227              </field>
30228              <field>
30229                <name>EP8_INTR</name>
30230                <description>EP8 Interrupt</description>
30231                <bitRange>[15:15]</bitRange>
30232                <access>read-only</access>
30233              </field>
30234            </fields>
30235          </register>
30236          <register>
30237            <name>DFT_CTL</name>
30238            <description>DFT control</description>
30239            <addressOffset>0x70</addressOffset>
30240            <size>32</size>
30241            <access>read-write</access>
30242            <resetValue>0x0</resetValue>
30243            <resetMask>0x1F</resetMask>
30244            <fields>
30245              <field>
30246                <name>DDFT_OUT_SEL</name>
30247                <description>DDFT output select signal</description>
30248                <bitRange>[2:0]</bitRange>
30249                <access>read-write</access>
30250                <enumeratedValues>
30251                  <enumeratedValue>
30252                    <name>OFF</name>
30253                    <description>Nothing connected, output 0</description>
30254                    <value>0</value>
30255                  </enumeratedValue>
30256                  <enumeratedValue>
30257                    <name>DP_SE</name>
30258                    <description>Single Ended output of DP</description>
30259                    <value>1</value>
30260                  </enumeratedValue>
30261                  <enumeratedValue>
30262                    <name>DM_SE</name>
30263                    <description>Single Ended output of DM</description>
30264                    <value>2</value>
30265                  </enumeratedValue>
30266                  <enumeratedValue>
30267                    <name>TXOE</name>
30268                    <description>Output Enable</description>
30269                    <value>3</value>
30270                  </enumeratedValue>
30271                  <enumeratedValue>
30272                    <name>RCV_DF</name>
30273                    <description>Differential Receiver output</description>
30274                    <value>4</value>
30275                  </enumeratedValue>
30276                  <enumeratedValue>
30277                    <name>GPIO_DP_OUT</name>
30278                    <description>GPIO output of DP</description>
30279                    <value>5</value>
30280                  </enumeratedValue>
30281                  <enumeratedValue>
30282                    <name>GPIO_DM_OUT</name>
30283                    <description>GPIO output of DM</description>
30284                    <value>6</value>
30285                  </enumeratedValue>
30286                </enumeratedValues>
30287              </field>
30288              <field>
30289                <name>DDFT_IN_SEL</name>
30290                <description>DDFT input select signal</description>
30291                <bitRange>[4:3]</bitRange>
30292                <access>read-write</access>
30293                <enumeratedValues>
30294                  <enumeratedValue>
30295                    <name>OFF</name>
30296                    <description>Nothing connected, output 0</description>
30297                    <value>0</value>
30298                  </enumeratedValue>
30299                  <enumeratedValue>
30300                    <name>GPIO_DP_IN</name>
30301                    <description>GPIO input of DP</description>
30302                    <value>1</value>
30303                  </enumeratedValue>
30304                  <enumeratedValue>
30305                    <name>GPIO_DM_IN</name>
30306                    <description>GPIO input of DM</description>
30307                    <value>2</value>
30308                  </enumeratedValue>
30309                </enumeratedValues>
30310              </field>
30311            </fields>
30312          </register>
30313        </cluster>
30314        <cluster>
30315          <name>USBHOST</name>
30316          <description>USB Host Controller</description>
30317          <addressOffset>0x00004000</addressOffset>
30318          <register>
30319            <name>HOST_CTL0</name>
30320            <description>Host Control 0 Register.</description>
30321            <addressOffset>0x0</addressOffset>
30322            <size>32</size>
30323            <access>read-write</access>
30324            <resetValue>0x0</resetValue>
30325            <resetMask>0x80000001</resetMask>
30326            <fields>
30327              <field>
30328                <name>HOST</name>
30329                <description>This bit selects an operating mode of this IP.
30330'0' : USB Device
30331'1' : USB Host
30332Notes:
30333- The mode of operation mode does not transition immediately after setting this bit.  Read this bit to confirm that the operation mode has changed.
30334- This bit is reset to '0' if the ENABLE bit in this register changes from '1' to '0'.
30335- Before changing from the USB Host to the USB Device, check that the following conditions are satisfied and also set the RST bit of the Host Control 1 Register (HOST_CTL1). to '1'.
30336     * The SOFBUSY bit of the Host Status Register (HOST_STATUS) is set to '0'.
30337     * The TKNEN bits of the Host Token Endpoint Register (HOST_TOKEN) is set to '000'.
30338     * The SUSP bit of the Host Status Register (HOST_STATUS) is set to '0'.</description>
30339                <bitRange>[0:0]</bitRange>
30340                <access>read-write</access>
30341              </field>
30342              <field>
30343                <name>ENABLE</name>
30344                <description>This bit enables the operation of this IP.
30345'0' : Disable USB Host
30346'1' : Enable USB Host
30347Note:
30348- This bit doesn't affect the USB Device.</description>
30349                <bitRange>[31:31]</bitRange>
30350                <access>read-write</access>
30351              </field>
30352            </fields>
30353          </register>
30354          <register>
30355            <name>HOST_CTL1</name>
30356            <description>Host Control 1 Register.</description>
30357            <addressOffset>0x10</addressOffset>
30358            <size>32</size>
30359            <access>read-write</access>
30360            <resetValue>0x83</resetValue>
30361            <resetMask>0x83</resetMask>
30362            <fields>
30363              <field>
30364                <name>CLKSEL</name>
30365                <description>This bit selects the operating clock of USB Host.
30366'0' : Low-speed clock
30367'1' : Full-speed clock
30368Notes:
30369- This bit is set to it's default vaulue '1' if the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'.
30370- This bit must always be set to '1' in the USB Device mode.</description>
30371                <bitRange>[0:0]</bitRange>
30372                <access>read-write</access>
30373              </field>
30374              <field>
30375                <name>USTP</name>
30376                <description>This bit stops the clock for the USB Host operating unit. When this bit is '1', power consumption can be reduced by configuring this bit.
30377'0' : Normal operating mode.
30378'1' : Stops the clock for the USB Host operating unit.
30379Notes:
30380- If this bit is set to '1', the function of USB Host can't be used because internal clock is stopped.
30381- This bit is initialized if ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'.</description>
30382                <bitRange>[1:1]</bitRange>
30383                <access>read-write</access>
30384              </field>
30385              <field>
30386                <name>RST</name>
30387                <description>This bit resets the USB Host.
30388'0' : Normal operating mode.
30389'1' : USB Host is reset.
30390Notes:
30391- This bit is to it's default value '1' if  the ENABLE bit of the Host Control 0 Register (HOST_CTL0) changes from '1' to '0'.
30392- If this bit is set to '1', both the BFINI bits of the Host Endpoint 1 Control Register (HOST_EP1_CTL) and Host Endpoint 2 Control Register (HOST_EP2_CTL) are set to '1'.</description>
30393                <bitRange>[7:7]</bitRange>
30394                <access>read-write</access>
30395              </field>
30396            </fields>
30397          </register>
30398          <register>
30399            <name>HOST_CTL2</name>
30400            <description>Host Control 2 Register.</description>
30401            <addressOffset>0x100</addressOffset>
30402            <size>32</size>
30403            <access>read-write</access>
30404            <resetValue>0x1</resetValue>
30405            <resetMask>0xFF</resetMask>
30406            <fields>
30407              <field>
30408                <name>RETRY</name>
30409                <description>If this bit is set to '1', the target token is retried if a NAK or error* occurs. Retry processing is performed after the time that is specified in the Host Retry Timer Setup Register (HOST_RTIMER).
30410* : HOST_ERR.RERR='1', HOST_ERR.TOUT='1', HOST_ERR.CRC='1', HOST_ERR.TGERR='1', HOST_ERR.STUFF='1'
30411'0' : Doesn't retry token sending.
30412'1' : Retries token sending
30413Note:
30414- This bit isn't initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
30415                <bitRange>[0:0]</bitRange>
30416                <access>read-write</access>
30417              </field>
30418              <field>
30419                <name>CANCEL</name>
30420                <description>When this bit is set to '1', if the target token is written to the Host Token Endpoint Register (HOST_TOKEN) in the EOF area (specified in the Host EOF Setup Register), its sending is canceled. When this bit is set to '0', token sending is not canceled even if the target token is written to the register. The cancellation of token sending is detected by reading the TCAN bit of the Interrupt USB Host Register (INTR_USBHOST).
30421'0' : Continues a token.
30422'1' : Cancels a token.</description>
30423                <bitRange>[1:1]</bitRange>
30424                <access>read-write</access>
30425              </field>
30426              <field>
30427                <name>SOFSTEP</name>
30428                <description>If this bit is set to '1', the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1' each time SOF is sent.
30429If this bit is set to '0', the set value of the Host SOF Interrupt Frame Compare Register (HOST_FCOMP) is compared with the low-order eight bits of the SOF frame number. If they match, the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is set to '1'.
30430'0' : An interrupt occurred due to the HOST_HFCOMP setting.
30431'1' : An interrupt occurred.
30432Notes:
30433- If a SOF token (TKNEN='001') is sent by the setting of the Host Token Endpoint Register (HOST_TOKEN), the SOF interrupt flag (INTR_USBHOST.SOFIRQ) is not set to '1' regardless of the setting of this bit.</description>
30434                <bitRange>[2:2]</bitRange>
30435                <access>read-write</access>
30436              </field>
30437              <field>
30438                <name>ALIVE</name>
30439                <description>This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to '1' while the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is '0', SE0 is output instead of SOF. This bit is only effective when the CLKSEL bit is '0'. If the CLKSEL bit is '1' (Full-Speed mode), SOF is output regardless of the setting of the ALIVE bit.
30440'0' : SOF output.
30441'1' : SE0 output (Keep alive)</description>
30442                <bitRange>[3:3]</bitRange>
30443                <access>read-write</access>
30444              </field>
30445              <field>
30446                <name>RSVD_4</name>
30447                <description>N/A</description>
30448                <bitRange>[4:4]</bitRange>
30449                <access>read-write</access>
30450              </field>
30451              <field>
30452                <name>RSVD_5</name>
30453                <description>N/A</description>
30454                <bitRange>[5:5]</bitRange>
30455                <access>read-write</access>
30456              </field>
30457              <field>
30458                <name>TTEST</name>
30459                <description>N/A</description>
30460                <bitRange>[7:6]</bitRange>
30461                <access>read-write</access>
30462              </field>
30463            </fields>
30464          </register>
30465          <register>
30466            <name>HOST_ERR</name>
30467            <description>Host Error Status Register.</description>
30468            <addressOffset>0x104</addressOffset>
30469            <size>32</size>
30470            <access>read-write</access>
30471            <resetValue>0x3</resetValue>
30472            <resetMask>0xFF</resetMask>
30473            <fields>
30474              <field>
30475                <name>HS</name>
30476                <description>These flags indicate the status of a handshake packet to be sent or received.
30477These flags are set to 'NULL' when no handshake occurs due to an error or when a SOF token has been ended with the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN).
30478These bits are updated when sending or receiving has been ended.
30479Write '11' to set the status back to 'NULL', all other write values are ignored.
30480Note:
30481This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
30482                <bitRange>[1:0]</bitRange>
30483                <access>read-write</access>
30484                <enumeratedValues>
30485                  <enumeratedValue>
30486                    <name>ACK</name>
30487                    <description>Acknowledge Packet</description>
30488                    <value>0</value>
30489                  </enumeratedValue>
30490                  <enumeratedValue>
30491                    <name>NAK</name>
30492                    <description>Non-Acknowledge Packet</description>
30493                    <value>1</value>
30494                  </enumeratedValue>
30495                  <enumeratedValue>
30496                    <name>STALL</name>
30497                    <description>Stall Packet</description>
30498                    <value>2</value>
30499                  </enumeratedValue>
30500                  <enumeratedValue>
30501                    <name>NULL</name>
30502                    <description>Null Packet</description>
30503                    <value>3</value>
30504                  </enumeratedValue>
30505                </enumeratedValues>
30506              </field>
30507              <field>
30508                <name>STUFF</name>
30509                <description>If this bit is set to '1', it means that a bit stuffing error has been detected. When this bit is '0', it means that no error is detected. If a stuffing error is detected, bit5 (TOUT) of this register is also set to '1'.  Write '1' to clear, a write of '0' is ignored.
30510'0' : No stuffing error.
30511'1' : Stuffing error detected.
30512Note:
30513- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
30514                <bitRange>[2:2]</bitRange>
30515                <access>read-write</access>
30516              </field>
30517              <field>
30518                <name>TGERR</name>
30519                <description>If this bit is set to '1', it means that the data does not match the TGGL data. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored.
30520'0' : No toggle error.
30521'1' : Toggle error detected.
30522Note:
30523- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
30524                <bitRange>[3:3]</bitRange>
30525                <access>read-write</access>
30526              </field>
30527              <field>
30528                <name>CRC</name>
30529                <description>If this bit is set to '1', it means that a CRC error is detected in the USB Host. When this bit is '0', it means that no error is detected. If a CRC error is detected, bit5 (TOUT) of this register is also set to '1'.  Write '1' to clear, a write of '0' is ignored.
30530'0' : No CRC error.
30531'1' : CRC error detected.
30532Note:
30533- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
30534                <bitRange>[4:4]</bitRange>
30535                <access>read-write</access>
30536              </field>
30537              <field>
30538                <name>TOUT</name>
30539                <description>If this bit is set to '1', it means that no response is returned from the device within the specified time after a token has been sent in the USB Host. When this bit is '0', it means that no timeout is detected.  Write '1' to clear, a write of '0' is ignored.
30540'0' : No timeout.
30541'1' : Timeout has detected.
30542Note:
30543- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
30544                <bitRange>[5:5]</bitRange>
30545                <access>read-write</access>
30546              </field>
30547              <field>
30548                <name>RERR</name>
30549                <description>When this bit is set to '1', it means that the received data exceeds the specified maximum number of packets in the USB Host. If a receive error is detected, bit5 (TOUT) of this register is also set to '1'. When this bit is '0', it means that no error is detected. Write '1' to clear, a write of '0' is ignored.
30550'0' : No receive error.
30551'1' : Maximum packet receive error detected.
30552- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
30553                <bitRange>[6:6]</bitRange>
30554                <access>read-write</access>
30555              </field>
30556              <field>
30557                <name>LSTSOF</name>
30558                <description>If this bit is set to '1', it means that the SOF token can't be sent in the USB Host because other token is in process. When this bit is '0', it means that SOF token was sent with no error. Write '1' to clear, a write of '0' is ignored.
30559'0' : SOF sent without error.
30560'1' : SOF error detected.
30561Note:
30562- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
30563                <bitRange>[7:7]</bitRange>
30564                <access>read-write</access>
30565              </field>
30566            </fields>
30567          </register>
30568          <register>
30569            <name>HOST_STATUS</name>
30570            <description>Host Status Register.</description>
30571            <addressOffset>0x108</addressOffset>
30572            <size>32</size>
30573            <access>read-write</access>
30574            <resetValue>0xC2</resetValue>
30575            <resetMask>0x1FF</resetMask>
30576            <fields>
30577              <field>
30578                <name>CSTAT</name>
30579                <description>When this bit is '1', it means that the device is connected. When this bit is '0', it means that the device is disconnected.
30580'0' : Device is disconnected.
30581'1' : Device is connected.
30582Notes:
30583- This bit is set to the default value if the RST bit of the Host Control 1 Register (Host_CTL1) is set to '1'.
30584- The transition to disconnected on RST isn't immediate.  Read this bit to confirm the transition is complete.</description>
30585                <bitRange>[0:0]</bitRange>
30586                <access>read-only</access>
30587              </field>
30588              <field>
30589                <name>TMODE</name>
30590                <description>If this bit is '1', it means that the device is connected in the full-speed mode. When this bit is '0', it means that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status Register (HOST_STATUS) is '1'.
30591'0' : Low-speed.
30592'1' : Full-speed.
30593Notes:
30594- This bit is set to the default value if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
30595- The transition to disconnected on RST isn't immediate.  Read this bit to confirm the transition is complete.</description>
30596                <bitRange>[1:1]</bitRange>
30597                <access>read-only</access>
30598              </field>
30599              <field>
30600                <name>SUSP</name>
30601                <description>If this bit is set to '1', the USB Host is placed into the suspend state. If this bit is set to '0' while it is '1' or the USB bus is placed into the k-state mode, then suspend state is released, and the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'.
30602Set to '1' : Suspend.
30603Set '0' when this bit is '1' : Resume.
30604Other conditions : Holds the status.
30605Notes:
30606- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
30607- The transition to disconnected on RST isn't immediate.  Read this bit to confirm the transition is complete.
30608- If this bit is set to '1', this bit must not be set to '1' until the RWIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'.
30609- Do not set this bit to '1' while the USB is active (during USB bus resetting, data transfer, or SOF timer running).
30610- If the value of this bit is changed, it is not immediately reflected on the state of the USB bus. To check whether or not the state is updated, read this bit.</description>
30611                <bitRange>[2:2]</bitRange>
30612                <access>read-write</access>
30613              </field>
30614              <field>
30615                <name>SOFBUSY</name>
30616                <description>When a SOF token is sent using the Host Token Endpoint Register (HOST_TOKEN), this bit is set to '1', which means that the SOF timer is active. When this bit is '0', it means that the SOF timer is under suspension. To stop the active SOF timer, write '0' to this bit. However, if this bit is written with '1', its value is ignored.
30617'0' : The SOF timer is stopped.
30618'1' : The SOF timer is active.
30619Notes:
30620- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
30621- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1).
30622- The SOF timer does not stop immediately after this bit has been set to '0' to stop the SOF timer. To check whether or not the SOF timer is stopped, read this bit.</description>
30623                <bitRange>[3:3]</bitRange>
30624                <access>read-write</access>
30625              </field>
30626              <field>
30627                <name>URST</name>
30628                <description>When this bit is set to '1', the USB bus is reset. This bit remains a '1' during USB bus resetting, and changes to '0' when USB bus resetting is ended. If this bit is set to '0', the USB bus reset is complete</description>
30629                <bitRange>[4:4]</bitRange>
30630                <access>read-write</access>
30631              </field>
30632              <field>
30633                <name>RSVD_5</name>
30634                <description>N/A</description>
30635                <bitRange>[5:5]</bitRange>
30636                <access>read-only</access>
30637              </field>
30638              <field>
30639                <name>RSTBUSY</name>
30640                <description>This bit shows that USB Host is being reset internally. If the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'.
30641If the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0', this bit is set to '0'.
30642'0' : USB Host isn't being reset.
30643'1' : USB Host is being reset.
30644Notes:
30645- If this bit is '1', the a token must not be executed.
30646- This bit isn't set to '0' or '1' immediately even if the RST bit of Host Control 1 Register (HOST_CTL1) is set to '0' or '1'. Read this bit to confirm the operation is complete.</description>
30647                <bitRange>[6:6]</bitRange>
30648                <access>read-only</access>
30649              </field>
30650              <field>
30651                <name>CLKSEL_ST</name>
30652                <description>This bit shows whether it is full-speed or not. If the CLKSEL bit of the Host Control 1 Register (HOST_CTL1) is set to '1', this bit is set to '1'.
30653'0' : Low speed
30654'1' : Full speed
30655Note:
30656- If this bit is different from the CLKSEL bit, The execution of the token and bus reset must wait these bits match.
30657- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete.</description>
30658                <bitRange>[7:7]</bitRange>
30659                <access>read-only</access>
30660              </field>
30661              <field>
30662                <name>HOST_ST</name>
30663                <description>This bit shows whether the device is in USB Host mode. If the HOST bit of the Host Control Register (HOST_CTL0) is set to '1', this bit is set to '1'.
30664'0' : USB Device
30665'1' : USB Host
30666Notes:
30667- If this bit is different from the HOST bit, The execution of a token must wait these bits match.
30668- This bit takes time to be initialized by the RST bit of the Host Control 1 Resgiter (HOST_CTL1). Read this bit to confirm the operation is complete.</description>
30669                <bitRange>[8:8]</bitRange>
30670                <access>read-only</access>
30671              </field>
30672            </fields>
30673          </register>
30674          <register>
30675            <name>HOST_FCOMP</name>
30676            <description>Host SOF Interrupt Frame Compare Register</description>
30677            <addressOffset>0x10C</addressOffset>
30678            <size>32</size>
30679            <access>read-write</access>
30680            <resetValue>0x0</resetValue>
30681            <resetMask>0xFF</resetMask>
30682            <fields>
30683              <field>
30684                <name>FRAMECOMP</name>
30685                <description>These bits are used to specify the data to be compared with the low-order eight bits of a frame number when sending a SOF token.
30686If the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '0', the frame number of SOF is compared with the value of this register when sending a SOF token. If they match, the SOFIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'.
30687The setting of this register is invalid when the SOFSTEP bit of Host Control 2 Register (HOST_CTL2) is '1'.
30688Note:
30689- This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
30690                <bitRange>[7:0]</bitRange>
30691                <access>read-write</access>
30692              </field>
30693            </fields>
30694          </register>
30695          <register>
30696            <name>HOST_RTIMER</name>
30697            <description>Host Retry Timer Setup Register</description>
30698            <addressOffset>0x110</addressOffset>
30699            <size>32</size>
30700            <access>read-write</access>
30701            <resetValue>0x0</resetValue>
30702            <resetMask>0x3FFFF</resetMask>
30703            <fields>
30704              <field>
30705                <name>RTIMER</name>
30706                <description>These bits are used to specify the retry time in this register. The retry timer is activated when token sending starts while the RETRY bit of Host Control 2 Register (HOST_CTL2) is '1'. The retry time is then decremented by one when a 1-bit transfer clock (12 MHz in the full-speed mode) is output. When the retry timer reaches 0, the target token is sent, and processing ends.
30707If a token retry occurs in the EOF area, the retry timer is stopped until SOF sending is ended. After SOF sending has been completed, the retry timer restarts with the value that is set when the timer stopped.</description>
30708                <bitRange>[17:0]</bitRange>
30709                <access>read-write</access>
30710              </field>
30711            </fields>
30712          </register>
30713          <register>
30714            <name>HOST_ADDR</name>
30715            <description>Host Address Register</description>
30716            <addressOffset>0x114</addressOffset>
30717            <size>32</size>
30718            <access>read-write</access>
30719            <resetValue>0x0</resetValue>
30720            <resetMask>0x7F</resetMask>
30721            <fields>
30722              <field>
30723                <name>ADDRESS</name>
30724                <description>These bits are used to specify a token address.
30725Note:
30726- This bit is reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
30727                <bitRange>[6:0]</bitRange>
30728                <access>read-write</access>
30729              </field>
30730            </fields>
30731          </register>
30732          <register>
30733            <name>HOST_EOF</name>
30734            <description>Host EOF Setup Register</description>
30735            <addressOffset>0x118</addressOffset>
30736            <size>32</size>
30737            <access>read-write</access>
30738            <resetValue>0x0</resetValue>
30739            <resetMask>0x3FFF</resetMask>
30740            <fields>
30741              <field>
30742                <name>EOF</name>
30743                <description>These bits are used to specify the time to disable token sending before transferring SOF. Specify the time with a margin, which is longer than the one-packet length. The time unit is the 1-bit transfer time.
30744Setting example: MAXPKT = 64 bytes, full-speed mode
30745 (Token_length + packet_length + header + CRC)*7/6 + Turn_around_time
30746  =(34 bit + 546 bit)*7/6 + 36 bit = 712.7 bit
30747 Therefore, set 0x2C9.
30748Note:
30749- This bit is not reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
30750                <bitRange>[13:0]</bitRange>
30751                <access>read-write</access>
30752              </field>
30753            </fields>
30754          </register>
30755          <register>
30756            <name>HOST_FRAME</name>
30757            <description>Host Frame Setup Register</description>
30758            <addressOffset>0x11C</addressOffset>
30759            <size>32</size>
30760            <access>read-write</access>
30761            <resetValue>0x0</resetValue>
30762            <resetMask>0x7FF</resetMask>
30763            <fields>
30764              <field>
30765                <name>FRAME</name>
30766                <description>These bits are used to specify a frame number of SOF.
30767Notes:
30768- This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
30769- Specify a frame number in this register before setting SOF in the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN).
30770- This register cannot be written while the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1' and a SOF token is in process.</description>
30771                <bitRange>[10:0]</bitRange>
30772                <access>read-write</access>
30773              </field>
30774            </fields>
30775          </register>
30776          <register>
30777            <name>HOST_TOKEN</name>
30778            <description>Host Token Endpoint Register</description>
30779            <addressOffset>0x120</addressOffset>
30780            <size>32</size>
30781            <access>read-write</access>
30782            <resetValue>0x0</resetValue>
30783            <resetMask>0x17F</resetMask>
30784            <fields>
30785              <field>
30786                <name>ENDPT</name>
30787                <description>These bits are used to specify an endpoint to send or receive data to or from the device.
30788Note:
30789- This bit isn't reset to default even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
30790                <bitRange>[3:0]</bitRange>
30791                <access>read-write</access>
30792              </field>
30793              <field>
30794                <name>TKNEN</name>
30795                <description>These bits send a token according to the current settings. After operation is complete, the TKNEN bit is set to '000', and the CMPIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to '1'.
30796The settings of the TGGL and ENDPT bits are ignored when sending a SOF token.
30797Notes:
30798- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
30799- The PRE packet isn't supported.
30800- Do not set '100' to the TKNEN bit when the SOFBUSY bit of the Host Status Register (HOST_STATUS) is '1'
30801- Mode should be USB Host before writing data to this bit.
30802- When issuing a token again after the token interrupt flag (CMPIRQ) has been set to '1', wait for 3 cycles or more after a USB transfer clock (12 MHz in the full-speed mode, 1.5 MHz in the low-speed mode) was output, then write data to this bit.
30803- Read the value of TKNEN bit if a new value is written in it .Continue writing in this bit until a retrieved value equals a new value written in. During this checking process, it is needed to prevent any interrupt.
30804- Take the following steps when CMPIRQ bit of Interrupt USB Host Register (INTR_USBHOST) is set to '1' by finishing IN token or Isochronous IN token.
308051. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'.
308062. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'.
308073. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'.</description>
30808                <bitRange>[6:4]</bitRange>
30809                <access>read-write</access>
30810                <enumeratedValues>
30811                  <enumeratedValue>
30812                    <name>NONE</name>
30813                    <description>Sends no data.</description>
30814                    <value>0</value>
30815                  </enumeratedValue>
30816                  <enumeratedValue>
30817                    <name>SETUP</name>
30818                    <description>Sends SETUP token.</description>
30819                    <value>1</value>
30820                  </enumeratedValue>
30821                  <enumeratedValue>
30822                    <name>IN</name>
30823                    <description>Sends IN token.</description>
30824                    <value>2</value>
30825                  </enumeratedValue>
30826                  <enumeratedValue>
30827                    <name>OUT</name>
30828                    <description>Sends OUT token.</description>
30829                    <value>3</value>
30830                  </enumeratedValue>
30831                  <enumeratedValue>
30832                    <name>SOF</name>
30833                    <description>Sends SOF token.</description>
30834                    <value>4</value>
30835                  </enumeratedValue>
30836                  <enumeratedValue>
30837                    <name>ISO_IN</name>
30838                    <description>Sends Isochronous IN.</description>
30839                    <value>5</value>
30840                  </enumeratedValue>
30841                  <enumeratedValue>
30842                    <name>ISO_OUT</name>
30843                    <description>Sends Isochronous OUT.</description>
30844                    <value>6</value>
30845                  </enumeratedValue>
30846                  <enumeratedValue>
30847                    <name>RSV</name>
30848                    <description>N/A</description>
30849                    <value>7</value>
30850                  </enumeratedValue>
30851                </enumeratedValues>
30852              </field>
30853              <field>
30854                <name>TGGL</name>
30855                <description>This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving toggle data, received toggle data is compared with the toggle data of this bit to verify whether or not an error occurs.
30856'0' : DATA0
30857'1' : DATA1
30858Notes:
30859- This bit isn't reset to the default value even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
30860- Set this bit when the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN) is '000'.</description>
30861                <bitRange>[8:8]</bitRange>
30862                <access>read-write</access>
30863              </field>
30864            </fields>
30865          </register>
30866          <register>
30867            <name>HOST_EP1_CTL</name>
30868            <description>Host Endpoint 1 Control Register</description>
30869            <addressOffset>0x400</addressOffset>
30870            <size>32</size>
30871            <access>read-write</access>
30872            <resetValue>0x8100</resetValue>
30873            <resetMask>0x9DFF</resetMask>
30874            <fields>
30875              <field>
30876                <name>PKS1</name>
30877                <description>This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x100.
30878- If automatic buffer transfer mode (DMAE='1') is used, Endpoint 0,1, or 2 cannot be used,</description>
30879                <bitRange>[8:0]</bitRange>
30880                <access>read-write</access>
30881              </field>
30882              <field>
30883                <name>NULLE</name>
30884                <description>When a data transfer request in OUT the direction is transmitted while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer.
30885'0' : Releases the NULL automatic transfer mode.
30886'1' : Sets the NULL automatic transfer mode.
30887Note :
30888- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication.</description>
30889                <bitRange>[10:10]</bitRange>
30890                <access>read-write</access>
30891              </field>
30892              <field>
30893                <name>DMAE</name>
30894                <description>This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred.
30895'0' : Releases the packet transfer mode.
30896'1' : Sets the packet transfer mode.
30897Note :
30898- The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS1 bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR).</description>
30899                <bitRange>[11:11]</bitRange>
30900                <access>read-write</access>
30901              </field>
30902              <field>
30903                <name>DIR</name>
30904                <description>This bit specifies the transfer direction the Endpoint support.
30905'0' : IN Endpoint.
30906'1' : OUT Endpoint
30907Note:
30908- This bit must be changed when INI_ST bit of the Host Endpoint 1 Status Register (HOST_EP1_STATUS) is '1'.</description>
30909                <bitRange>[12:12]</bitRange>
30910                <access>read-write</access>
30911              </field>
30912              <field>
30913                <name>BFINI</name>
30914                <description>This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit.
30915'0' : Clears the initialization.
30916'1' : Initializes the send/receive buffer
30917Note :
30918- The EP1 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP1DRQ and EP1SPK bits.</description>
30919                <bitRange>[15:15]</bitRange>
30920                <access>read-write</access>
30921              </field>
30922            </fields>
30923          </register>
30924          <register>
30925            <name>HOST_EP1_STATUS</name>
30926            <description>Host Endpoint 1 Status Register</description>
30927            <addressOffset>0x404</addressOffset>
30928            <size>32</size>
30929            <access>read-only</access>
30930            <resetValue>0x60000</resetValue>
30931            <resetMask>0x70000</resetMask>
30932            <fields>
30933              <field>
30934                <name>SIZE1</name>
30935                <description>These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP1 has finished.
30936The indication range is from 0x000 to 0x100.
30937Note :
30938- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect.</description>
30939                <bitRange>[8:0]</bitRange>
30940                <access>read-only</access>
30941              </field>
30942              <field>
30943                <name>VAL_DATA</name>
30944                <description>This bit shows that there is valid data in the EP1 buffer.
30945'0' : Invalid data in the buffer
30946'1' : Valid data in the buffer</description>
30947                <bitRange>[16:16]</bitRange>
30948                <access>read-only</access>
30949              </field>
30950              <field>
30951                <name>INI_ST</name>
30952                <description>This bit shows that EP1 is initialized. If the init bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '1' and EP1 is initialized, this bit is to '1'.
30953'0' : Not initiatialized
30954'1' : Initialized
30955Note:
30956- This bit isn't set to '0' or '1' immediately even if BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is set to '0' or '1'.  Read this bit to confirm the transition.</description>
30957                <bitRange>[17:17]</bitRange>
30958                <access>read-only</access>
30959              </field>
30960              <field>
30961                <name>RSVD_18</name>
30962                <description>N/A</description>
30963                <bitRange>[18:18]</bitRange>
30964                <access>read-only</access>
30965              </field>
30966            </fields>
30967          </register>
30968          <register>
30969            <name>HOST_EP1_RW1_DR</name>
30970            <description>Host Endpoint 1 Data 1-Byte Register</description>
30971            <addressOffset>0x408</addressOffset>
30972            <size>32</size>
30973            <access>read-write</access>
30974            <resetValue>0x0</resetValue>
30975            <resetMask>0xFF</resetMask>
30976            <fields>
30977              <field>
30978                <name>BFDT8</name>
30979                <description>Data Register for EP1 for 1-byte data</description>
30980                <bitRange>[7:0]</bitRange>
30981                <access>read-write</access>
30982              </field>
30983            </fields>
30984          </register>
30985          <register>
30986            <name>HOST_EP1_RW2_DR</name>
30987            <description>Host Endpoint 1 Data 2-Byte Register</description>
30988            <addressOffset>0x40C</addressOffset>
30989            <size>32</size>
30990            <access>read-write</access>
30991            <resetValue>0x0</resetValue>
30992            <resetMask>0xFFFF</resetMask>
30993            <fields>
30994              <field>
30995                <name>BFDT16</name>
30996                <description>Data Register for EP1 for 2-byte data</description>
30997                <bitRange>[15:0]</bitRange>
30998                <access>read-write</access>
30999              </field>
31000            </fields>
31001          </register>
31002          <register>
31003            <name>HOST_EP2_CTL</name>
31004            <description>Host Endpoint 2 Control Register</description>
31005            <addressOffset>0x500</addressOffset>
31006            <size>32</size>
31007            <access>read-write</access>
31008            <resetValue>0x8040</resetValue>
31009            <resetMask>0x9C7F</resetMask>
31010            <fields>
31011              <field>
31012                <name>PKS2</name>
31013                <description>This bit specifies the maximum size transferred by one packet. The configurable range is from 0x001 to 0x40.
31014- If automatic buffer transfer mode (DMAE='1') is used, this Endpoint must not set from 0 to 2.</description>
31015                <bitRange>[6:0]</bitRange>
31016                <access>read-write</access>
31017              </field>
31018              <field>
31019                <name>NULLE</name>
31020                <description>When a data transfer request in the OUT direction transmitted while packet transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer.
31021'0' : Releases the NULL automatic transfer mode.
31022'1' : Sets the NULL automatic transfer mode.
31023Note :
31024- For data transfer in the IN direction or when automatic buffer transfer mode is not set, the NULL bit configuration does not affect communication.</description>
31025                <bitRange>[10:10]</bitRange>
31026                <access>read-write</access>
31027              </field>
31028              <field>
31029                <name>DMAE</name>
31030                <description>This bit sets a mode that uses DMA for writing or reading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction. Until the data size set in the DMA is reached, the data is transferred.
31031'0' : Releases the automatic buffer transfer mode.
31032'1' : Sets the automatic buffer transfer mode.
31033Note :
31034- The CPU must not access the send/receive buffer while the DMAE bit is set to '1'. For data transfer in the IN direction, set the DMA transfer size to the multiples of that set in PKS bits of the Host EP1 Control Register (HOST_EP1_CTL) and Host EP2 Control Register (HOST_EP2_CTR).</description>
31035                <bitRange>[11:11]</bitRange>
31036                <access>read-write</access>
31037              </field>
31038              <field>
31039                <name>DIR</name>
31040                <description>This bit specifies the transfer direction the Endpoint support.
31041'0' : IN Endpoint.
31042'1' : OUT Endpoint
31043Note:
31044- This bit must be changed when INI_ST bit of the Host Endpoint 2 Status Register (HOST_EP2_STATUS) is '1'.</description>
31045                <bitRange>[12:12]</bitRange>
31046                <access>read-write</access>
31047              </field>
31048              <field>
31049                <name>BFINI</name>
31050                <description>This bit initializes the send/receive buffer of transfer data. The BFINI bit is also automatically set by setting the RST bit of the HOST Control 1 Register (HOST_CTL1). If the RST bit was used for resetting, therefore, set the RST bit to '0' before clearing the BFINI bit.
31051'0' : Clears the initialization.
31052'1' : Initializes the send/receive buffer
31053Note :
31054- The EP2 buffer has a double-buffer configuration. The BFINI bit initialization initializes the double buffers concurrently and also initializes the EP2DRQ and EP2SPK bits.</description>
31055                <bitRange>[15:15]</bitRange>
31056                <access>read-write</access>
31057              </field>
31058            </fields>
31059          </register>
31060          <register>
31061            <name>HOST_EP2_STATUS</name>
31062            <description>Host Endpoint 2 Status Register</description>
31063            <addressOffset>0x504</addressOffset>
31064            <size>32</size>
31065            <access>read-only</access>
31066            <resetValue>0x60000</resetValue>
31067            <resetMask>0x70000</resetMask>
31068            <fields>
31069              <field>
31070                <name>SIZE2</name>
31071                <description>These bits indicate the number of data bytes written to the receive buffer when IN packet transfer of EP2 has finished.
31072The indication range is from 0x000 to 0x40.
31073Note :
31074- These bits are set to the data size transferred in the IN direction and written to the buffer. Therefore, a value read during transfer in the OUT direction has no effect.</description>
31075                <bitRange>[6:0]</bitRange>
31076                <access>read-only</access>
31077              </field>
31078              <field>
31079                <name>VAL_DATA</name>
31080                <description>This bit shows that there is valid data in the EP2 buffer.
31081'0' : Invalid data in the buffer
31082'1' : Valid data in the buffer</description>
31083                <bitRange>[16:16]</bitRange>
31084                <access>read-only</access>
31085              </field>
31086              <field>
31087                <name>INI_ST</name>
31088                <description>This bit shows that EP2 is initialized. If the BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '1' and EP2 is initialized, this bit is to '1'.
31089'0' : Not Initialized
31090'1' : Initialized
31091Note:
31092- This bit isn't set to '0' or '1' immediately evne if BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is set to '0' or '1'.</description>
31093                <bitRange>[17:17]</bitRange>
31094                <access>read-only</access>
31095              </field>
31096              <field>
31097                <name>RSVD_18</name>
31098                <description>N/A</description>
31099                <bitRange>[18:18]</bitRange>
31100                <access>read-only</access>
31101              </field>
31102            </fields>
31103          </register>
31104          <register>
31105            <name>HOST_EP2_RW1_DR</name>
31106            <description>Host Endpoint 2 Data 1-Byte Register</description>
31107            <addressOffset>0x508</addressOffset>
31108            <size>32</size>
31109            <access>read-write</access>
31110            <resetValue>0x0</resetValue>
31111            <resetMask>0xFF</resetMask>
31112            <fields>
31113              <field>
31114                <name>BFDT8</name>
31115                <description>Data Register for EP2 for 1-byte data.</description>
31116                <bitRange>[7:0]</bitRange>
31117                <access>read-write</access>
31118              </field>
31119            </fields>
31120          </register>
31121          <register>
31122            <name>HOST_EP2_RW2_DR</name>
31123            <description>Host Endpoint 2 Data 2-Byte Register</description>
31124            <addressOffset>0x50C</addressOffset>
31125            <size>32</size>
31126            <access>read-write</access>
31127            <resetValue>0x0</resetValue>
31128            <resetMask>0xFFFF</resetMask>
31129            <fields>
31130              <field>
31131                <name>BFDT16</name>
31132                <description>Data Register for EP2 for 2 byte data.</description>
31133                <bitRange>[15:0]</bitRange>
31134                <access>read-write</access>
31135              </field>
31136            </fields>
31137          </register>
31138          <register>
31139            <name>HOST_LVL1_SEL</name>
31140            <description>Host Interrupt Level 1 Selection Register</description>
31141            <addressOffset>0x800</addressOffset>
31142            <size>32</size>
31143            <access>read-write</access>
31144            <resetValue>0x0</resetValue>
31145            <resetMask>0xFFFF</resetMask>
31146            <fields>
31147              <field>
31148                <name>SOFIRQ_SEL</name>
31149                <description>These bits assign SOFIRQ interrupt flag to selected interrupt signals.</description>
31150                <bitRange>[1:0]</bitRange>
31151                <access>read-write</access>
31152                <enumeratedValues>
31153                  <enumeratedValue>
31154                    <name>HI</name>
31155                    <description>High priority interrupt</description>
31156                    <value>0</value>
31157                  </enumeratedValue>
31158                  <enumeratedValue>
31159                    <name>MED</name>
31160                    <description>Medium priority interrupt</description>
31161                    <value>1</value>
31162                  </enumeratedValue>
31163                  <enumeratedValue>
31164                    <name>LO</name>
31165                    <description>Low priority interrupt</description>
31166                    <value>2</value>
31167                  </enumeratedValue>
31168                  <enumeratedValue>
31169                    <name>RSVD</name>
31170                    <description>N/A</description>
31171                    <value>3</value>
31172                  </enumeratedValue>
31173                </enumeratedValues>
31174              </field>
31175              <field>
31176                <name>DIRQ_SEL</name>
31177                <description>These bits assign DIRQ interrupt flag to selected interrupt signals.</description>
31178                <bitRange>[3:2]</bitRange>
31179                <access>read-write</access>
31180              </field>
31181              <field>
31182                <name>CNNIRQ_SEL</name>
31183                <description>These bits assign CNNIRQ interrupt flag to selected interrupt signals.</description>
31184                <bitRange>[5:4]</bitRange>
31185                <access>read-write</access>
31186              </field>
31187              <field>
31188                <name>CMPIRQ_SEL</name>
31189                <description>These bits assign URIRQ interrupt flag to selected interrupt signals.</description>
31190                <bitRange>[7:6]</bitRange>
31191                <access>read-write</access>
31192              </field>
31193              <field>
31194                <name>URIRQ_SEL</name>
31195                <description>These bits assign URIRQ interrupt flag to selected interrupt signals.</description>
31196                <bitRange>[9:8]</bitRange>
31197                <access>read-write</access>
31198              </field>
31199              <field>
31200                <name>RWKIRQ_SEL</name>
31201                <description>These bits assign RWKIRQ interrupt flag to selected interrupt signals.</description>
31202                <bitRange>[11:10]</bitRange>
31203                <access>read-write</access>
31204              </field>
31205              <field>
31206                <name>RSVD_13_12</name>
31207                <description>N/A</description>
31208                <bitRange>[13:12]</bitRange>
31209                <access>read-write</access>
31210              </field>
31211              <field>
31212                <name>TCAN_SEL</name>
31213                <description>These bits assign TCAN interrupt flag to selected interrupt signals.</description>
31214                <bitRange>[15:14]</bitRange>
31215                <access>read-write</access>
31216              </field>
31217            </fields>
31218          </register>
31219          <register>
31220            <name>HOST_LVL2_SEL</name>
31221            <description>Host Interrupt Level 2 Selection Register</description>
31222            <addressOffset>0x804</addressOffset>
31223            <size>32</size>
31224            <access>read-write</access>
31225            <resetValue>0x0</resetValue>
31226            <resetMask>0xFF0</resetMask>
31227            <fields>
31228              <field>
31229                <name>EP1_DRQ_SEL</name>
31230                <description>These bits assign EP1_DRQ interrupt flag to selected interrupt signals.</description>
31231                <bitRange>[5:4]</bitRange>
31232                <access>read-write</access>
31233                <enumeratedValues>
31234                  <enumeratedValue>
31235                    <name>HI</name>
31236                    <description>High priority interrupt</description>
31237                    <value>0</value>
31238                  </enumeratedValue>
31239                  <enumeratedValue>
31240                    <name>MED</name>
31241                    <description>Medium priority interrupt</description>
31242                    <value>1</value>
31243                  </enumeratedValue>
31244                  <enumeratedValue>
31245                    <name>LO</name>
31246                    <description>Low priority interrupt</description>
31247                    <value>2</value>
31248                  </enumeratedValue>
31249                  <enumeratedValue>
31250                    <name>RSVD</name>
31251                    <description>N/A</description>
31252                    <value>3</value>
31253                  </enumeratedValue>
31254                </enumeratedValues>
31255              </field>
31256              <field>
31257                <name>EP1_SPK_SEL</name>
31258                <description>These bits assign EP1_SPK interrupt flag to selected interrupt signals.</description>
31259                <bitRange>[7:6]</bitRange>
31260                <access>read-write</access>
31261              </field>
31262              <field>
31263                <name>EP2_DRQ_SEL</name>
31264                <description>These bits assign EP2_DRQ interrupt flag to selected interrupt signals.</description>
31265                <bitRange>[9:8]</bitRange>
31266                <access>read-write</access>
31267              </field>
31268              <field>
31269                <name>EP2_SPK_SEL</name>
31270                <description>These bits assign EP2_SPK interrupt flag to selected interrupt signals.</description>
31271                <bitRange>[11:10]</bitRange>
31272                <access>read-write</access>
31273              </field>
31274            </fields>
31275          </register>
31276          <register>
31277            <name>INTR_USBHOST_CAUSE_HI</name>
31278            <description>Interrupt USB Host Cause High Register</description>
31279            <addressOffset>0x900</addressOffset>
31280            <size>32</size>
31281            <access>read-only</access>
31282            <resetValue>0x0</resetValue>
31283            <resetMask>0xFF</resetMask>
31284            <fields>
31285              <field>
31286                <name>SOFIRQ_INT</name>
31287                <description>SOFIRQ interrupt</description>
31288                <bitRange>[0:0]</bitRange>
31289                <access>read-only</access>
31290              </field>
31291              <field>
31292                <name>DIRQ_INT</name>
31293                <description>DIRQ interrupt</description>
31294                <bitRange>[1:1]</bitRange>
31295                <access>read-only</access>
31296              </field>
31297              <field>
31298                <name>CNNIRQ_INT</name>
31299                <description>CNNIRQ interrupt</description>
31300                <bitRange>[2:2]</bitRange>
31301                <access>read-only</access>
31302              </field>
31303              <field>
31304                <name>CMPIRQ_INT</name>
31305                <description>CMPIRQ interrupt</description>
31306                <bitRange>[3:3]</bitRange>
31307                <access>read-only</access>
31308              </field>
31309              <field>
31310                <name>URIRQ_INT</name>
31311                <description>URIRQ interrupt</description>
31312                <bitRange>[4:4]</bitRange>
31313                <access>read-only</access>
31314              </field>
31315              <field>
31316                <name>RWKIRQ_INT</name>
31317                <description>RWKIRQ interrupt</description>
31318                <bitRange>[5:5]</bitRange>
31319                <access>read-only</access>
31320              </field>
31321              <field>
31322                <name>RSVD_6</name>
31323                <description>N/A</description>
31324                <bitRange>[6:6]</bitRange>
31325                <access>read-only</access>
31326              </field>
31327              <field>
31328                <name>TCAN_INT</name>
31329                <description>TCAN interrupt</description>
31330                <bitRange>[7:7]</bitRange>
31331                <access>read-only</access>
31332              </field>
31333            </fields>
31334          </register>
31335          <register>
31336            <name>INTR_USBHOST_CAUSE_MED</name>
31337            <description>Interrupt USB Host Cause Medium Register</description>
31338            <addressOffset>0x904</addressOffset>
31339            <size>32</size>
31340            <access>read-only</access>
31341            <resetValue>0x0</resetValue>
31342            <resetMask>0xFF</resetMask>
31343            <fields>
31344              <field>
31345                <name>SOFIRQ_INT</name>
31346                <description>SOFIRQ interrupt</description>
31347                <bitRange>[0:0]</bitRange>
31348                <access>read-only</access>
31349              </field>
31350              <field>
31351                <name>DIRQ_INT</name>
31352                <description>DIRQ interrupt</description>
31353                <bitRange>[1:1]</bitRange>
31354                <access>read-only</access>
31355              </field>
31356              <field>
31357                <name>CNNIRQ_INT</name>
31358                <description>CNNIRQ interrupt</description>
31359                <bitRange>[2:2]</bitRange>
31360                <access>read-only</access>
31361              </field>
31362              <field>
31363                <name>CMPIRQ_INT</name>
31364                <description>CMPIRQ interrupt</description>
31365                <bitRange>[3:3]</bitRange>
31366                <access>read-only</access>
31367              </field>
31368              <field>
31369                <name>URIRQ_INT</name>
31370                <description>URIRQ interrupt</description>
31371                <bitRange>[4:4]</bitRange>
31372                <access>read-only</access>
31373              </field>
31374              <field>
31375                <name>RWKIRQ_INT</name>
31376                <description>RWKIRQ interrupt</description>
31377                <bitRange>[5:5]</bitRange>
31378                <access>read-only</access>
31379              </field>
31380              <field>
31381                <name>RSVD_6</name>
31382                <description>N/A</description>
31383                <bitRange>[6:6]</bitRange>
31384                <access>read-only</access>
31385              </field>
31386              <field>
31387                <name>TCAN_INT</name>
31388                <description>TCAN interrupt</description>
31389                <bitRange>[7:7]</bitRange>
31390                <access>read-only</access>
31391              </field>
31392            </fields>
31393          </register>
31394          <register>
31395            <name>INTR_USBHOST_CAUSE_LO</name>
31396            <description>Interrupt USB Host Cause Low Register</description>
31397            <addressOffset>0x908</addressOffset>
31398            <size>32</size>
31399            <access>read-only</access>
31400            <resetValue>0x0</resetValue>
31401            <resetMask>0xFF</resetMask>
31402            <fields>
31403              <field>
31404                <name>SOFIRQ_INT</name>
31405                <description>SOFIRQ interrupt</description>
31406                <bitRange>[0:0]</bitRange>
31407                <access>read-only</access>
31408              </field>
31409              <field>
31410                <name>DIRQ_INT</name>
31411                <description>DIRQ interrupt</description>
31412                <bitRange>[1:1]</bitRange>
31413                <access>read-only</access>
31414              </field>
31415              <field>
31416                <name>CNNIRQ_INT</name>
31417                <description>CNNIRQ interrupt</description>
31418                <bitRange>[2:2]</bitRange>
31419                <access>read-only</access>
31420              </field>
31421              <field>
31422                <name>CMPIRQ_INT</name>
31423                <description>CMPIRQ interrupt</description>
31424                <bitRange>[3:3]</bitRange>
31425                <access>read-only</access>
31426              </field>
31427              <field>
31428                <name>URIRQ_INT</name>
31429                <description>URIRQ interrupt</description>
31430                <bitRange>[4:4]</bitRange>
31431                <access>read-only</access>
31432              </field>
31433              <field>
31434                <name>RWKIRQ_INT</name>
31435                <description>RWKIRQ interrupt</description>
31436                <bitRange>[5:5]</bitRange>
31437                <access>read-only</access>
31438              </field>
31439              <field>
31440                <name>RSVD_6</name>
31441                <description>N/A</description>
31442                <bitRange>[6:6]</bitRange>
31443                <access>read-only</access>
31444              </field>
31445              <field>
31446                <name>TCAN_INT</name>
31447                <description>TCAN interrupt</description>
31448                <bitRange>[7:7]</bitRange>
31449                <access>read-only</access>
31450              </field>
31451            </fields>
31452          </register>
31453          <register>
31454            <name>INTR_HOST_EP_CAUSE_HI</name>
31455            <description>Interrupt USB Host Endpoint Cause High Register</description>
31456            <addressOffset>0x920</addressOffset>
31457            <size>32</size>
31458            <access>read-only</access>
31459            <resetValue>0x0</resetValue>
31460            <resetMask>0x3C</resetMask>
31461            <fields>
31462              <field>
31463                <name>EP1DRQ_INT</name>
31464                <description>EP1DRQ interrupt</description>
31465                <bitRange>[2:2]</bitRange>
31466                <access>read-only</access>
31467              </field>
31468              <field>
31469                <name>EP1SPK_INT</name>
31470                <description>EP1SPK interrupt</description>
31471                <bitRange>[3:3]</bitRange>
31472                <access>read-only</access>
31473              </field>
31474              <field>
31475                <name>EP2DRQ_INT</name>
31476                <description>EP2DRQ interrupt</description>
31477                <bitRange>[4:4]</bitRange>
31478                <access>read-only</access>
31479              </field>
31480              <field>
31481                <name>EP2SPK_INT</name>
31482                <description>EP2SPK interrupt</description>
31483                <bitRange>[5:5]</bitRange>
31484                <access>read-only</access>
31485              </field>
31486            </fields>
31487          </register>
31488          <register>
31489            <name>INTR_HOST_EP_CAUSE_MED</name>
31490            <description>Interrupt USB Host Endpoint Cause Medium Register</description>
31491            <addressOffset>0x924</addressOffset>
31492            <size>32</size>
31493            <access>read-only</access>
31494            <resetValue>0x0</resetValue>
31495            <resetMask>0x3C</resetMask>
31496            <fields>
31497              <field>
31498                <name>EP1DRQ_INT</name>
31499                <description>EP1DRQ interrupt</description>
31500                <bitRange>[2:2]</bitRange>
31501                <access>read-only</access>
31502              </field>
31503              <field>
31504                <name>EP1SPK_INT</name>
31505                <description>EP1SPK interrupt</description>
31506                <bitRange>[3:3]</bitRange>
31507                <access>read-only</access>
31508              </field>
31509              <field>
31510                <name>EP2DRQ_INT</name>
31511                <description>EP2DRQ interrupt</description>
31512                <bitRange>[4:4]</bitRange>
31513                <access>read-only</access>
31514              </field>
31515              <field>
31516                <name>EP2SPK_INT</name>
31517                <description>EP2SPK interrupt</description>
31518                <bitRange>[5:5]</bitRange>
31519                <access>read-only</access>
31520              </field>
31521            </fields>
31522          </register>
31523          <register>
31524            <name>INTR_HOST_EP_CAUSE_LO</name>
31525            <description>Interrupt USB Host Endpoint Cause Low Register</description>
31526            <addressOffset>0x928</addressOffset>
31527            <size>32</size>
31528            <access>read-only</access>
31529            <resetValue>0x0</resetValue>
31530            <resetMask>0x3C</resetMask>
31531            <fields>
31532              <field>
31533                <name>EP1DRQ_INT</name>
31534                <description>EP1DRQ interrupt</description>
31535                <bitRange>[2:2]</bitRange>
31536                <access>read-only</access>
31537              </field>
31538              <field>
31539                <name>EP1SPK_INT</name>
31540                <description>EP1SPK interrupt</description>
31541                <bitRange>[3:3]</bitRange>
31542                <access>read-only</access>
31543              </field>
31544              <field>
31545                <name>EP2DRQ_INT</name>
31546                <description>EP2DRQ interrupt</description>
31547                <bitRange>[4:4]</bitRange>
31548                <access>read-only</access>
31549              </field>
31550              <field>
31551                <name>EP2SPK_INT</name>
31552                <description>EP2SPK interrupt</description>
31553                <bitRange>[5:5]</bitRange>
31554                <access>read-only</access>
31555              </field>
31556            </fields>
31557          </register>
31558          <register>
31559            <name>INTR_USBHOST</name>
31560            <description>Interrupt USB Host Register</description>
31561            <addressOffset>0x940</addressOffset>
31562            <size>32</size>
31563            <access>read-write</access>
31564            <resetValue>0x0</resetValue>
31565            <resetMask>0xFF</resetMask>
31566            <fields>
31567              <field>
31568                <name>SOFIRQ</name>
31569                <description>If this bit is set to '1', it means that SOF token sending is started. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored.
31570'0' : Does not issue an interrupt request by starting a SOF token.
31571'1' : Issues an interrupt request by starting a SOF token.
31572Note :
31573- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
31574                <bitRange>[0:0]</bitRange>
31575                <access>read-write</access>
31576              </field>
31577              <field>
31578                <name>DIRQ</name>
31579                <description>If this bit is set to '1', it means that a device disconnection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored.
31580'0' : Issues no interrupt request by detecting a device disconnection.
31581'1' : Issues an interrupt request by detecting a device disconnection.
31582Note :
31583- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
31584                <bitRange>[1:1]</bitRange>
31585                <access>read-write</access>
31586              </field>
31587              <field>
31588                <name>CNNIRQ</name>
31589                <description>If this bit is set to '1', it means that a device connection is detected. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored.
31590'0' : Issues no interrupt request by detecting a device connection.
31591'1' : Issues an interrupt request by detecting a device connection.
31592Note :
31593- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
31594                <bitRange>[2:2]</bitRange>
31595                <access>read-write</access>
31596              </field>
31597              <field>
31598                <name>CMPIRQ</name>
31599                <description>If this bit is set to '1', it means that a token is completed. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored.
31600'0' : Issues no interrupt request by token completion.
31601'1' : Issues an interrupt request by token completion.
31602Note :
31603- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.
31604- This bit is not set to '1' even if the TCAN bit of the Interrupt USBHost Register (INTR_USBHOST) changes to '1'.
31605- Take the following steps when this bit is set to '1' by finishing IN token or Isochronous IN token.
316061. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to '0'.
316072. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to '1' if HS bit of Host Error Status Register (HOST_ERR) is equal to '00' and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to '1'. Finish the IN token processing if HS bit is not equal to '00'.
316083. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to '1'.</description>
31609                <bitRange>[3:3]</bitRange>
31610                <access>read-write</access>
31611              </field>
31612              <field>
31613                <name>URIRQ</name>
31614                <description>If this bit is set to '1', it means that USB bus resetting is ended. When this bit is '0', it has no meaning. If this bit is written with '1', it is set to '0'. However, if this bit is written with '0', its value is ignored.
31615'0' : Issues no interrupt request by USB bus resetting.
31616'1' : Issues an interrupt request by USB bus resetting.
31617Note :
31618- This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
31619                <bitRange>[4:4]</bitRange>
31620                <access>read-write</access>
31621              </field>
31622              <field>
31623                <name>RWKIRQ</name>
31624                <description>If this bit is set to '1', it means that remote Wake-up is ended. When this bit is '0', it has no meaning. Write '1' to clear, a write of '0' is ignored.
31625'0' : Issues no interrupt request by restart.
31626'1' : Issues an interrupt request by restart.
31627Note :
31628- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
31629                <bitRange>[5:5]</bitRange>
31630                <access>read-write</access>
31631              </field>
31632              <field>
31633                <name>RSVD_6</name>
31634                <description>N/A</description>
31635                <bitRange>[6:6]</bitRange>
31636                <access>read-write</access>
31637              </field>
31638              <field>
31639                <name>TCAN</name>
31640                <description>If this bit is set to '1', it means that token sending is canceled based on the setting of the CANCEL bit of Host Control 2 Register (HOST_CTL2). When this bit is '0', it means that token sending is not canceled. Write '1' to clear, a write of '0' is ignored.
31641'0' : Does not cancel token sending.
31642'1' : Cancels token sending.
31643Note :
31644- This bit is set to the default value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to '1'.</description>
31645                <bitRange>[7:7]</bitRange>
31646                <access>read-write</access>
31647              </field>
31648            </fields>
31649          </register>
31650          <register>
31651            <name>INTR_USBHOST_SET</name>
31652            <description>Interrupt USB Host Set Register</description>
31653            <addressOffset>0x944</addressOffset>
31654            <size>32</size>
31655            <access>read-write</access>
31656            <resetValue>0x0</resetValue>
31657            <resetMask>0xFF</resetMask>
31658            <fields>
31659              <field>
31660                <name>SOFIRQS</name>
31661                <description>This bit sets SOFIRQ bit. If this bit is written to '1', SOFIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
31662                <bitRange>[0:0]</bitRange>
31663                <access>read-write</access>
31664              </field>
31665              <field>
31666                <name>DIRQS</name>
31667                <description>This bit sets DIRQ bit. If this bit is written to '1', DIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
31668                <bitRange>[1:1]</bitRange>
31669                <access>read-write</access>
31670              </field>
31671              <field>
31672                <name>CNNIRQS</name>
31673                <description>This bit sets CNNIRQ bit. If this bit is written to '1', CNNIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
31674                <bitRange>[2:2]</bitRange>
31675                <access>read-write</access>
31676              </field>
31677              <field>
31678                <name>CMPIRQS</name>
31679                <description>This bit sets CMPIRQ bit. If this bit is written to '1', CMPIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
31680                <bitRange>[3:3]</bitRange>
31681                <access>read-write</access>
31682              </field>
31683              <field>
31684                <name>URIRQS</name>
31685                <description>This bit sets URIRQ bit. If this bit is written to '1', URIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
31686                <bitRange>[4:4]</bitRange>
31687                <access>read-write</access>
31688              </field>
31689              <field>
31690                <name>RWKIRQS</name>
31691                <description>This bit sets RWKIRQ bit. If this bit is written to '1', RWKIRQ is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
31692                <bitRange>[5:5]</bitRange>
31693                <access>read-write</access>
31694              </field>
31695              <field>
31696                <name>RSVD_6</name>
31697                <description>N/A</description>
31698                <bitRange>[6:6]</bitRange>
31699                <access>read-write</access>
31700              </field>
31701              <field>
31702                <name>TCANS</name>
31703                <description>This bit sets TCAN bit. If this bit is written to '1', TCAN is set to '1'. However, if this bit is written with '0', its value is ignored.</description>
31704                <bitRange>[7:7]</bitRange>
31705                <access>read-write</access>
31706              </field>
31707            </fields>
31708          </register>
31709          <register>
31710            <name>INTR_USBHOST_MASK</name>
31711            <description>Interrupt USB Host Mask Register</description>
31712            <addressOffset>0x948</addressOffset>
31713            <size>32</size>
31714            <access>read-write</access>
31715            <resetValue>0x0</resetValue>
31716            <resetMask>0xFF</resetMask>
31717            <fields>
31718              <field>
31719                <name>SOFIRQM</name>
31720                <description>This bit masks the interrupt by SOF flag.
31721'0' : Disables
31722'1' : Enables</description>
31723                <bitRange>[0:0]</bitRange>
31724                <access>read-write</access>
31725              </field>
31726              <field>
31727                <name>DIRQM</name>
31728                <description>This bit masks the interrupt by DIRQ flag.
31729'0' : Disables
31730'1' : Enables</description>
31731                <bitRange>[1:1]</bitRange>
31732                <access>read-write</access>
31733              </field>
31734              <field>
31735                <name>CNNIRQM</name>
31736                <description>This bit masks the interrupt by CNNIRQ flag.
31737'0' : Disables
31738'1' : Enables</description>
31739                <bitRange>[2:2]</bitRange>
31740                <access>read-write</access>
31741              </field>
31742              <field>
31743                <name>CMPIRQM</name>
31744                <description>This bit masks the interrupt by CMPIRQ flag.
31745'0' : Disables
31746'1' : Enables</description>
31747                <bitRange>[3:3]</bitRange>
31748                <access>read-write</access>
31749              </field>
31750              <field>
31751                <name>URIRQM</name>
31752                <description>This bit masks the interrupt by URIRQ flag.
31753'0' : Disables
31754'1' : Enables</description>
31755                <bitRange>[4:4]</bitRange>
31756                <access>read-write</access>
31757              </field>
31758              <field>
31759                <name>RWKIRQM</name>
31760                <description>This bit masks the interrupt by RWKIRQ flag.
31761'0' : Disables
31762'1' : Enables</description>
31763                <bitRange>[5:5]</bitRange>
31764                <access>read-write</access>
31765              </field>
31766              <field>
31767                <name>RSVD_6</name>
31768                <description>N/A</description>
31769                <bitRange>[6:6]</bitRange>
31770                <access>read-write</access>
31771              </field>
31772              <field>
31773                <name>TCANM</name>
31774                <description>This bit masks the interrupt by TCAN flag.
31775'0' : Disables
31776'1' : Enables</description>
31777                <bitRange>[7:7]</bitRange>
31778                <access>read-write</access>
31779              </field>
31780            </fields>
31781          </register>
31782          <register>
31783            <name>INTR_USBHOST_MASKED</name>
31784            <description>Interrupt USB Host Masked Register</description>
31785            <addressOffset>0x94C</addressOffset>
31786            <size>32</size>
31787            <access>read-only</access>
31788            <resetValue>0x0</resetValue>
31789            <resetMask>0xFF</resetMask>
31790            <fields>
31791              <field>
31792                <name>SOFIRQED</name>
31793                <description>This bit indicates the interrupt by SOF flag.
31794'0' : Doesn't request the interrupt by SOF
31795'1' : Request the interrupt by SOF</description>
31796                <bitRange>[0:0]</bitRange>
31797                <access>read-only</access>
31798              </field>
31799              <field>
31800                <name>DIRQED</name>
31801                <description>This bit indicates the interrupt by DIRQ flag.
31802'0' : Doesn't request the interrupt by DIRQ
31803'1' : Request the interrupt by DIRQ</description>
31804                <bitRange>[1:1]</bitRange>
31805                <access>read-only</access>
31806              </field>
31807              <field>
31808                <name>CNNIRQED</name>
31809                <description>This bit indicates the interrupt by CNNIRQ flag.
31810'0' : Doesn't request the interrupt by CNNIRQ
31811'1' : Request the interrupt by CNNIRQ</description>
31812                <bitRange>[2:2]</bitRange>
31813                <access>read-only</access>
31814              </field>
31815              <field>
31816                <name>CMPIRQED</name>
31817                <description>This bit indicates the interrupt by CMPIRQ flag.
31818'0' : Doesn't request the interrupt by CMPIRQ
31819'1' : Request the interrupt by CMPIRQ</description>
31820                <bitRange>[3:3]</bitRange>
31821                <access>read-only</access>
31822              </field>
31823              <field>
31824                <name>URIRQED</name>
31825                <description>This bit indicates the interrupt by URIRQ flag.
31826'0' : Doesn't request the interrupt by URIRQ
31827'1' : Request the interrupt by URIRQ</description>
31828                <bitRange>[4:4]</bitRange>
31829                <access>read-only</access>
31830              </field>
31831              <field>
31832                <name>RWKIRQED</name>
31833                <description>This bit indicates the interrupt by RWKIRQ flag.
31834'0' : Doesn't request the interrupt by RWKIRQ
31835'1' : Request the interrupt by RWKIRQ</description>
31836                <bitRange>[5:5]</bitRange>
31837                <access>read-only</access>
31838              </field>
31839              <field>
31840                <name>RSVD_6</name>
31841                <description>N/A</description>
31842                <bitRange>[6:6]</bitRange>
31843                <access>read-only</access>
31844              </field>
31845              <field>
31846                <name>TCANED</name>
31847                <description>This bit indicates the interrupt by TCAN flag.
31848'0' : Doesn't request the interrupt by TCAN
31849'1' : Request the interrupt by TCAN</description>
31850                <bitRange>[7:7]</bitRange>
31851                <access>read-only</access>
31852              </field>
31853            </fields>
31854          </register>
31855          <register>
31856            <name>INTR_HOST_EP</name>
31857            <description>Interrupt USB Host Endpoint Register</description>
31858            <addressOffset>0xA00</addressOffset>
31859            <size>32</size>
31860            <access>read-write</access>
31861            <resetValue>0x0</resetValue>
31862            <resetMask>0x3C</resetMask>
31863            <fields>
31864              <field>
31865                <name>EP1DRQ</name>
31866                <description>This bit indicates that the EP1 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'.
31867'0' : Clears the interrupt cause
31868'1' : Packet transfer normally ended
31869Note :
31870- If automatic buffer transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 1 Control Register (HOST_EP1_CTL)  is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written.</description>
31871                <bitRange>[2:2]</bitRange>
31872                <access>read-write</access>
31873              </field>
31874              <field>
31875                <name>EP1SPK</name>
31876                <description>This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS in the Host Endpoint 1 Control Register (HOST_EP1_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'.
31877'0' : Received data size satisfies the maximum packet size
31878'1' : Received data size does not satisfy the maximum packet size
31879Note :
31880- The EP1SPK bit is not set during data transfer in the OUT direction.</description>
31881                <bitRange>[3:3]</bitRange>
31882                <access>read-write</access>
31883              </field>
31884              <field>
31885                <name>EP2DRQ</name>
31886                <description>This bit indicates that the EP2 packet transfer has normally ended, and processing of the data is required. The DRQ bit is an interrupt cause, and writing '0' is ignored. Clear the DRQ bit by writing '1'.
31887'0' : Clears the interrupt cause
31888'1' : Packet transfer normally ended
31889Note :
31890- If packet transfer mode (DMAE = '1') is not used, '1' must be written to the DRQ bit after data has been written or read to/from the send/receive buffer. Switch the access buffers once the DRQ bit is cleared. That DRQ = '0' may not be read after the DRQ bit is cleared. If the transfer direction is set to OUT, and the DRQ bit is cleared without writing buffer data while the DRQ bit is '1', it implies that 0-byte data is set. If DIR of the Host Endpoint 2 Control Register (HOST_EP2_CTL)  is set to '1' at initial settings, the DRQ bit of corresponding Endpoint is set at the same time. Also while the DRQ bit is not set, '1' must not be written.</description>
31891                <bitRange>[4:4]</bitRange>
31892                <access>read-write</access>
31893              </field>
31894              <field>
31895                <name>EP2SPK</name>
31896                <description>This bit indicates that the data size transferred from the host does not satisfy the maximum packet size (including 0-byte) set by PKS1 in the Host Endpoint 2 Control Register (HOST_EP2_CTL) when the data has been received successfully. This bit is an interrupt cause, and writing '0' is ignored. Clear it by writing '1'.
31897'0' : Received data size satisfies the maximum packet size
31898'1' : Received data size does not satisfy the maximum packet size
31899Note :
31900- The SPK bit is not set during data transfer in the OUT direction.</description>
31901                <bitRange>[5:5]</bitRange>
31902                <access>read-write</access>
31903              </field>
31904            </fields>
31905          </register>
31906          <register>
31907            <name>INTR_HOST_EP_SET</name>
31908            <description>Interrupt USB Host Endpoint Set Register</description>
31909            <addressOffset>0xA04</addressOffset>
31910            <size>32</size>
31911            <access>read-write</access>
31912            <resetValue>0x0</resetValue>
31913            <resetMask>0x3C</resetMask>
31914            <fields>
31915              <field>
31916                <name>EP1DRQS</name>
31917                <description>This bit sets EP1DRQ bit. If this bit is written to '1', EP1DRQ is set to '1'. However, if this bit is written with '0', its value is ignored.
31918Note:
31919If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1DRQ can't be set to '1'.</description>
31920                <bitRange>[2:2]</bitRange>
31921                <access>read-write</access>
31922              </field>
31923              <field>
31924                <name>EP1SPKS</name>
31925                <description>This bit sets EP1SPK bit. If this bit is written to '1', EP1SPK is set to '1'. However, if this bit is written with '0', its value is ignored.
31926Note:
31927If BFINI bit of the Host Endpoint 1 Control Register (HOST_EP1_CTL) is '1', EP1SPK can't be set to '1'.</description>
31928                <bitRange>[3:3]</bitRange>
31929                <access>read-write</access>
31930              </field>
31931              <field>
31932                <name>EP2DRQS</name>
31933                <description>This bit sets EP2DRQ bit. If this bit is written to '1', EP2DRQ is set to '1'. However, if this bit is written with '0', its value is ignored.
31934Note:
31935If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2DRQ can't be set to '1'.</description>
31936                <bitRange>[4:4]</bitRange>
31937                <access>read-write</access>
31938              </field>
31939              <field>
31940                <name>EP2SPKS</name>
31941                <description>This bit sets EP2SPK bit. If this bit is written to '1', EP2SPK is set to '1'. However, if this bit is written with '0', its value is ignored.
31942Note:
31943If BFINI bit of the Host Endpoint 2 Control Register (HOST_EP2_CTL) is '1', EP2SPK can't be set to '1'.</description>
31944                <bitRange>[5:5]</bitRange>
31945                <access>read-write</access>
31946              </field>
31947            </fields>
31948          </register>
31949          <register>
31950            <name>INTR_HOST_EP_MASK</name>
31951            <description>Interrupt USB Host Endpoint Mask Register</description>
31952            <addressOffset>0xA08</addressOffset>
31953            <size>32</size>
31954            <access>read-write</access>
31955            <resetValue>0x0</resetValue>
31956            <resetMask>0x3C</resetMask>
31957            <fields>
31958              <field>
31959                <name>EP1DRQM</name>
31960                <description>This bit masks the interrupt by EP1DRQ flag.
31961'0' : Disables
31962'1' : Enables</description>
31963                <bitRange>[2:2]</bitRange>
31964                <access>read-write</access>
31965              </field>
31966              <field>
31967                <name>EP1SPKM</name>
31968                <description>This bit masks the interrupt by EP1SPK flag.
31969'0' : Disables
31970'1' : Enables</description>
31971                <bitRange>[3:3]</bitRange>
31972                <access>read-write</access>
31973              </field>
31974              <field>
31975                <name>EP2DRQM</name>
31976                <description>This bit masks the interrupt by EP2DRQ flag.
31977'0' : Disables
31978'1' : Enables</description>
31979                <bitRange>[4:4]</bitRange>
31980                <access>read-write</access>
31981              </field>
31982              <field>
31983                <name>EP2SPKM</name>
31984                <description>This bit masks the interrupt by EP2SPK flag.
31985'0' : Disables
31986'1' : Enables</description>
31987                <bitRange>[5:5]</bitRange>
31988                <access>read-write</access>
31989              </field>
31990            </fields>
31991          </register>
31992          <register>
31993            <name>INTR_HOST_EP_MASKED</name>
31994            <description>Interrupt USB Host Endpoint Masked Register</description>
31995            <addressOffset>0xA0C</addressOffset>
31996            <size>32</size>
31997            <access>read-only</access>
31998            <resetValue>0x0</resetValue>
31999            <resetMask>0x3C</resetMask>
32000            <fields>
32001              <field>
32002                <name>EP1DRQED</name>
32003                <description>This bit indicates the interrupt by EP1DRQ flag.
32004'0' : Doesn't request the interrupt by EP1DRQ
32005'1' : Request the interrupt by EP1DRQ</description>
32006                <bitRange>[2:2]</bitRange>
32007                <access>read-only</access>
32008              </field>
32009              <field>
32010                <name>EP1SPKED</name>
32011                <description>This bit indicates the interrupt by EP1SPK flag.
32012'0' : Doesn't request the interrupt by EP1SPK
32013'1' : Request the interrupt by EP1SPK</description>
32014                <bitRange>[3:3]</bitRange>
32015                <access>read-only</access>
32016              </field>
32017              <field>
32018                <name>EP2DRQED</name>
32019                <description>This bit indicates the interrupt by EP2DRQ flag.
32020'0' : Doesn't request the interrupt by EP2DRQ
32021'1' : Request the interrupt by EP2DRQ</description>
32022                <bitRange>[4:4]</bitRange>
32023                <access>read-only</access>
32024              </field>
32025              <field>
32026                <name>EP2SPKED</name>
32027                <description>This bit indicates the interrupt by EP2SPK flag.
32028'0' : Doesn't request the interrupt by EP2SPK
32029'1' : Request the interrupt by EP2SPK</description>
32030                <bitRange>[5:5]</bitRange>
32031                <access>read-only</access>
32032              </field>
32033            </fields>
32034          </register>
32035          <register>
32036            <name>HOST_DMA_ENBL</name>
32037            <description>Host DMA Enable Register</description>
32038            <addressOffset>0xB00</addressOffset>
32039            <size>32</size>
32040            <access>read-write</access>
32041            <resetValue>0x0</resetValue>
32042            <resetMask>0xC</resetMask>
32043            <fields>
32044              <field>
32045                <name>DM_EP1DRQE</name>
32046                <description>This bit enables DMA Request by EP1DRQ.
32047'0' : Disable
32048'1' : Enable</description>
32049                <bitRange>[2:2]</bitRange>
32050                <access>read-write</access>
32051              </field>
32052              <field>
32053                <name>DM_EP2DRQE</name>
32054                <description>This bit enables DMA Request by EP2DRQ.
32055'0' : Disable
32056'1' : Enable</description>
32057                <bitRange>[3:3]</bitRange>
32058                <access>read-write</access>
32059              </field>
32060            </fields>
32061          </register>
32062          <register>
32063            <name>HOST_EP1_BLK</name>
32064            <description>Host Endpoint 1 Block Register</description>
32065            <addressOffset>0xB20</addressOffset>
32066            <size>32</size>
32067            <access>read-write</access>
32068            <resetValue>0x0</resetValue>
32069            <resetMask>0xFFFF0000</resetMask>
32070            <fields>
32071              <field>
32072                <name>BLK_NUM</name>
32073                <description>Set the total byte number for DMA transfer. If HOST_EP1_RW1_DR or HOST_EP1_RW2_DR is written, the block number counter is decremented when DMAE='1'.
32074- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP1DRQE='1')</description>
32075                <bitRange>[31:16]</bitRange>
32076                <access>read-write</access>
32077              </field>
32078            </fields>
32079          </register>
32080          <register>
32081            <name>HOST_EP2_BLK</name>
32082            <description>Host Endpoint 2 Block Register</description>
32083            <addressOffset>0xB30</addressOffset>
32084            <size>32</size>
32085            <access>read-write</access>
32086            <resetValue>0x0</resetValue>
32087            <resetMask>0xFFFF0000</resetMask>
32088            <fields>
32089              <field>
32090                <name>BLK_NUM</name>
32091                <description>Set the total byte number for DMA transfer. If HOST_EP2_RW1_DR or HOST_EP2_RW2_DR is written, the block number counter is decremented when DMAE='1'.
32092- Set this bits before DMA transfer is enabled (HOST_DMA_ENBL.DM_DP2DRQE='1')</description>
32093                <bitRange>[31:16]</bitRange>
32094                <access>read-write</access>
32095              </field>
32096            </fields>
32097          </register>
32098        </cluster>
32099      </registers>
32100    </peripheral>
32101    <peripheral>
32102      <name>SMIF0</name>
32103      <description>Serial Memory Interface</description>
32104      <headerStructName>SMIF</headerStructName>
32105      <baseAddress>0x40420000</baseAddress>
32106      <addressBlock>
32107        <offset>0</offset>
32108        <size>65536</size>
32109        <usage>registers</usage>
32110      </addressBlock>
32111      <registers>
32112        <register>
32113          <name>CTL</name>
32114          <description>Control</description>
32115          <addressOffset>0x0</addressOffset>
32116          <size>32</size>
32117          <access>read-write</access>
32118          <resetValue>0x3000</resetValue>
32119          <resetMask>0x81073001</resetMask>
32120          <fields>
32121            <field>
32122              <name>XIP_MODE</name>
32123              <description>Mode of operation.
32124
32125Note: this field should only be changed when the IP is disabled or when STATUS.BUSY is '0' and SW should not be executing from the XIP interface or MMIO interface.</description>
32126              <bitRange>[0:0]</bitRange>
32127              <access>read-write</access>
32128              <enumeratedValues>
32129                <enumeratedValue>
32130                  <name>MMIO_MODE</name>
32131                  <description>'0': MMIO mode. Individual MMIO accesses to TX and RX FIFOs are used to generate a sequence of SPI transfers. This mode of operation allows for large flexibility in terms of the SPI transfers that can be generated.</description>
32132                  <value>0</value>
32133                </enumeratedValue>
32134                <enumeratedValue>
32135                  <name>XIP_MODE</name>
32136                  <description>1': XIP mode. eXecute-In-Place mode: incoming read and write transfers over the AHB-Lite bus infrastructure are automatically translated in SPI transfers to read data from and write data to a device. This mode of operation allow for efficient device read and write operations. This mode is only supported in SPI_MODE.</description>
32137                  <value>1</value>
32138                </enumeratedValue>
32139              </enumeratedValues>
32140            </field>
32141            <field>
32142              <name>CLOCK_IF_RX_SEL</name>
32143              <description>Specifies device interface receiver clock 'clk_if_rx' source. MISO data is captured on the rising edge of 'clk_if_rx'.
32144'0': 'spi_clk_out' (internal clock)
32145'1': !'spi_clk_out' (internal clock)
32146'2': 'spi_clk_in' (feedback clock)
32147'3': !'spi_clk_in' (feedback clock)
32148
32149Note: the device interface transmitter clock 'clk_if_tx' is fixed and is 'spi_clk_out' MOSI data is driven on the falling edge of 'clk_if_tx'.</description>
32150              <bitRange>[13:12]</bitRange>
32151              <access>read-write</access>
32152            </field>
32153            <field>
32154              <name>DESELECT_DELAY</name>
32155              <description>Specifies the minimum duration of SPI deselection ('spi_select_out[]' is high/'1') in between SPI transfers:
32156'0': 1 interface clock cycle.
32157'1': 2 interface clock cycles.
32158'2': 3 interface clock cycles.
32159'3': 4 interface clock cycles.
32160'4': 5 interface clock cycles.
32161'5': 6 interface clock cycles.
32162'6': 7 interface clock cycles.
32163'7': 8 interface clock cycles.
32164
32165During SPI deselection, 'spi_select_out[]' are '1'/inactive, 'spi_data_out[]' are '1' and 'spi_clk_out' is '0'/inactive.</description>
32166              <bitRange>[18:16]</bitRange>
32167              <access>read-write</access>
32168            </field>
32169            <field>
32170              <name>BLOCK</name>
32171              <description>Specifies what happens for MMIO interface read accesses to an empty RX data FIFO or to a full TX format/data FIFO. Note: the FIFOs can only be accessed in MMIO_MODE.
32172
32173This field is not used for test controller accesses.</description>
32174              <bitRange>[24:24]</bitRange>
32175              <access>read-write</access>
32176              <enumeratedValues>
32177                <enumeratedValue>
32178                  <name>BUS_ERROR</name>
32179                  <description>0': Generate an AHB-Lite bus error. This option is useful when SW decides to use polling on STATUS.TR_BUSY to determine if a interface transfer is no longer busy (transfer is completed). This option adds SW complexity, but limits the number of AHB-Lite wait states (and limits ISR latency).</description>
32180                  <value>0</value>
32181                </enumeratedValue>
32182                <enumeratedValue>
32183                  <name>WAIT_STATES</name>
32184                  <description>1': Introduce wait states. This setting potentially locks up the AHB-Lite infrastructure and may increase the CPU interrupt latency.This option is useful when SW performs TX/RX data FIFO accesses immediately after a command is setup using the TX format FIFO. This option has low SW complexity, but may result in a significant number of AHB-Lite wait states (and may increase ISR latency).</description>
32185                  <value>1</value>
32186                </enumeratedValue>
32187              </enumeratedValues>
32188            </field>
32189            <field>
32190              <name>ENABLED</name>
32191              <description>IP enable:
32192'0': Disabled. All non-retention registers are reset to their default value when the IP is disabled. When the IP is disabled, the XIP accesses produce AHB-Lite bus errors.
32193'1': Enabled.
32194
32195Note: Before disabling the IP, SW should ensure that the IP is NOT busy (STATUS.BUSY is '0'), otherwise illegal interface transfers may occur.</description>
32196              <bitRange>[31:31]</bitRange>
32197              <access>read-write</access>
32198              <enumeratedValues>
32199                <enumeratedValue>
32200                  <name>DISABLED</name>
32201                  <description>N/A</description>
32202                  <value>0</value>
32203                </enumeratedValue>
32204                <enumeratedValue>
32205                  <name>ENABLED</name>
32206                  <description>N/A</description>
32207                  <value>1</value>
32208                </enumeratedValue>
32209              </enumeratedValues>
32210            </field>
32211          </fields>
32212        </register>
32213        <register>
32214          <name>STATUS</name>
32215          <description>Status</description>
32216          <addressOffset>0x4</addressOffset>
32217          <size>32</size>
32218          <access>read-only</access>
32219          <resetValue>0x0</resetValue>
32220          <resetMask>0x80000000</resetMask>
32221          <fields>
32222            <field>
32223              <name>BUSY</name>
32224              <description>Cache, cryptography, XIP, device interface or any other logic busy in the IP:
32225'0': not busy
32226'1': busy
32227When BUSY is '0', the IP can be safely disabled without:
32228- the potential loss of transient write data.
32229- the potential risk of aborting an inflight SPI device interface transfer.
32230When BUSY is '0', the mode of operation (XIP_MODE or MMIO_MODE) can be safely changed.</description>
32231              <bitRange>[31:31]</bitRange>
32232              <access>read-only</access>
32233            </field>
32234          </fields>
32235        </register>
32236        <register>
32237          <name>TX_CMD_FIFO_STATUS</name>
32238          <description>Transmitter command FIFO status</description>
32239          <addressOffset>0x44</addressOffset>
32240          <size>32</size>
32241          <access>read-only</access>
32242          <resetValue>0x0</resetValue>
32243          <resetMask>0x7</resetMask>
32244          <fields>
32245            <field>
32246              <name>USED3</name>
32247              <description>Number of entries that are used in the TX command FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 4].</description>
32248              <bitRange>[2:0]</bitRange>
32249              <access>read-only</access>
32250            </field>
32251          </fields>
32252        </register>
32253        <register>
32254          <name>TX_CMD_FIFO_WR</name>
32255          <description>Transmitter command FIFO write</description>
32256          <addressOffset>0x50</addressOffset>
32257          <size>32</size>
32258          <access>write-only</access>
32259          <resetValue>0x0</resetValue>
32260          <resetMask>0xFFFFF</resetMask>
32261          <fields>
32262            <field>
32263              <name>DATA20</name>
32264              <description>Command data. The higher two bits DATA[19:18] specify the specific command
32265'0'/TX: A SPI transfer always start with a TX command FIFO entry of the 'TX' format.
32266- DATA[17:16] specifies the width of the data transfer:
32267   - '0': 1 bit/cycle (single data transfer).
32268   - '1': 2 bits/cycle (dual data transfer).
32269   - '2': 4 bits/cycle (quad data transfer).
32270   - '3': 8 bits/cycle (octal data transfer).
32271- DATA[15]: specifies whether this is the last TX Byte; i.e. whether the 'spi_select_out[3:0]' IO output signals are de-activated after the transfer.
32272- DATA[11:8] specifies which of the four devices are selected. DATA[11:8] are directly mapped to 'spi_select_out[3:0]'. Two devices can be selected at the same time in dual-quad mode.
32273  - '0': device deselected
32274  - '1': device selected
32275- DATA[7:0] specifies the transmitted Byte.
32276
32277'1'/TX_COUNT: The 'TX_COUNT' command relies on the TX data FIFO to provide the transmitted bytes. The 'TX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers.
32278- DATA[17:16] specifies the width of the transfer.
32279- DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) from the TX data FIFO.
32280
32281'2'/RX_COUNT: The 'RX_COUNT' command relies on the RX data FIFO to accept the received bytes. The 'RX_COUNT' command is ALWAYS considered to be the last command of a SPI data transfers.
32282- DATA[17:16] specifies the width of the transfer.
32283- DATA[15:0] specifies the number of to be transmitted Bytes (minus 1) to the RX data FIFO.
32284
32285'3'/DUMMY_COUNT: The 'DUMMY_COUNT' command conveys dummy cycles. Dummy cycles are used to implement a Turn-Around time in which the SPI master changes from a transmitter driving the data lines to a receiver receiving on the same data lines. The 'DUMMY_COUNT' command is ALWAYS considered to be NOT the last command of a SPI data transfers; i.e. it needs to be followed by another command.
32286- DATA[15:0] specifies the number of dummy cycles (minus 1). In dummy cycles, the data lines are not driven.</description>
32287              <bitRange>[19:0]</bitRange>
32288              <access>write-only</access>
32289            </field>
32290          </fields>
32291        </register>
32292        <register>
32293          <name>TX_DATA_FIFO_CTL</name>
32294          <description>Transmitter data FIFO control</description>
32295          <addressOffset>0x80</addressOffset>
32296          <size>32</size>
32297          <access>read-write</access>
32298          <resetValue>0x0</resetValue>
32299          <resetMask>0x7</resetMask>
32300          <fields>
32301            <field>
32302              <name>TRIGGER_LEVEL</name>
32303              <description>Determines when the TX data FIFO 'tr_tx_req' trigger is activated  (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE):
32304- Trigger is active when TX_DATA_FIFO_STATUS.USED &lt;= TRIGGER_LEVEL.</description>
32305              <bitRange>[2:0]</bitRange>
32306              <access>read-write</access>
32307            </field>
32308          </fields>
32309        </register>
32310        <register>
32311          <name>TX_DATA_FIFO_STATUS</name>
32312          <description>Transmitter data FIFO status</description>
32313          <addressOffset>0x84</addressOffset>
32314          <size>32</size>
32315          <access>read-only</access>
32316          <resetValue>0x0</resetValue>
32317          <resetMask>0xF</resetMask>
32318          <fields>
32319            <field>
32320              <name>USED4</name>
32321              <description>Number of entries that are used in the TX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8].</description>
32322              <bitRange>[3:0]</bitRange>
32323              <access>read-only</access>
32324            </field>
32325          </fields>
32326        </register>
32327        <register>
32328          <name>TX_DATA_FIFO_WR1</name>
32329          <description>Transmitter data FIFO write</description>
32330          <addressOffset>0x90</addressOffset>
32331          <size>32</size>
32332          <access>write-only</access>
32333          <resetValue>0x0</resetValue>
32334          <resetMask>0xFF</resetMask>
32335          <fields>
32336            <field>
32337              <name>DATA0</name>
32338              <description>TX data (written to TX data FIFO).</description>
32339              <bitRange>[7:0]</bitRange>
32340              <access>write-only</access>
32341            </field>
32342          </fields>
32343        </register>
32344        <register>
32345          <name>TX_DATA_FIFO_WR2</name>
32346          <description>Transmitter data FIFO write</description>
32347          <addressOffset>0x94</addressOffset>
32348          <size>32</size>
32349          <access>write-only</access>
32350          <resetValue>0x0</resetValue>
32351          <resetMask>0xFFFF</resetMask>
32352          <fields>
32353            <field>
32354              <name>DATA0</name>
32355              <description>TX data (written to TX data FIFO, first byte).</description>
32356              <bitRange>[7:0]</bitRange>
32357              <access>write-only</access>
32358            </field>
32359            <field>
32360              <name>DATA1</name>
32361              <description>TX data (written to TX data FIFO, second byte).</description>
32362              <bitRange>[15:8]</bitRange>
32363              <access>write-only</access>
32364            </field>
32365          </fields>
32366        </register>
32367        <register>
32368          <name>TX_DATA_FIFO_WR4</name>
32369          <description>Transmitter data FIFO write</description>
32370          <addressOffset>0x98</addressOffset>
32371          <size>32</size>
32372          <access>write-only</access>
32373          <resetValue>0x0</resetValue>
32374          <resetMask>0xFFFFFFFF</resetMask>
32375          <fields>
32376            <field>
32377              <name>DATA0</name>
32378              <description>TX data (written to TX data FIFO, first byte).</description>
32379              <bitRange>[7:0]</bitRange>
32380              <access>write-only</access>
32381            </field>
32382            <field>
32383              <name>DATA1</name>
32384              <description>TX data (written to TX data FIFO, second byte).</description>
32385              <bitRange>[15:8]</bitRange>
32386              <access>write-only</access>
32387            </field>
32388            <field>
32389              <name>DATA2</name>
32390              <description>TX data (written to TX data FIFO, third byte).</description>
32391              <bitRange>[23:16]</bitRange>
32392              <access>write-only</access>
32393            </field>
32394            <field>
32395              <name>DATA3</name>
32396              <description>TX data (written to TX data FIFO, fourth byte).</description>
32397              <bitRange>[31:24]</bitRange>
32398              <access>write-only</access>
32399            </field>
32400          </fields>
32401        </register>
32402        <register>
32403          <name>RX_DATA_FIFO_CTL</name>
32404          <description>Receiver data FIFO control</description>
32405          <addressOffset>0xC0</addressOffset>
32406          <size>32</size>
32407          <access>read-write</access>
32408          <resetValue>0x0</resetValue>
32409          <resetMask>0x7</resetMask>
32410          <fields>
32411            <field>
32412              <name>TRIGGER_LEVEL</name>
32413              <description>Determines when RX data FIFO 'tr_rx_req' trigger is activated (trigger activation requires MMIO_MODE, the trigger is NOT activated in XIP_MODE):
32414- Trigger is active when RX_DATA_FIFO_STATUS.USED &gt; TRIGGER_LEVEL.</description>
32415              <bitRange>[2:0]</bitRange>
32416              <access>read-write</access>
32417            </field>
32418          </fields>
32419        </register>
32420        <register>
32421          <name>RX_DATA_FIFO_STATUS</name>
32422          <description>Receiver data FIFO status</description>
32423          <addressOffset>0xC4</addressOffset>
32424          <size>32</size>
32425          <access>read-only</access>
32426          <resetValue>0x0</resetValue>
32427          <resetMask>0xF</resetMask>
32428          <fields>
32429            <field>
32430              <name>USED4</name>
32431              <description>Number of entries that are used in the RX data FIFO (available in both XIP_MODE and MMIO_MODE). Legal range: [0, 8].</description>
32432              <bitRange>[3:0]</bitRange>
32433              <access>read-only</access>
32434            </field>
32435          </fields>
32436        </register>
32437        <register>
32438          <name>RX_DATA_FIFO_RD1</name>
32439          <description>Receiver data FIFO read</description>
32440          <addressOffset>0xD0</addressOffset>
32441          <size>32</size>
32442          <access>read-only</access>
32443          <resetValue>0x0</resetValue>
32444          <resetMask>0xFF</resetMask>
32445          <fields>
32446            <field>
32447              <name>DATA0</name>
32448              <description>RX data (read from RX data FIFO).</description>
32449              <bitRange>[7:0]</bitRange>
32450              <access>read-only</access>
32451            </field>
32452          </fields>
32453        </register>
32454        <register>
32455          <name>RX_DATA_FIFO_RD2</name>
32456          <description>Receiver data FIFO read</description>
32457          <addressOffset>0xD4</addressOffset>
32458          <size>32</size>
32459          <access>read-only</access>
32460          <resetValue>0x0</resetValue>
32461          <resetMask>0xFFFF</resetMask>
32462          <fields>
32463            <field>
32464              <name>DATA0</name>
32465              <description>RX data (read from RX data FIFO, first byte).</description>
32466              <bitRange>[7:0]</bitRange>
32467              <access>read-only</access>
32468            </field>
32469            <field>
32470              <name>DATA1</name>
32471              <description>RX data (read from RX data FIFO, second byte).</description>
32472              <bitRange>[15:8]</bitRange>
32473              <access>read-only</access>
32474            </field>
32475          </fields>
32476        </register>
32477        <register>
32478          <name>RX_DATA_FIFO_RD4</name>
32479          <description>Receiver data FIFO read</description>
32480          <addressOffset>0xD8</addressOffset>
32481          <size>32</size>
32482          <access>read-only</access>
32483          <resetValue>0x0</resetValue>
32484          <resetMask>0xFFFFFFFF</resetMask>
32485          <fields>
32486            <field>
32487              <name>DATA0</name>
32488              <description>RX data (read from RX data FIFO, first byte).</description>
32489              <bitRange>[7:0]</bitRange>
32490              <access>read-only</access>
32491            </field>
32492            <field>
32493              <name>DATA1</name>
32494              <description>RX data (read from RX data FIFO, second byte).</description>
32495              <bitRange>[15:8]</bitRange>
32496              <access>read-only</access>
32497            </field>
32498            <field>
32499              <name>DATA2</name>
32500              <description>RX data (read from RX data FIFO, third byte).</description>
32501              <bitRange>[23:16]</bitRange>
32502              <access>read-only</access>
32503            </field>
32504            <field>
32505              <name>DATA3</name>
32506              <description>RX data (read from RX data FIFO, fourth byte).</description>
32507              <bitRange>[31:24]</bitRange>
32508              <access>read-only</access>
32509            </field>
32510          </fields>
32511        </register>
32512        <register>
32513          <name>RX_DATA_FIFO_RD1_SILENT</name>
32514          <description>Receiver data FIFO silent read</description>
32515          <addressOffset>0xE0</addressOffset>
32516          <size>32</size>
32517          <access>read-only</access>
32518          <resetValue>0x0</resetValue>
32519          <resetMask>0xFF</resetMask>
32520          <fields>
32521            <field>
32522              <name>DATA0</name>
32523              <description>RX data (read from RX data FIFO).</description>
32524              <bitRange>[7:0]</bitRange>
32525              <access>read-only</access>
32526            </field>
32527          </fields>
32528        </register>
32529        <register>
32530          <name>SLOW_CA_CTL</name>
32531          <description>Slow cache control</description>
32532          <addressOffset>0x100</addressOffset>
32533          <size>32</size>
32534          <access>read-write</access>
32535          <resetValue>0xC0000000</resetValue>
32536          <resetMask>0xC3030000</resetMask>
32537          <fields>
32538            <field>
32539              <name>WAY</name>
32540              <description>Specifies the cache way for which cache information is provided in SLOW_CA_STATUS0/1/2.</description>
32541              <bitRange>[17:16]</bitRange>
32542              <access>read-write</access>
32543            </field>
32544            <field>
32545              <name>SET_ADDR</name>
32546              <description>Specifies the cache set for which cache information is provided in SLOW_CA_STATUS0/1/2.</description>
32547              <bitRange>[25:24]</bitRange>
32548              <access>read-write</access>
32549            </field>
32550            <field>
32551              <name>PREF_EN</name>
32552              <description>Prefetch enable:
32553'0': Disabled.
32554'1': Enabled.
32555
32556Prefetching requires the cache to be enabled; i.e. ENABLED is '1'.</description>
32557              <bitRange>[30:30]</bitRange>
32558              <access>read-write</access>
32559            </field>
32560            <field>
32561              <name>ENABLED</name>
32562              <description>Cache enable:
32563'0': Disabled.
32564'1': Enabled.</description>
32565              <bitRange>[31:31]</bitRange>
32566              <access>read-write</access>
32567            </field>
32568          </fields>
32569        </register>
32570        <register>
32571          <name>SLOW_CA_CMD</name>
32572          <description>Slow cache command</description>
32573          <addressOffset>0x108</addressOffset>
32574          <size>32</size>
32575          <access>read-write</access>
32576          <resetValue>0x0</resetValue>
32577          <resetMask>0x1</resetMask>
32578          <fields>
32579            <field>
32580              <name>INV</name>
32581              <description>Cache and prefetch buffer invalidation.
32582SW writes a '1' to clear the cache and prefetch buffer. The cache's LRU structure is also reset to its default state.
32583Note,
32584A write access will invalidate the prefetch buffer automatically in hardware.
32585A write access should invalidate both fast and slow caches, by firmware.
32586Note, firmware should invalidate the cache and prefetch buffer only when STATUS.BUSY is '0'.</description>
32587              <bitRange>[0:0]</bitRange>
32588              <access>read-write</access>
32589            </field>
32590          </fields>
32591        </register>
32592        <register>
32593          <name>FAST_CA_CTL</name>
32594          <description>Fast cache control</description>
32595          <addressOffset>0x180</addressOffset>
32596          <size>32</size>
32597          <access>read-write</access>
32598          <resetValue>0xC0000000</resetValue>
32599          <resetMask>0xC3030000</resetMask>
32600          <fields>
32601            <field>
32602              <name>WAY</name>
32603              <description>See SLOW_CA_CTL.WAY.</description>
32604              <bitRange>[17:16]</bitRange>
32605              <access>read-write</access>
32606            </field>
32607            <field>
32608              <name>SET_ADDR</name>
32609              <description>See SLOW_CA_CTL.SET_ADDR.</description>
32610              <bitRange>[25:24]</bitRange>
32611              <access>read-write</access>
32612            </field>
32613            <field>
32614              <name>PREF_EN</name>
32615              <description>See SLOW_CA_CTL.PREF_EN.</description>
32616              <bitRange>[30:30]</bitRange>
32617              <access>read-write</access>
32618            </field>
32619            <field>
32620              <name>ENABLED</name>
32621              <description>See SLOW_CA_CTL.ENABLED.</description>
32622              <bitRange>[31:31]</bitRange>
32623              <access>read-write</access>
32624            </field>
32625          </fields>
32626        </register>
32627        <register>
32628          <name>FAST_CA_CMD</name>
32629          <description>Fast cache command</description>
32630          <addressOffset>0x188</addressOffset>
32631          <size>32</size>
32632          <access>read-write</access>
32633          <resetValue>0x0</resetValue>
32634          <resetMask>0x1</resetMask>
32635          <fields>
32636            <field>
32637              <name>INV</name>
32638              <description>See SLOW_CA_CMD.INV.</description>
32639              <bitRange>[0:0]</bitRange>
32640              <access>read-write</access>
32641            </field>
32642          </fields>
32643        </register>
32644        <register>
32645          <name>CRYPTO_CMD</name>
32646          <description>Cryptography Command</description>
32647          <addressOffset>0x200</addressOffset>
32648          <size>32</size>
32649          <access>read-write</access>
32650          <resetValue>0x0</resetValue>
32651          <resetMask>0x1</resetMask>
32652          <fields>
32653            <field>
32654              <name>START</name>
32655              <description>SW sets this field to '1' to start a AES-128 forward block cipher operation (on the address in CRYPTO_ADDR). HW sets this field to '0' to indicate that the operation has completed. Once completed, the result of the operation can be read from CRYPTO_RESULT0, ..., CRYPTO_RESULT3.
32656
32657The operation takes roughly 13 clk_hf clock cycles.
32658
32659Note: An operation can only be started in MMIO_MODE.</description>
32660              <bitRange>[0:0]</bitRange>
32661              <access>read-write</access>
32662            </field>
32663          </fields>
32664        </register>
32665        <register>
32666          <name>CRYPTO_INPUT0</name>
32667          <description>Cryptography input 0</description>
32668          <addressOffset>0x220</addressOffset>
32669          <size>32</size>
32670          <access>read-write</access>
32671          <resetValue>0x0</resetValue>
32672          <resetMask>0x0</resetMask>
32673          <fields>
32674            <field>
32675              <name>INPUT</name>
32676              <description>Four Bytes of the plaintext PT[31:0] = CRYPTO_INPUT0.INPUT[31:0].</description>
32677              <bitRange>[31:0]</bitRange>
32678              <access>read-write</access>
32679            </field>
32680          </fields>
32681        </register>
32682        <register>
32683          <name>CRYPTO_INPUT1</name>
32684          <description>Cryptography input 1</description>
32685          <addressOffset>0x224</addressOffset>
32686          <size>32</size>
32687          <access>read-write</access>
32688          <resetValue>0x0</resetValue>
32689          <resetMask>0x0</resetMask>
32690          <fields>
32691            <field>
32692              <name>INPUT</name>
32693              <description>Four Bytes of the plaintext PT[63:32] = CRYPTO_INPUT1.INPUT[31:0].</description>
32694              <bitRange>[31:0]</bitRange>
32695              <access>read-write</access>
32696            </field>
32697          </fields>
32698        </register>
32699        <register>
32700          <name>CRYPTO_INPUT2</name>
32701          <description>Cryptography input 2</description>
32702          <addressOffset>0x228</addressOffset>
32703          <size>32</size>
32704          <access>read-write</access>
32705          <resetValue>0x0</resetValue>
32706          <resetMask>0x0</resetMask>
32707          <fields>
32708            <field>
32709              <name>INPUT</name>
32710              <description>Four Bytes of the plaintext PT[95:64] = CRYPTO_INPUT2.INPUT[31:0].</description>
32711              <bitRange>[31:0]</bitRange>
32712              <access>read-write</access>
32713            </field>
32714          </fields>
32715        </register>
32716        <register>
32717          <name>CRYPTO_INPUT3</name>
32718          <description>Cryptography input 3</description>
32719          <addressOffset>0x22C</addressOffset>
32720          <size>32</size>
32721          <access>read-write</access>
32722          <resetValue>0x0</resetValue>
32723          <resetMask>0x0</resetMask>
32724          <fields>
32725            <field>
32726              <name>INPUT</name>
32727              <description>Four Bytes of the plaintext PT[127:96] = CRYPTO_INPUT3.INPUT[31:0].</description>
32728              <bitRange>[31:0]</bitRange>
32729              <access>read-write</access>
32730            </field>
32731          </fields>
32732        </register>
32733        <register>
32734          <name>CRYPTO_KEY0</name>
32735          <description>Cryptography key 0</description>
32736          <addressOffset>0x240</addressOffset>
32737          <size>32</size>
32738          <access>write-only</access>
32739          <resetValue>0x0</resetValue>
32740          <resetMask>0x0</resetMask>
32741          <fields>
32742            <field>
32743              <name>KEY</name>
32744              <description>Four Bytes of the key KEY[31:0] = CRYPTO_KEY0.KEY[31:0].</description>
32745              <bitRange>[31:0]</bitRange>
32746              <access>write-only</access>
32747            </field>
32748          </fields>
32749        </register>
32750        <register>
32751          <name>CRYPTO_KEY1</name>
32752          <description>Cryptography key 1</description>
32753          <addressOffset>0x244</addressOffset>
32754          <size>32</size>
32755          <access>write-only</access>
32756          <resetValue>0x0</resetValue>
32757          <resetMask>0x0</resetMask>
32758          <fields>
32759            <field>
32760              <name>KEY</name>
32761              <description>Four Bytes of the key KEY[63:32] = CRYPTO_KEY1.KEY[31:0].</description>
32762              <bitRange>[31:0]</bitRange>
32763              <access>write-only</access>
32764            </field>
32765          </fields>
32766        </register>
32767        <register>
32768          <name>CRYPTO_KEY2</name>
32769          <description>Cryptography key 2</description>
32770          <addressOffset>0x248</addressOffset>
32771          <size>32</size>
32772          <access>write-only</access>
32773          <resetValue>0x0</resetValue>
32774          <resetMask>0x0</resetMask>
32775          <fields>
32776            <field>
32777              <name>KEY</name>
32778              <description>Four Bytes of the key KEY[95:64] = CRYPTO_KEY2.KEY[31:0].</description>
32779              <bitRange>[31:0]</bitRange>
32780              <access>write-only</access>
32781            </field>
32782          </fields>
32783        </register>
32784        <register>
32785          <name>CRYPTO_KEY3</name>
32786          <description>Cryptography key 3</description>
32787          <addressOffset>0x24C</addressOffset>
32788          <size>32</size>
32789          <access>write-only</access>
32790          <resetValue>0x0</resetValue>
32791          <resetMask>0x0</resetMask>
32792          <fields>
32793            <field>
32794              <name>KEY</name>
32795              <description>Four Bytes of the key KEY[127:96] = CRYPTO_KEY3.KEY[31:0].</description>
32796              <bitRange>[31:0]</bitRange>
32797              <access>write-only</access>
32798            </field>
32799          </fields>
32800        </register>
32801        <register>
32802          <name>CRYPTO_OUTPUT0</name>
32803          <description>Cryptography output 0</description>
32804          <addressOffset>0x260</addressOffset>
32805          <size>32</size>
32806          <access>read-write</access>
32807          <resetValue>0x0</resetValue>
32808          <resetMask>0x0</resetMask>
32809          <fields>
32810            <field>
32811              <name>OUTPUT</name>
32812              <description>Four Bytes of the ciphertext CT[31:0] = CRYPTO_OUTPUT0.OUTPUT[31:0].</description>
32813              <bitRange>[31:0]</bitRange>
32814              <access>read-write</access>
32815            </field>
32816          </fields>
32817        </register>
32818        <register>
32819          <name>CRYPTO_OUTPUT1</name>
32820          <description>Cryptography output 1</description>
32821          <addressOffset>0x264</addressOffset>
32822          <size>32</size>
32823          <access>read-write</access>
32824          <resetValue>0x0</resetValue>
32825          <resetMask>0x0</resetMask>
32826          <fields>
32827            <field>
32828              <name>OUTPUT</name>
32829              <description>Four Bytes of the ciphertext CT[63:32] = CRYPTO_OUTPUT1.OUTPUT[31:0].</description>
32830              <bitRange>[31:0]</bitRange>
32831              <access>read-write</access>
32832            </field>
32833          </fields>
32834        </register>
32835        <register>
32836          <name>CRYPTO_OUTPUT2</name>
32837          <description>Cryptography output 2</description>
32838          <addressOffset>0x268</addressOffset>
32839          <size>32</size>
32840          <access>read-write</access>
32841          <resetValue>0x0</resetValue>
32842          <resetMask>0x0</resetMask>
32843          <fields>
32844            <field>
32845              <name>OUTPUT</name>
32846              <description>Four Bytes of the ciphertext CT[95:64] = CRYPTO_OUTPUT2.OUTPUT[31:0].</description>
32847              <bitRange>[31:0]</bitRange>
32848              <access>read-write</access>
32849            </field>
32850          </fields>
32851        </register>
32852        <register>
32853          <name>CRYPTO_OUTPUT3</name>
32854          <description>Cryptography output 3</description>
32855          <addressOffset>0x26C</addressOffset>
32856          <size>32</size>
32857          <access>read-write</access>
32858          <resetValue>0x0</resetValue>
32859          <resetMask>0x0</resetMask>
32860          <fields>
32861            <field>
32862              <name>OUTPUT</name>
32863              <description>Four Bytes of the ciphertext CT[127:96] = CRYPTO_OUTPUT3.OUTPUT[31:0].</description>
32864              <bitRange>[31:0]</bitRange>
32865              <access>read-write</access>
32866            </field>
32867          </fields>
32868        </register>
32869        <register>
32870          <name>INTR</name>
32871          <description>Interrupt register</description>
32872          <addressOffset>0x7C0</addressOffset>
32873          <size>32</size>
32874          <access>read-write</access>
32875          <resetValue>0x0</resetValue>
32876          <resetMask>0x3F</resetMask>
32877          <fields>
32878            <field>
32879              <name>TR_TX_REQ</name>
32880              <description>Activated in MMIO mode, when a TX data FIFO trigger 'tr_tx_req' is activated.</description>
32881              <bitRange>[0:0]</bitRange>
32882              <access>read-write</access>
32883            </field>
32884            <field>
32885              <name>TR_RX_REQ</name>
32886              <description>Activated in MMIO mode, when a RX data FIFO trigger 'tr_rx_req' is activated.</description>
32887              <bitRange>[1:1]</bitRange>
32888              <access>read-write</access>
32889            </field>
32890            <field>
32891              <name>XIP_ALIGNMENT_ERROR</name>
32892              <description>Activated in XIP mode, if:
32893- The selected device's ADDR_CTL.DIV2 is '1' and the AHB-Lite bus transfer address is not a multiple of 2.
32894- The selected device's ADDR_CTL.DIV2 is '1' and the XIP transfer request is NOT for a multiple of 2 Bytes.
32895
32896Note: In dual-quad SPI mode (ADDR_CTL.DIV is '1'), each memory device contributes a 4-bit nibble for read data or write data. This is only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2.</description>
32897              <bitRange>[2:2]</bitRange>
32898              <access>read-write</access>
32899            </field>
32900            <field>
32901              <name>TX_CMD_FIFO_OVERFLOW</name>
32902              <description>Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available.</description>
32903              <bitRange>[3:3]</bitRange>
32904              <access>read-write</access>
32905            </field>
32906            <field>
32907              <name>TX_DATA_FIFO_OVERFLOW</name>
32908              <description>Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, TX_DATA_FIFO_WR4) with not enough free entries available.</description>
32909              <bitRange>[4:4]</bitRange>
32910              <access>read-write</access>
32911            </field>
32912            <field>
32913              <name>RX_DATA_FIFO_UNDERFLOW</name>
32914              <description>Activated in MMIO mode, on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FIFO_RD1, RX_DATA_FIFO_RD2, RX_DATA_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers.</description>
32915              <bitRange>[5:5]</bitRange>
32916              <access>read-write</access>
32917            </field>
32918          </fields>
32919        </register>
32920        <register>
32921          <name>INTR_SET</name>
32922          <description>Interrupt set register</description>
32923          <addressOffset>0x7C4</addressOffset>
32924          <size>32</size>
32925          <access>read-write</access>
32926          <resetValue>0x0</resetValue>
32927          <resetMask>0x3F</resetMask>
32928          <fields>
32929            <field>
32930              <name>TR_TX_REQ</name>
32931              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32932              <bitRange>[0:0]</bitRange>
32933              <access>read-write</access>
32934            </field>
32935            <field>
32936              <name>TR_RX_REQ</name>
32937              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32938              <bitRange>[1:1]</bitRange>
32939              <access>read-write</access>
32940            </field>
32941            <field>
32942              <name>XIP_ALIGNMENT_ERROR</name>
32943              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32944              <bitRange>[2:2]</bitRange>
32945              <access>read-write</access>
32946            </field>
32947            <field>
32948              <name>TX_CMD_FIFO_OVERFLOW</name>
32949              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32950              <bitRange>[3:3]</bitRange>
32951              <access>read-write</access>
32952            </field>
32953            <field>
32954              <name>TX_DATA_FIFO_OVERFLOW</name>
32955              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32956              <bitRange>[4:4]</bitRange>
32957              <access>read-write</access>
32958            </field>
32959            <field>
32960              <name>RX_DATA_FIFO_UNDERFLOW</name>
32961              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
32962              <bitRange>[5:5]</bitRange>
32963              <access>read-write</access>
32964            </field>
32965          </fields>
32966        </register>
32967        <register>
32968          <name>INTR_MASK</name>
32969          <description>Interrupt mask register</description>
32970          <addressOffset>0x7C8</addressOffset>
32971          <size>32</size>
32972          <access>read-write</access>
32973          <resetValue>0x0</resetValue>
32974          <resetMask>0x3F</resetMask>
32975          <fields>
32976            <field>
32977              <name>TR_TX_REQ</name>
32978              <description>Mask bit for corresponding bit in interrupt request register.</description>
32979              <bitRange>[0:0]</bitRange>
32980              <access>read-write</access>
32981            </field>
32982            <field>
32983              <name>TR_RX_REQ</name>
32984              <description>Mask bit for corresponding bit in interrupt request register.</description>
32985              <bitRange>[1:1]</bitRange>
32986              <access>read-write</access>
32987            </field>
32988            <field>
32989              <name>XIP_ALIGNMENT_ERROR</name>
32990              <description>Mask bit for corresponding bit in interrupt request register.</description>
32991              <bitRange>[2:2]</bitRange>
32992              <access>read-write</access>
32993            </field>
32994            <field>
32995              <name>TX_CMD_FIFO_OVERFLOW</name>
32996              <description>Mask bit for corresponding bit in interrupt request register.</description>
32997              <bitRange>[3:3]</bitRange>
32998              <access>read-write</access>
32999            </field>
33000            <field>
33001              <name>TX_DATA_FIFO_OVERFLOW</name>
33002              <description>Mask bit for corresponding bit in interrupt request register.</description>
33003              <bitRange>[4:4]</bitRange>
33004              <access>read-write</access>
33005            </field>
33006            <field>
33007              <name>RX_DATA_FIFO_UNDERFLOW</name>
33008              <description>Mask bit for corresponding bit in interrupt request register.</description>
33009              <bitRange>[5:5]</bitRange>
33010              <access>read-write</access>
33011            </field>
33012          </fields>
33013        </register>
33014        <register>
33015          <name>INTR_MASKED</name>
33016          <description>Interrupt masked register</description>
33017          <addressOffset>0x7CC</addressOffset>
33018          <size>32</size>
33019          <access>read-only</access>
33020          <resetValue>0x0</resetValue>
33021          <resetMask>0x3F</resetMask>
33022          <fields>
33023            <field>
33024              <name>TR_TX_REQ</name>
33025              <description>Logical and of corresponding request and mask bits.</description>
33026              <bitRange>[0:0]</bitRange>
33027              <access>read-only</access>
33028            </field>
33029            <field>
33030              <name>TR_RX_REQ</name>
33031              <description>Logical and of corresponding request and mask bits.</description>
33032              <bitRange>[1:1]</bitRange>
33033              <access>read-only</access>
33034            </field>
33035            <field>
33036              <name>XIP_ALIGNMENT_ERROR</name>
33037              <description>Logical and of corresponding request and mask bits.</description>
33038              <bitRange>[2:2]</bitRange>
33039              <access>read-only</access>
33040            </field>
33041            <field>
33042              <name>TX_CMD_FIFO_OVERFLOW</name>
33043              <description>Logical and of corresponding request and mask bits.</description>
33044              <bitRange>[3:3]</bitRange>
33045              <access>read-only</access>
33046            </field>
33047            <field>
33048              <name>TX_DATA_FIFO_OVERFLOW</name>
33049              <description>Logical and of corresponding request and mask bits.</description>
33050              <bitRange>[4:4]</bitRange>
33051              <access>read-only</access>
33052            </field>
33053            <field>
33054              <name>RX_DATA_FIFO_UNDERFLOW</name>
33055              <description>Logical and of corresponding request and mask bits.</description>
33056              <bitRange>[5:5]</bitRange>
33057              <access>read-only</access>
33058            </field>
33059          </fields>
33060        </register>
33061        <cluster>
33062          <dim>4</dim>
33063          <dimIncrement>128</dimIncrement>
33064          <name>DEVICE[%s]</name>
33065          <description>Device (only used in XIP mode)</description>
33066          <addressOffset>0x00000800</addressOffset>
33067          <register>
33068            <name>CTL</name>
33069            <description>Control</description>
33070            <addressOffset>0x0</addressOffset>
33071            <size>32</size>
33072            <access>read-write</access>
33073            <resetValue>0x0</resetValue>
33074            <resetMask>0x80030101</resetMask>
33075            <fields>
33076              <field>
33077                <name>WR_EN</name>
33078                <description>Write enable:
33079'0': write transfers are not allowed to this device. An attempt to write to this device results in an AHB-Lite bus error.
33080'1': write transfers are allowed to this device.</description>
33081                <bitRange>[0:0]</bitRange>
33082                <access>read-write</access>
33083              </field>
33084              <field>
33085                <name>CRYPTO_EN</name>
33086                <description>Cryptography on read/write accesses:
33087'0': disabled.
33088'1': enabled.</description>
33089                <bitRange>[8:8]</bitRange>
33090                <access>read-write</access>
33091              </field>
33092              <field>
33093                <name>DATA_SEL</name>
33094                <description>Specifies the connection of the IP's data lines (spi_data[0], ..., spi_data[7]) to the device's data lines (SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7):
33095'0': spi_data[0] = IO0, spi_data[1] = IO1, ..., spi_data[7] = IO7. This value is allowed for single, dual, quad, dual quad and octal SPI modes. This value must be used for the first device in dual quad SPI mode. This value must be used for octal SPI mode.
33096'1': spi_data[2] = IO0, spi_data[3] = IO1. This value is only allowed for single and dual SPI modes.
33097'2': spi_data[4] = IO0, spi_data[5] = IO1, ..., spi_data[7] = IO3. This value is only allowed for single, dual, quad and dual quad  SPI modes. In dual quad SPI mode, this value must be used for the second device.
33098'3': spi_data[6] = IO0, spi_data[7] = IO1. This value is only allowed for single and dual SPI modes.</description>
33099                <bitRange>[17:16]</bitRange>
33100                <access>read-write</access>
33101              </field>
33102              <field>
33103                <name>ENABLED</name>
33104                <description>Device enable:
33105'0': Disabled.
33106'1': Enabled.</description>
33107                <bitRange>[31:31]</bitRange>
33108                <access>read-write</access>
33109              </field>
33110            </fields>
33111          </register>
33112          <register>
33113            <name>ADDR</name>
33114            <description>Device region base address</description>
33115            <addressOffset>0x8</addressOffset>
33116            <size>32</size>
33117            <access>read-write</access>
33118            <resetValue>0x0</resetValue>
33119            <resetMask>0x0</resetMask>
33120            <fields>
33121              <field>
33122                <name>ADDR</name>
33123                <description>Specifies the base address of the device region. If the device region is 2^m Bytes, ADDR MUST be a multiple of 2^m.
33124
33125In dual quad SPI data transfer, the two devices should have the same ADDR and MASK register settings. The device control information (ADDR_CTL, RD_CMD_CTL, etc.) are provided by the MMIO control registers of the device with the lowest index.
33126
33127The most significant bit fields are constants and set based on the SMIF_XIP_ADDR parameter. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK is 0xff00:0000 (16 MB XIP memory region), ADDR[31:24] = SMIF_XIP_ADDR[31:24].</description>
33128                <bitRange>[31:8]</bitRange>
33129                <access>read-write</access>
33130              </field>
33131            </fields>
33132          </register>
33133          <register>
33134            <name>MASK</name>
33135            <description>Device region mask</description>
33136            <addressOffset>0xC</addressOffset>
33137            <size>32</size>
33138            <access>read-write</access>
33139            <resetValue>0x0</resetValue>
33140            <resetMask>0x0</resetMask>
33141            <fields>
33142              <field>
33143                <name>MASK</name>
33144                <description>Specifies the size of the device region. All '1' bits are used to compare the incoming transfer request address A[31:0] with the address as specified in ADDR.ADDR: Address A is in the device when (A[31:8] &amp; MASK[31:8]) == ADDR.ADDR[31:8].
33145
33146The most significant bit fields are constants and set to'1'. The most significant bits are identified on the SMIF_XIP_MASK parameter. E.g., if SMIF_XIP_MASK  is 0xff00:0000 (16 MB XIP memory region), MASK[31:24] = 0xff.
33147
33148Note: a transfer request that is not in any device region results in an AHB-Lite bus error.</description>
33149                <bitRange>[31:8]</bitRange>
33150                <access>read-write</access>
33151              </field>
33152            </fields>
33153          </register>
33154          <register>
33155            <name>ADDR_CTL</name>
33156            <description>Address control</description>
33157            <addressOffset>0x20</addressOffset>
33158            <size>32</size>
33159            <access>read-write</access>
33160            <resetValue>0x0</resetValue>
33161            <resetMask>0x103</resetMask>
33162            <fields>
33163              <field>
33164                <name>SIZE2</name>
33165                <description>Specifies the size of the XIP device address in Bytes:
33166'0': 1 Byte address.
33167'1': 2 Byte address.
33168'2': 3 Byte address.
33169'3': 4 Byte address.
33170The lower significant address Bytes of the transfer request are used as XIP address to the external device. Note that for dual quad SPI data transfer, the transfer request address is divided by 2. Therefore, the transfer request address needs to be a multiple of 2. If the trasnfer requestaddress is NOT a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.</description>
33171                <bitRange>[1:0]</bitRange>
33172                <access>read-write</access>
33173              </field>
33174              <field>
33175                <name>DIV2</name>
33176                <description>Specifies if the AHB-Lite bus transfer address is divided by 2 or not:
33177'0': No divide by 2.
33178'1': Divide by 2.
33179
33180This functionality is used for read and write operation in XIP, dual quad SPI mode; i.e. this DIV2 must be set to '1' in dual quad SPI mode. If the transfer request address is NOT a multiple of 2 or the requested number of Bytes is not a multiple of 2, the XIP_ALIGNMENT_ERROR interrupt cause is activated.</description>
33181                <bitRange>[8:8]</bitRange>
33182                <access>read-write</access>
33183              </field>
33184            </fields>
33185          </register>
33186          <register>
33187            <name>RD_CMD_CTL</name>
33188            <description>Read command control</description>
33189            <addressOffset>0x40</addressOffset>
33190            <size>32</size>
33191            <access>read-write</access>
33192            <resetValue>0x0</resetValue>
33193            <resetMask>0x800300FF</resetMask>
33194            <fields>
33195              <field>
33196                <name>CODE</name>
33197                <description>Command byte code.</description>
33198                <bitRange>[7:0]</bitRange>
33199                <access>read-write</access>
33200              </field>
33201              <field>
33202                <name>WIDTH</name>
33203                <description>Width of data transfer:
33204'0': 1 bit/cycle (single data transfer).
33205'1': 2 bits/cycle (dual data transfer).
33206'2': 4 bits/cycle (quad data transfer).
33207'3': 8 bits/cycle (octal data transfer).</description>
33208                <bitRange>[17:16]</bitRange>
33209                <access>read-write</access>
33210              </field>
33211              <field>
33212                <name>PRESENT</name>
33213                <description>Presence of command field:
33214'0': not present
33215'1': present</description>
33216                <bitRange>[31:31]</bitRange>
33217                <access>read-write</access>
33218              </field>
33219            </fields>
33220          </register>
33221          <register>
33222            <name>RD_ADDR_CTL</name>
33223            <description>Read address control</description>
33224            <addressOffset>0x44</addressOffset>
33225            <size>32</size>
33226            <access>read-write</access>
33227            <resetValue>0x0</resetValue>
33228            <resetMask>0x30000</resetMask>
33229            <fields>
33230              <field>
33231                <name>WIDTH</name>
33232                <description>Width of transfer.</description>
33233                <bitRange>[17:16]</bitRange>
33234                <access>read-write</access>
33235              </field>
33236            </fields>
33237          </register>
33238          <register>
33239            <name>RD_MODE_CTL</name>
33240            <description>Read mode control</description>
33241            <addressOffset>0x48</addressOffset>
33242            <size>32</size>
33243            <access>read-write</access>
33244            <resetValue>0x0</resetValue>
33245            <resetMask>0x800300FF</resetMask>
33246            <fields>
33247              <field>
33248                <name>CODE</name>
33249                <description>Mode byte code.</description>
33250                <bitRange>[7:0]</bitRange>
33251                <access>read-write</access>
33252              </field>
33253              <field>
33254                <name>WIDTH</name>
33255                <description>Width of transfer.</description>
33256                <bitRange>[17:16]</bitRange>
33257                <access>read-write</access>
33258              </field>
33259              <field>
33260                <name>PRESENT</name>
33261                <description>Presence of mode field:
33262'0': not present
33263'1': present</description>
33264                <bitRange>[31:31]</bitRange>
33265                <access>read-write</access>
33266              </field>
33267            </fields>
33268          </register>
33269          <register>
33270            <name>RD_DUMMY_CTL</name>
33271            <description>Read dummy control</description>
33272            <addressOffset>0x4C</addressOffset>
33273            <size>32</size>
33274            <access>read-write</access>
33275            <resetValue>0x0</resetValue>
33276            <resetMask>0x8000001F</resetMask>
33277            <fields>
33278              <field>
33279                <name>SIZE5</name>
33280                <description>Number of dummy cycles (minus 1):
33281'0': 1 cycles
33282...
33283'31': 32 cycles.
33284
33285Note: this field specifies dummy cycles, not dummy Bytes!</description>
33286                <bitRange>[4:0]</bitRange>
33287                <access>read-write</access>
33288              </field>
33289              <field>
33290                <name>PRESENT</name>
33291                <description>Presence of dummy cycles:
33292'0': not present
33293'1': present</description>
33294                <bitRange>[31:31]</bitRange>
33295                <access>read-write</access>
33296              </field>
33297            </fields>
33298          </register>
33299          <register>
33300            <name>RD_DATA_CTL</name>
33301            <description>Read data control</description>
33302            <addressOffset>0x50</addressOffset>
33303            <size>32</size>
33304            <access>read-write</access>
33305            <resetValue>0x0</resetValue>
33306            <resetMask>0x30000</resetMask>
33307            <fields>
33308              <field>
33309                <name>WIDTH</name>
33310                <description>Width of transfer.</description>
33311                <bitRange>[17:16]</bitRange>
33312                <access>read-write</access>
33313              </field>
33314            </fields>
33315          </register>
33316          <register>
33317            <name>WR_CMD_CTL</name>
33318            <description>Write command control</description>
33319            <addressOffset>0x60</addressOffset>
33320            <size>32</size>
33321            <access>read-write</access>
33322            <resetValue>0x0</resetValue>
33323            <resetMask>0x800300FF</resetMask>
33324            <fields>
33325              <field>
33326                <name>CODE</name>
33327                <description>Command byte code.</description>
33328                <bitRange>[7:0]</bitRange>
33329                <access>read-write</access>
33330              </field>
33331              <field>
33332                <name>WIDTH</name>
33333                <description>Width of transfer.</description>
33334                <bitRange>[17:16]</bitRange>
33335                <access>read-write</access>
33336              </field>
33337              <field>
33338                <name>PRESENT</name>
33339                <description>Presence of command field:
33340'0': not present
33341'1': present</description>
33342                <bitRange>[31:31]</bitRange>
33343                <access>read-write</access>
33344              </field>
33345            </fields>
33346          </register>
33347          <register>
33348            <name>WR_ADDR_CTL</name>
33349            <description>Write address control</description>
33350            <addressOffset>0x64</addressOffset>
33351            <size>32</size>
33352            <access>read-write</access>
33353            <resetValue>0x0</resetValue>
33354            <resetMask>0x30000</resetMask>
33355            <fields>
33356              <field>
33357                <name>WIDTH</name>
33358                <description>Width of transfer.</description>
33359                <bitRange>[17:16]</bitRange>
33360                <access>read-write</access>
33361              </field>
33362            </fields>
33363          </register>
33364          <register>
33365            <name>WR_MODE_CTL</name>
33366            <description>Write mode control</description>
33367            <addressOffset>0x68</addressOffset>
33368            <size>32</size>
33369            <access>read-write</access>
33370            <resetValue>0x0</resetValue>
33371            <resetMask>0x800300FF</resetMask>
33372            <fields>
33373              <field>
33374                <name>CODE</name>
33375                <description>Mode byte code.</description>
33376                <bitRange>[7:0]</bitRange>
33377                <access>read-write</access>
33378              </field>
33379              <field>
33380                <name>WIDTH</name>
33381                <description>Width of transfer.</description>
33382                <bitRange>[17:16]</bitRange>
33383                <access>read-write</access>
33384              </field>
33385              <field>
33386                <name>PRESENT</name>
33387                <description>Presence of mode field:
33388'0': not present
33389'1': present</description>
33390                <bitRange>[31:31]</bitRange>
33391                <access>read-write</access>
33392              </field>
33393            </fields>
33394          </register>
33395          <register>
33396            <name>WR_DUMMY_CTL</name>
33397            <description>Write dummy control</description>
33398            <addressOffset>0x6C</addressOffset>
33399            <size>32</size>
33400            <access>read-write</access>
33401            <resetValue>0x0</resetValue>
33402            <resetMask>0x8000001F</resetMask>
33403            <fields>
33404              <field>
33405                <name>SIZE5</name>
33406                <description>Number of dummy cycles (minus 1):
33407'0': 1 cycles
33408...
33409'31': 32 cycles.</description>
33410                <bitRange>[4:0]</bitRange>
33411                <access>read-write</access>
33412              </field>
33413              <field>
33414                <name>PRESENT</name>
33415                <description>Presence of dummy cycles:
33416'0': not present
33417'1': present</description>
33418                <bitRange>[31:31]</bitRange>
33419                <access>read-write</access>
33420              </field>
33421            </fields>
33422          </register>
33423          <register>
33424            <name>WR_DATA_CTL</name>
33425            <description>Write data control</description>
33426            <addressOffset>0x70</addressOffset>
33427            <size>32</size>
33428            <access>read-write</access>
33429            <resetValue>0x0</resetValue>
33430            <resetMask>0x30000</resetMask>
33431            <fields>
33432              <field>
33433                <name>WIDTH</name>
33434                <description>Width of transfer.</description>
33435                <bitRange>[17:16]</bitRange>
33436                <access>read-write</access>
33437              </field>
33438            </fields>
33439          </register>
33440        </cluster>
33441      </registers>
33442    </peripheral>
33443    <peripheral>
33444      <name>SDHC0</name>
33445      <description>SD/eMMC Host Controller</description>
33446      <headerStructName>SDHC</headerStructName>
33447      <baseAddress>0x40460000</baseAddress>
33448      <addressBlock>
33449        <offset>0</offset>
33450        <size>65536</size>
33451        <usage>registers</usage>
33452      </addressBlock>
33453      <registers>
33454        <cluster>
33455          <name>WRAP</name>
33456          <description>MMIO at SDHC wrapper level</description>
33457          <addressOffset>0x00000000</addressOffset>
33458          <register>
33459            <name>CTL</name>
33460            <description>Top level wrapper control</description>
33461            <addressOffset>0x0</addressOffset>
33462            <size>32</size>
33463            <access>read-write</access>
33464            <resetValue>0x0</resetValue>
33465            <resetMask>0x80000000</resetMask>
33466            <fields>
33467              <field>
33468                <name>ENABLE</name>
33469                <description>IP Enable:
334700: IP disabled, RAM in DeepSleep, SDHC_CORE regs are inaccessible (any attempts to access will result in AHB Error responses), IP is NOT held in reset but the clocks are gated
334711: IP enabled, normal operation</description>
33472                <bitRange>[31:31]</bitRange>
33473                <access>read-write</access>
33474              </field>
33475            </fields>
33476          </register>
33477        </cluster>
33478        <cluster>
33479          <name>CORE</name>
33480          <description>MMIO for Synopsys Mobile Storage Host Controller IP</description>
33481          <addressOffset>0x00001000</addressOffset>
33482          <register>
33483            <name>SDMASA_R</name>
33484            <description>SDMA System Address register</description>
33485            <addressOffset>0x0</addressOffset>
33486            <size>32</size>
33487            <access>read-write</access>
33488            <resetValue>0x0</resetValue>
33489            <resetMask>0xFFFFFFFF</resetMask>
33490            <fields>
33491              <field>
33492                <name>BLOCKCNT_SDMASA</name>
33493                <description>32-bit Block Count (SDMA System Address)
33494- SDMA System Address (Host Version 4 Enable = 0): This
33495register contains the system memory address for an
33496SDMA transfer in the 32-bit addressing mode. When the
33497Host Controller stops an SDMA transfer, this register
33498points to the system address of the next contiguous data
33499position. It can be accessed only if no transaction is
33500executing. Reading this register during data transfers may
33501return an invalid value.
33502- 32-bit Block Count (Host Version 4 Enable = 1): From the
33503Host Controller Version 4.10 specification, this register is
33504redefined as 32-bit Block Count. The Host Controller
33505decrements the block count of this register for every block
33506transfer and the data transfer stops when the count
33507reaches zero. This register must be accessed when no
33508transaction is executing. Reading this register during data
33509transfers may return invalid value.
33510Following are the values for BLOCKCNT_SDMASA:
33511- 0xFFFF_FFFF - 4G - 1 Block
33512- ......
33513- 0x0000_0002 - 2 Blocks
33514- 0x0000_0001 - 1 Block
33515- 0x0000_0000 - Stop Count
33516Note:
33517- When Host Version 4 Enable = 0, SDMA uses this register as system address and hence Auto CMD23 cannot be used with SDMA since this register is assigned for Auto CMD23 as 32-bit Block Count register.
33518-When Host Version 4 Enable = 1, SDMA uses ADMA system address register and this register is reassigned to 32-bit Block Count. This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. SDMA may use Auto CMD23 if 32-bit Block Count register is used.</description>
33519                <bitRange>[31:0]</bitRange>
33520                <access>read-write</access>
33521              </field>
33522            </fields>
33523          </register>
33524          <register>
33525            <name>BLOCKSIZE_R</name>
33526            <description>Block Size register</description>
33527            <addressOffset>0x4</addressOffset>
33528            <size>16</size>
33529            <access>read-write</access>
33530            <resetValue>0x0</resetValue>
33531            <resetMask>0x7FFF</resetMask>
33532            <fields>
33533              <field>
33534                <name>XFER_BLOCK_SIZE</name>
33535                <description>Transfer Block Size
33536These bits specify the block size of data transfers. In case of
33537memory, it is set to 512 bytes. It can be accessed only if no
33538transaction is executing. Read operations during transfers
33539may return an invalid value, and write operations are
33540ignored. Following are the values for XFER_BLOCK_SIZE:
33541- 0x1: 1 byte
33542- 0x2: 2 bytes
33543- 0x3: 3 bytes
33544- ......
33545- 0x1FF: 511 byte
33546- 0x200: 512 bytes
33547- ......
33548- 0x800: 2048 bytes
33549Note: This register must be programmed with a non-zero
33550value for data transfer.</description>
33551                <bitRange>[11:0]</bitRange>
33552                <access>read-write</access>
33553              </field>
33554              <field>
33555                <name>SDMA_BUF_BDARY</name>
33556                <description>SDMA Buffer Boundary
33557These bits specify the size of contiguous buffer in system
33558memory. The SDMA transfer waits at every boundary
33559specified by these fields and the Host Controller generates
33560the DMA interrupt to request the Host Driver to update the
33561SDMA System Address register.
33562Values:
33563- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary
33564- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary
33565- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary
33566- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary
33567- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary
33568- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary
33569- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary
33570- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary</description>
33571                <bitRange>[14:12]</bitRange>
33572                <access>read-write</access>
33573              </field>
33574            </fields>
33575          </register>
33576          <register>
33577            <name>BLOCKCOUNT_R</name>
33578            <description>16-bit Block Count register</description>
33579            <addressOffset>0x6</addressOffset>
33580            <size>16</size>
33581            <access>read-write</access>
33582            <resetValue>0x0</resetValue>
33583            <resetMask>0xFFFF</resetMask>
33584            <fields>
33585              <field>
33586                <name>BLOCK_CNT</name>
33587                <description>16-bit Block Count
33588- If the Host Version 4 Enable bit is set 0 or the 16-bit Block
33589Count register is set to non-zero, the 16-bit Block Count
33590register is selected.
33591- If the Host Version 4 Enable bit is set 1 and the 16-bit
33592Block Count register is set to zero, the 32-bit Block Count
33593register is selected.
33594Following are the values for BLOCK_CNT:
33595- 0x0: Stop Count
33596- 0x1: 1 Block
33597- 0x2: 2 Blocks
33598- ... - ...
33599- 0xFFFF: 65535 Blocks
33600Note: For Host Version 4 Enable = 0, this register must be
33601set to 0000h before programming the 32-bit block count
33602register when Auto CMD23 is enabled for non-DMA and
33603ADMA modes.</description>
33604                <bitRange>[15:0]</bitRange>
33605                <access>read-write</access>
33606              </field>
33607            </fields>
33608          </register>
33609          <register>
33610            <name>ARGUMENT_R</name>
33611            <description>Argument register</description>
33612            <addressOffset>0x8</addressOffset>
33613            <size>32</size>
33614            <access>read-write</access>
33615            <resetValue>0x0</resetValue>
33616            <resetMask>0xFFFFFFFF</resetMask>
33617            <fields>
33618              <field>
33619                <name>ARGUMENT</name>
33620                <description>Command Argument
33621These bits specify the SD/eMMC command argument that is
33622specified in bits 39-8 of the Command format.</description>
33623                <bitRange>[31:0]</bitRange>
33624                <access>read-write</access>
33625              </field>
33626            </fields>
33627          </register>
33628          <register>
33629            <name>XFER_MODE_R</name>
33630            <description>Transfer Mode register</description>
33631            <addressOffset>0xC</addressOffset>
33632            <size>16</size>
33633            <access>read-write</access>
33634            <resetValue>0x0</resetValue>
33635            <resetMask>0x1FF</resetMask>
33636            <fields>
33637              <field>
33638                <name>DMA_ENABLE</name>
33639                <description>DMA Enable
33640This bit enables the DMA functionality. If this bit is set to 1, a
33641DMA operation begins when the Host Driver writes to the
33642Command register. You can select one of the DMA modes by
33643using DMA Select in the Host Control 1 register.
33644Values:
33645- 0x1 (ENABLED): DMA Data transfer
33646- 0x0 (DISABLED): No data transfer or Non-DMA data
33647transfer</description>
33648                <bitRange>[0:0]</bitRange>
33649                <access>read-write</access>
33650              </field>
33651              <field>
33652                <name>BLOCK_COUNT_ENABLE</name>
33653                <description>Block Count Enable
33654This bit is used to enable the Block Count register, which is
33655relevant for multiple block transfers. If this bit is set to 0, the
33656Block Count register is disabled, which is useful in executing
33657an infinite transfer. The Host Driver must set this bit to 0
33658when ADMA is used.  When 16-bit Block Count register is used, the Host Driver can set this bit to 0 in ADMA2 mode to enable larger data transfer than the maximum of 65535 block counts supported by the 16-bit Block Count register.</description>
33659                <bitRange>[1:1]</bitRange>
33660                <access>read-write</access>
33661              </field>
33662              <field>
33663                <name>AUTO_CMD_ENABLE</name>
33664                <description>Auto Command Enable
33665This field determines use of Auto Command functions.
33666Note: In SDIO, this field must be set as 00b (Auto Command
33667Disabled).
33668Values:
33669- 0x0 (AUTO_CMD_DISABLED): Auto Command Disabled
33670- 0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable
33671- 0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable
33672- 0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Select</description>
33673                <bitRange>[3:2]</bitRange>
33674                <access>read-write</access>
33675              </field>
33676              <field>
33677                <name>DATA_XFER_DIR</name>
33678                <description>Data Transfer Direction Select
33679This bit defines the direction of DAT line data transfers. This
33680bit is set to 1 by the Host Driver to transfer data from the
33681SD/eMMC card to the Host Controller and it is set to 0 for all
33682other commands.
33683Values:
33684- 0x1 (READ): Read (Card to Host)
33685- 0x0 (WRITE): Write (Host to Card)</description>
33686                <bitRange>[4:4]</bitRange>
33687                <access>read-write</access>
33688              </field>
33689              <field>
33690                <name>MULTI_BLK_SEL</name>
33691                <description>Multi/Single Block Select
33692This bit is set when issuing multiple-block transfer
33693commands using the DAT line. If this bit is set to 0, it is not
33694necessary to set the Block Count register.</description>
33695                <bitRange>[5:5]</bitRange>
33696                <access>read-write</access>
33697              </field>
33698              <field>
33699                <name>RESP_TYPE</name>
33700                <description>Response Type R1/R5
33701This bit selects either R1 or R5 as a response type when the
33702Response Error Check is selected.
33703Error statuses checked in R1:
33704- OUT_OF_RANGE
33705- ADDRESS_ERROR
33706- BLOCK_LEN_ERROR
33707- WP_VIOLATION
33708- CARD_IS_LOCKED
33709- COM_CRC_ERROR
33710- CARD_ECC_FAILED
33711- CC_ERROR
33712- ERROR
33713Response Flags checked in R5:
33714- COM_CRC_ERROR
33715- ERROR
33716- FUNCTION_NUMBER
33717- OUT_OF_RANGE
33718Values:
33719- 0x0 (RESP_R1): R1 (Memory)
33720- 0x1 (RESP_R5): R5 (SDIO)</description>
33721                <bitRange>[6:6]</bitRange>
33722                <access>read-write</access>
33723              </field>
33724              <field>
33725                <name>RESP_ERR_CHK_ENABLE</name>
33726                <description>Response Error Check Enable
33727The Host Controller supports response check function to
33728avoid overhead of response error check by Host driver.
33729Response types of only R1 and R5 can be checked by the
33730Controller. If the Host Controller checks the response error,
33731set this bit to 1 and set Response Interrupt Disable to 1. If an
33732error is detected, the Response Error interrupt is generated
33733in the Error Interrupt Status register.
33734Note:
33735- Response error check must not be enabled for any
33736response type other than R1 and R5.
33737Values:
33738- 0x0 (DISABLED): Response Error Check is disabled
33739- 0x1 (ENABLED): Response Error Check is enabled</description>
33740                <bitRange>[7:7]</bitRange>
33741                <access>read-write</access>
33742              </field>
33743              <field>
33744                <name>RESP_INT_DISABLE</name>
33745                <description>Response Interrupt Disable
33746The Host Controller supports response check function to
33747avoid overhead of response error check by the Host driver.
33748Response types of only R1 and R5 can be checked by the
33749Controller.
33750If Host Driver checks the response error, set this bit to 0 and
33751wait for Command Complete Interrupt and then check the
33752response register.
33753If the Host Controller checks the response error, set this bit
33754to 1 and set the Response Error Check Enable bit to 1. The
33755Command Complete Interrupt is disabled by this bit
33756regardless of the Command Complete Signal Enable.
33757Values:
33758- 0x0 (ENABLED): Response Interrupt is enabled
33759- 0x1 (DISABLED): Response Interrupt is disabled</description>
33760                <bitRange>[8:8]</bitRange>
33761                <access>read-write</access>
33762              </field>
33763            </fields>
33764          </register>
33765          <register>
33766            <name>CMD_R</name>
33767            <description>Command register</description>
33768            <addressOffset>0xE</addressOffset>
33769            <size>16</size>
33770            <access>read-write</access>
33771            <resetValue>0x0</resetValue>
33772            <resetMask>0x3FFF</resetMask>
33773            <fields>
33774              <field>
33775                <name>RESP_TYPE_SELECT</name>
33776                <description>Response Type Select
33777This bit indicates the type of response expected from the
33778card.
33779Values:
33780- 0x0 (NO_RESP): No Response
33781- 0x1 (RESP_LEN_136): Response Length 136
33782- 0x2 (RESP_LEN_48): Response Length 48
33783- 0x3 (RESP_LEN_48B): Response Length 48; Check
33784Busy after response</description>
33785                <bitRange>[1:0]</bitRange>
33786                <access>read-write</access>
33787              </field>
33788              <field>
33789                <name>SUB_CMD_FLAG</name>
33790                <description>Sub Command Flag
33791This bit distinguishes between a main command and a sub
33792command.
33793Values:
33794- 0x0 (MAIN): Main Command
33795- 0x1 (SUB): Sub Command</description>
33796                <bitRange>[2:2]</bitRange>
33797                <access>read-write</access>
33798              </field>
33799              <field>
33800                <name>CMD_CRC_CHK_ENABLE</name>
33801                <description>Command CRC Check Enable
33802This bit enables the Host Controller to check the CRC field in
33803the response. If an error is detected, it is reported as a
33804Command CRC error.
33805Note:
33806- CRC Check enable must be set to 0 for the command
33807with no response, R3 response, and R4 response.
33808Values:
33809- 0x0 (DISABLED): Disable
33810- 0x1 (ENABLED): Enable</description>
33811                <bitRange>[3:3]</bitRange>
33812                <access>read-write</access>
33813              </field>
33814              <field>
33815                <name>CMD_IDX_CHK_ENABLE</name>
33816                <description>Command Index Check Enable
33817This bit enables the Host Controller to check the index field in
33818the response to verify if it has the same value as the
33819command index. If the value is not the same, it is reported as
33820a Command Index error.
33821Note:
33822- Index Check enable must be set to 0 for the command
33823with no response, R2 response, R3 response and R4
33824response.
33825Values:
33826- 0x0 (DISABLED): Disable
33827- 0x1 (ENABLED): Enable</description>
33828                <bitRange>[4:4]</bitRange>
33829                <access>read-write</access>
33830              </field>
33831              <field>
33832                <name>DATA_PRESENT_SEL</name>
33833                <description>Data Present Select
33834This bit is set to 1 to indicate that data is present and that the
33835data is transferred using the DAT line. This bit is set to 0 in
33836the following instances:
33837- Command using the CMD line
33838- Command with no data transfer but using busy signal on
33839the DAT[0] line
33840- Resume Command
33841Values:
33842- 0x0 (NO_DATA): No Data Present
33843- 0x1 (DATA): Data Present</description>
33844                <bitRange>[5:5]</bitRange>
33845                <access>read-write</access>
33846              </field>
33847              <field>
33848                <name>CMD_TYPE</name>
33849                <description>Command Type
33850These bits indicate the command type.
33851Note: While issuing Abort CMD using CMD12/CMD52 or
33852reset CMD using CMD0/CMD52, CMD_TYPE field shall be
33853set to 0x3.
33854Values:
33855- 0x3 (ABORT_CMD): Abort
33856- 0x2 (RESUME_CMD): Resume
33857- 0x1 (SUSPEND_CMD): Suspend
33858- 0x0 (NORMAL_CMD): Normal</description>
33859                <bitRange>[7:6]</bitRange>
33860                <access>read-write</access>
33861              </field>
33862              <field>
33863                <name>CMD_INDEX</name>
33864                <description>Command Index
33865These bits are set to the command number that is specified
33866in bits 45-40 of the Command Format.</description>
33867                <bitRange>[13:8]</bitRange>
33868                <access>read-write</access>
33869              </field>
33870            </fields>
33871          </register>
33872          <register>
33873            <name>RESP01_R</name>
33874            <description>Response Register 0/1</description>
33875            <addressOffset>0x10</addressOffset>
33876            <size>32</size>
33877            <access>read-only</access>
33878            <resetValue>0x0</resetValue>
33879            <resetMask>0xFFFFFFFF</resetMask>
33880            <fields>
33881              <field>
33882                <name>RESP01</name>
33883                <description>Command Response
33884These bits reflect 39-8 bits of SD/eMMC Response Field.
33885Note: For Auto CMD, the 32-bit response (bits 39-8 of the
33886Response Field) is updated in the RESP67_R register.</description>
33887                <bitRange>[31:0]</bitRange>
33888                <access>read-only</access>
33889              </field>
33890            </fields>
33891          </register>
33892          <register>
33893            <name>RESP23_R</name>
33894            <description>Response Register 2/3</description>
33895            <addressOffset>0x14</addressOffset>
33896            <size>32</size>
33897            <access>read-only</access>
33898            <resetValue>0x0</resetValue>
33899            <resetMask>0xFFFFFFFF</resetMask>
33900            <fields>
33901              <field>
33902                <name>RESP23</name>
33903                <description>Command Response
33904These bits reflect 71-40 bits of the SD/eMMC Response</description>
33905                <bitRange>[31:0]</bitRange>
33906                <access>read-only</access>
33907              </field>
33908            </fields>
33909          </register>
33910          <register>
33911            <name>RESP45_R</name>
33912            <description>Response Register 4/5</description>
33913            <addressOffset>0x18</addressOffset>
33914            <size>32</size>
33915            <access>read-only</access>
33916            <resetValue>0x0</resetValue>
33917            <resetMask>0xFFFFFFFF</resetMask>
33918            <fields>
33919              <field>
33920                <name>RESP45</name>
33921                <description>Command Response
33922These bits reflect 103-72 bits of the Response Field.</description>
33923                <bitRange>[31:0]</bitRange>
33924                <access>read-only</access>
33925              </field>
33926            </fields>
33927          </register>
33928          <register>
33929            <name>RESP67_R</name>
33930            <description>Response Register 6/7</description>
33931            <addressOffset>0x1C</addressOffset>
33932            <size>32</size>
33933            <access>read-only</access>
33934            <resetValue>0x0</resetValue>
33935            <resetMask>0xFFFFFFFF</resetMask>
33936            <fields>
33937              <field>
33938                <name>RESP67</name>
33939                <description>Command Response
33940These bits reflect bits 135-104 of SD/EMMC Response
33941Field.
33942Note: For Auto CMD, this register also reflects the 32-bit
33943response (bits 39-8 of the Response Field).</description>
33944                <bitRange>[31:0]</bitRange>
33945                <access>read-only</access>
33946              </field>
33947            </fields>
33948          </register>
33949          <register>
33950            <name>BUF_DATA_R</name>
33951            <description>Buffer Data Port Register</description>
33952            <addressOffset>0x20</addressOffset>
33953            <size>32</size>
33954            <access>read-write</access>
33955            <resetValue>0x0</resetValue>
33956            <resetMask>0xFFFFFFFF</resetMask>
33957            <fields>
33958              <field>
33959                <name>BUF_DATA</name>
33960                <description>Buffer Data
33961These bits enable access to the Host Controller packet
33962buffer.</description>
33963                <bitRange>[31:0]</bitRange>
33964                <access>read-write</access>
33965              </field>
33966            </fields>
33967          </register>
33968          <register>
33969            <name>PSTATE_REG</name>
33970            <description>Present State Register</description>
33971            <addressOffset>0x24</addressOffset>
33972            <size>32</size>
33973            <access>read-only</access>
33974            <resetValue>0x0</resetValue>
33975            <resetMask>0x1BFF0FF7</resetMask>
33976            <fields>
33977              <field>
33978                <name>CMD_INHIBIT</name>
33979                <description>Command Inhibit (CMD)
33980This bit indicates the following :
33981- SD/eMMC mode: If this bit is set to 0, it indicates that the
33982CMD line is not in use and the Host controller can issue
33983an SD/eMMC command using the CMD line. This bit is
33984set when the command register is written. This bit is
33985cleared when the command response is received. This bit
33986is not cleared by the response of auto CMD12/23 but
33987cleared by the response of read/write command.
33988Values:
33989- 0x0 (READY): Host Controller is ready to issue a
33990command
33991- 0x1 (NOT_READY): Host Controller is not ready to issue
33992a command</description>
33993                <bitRange>[0:0]</bitRange>
33994                <access>read-only</access>
33995              </field>
33996              <field>
33997                <name>CMD_INHIBIT_DAT</name>
33998                <description>Command Inhibit (DAT)
33999This bit is applicable for SD/eMMC mode and is generated if
34000either DAT line active or Read transfer active is set to 1. If
34001this bit is set to 0, it indicates that the Host Controller can
34002issue subsequent SD/eMMC commands.
34003Values:
34004- 0x0 (READY): Can issue command which used DAT line
34005- 0x1 (NOT_READY): Cannot issue command which used
34006DAT line</description>
34007                <bitRange>[1:1]</bitRange>
34008                <access>read-only</access>
34009              </field>
34010              <field>
34011                <name>DAT_LINE_ACTIVE</name>
34012                <description>DAT Line Active (SD/eMMC Mode only)
34013This bit indicates whether one of the DAT lines on the
34014SD/eMMC bus is in use.
34015In the case of read transactions, this bit indicates whether a
34016read transfer is executing on the SD/eMMC bus.
34017In the case of write transactions, this bit indicates whether a
34018write transfer is executing on the SD/eMMC bus.
34019For a command with busy, this status indicates whether the
34020command executing busy is executing on an SD or eMMC
34021bus.
34022Values:
34023- 0x0 (INACTIVE): DAT Line Inactive
34024- 0x1 (ACTIVE): DAT Line Active</description>
34025                <bitRange>[2:2]</bitRange>
34026                <access>read-only</access>
34027              </field>
34028              <field>
34029                <name>DAT_7_4</name>
34030                <description>DAT[7:4] Line Signal Level
34031This bit is used to check the DAT line level to recover from
34032errors and for debugging. These bits reflect the value of the
34033sd_dat_in (upper nibble) signal.</description>
34034                <bitRange>[7:4]</bitRange>
34035                <access>read-only</access>
34036              </field>
34037              <field>
34038                <name>WR_XFER_ACTIVE</name>
34039                <description>Write Transfer Active
34040This status indicates whether a write transfer is active for
34041SD/eMMC mode.
34042Values:
34043- 0x0 (INACTIVE): No valid data
34044- 0x1 (ACTIVE): Transferring data</description>
34045                <bitRange>[8:8]</bitRange>
34046                <access>read-only</access>
34047              </field>
34048              <field>
34049                <name>RD_XFER_ACTIVE</name>
34050                <description>Read Transfer Active
34051This bit indicates whether a read transfer is active for
34052SD/eMMC mode.
34053Values:
34054- 0x0 (INACTIVE): No valid data
34055- 0x1 (ACTIVE): Transferring data</description>
34056                <bitRange>[9:9]</bitRange>
34057                <access>read-only</access>
34058              </field>
34059              <field>
34060                <name>BUF_WR_ENABLE</name>
34061                <description>Buffer Write Enable
34062This bit is used for non-DMA transfers. This bit is set if space
34063is available for writing data.
34064Values:
34065- 0x0 (DISABLED): Write disable
34066- 0x1 (ENABLED): Write enable</description>
34067                <bitRange>[10:10]</bitRange>
34068                <access>read-only</access>
34069              </field>
34070              <field>
34071                <name>BUF_RD_ENABLE</name>
34072                <description>Buffer Read Enable
34073This bit is used for non-DMA transfers. This bit is set if valid
34074data exists in the Host buffer.
34075Values:
34076- 0x0 (DISABLED): Read disable
34077- 0x1 (ENABLED): Read enable</description>
34078                <bitRange>[11:11]</bitRange>
34079                <access>read-only</access>
34080              </field>
34081              <field>
34082                <name>CARD_INSERTED</name>
34083                <description>Card Inserted
34084This bit indicates whether a card has been inserted. The
34085Host Controller debounces this signal so that Host Driver
34086need not wait for it to stabilize.
34087Values:
34088- 0x0 (FALSE): Reset, Debouncing, or No card
34089- 0x1 (TRUE): Card Inserted</description>
34090                <bitRange>[16:16]</bitRange>
34091                <access>read-only</access>
34092              </field>
34093              <field>
34094                <name>CARD_STABLE</name>
34095                <description>Card Stable
34096This bit indicates the stability of the Card Detect Pin Level. A
34097card is not detected if this bit is set to 1 and the value of the
34098CARD_INSERTED bit is 0.
34099Values:
34100- 0x0 (FALSE): Reset or Debouncing
34101- 0x1 (TRUE): No Card or Inserted</description>
34102                <bitRange>[17:17]</bitRange>
34103                <access>read-only</access>
34104              </field>
34105              <field>
34106                <name>CARD_DETECT_PIN_LEVEL</name>
34107                <description>Card Detect Pin Level
34108This bit reflects the inverse synchronized value of the
34109card_detect_n signal.
34110Values:
34111- 0x0 (FALSE): No card present
34112- 0x1 (TRUE): Card Present</description>
34113                <bitRange>[18:18]</bitRange>
34114                <access>read-only</access>
34115              </field>
34116              <field>
34117                <name>WR_PROTECT_SW_LVL</name>
34118                <description>Write Protect Switch Pin Level
34119This bit is supported only for memory and combo cards. This
34120bit reflects the synchronized value of the card_write_prot
34121signal.
34122Values:
34123- 0x0 (FALSE): Write protected
34124- 0x1 (TRUE): Write enabled</description>
34125                <bitRange>[19:19]</bitRange>
34126                <access>read-only</access>
34127              </field>
34128              <field>
34129                <name>DAT_3_0</name>
34130                <description>DAT[3:0] Line Signal Level
34131This bit is used to check the DAT line level to recover from
34132errors and for debugging. These bits reflect the value of the
34133sd_dat_in (lower nibble) signal.</description>
34134                <bitRange>[23:20]</bitRange>
34135                <access>read-only</access>
34136              </field>
34137              <field>
34138                <name>CMD_LINE_LVL</name>
34139                <description>Command-Line Signal Level
34140This bit is used to check the CMD line level to recover from
34141errors and for debugging. These bits reflect the value of the
34142sd_cmd_in signal.</description>
34143                <bitRange>[24:24]</bitRange>
34144                <access>read-only</access>
34145              </field>
34146              <field>
34147                <name>HOST_REG_VOL</name>
34148                <description>Host Regulator Voltage Stable
34149This bit is used to check whether the host regulator voltage is
34150stable for switching the voltage of UHS-I mode. This bit
34151reflects the synchronized value of the host_reg_vol_stable
34152signal.
34153Values:
34154- 0x0 (FALSE): Host Regulator Voltage is not stable
34155- 0x1 (TRUE): Host Regulator Voltage is stable</description>
34156                <bitRange>[25:25]</bitRange>
34157                <access>read-only</access>
34158              </field>
34159              <field>
34160                <name>CMD_ISSU_ERR</name>
34161                <description>Command Not Issued by Error
34162This bit is set if a command cannot be issued after setting
34163the command register due to an error except the Auto
34164CMD12 error.
34165Values:
34166- 0x0 (FALSE): No error for issuing a command
34167- 0x1 (TRUE): Command cannot be issued</description>
34168                <bitRange>[27:27]</bitRange>
34169                <access>read-only</access>
34170              </field>
34171              <field>
34172                <name>SUB_CMD_STAT</name>
34173                <description>Sub Command Status
34174This bit is used to distinguish between a main command and
34175a sub command status.
34176Values:
34177- 0x0 (FALSE): Main Command Status
34178- 0x1 (TRUE): Sub Command Status</description>
34179                <bitRange>[28:28]</bitRange>
34180                <access>read-only</access>
34181              </field>
34182            </fields>
34183          </register>
34184          <register>
34185            <name>HOST_CTRL1_R</name>
34186            <description>Host Control 1 Register</description>
34187            <addressOffset>0x28</addressOffset>
34188            <size>8</size>
34189            <access>read-write</access>
34190            <resetValue>0x0</resetValue>
34191            <resetMask>0xFF</resetMask>
34192            <fields>
34193              <field>
34194                <name>LED_CTRL</name>
34195                <description>LED Control
34196This bit is used to caution the user not to remove the card
34197while the SD card is being accessed. The value is reflected
34198on the led_ctrl ouput.
34199Values:
34200- 0x0 (OFF): LED off
34201- 0x1 (ON): LED on</description>
34202                <bitRange>[0:0]</bitRange>
34203                <access>read-write</access>
34204              </field>
34205              <field>
34206                <name>DAT_XFER_WIDTH</name>
34207                <description>Data Transfer Width
34208For SD/eMMC mode,this bit selects the data transfer width of
34209the Host Controller. The Host Driver sets it to match the data
34210width of the SD/eMMC card.
34211Values:
34212- 0x1 (FOUR_BIT): 4-bit mode
34213- 0x0 (ONE_BIT): 1-bit mode</description>
34214                <bitRange>[1:1]</bitRange>
34215                <access>read-write</access>
34216              </field>
34217              <field>
34218                <name>HIGH_SPEED_EN</name>
34219                <description>High Speed Enable (SD/eMMC Mode only)
34220Before setting this bit, the Host Driver checks the High Speed
34221Support in the Capabilities register.
34222Note: SDHC always outputs the sd_cmd_out and
34223sd_dat_out lines at the rising edge of card clock
34224irrespective of this bit.
34225Values:
34226- 0x1 (HIGH_SPEED): High Speed mode
34227- 0x0 (NORMAL_SPEED): Normal Speed mode</description>
34228                <bitRange>[2:2]</bitRange>
34229                <access>read-write</access>
34230              </field>
34231              <field>
34232                <name>DMA_SEL</name>
34233                <description>N/A</description>
34234                <bitRange>[4:3]</bitRange>
34235                <access>read-write</access>
34236              </field>
34237              <field>
34238                <name>EXT_DAT_XFER</name>
34239                <description>Extended Data Transfer Width
34240This bit controls 8-bit bus width mode of embedded device.
34241Values:
34242- 0x1 (EIGHT_BIT): 8-bit Bus Width
34243- 0x0 (DEFAULT): Bus Width is selected by the Data
34244Transfer Width</description>
34245                <bitRange>[5:5]</bitRange>
34246                <access>read-write</access>
34247              </field>
34248              <field>
34249                <name>CARD_DETECT_TEST_LVL</name>
34250                <description>Card Detect Test Level
34251This bit is enabled while the Card Detect Signal Selection is
34252set to 1 and it indicates whether a card inserted or not.
34253Values:
34254- 0x1 (CARD_INSERTED): Card Inserted
34255- 0x0 (No_CARD): No Card</description>
34256                <bitRange>[6:6]</bitRange>
34257                <access>read-write</access>
34258              </field>
34259              <field>
34260                <name>CARD_DETECT_SIG_SEL</name>
34261                <description>Card Detect Signal Selection
34262This bit selects a source for card detection. When the source
34263for the card detection is switched, the interrupt must be
34264disabled during the switching period.
34265Values:
34266- 0x1 (CARD_DT_TEST_LEVEL): Card Detect Test Level
34267is selected (for test purpose)
34268- 0x0 (card_detect_n): card_detect_n signal is
34269selected (for normal use)</description>
34270                <bitRange>[7:7]</bitRange>
34271                <access>read-write</access>
34272              </field>
34273            </fields>
34274          </register>
34275          <register>
34276            <name>PWR_CTRL_R</name>
34277            <description>Power Control Register</description>
34278            <addressOffset>0x29</addressOffset>
34279            <size>8</size>
34280            <access>read-write</access>
34281            <resetValue>0x0</resetValue>
34282            <resetMask>0xF</resetMask>
34283            <fields>
34284              <field>
34285                <name>SD_BUS_PWR_VDD1</name>
34286                <description>SD Bus Power for VDD1
34287This bit enables VDD1 power of the card. This setting is
34288available on the card_if_pwr_en output so that it
34289can be used to control the VDD1 power supply of the card.
34290Before setting this bit, the SD Host Driver sets the SD Bus
34291Voltage Select bit. If the Host Controller detects a No Card
34292state, this bit is cleared.
34293In SD mode, if this bit is cleared, the Host Controller stops
34294the SD Clock by clearing the SD_CLK_IN bit in the
34295CLK_CTRL_R register.
34296Values:
34297- 0x0 (OFF): Power off
34298- 0x1 (ON): Power on</description>
34299                <bitRange>[0:0]</bitRange>
34300                <access>read-write</access>
34301              </field>
34302              <field>
34303                <name>SD_BUS_VOL_VDD1</name>
34304                <description>These bits are NON-operational (they can be written and read but they have no effect).  In a generic HCI host these would select the card supply voltage.  But, for the applications targeted for this block it is assumed that the card supply voltage is always fixed at the board level.  If for some reason there is a variable power supply then that can be managed through normal GPIO programming separately.</description>
34305                <bitRange>[3:1]</bitRange>
34306                <access>read-write</access>
34307              </field>
34308            </fields>
34309          </register>
34310          <register>
34311            <name>BGAP_CTRL_R</name>
34312            <description>Block Gap Control Register</description>
34313            <addressOffset>0x2A</addressOffset>
34314            <size>8</size>
34315            <access>read-write</access>
34316            <resetValue>0x0</resetValue>
34317            <resetMask>0xF</resetMask>
34318            <fields>
34319              <field>
34320                <name>STOP_BG_REQ</name>
34321                <description>Stop At Block Gap Request
34322This bit is used to stop executing read and write transactions
34323at the next block gap for non-DMA, SDMA, and ADMA
34324transfers.
34325Values:
34326- 0x0 (XFER): Transfer
34327- 0x1 (STOP): Stop</description>
34328                <bitRange>[0:0]</bitRange>
34329                <access>read-write</access>
34330              </field>
34331              <field>
34332                <name>CONTINUE_REQ</name>
34333                <description>Continue Request
34334This bit is used to restart the transaction, which was stopped
34335using the Stop At Block Gap Request. The Host Controller
34336automatically clears this bit when the transaction restarts. If
34337stop at block gap request is set to 1, any write to this bit is
34338ignored.
34339Values:
34340- 0x0 (NO_AFFECT): No Affect
34341- 0x1 (RESTART): Restart</description>
34342                <bitRange>[1:1]</bitRange>
34343                <access>read-write</access>
34344              </field>
34345              <field>
34346                <name>RD_WAIT_CTRL</name>
34347                <description>N/A</description>
34348                <bitRange>[2:2]</bitRange>
34349                <access>read-write</access>
34350              </field>
34351              <field>
34352                <name>INT_AT_BGAP</name>
34353                <description>Interrupt At Block Gap
34354This bit is valid only in the 4-bit mode of an SDIO card and is
34355used to select a sample point in the interrupt cycle. Setting to
343561 enables interrupt detection at the block gap for a multiple
34357block transfer.
34358Values:
34359- 0x0 (DISABLE): Disabled
34360- 0x1 (ENABLE): Enabled</description>
34361                <bitRange>[3:3]</bitRange>
34362                <access>read-write</access>
34363              </field>
34364            </fields>
34365          </register>
34366          <register>
34367            <name>WUP_CTRL_R</name>
34368            <description>Wakeup Control Register</description>
34369            <addressOffset>0x2B</addressOffset>
34370            <size>8</size>
34371            <access>read-write</access>
34372            <resetValue>0x0</resetValue>
34373            <resetMask>0x7</resetMask>
34374            <fields>
34375              <field>
34376                <name>WUP_CARD_INT</name>
34377                <description>Wakeup Event Enable on SDIO Card Interrupt (through DAT[1]).
34378This bit enables wakeup event through an SDIO Card Interrupt
34379assertion in the Normal Interrupt Status register. This bit can
34380be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1.
34381Values:
34382- 0x0 (DISABLED): Disable
34383- 0x1 (ENABLED): Enable</description>
34384                <bitRange>[0:0]</bitRange>
34385                <access>read-write</access>
34386              </field>
34387              <field>
34388                <name>WUP_CARD_INSERT</name>
34389                <description>Wakeup Event Enable on SD Card Insertion
34390This bit enables wakeup event through Card Insertion
34391assertion in the Normal Interrupt Status register. FN_WUS
34392(Wake Up Support) in CIS does not affect this bit.
34393Values:
34394- 0x0 (DISABLED): Disable
34395- 0x1 (ENABLED): Enable</description>
34396                <bitRange>[1:1]</bitRange>
34397                <access>read-write</access>
34398              </field>
34399              <field>
34400                <name>WUP_CARD_REMOVAL</name>
34401                <description>Wakeup Event Enable on SD Card Removal
34402This bit enables wakeup event through Card Removal
34403assertion in the Normal Interrupt Status register. For the
34404SDIO card, Wake Up Support (FN_WUS) in the Card
34405Information Structure (CIS) register does not affect this bit.
34406Values:
34407- 0x0 (DISABLED): Disable
34408- 0x1 (ENABLED): Enable</description>
34409                <bitRange>[2:2]</bitRange>
34410                <access>read-write</access>
34411              </field>
34412            </fields>
34413          </register>
34414          <register>
34415            <name>CLK_CTRL_R</name>
34416            <description>Clock Control Register</description>
34417            <addressOffset>0x2C</addressOffset>
34418            <size>16</size>
34419            <access>read-write</access>
34420            <resetValue>0x0</resetValue>
34421            <resetMask>0xFFEF</resetMask>
34422            <fields>
34423              <field>
34424                <name>INTERNAL_CLK_EN</name>
34425                <description>Internal Clock Enable
34426This bit is set to 0 when the Host Driver is not using the Host
34427Controller or the Host Controller awaits a wakeup interrupt.
34428The Host Controller must stop its internal clock to enter a
34429very low power state. Certain registers are not accessible when this bit is off.  So, to be safe turn it on for any register access.
34430Values:
34431- 0x0 (FALSE): Stop
34432- 0x1 (TRUE): Oscillate</description>
34433                <bitRange>[0:0]</bitRange>
34434                <access>read-write</access>
34435              </field>
34436              <field>
34437                <name>INTERNAL_CLK_STABLE</name>
34438                <description>Internal Clock Stable
34439This bit enables the Host Driver to check the clock stability
34440twice after the Internal Clock Enable bit is set and after the
34441PLL Enable bit is set. This bit reflects the synchronized
34442value of the Internal Clock Stable signal after the Internal Clock
34443Enable bit is set to 1 and also reflects the synchronized
34444value of the Card Clock Stable signal after the PLL Enable bit is
34445set to 1.
34446Values:
34447- 0x0 (FALSE): Not Ready
34448- 0x1 (TRUE): Ready</description>
34449                <bitRange>[1:1]</bitRange>
34450                <access>read-only</access>
34451              </field>
34452              <field>
34453                <name>SD_CLK_EN</name>
34454                <description>SD/eMMC Clock Enable
34455This bit stops the clk_card output when set to 0. The
34456SDCLK Frequency Select bit can be changed when
34457this bit is set to 0.
34458Values:
34459- 0x0 (FALSE): Disable providing clk_card
34460- 0x1 (TRUE): Enable providing clk_card</description>
34461                <bitRange>[2:2]</bitRange>
34462                <access>read-write</access>
34463              </field>
34464              <field>
34465                <name>PLL_ENABLE</name>
34466                <description>PLL Enable
34467This bit is used to activate the PLL (applicable when Host
34468Version 4 Enable = 1).
34469Values:
34470- 0x0 (FALSE): PLL is in low power mode
34471- 0x1 (TRUE): PLL is enabled</description>
34472                <bitRange>[3:3]</bitRange>
34473                <access>read-write</access>
34474              </field>
34475              <field>
34476                <name>CLK_GEN_SELECT</name>
34477                <description>Clock Generator Select
34478This bit is used to select the clock generator mode in
34479SDCLK Frequency Select.
34480Values:
34481- 0x0 (FALSE): Divided Clock Mode
34482- 0x1 (TRUE): Programmable Clock Mode</description>
34483                <bitRange>[5:5]</bitRange>
34484                <access>read-write</access>
34485              </field>
34486              <field>
34487                <name>UPPER_FREQ_SEL</name>
34488                <description>These bits specify the upper 2 bits of 10-bit SDCLK
34489Frequency Select control.</description>
34490                <bitRange>[7:6]</bitRange>
34491                <access>read-write</access>
34492              </field>
34493              <field>
34494                <name>FREQ_SEL</name>
34495                <description>SDCLK Frequency Select
34496These bits are used to select the frequency of the SDCLK
34497signal.
3449810-bit Divided Clock Mode:
34499- 0x3FF - 1/2046 Divided clock
34500- ..........
34501- N - 1/2N Divided Clock
34502- ..........
34503- 0x002 - 1/4 Divided Clock
34504- 0x001 - 1/2 Divided Clock
34505- 0x000 - Base clock (10MHz - 255 MHz)</description>
34506                <bitRange>[15:8]</bitRange>
34507                <access>read-write</access>
34508              </field>
34509            </fields>
34510          </register>
34511          <register>
34512            <name>TOUT_CTRL_R</name>
34513            <description>Timeout Control Register</description>
34514            <addressOffset>0x2E</addressOffset>
34515            <size>8</size>
34516            <access>read-write</access>
34517            <resetValue>0x0</resetValue>
34518            <resetMask>0xF</resetMask>
34519            <fields>
34520              <field>
34521                <name>TOUT_CNT</name>
34522                <description>N/A</description>
34523                <bitRange>[3:0]</bitRange>
34524                <access>read-write</access>
34525              </field>
34526            </fields>
34527          </register>
34528          <register>
34529            <name>SW_RST_R</name>
34530            <description>Software Reset Register</description>
34531            <addressOffset>0x2F</addressOffset>
34532            <size>8</size>
34533            <access>read-write</access>
34534            <resetValue>0x0</resetValue>
34535            <resetMask>0x7</resetMask>
34536            <fields>
34537              <field>
34538                <name>SW_RST_ALL</name>
34539                <description>Software Reset For All
34540This reset affects the entire Host Controller except for the
34541card detection circuit. During its initialization, the Host Driver
34542sets this bit to 1 to reset the Host Controller. All registers are
34543reset except the capabilities register. If this bit is set to 1, the
34544Host Driver must issue reset command and reinitialize the
34545card.
34546Values:
34547- 0x0 (FALSE): Work
34548- 0x1 (TRUE): Reset</description>
34549                <bitRange>[0:0]</bitRange>
34550                <access>read-write</access>
34551              </field>
34552              <field>
34553                <name>SW_RST_CMD</name>
34554                <description>Software Reset For CMD line
34555This bit resets only a part of the command circuit to be able
34556to issue a command. This reset is effective only for a command
34557issuing circuit (including response error statuses related to
34558Command Inhibit (CMD) control) and does not affect the
34559data transfer circuit. Host Controller can continue data
34560transfer even after this reset is executed while handling
34561subcommand-response errors.
34562The following registers and bits are cleared by this bit:
34563- Present State register - Command Inhibit (CMD) bit
34564- Normal Interrupt Status register - Command Complete bit
34565- Error Interrupt Status - Response error statuses related
34566to Command Inhibit (CMD) bit
34567Values:
34568- 0x0 (FALSE): Work
34569- 0x1 (TRUE): Reset</description>
34570                <bitRange>[1:1]</bitRange>
34571                <access>read-write</access>
34572              </field>
34573              <field>
34574                <name>SW_RST_DAT</name>
34575                <description>Software Reset For DAT line
34576This bit is used in SD/eMMC mode and it resets only a part
34577of the data circuit and the DMA circuit is also reset.
34578The following registers and bits are cleared by this bit:
34579- Buffer Data Port register
34580- Buffer is cleared and initialized.
34581- Present state register
34582- Buffer Read Enable
34583- Buffer Write Enable
34584- Read Transfer Active
34585- Write Transfer Active
34586- DAT Line Active
34587- Command Inhibit (DAT)
34588- Block Gap Control register
34589- Continue Request
34590- Stop At Block Gap Request
34591- Normal Interrupt status register
34592- Buffer Read Ready
34593- Buffer Write Ready
34594- DMA Interrupt
34595- Block Gap Event
34596- Transfer Complete
34597Values:
34598- 0x0 (FALSE): Work
34599- 0x1 (TRUE): Reset</description>
34600                <bitRange>[2:2]</bitRange>
34601                <access>read-write</access>
34602              </field>
34603            </fields>
34604          </register>
34605          <register>
34606            <name>NORMAL_INT_STAT_R</name>
34607            <description>Normal Interrupt Status Register</description>
34608            <addressOffset>0x30</addressOffset>
34609            <size>16</size>
34610            <access>read-write</access>
34611            <resetValue>0x0</resetValue>
34612            <resetMask>0xE1FF</resetMask>
34613            <fields>
34614              <field>
34615                <name>CMD_COMPLETE</name>
34616                <description>Command Complete
34617In an SD/eMMC Mode, this bit is set when the end bit of a
34618response except for Auto CMD12 and Auto CMD23.
34619This interrupt is not generated when the Response Interrupt
34620Disable in Transfer Mode Register is set to 1.
34621Values:
34622- 0x0 (FALSE): No command complete
34623- 0x1 (TRUE): Command Complete</description>
34624                <bitRange>[0:0]</bitRange>
34625                <access>read-write</access>
34626              </field>
34627              <field>
34628                <name>XFER_COMPLETE</name>
34629                <description>Transfer Complete
34630This bit is set when a read/write transfer and a command
34631with status busy is completed.
34632Values:
34633- 0x0 (FALSE): Not complete
34634- 0x1 (TRUE): Command execution is completed</description>
34635                <bitRange>[1:1]</bitRange>
34636                <access>read-write</access>
34637              </field>
34638              <field>
34639                <name>BGAP_EVENT</name>
34640                <description>Block Gap Event
34641This bit is set when both read/write transaction is stopped at
34642block gap due to a Stop at Block Gap Request.
34643Values:
34644- 0x0 (FALSE): No Block Gap Event
34645- 0x1 (TRUE): Transaction stopped at block gap</description>
34646                <bitRange>[2:2]</bitRange>
34647                <access>read-write</access>
34648              </field>
34649              <field>
34650                <name>DMA_INTERRUPT</name>
34651                <description>DMA Interrupt
34652This bit is set if the Host Controller detects the SDMA Buffer
34653Boundary during transfer. In case of ADMA, by setting the Int
34654field in the descriptor table, the Host controller generates this
34655interrupt. This interrupt is not generated after a Transfer
34656Complete.
34657Values:
34658- 0x0 (FALSE): No DMA Interrupt
34659- 0x1 (TRUE): DMA Interrupt is generated</description>
34660                <bitRange>[3:3]</bitRange>
34661                <access>read-write</access>
34662              </field>
34663              <field>
34664                <name>BUF_WR_READY</name>
34665                <description>Buffer Write Ready
34666This bit is set if the Buffer Write Enable changes from 0 to 1.
34667Values:
34668- 0x0 (FALSE): Not ready to write buffer
34669- 0x1 (TRUE): Ready to write buffer</description>
34670                <bitRange>[4:4]</bitRange>
34671                <access>read-write</access>
34672              </field>
34673              <field>
34674                <name>BUF_RD_READY</name>
34675                <description>Buffer Read Ready
34676This bit is set if the Buffer Read Enable changes from 0 to 1.
34677Values:
34678- 0x0 (FALSE): Not ready to read buffer
34679- 0x1 (TRUE): Ready to read buffer</description>
34680                <bitRange>[5:5]</bitRange>
34681                <access>read-write</access>
34682              </field>
34683              <field>
34684                <name>CARD_INSERTION</name>
34685                <description>Card Insertion
34686This bit is set if the Card Inserted in the Present State
34687register changes from 0 to 1.
34688Values:
34689- 0x0 (FALSE): Card state stable or Debouncing
34690- 0x1 (TRUE): Card Inserted</description>
34691                <bitRange>[6:6]</bitRange>
34692                <access>read-write</access>
34693              </field>
34694              <field>
34695                <name>CARD_REMOVAL</name>
34696                <description>Card Removal
34697This bit is set if the Card Inserted in the Present State
34698register changes from 1 to 0.
34699Values:
34700- 0x0 (FALSE): Card state stable or Debouncing
34701- 0x1 (TRUE): Card Removed</description>
34702                <bitRange>[7:7]</bitRange>
34703                <access>read-write</access>
34704              </field>
34705              <field>
34706                <name>CARD_INTERRUPT</name>
34707                <description>Card Interrupt
34708This bit reflects the synchronized value of:
34709- DAT[1] Interrupt Input for SD Mode
34710Values:
34711- 0x0 (FALSE): No Card Interrupt
34712- 0x1 (TRUE): Generate Card Interrupt</description>
34713                <bitRange>[8:8]</bitRange>
34714                <access>read-only</access>
34715              </field>
34716              <field>
34717                <name>FX_EVENT</name>
34718                <description>FX Event
34719This status is set when R[14] of response register is set to 1
34720and Response Type R1/R5 is set to 0 in Transfer Mode
34721register. This interrupt is used with response check function.
34722Values:
34723- 0x0 (FALSE): No Event
34724- 0x1 (TRUE): FX Event is detected</description>
34725                <bitRange>[13:13]</bitRange>
34726                <access>read-only</access>
34727              </field>
34728              <field>
34729                <name>CQE_EVENT</name>
34730                <description>Command Queuing Event
34731This status is set if Command Queuing/Crypto related event
34732has occurred in eMMC/SD mode. Read CQHCI's
34733CQIS/CRNQIS register for more details. In UHS-II Mode,
34734this bit is irrelevant.
34735Values:
34736- 0x0 (FALSE): No Event
34737- 0x1 (TRUE): Command Queuing Event is detected</description>
34738                <bitRange>[14:14]</bitRange>
34739                <access>read-write</access>
34740              </field>
34741              <field>
34742                <name>ERR_INTERRUPT</name>
34743                <description>Error Interrupt
34744If any of the bits in the Error Interrupt Status register are set,
34745then this bit is set.
34746Values:
34747- 0x0 (FALSE): No Error
34748- 0x1 (TRUE): Error</description>
34749                <bitRange>[15:15]</bitRange>
34750                <access>read-only</access>
34751              </field>
34752            </fields>
34753          </register>
34754          <register>
34755            <name>ERROR_INT_STAT_R</name>
34756            <description>Error Interrupt Status Register</description>
34757            <addressOffset>0x32</addressOffset>
34758            <size>16</size>
34759            <access>read-write</access>
34760            <resetValue>0x0</resetValue>
34761            <resetMask>0x1FFF</resetMask>
34762            <fields>
34763              <field>
34764                <name>CMD_TOUT_ERR</name>
34765                <description>Command Timeout Error
34766In SD/eMMC Mode,this bit is set only if no response is
34767returned within 64 SD clock cycles from the end bit of the
34768command. If the Host Controller detects a CMD line conflict,
34769along with Command CRC Error bit, this bit is set to 1,
34770without waiting for 64 SD/eMMC card clock cycles.
34771Values:
34772- 0x0 (FALSE): No error
34773- 0x1 (TRUE): Time out</description>
34774                <bitRange>[0:0]</bitRange>
34775                <access>read-write</access>
34776              </field>
34777              <field>
34778                <name>CMD_CRC_ERR</name>
34779                <description>Command CRC Error
34780Command CRC Error is generated in SD/eMMC mode for
34781following two cases.
34782- If a response is returned and the Command Timeout
34783Error is set to 0 (indicating no timeout), this bit is set to 1
34784when detecting a CRC error in the command response.
34785- The Host Controller detects a CMD line conflict by
34786monitoring the CMD line when a command is issued. If
34787the Host Controller drives the CMD line to 1 level, but
34788detects 0 level on the CMD line at the next SD clock
34789edge, then the Host Controller aborts the command (stop
34790driving CMD line) and set this bit to 1. The Command
34791Timeout Error is also set to 1 to distinguish a CMD line
34792conflict.
34793Values:
34794- 0x0 (FALSE): No error
34795- 0x1 (TRUE): CRC error generated</description>
34796                <bitRange>[1:1]</bitRange>
34797                <access>read-write</access>
34798              </field>
34799              <field>
34800                <name>CMD_END_BIT_ERR</name>
34801                <description>Command End Bit Error
34802This bit is set when detecting that the end bit of a command
34803response is 0 in SD/eMMC mode.
34804Values:
34805- 0x0 (FALSE): No error
34806- 0x1 (TRUE): End Bit error generated</description>
34807                <bitRange>[2:2]</bitRange>
34808                <access>read-write</access>
34809              </field>
34810              <field>
34811                <name>CMD_IDX_ERR</name>
34812                <description>Command Index Error
34813This bit is set if a Command Index error occurs in the
34814command respons in SD/eMMC mode.
34815Values:
34816- 0x0 (FALSE): No error
34817- 0x1 (TRUE): Error</description>
34818                <bitRange>[3:3]</bitRange>
34819                <access>read-write</access>
34820              </field>
34821              <field>
34822                <name>DATA_TOUT_ERR</name>
34823                <description>Data Timeout Error
34824This bit is set in SD/eMMC mode when detecting one of the
34825following timeout conditions:
34826- Busy timeout for R1b, R5b type
34827- Busy timeout after Write CRC status
34828- Write CRC Status timeout
34829- Read Data timeout
34830Values:
34831- 0x0 (FALSE): No error
34832- 0x1 (TRUE): Time out</description>
34833                <bitRange>[4:4]</bitRange>
34834                <access>read-write</access>
34835              </field>
34836              <field>
34837                <name>DATA_CRC_ERR</name>
34838                <description>Data CRC Error
34839This error occurs in SD/eMMC mode when detecting CRC
34840error when transferring read data which uses the DAT line,
34841when detecting the Write CRC status having a value of other
34842than 010 or when write CRC status timeout.
34843Values:
34844- 0x0 (FALSE): No error
34845- 0x1 (TRUE): Error</description>
34846                <bitRange>[5:5]</bitRange>
34847                <access>read-write</access>
34848              </field>
34849              <field>
34850                <name>DATA_END_BIT_ERR</name>
34851                <description>Data End Bit Error
34852This error occurs in SD/eMMC mode either when detecting 0
34853at the end bit position of read data that uses the DAT line or
34854at the end bit position of the CRC status.
34855Values:
34856- 0x0 (FALSE): No error
34857- 0x1 (TRUE): Error</description>
34858                <bitRange>[6:6]</bitRange>
34859                <access>read-write</access>
34860              </field>
34861              <field>
34862                <name>CUR_LMT_ERR</name>
34863                <description>Current Limit Error
34864By setting the SD Bus Power bit in the Power Control
34865register, the Host Controller is requested to supply power for
34866the SD Bus. If the Host Controller supports the Current Limit
34867function, it can be protected from an illegal card by stopping
34868power supply to the card in which case this bit indicates a
34869failure status. A reading of 1 for this bit means that the Host
34870Controller is not supplying power to the SD card due to some
34871failure. A reading of 0 for this bit means that the Host
34872Controller is supplying power and no error has occurred. The
34873Host Controller may require some sampling time to detect
34874the current limit. DWC_mshc Host Controller does not
34875support this function, this bit is always set to 0.
34876Values:
34877- 0x0 (FALSE): No error
34878- 0x1 (TRUE): Power Fail</description>
34879                <bitRange>[7:7]</bitRange>
34880                <access>read-write</access>
34881              </field>
34882              <field>
34883                <name>AUTO_CMD_ERR</name>
34884                <description>Auto CMD Error
34885This error status is used by Auto CMD12 and Auto CMD23 in
34886SD/eMMC mode. This bit is set when detecting that any of
34887the bits D00 to D05 in Auto CMD Error Status register has
34888changed from 0 to 1. D07 is effective in case of Auto CMD12.
34889Auto CMD Error Status register is valid while this bit is set to
348901 and may be cleared by clearing of this bit.
34891Values:
34892- 0x0 (FALSE): No error
34893- 0x1 (TRUE): Error</description>
34894                <bitRange>[8:8]</bitRange>
34895                <access>read-write</access>
34896              </field>
34897              <field>
34898                <name>ADMA_ERR</name>
34899                <description>ADMA Error
34900This bit is set when the Host Controller detects error during
34901ADMA-based data transfer. The error could be due to
34902following reasons:
34903- Error response received from System bus (Master I/F)
34904- ADMA3,ADMA2 Descriptors invalid
34905- CQE Task or Transfer descriptors invalid
34906When the error occurs, the state of the ADMA is saved in the
34907ADMA Error Status register.
34908In eMMC CQE mode:
34909The Host Controller generates this Interrupt when it detects
34910an invalid descriptor data (Valid=0) at the ST_FDS state.
34911ADMA Error State in the ADMA Error Status indicates that
34912an error has occurred in ST_FDS state. The Host Driver may
34913find that Valid bit is not set at the error descriptor.
34914Values:
34915- 0x0 (FALSE): No error
34916- 0x1 (TRUE): Error</description>
34917                <bitRange>[9:9]</bitRange>
34918                <access>read-write</access>
34919              </field>
34920              <field>
34921                <name>TUNING_ERR</name>
34922                <description>N/A</description>
34923                <bitRange>[10:10]</bitRange>
34924                <access>read-write</access>
34925              </field>
34926              <field>
34927                <name>RESP_ERR</name>
34928                <description>Response Error
34929Host Controller Version 4.00 supports response error check
34930function to avoid overhead of response error check by Host
34931Driver during DMA execution. If Response Error Check
34932Enable is set to 1 in the Transfer Mode register, Host
34933Controller Checks R1 or R5 response. If an error is detected
34934in a response, this bit is set to 1.This is applicable in
34935SD/eMMC mode.
34936Values:
34937- 0x0 (FALSE): No error
34938- 0x1 (TRUE): Error</description>
34939                <bitRange>[11:11]</bitRange>
34940                <access>read-write</access>
34941              </field>
34942              <field>
34943                <name>BOOT_ACK_ERR</name>
34944                <description>Boot Acknowledgement Error
34945This bit is set when there is a timeout for boot
34946acknowledgement or when detecting boot ack status having
34947a value other than 010. This is applicable only when boot
34948acknowledgement is expected in eMMC mode.
34949In SD mode, this bit is irrelevant.
34950Values:
34951- 0x0 (FALSE): No error
34952- 0x1 (TRUE): Error</description>
34953                <bitRange>[12:12]</bitRange>
34954                <access>read-write</access>
34955              </field>
34956            </fields>
34957          </register>
34958          <register>
34959            <name>NORMAL_INT_STAT_EN_R</name>
34960            <description>Normal Interrupt Status Enable Register</description>
34961            <addressOffset>0x34</addressOffset>
34962            <size>16</size>
34963            <access>read-write</access>
34964            <resetValue>0x0</resetValue>
34965            <resetMask>0x7FFF</resetMask>
34966            <fields>
34967              <field>
34968                <name>CMD_COMPLETE_STAT_EN</name>
34969                <description>Command Complete Status Enable
34970Values:
34971- 0x0 (FALSE): Masked
34972- 0x1 (TRUE): Enabled</description>
34973                <bitRange>[0:0]</bitRange>
34974                <access>read-write</access>
34975              </field>
34976              <field>
34977                <name>XFER_COMPLETE_STAT_EN</name>
34978                <description>Transfer Complete Status Enable
34979Values:
34980- 0x0 (FALSE): Masked
34981- 0x1 (TRUE): Enabled</description>
34982                <bitRange>[1:1]</bitRange>
34983                <access>read-write</access>
34984              </field>
34985              <field>
34986                <name>BGAP_EVENT_STAT_EN</name>
34987                <description>Block Gap Event Status Enable
34988Values:
34989- 0x0 (FALSE): Masked
34990- 0x1 (TRUE): Enabled</description>
34991                <bitRange>[2:2]</bitRange>
34992                <access>read-write</access>
34993              </field>
34994              <field>
34995                <name>DMA_INTERRUPT_STAT_EN</name>
34996                <description>DMA Interrupt Status Enable
34997Values:
34998- 0x0 (FALSE): Masked
34999- 0x1 (TRUE): Enabled</description>
35000                <bitRange>[3:3]</bitRange>
35001                <access>read-write</access>
35002              </field>
35003              <field>
35004                <name>BUF_WR_READY_STAT_EN</name>
35005                <description>Buffer Write Ready Status Enable
35006Values:
35007- 0x0 (FALSE): Masked
35008- 0x1 (TRUE): Enabled</description>
35009                <bitRange>[4:4]</bitRange>
35010                <access>read-write</access>
35011              </field>
35012              <field>
35013                <name>BUF_RD_READY_STAT_EN</name>
35014                <description>Buffer Read Ready Status Enable
35015Values:
35016- 0x0 (FALSE): Masked
35017- 0x1 (TRUE): Enabled</description>
35018                <bitRange>[5:5]</bitRange>
35019                <access>read-write</access>
35020              </field>
35021              <field>
35022                <name>CARD_INSERTION_STAT_EN</name>
35023                <description>Card Insertion Status Enable
35024Values:
35025- 0x0 (FALSE): Masked
35026- 0x1 (TRUE): Enabled</description>
35027                <bitRange>[6:6]</bitRange>
35028                <access>read-write</access>
35029              </field>
35030              <field>
35031                <name>CARD_REMOVAL_STAT_EN</name>
35032                <description>Card Removal Status Enable
35033Values:
35034- 0x0 (FALSE): Masked
35035- 0x1 (TRUE): Enabled</description>
35036                <bitRange>[7:7]</bitRange>
35037                <access>read-write</access>
35038              </field>
35039              <field>
35040                <name>CARD_INTERRUPT_STAT_EN</name>
35041                <description>Card Interrupt Status Enable
35042If this bit is set to 0, the Host Controller clears the interrupt
35043request to the System. The Card Interrupt detection is
35044stopped when this bit is cleared and restarted when this bit is
35045set to 1. The Host Driver may clear the Card Interrupt Status
35046Enable before servicing the Card Interrupt and may set this
35047bit again after all interrupt requests from the card are cleared
35048to prevent inadvertent interrupts.
35049Values:
35050- 0x0 (FALSE): Masked
35051- 0x1 (TRUE): Enabled</description>
35052                <bitRange>[8:8]</bitRange>
35053                <access>read-write</access>
35054              </field>
35055              <field>
35056                <name>INT_A_STAT_EN</name>
35057                <description>N/A</description>
35058                <bitRange>[9:9]</bitRange>
35059                <access>read-write</access>
35060              </field>
35061              <field>
35062                <name>INT_B_STAT_EN</name>
35063                <description>N/A</description>
35064                <bitRange>[10:10]</bitRange>
35065                <access>read-write</access>
35066              </field>
35067              <field>
35068                <name>INT_C_STAT_EN</name>
35069                <description>N/A</description>
35070                <bitRange>[11:11]</bitRange>
35071                <access>read-write</access>
35072              </field>
35073              <field>
35074                <name>RE_TUNE_EVENT_STAT_EN</name>
35075                <description>N/A</description>
35076                <bitRange>[12:12]</bitRange>
35077                <access>read-write</access>
35078              </field>
35079              <field>
35080                <name>FX_EVENT_STAT_EN</name>
35081                <description>FX Event Status Enable
35082This bit is added from Version 4.10.
35083Values:
35084- 0x0 (FALSE): Masked
35085- 0x1 (TRUE): Enabled</description>
35086                <bitRange>[13:13]</bitRange>
35087                <access>read-write</access>
35088              </field>
35089              <field>
35090                <name>CQE_EVENT_STAT_EN</name>
35091                <description>CQE Event Status Enable
35092Values:
35093- 0x0 (FALSE): Masked
35094- 0x1 (TRUE): Enabled</description>
35095                <bitRange>[14:14]</bitRange>
35096                <access>read-write</access>
35097              </field>
35098            </fields>
35099          </register>
35100          <register>
35101            <name>ERROR_INT_STAT_EN_R</name>
35102            <description>Error Interrupt Status Enable Register</description>
35103            <addressOffset>0x36</addressOffset>
35104            <size>16</size>
35105            <access>read-write</access>
35106            <resetValue>0x0</resetValue>
35107            <resetMask>0xFFFF</resetMask>
35108            <fields>
35109              <field>
35110                <name>CMD_TOUT_ERR_STAT_EN</name>
35111                <description>Command Timeout Error Status Enable (SD/eMMC Mode
35112only).
35113Values:
35114- 0x0 (FALSE): Masked
35115- 0x1 (TRUE): Enabled</description>
35116                <bitRange>[0:0]</bitRange>
35117                <access>read-write</access>
35118              </field>
35119              <field>
35120                <name>CMD_CRC_ERR_STAT_EN</name>
35121                <description>ommand CRC Error Status Enable (SD/eMMC Mode only)
35122Values:
35123- 0x0 (FALSE): Masked
35124- 0x1 (TRUE): Enabled</description>
35125                <bitRange>[1:1]</bitRange>
35126                <access>read-write</access>
35127              </field>
35128              <field>
35129                <name>CMD_END_BIT_ERR_STAT_EN</name>
35130                <description>Command End Bit Error Status Enable (SD/eMMC Mode
35131only)
35132Values:
35133- 0x0 (FALSE): Masked
35134- 0x1 (TRUE): Enabled</description>
35135                <bitRange>[2:2]</bitRange>
35136                <access>read-write</access>
35137              </field>
35138              <field>
35139                <name>CMD_IDX_ERR_STAT_EN</name>
35140                <description>Command Index Error Status Enable (SD/eMMC Mode only)
35141Values:
35142- 0x0 (FALSE): Masked
35143- 0x1 (TRUE): Enabled</description>
35144                <bitRange>[3:3]</bitRange>
35145                <access>read-write</access>
35146              </field>
35147              <field>
35148                <name>DATA_TOUT_ERR_STAT_EN</name>
35149                <description>Data Timeout Error Status Enable (SD/eMMC Mode only)
35150Values:
35151- 0x0 (FALSE): Masked
35152- 0x1 (TRUE): Enabled</description>
35153                <bitRange>[4:4]</bitRange>
35154                <access>read-write</access>
35155              </field>
35156              <field>
35157                <name>DATA_CRC_ERR_STAT_EN</name>
35158                <description>Data CRC Error Status Enable (SD/eMMC Mode only)
35159Values:
35160- 0x0 (FALSE): Masked
35161- 0x1 (TRUE): Enabled</description>
35162                <bitRange>[5:5]</bitRange>
35163                <access>read-write</access>
35164              </field>
35165              <field>
35166                <name>DATA_END_BIT_ERR_STAT_EN</name>
35167                <description>Data End Bit Error Status Enable (SD/eMMC Mode only).
35168Values:
35169- 0x0 (FALSE): Masked
35170- 0x1 (TRUE): Enabled</description>
35171                <bitRange>[6:6]</bitRange>
35172                <access>read-write</access>
35173              </field>
35174              <field>
35175                <name>CUR_LMT_ERR_STAT_EN</name>
35176                <description>Current Limit Error Status Enable
35177Values:
35178- 0x0 (FALSE): Masked
35179- 0x1 (TRUE): Enabled</description>
35180                <bitRange>[7:7]</bitRange>
35181                <access>read-write</access>
35182              </field>
35183              <field>
35184                <name>AUTO_CMD_ERR_STAT_EN</name>
35185                <description>Auto CMD Error Status Enable (SD/eMMC Mode only).
35186Values:
35187- 0x0 (FALSE): Masked
35188- 0x1 (TRUE): Enabled</description>
35189                <bitRange>[8:8]</bitRange>
35190                <access>read-write</access>
35191              </field>
35192              <field>
35193                <name>ADMA_ERR_STAT_EN</name>
35194                <description>ADMA Error Status Enable
35195Values:
35196- 0x0 (FALSE): Masked
35197- 0x1 (TRUE): Enabled</description>
35198                <bitRange>[9:9]</bitRange>
35199                <access>read-write</access>
35200              </field>
35201              <field>
35202                <name>TUNING_ERR_STAT_EN</name>
35203                <description>Tuning Error Status Enable (UHS-I Mode only)
35204Values:
35205- 0x0 (FALSE): Masked
35206- 0x1 (TRUE): Enabled</description>
35207                <bitRange>[10:10]</bitRange>
35208                <access>read-write</access>
35209              </field>
35210              <field>
35211                <name>RESP_ERR_STAT_EN</name>
35212                <description>Response Error Status Enable (SD Mode only)
35213Values:
35214- 0x0 (FALSE): Masked
35215- 0x1 (TRUE): Enabled</description>
35216                <bitRange>[11:11]</bitRange>
35217                <access>read-write</access>
35218              </field>
35219              <field>
35220                <name>BOOT_ACK_ERR_STAT_EN</name>
35221                <description>Boot Acknowledgment Error (eMMC Mode only)
35222Setting this bit to 1 enables setting of Boot Acknowledgment
35223Error in Error Interrupt Status register
35224(ERROR_INT_STAT_R).
35225Values:
35226- 0x0 (FALSE): Masked
35227- 0x1 (TRUE): Enabled</description>
35228                <bitRange>[12:12]</bitRange>
35229                <access>read-write</access>
35230              </field>
35231              <field>
35232                <name>VENDOR_ERR_STAT_EN1</name>
35233                <description>N/A</description>
35234                <bitRange>[13:13]</bitRange>
35235                <access>read-write</access>
35236              </field>
35237              <field>
35238                <name>VENDOR_ERR_STAT_EN2</name>
35239                <description>N/A</description>
35240                <bitRange>[14:14]</bitRange>
35241                <access>read-write</access>
35242              </field>
35243              <field>
35244                <name>VENDOR_ERR_STAT_EN3</name>
35245                <description>N/A</description>
35246                <bitRange>[15:15]</bitRange>
35247                <access>read-write</access>
35248              </field>
35249            </fields>
35250          </register>
35251          <register>
35252            <name>NORMAL_INT_SIGNAL_EN_R</name>
35253            <description>Normal Interrupt Signal Enable Register</description>
35254            <addressOffset>0x38</addressOffset>
35255            <size>16</size>
35256            <access>read-write</access>
35257            <resetValue>0x0</resetValue>
35258            <resetMask>0x7FFF</resetMask>
35259            <fields>
35260              <field>
35261                <name>CMD_COMPLETE_SIGNAL_EN</name>
35262                <description>Command Complete Signal Enable
35263Values:
35264- 0x0 (FALSE): Masked
35265- 0x1 (TRUE): Enabled</description>
35266                <bitRange>[0:0]</bitRange>
35267                <access>read-write</access>
35268              </field>
35269              <field>
35270                <name>XFER_COMPLETE_SIGNAL_EN</name>
35271                <description>Transfer Complete Signal Enable
35272Values:
35273- 0x0 (FALSE): Masked
35274- 0x1 (TRUE): Enabled</description>
35275                <bitRange>[1:1]</bitRange>
35276                <access>read-write</access>
35277              </field>
35278              <field>
35279                <name>BGAP_EVENT_SIGNAL_EN</name>
35280                <description>Block Gap Event Signal Enable
35281Values:
35282- 0x0 (FALSE): Masked
35283- 0x1 (TRUE): Enabled</description>
35284                <bitRange>[2:2]</bitRange>
35285                <access>read-write</access>
35286              </field>
35287              <field>
35288                <name>DMA_INTERRUPT_SIGNAL_EN</name>
35289                <description>DMA Interrupt Signal Enable
35290Values:
35291- 0x0 (FALSE): Masked
35292- 0x1 (TRUE): Enabled</description>
35293                <bitRange>[3:3]</bitRange>
35294                <access>read-write</access>
35295              </field>
35296              <field>
35297                <name>BUF_WR_READY_SIGNAL_EN</name>
35298                <description>Buffer Write Ready Signal Enable
35299Values:
35300- 0x0 (FALSE): Masked
35301- 0x1 (TRUE): Enabled</description>
35302                <bitRange>[4:4]</bitRange>
35303                <access>read-write</access>
35304              </field>
35305              <field>
35306                <name>BUF_RD_READY_SIGNAL_EN</name>
35307                <description>Buffer Read Ready Signal Enable
35308Values:
35309- 0x0 (FALSE): Masked
35310- 0x1 (TRUE): Enabled</description>
35311                <bitRange>[5:5]</bitRange>
35312                <access>read-write</access>
35313              </field>
35314              <field>
35315                <name>CARD_INSERTION_SIGNAL_EN</name>
35316                <description>Card Insertion Signal Enable
35317Values:
35318- 0x0 (FALSE): Masked
35319- 0x1 (TRUE): Enabled</description>
35320                <bitRange>[6:6]</bitRange>
35321                <access>read-write</access>
35322              </field>
35323              <field>
35324                <name>CARD_REMOVAL_SIGNAL_EN</name>
35325                <description>Card Removal Signal Enable
35326Values:
35327- 0x0 (FALSE): Masked
35328- 0x1 (TRUE): Enabled</description>
35329                <bitRange>[7:7]</bitRange>
35330                <access>read-write</access>
35331              </field>
35332              <field>
35333                <name>CARD_INTERRUPT_SIGNAL_EN</name>
35334                <description>Card Interrupt Signal Enable
35335Values:
35336- 0x0 (FALSE): Masked
35337- 0x1 (TRUE): Enabled</description>
35338                <bitRange>[8:8]</bitRange>
35339                <access>read-write</access>
35340              </field>
35341              <field>
35342                <name>INT_A_SIGNAL_EN</name>
35343                <description>N/A</description>
35344                <bitRange>[9:9]</bitRange>
35345                <access>read-write</access>
35346              </field>
35347              <field>
35348                <name>INT_B_SIGNAL_EN</name>
35349                <description>N/A</description>
35350                <bitRange>[10:10]</bitRange>
35351                <access>read-write</access>
35352              </field>
35353              <field>
35354                <name>INT_C_SIGNAL_EN</name>
35355                <description>N/A</description>
35356                <bitRange>[11:11]</bitRange>
35357                <access>read-write</access>
35358              </field>
35359              <field>
35360                <name>RE_TUNE_EVENT_SIGNAL_EN</name>
35361                <description>N/A</description>
35362                <bitRange>[12:12]</bitRange>
35363                <access>read-write</access>
35364              </field>
35365              <field>
35366                <name>FX_EVENT_SIGNAL_EN</name>
35367                <description>FX Event Signal Enable
35368Values:
35369- 0x0 (FALSE): Masked
35370- 0x1 (TRUE): Enabled</description>
35371                <bitRange>[13:13]</bitRange>
35372                <access>read-write</access>
35373              </field>
35374              <field>
35375                <name>CQE_EVENT_SIGNAL_EN</name>
35376                <description>Command Queuing Engine Event Signal Enable
35377Values:
35378- 0x0 (FALSE): Masked
35379- 0x1 (TRUE): Enabled</description>
35380                <bitRange>[14:14]</bitRange>
35381                <access>read-write</access>
35382              </field>
35383            </fields>
35384          </register>
35385          <register>
35386            <name>ERROR_INT_SIGNAL_EN_R</name>
35387            <description>Error Interrupt Signal Enable Register</description>
35388            <addressOffset>0x3A</addressOffset>
35389            <size>16</size>
35390            <access>read-write</access>
35391            <resetValue>0x0</resetValue>
35392            <resetMask>0xFFFF</resetMask>
35393            <fields>
35394              <field>
35395                <name>CMD_TOUT_ERR_SIGNAL_EN</name>
35396                <description>Command Timeout Error Signal Enable (SD/eMMC Mode
35397only)
35398Values:
35399- 0x0 (FALSE): Masked
35400- 0x1 (TRUE): Enabled</description>
35401                <bitRange>[0:0]</bitRange>
35402                <access>read-write</access>
35403              </field>
35404              <field>
35405                <name>CMD_CRC_ERR_SIGNAL_EN</name>
35406                <description>Command CRC Error Signal Enable (SD/eMMC Mode only)
35407Values:
35408- 0x0 (FALSE): Masked
35409- 0x1 (TRUE): Enabled</description>
35410                <bitRange>[1:1]</bitRange>
35411                <access>read-write</access>
35412              </field>
35413              <field>
35414                <name>CMD_END_BIT_ERR_SIGNAL_EN</name>
35415                <description>Command End Bit Error Signal Enable (SD/eMMC Mode
35416only)
35417Values:
35418- 0x0 (FALSE): Masked
35419- 0x1 (TRUE): Enabled</description>
35420                <bitRange>[2:2]</bitRange>
35421                <access>read-write</access>
35422              </field>
35423              <field>
35424                <name>CMD_IDX_ERR_SIGNAL_EN</name>
35425                <description>Command Index Error Signal Enable (SD/eMMC Mode only)
35426Values:
35427- 0x0 (FALSE): No error
35428- 0x1 (TRUE): Error</description>
35429                <bitRange>[3:3]</bitRange>
35430                <access>read-write</access>
35431              </field>
35432              <field>
35433                <name>DATA_TOUT_ERR_SIGNAL_EN</name>
35434                <description>Data Timeout Error Signal Enable (SD/eMMC Mode only)
35435Values:
35436- 0x0 (FALSE): Masked
35437- 0x1 (TRUE): Enabled</description>
35438                <bitRange>[4:4]</bitRange>
35439                <access>read-write</access>
35440              </field>
35441              <field>
35442                <name>DATA_CRC_ERR_SIGNAL_EN</name>
35443                <description>Data CRC Error Signal Enable (SD/eMMC Mode only)
35444Values:
35445- 0x0 (FALSE): Masked
35446- 0x1 (TRUE): Enabled</description>
35447                <bitRange>[5:5]</bitRange>
35448                <access>read-write</access>
35449              </field>
35450              <field>
35451                <name>DATA_END_BIT_ERR_SIGNAL_EN</name>
35452                <description>Data End Bit Error Signal Enable (SD/eMMC Mode only)
35453Values:
35454- 0x0 (FALSE): Masked
35455- 0x1 (TRUE): Enabled</description>
35456                <bitRange>[6:6]</bitRange>
35457                <access>read-write</access>
35458              </field>
35459              <field>
35460                <name>CUR_LMT_ERR_SIGNAL_EN</name>
35461                <description>Current Limit Error Signal Enable
35462Values:
35463- 0x0 (FALSE): Masked
35464- 0x1 (TRUE): Enabled</description>
35465                <bitRange>[7:7]</bitRange>
35466                <access>read-write</access>
35467              </field>
35468              <field>
35469                <name>AUTO_CMD_ERR_SIGNAL_EN</name>
35470                <description>Auto CMD Error Signal Enable (SD/eMMC Mode only)
35471Values:
35472- 0x0 (FALSE): Masked
35473- 0x1 (TRUE): Enabled</description>
35474                <bitRange>[8:8]</bitRange>
35475                <access>read-write</access>
35476              </field>
35477              <field>
35478                <name>ADMA_ERR_SIGNAL_EN</name>
35479                <description>ADMA Error Signal Enable
35480Values:
35481- 0x0 (FALSE): Masked
35482- 0x1 (TRUE): Enabled</description>
35483                <bitRange>[9:9]</bitRange>
35484                <access>read-write</access>
35485              </field>
35486              <field>
35487                <name>TUNING_ERR_SIGNAL_EN</name>
35488                <description>N/A</description>
35489                <bitRange>[10:10]</bitRange>
35490                <access>read-write</access>
35491              </field>
35492              <field>
35493                <name>RESP_ERR_SIGNAL_EN</name>
35494                <description>Response Error Signal Enable (SD Mode only)
35495Values:
35496- 0x0 (FALSE): Masked
35497- 0x1 (TRUE): Enabled</description>
35498                <bitRange>[11:11]</bitRange>
35499                <access>read-write</access>
35500              </field>
35501              <field>
35502                <name>BOOT_ACK_ERR_SIGNAL_EN</name>
35503                <description>Boot Acknowledgment Error (eMMC Mode only).
35504Setting this bit to 1 enables generating interrupt signal when
35505Boot Acknowledgement Error in Error Interrupt Status
35506register is set.
35507Values:
35508- 0x0 (FALSE): Masked
35509- 0x1 (TRUE): Enabled</description>
35510                <bitRange>[12:12]</bitRange>
35511                <access>read-write</access>
35512              </field>
35513              <field>
35514                <name>VENDOR_ERR_SIGNAL_EN1</name>
35515                <description>N/A</description>
35516                <bitRange>[13:13]</bitRange>
35517                <access>read-write</access>
35518              </field>
35519              <field>
35520                <name>VENDOR_ERR_SIGNAL_EN2</name>
35521                <description>N/A</description>
35522                <bitRange>[14:14]</bitRange>
35523                <access>read-write</access>
35524              </field>
35525              <field>
35526                <name>VENDOR_ERR_SIGNAL_EN3</name>
35527                <description>N/A</description>
35528                <bitRange>[15:15]</bitRange>
35529                <access>read-write</access>
35530              </field>
35531            </fields>
35532          </register>
35533          <register>
35534            <name>AUTO_CMD_STAT_R</name>
35535            <description>Auto CMD Status Register</description>
35536            <addressOffset>0x3C</addressOffset>
35537            <size>16</size>
35538            <access>read-only</access>
35539            <resetValue>0x0</resetValue>
35540            <resetMask>0xBF</resetMask>
35541            <fields>
35542              <field>
35543                <name>AUTO_CMD12_NOT_EXEC</name>
35544                <description>Auto CMD12 Not Executed
35545If multiple memory block data transfer is not started due to a
35546command error, this bit is not set because it is not necessary
35547to issue an Auto CMD12. Setting this bit to 1 means that the
35548Host Controller cannot issue Auto CMD12 to stop multiple
35549memory block data transfer, due to some error. If this bit is
35550set to 1, error status bits (D04-D01) is meaningless.
35551This bit is set to 0 when Auto CMD Error is generated by
35552Auto CMD23.
35553Values:
35554- 0x1 (TRUE): Not Executed
35555- 0x0 (FALSE): Executed</description>
35556                <bitRange>[0:0]</bitRange>
35557                <access>read-only</access>
35558              </field>
35559              <field>
35560                <name>AUTO_CMD_TOUT_ERR</name>
35561                <description>Auto CMD Timeout Error
35562This bit is set if no response is returned with 64 SDCLK
35563cycles from the end bit of the command.
35564If this bit is set to 1, error status bits (D04-D01) are
35565meaningless.
35566Values:
35567- 0x1 (TRUE): Time out
35568- 0x0 (FALSE): No Error</description>
35569                <bitRange>[1:1]</bitRange>
35570                <access>read-only</access>
35571              </field>
35572              <field>
35573                <name>AUTO_CMD_CRC_ERR</name>
35574                <description>Auto CMD CRC Error
35575This bit is set when detecting a CRC error in the command
35576response.
35577Values:
35578- 0x1 (TRUE): CRC Error Generated
35579- 0x0 (FALSE): No Error</description>
35580                <bitRange>[2:2]</bitRange>
35581                <access>read-only</access>
35582              </field>
35583              <field>
35584                <name>AUTO_CMD_EBIT_ERR</name>
35585                <description>Auto CMD End Bit Error
35586This bit is set when detecting that the end bit of command
35587response is 0.
35588Values:
35589- 0x1 (TRUE): End Bit Error Generated
35590- 0x0 (FALSE): No Error</description>
35591                <bitRange>[3:3]</bitRange>
35592                <access>read-only</access>
35593              </field>
35594              <field>
35595                <name>AUTO_CMD_IDX_ERR</name>
35596                <description>Auto CMD Index Error
35597This bit is set if the command index error occurs in response
35598to a command.
35599Values:
35600- 0x1 (TRUE): Error
35601- 0x0 (FALSE): No Error</description>
35602                <bitRange>[4:4]</bitRange>
35603                <access>read-only</access>
35604              </field>
35605              <field>
35606                <name>AUTO_CMD_RESP_ERR</name>
35607                <description>Auto CMD Response Error
35608This bit is set when Response Error Check Enable in the
35609Transfer Mode register is set to 1 and an error is detected in
35610R1 response of either Auto CMD12 or CMD13. This status is
35611ignored if any bit between D00 to D04 is set to 1.
35612Values:
35613- 0x1 (TRUE): Error
35614- 0x0 (FALSE): No Error</description>
35615                <bitRange>[5:5]</bitRange>
35616                <access>read-only</access>
35617              </field>
35618              <field>
35619                <name>CMD_NOT_ISSUED_AUTO_CMD12</name>
35620                <description>Command Not Issued By Auto CMD12 Error
35621If this bit is set to 1, CMD_wo_DAT is not executed due to an
35622Auto CMD12 Error (D04-D01) in this register.
35623This bit is set to 0 when Auto CMD Error is generated by
35624Auto CMD23.
35625Values:
35626- 0x1 (TRUE): Not Issued
35627- 0x0 (FALSE): No Error</description>
35628                <bitRange>[7:7]</bitRange>
35629                <access>read-only</access>
35630              </field>
35631            </fields>
35632          </register>
35633          <register>
35634            <name>HOST_CTRL2_R</name>
35635            <description>Host Control 2 Register</description>
35636            <addressOffset>0x3E</addressOffset>
35637            <size>16</size>
35638            <access>read-write</access>
35639            <resetValue>0x0</resetValue>
35640            <resetMask>0xFDFF</resetMask>
35641            <fields>
35642              <field>
35643                <name>UHS_MODE_SEL</name>
35644                <description>N/A</description>
35645                <bitRange>[2:0]</bitRange>
35646                <access>read-write</access>
35647              </field>
35648              <field>
35649                <name>SIGNALING_EN</name>
35650                <description>1.8V Signaling Enable
35651This bit controls voltage regulator for I/O cell in SD UHS-I mode. Setting this bit from 0 to 1 starts changing the
35652signal voltage from 3.3V to 1.8V. Host Controller clears this
35653bit if switching to 1.8V signaling fails per protocol. The value is reflected on the io_volt_sel output which can then be used to change an external regulator to supply 1.8V instead of 3.3V on the VDDIO pin associated with the CLK/CMD/DAT signals.
35654Note: This bit must be set for all UHS-I speed modes
35655(SDR12/SDR25/SDR50/DDR50).
35656Values:
35657- 0x0 (V_3_3): 3.3V Signalling
35658- 0x1 (V_1_8): 1.8V Signalling</description>
35659                <bitRange>[3:3]</bitRange>
35660                <access>read-write</access>
35661              </field>
35662              <field>
35663                <name>DRV_STRENGTH_SEL</name>
35664                <description>Driver Strength Select
35665These bits are used to select the Host Controller output driver in
356661.8V signaling UHS-I/eMMC speed modes. The value is reflected on the io_drive_strength[1:0] output.
35667- 0x0 (TYPEB): Driver TYPEB is selected
35668- 0x1 (TYPEA): Driver TYPEA is selected
35669- 0x2 (TYPEC): Driver TYPEC is selected
35670- 0x3 (TYPED): Driver TYPED is selected</description>
35671                <bitRange>[5:4]</bitRange>
35672                <access>read-write</access>
35673              </field>
35674              <field>
35675                <name>EXEC_TUNING</name>
35676                <description>N/A</description>
35677                <bitRange>[6:6]</bitRange>
35678                <access>read-write</access>
35679              </field>
35680              <field>
35681                <name>SAMPLE_CLK_SEL</name>
35682                <description>N/A</description>
35683                <bitRange>[7:7]</bitRange>
35684                <access>read-write</access>
35685              </field>
35686              <field>
35687                <name>UHS2_IF_ENABLE</name>
35688                <description>N/A</description>
35689                <bitRange>[8:8]</bitRange>
35690                <access>read-write</access>
35691              </field>
35692              <field>
35693                <name>ADMA2_LEN_MODE</name>
35694                <description>ADMA2 Length Mode
35695This bit selects ADMA2 Length mode to be either 16-bit or
3569626-bit.
35697Values:
35698- 0x0 (FALSE): 16-bit Data Length Mode
35699- 0x1 (TRUE): 26-bit Data Length Mode</description>
35700                <bitRange>[10:10]</bitRange>
35701                <access>read-write</access>
35702              </field>
35703              <field>
35704                <name>CMD23_ENABLE</name>
35705                <description>CMD23 Enable
35706If the card supports CMD23, this bit is set to 1. This bit is
35707used to select Auto CMD23 or Auto CMD12 for ADMA3 data
35708transfer.
35709Values:
35710- 0x0 (FALSE): Auto CMD23 is disabled
35711- 0x1 (TRUE): Auto CMD23 is enabled</description>
35712                <bitRange>[11:11]</bitRange>
35713                <access>read-write</access>
35714              </field>
35715              <field>
35716                <name>HOST_VER4_ENABLE</name>
35717                <description>Host Version 4 Enable
35718This bit selects either Version 3.00 compatible mode or
35719Version 4 mode.
35720Functions of following fields are modified for Host Version 4
35721mode:
35722- SDMA Address: SDMA uses ADMA System Address
35723(05Fh-058h) instead of SDMA System Address register
35724(003h-000h)
35725- ADMA2/ADMA3 selection: ADMA3 is selected by DMA
35726select in Host Control 1 register
35727- 32-bit Block Count: SDMA System Address register
35728(003h-000h) is modified to 32-bit Block Count register
35729Note: It is recommended not to program ADMA3 Integrated
35730Descriptor Address registers and
35731Command Queuing registers (if applicable) while operating
35732in Host version less than 4 mode (Host Version 4 Enable =
357330).
35734Values:
35735- 0x0 (FALSE): Version 3.00 compatible mode
35736- 0x1 (TRUE): Version 4 mode</description>
35737                <bitRange>[12:12]</bitRange>
35738                <access>read-write</access>
35739              </field>
35740              <field>
35741                <name>ADDRESSING</name>
35742                <description>N/A</description>
35743                <bitRange>[13:13]</bitRange>
35744                <access>read-write</access>
35745              </field>
35746              <field>
35747                <name>ASYNC_INT_ENABLE</name>
35748                <description>Asynchronous Interrupt Enable
35749This bit can be set if a card supports asynchronous
35750interrupts and Asynchronous Interrupt Support is set to 1 in
35751the Capabilities register.
35752Values:
35753- 0x0 (FALSE): Disabled
35754- 0x1 (TRUE): Enabled</description>
35755                <bitRange>[14:14]</bitRange>
35756                <access>read-write</access>
35757              </field>
35758              <field>
35759                <name>PRESET_VAL_ENABLE</name>
35760                <description>N/A</description>
35761                <bitRange>[15:15]</bitRange>
35762                <access>read-write</access>
35763              </field>
35764            </fields>
35765          </register>
35766          <register>
35767            <name>CAPABILITIES1_R</name>
35768            <description>Capabilities 1 Register - 0 to 31</description>
35769            <addressOffset>0x40</addressOffset>
35770            <size>32</size>
35771            <access>read-only</access>
35772            <resetValue>0x276C6481</resetValue>
35773            <resetMask>0xFFEFFFBF</resetMask>
35774            <fields>
35775              <field>
35776                <name>TOUT_CLK_FREQ</name>
35777                <description>Timeout Clock Frequency
35778This bit shows the base clock frequency used to detect Data
35779Timeout Error. The Timeout Clock unit defines the unit of
35780timeout clock frequency. It can be KHz or MHz.
35781- 0x00 - Get information through another method
35782- 0x01 - 1KHz / 1MHz
35783- 0x02 - 2KHz / 2MHz
35784- 0x03 - 3KHz / 3MHz
35785- ...........
35786- 0x3F - 63KHz / 63MHz</description>
35787                <bitRange>[5:0]</bitRange>
35788                <access>read-only</access>
35789              </field>
35790              <field>
35791                <name>TOUT_CLK_UNIT</name>
35792                <description>Timeout Clock Unit
35793This bit shows the unit of base clock frequency used to
35794detect Data TImeout Error.
35795Values:
35796- 0x0 (KHZ): KHz
35797- 0x1 (MHZ): MHz</description>
35798                <bitRange>[7:7]</bitRange>
35799                <access>read-only</access>
35800              </field>
35801              <field>
35802                <name>BASE_CLK_FREQ</name>
35803                <description>Base Clock Frequency for SD clock
35804These bits indicate the base (maximum) clock frequency for
35805the SD Clock. The definition of these bits depend on the Host
35806Controller Version.
35807- 6-Bit Base Clock Frequency: This mode is supported by
35808the Host Controller version 1.00 and 2.00. The upper 2
35809bits are not effective and are always 0. The unit values
35810are 1 MHz. The supported clock range is 10 MHz to 63
35811MHz.
35812- 0x00 - Get information through another method
35813- 0x01 - 1 MHz
35814- 0x02 - 2 MHz
35815- .............
35816- 0x3F - 63 MHz
35817- 0x40-0xFF - Not Supported
35818- 8-Bit Base Clock Frequency: This mode is supported by
35819the Host Controller version 3.00. The unit values are 1
35820MHz. The supported clock range is 10 MHz to 255 MHz.
35821- 0x00 - Get information through another method
35822- 0x01 - 1 MHz
35823- 0x02 - 2 MHz
35824- ............
35825- 0xFF - 255 MHz
35826If the frequency is 16.5 MHz, the larger value is set to
358270001001b (17 MHz) because the Host Driver uses this value
35828to calculate the clock divider value and it does not exceed
35829the upper limit of the SD Clock frequency. If these bits are all
358300, the Host system has to get information using a different
35831method.</description>
35832                <bitRange>[15:8]</bitRange>
35833                <access>read-only</access>
35834              </field>
35835              <field>
35836                <name>MAX_BLK_LEN</name>
35837                <description>N/A</description>
35838                <bitRange>[17:16]</bitRange>
35839                <access>read-only</access>
35840              </field>
35841              <field>
35842                <name>EMBEDDED_8_BIT</name>
35843                <description>8-bit Support for Embedded Device
35844This bit indicates whether the Host Controller is capable of
35845using an 8-bit bus width mode. This bit is not effective when
35846the Slot Type is set to 10b.
35847Values:
35848- 0x0 (FALSE): 8-bit Bus Width not Supported
35849- 0x1 (TRUE): 8-bit Bus Width Supported</description>
35850                <bitRange>[18:18]</bitRange>
35851                <access>read-only</access>
35852              </field>
35853              <field>
35854                <name>ADMA2_SUPPORT</name>
35855                <description>ADMA2 Support
35856This bit indicates whether the Host Controller is capable of
35857using ADMA2.
35858Values:
35859- 0x0 (FALSE): ADMA2 not Supported
35860- 0x1 (TRUE): ADMA2 Supported</description>
35861                <bitRange>[19:19]</bitRange>
35862                <access>read-only</access>
35863              </field>
35864              <field>
35865                <name>HIGH_SPEED_SUPPORT</name>
35866                <description>High Speed Support
35867This bit indicates whether the Host Controller and the Host
35868System supports High Speed mode and they can supply the
35869SD Clock frequency from 25 MHz to 50 MHz.
35870Values:
35871- 0x0 (FALSE): High Speed not Supported
35872- 0x1 (TRUE): High Speed Supported</description>
35873                <bitRange>[21:21]</bitRange>
35874                <access>read-only</access>
35875              </field>
35876              <field>
35877                <name>SDMA_SUPPORT</name>
35878                <description>SDMA Support
35879This bit indicates whether the Host Controller is capable of
35880using SDMA to transfer data between the system memory
35881and the Host Controller directly.
35882Values:
35883- 0x0 (FALSE): SDMA not Supported
35884- 0x1 (TRUE): SDMA Supported</description>
35885                <bitRange>[22:22]</bitRange>
35886                <access>read-only</access>
35887              </field>
35888              <field>
35889                <name>SUS_RES_SUPPORT</name>
35890                <description>Suspense/Resume Support
35891This bit indicates whether the Host Controller supports
35892Suspend/Resume functionality. If this bit is 0, the Host Driver
35893does not issue either Suspend or Resume commands
35894because the Suspend and Resume mechanism is not
35895supported.
35896Values:
35897- 0x0 (FALSE): Not Supported
35898- 0x1 (TRUE): Supported</description>
35899                <bitRange>[23:23]</bitRange>
35900                <access>read-only</access>
35901              </field>
35902              <field>
35903                <name>VOLT_33</name>
35904                <description>Voltage Support 3.3V
35905Values:
35906- 0x0 (FALSE): 3.3V Not Supported
35907- 0x1 (TRUE): 3.3V Supported</description>
35908                <bitRange>[24:24]</bitRange>
35909                <access>read-only</access>
35910              </field>
35911              <field>
35912                <name>VOLT_30</name>
35913                <description>Voltage Support 3.0V
35914Values:
35915- 0x0 (FALSE): 3.0V Not Supported
35916- 0x1 (TRUE): 3.0V Supported</description>
35917                <bitRange>[25:25]</bitRange>
35918                <access>read-only</access>
35919              </field>
35920              <field>
35921                <name>VOLT_18</name>
35922                <description>Voltage Support 1.8V
35923Values:
35924- 0x0 (FALSE): 1.8V Not Supported
35925- 0x1 (TRUE): 1.8V Supported</description>
35926                <bitRange>[26:26]</bitRange>
35927                <access>read-only</access>
35928              </field>
35929              <field>
35930                <name>SYS_ADDR_64_V4</name>
35931                <description>64-bit System Address Support for V4
35932This bit sets the Host Controller to support 64-bit System
35933Addressing of V4 mode. When this bit is set to 1, full or part
35934of 64-bit address must be used to decode the Host Controller
35935Registers so that Host Controller Registers can be placed
35936above system memory area. 64-bit address decode of Host
35937Controller registers is effective regardless of setting to 64-bit
35938Addressing in Host Control 2.
35939If this bit is set to 1, 64-bit DMA Addressing for version 4 is
35940enabled by setting Host Version 4 Enable
35941(HOST_VER4_ENABLE = 1) and by setting 64-bit
35942Addressing (ADDRESSING =1) in the Host Control 2
35943register. SDMA can be used and ADMA2 uses 128-bit
35944Descriptor.
35945Values:
35946- 0x0 (FALSE): 64-bit System Address for V4 is Not
35947Supported
35948- 0x1 (TRUE): 64-bit System Address for V4 is Supported</description>
35949                <bitRange>[27:27]</bitRange>
35950                <access>read-only</access>
35951              </field>
35952              <field>
35953                <name>SYS_ADDR_64_V3</name>
35954                <description>64-bit System Address Support for V3
35955This bit sets the Host controller to support 64-bit System
35956Addressing of V3 mode.
35957SDMA cannot be used in 64-bit Addressing in Version 3
35958Mode.
35959If this bit is set to 1, 64-bit ADMA2 with using 96-bit
35960Descriptor can be enabled by setting Host Version 4 Enable
35961(HOST_VER4_ENABLE = 0) and DMA select (DMA_SEL =
3596211b).
35963Values:
35964- 0x0 (FALSE): 64-bit System Address for V3 is Not
35965Supported
35966- 0x1 (TRUE): 64-bit System Address for V3 is Supported</description>
35967                <bitRange>[28:28]</bitRange>
35968                <access>read-only</access>
35969              </field>
35970              <field>
35971                <name>ASYNC_INT_SUPPORT</name>
35972                <description>Asynchronous Interrupt Support (SD Mode only)
35973Values:
35974- 0x0 (FALSE): Asynchronous Interrupt Not Supported
35975- 0x1 (TRUE): Asynchronous Interrupt Supported</description>
35976                <bitRange>[29:29]</bitRange>
35977                <access>read-only</access>
35978              </field>
35979              <field>
35980                <name>SLOT_TYPE_R</name>
35981                <description>Slot Type
35982These bits indicate usage of a slot by a specific Host
35983System.
35984Values:
35985- 0x0 (REMOVABLE_SLOT): Removable Card Slot
35986- 0x1 (EMBEDDED_SLOT): Embedded Slot for one Device
35987- 0x2 (SHARED_SLOT): Shared Bus Slot (SD mode)
35988- 0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple
35989Embedded Devices</description>
35990                <bitRange>[31:30]</bitRange>
35991                <access>read-only</access>
35992              </field>
35993            </fields>
35994          </register>
35995          <register>
35996            <name>CAPABILITIES2_R</name>
35997            <description>Capabilities Register - 32 to 63</description>
35998            <addressOffset>0x44</addressOffset>
35999            <size>32</size>
36000            <access>read-only</access>
36001            <resetValue>0x8000077</resetValue>
36002            <resetMask>0x18FFEF7F</resetMask>
36003            <fields>
36004              <field>
36005                <name>SDR50_SUPPORT</name>
36006                <description>SDR50 Support (UHS-I only)
36007Thsi bit indicates that SDR50 is supported. The bit 13
36008(USE_TUNING_SDR50) indicates whether SDR50 requires
36009tuning or not.
36010Values:
36011- 0x0 (FALSE): SDR50 is not supported
36012- 0x1 (TRUE): SDR50 is supported</description>
36013                <bitRange>[0:0]</bitRange>
36014                <access>read-only</access>
36015              </field>
36016              <field>
36017                <name>SDR104_SUPPORT</name>
36018                <description>SDR104 Support (UHS-I only)
36019This bit mentions that SDR104 requires tuning.
36020Values:
36021- 0x0 (FALSE): SDR104 is not supported
36022- 0x1 (TRUE): SDR104 is supported (NOT ACTUALLY SUPPORTED)</description>
36023                <bitRange>[1:1]</bitRange>
36024                <access>read-only</access>
36025              </field>
36026              <field>
36027                <name>DDR50_SUPPORT</name>
36028                <description>DDR50 Support (UHS-I only)
36029Values:
36030- 0x0 (FALSE): DDR50 is not supported
36031- 0x1 (TRUE): DDR50 is supported</description>
36032                <bitRange>[2:2]</bitRange>
36033                <access>read-only</access>
36034              </field>
36035              <field>
36036                <name>UHS2_SUPPORT</name>
36037                <description>UHS-II Support (UHS-II only)
36038This bit indicates whether Host Controller supports UHS-II.
36039Values:
36040- 0x0 (FALSE): UHS-II is not supported
36041- 0x1 (TRUE): UHS-II is supported</description>
36042                <bitRange>[3:3]</bitRange>
36043                <access>read-only</access>
36044              </field>
36045              <field>
36046                <name>DRV_TYPEA</name>
36047                <description>Driver Type A Support (UHS-I only)
36048This bit indicates support of Driver Type A for 1.8 Signaling.
36049Values:
36050- 0x0 (FALSE): Driver Type A is not supported
36051- 0x1 (TRUE): Driver Type A is supported</description>
36052                <bitRange>[4:4]</bitRange>
36053                <access>read-only</access>
36054              </field>
36055              <field>
36056                <name>DRV_TYPEC</name>
36057                <description>Driver Type C Support (UHS-I only)
36058This bit indicates support of Driver Type C for 1.8 Signaling.
36059Values:
36060- 0x0 (FALSE): Driver Type C is not supported
36061- 0x1 (TRUE): Driver Type C is supported</description>
36062                <bitRange>[5:5]</bitRange>
36063                <access>read-only</access>
36064              </field>
36065              <field>
36066                <name>DRV_TYPED</name>
36067                <description>Driver Type D Support (UHS-I only)
36068This bit indicates support of Driver Type D for 1.8 Signaling.
36069Values:
36070- 0x0 (FALSE): Driver Type D is not supported
36071- 0x1 (TRUE): Driver Type D is supported</description>
36072                <bitRange>[6:6]</bitRange>
36073                <access>read-only</access>
36074              </field>
36075              <field>
36076                <name>RETUNE_CNT</name>
36077                <description>N/A</description>
36078                <bitRange>[11:8]</bitRange>
36079                <access>read-only</access>
36080              </field>
36081              <field>
36082                <name>USE_TUNING_SDR50</name>
36083                <description>Use Tuning for SDR50 (UHS-I only)
36084Values:
36085- 0x0 (ZERO): SDR50 does not require tuning
36086- 0x1 (ONE): SDR50 requires tuning</description>
36087                <bitRange>[13:13]</bitRange>
36088                <access>read-only</access>
36089              </field>
36090              <field>
36091                <name>RE_TUNING_MODES</name>
36092                <description>N/A</description>
36093                <bitRange>[15:14]</bitRange>
36094                <access>read-only</access>
36095              </field>
36096              <field>
36097                <name>CLK_MUL</name>
36098                <description>Clock Multiplier
36099These bits indicate the clock multiplier of the programmable
36100clock generator. Setting these bits to 0 means that the Host
36101Controller does not support a programmable clock generator.
36102- 0x0: Clock Multiplier is not Supported
36103- 0x1: Clock Multiplier M = 2
36104- 0x2: Clock Multiplier M = 3
36105- .........
36106- 0xFF: Clock Multiplier M = 256</description>
36107                <bitRange>[23:16]</bitRange>
36108                <access>read-only</access>
36109              </field>
36110              <field>
36111                <name>ADMA3_SUPPORT</name>
36112                <description>ADMA3 Support
36113This bit indicates whether the Host Controller is capable of
36114using ADMA3.
36115Values:
36116- 0x0 (FALSE): ADMA3 not Supported
36117- 0x1 (TRUE): ADMA3 Supported</description>
36118                <bitRange>[27:27]</bitRange>
36119                <access>read-only</access>
36120              </field>
36121              <field>
36122                <name>VDD2_18V_SUPPORT</name>
36123                <description>1.8V VDD2 Support
36124This bit indicates support of VDD2 for the Host System.
36125Values:
36126- 0x0 (FALSE): 1.8V VDD2 is not Supported
36127- 0x1 (TRUE): 1.8V VDD2 is Supported</description>
36128                <bitRange>[28:28]</bitRange>
36129                <access>read-only</access>
36130              </field>
36131            </fields>
36132          </register>
36133          <register>
36134            <name>CURR_CAPABILITIES1_R</name>
36135            <description>Current Capabilities Register - 0 to 31</description>
36136            <addressOffset>0x48</addressOffset>
36137            <size>32</size>
36138            <access>read-only</access>
36139            <resetValue>0x0</resetValue>
36140            <resetMask>0xFFFFFF</resetMask>
36141            <fields>
36142              <field>
36143                <name>MAX_CUR_33V</name>
36144                <description>Maximum Current for 3.3V
36145This bit specifies the Maximum Current for 3.3V VDD1 power
36146supply for the card.
36147- 0: Get information through another method
36148- 1: 4mA
36149- 2: 8mA
36150- 3: 13mA
36151- .......
36152- 255: 1020mA</description>
36153                <bitRange>[7:0]</bitRange>
36154                <access>read-only</access>
36155              </field>
36156              <field>
36157                <name>MAX_CUR_30V</name>
36158                <description>Maximum Current for 3.0V
36159This bit specifies the Maximum Current for 3.0V VDD1 power
36160supply for the card.
36161- 0: Get information through another method
36162- 1: 4mA
36163- 2: 8mA
36164- 3: 13mA
36165- .......
36166- 255: 1020mA</description>
36167                <bitRange>[15:8]</bitRange>
36168                <access>read-only</access>
36169              </field>
36170              <field>
36171                <name>MAX_CUR_18V</name>
36172                <description>Maximum Current for 1.8V
36173This bit specifies the Maximum Current for 1.8V VDD1 power
36174supply for the card.
36175- 0: Get information through another method
36176- 1: 4mA
36177- 2: 8mA
36178- 3: 13mA
36179- .......
36180- 255: 1020mA</description>
36181                <bitRange>[23:16]</bitRange>
36182                <access>read-only</access>
36183              </field>
36184            </fields>
36185          </register>
36186          <register>
36187            <name>CURR_CAPABILITIES2_R</name>
36188            <description>Maximum Current Capabilities Register - 32 to 63</description>
36189            <addressOffset>0x4C</addressOffset>
36190            <size>32</size>
36191            <access>read-only</access>
36192            <resetValue>0x0</resetValue>
36193            <resetMask>0xFF</resetMask>
36194            <fields>
36195              <field>
36196                <name>MAX_CUR_VDD2_18V</name>
36197                <description>Maximum Current for 1.8V VDD2
36198This bit specifies the Maximum Current for 1.8V VDD2 power
36199supply for the UHS-II card.
36200- 0: Get information through another method
36201- 1: 4mA
36202- 2: 8mA
36203- 3: 13mA
36204- .......
36205- 255: 1020mA</description>
36206                <bitRange>[7:0]</bitRange>
36207                <access>read-only</access>
36208              </field>
36209            </fields>
36210          </register>
36211          <register>
36212            <name>FORCE_AUTO_CMD_STAT_R</name>
36213            <description>Force Event Register for Auto CMD Error Status register</description>
36214            <addressOffset>0x50</addressOffset>
36215            <size>16</size>
36216            <access>write-only</access>
36217            <resetValue>0x0</resetValue>
36218            <resetMask>0xBF</resetMask>
36219            <fields>
36220              <field>
36221                <name>FORCE_AUTO_CMD12_NOT_EXEC</name>
36222                <description>Force Event for Auto CMD12 Not Executed
36223Values:
36224- 0x1 (TRUE): Auto CMD12 Not Executed Status is set
36225- 0x0 (FALSE): Not Affected</description>
36226                <bitRange>[0:0]</bitRange>
36227                <access>write-only</access>
36228              </field>
36229              <field>
36230                <name>FORCE_AUTO_CMD_TOUT_ERR</name>
36231                <description>Force Event for Auto CMD Timeout Error
36232Values:
36233- 0x1 (TRUE): Auto CMD Timeout Error Status is set
36234- 0x0 (FALSE): Not Affected</description>
36235                <bitRange>[1:1]</bitRange>
36236                <access>write-only</access>
36237              </field>
36238              <field>
36239                <name>FORCE_AUTO_CMD_CRC_ERR</name>
36240                <description>Force Event for Auto CMD CRC Error
36241Values:
36242- 0x1 (TRUE): Auto CMD CRC Error Status is set
36243- 0x0 (FALSE): Not Affected</description>
36244                <bitRange>[2:2]</bitRange>
36245                <access>write-only</access>
36246              </field>
36247              <field>
36248                <name>FORCE_AUTO_CMD_EBIT_ERR</name>
36249                <description>Force Event for Auto CMD End Bit Error
36250Values:
36251- 0x1 (TRUE): Auto CMD End Bit Error Status is set
36252- 0x0 (FALSE): Not Affected</description>
36253                <bitRange>[3:3]</bitRange>
36254                <access>write-only</access>
36255              </field>
36256              <field>
36257                <name>FORCE_AUTO_CMD_IDX_ERR</name>
36258                <description>Force Event for Auto CMD Index Error
36259Values:
36260- 0x1 (TRUE): Auto CMD Index Error Status is set
36261- 0x0 (FALSE): Not Affected</description>
36262                <bitRange>[4:4]</bitRange>
36263                <access>write-only</access>
36264              </field>
36265              <field>
36266                <name>FORCE_AUTO_CMD_RESP_ERR</name>
36267                <description>Force Event for Auto CMD Response Error
36268Values:
36269- 0x1 (TRUE): Auto CMD Response Error Status is set
36270- 0x0 (FALSE): Not Affected</description>
36271                <bitRange>[5:5]</bitRange>
36272                <access>write-only</access>
36273              </field>
36274              <field>
36275                <name>FORCE_CMD_NOT_ISSUED_AUTO_CMD12</name>
36276                <description>Force Event for Command Not Issued By Auto CMD12 Error
36277Values:
36278- 0x1 (TRUE): Command Not Issued By Auto CMD12 Error
36279Status is set
36280- 0x0 (FALSE): Not Affected</description>
36281                <bitRange>[7:7]</bitRange>
36282                <access>write-only</access>
36283              </field>
36284            </fields>
36285          </register>
36286          <register>
36287            <name>FORCE_ERROR_INT_STAT_R</name>
36288            <description>Force Event Register for Error Interrupt Status</description>
36289            <addressOffset>0x52</addressOffset>
36290            <size>16</size>
36291            <access>read-write</access>
36292            <resetValue>0x0</resetValue>
36293            <resetMask>0xFFFF</resetMask>
36294            <fields>
36295              <field>
36296                <name>FORCE_CMD_TOUT_ERR</name>
36297                <description>Force Event for Command Timeout Error (SD/eMMC Mode
36298only)
36299Values:
36300- 0x0 (FALSE): Not Affected
36301- 0x1 (TRUE): Command Timeout Error Status is set</description>
36302                <bitRange>[0:0]</bitRange>
36303                <access>read-write</access>
36304              </field>
36305              <field>
36306                <name>FORCE_CMD_CRC_ERR</name>
36307                <description>Force Event for Command CRC Error (SD/eMMC Mode
36308only)
36309Values:
36310- 0x0 (FALSE): Not Affected
36311- 0x1 (TRUE): Command CRC Error Status is set</description>
36312                <bitRange>[1:1]</bitRange>
36313                <access>read-write</access>
36314              </field>
36315              <field>
36316                <name>FORCE_CMD_END_BIT_ERR</name>
36317                <description>Force Event for Command End Bit Error (SD/eMMC Mode
36318only)
36319Values:
36320- 0x0 (FALSE): Not Affected
36321- 0x1 (TRUE): Command End Bit Error Status is set</description>
36322                <bitRange>[2:2]</bitRange>
36323                <access>read-write</access>
36324              </field>
36325              <field>
36326                <name>FORCE_CMD_IDX_ERR</name>
36327                <description>Force Event for Command Index Error (SD/eMMC Mode
36328only)
36329Values:
36330- 0x0 (FALSE): Not Affected
36331- 0x1 (TRUE): Command Index Error Status is set</description>
36332                <bitRange>[3:3]</bitRange>
36333                <access>read-write</access>
36334              </field>
36335              <field>
36336                <name>FORCE_DATA_TOUT_ERR</name>
36337                <description>Force Event for Data Timeout Error (SD/eMMC Mode only)
36338Values:
36339- 0x0 (FALSE): Not Affected
36340- 0x1 (TRUE): Data Timeout Error Status is set</description>
36341                <bitRange>[4:4]</bitRange>
36342                <access>read-write</access>
36343              </field>
36344              <field>
36345                <name>FORCE_DATA_CRC_ERR</name>
36346                <description>Force Event for Data CRC Error (SD/eMMC Mode only)
36347Values:
36348- 0x0 (FALSE): Not Affected
36349- 0x1 (TRUE): Data CRC Error Status is set</description>
36350                <bitRange>[5:5]</bitRange>
36351                <access>read-write</access>
36352              </field>
36353              <field>
36354                <name>FORCE_DATA_END_BIT_ERR</name>
36355                <description>Force Event for Data End Bit Error (SD/eMMC Mode only)
36356Values:
36357- 0x0 (FALSE): Not Affected
36358- 0x1 (TRUE): Data End Bit Error Status is set</description>
36359                <bitRange>[6:6]</bitRange>
36360                <access>read-write</access>
36361              </field>
36362              <field>
36363                <name>FORCE_CUR_LMT_ERR</name>
36364                <description>Force Event for Current Limit Error
36365Values:
36366- 0x0 (FALSE): Not Affected
36367- 0x1 (TRUE): Current Limit Error Status is set</description>
36368                <bitRange>[7:7]</bitRange>
36369                <access>read-write</access>
36370              </field>
36371              <field>
36372                <name>FORCE_AUTO_CMD_ERR</name>
36373                <description>Force Event for Auto CMD Error (SD/eMMC Mode only)
36374Values:
36375- 0x0 (FALSE): Not Affected
36376- 0x1 (TRUE): Auto CMD Error Status is set</description>
36377                <bitRange>[8:8]</bitRange>
36378                <access>read-write</access>
36379              </field>
36380              <field>
36381                <name>FORCE_ADMA_ERR</name>
36382                <description>Force Event for ADMA Error
36383Values:
36384- 0x0 (FALSE): Not Affected
36385- 0x1 (TRUE): ADMA Error Status is set</description>
36386                <bitRange>[9:9]</bitRange>
36387                <access>read-write</access>
36388              </field>
36389              <field>
36390                <name>FORCE_TUNING_ERR</name>
36391                <description>Force Event for Tuning Error (UHS-I Mode only)
36392Values:
36393- 0x0 (FALSE): Not Affected
36394- 0x1 (TRUE): Tuning Error Status is set</description>
36395                <bitRange>[10:10]</bitRange>
36396                <access>read-write</access>
36397              </field>
36398              <field>
36399                <name>FORCE_RESP_ERR</name>
36400                <description>Force Event for Response Error (SD Mode only)
36401Values:
36402- 0x0 (FALSE): Not Affected
36403- 0x1 (TRUE): Response Error Status is set</description>
36404                <bitRange>[11:11]</bitRange>
36405                <access>read-write</access>
36406              </field>
36407              <field>
36408                <name>FORCE_BOOT_ACK_ERR</name>
36409                <description>Force Event for Boot Ack error
36410Values:
36411- 0x0 (FALSE): Not Affected
36412- 0x1 (TRUE): Boot ack Error Status is set</description>
36413                <bitRange>[12:12]</bitRange>
36414                <access>read-write</access>
36415              </field>
36416              <field>
36417                <name>FORCE_VENDOR_ERR1</name>
36418                <description>N/A</description>
36419                <bitRange>[13:13]</bitRange>
36420                <access>read-write</access>
36421              </field>
36422              <field>
36423                <name>FORCE_VENDOR_ERR2</name>
36424                <description>N/A</description>
36425                <bitRange>[14:14]</bitRange>
36426                <access>read-write</access>
36427              </field>
36428              <field>
36429                <name>FORCE_VENDOR_ERR3</name>
36430                <description>N/A</description>
36431                <bitRange>[15:15]</bitRange>
36432                <access>read-write</access>
36433              </field>
36434            </fields>
36435          </register>
36436          <register>
36437            <name>ADMA_ERR_STAT_R</name>
36438            <description>ADMA Error Status Register</description>
36439            <addressOffset>0x54</addressOffset>
36440            <size>8</size>
36441            <access>read-only</access>
36442            <resetValue>0x0</resetValue>
36443            <resetMask>0x7</resetMask>
36444            <fields>
36445              <field>
36446                <name>ADMA_ERR_STATES</name>
36447                <description>ADMA Error States
36448These bits indicate the state of ADMA when an error occurs
36449during ADMA data transfer.
36450Values:
36451- 0x0 (ST_STOP): Stop DMA - SYS_ADR register points to
36452a location next to the error descriptor
36453- 0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register
36454points to the error descriptor
36455- 0x2 (UNUSED): Never set this state
36456- 0x3 (ST_TFR): Transfer Data - SYS_ADR register points
36457to a location next to the error descriptor</description>
36458                <bitRange>[1:0]</bitRange>
36459                <access>read-only</access>
36460              </field>
36461              <field>
36462                <name>ADMA_LEN_ERR</name>
36463                <description>ADMA Length Mismatch Error States
36464This error occurs in the following instances:
36465- While the Block Count Enable is being set, the total data
36466length specified by the Descriptor table is different from
36467that specified by the Block Count and Block Length
36468- When the total data length cannot be divided by the block
36469length
36470Values:
36471- 0x0 (NO_ERR): No Error
36472- 0x1 (ERROR): Error</description>
36473                <bitRange>[2:2]</bitRange>
36474                <access>read-only</access>
36475              </field>
36476            </fields>
36477          </register>
36478          <register>
36479            <name>ADMA_SA_LOW_R</name>
36480            <description>ADMA System Address Register - Low</description>
36481            <addressOffset>0x58</addressOffset>
36482            <size>32</size>
36483            <access>read-write</access>
36484            <resetValue>0x0</resetValue>
36485            <resetMask>0xFFFFFFFF</resetMask>
36486            <fields>
36487              <field>
36488                <name>ADMA_SA_LOW</name>
36489                <description>ADMA System Address
36490These bits indicate the lower 32 bits of the ADMA system
36491address.
36492- SDMA: If Host Version 4 Enable is set to 1, this register
36493stores the system address of the data location
36494- ADMA2: This register stores the byte address of the
36495executing command of the descriptor table
36496- ADMA3: This register is set by ADMA3. ADMA2
36497increments the address of this register that points to the
36498next line, every time a Descriptor line is fetched.</description>
36499                <bitRange>[31:0]</bitRange>
36500                <access>read-write</access>
36501              </field>
36502            </fields>
36503          </register>
36504          <register>
36505            <name>ADMA_ID_LOW_R</name>
36506            <description>ADMA3 Integrated Descriptor Address Register - Low</description>
36507            <addressOffset>0x78</addressOffset>
36508            <size>32</size>
36509            <access>read-write</access>
36510            <resetValue>0x0</resetValue>
36511            <resetMask>0xFFFFFFFF</resetMask>
36512            <fields>
36513              <field>
36514                <name>ADMA_ID_LOW</name>
36515                <description>ADMA Integrated Descriptor Address
36516These bits indicate the lower 32-bit of the ADMA Integrated
36517Descriptor address. The start address of Integrated
36518Descriptor is set to these register bits. The ADMA3 fetches
36519one Descriptor Address and increments these bits to indicate
36520the next Descriptor address.</description>
36521                <bitRange>[31:0]</bitRange>
36522                <access>read-write</access>
36523              </field>
36524            </fields>
36525          </register>
36526          <register>
36527            <name>HOST_CNTRL_VERS_R</name>
36528            <description>Host Controller Version</description>
36529            <addressOffset>0xFE</addressOffset>
36530            <size>16</size>
36531            <access>read-only</access>
36532            <resetValue>0x5</resetValue>
36533            <resetMask>0xFFFF</resetMask>
36534            <fields>
36535              <field>
36536                <name>SPEC_VERSION_NUM</name>
36537                <description>N/A</description>
36538                <bitRange>[7:0]</bitRange>
36539                <access>read-only</access>
36540              </field>
36541              <field>
36542                <name>VENDOR_VERSION_NUM</name>
36543                <description>N/A</description>
36544                <bitRange>[15:8]</bitRange>
36545                <access>read-only</access>
36546              </field>
36547            </fields>
36548          </register>
36549          <register>
36550            <name>CQVER</name>
36551            <description>Command Queuing Version register</description>
36552            <addressOffset>0x180</addressOffset>
36553            <size>32</size>
36554            <access>read-only</access>
36555            <resetValue>0x510</resetValue>
36556            <resetMask>0xFFF</resetMask>
36557            <fields>
36558              <field>
36559                <name>EMMC_VER_SUFFIX</name>
36560                <description>This bit indicates the eMMC version suffix (2nd digit right of
36561decimal point) in BCD format.</description>
36562                <bitRange>[3:0]</bitRange>
36563                <access>read-only</access>
36564              </field>
36565              <field>
36566                <name>EMMC_VER_MINOR</name>
36567                <description>This bit indicates the eMMC minor version (1st digit right of
36568decimal point) in BCD format.</description>
36569                <bitRange>[7:4]</bitRange>
36570                <access>read-only</access>
36571              </field>
36572              <field>
36573                <name>EMMC_VER_MAJOR</name>
36574                <description>This bit indicates the eMMC major version (1st digit left of
36575decimal point) in BCD format.</description>
36576                <bitRange>[11:8]</bitRange>
36577                <access>read-only</access>
36578              </field>
36579            </fields>
36580          </register>
36581          <register>
36582            <name>CQCAP</name>
36583            <description>Command Queuing Capabilities register</description>
36584            <addressOffset>0x184</addressOffset>
36585            <size>32</size>
36586            <access>read-only</access>
36587            <resetValue>0x30C8</resetValue>
36588            <resetMask>0x1000F3FF</resetMask>
36589            <fields>
36590              <field>
36591                <name>ITCFVAL</name>
36592                <description>Internal Timer Clock Frequency Value (ITCFVAL)
36593This field scales the frequency of the timer clock provided by
36594ITCFMUL. The Final clock frequency of actual timer clock is
36595calculated as ITCFVAL* ITCFMUL.</description>
36596                <bitRange>[9:0]</bitRange>
36597                <access>read-only</access>
36598              </field>
36599              <field>
36600                <name>ITCFMUL</name>
36601                <description>N/A</description>
36602                <bitRange>[15:12]</bitRange>
36603                <access>read-only</access>
36604              </field>
36605              <field>
36606                <name>CRYPTO_SUPPORT</name>
36607                <description>Crypto Support
36608This bit indicates whether the Host Controller supports
36609cryptographic operations.
36610Values:
36611- 0x0 (FALSE): Crypto not Supported
36612- 0x1 (TRUE): Crypto Supported</description>
36613                <bitRange>[28:28]</bitRange>
36614                <access>read-only</access>
36615              </field>
36616            </fields>
36617          </register>
36618          <register>
36619            <name>CQCFG</name>
36620            <description>Command Queuing Configuration register</description>
36621            <addressOffset>0x188</addressOffset>
36622            <size>32</size>
36623            <access>read-write</access>
36624            <resetValue>0x0</resetValue>
36625            <resetMask>0x1103</resetMask>
36626            <fields>
36627              <field>
36628                <name>CQ_EN</name>
36629                <description>Enable command queuing engine (CQE).
36630When CQE is disable, the software controls the eMMC bus
36631using the registers between the addresses 0x000 to 0x1FF.
36632Before the software writes to this bit, the software verifies
36633that the eMMC host controller is in idle state and there are no
36634ongoing commands or data transfers. When software wants
36635to exit command queuing mode, it clears all previous tasks (if
36636any) before setting this bit to 0.
36637Values:
36638- 0x1 (CQE_ENABLE): Enable command queuing
36639- 0x0 (CQE_DISABLE): Disable command queuing</description>
36640                <bitRange>[0:0]</bitRange>
36641                <access>read-write</access>
36642              </field>
36643              <field>
36644                <name>CR_GENERAL_EN</name>
36645                <description>N/A</description>
36646                <bitRange>[1:1]</bitRange>
36647                <access>read-write</access>
36648              </field>
36649              <field>
36650                <name>TASK_DESC_SIZE</name>
36651                <description>Bit Value Description
36652This bit indicates the size of task descriptor used in host
36653memory. This bit can only be configured when Command
36654Queuing Enable bit is 0 (command queuing is disabled).
36655Values:
36656- 0x1 (TASK_DESC_128b): Task descriptor size is 128 bits
36657- 0x0 (TASK_DESC_64b): Task descriptor size is 64 bits</description>
36658                <bitRange>[8:8]</bitRange>
36659                <access>read-write</access>
36660              </field>
36661              <field>
36662                <name>DCMD_EN</name>
36663                <description>This bit indicates to the hardware whether the Task
36664Descriptor in slot #31 of the TDL is a data transfer descriptor
36665or a direct-command descriptor. CQE uses this bit when a
36666task is issued in slot #31, to determine how to decode the
36667Task Descriptor.
36668Values:
36669- 0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot
36670#31 is a DCMD Task Descriptor
36671- 0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot
36672#31 is a data Transfer Task Descriptor</description>
36673                <bitRange>[12:12]</bitRange>
36674                <access>read-write</access>
36675              </field>
36676            </fields>
36677          </register>
36678          <register>
36679            <name>CQCTL</name>
36680            <description>Command Queuing Control register</description>
36681            <addressOffset>0x18C</addressOffset>
36682            <size>32</size>
36683            <access>read-write</access>
36684            <resetValue>0x0</resetValue>
36685            <resetMask>0x101</resetMask>
36686            <fields>
36687              <field>
36688                <name>HALT</name>
36689                <description>Halt request and resume
36690Values:
36691- 0x1 (HALT_CQE): Software writes 1 to this bit when it
36692wants to acquire software control over the eMMC bus and
36693to disable CQE from issuing command on the bus.
36694For example, issuing a Discard Task command
36695(CMDQ_TASK_MGMT). When the software writes 1, CQE
36696completes the ongoing task (if any in progress). After the
36697task is completed and the CQE is in idle state, CQE does not
36698issue new commands and indicates to the software by
36699setting this bit to 1. The software can poll on this bit until it is
36700set to 1 and only then send commands on the eMMC bus.
36701- 0x0 (RESUME_CQE): Software writes 0 to this bit to exit
36702from the halt state and resume CQE activity.</description>
36703                <bitRange>[0:0]</bitRange>
36704                <access>read-write</access>
36705              </field>
36706              <field>
36707                <name>CLR_ALL_TASKS</name>
36708                <description>Clear all tasks
36709This bit can only be written when the controller is halted. This
36710bit does not clear tasks in the device. The software has to
36711use the CMDQ_TASK_MGMT command to clear device's
36712queue.
36713Values:
36714- 0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the
36715controller
36716- 0x0 (NO_EFFECT): Programming 0 has no effect</description>
36717                <bitRange>[8:8]</bitRange>
36718                <access>read-write</access>
36719              </field>
36720            </fields>
36721          </register>
36722          <register>
36723            <name>CQIS</name>
36724            <description>Command Queuing Interrupt Status register</description>
36725            <addressOffset>0x190</addressOffset>
36726            <size>32</size>
36727            <access>read-write</access>
36728            <resetValue>0x0</resetValue>
36729            <resetMask>0x3F</resetMask>
36730            <fields>
36731              <field>
36732                <name>HAC</name>
36733                <description>Halt complete interrupt
36734This status bit is asserted (only if CQISE.HAC_STE=1) when
36735halt bit in the CQCTL register transitions from 0 to 1
36736indicating that the host controller has completed its current
36737ongoing task and has entered halt state. A value of 1 clears
36738this status bit.
36739Values:
36740- 0x1 (SET): HAC Interrupt is set
36741- 0x0 (NOTSET): HAC Interrupt is not set</description>
36742                <bitRange>[0:0]</bitRange>
36743                <access>read-write</access>
36744              </field>
36745              <field>
36746                <name>TCC</name>
36747                <description>Task complete interrupt
36748This status bit is asserted (if CQISE.TCC_STE=1) when at
36749least one of the following conditions are met:
36750- A task is completed and the INT bit is set in its Task
36751Descriptor
36752- Interrupt caused by Interrupt Coalescing logic due to
36753timeout
36754- Interrupt Coalescing logic reached the configured
36755threshold
36756A value of 1 clears this status bit
36757Values:
36758- 0x1 (SET): TCC Interrupt is set
36759- 0x0 (NOTSET): TCC Interrupt is not set</description>
36760                <bitRange>[1:1]</bitRange>
36761                <access>read-write</access>
36762              </field>
36763              <field>
36764                <name>RED</name>
36765                <description>Response error detected interrupt
36766This status bit is asserted (if CQISE.RED_STE=1) when a
36767response is received with an error bit set in the device status
36768field. Configure the CQRMEM register to identify device
36769status bit fields that may trigger an interrupt and that are
36770masked. A value of 1 clears this status bit.
36771Values:
36772- 0x1 (SET): RED Interrupt is set
36773- 0x0 (NOTSET): RED Interrupt is not set</description>
36774                <bitRange>[2:2]</bitRange>
36775                <access>read-write</access>
36776              </field>
36777              <field>
36778                <name>TCL</name>
36779                <description>Task cleared interrupt
36780This status bit is asserted (if CQISE.TCL_STE=1) when a
36781task clear operation is completed by CQE. The completed
36782task clear operation is either an individual task clear (by
36783writing CQTCLR) or clearing of all tasks (by writing CQCTL).
36784A value of 1 clears this status bit.
36785Values:
36786- 0x1 (SET): TCL Interrupt is set
36787- 0x0 (NOTSET): TCL Interrupt is not set</description>
36788                <bitRange>[3:3]</bitRange>
36789                <access>read-write</access>
36790              </field>
36791              <field>
36792                <name>GCE</name>
36793                <description>N/A</description>
36794                <bitRange>[4:4]</bitRange>
36795                <access>read-write</access>
36796              </field>
36797              <field>
36798                <name>ICCE</name>
36799                <description>N/A</description>
36800                <bitRange>[5:5]</bitRange>
36801                <access>read-write</access>
36802              </field>
36803            </fields>
36804          </register>
36805          <register>
36806            <name>CQISE</name>
36807            <description>Command Queuing Interrupt Status Enable register</description>
36808            <addressOffset>0x194</addressOffset>
36809            <size>32</size>
36810            <access>read-write</access>
36811            <resetValue>0x0</resetValue>
36812            <resetMask>0x3F</resetMask>
36813            <fields>
36814              <field>
36815                <name>HAC_STE</name>
36816                <description>Halt complete interrupt status enable
36817Values:
36818- 0x1 (INT_STS_ENABLE): CQIS.HAC is set when its
36819interrupt condition is active
36820- 0x0 (INT_STS_DISABLE): CQIS.HAC is disabled</description>
36821                <bitRange>[0:0]</bitRange>
36822                <access>read-write</access>
36823              </field>
36824              <field>
36825                <name>TCC_STE</name>
36826                <description>Task complete interrupt status enable
36827Values:
36828- 0x1 (INT_STS_ENABLE): CQIS.TCC is set when its
36829interrupt condition is active
36830- 0x0 (INT_STS_DISABLE): CQIS.TCC is disabled</description>
36831                <bitRange>[1:1]</bitRange>
36832                <access>read-write</access>
36833              </field>
36834              <field>
36835                <name>RED_STE</name>
36836                <description>Response error detected interrupt status enable
36837Values:
36838- 0x1 (INT_STS_ENABLE): CQIS.RED is set when its
36839interrupt condition is active
36840- 0x0 (INT_STS_DISABLE): CQIS.RED is disabled</description>
36841                <bitRange>[2:2]</bitRange>
36842                <access>read-write</access>
36843              </field>
36844              <field>
36845                <name>TCL_STE</name>
36846                <description>Task cleared interrupt status enable
36847Values:
36848- 0x1 (INT_STS_ENABLE): CQIS.TCL is set when its
36849interrupt condition is active
36850- 0x0 (INT_STS_DISABLE): CQIS.TCL is disabled</description>
36851                <bitRange>[3:3]</bitRange>
36852                <access>read-write</access>
36853              </field>
36854              <field>
36855                <name>GCE_STE</name>
36856                <description>General Crypto Error interrupt status enable
36857Values:
36858- 0x1 (INT_STS_ENABLE): CQIS.GCE is set when its
36859interrupt condition is active
36860- 0x0 (INT_STS_DISABLE): CQIS.GCE is disabled</description>
36861                <bitRange>[4:4]</bitRange>
36862                <access>read-write</access>
36863              </field>
36864              <field>
36865                <name>ICCE_STE</name>
36866                <description>Invalid Crypto Configuration Error interrupt status enable
36867Values:
36868- 0x1 (INT_STS_ENABLE): CQIS.ICCE is set when its
36869interrupt condition is active
36870- 0x0 (INT_STS_DISABLE): CQIS.ICCE is disabled</description>
36871                <bitRange>[5:5]</bitRange>
36872                <access>read-write</access>
36873              </field>
36874            </fields>
36875          </register>
36876          <register>
36877            <name>CQISGE</name>
36878            <description>Command Queuing Interrupt signal enable register</description>
36879            <addressOffset>0x198</addressOffset>
36880            <size>32</size>
36881            <access>read-write</access>
36882            <resetValue>0x0</resetValue>
36883            <resetMask>0x3F</resetMask>
36884            <fields>
36885              <field>
36886                <name>HAC_SGE</name>
36887                <description>Halt complete interrupt signal enable
36888Values:
36889- 0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal
36890generation is active
36891- 0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal
36892generation is disabled</description>
36893                <bitRange>[0:0]</bitRange>
36894                <access>read-write</access>
36895              </field>
36896              <field>
36897                <name>TCC_SGE</name>
36898                <description>Task complete interrupt signal enable
36899Values:
36900- 0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal
36901generation is active
36902- 0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal
36903generation is disabled</description>
36904                <bitRange>[1:1]</bitRange>
36905                <access>read-write</access>
36906              </field>
36907              <field>
36908                <name>RED_SGE</name>
36909                <description>Response error detected interrupt signal enable
36910Values:
36911- 0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal
36912generation is active
36913- 0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal
36914generation is disabled</description>
36915                <bitRange>[2:2]</bitRange>
36916                <access>read-write</access>
36917              </field>
36918              <field>
36919                <name>TCL_SGE</name>
36920                <description>Task cleared interrupt signal enable
36921Values:
36922- 0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal
36923generation is active
36924- 0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal
36925generation is disabled</description>
36926                <bitRange>[3:3]</bitRange>
36927                <access>read-write</access>
36928              </field>
36929              <field>
36930                <name>GCE_SGE</name>
36931                <description>General Crypto Error interrupt signal enable
36932Values:
36933- 0x1 (INT_SIG_ENABLE): CQIS.GCE interrupt signal
36934generation is active
36935- 0x0 (INT_SIG_DISABLE): CQIS.GCE interrupt signal
36936generation is disabled</description>
36937                <bitRange>[4:4]</bitRange>
36938                <access>read-write</access>
36939              </field>
36940              <field>
36941                <name>ICCE_SGE</name>
36942                <description>Invalid Crypto Configuration Error interrupt signal enable
36943Values:
36944- 0x1 (INT_SIG_ENABLE): CQIS.ICCE interrupt signal
36945generation is active
36946- 0x0 (INT_SIG_DISABLE): CQIS.ICCE interrupt signal
36947generation is disabled</description>
36948                <bitRange>[5:5]</bitRange>
36949                <access>read-write</access>
36950              </field>
36951            </fields>
36952          </register>
36953          <register>
36954            <name>CQIC</name>
36955            <description>Command Queuing Interrupt Coalescing register</description>
36956            <addressOffset>0x19C</addressOffset>
36957            <size>32</size>
36958            <access>read-write</access>
36959            <resetValue>0x0</resetValue>
36960            <resetMask>0x80119FFF</resetMask>
36961            <fields>
36962              <field>
36963                <name>TOUT_VAL</name>
36964                <description>Interrupt Coalescing Timeout Value
36965Software uses this field to configure the maximum time
36966allowed between the completion of a task on the bus and the
36967generation of an interrupt.
36968Timer Operation: The timer is reset by software during the
36969interrupt service routine. It starts running when the first data
36970transfer task with INT=0 is completed, after the timer was
36971reset. When the timer reaches the value configured in
36972ICTOVAL field, it generates an interrupt and stops.
36973The timer's unit is equal to 1024 clock periods of the clock
36974whose frequency is specified in the Internal Timer Clock
36975Frequency field CQCAP register.
36976- 0x0: Timer is disabled. Timeout-based interrupt is not
36977generated
36978- 0x1: Timeout on 01x1024 cycles of timer clock frequency
36979- 0x2: Timeout on 02x1024 cycles of timer clock frequency
36980- ........
36981- 0x7f: Timeout on 127x1024 cycles of timer clock
36982frequency
36983In order to write to this field, the TOUT_VAL_WEN bit must
36984be set at the same write operation.</description>
36985                <bitRange>[6:0]</bitRange>
36986                <access>read-write</access>
36987              </field>
36988              <field>
36989                <name>TOUT_VAL_WEN</name>
36990                <description>When software writes 1 to this bit, the value TOUT_VAL is
36991updated with the contents written on the same cycle.
36992Values:
36993- 0x1 (WEN_SET): Sets TOUT_VAL_WEN
36994- 0x0 (WEN_CLR): clears TOUT_VAL_WEN</description>
36995                <bitRange>[7:7]</bitRange>
36996                <access>write-only</access>
36997              </field>
36998              <field>
36999                <name>INTC_TH</name>
37000                <description>Interrupt Coalescing Counter Threshold filed
37001Software uses this field to configure the number of task
37002completions (only tasks with INT=0 in the Task Descriptor),
37003which are required in order to generate an interrupt.
37004Counter Operation: As data transfer tasks with INT=0
37005complete, they are counted by CQE. The counter is reset by
37006software during the interrupt service routine. The counter
37007stops counting when it reaches the value configured in
37008INTC_TH, and generates interrupt.
37009- 0x0: Interrupt coalescing feature disabled
37010- 0x1: Interrupt coalescing interrupt generated after 1 task
37011when INT=0 completes
37012- 0x2: Interrupt coalescing interrupt generated after 2 tasks
37013when INT=0 completes
37014- ........
37015- 0x1f: Interrupt coalescing interrupt generated after 31
37016tasks when INT=0 completes
37017To write to this field, the INTC_TH_WEN bit must be set
37018during the same write operation.</description>
37019                <bitRange>[12:8]</bitRange>
37020                <access>write-only</access>
37021              </field>
37022              <field>
37023                <name>INTC_TH_WEN</name>
37024                <description>Interrupt Coalescing Counter Threshold Write Enable
37025When software writes 1 to this bit, the value INTC_TH is
37026updated with the contents written on the same cycle.
37027Values:
37028- 0x1 (WEN_SET): Sets INTC_TH_WEN
37029- 0x0 (WEN_CLR): Clears INTC_TH_WEN</description>
37030                <bitRange>[15:15]</bitRange>
37031                <access>write-only</access>
37032              </field>
37033              <field>
37034                <name>INTC_RST</name>
37035                <description>Counter and Timer Reset
37036When host driver writes 1, the interrupt coalescing timer and
37037counter are reset.
37038Values:
37039- 0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer
37040and counter are reset
37041- 0x0 (NO_EFFECT): No Effect</description>
37042                <bitRange>[16:16]</bitRange>
37043                <access>write-only</access>
37044              </field>
37045              <field>
37046                <name>INTC_STAT</name>
37047                <description>Interrupt Coalescing Status Bit
37048This bit indicates to the software whether any tasks (with
37049INT=0) have completed and counted towards interrupt
37050coalescing (that is, this is set if and only if INTC counter &gt; 0).
37051Values:
37052- 0x1 (INTC_ATLEAST1_COMP): At least one INT0 task
37053completion has been counted (INTC counter &gt; 0)
37054- 0x0 (INTC_NO_TASK_COMP): INT0 Task completions
37055have not occurred since last counter reset (INTC counter
37056== 0)</description>
37057                <bitRange>[20:20]</bitRange>
37058                <access>read-only</access>
37059              </field>
37060              <field>
37061                <name>INTC_EN</name>
37062                <description>Interrupt Coalescing Enable Bit
37063Values:
37064- 0x1 (ENABLE_INT_COALESCING): Interrupt coalescing
37065mechanism is active. Interrupts are counted and timed,
37066and coalesced interrupts are generated
37067- 0x0 (DISABLE_INT_COALESCING): Interrupt coalescing
37068mechanism is disabled (Default).</description>
37069                <bitRange>[31:31]</bitRange>
37070                <access>read-write</access>
37071              </field>
37072            </fields>
37073          </register>
37074          <register>
37075            <name>CQTDLBA</name>
37076            <description>Command Queuing Task Descriptor List Base Address register</description>
37077            <addressOffset>0x1A0</addressOffset>
37078            <size>32</size>
37079            <access>read-write</access>
37080            <resetValue>0x0</resetValue>
37081            <resetMask>0xFFFFFFFF</resetMask>
37082            <fields>
37083              <field>
37084                <name>TDLBA</name>
37085                <description>This register stores the LSB bits (31:0) of the byte address of
37086the head of the Task Descriptor List in system memory.
37087The size of the task descriptor list is 32 * (Task Descriptor
37088size + Transfer Descriptor size) as configured by the host
37089driver. This address is set on 1 KB boundary. The lower 10
37090bits of this register are set to 0 by the software and are
37091ignored by CQE.</description>
37092                <bitRange>[31:0]</bitRange>
37093                <access>read-write</access>
37094              </field>
37095            </fields>
37096          </register>
37097          <register>
37098            <name>CQTDBR</name>
37099            <description>Command Queuing DoorBell register</description>
37100            <addressOffset>0x1A8</addressOffset>
37101            <size>32</size>
37102            <access>read-write</access>
37103            <resetValue>0x0</resetValue>
37104            <resetMask>0xFFFFFFFF</resetMask>
37105            <fields>
37106              <field>
37107                <name>DBR</name>
37108                <description>The software configures TDLBA and TDLBAU, and enable
37109CQE in CQCFG before using this register.
37110Writing 1 to bit n of this register triggers CQE to start
37111processing the task encoded in slot n of the TDL. Writing 0
37112by the software does not have any impact on the hardware,
37113and does not change the value of the register bit.
37114CQE always processes tasks according to the order
37115submitted to the list by CQTDBR write transactions. CQE
37116processes Data Transfer tasks by reading the Task
37117Descriptor and sending QUEUED_TASK_PARAMS (CMD44)
37118and QUEUED_TASK_ADDRESS (CMD45) commands to
37119the device. CQE processes DCMD tasks (in slot #31, when
37120enabled) by reading the Task Descriptor, and generating the
37121command encoded by its index and argument.
37122The corresponding bit is cleared to 0 by CQE in one of the
37123following events:
37124- A task execution is completed (with success or error).
37125- The task is cleared using CQTCLR register.
37126- All tasks are cleared using CQCTL register.
37127- CQE is disabled using CQCFG register.
37128Software may initiate multiple tasks at the same time (batch
37129submission) by writing 1 to multiple bits of this register in the
37130same transaction. In the case of batch submission, CQE
37131processes the tasks in order of the task index, starting with
37132the lowest index. If one or more tasks in the batch are
37133marked with QBR, the ordering of execution is based on said
37134processing order.</description>
37135                <bitRange>[31:0]</bitRange>
37136                <access>read-write</access>
37137              </field>
37138            </fields>
37139          </register>
37140          <register>
37141            <name>CQTCN</name>
37142            <description>Command Queuing TaskClear Notification register</description>
37143            <addressOffset>0x1AC</addressOffset>
37144            <size>32</size>
37145            <access>read-write</access>
37146            <resetValue>0x0</resetValue>
37147            <resetMask>0xFFFFFFFF</resetMask>
37148            <fields>
37149              <field>
37150                <name>TCN</name>
37151                <description>Task Completion Notification
37152Each of the 32 bits are bit mapped to the 32 tasks.
37153- Bit-N(1): Task-N has completed execution (with success
37154or errors)
37155- Bit-N(0): Task-N has not completed, could be pending or
37156not submitted.
37157On task completion, software may read this register to know
37158tasks that have completed. After reading this register,
37159software may clear the relevant bit fields by writing 1 to the
37160corresponding bits.</description>
37161                <bitRange>[31:0]</bitRange>
37162                <access>read-write</access>
37163              </field>
37164            </fields>
37165          </register>
37166          <register>
37167            <name>CQDQS</name>
37168            <description>Device queue status register</description>
37169            <addressOffset>0x1B0</addressOffset>
37170            <size>32</size>
37171            <access>read-only</access>
37172            <resetValue>0x0</resetValue>
37173            <resetMask>0xFFFFFFFF</resetMask>
37174            <fields>
37175              <field>
37176                <name>DQS</name>
37177                <description>Device Queue Status
37178Each of the 32 bits are bit mapped to the 32 tasks.
37179- Bit-N(1): Device has marked task N as ready for
37180execution
37181- Bit-N(0): Task-N is not ready for execution. This task
37182could be pending in device or not submitted.
37183Host controller updates this register with response of the
37184Device Queue Status command.</description>
37185                <bitRange>[31:0]</bitRange>
37186                <access>read-only</access>
37187              </field>
37188            </fields>
37189          </register>
37190          <register>
37191            <name>CQDPT</name>
37192            <description>Device pending tasks register</description>
37193            <addressOffset>0x1B4</addressOffset>
37194            <size>32</size>
37195            <access>read-only</access>
37196            <resetValue>0x0</resetValue>
37197            <resetMask>0xFFFFFFFF</resetMask>
37198            <fields>
37199              <field>
37200                <name>DPT</name>
37201                <description>Device-Pending Tasks
37202Each of the 32 bits are bit mapped to the 32 tasks.
37203- Bit-N(1): Task-N has been successfully queued into the
37204device and is awaiting execution
37205- Bit-N(0): Task-N is not yet queued.
37206Bit n of this register is set if and only if
37207QUEUED_TASK_PARAMS (CMD44) and
37208QUEUED_TASK_ADDRESS (CMD45) were sent for this
37209specific task and if this task has not been executed.
37210The controller sets this bit after receiving a successful
37211response for CMD45. CQE clears this bit after the task has
37212completed execution.
37213Software reads this register in the task-discard procedure to
37214determine if the task is queued in the device.</description>
37215                <bitRange>[31:0]</bitRange>
37216                <access>read-only</access>
37217              </field>
37218            </fields>
37219          </register>
37220          <register>
37221            <name>CQTCLR</name>
37222            <description>Command Queuing DoorBell register</description>
37223            <addressOffset>0x1B8</addressOffset>
37224            <size>32</size>
37225            <access>read-write</access>
37226            <resetValue>0x0</resetValue>
37227            <resetMask>0xFFFFFFFF</resetMask>
37228            <fields>
37229              <field>
37230                <name>TCLR</name>
37231                <description>Writing 1 to bit n of this register orders CQE to clear a task
37232that the software has previously issued.
37233This bit can only be written when CQE is in Halt state as
37234indicated in CQCFG register Halt bit. When software writes 1
37235to a bit in this register, CQE updates the value to 1, and
37236starts clearing the data structures related to the task. CQE
37237clears the bit fields (sets a value of 0) in CQTCLR and in
37238CQTDBR once the clear operation is complete. Software
37239must poll on the CQTCLR until it is cleared to verify that a
37240clear operation was done.</description>
37241                <bitRange>[31:0]</bitRange>
37242                <access>read-write</access>
37243              </field>
37244            </fields>
37245          </register>
37246          <register>
37247            <name>CQSSC1</name>
37248            <description>CQ Send Status Configuration 1 register</description>
37249            <addressOffset>0x1C0</addressOffset>
37250            <size>32</size>
37251            <access>read-write</access>
37252            <resetValue>0x11000</resetValue>
37253            <resetMask>0xFFFFF</resetMask>
37254            <fields>
37255              <field>
37256                <name>SQSCMD_IDLE_TMR</name>
37257                <description>This field configures the polling period to be used when
37258using periodic SEND_QUEUE_STATUS (CMD13) polling.
37259Periodic polling is used when tasks are pending in the
37260device, but no data transfer is in progress. When a
37261SEND_QUEUE_STATUS response indicates that no task is
37262ready for execution, CQE counts the configured time until it
37263issues the next SEND_QUEUE_STATUS.
37264Timer units are clock periods of the clock whose frequency is
37265specified in the Internal Timer Clock Frequency field CQCAP
37266register. The minimum value is 0001h (1 clock period) and
37267the maximum value is FFFFh (65535 clock periods).
37268For example, a CQCAP field value of 0 indicates a 19.2 MHz
37269clock frequency (period = 52.08 ns). If the setting in
37270CQSSC1.CIT is 1000h, the calculated polling period is
372714096*52.08 ns= 213.33 ns.
37272Should be programmed only when CQCFG.CQ_EN is '0'.</description>
37273                <bitRange>[15:0]</bitRange>
37274                <access>read-write</access>
37275              </field>
37276              <field>
37277                <name>SQSCMD_BLK_CNT</name>
37278                <description>This field indicates when SQS CMD is sent while data
37279transfer is in progress.
37280A value of 'n' indicates that CQE sends status command on
37281the CMD line, during the transfer of data block BLOCK_CNTn,
37282on the data lines, where BLOCK_CNT is the number of
37283blocks in the current transaction.
37284- 0x0: SEND_QUEUE_STATUS (CMD13) command is not
37285sent during the transaction. Instead, it is sent only when
37286the data lines are idle.
37287- 0x1: SEND_QUEUE_STATUS command is to be sent
37288during the last block of the transaction.
37289- 0x2: SEND_QUEUE_STATUS command when last 2
37290blocks are pending.
37291- 0x3: SEND_QUEUE_STATUS command when last 3
37292blocks are pending.
37293- ........
37294- 0xf: SEND_QUEUE_STATUS command when last 15
37295blocks are pending.
37296Should be programmed only when CQCFG.CQ_EN is '0'</description>
37297                <bitRange>[19:16]</bitRange>
37298                <access>read-write</access>
37299              </field>
37300            </fields>
37301          </register>
37302          <register>
37303            <name>CQSSC2</name>
37304            <description>CQ Send Status Configuration 2 register</description>
37305            <addressOffset>0x1C4</addressOffset>
37306            <size>32</size>
37307            <access>read-write</access>
37308            <resetValue>0x0</resetValue>
37309            <resetMask>0xFFFF</resetMask>
37310            <fields>
37311              <field>
37312                <name>SQSCMD_RCA</name>
37313                <description>This field provides CQE with the contents of the 16-bit RCA
37314field in SEND_QUEUE_STATUS (CMD13) command
37315argument.
37316CQE copies this field to bits 31:16 of the argument when
37317transmitting SEND_ QUEUE_STATUS (CMD13) command.</description>
37318                <bitRange>[15:0]</bitRange>
37319                <access>read-write</access>
37320              </field>
37321            </fields>
37322          </register>
37323          <register>
37324            <name>CQCRDCT</name>
37325            <description>Command response for direct command register</description>
37326            <addressOffset>0x1C8</addressOffset>
37327            <size>32</size>
37328            <access>read-only</access>
37329            <resetValue>0x0</resetValue>
37330            <resetMask>0xFFFFFFFF</resetMask>
37331            <fields>
37332              <field>
37333                <name>DCMD_RESP</name>
37334                <description>This register contains the response of the command
37335generated by the last direct command (DCMD) task that was
37336sent.
37337Contents of this register are valid only after bit 31 of
37338CQTDBR register is cleared by the controller.</description>
37339                <bitRange>[31:0]</bitRange>
37340                <access>read-only</access>
37341              </field>
37342            </fields>
37343          </register>
37344          <register>
37345            <name>CQRMEM</name>
37346            <description>Command response mode error mask register</description>
37347            <addressOffset>0x1D0</addressOffset>
37348            <size>32</size>
37349            <access>read-write</access>
37350            <resetValue>0xFDF9A080</resetValue>
37351            <resetMask>0xFFFFFFFF</resetMask>
37352            <fields>
37353              <field>
37354                <name>RESP_ERR_MASK</name>
37355                <description>The bits of this field are bit mapped to the device response.
37356This bit is used as an interrupt mask on the device status
37357filed that is received in R1/R1b responses.
37358- 1: When a R1/R1b response is received, with a bit i in the
37359device status set, a RED interrupt is generated.
37360- 0: When a R1/R1b response is received, bit i in the device
37361status is ignored.
37362The reset value of this register is set to trigger an interrupt on
37363all 'Error' type bits in the device status.
37364Note: Responses to CMD13 (SQS) encode the QSR so that
37365they are ignored by this logic.</description>
37366                <bitRange>[31:0]</bitRange>
37367                <access>read-write</access>
37368              </field>
37369            </fields>
37370          </register>
37371          <register>
37372            <name>CQTERRI</name>
37373            <description>CQ Task Error Information register</description>
37374            <addressOffset>0x1D4</addressOffset>
37375            <size>32</size>
37376            <access>read-only</access>
37377            <resetValue>0x0</resetValue>
37378            <resetMask>0x9F3F9F3F</resetMask>
37379            <fields>
37380              <field>
37381                <name>RESP_ERR_CMD_INDX</name>
37382                <description>This field captures the index of the command that was
37383executed on the command line when the error occurred.</description>
37384                <bitRange>[5:0]</bitRange>
37385                <access>read-only</access>
37386              </field>
37387              <field>
37388                <name>RESP_ERR_TASKID</name>
37389                <description>This field captures the ID of the task which was executed on
37390the command line when the error occurred.</description>
37391                <bitRange>[12:8]</bitRange>
37392                <access>read-only</access>
37393              </field>
37394              <field>
37395                <name>RESP_ERR_FIELDS_VALID</name>
37396                <description>This bit is updated when an error is detected while a
37397command transaction was in progress.
37398Values:
37399- 0x1 (SET): Response-related error is detected. Check
37400contents of RESP_ERR_TASKID and
37401RESP_ERR_CMD_INDX fields
37402- 0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID
37403and RESP_ERR_CMD_INDX</description>
37404                <bitRange>[15:15]</bitRange>
37405                <access>read-only</access>
37406              </field>
37407              <field>
37408                <name>TRANS_ERR_CMD_INDX</name>
37409                <description>This field captures the index of the command that was
37410executed and whose data transfer has errors.</description>
37411                <bitRange>[21:16]</bitRange>
37412                <access>read-only</access>
37413              </field>
37414              <field>
37415                <name>TRANS_ERR_TASKID</name>
37416                <description>This field captures the ID of the task that was executed and
37417whose data transfer has errors.</description>
37418                <bitRange>[28:24]</bitRange>
37419                <access>read-only</access>
37420              </field>
37421              <field>
37422                <name>TRANS_ERR_FIELDS_VALID</name>
37423                <description>This bit is updated when an error is detected while a data
37424transfer transaction was in progress.
37425Values:
37426- 0x1 (SET): data transfer related error detected. Check
37427contents of TRANS_ERR_TASKID and
37428TRANS_ERR_CMD_INDX fields
37429- 0x0 (NOT_SET): Ignore contents of
37430TRANS_ERR_TASKID and TRANS_ERR_CMD_INDX</description>
37431                <bitRange>[31:31]</bitRange>
37432                <access>read-only</access>
37433              </field>
37434            </fields>
37435          </register>
37436          <register>
37437            <name>CQCRI</name>
37438            <description>CQ Command response index</description>
37439            <addressOffset>0x1D8</addressOffset>
37440            <size>32</size>
37441            <access>read-only</access>
37442            <resetValue>0x0</resetValue>
37443            <resetMask>0x3F</resetMask>
37444            <fields>
37445              <field>
37446                <name>CMD_RESP_INDX</name>
37447                <description>Last Command Response index
37448This field stores the index of the last received command
37449response. Controller updates the value every time a
37450command response is received.</description>
37451                <bitRange>[5:0]</bitRange>
37452                <access>read-only</access>
37453              </field>
37454            </fields>
37455          </register>
37456          <register>
37457            <name>CQCRA</name>
37458            <description>CQ Command response argument register</description>
37459            <addressOffset>0x1DC</addressOffset>
37460            <size>32</size>
37461            <access>read-only</access>
37462            <resetValue>0x0</resetValue>
37463            <resetMask>0xFFFFFFFF</resetMask>
37464            <fields>
37465              <field>
37466                <name>CMD_RESP_ARG</name>
37467                <description>Last Command Response argument
37468This field stores the argument of the last received command
37469response. Controller updates the value every time a
37470command response is received.</description>
37471                <bitRange>[31:0]</bitRange>
37472                <access>read-only</access>
37473              </field>
37474            </fields>
37475          </register>
37476          <register>
37477            <name>MSHC_VER_ID_R</name>
37478            <description>MSHC version</description>
37479            <addressOffset>0x500</addressOffset>
37480            <size>32</size>
37481            <access>read-only</access>
37482            <resetValue>0x3137302A</resetValue>
37483            <resetMask>0xFFFFFFFF</resetMask>
37484            <fields>
37485              <field>
37486                <name>MSHC_VER_ID</name>
37487                <description>Current release number
37488This field indicates the Synopsys DesignWare Cores
37489DWC_mshc/DWC_mshc_lite current release number that is
37490read by an application.
37491For example, release number '1.60a' is represented in
37492ASCII as 0x313630. Lower 8 bits read from this register can
37493be ignored by the application.
37494An application reading this register in conjunction with the
37495MSHC_VER_TYPE_R register, gathers details of the current
37496release.</description>
37497                <bitRange>[31:0]</bitRange>
37498                <access>read-only</access>
37499              </field>
37500            </fields>
37501          </register>
37502          <register>
37503            <name>MSHC_VER_TYPE_R</name>
37504            <description>MSHC version type</description>
37505            <addressOffset>0x504</addressOffset>
37506            <size>32</size>
37507            <access>read-only</access>
37508            <resetValue>0x67612A2A</resetValue>
37509            <resetMask>0xFFFFFFFF</resetMask>
37510            <fields>
37511              <field>
37512                <name>MSHC_VER_TYPE</name>
37513                <description>Current release type
37514This field indicates the Synopsys DesignWare Cores
37515DWC_mshc/DWC_mshc_lite current release type that is
37516read by an application.
37517For example, release type is 'ga' is represented in ASCII as
375180x6761. Lower 16 bits read from this register can be ignored
37519by the application.
37520An application reading this register in conjunction with the
37521MSHC_VER_ID_R register, gathers details of the current
37522release.</description>
37523                <bitRange>[31:0]</bitRange>
37524                <access>read-only</access>
37525              </field>
37526            </fields>
37527          </register>
37528          <register>
37529            <name>MSHC_CTRL_R</name>
37530            <description>MSHC Control register</description>
37531            <addressOffset>0x508</addressOffset>
37532            <size>8</size>
37533            <access>read-write</access>
37534            <resetValue>0x1</resetValue>
37535            <resetMask>0x11</resetMask>
37536            <fields>
37537              <field>
37538                <name>CMD_CONFLICT_CHECK</name>
37539                <description>Command conflict check
37540This bit enables command conflict check.
37541Note: DWC_mshc controller monitors the CMD line
37542whenever a command is issued and checks whether the
37543value driven on sd_cmd_out matches the value on
37544sd_cmd_in at next subsequent edge of cclk_tx to determine
37545command conflict error. This bit is cleared only if the feed
37546back delay (including IO Pad delay) is more than
37547(t_card_clk_period - t_setup), where t_setup is the setup
37548time of a flop in DWC_mshc. The I/O pad delay is consistent
37549across CMD and DATA lines, and it is within the value:
37550(2*t_card_clk_period - t_setup)
37551Values:
37552- 0x0 (DISABLE_CMD_CONFLICT_CHK): Disable
37553command conflict check
37554- 0x1 (CMD_CONFLICT_CHK_LAT1): Check for command
37555conflict after 1 card clock cycle</description>
37556                <bitRange>[0:0]</bitRange>
37557                <access>read-write</access>
37558              </field>
37559              <field>
37560                <name>SW_CG_DIS</name>
37561                <description>Internal clock gating disable control
37562This bit must be used to disable IP's internal clock gating
37563when required. when disabled clocks are not gated. Clocks
37564to the core (except hclk) must be stopped when
37565programming this bit.
37566Values:
37567- 0x0 (ENABLE): Internal clock gates are active and clock
37568gating is controlled internally
37569- 0x1 (DISABLE): Internal clock gating is disabled, clocks
37570are not gated internally</description>
37571                <bitRange>[4:4]</bitRange>
37572                <access>read-write</access>
37573              </field>
37574            </fields>
37575          </register>
37576          <register>
37577            <name>MBIU_CTRL_R</name>
37578            <description>MBIU Control register</description>
37579            <addressOffset>0x510</addressOffset>
37580            <size>8</size>
37581            <access>read-write</access>
37582            <resetValue>0x1</resetValue>
37583            <resetMask>0xF</resetMask>
37584            <fields>
37585              <field>
37586                <name>UNDEFL_INCR_EN</name>
37587                <description>Undefined INCR Burst
37588Controls generation of undefined length INCR transfer on
37589Master interface.
37590Values:
37591- 0x0 (FALSE): Undefined INCR type burst is the least
37592preferred burst on AHB Master I/F
37593- 0x1 (TRUE): Undefined INCR type burst is the most
37594preferred burst on AHB Master I/F</description>
37595                <bitRange>[0:0]</bitRange>
37596                <access>read-write</access>
37597              </field>
37598              <field>
37599                <name>BURST_INCR4_EN</name>
37600                <description>INCR4 Burst
37601Controls generation of INCR4 transfers on Master interface.
37602Values:
37603- 0x0 (FALSE): AHB INCR4 burst type is not generated on
37604Master I/F
37605- 0x1 (TRUE): AHB INCR4 burst type can be generated on
37606Master I/F</description>
37607                <bitRange>[1:1]</bitRange>
37608                <access>read-write</access>
37609              </field>
37610              <field>
37611                <name>BURST_INCR8_EN</name>
37612                <description>INCR8 Burst
37613Controls generation of INCR8 transfers on Master interface.
37614Values:
37615- 0x0 (FALSE): AHB INCR8 burst type is not generated on
37616Master I/F
37617- 0x1 (TRUE): AHB INCR8 burst type can be generated on
37618Master I/F</description>
37619                <bitRange>[2:2]</bitRange>
37620                <access>read-write</access>
37621              </field>
37622              <field>
37623                <name>BURST_INCR16_EN</name>
37624                <description>INCR16 Burst
37625Controls generation of INCR16 transfers on Master
37626interface.
37627Values:
37628- 0x0 (FALSE): AHB INCR16 burst type is not generated on
37629Master I/F
37630- 0x1 (TRUE): AHB INCR16 burst type can be generated
37631on Master I/F</description>
37632                <bitRange>[3:3]</bitRange>
37633                <access>read-write</access>
37634              </field>
37635            </fields>
37636          </register>
37637          <register>
37638            <name>EMMC_CTRL_R</name>
37639            <description>eMMC Control register</description>
37640            <addressOffset>0x52C</addressOffset>
37641            <size>16</size>
37642            <access>read-write</access>
37643            <resetValue>0xC</resetValue>
37644            <resetMask>0x60F</resetMask>
37645            <fields>
37646              <field>
37647                <name>CARD_IS_EMMC</name>
37648                <description>eMMC Card present
37649This bit indicates the type of card connected. An application
37650program this bit based on the card connected to SDHC.
37651Values:
37652- 0x1 (EMMC_CARD): Card connected to SDHC is an
37653eMMC card
37654- 0x0 (NON_EMMC_CARD): Card connected to SDHC is
37655a non-eMMC card</description>
37656                <bitRange>[0:0]</bitRange>
37657                <access>read-write</access>
37658              </field>
37659              <field>
37660                <name>DISABLE_DATA_CRC_CHK</name>
37661                <description>Disable Data CRC Check
37662This bit controls masking of CRC16 error for Card Write in
37663eMMC mode. This is useful in bus testing (CMD19) for an
37664eMMC device. In bus testing, an eMMC card does not send
37665CRC status for a block, which may generate CRC error. This
37666CRC error can be masked using this bit during bus testing.
37667Values:
37668- 0x1 (DISABLE): DATA CRC check is disabled
37669- 0x0 (ENABLE): DATA CRC check is enabled</description>
37670                <bitRange>[1:1]</bitRange>
37671                <access>read-write</access>
37672              </field>
37673              <field>
37674                <name>EMMC_RST_N</name>
37675                <description>EMMC Device Reset signal control.
37676This register field controls the card_emmc_reset_n output of SDHC
37677Values:
37678- 0x1 (RST_DEASSERT): Reset to eMMC device is
37679deasserted
37680- 0x0 (RST_ASSERT): Reset to eMMC device asserted
37681(active low)</description>
37682                <bitRange>[2:2]</bitRange>
37683                <access>read-write</access>
37684              </field>
37685              <field>
37686                <name>EMMC_RST_N_OE</name>
37687                <description>Output Enable (OE) control for EMMC Device Reset signal (card_emmc_reset_n).
37688Values:
37689- 0x1 (ENABLE): OE for card_emmc_reset_n is 1
37690- 0x0 (DISABLE): OE for card_emmc_reset_n is 0</description>
37691                <bitRange>[3:3]</bitRange>
37692                <access>read-write</access>
37693              </field>
37694              <field>
37695                <name>CQE_ALGO_SEL</name>
37696                <description>Scheduler algorithm selected for execution
37697This bit selects the Algorithm used for selecting one of the
37698many ready tasks for execution.
37699Values:
37700- 0x0 (PRI_REORDER_PLUS_FCFS): Priority based
37701reordering with FCFS to resolve equal priority tasks
37702- 0x1 (FCFS_ONLY): First come First serve, in the order of
37703DBR rings</description>
37704                <bitRange>[9:9]</bitRange>
37705                <access>read-write</access>
37706              </field>
37707              <field>
37708                <name>CQE_PREFETCH_DISABLE</name>
37709                <description>Enable or Disable CQE's PREFETCH feature
37710This field allows Software to disable CQE's data prefetch
37711feature when set to 1.
37712Values:
37713- 0x0 (PREFETCH_ENABLE): CQE can Prefetch data for
37714sucessive WRITE transfers and pipeline sucessive READ
37715transfers
37716- 0x1 (PREFETCH_DISABLE): Prefetch for WRITE and
37717Pipeline for READ are disabled</description>
37718                <bitRange>[10:10]</bitRange>
37719                <access>read-write</access>
37720              </field>
37721            </fields>
37722          </register>
37723          <register>
37724            <name>BOOT_CTRL_R</name>
37725            <description>eMMC Boot Control register</description>
37726            <addressOffset>0x52E</addressOffset>
37727            <size>16</size>
37728            <access>read-write</access>
37729            <resetValue>0x0</resetValue>
37730            <resetMask>0xF181</resetMask>
37731            <fields>
37732              <field>
37733                <name>MAN_BOOT_EN</name>
37734                <description>Mandatory Boot Enable
37735This bit is used to initiate the mandatory boot operation. The
37736application sets this bit along with VALIDATE_BOOT bit.
37737Writing 0 is ignored. The SDHC clears this bit after the
37738boot transfer is completed or terminated.
37739Values:
37740- 0x1 (MAN_BOOT_EN): Mandatory boot enable
37741- 0x0 (MAN_BOOT_DIS): Mandatory boot disable</description>
37742                <bitRange>[0:0]</bitRange>
37743                <access>read-write</access>
37744              </field>
37745              <field>
37746                <name>VALIDATE_BOOT</name>
37747                <description>Validate Mandatory Boot Enable bit
37748This bit is used to validate the MAN_BOOT_EN bit.
37749Values:
37750- 0x1 (TRUE): Validate Mandatory boot enable bit
37751- 0x0 (FALSE): Ignore Mandatory boot Enable bit</description>
37752                <bitRange>[7:7]</bitRange>
37753                <access>write-only</access>
37754              </field>
37755              <field>
37756                <name>BOOT_ACK_ENABLE</name>
37757                <description>Boot Acknowledge Enable
37758When this bit set, SDHC checks for boot acknowledge
37759start pattern of 0-1-0 during boot operation. This bit is
37760applicable for both mandatory and alternate boot mode.
37761Values:
37762- 0x1 (TRUE): Boot Ack enable
37763- 0x0 (FALSE): Boot Ack disable</description>
37764                <bitRange>[8:8]</bitRange>
37765                <access>read-write</access>
37766              </field>
37767              <field>
37768                <name>BOOT_TOUT_CNT</name>
37769                <description>N/A</description>
37770                <bitRange>[15:12]</bitRange>
37771                <access>read-write</access>
37772              </field>
37773            </fields>
37774          </register>
37775          <register>
37776            <name>GP_IN_R</name>
37777            <description>General Purpose Input register</description>
37778            <addressOffset>0x530</addressOffset>
37779            <size>32</size>
37780            <access>read-only</access>
37781            <resetValue>0x0</resetValue>
37782            <resetMask>0x1</resetMask>
37783            <fields>
37784              <field>
37785                <name>GP_IN</name>
37786                <description>It reflects the value of gp_in ports.
37787NOT USED - ALWAYS READS 0</description>
37788                <bitRange>[0:0]</bitRange>
37789                <access>read-only</access>
37790              </field>
37791            </fields>
37792          </register>
37793          <register>
37794            <name>GP_OUT_R</name>
37795            <description>General Purpose Output register</description>
37796            <addressOffset>0x534</addressOffset>
37797            <size>32</size>
37798            <access>read-write</access>
37799            <resetValue>0x0</resetValue>
37800            <resetMask>0x3FF</resetMask>
37801            <fields>
37802              <field>
37803                <name>CARD_DETECT_EN</name>
37804                <description>0: Force card_detect_n input to 0
378051:  Normal card_detect_n operation allowing card detection from a device pin</description>
37806                <bitRange>[0:0]</bitRange>
37807                <access>read-write</access>
37808              </field>
37809              <field>
37810                <name>CARD_MECH_WRITE_PROT_EN</name>
37811                <description>card_mech_write_prot, despite its name, is an active low signal (per the SD Host Controller Standard spec it is officially called SDWP#).  Consider that in the following:
378120: Force card_mech_write_prot input to 0 internally; this forces write protection to be active
378131: Allow card_mech_write_prot to work normally per the device's pin state</description>
37814                <bitRange>[1:1]</bitRange>
37815                <access>read-write</access>
37816              </field>
37817              <field>
37818                <name>LED_CTRL_OE</name>
37819                <description>Active high output enable for the LED output signal (led_ctrl) controlled through HOST_CTRL1_R.LED_CTRL:
378200: disable OE associated with the led_ctrl output
378211: enable OE associated with the led_ctrl output</description>
37822                <bitRange>[2:2]</bitRange>
37823                <access>read-write</access>
37824              </field>
37825              <field>
37826                <name>CARD_CLOCK_OE</name>
37827                <description>Active high output enable for the card clock output (clk_card) which is gated by CLK_CTRL_R.SD_CLK_EN:
378280: disable OE to the clk_card output
378291: enable OE to the clk_card output</description>
37830                <bitRange>[3:3]</bitRange>
37831                <access>read-write</access>
37832              </field>
37833              <field>
37834                <name>CARD_IF_PWR_EN_OE</name>
37835                <description>Active high output enable for the card interface power enable output (card_if_pwr_en) controlled through PWR_CTRL_R.SD_BUS_PWR_VDD1:
378360: disable OE to the card_if_pwr_en output
378371: enable OE to the card_if_pwr_en output</description>
37838                <bitRange>[4:4]</bitRange>
37839                <access>read-write</access>
37840              </field>
37841              <field>
37842                <name>IO_VOLT_SEL_OE</name>
37843                <description>Active high output enable for the IO voltage selection signal (io_volt_sel) controlled through HOST_CTRL_2.SIGNALING_EN:
378440: disable OE to the io_volt_sel output
378451: enable OE to the io_volt_sel output</description>
37846                <bitRange>[5:5]</bitRange>
37847                <access>read-write</access>
37848              </field>
37849              <field>
37850                <name>CARD_CLOCK_OUT_DLY</name>
37851                <description>N/A</description>
37852                <bitRange>[7:6]</bitRange>
37853                <access>read-write</access>
37854              </field>
37855              <field>
37856                <name>CARD_CLOCK_IN_DLY</name>
37857                <description>Delay CARD_CLOCK input internally to optimally sample CMD/DAT; set according to interface mode:
3785800: SD Default Speed, SD SDR12, eMMC Legacy
3785901: SD SDR25, SD SDR50
3786010: SD High Speed, eMMC High Speed SDR
3786111: SD DDR50, eMMC DDR</description>
37862                <bitRange>[9:8]</bitRange>
37863                <access>read-write</access>
37864              </field>
37865            </fields>
37866          </register>
37867        </cluster>
37868      </registers>
37869    </peripheral>
37870    <peripheral derivedFrom="SDHC0">
37871      <name>SDHC1</name>
37872      <baseAddress>0x40470000</baseAddress>
37873    </peripheral>
37874    <peripheral>
37875      <name>SCB0</name>
37876      <description>Serial Communications Block (SPI/UART/I2C)</description>
37877      <headerStructName>SCB</headerStructName>
37878      <baseAddress>0x40600000</baseAddress>
37879      <addressBlock>
37880        <offset>0</offset>
37881        <size>65536</size>
37882        <usage>registers</usage>
37883      </addressBlock>
37884      <registers>
37885        <register>
37886          <name>CTRL</name>
37887          <description>Generic control</description>
37888          <addressOffset>0x0</addressOffset>
37889          <size>32</size>
37890          <access>read-write</access>
37891          <resetValue>0x300000F</resetValue>
37892          <resetMask>0x83031F0F</resetMask>
37893          <fields>
37894            <field>
37895              <name>OVS</name>
37896              <description>N/A</description>
37897              <bitRange>[3:0]</bitRange>
37898              <access>read-write</access>
37899            </field>
37900            <field>
37901              <name>EC_AM_MODE</name>
37902              <description>Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported.
37903
37904In UART mode this field should be '0'.</description>
37905              <bitRange>[8:8]</bitRange>
37906              <access>read-write</access>
37907            </field>
37908            <field>
37909              <name>EC_OP_MODE</name>
37910              <description>Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported. The maximum SPI slave, EZ mode bitrate is 48 Mbps (transmission and IO delays outside the IP will degrade the effective bitrate).
37911
37912In UART mode this field should be '0'.</description>
37913              <bitRange>[9:9]</bitRange>
37914              <access>read-write</access>
37915            </field>
37916            <field>
37917              <name>EZ_MODE</name>
37918              <description>Non EZ mode ('0') or EZ mode ('1'). In EZ mode, a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory address, a write memory data element or a read memory data element. EZ mode is only used for synchronous serial interface protocols: SPI and I2C. In SPI mode, only Motorola submode (all Motorola modes: 0, 1, 2, 3) is supported and the transmitter should use continuous data frames; i.e. data frames mot separated by slave deselection. This mode is only applicable to slave functionality. In EZ mode, the slave can read from and write to an addressable memory structure of up to 256 bytes. In EZ mode, data frames should 8-bit in size and should be transmitted and received with the Most Significant Bit (MSB) first.
37919
37920In UART mode this field should be '0'.</description>
37921              <bitRange>[10:10]</bitRange>
37922              <access>read-write</access>
37923            </field>
37924            <field>
37925              <name>BYTE_MODE</name>
37926              <description>Determines the number of bits per FIFO data element:
37927'0': 16-bit FIFO data elements.
37928'1': 8-bit FIFO data elements. This mode doubles the amount of FIFO entries, but  TX_CTRL.DATA_WIDTH and RX_CTRL.DATA_WIDTH are restricted to [0, 7].</description>
37929              <bitRange>[11:11]</bitRange>
37930              <access>read-write</access>
37931            </field>
37932            <field>
37933              <name>CMD_RESP_MODE</name>
37934              <description>Determines CMD_RESP mode of operation:
37935'0': CMD_RESP mode disabled.
37936'1': CMD_RESP mode enabled (also requires EC_AM_MODE and EC_OP_MODE to be set to '1').</description>
37937              <bitRange>[12:12]</bitRange>
37938              <access>read-write</access>
37939            </field>
37940            <field>
37941              <name>ADDR_ACCEPT</name>
37942              <description>Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0').
37943
37944In I2C mode, this field is used to allow the slave to put the received slave address or general call address in the RX FIFO. Note that a received matching address is put in the RX FIFO when ADDR_ACCEPT is '1' for both I2C read and write transfers.
37945
37946In multi-processor UART receiver mode, this field is used to allow the receiver to put the received address in the RX FIFO. Note: non-matching addresses are never put in the RX FIFO.</description>
37947              <bitRange>[16:16]</bitRange>
37948              <access>read-write</access>
37949            </field>
37950            <field>
37951              <name>BLOCK</name>
37952              <description>Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide, this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0'). IF BLOCK is '0' and the accesses collide, MMIO read operations return 0xffff:ffff and MMIO write operations are ignored. Colliding accesses are registered as interrupt causes: field BLOCKED of MMIO registers INTR_TX and INTR_RX.</description>
37953              <bitRange>[17:17]</bitRange>
37954              <access>read-write</access>
37955            </field>
37956            <field>
37957              <name>MODE</name>
37958              <description>N/A</description>
37959              <bitRange>[25:24]</bitRange>
37960              <access>read-write</access>
37961              <enumeratedValues>
37962                <enumeratedValue>
37963                  <name>I2C</name>
37964                  <description>Inter-Integrated Circuits (I2C) mode.</description>
37965                  <value>0</value>
37966                </enumeratedValue>
37967                <enumeratedValue>
37968                  <name>SPI</name>
37969                  <description>Serial Peripheral Interface (SPI) mode.</description>
37970                  <value>1</value>
37971                </enumeratedValue>
37972                <enumeratedValue>
37973                  <name>UART</name>
37974                  <description>Universal Asynchronous Receiver/Transmitter (UART) mode.</description>
37975                  <value>2</value>
37976                </enumeratedValue>
37977              </enumeratedValues>
37978            </field>
37979            <field>
37980              <name>ENABLED</name>
37981              <description>IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:
37982- Program protocol specific information using SPI_CTRL, UART_CTRL (and UART_TX_CTRL and UART_RX_CTRL) or I2C_CTRL. This includes selection of a submode, master/slave functionality and transmitter/receiver functionality when applicable.
37983- Program generic transmitter (TX_CTRL) and receiver (RX_CTRL) information. This includes enabling of the transmitter and receiver functionality.
37984- Program transmitter FIFO (TX_FIFO_CTRL) and receiver FIFO (RX_FIFO_CTRL) information.
37985- Program CTRL to enable IP, select the specific operation mode and oversampling factor.
37986When the IP is enabled, no control information should be changed. Changes should be made AFTER disabling the IP, e.g. to modify the operation mode (from I2C to SPI) or to go from externally to internally clocked. The change takes effect after the IP is re-enabled. Note that disabling the IP will cause re-initialization of the design and associated state is lost (e.g. FIFO content).</description>
37987              <bitRange>[31:31]</bitRange>
37988              <access>read-write</access>
37989            </field>
37990          </fields>
37991        </register>
37992        <register>
37993          <name>STATUS</name>
37994          <description>Generic status</description>
37995          <addressOffset>0x4</addressOffset>
37996          <size>32</size>
37997          <access>read-only</access>
37998          <resetValue>0x0</resetValue>
37999          <resetMask>0x0</resetMask>
38000          <fields>
38001            <field>
38002              <name>EC_BUSY</name>
38003              <description>Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a blocked SW access) or bus errors being generated). Note that the INTR_TX.BLOCKED and INTR_RX.BLOCKED interrupt causes are used to indicate whether a SW access was actually blocked by externally clocked logic.</description>
38004              <bitRange>[0:0]</bitRange>
38005              <access>read-only</access>
38006            </field>
38007          </fields>
38008        </register>
38009        <register>
38010          <name>CMD_RESP_CTRL</name>
38011          <description>Command/response control</description>
38012          <addressOffset>0x8</addressOffset>
38013          <size>32</size>
38014          <access>read-write</access>
38015          <resetValue>0x0</resetValue>
38016          <resetMask>0x1FF01FF</resetMask>
38017          <fields>
38018            <field>
38019              <name>BASE_RD_ADDR</name>
38020              <description>I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to CMD_RESP_STATUS.CURR_RD_ADDR. This field should not be modified during ongoing bus transfers.</description>
38021              <bitRange>[8:0]</bitRange>
38022              <access>read-write</access>
38023            </field>
38024            <field>
38025              <name>BASE_WR_ADDR</name>
38026              <description>I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to CMD_RESP_STATUS.CURR_WR_ADDR. This field should not be modified during ongoing bus transfers.</description>
38027              <bitRange>[24:16]</bitRange>
38028              <access>read-write</access>
38029            </field>
38030          </fields>
38031        </register>
38032        <register>
38033          <name>CMD_RESP_STATUS</name>
38034          <description>Command/response status</description>
38035          <addressOffset>0xC</addressOffset>
38036          <size>32</size>
38037          <access>read-only</access>
38038          <resetValue>0x0</resetValue>
38039          <resetMask>0x0</resetMask>
38040          <fields>
38041            <field>
38042              <name>CURR_RD_ADDR</name>
38043              <description>I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address).
38044
38045The field is used to determine how many bytes have been read (# bytes = CURR_RD_ADDR - CMD_RESP_CTRL.BASE_RD_ADDR).
38046
38047This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable.</description>
38048              <bitRange>[8:0]</bitRange>
38049              <access>read-only</access>
38050            </field>
38051            <field>
38052              <name>CURR_WR_ADDR</name>
38053              <description>I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However, when the last memory buffer address is reached, the address is NOT incremented (but remains at the maximum memory buffer address).
38054
38055The field is used to determine how many bytes have been written (# bytes = CURR_WR_ADDR - CMD_RESP_CTRL.BASE_WR_ADDR).
38056
38057This field is reliable during when there is no bus transfer. This field is potentially unreliable when there is a bus transfer bus transfer: when CMD_RESP_EC_BUSY is '0', the field is reliable.</description>
38058              <bitRange>[24:16]</bitRange>
38059              <access>read-only</access>
38060            </field>
38061            <field>
38062              <name>CMD_RESP_EC_BUS_BUSY</name>
38063              <description>Indicates whether there is an ongoing bus transfer to the IP.
38064'0': no ongoing bus transfer.
38065'1': ongoing bus transfer.
38066
38067For SPI, the field is '1' when the slave is selected.
38068
38069For I2C, the field is set to '1' at a I2C START/RESTART. In case of an address match, the  field is set to '0' on a I2C STOP. In case of NO address match, the field is set to '0' after the failing address match.</description>
38070              <bitRange>[30:30]</bitRange>
38071              <access>read-only</access>
38072            </field>
38073            <field>
38074              <name>CMD_RESP_EC_BUSY</name>
38075              <description>Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:
38076- When there is no ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable).
38077- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '0' (reliable), when the CURR_RD_ADDR and CURR_WR_ADDR are not being updated by the HW.
38078- When there is a ongoing bus transfer, CMD_RESP_EC_BUSY is '1' (not reliable), when the CURR_RD_ADDR or CURR_WR_ADDR are being updated by the HW.
38079   Note that this update lasts one I2C clock cycle, or two SPI clock cycles.</description>
38080              <bitRange>[31:31]</bitRange>
38081              <access>read-only</access>
38082            </field>
38083          </fields>
38084        </register>
38085        <register>
38086          <name>SPI_CTRL</name>
38087          <description>SPI control</description>
38088          <addressOffset>0x20</addressOffset>
38089          <size>32</size>
38090          <access>read-write</access>
38091          <resetValue>0x3000000</resetValue>
38092          <resetMask>0x8F010F3F</resetMask>
38093          <fields>
38094            <field>
38095              <name>SSEL_CONTINUOUS</name>
38096              <description>Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode, both continuous and non-continuous SPI data transfers are supported independent of this field.
38097
38098When continuous transfers are enabled individual data frame transfers are not necessarily separated by slave deselection (as indicated by the level or pulse on the SELECT line): if the TX FIFO has multiple data frames, data frames are send out without slave deselection.
38099
38100When continuous transfers are not enabled individual data frame transfers are always separated by slave deselection: independent of the availability of TX FIFO data frames.</description>
38101              <bitRange>[0:0]</bitRange>
38102              <access>read-write</access>
38103            </field>
38104            <field>
38105              <name>SELECT_PRECEDE</name>
38106              <description>Only used in SPI Texas Instruments' submode.
38107
38108When '1', the data frame start indication is a pulse on the SELECT line that precedes the transfer of the first data frame bit.
38109
38110When '0', the data frame start indication is a pulse on the SELECT line that coincides with the transfer of the first data frame bit.</description>
38111              <bitRange>[1:1]</bitRange>
38112              <access>read-write</access>
38113            </field>
38114            <field>
38115              <name>CPHA</name>
38116              <description>Indicates the clock phase. This field, together with the CPOL field, indicates when MOSI data is driven and MISO data is captured:
38117- Motorola mode 0. CPOL is '0', CPHA is '0': MOSI  is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK.
38118- Motorola mode 1. CPOL is '0', CPHA is '1': MOSI  is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK.
38119- Motorola mode 2. CPOL is '1', CPHA is '0': MOSI  is driven on a rising edge of SCLK. MISO is captured on a falling edge of SCLK.
38120- Motorola mode 3. CPOL is '1', CPHA is '1': MOSI  is driven on a falling edge of SCLK. MISO is captured on a rising edge of SCLK.
38121
38122In SPI Motorola submode, all four CPOL/CPHA modes are valid.
38123in SPI NS submode, only CPOL=0 CPHA=0 mode is valid.
38124in SPI TI submode, only CPOL=0 CPHA=1 mode is valid.</description>
38125              <bitRange>[2:2]</bitRange>
38126              <access>read-write</access>
38127            </field>
38128            <field>
38129              <name>CPOL</name>
38130              <description>Indicates the clock polarity. This field, together with the CPHA field, indicates when MOSI data is driven and MISO data is captured:
38131- CPOL is '0': SCLK is '0' when not transmitting data.
38132- CPOL is '1': SCLK is '1' when not transmitting data.</description>
38133              <bitRange>[3:3]</bitRange>
38134              <access>read-write</access>
38135            </field>
38136            <field>
38137              <name>LATE_MISO_SAMPLE</name>
38138              <description>Changes the SCLK edge on which MISO is captured. Only used in master mode.
38139
38140When '0', the default applies (for Motorola as determined by CPOL and CPHA, for Texas Instruments on the falling edge of SCLK and for National Semiconductors on the rising edge of SCLK).
38141
38142When '1', the alternate clock edge is used (which comes half a SPI SCLK period later). Late sampling addresses the round trip delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master.</description>
38143              <bitRange>[4:4]</bitRange>
38144              <access>read-write</access>
38145            </field>
38146            <field>
38147              <name>SCLK_CONTINUOUS</name>
38148              <description>Only applicable in master mode.
38149'0': SCLK is generated, when the SPI master is enabled and data is transmitted.
38150'1': SCLK is generated, when the SPI master is enabled. This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality.</description>
38151              <bitRange>[5:5]</bitRange>
38152              <access>read-write</access>
38153            </field>
38154            <field>
38155              <name>SSEL_POLARITY0</name>
38156              <description>Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:
38157'0': slave select is low/'0' active.
38158'1': slave select is high/'1' active.
38159For Texas Instruments submode:
38160'0': high/'1' active precede/coincide pulse.
38161'1': low/'0' active precede/coincide pulse.</description>
38162              <bitRange>[8:8]</bitRange>
38163              <access>read-write</access>
38164            </field>
38165            <field>
38166              <name>SSEL_POLARITY1</name>
38167              <description>Slave select polarity.</description>
38168              <bitRange>[9:9]</bitRange>
38169              <access>read-write</access>
38170            </field>
38171            <field>
38172              <name>SSEL_POLARITY2</name>
38173              <description>Slave select polarity.</description>
38174              <bitRange>[10:10]</bitRange>
38175              <access>read-write</access>
38176            </field>
38177            <field>
38178              <name>SSEL_POLARITY3</name>
38179              <description>Slave select polarity.</description>
38180              <bitRange>[11:11]</bitRange>
38181              <access>read-write</access>
38182            </field>
38183            <field>
38184              <name>LOOPBACK</name>
38185              <description>Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode.
38186'0': the SPI master MISO line 'spi_miso_in' is connected to the SPI MISO pin.
38187'1': the SPI master MISO line 'spi_miso_in' is connected to the SPI master MOSI line 'spi_mosi_out'. In other words, in loopback mode the SPI master receives on MISO what it transmits on MOSI.</description>
38188              <bitRange>[16:16]</bitRange>
38189              <access>read-write</access>
38190            </field>
38191            <field>
38192              <name>MODE</name>
38193              <description>N/A</description>
38194              <bitRange>[25:24]</bitRange>
38195              <access>read-write</access>
38196              <enumeratedValues>
38197                <enumeratedValue>
38198                  <name>SPI_MOTOROLA</name>
38199                  <description>SPI Motorola submode. In master mode, when not transmitting data (SELECT is inactive), SCLK is stable at CPOL. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive.</description>
38200                  <value>0</value>
38201                </enumeratedValue>
38202                <enumeratedValue>
38203                  <name>SPI_TI</name>
38204                  <description>SPI Texas Instruments submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive; i.e. no pulse is generated.</description>
38205                  <value>1</value>
38206                </enumeratedValue>
38207                <enumeratedValue>
38208                  <name>SPI_NS</name>
38209                  <description>SPI National Semiconductors submode. In master mode, when not transmitting data, SCLK is stable at '0'. In slave mode, when not selected, SCLK is ignored; i.e. it can be either stable or clocking. In master mode, when there is no data to transmit (TX FIFO is empty), SELECT is inactive.</description>
38210                  <value>2</value>
38211                </enumeratedValue>
38212              </enumeratedValues>
38213            </field>
38214            <field>
38215              <name>SSEL</name>
38216              <description>Selects one of the four incoming/outgoing SPI slave select signals:
38217- 0: Slave 0, SSEL[0].
38218- 1: Slave 1, SSEL[1].
38219- 2: Slave 2, SSEL[2].
38220- 3: Slave 3, SSEL[3].
38221The IP should be disabled when changes are made to this field.</description>
38222              <bitRange>[27:26]</bitRange>
38223              <access>read-write</access>
38224            </field>
38225            <field>
38226              <name>MASTER_MODE</name>
38227              <description>Master ('1') or slave ('0') mode. In master mode, transmission will commence on availability of data frames in the TX FIFO. In slave mode, when selected and there is no data frame in the TX FIFO, the slave will transmit all '1's. In both master and slave modes, received data frames will be lost if the RX FIFO is full.</description>
38228              <bitRange>[31:31]</bitRange>
38229              <access>read-write</access>
38230            </field>
38231          </fields>
38232        </register>
38233        <register>
38234          <name>SPI_STATUS</name>
38235          <description>SPI status</description>
38236          <addressOffset>0x24</addressOffset>
38237          <size>32</size>
38238          <access>read-only</access>
38239          <resetValue>0x0</resetValue>
38240          <resetMask>0x0</resetMask>
38241          <fields>
38242            <field>
38243              <name>BUS_BUSY</name>
38244              <description>SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes, the busy bit is '1', when the slave selection is activated. For TI submode, the busy bit is '1' from the time the preceding/coinciding slave select is activated for the first transmitted data frame, till the last MOSI/MISO bit of the last data frame is transmitted.</description>
38245              <bitRange>[0:0]</bitRange>
38246              <access>read-only</access>
38247            </field>
38248            <field>
38249              <name>SPI_EC_BUSY</name>
38250              <description>Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable.</description>
38251              <bitRange>[1:1]</bitRange>
38252              <access>read-only</access>
38253            </field>
38254            <field>
38255              <name>CURR_EZ_ADDR</name>
38256              <description>SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1'), as clock domain synchronization is not performed in the design.</description>
38257              <bitRange>[15:8]</bitRange>
38258              <access>read-only</access>
38259            </field>
38260            <field>
38261              <name>BASE_EZ_ADDR</name>
38262              <description>SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design.</description>
38263              <bitRange>[23:16]</bitRange>
38264              <access>read-only</access>
38265            </field>
38266          </fields>
38267        </register>
38268        <register>
38269          <name>UART_CTRL</name>
38270          <description>UART control</description>
38271          <addressOffset>0x40</addressOffset>
38272          <size>32</size>
38273          <access>read-write</access>
38274          <resetValue>0x3000000</resetValue>
38275          <resetMask>0x3010000</resetMask>
38276          <fields>
38277            <field>
38278              <name>LOOPBACK</name>
38279              <description>Local loopback control (does NOT affect the information on the pins). When '0', the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1', the transmitter TX line 'uart_tx_out' is connected to the receiver RX line 'uart_rx_in'. A similar connections scheme is followed for 'uart_rts_out' and 'uart_cts_in'.
38280
38281This allows a SCB UART transmitter to communicate with its receiver counterpart.</description>
38282              <bitRange>[16:16]</bitRange>
38283              <access>read-write</access>
38284            </field>
38285            <field>
38286              <name>MODE</name>
38287              <description>N/A</description>
38288              <bitRange>[25:24]</bitRange>
38289              <access>read-write</access>
38290              <enumeratedValues>
38291                <enumeratedValue>
38292                  <name>UART_STD</name>
38293                  <description>Standard UART submode.</description>
38294                  <value>0</value>
38295                </enumeratedValue>
38296                <enumeratedValue>
38297                  <name>UART_SMARTCARD</name>
38298                  <description>SmartCard (ISO7816) submode. Support for negative acknowledgement (NACK) on the receiver side and retransmission on the transmitter side.</description>
38299                  <value>1</value>
38300                </enumeratedValue>
38301                <enumeratedValue>
38302                  <name>UART_IRDA</name>
38303                  <description>Infrared Data Association (IrDA) submode. Return to Zero modulation scheme.</description>
38304                  <value>2</value>
38305                </enumeratedValue>
38306              </enumeratedValues>
38307            </field>
38308          </fields>
38309        </register>
38310        <register>
38311          <name>UART_TX_CTRL</name>
38312          <description>UART transmitter control</description>
38313          <addressOffset>0x44</addressOffset>
38314          <size>32</size>
38315          <access>read-write</access>
38316          <resetValue>0x2</resetValue>
38317          <resetMask>0x137</resetMask>
38318          <fields>
38319            <field>
38320              <name>STOP_BITS</name>
38321              <description>Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period.</description>
38322              <bitRange>[2:0]</bitRange>
38323              <access>read-write</access>
38324            </field>
38325            <field>
38326              <name>PARITY</name>
38327              <description>Parity bit. When '0', the transmitter generates an even parity. When '1', the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes.</description>
38328              <bitRange>[4:4]</bitRange>
38329              <access>read-write</access>
38330            </field>
38331            <field>
38332              <name>PARITY_ENABLED</name>
38333              <description>Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware</description>
38334              <bitRange>[5:5]</bitRange>
38335              <access>read-write</access>
38336            </field>
38337            <field>
38338              <name>RETRY_ON_NACK</name>
38339              <description>When '1', a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode.</description>
38340              <bitRange>[8:8]</bitRange>
38341              <access>read-write</access>
38342            </field>
38343          </fields>
38344        </register>
38345        <register>
38346          <name>UART_RX_CTRL</name>
38347          <description>UART receiver control</description>
38348          <addressOffset>0x48</addressOffset>
38349          <size>32</size>
38350          <access>read-write</access>
38351          <resetValue>0xA0002</resetValue>
38352          <resetMask>0xF3777</resetMask>
38353          <fields>
38354            <field>
38355              <name>STOP_BITS</name>
38356              <description>Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period.
38357
38358Note that in case of a stop bits error, the successive data frames may get lost as the receiver needs to resynchronize its start bit detection. The amount of lost data frames depends on both the amount of stop bits, the idle ('1') time between data frames and the data frame value.</description>
38359              <bitRange>[2:0]</bitRange>
38360              <access>read-write</access>
38361            </field>
38362            <field>
38363              <name>PARITY</name>
38364              <description>Parity bit. When '0', the receiver expects an even parity. When '1', the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes.</description>
38365              <bitRange>[4:4]</bitRange>
38366              <access>read-write</access>
38367            </field>
38368            <field>
38369              <name>PARITY_ENABLED</name>
38370              <description>Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode, parity checking is always enabled through hardware. In IrDA submode, parity checking is always disabled through hardware.</description>
38371              <bitRange>[5:5]</bitRange>
38372              <access>read-write</access>
38373            </field>
38374            <field>
38375              <name>POLARITY</name>
38376              <description>Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality.</description>
38377              <bitRange>[6:6]</bitRange>
38378              <access>read-write</access>
38379            </field>
38380            <field>
38381              <name>DROP_ON_PARITY_ERROR</name>
38382              <description>Behavior when a parity check fails. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames may be dropped with this field).</description>
38383              <bitRange>[8:8]</bitRange>
38384              <access>read-write</access>
38385            </field>
38386            <field>
38387              <name>DROP_ON_FRAME_ERROR</name>
38388              <description>Behavior when an error is detected in a start or stop period. When '0', received data is send to the RX FIFO. When '1', received data is dropped and lost.</description>
38389              <bitRange>[9:9]</bitRange>
38390              <access>read-write</access>
38391            </field>
38392            <field>
38393              <name>MP_MODE</name>
38394              <description>Multi-processor mode. When '1', multi-processor mode is enabled. In this mode, RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode, the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is '0'). A received address is matched with RX_MATCH.DATA and RX_MATCH.MASK. In the case of a match, subsequent received data are sent to the RX FIFO. In the case of NO match, subsequent received data are dropped.</description>
38395              <bitRange>[10:10]</bitRange>
38396              <access>read-write</access>
38397            </field>
38398            <field>
38399              <name>LIN_MODE</name>
38400              <description>Only applicable in standard UART submode. When '1', the receiver performs break detection and baud rate detection on the incoming data. First, break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies the minimum required amount of bit periods. Successful break detection sets the INTR_RX.BREAK_DETECT interrupt cause to '1'. Second, baud rate detection counts the amount of peripheral clock periods that are use to receive the synchronization byte (0x55; least significant bit first). The count is available through UART_RX_STATUS.BR_COUNTER. Successful baud rate detection sets the INTR_RX.BAUD_DETECT interrupt cause to '1' (BR_COUNTER is reliable). This functionality is used to synchronize/refine the receiver clock to the transmitter clock. The receiver software can use the BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte.</description>
38401              <bitRange>[12:12]</bitRange>
38402              <access>read-write</access>
38403            </field>
38404            <field>
38405              <name>SKIP_START</name>
38406              <description>Only applicable in standard UART submode. When '1', the receiver skips start bit detection for the first received data frame. Instead, it synchronizes on the first received data frame bit, which should be a '1'. This functionality is intended for wake up from DeepSleep when receiving a data frame. The transition from idle ('1') to START ('0') on the RX line is used to wake up the CPU. The transition detection (and the associated wake up functionality) is performed by the GPIO2 IP. The woken up CPU will enable the SCB's UART receiver functionality. Once enabled, it is assumed that the START bit is ongoing (the CPU wakeup and SCB enable time should be less than the START bit period). The SCB will synchronize to a '0' to '1' transition, which indicates the first data frame bit is received (first data frame bit should be '1'). After synchronization to the first data frame bit, the SCB will resume normal UART functionality: subsequent data frames will be synchronized on the receipt of a START bit.</description>
38407              <bitRange>[13:13]</bitRange>
38408              <access>read-write</access>
38409            </field>
38410            <field>
38411              <name>BREAK_WIDTH</name>
38412              <description>Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once, the break is detected, the INTR_RX.BREAK_DETECT bit is set to '1'. Note that break detection precedes baud rate detection, which is used to synchronize/refine the receiver clock to the transmitter clock. As a result, break detection operates with an unsynchronized/unrefined receiver clock. Therefore, the receiver's definition of a bit period is imprecise and the setting of this field should take this imprecision into account. The LIN standard also accounts for this imprecision: a LIN start bit followed by 8 data bits allows for up to 9 consecutive '0' bit periods during regular transmission, whereas the LIN break detection should be at least 13 consecutive '0' bit periods. This provides for a margin of 4 bit periods. Therefore, the default value of this field is set to 10, representing a minimal break field with of 10+1 = 11 bit periods; a value in between the 9 consecutive bit periods of a regular transmission and the 13 consecutive bit periods of a break field. This provides for slight imprecisions of the receiver clock wrt. the transmitter clock. There should not be a need to program this field to any value other than its default value.</description>
38413              <bitRange>[19:16]</bitRange>
38414              <access>read-write</access>
38415            </field>
38416          </fields>
38417        </register>
38418        <register>
38419          <name>UART_RX_STATUS</name>
38420          <description>UART receiver status</description>
38421          <addressOffset>0x4C</addressOffset>
38422          <size>32</size>
38423          <access>read-only</access>
38424          <resetValue>0x0</resetValue>
38425          <resetMask>0x0</resetMask>
38426          <fields>
38427            <field>
38428              <name>BR_COUNTER</name>
38429              <description>Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period. This field has valid data when INTR_RX.BAUD_DETECT is set to '1'.</description>
38430              <bitRange>[11:0]</bitRange>
38431              <access>read-only</access>
38432            </field>
38433          </fields>
38434        </register>
38435        <register>
38436          <name>UART_FLOW_CTRL</name>
38437          <description>UART flow control</description>
38438          <addressOffset>0x50</addressOffset>
38439          <size>32</size>
38440          <access>read-write</access>
38441          <resetValue>0x0</resetValue>
38442          <resetMask>0x30100FF</resetMask>
38443          <fields>
38444            <field>
38445              <name>TRIGGER_LEVEL</name>
38446              <description>Trigger level. When the receiver FIFO has less entries than the amount of this field, a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0', flow control is effectively SW disabled (may be useful for debug purposes).</description>
38447              <bitRange>[7:0]</bitRange>
38448              <access>read-write</access>
38449            </field>
38450            <field>
38451              <name>RTS_POLARITY</name>
38452              <description>Polarity of the RTS output signal 'uart_rts_out':
38453'0': RTS is low/'0' active; 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive.
38454'1': RTS is high/'1' active; 'uart_rts_out' is '1' when active and 'uart_rts_out' is '0' when inactive.
38455
38456During IP reset (Hibernate system power mode), 'uart_rts_out' is '1'. This represents an inactive state assuming a low/'0' active polarity.</description>
38457              <bitRange>[16:16]</bitRange>
38458              <access>read-write</access>
38459            </field>
38460            <field>
38461              <name>CTS_POLARITY</name>
38462              <description>Polarity of the CTS input signal 'uart_cts_in':
38463'0': CTS is low/'0' active; 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive.
38464'1': CTS is high/'1' active; 'uart_cts_in' is '1' when active and 'uart_cts_in' is '0' when inactive.</description>
38465              <bitRange>[24:24]</bitRange>
38466              <access>read-write</access>
38467            </field>
38468            <field>
38469              <name>CTS_ENABLED</name>
38470              <description>Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:
38471'0': Disabled. The UART transmitter ignores 'uart_cts_in', and transmits when a data frame is available for transmission in the TX FIFO or the TX shift register.
38472'1': Enabled. The UART transmitter uses 'uart_cts_in' to qualify the transmission of data. It transmits when 'uart_cts_in' is active and a data frame is available for transmission in the TX FIFO or the TX shift register.
38473
38474If UART_CTRL.LOOPBACK is '1', 'uart_cts_in' is connected to 'uart_rts_out' in the IP (both signals are subjected to signal polarity changes as indicated by RTS_POLARITY and CTS_POLARITY).</description>
38475              <bitRange>[25:25]</bitRange>
38476              <access>read-write</access>
38477            </field>
38478          </fields>
38479        </register>
38480        <register>
38481          <name>I2C_CTRL</name>
38482          <description>I2C control</description>
38483          <addressOffset>0x60</addressOffset>
38484          <size>32</size>
38485          <access>read-write</access>
38486          <resetValue>0xFB88</resetValue>
38487          <resetMask>0xC001FBFF</resetMask>
38488          <fields>
38489            <field>
38490              <name>HIGH_PHASE_OVS</name>
38491              <description>Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5, 15] with input signal median filtering and [4, 15] without input signal median filtering.
38492
38493The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular interface (IF) high time to guarantee functional correct behavior. With input signal median filtering, the IF high time should be &gt;= 6 IP clock cycles and &lt;= 16 IP clock cycles. Without input signal median filtering, the IF high time should be &gt;= 5 IP clock cycles and &lt;= 16 IP clock cycles.</description>
38494              <bitRange>[3:0]</bitRange>
38495              <access>read-write</access>
38496            </field>
38497            <field>
38498              <name>LOW_PHASE_OVS</name>
38499              <description>Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering.
38500
38501The field is only used in master mode. In slave mode, the field is NOT used. However, there is a frequency requirement for the IP clock wrt. the regular (no stretching) interface (IF) low time to guarantee functional correct behavior. With input signal median filtering, the IF low time should be &gt;= 8 IP clock cycles and &lt;= 16 IP clock cycles. Without input signal median filtering, the IF low time should be &gt;= 7 IP clock cycles and &lt;= 16 IP clock cycles.</description>
38502              <bitRange>[7:4]</bitRange>
38503              <access>read-write</access>
38504            </field>
38505            <field>
38506              <name>M_READY_DATA_ACK</name>
38507              <description>When '1', a received data element by the master is immediately ACK'd when the receiver FIFO is not full.</description>
38508              <bitRange>[8:8]</bitRange>
38509              <access>read-write</access>
38510            </field>
38511            <field>
38512              <name>M_NOT_READY_DATA_NACK</name>
38513              <description>When '1', a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0', clock stretching is used instead (till the receiver FIFO is no longer full).</description>
38514              <bitRange>[9:9]</bitRange>
38515              <access>read-write</access>
38516            </field>
38517            <field>
38518              <name>S_GENERAL_IGNORE</name>
38519              <description>When '1', a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure.</description>
38520              <bitRange>[11:11]</bitRange>
38521              <access>read-write</access>
38522            </field>
38523            <field>
38524              <name>S_READY_ADDR_ACK</name>
38525              <description>When '1', a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'.</description>
38526              <bitRange>[12:12]</bitRange>
38527              <access>read-write</access>
38528            </field>
38529            <field>
38530              <name>S_READY_DATA_ACK</name>
38531              <description>When '1', a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode, this field should be set to '1'.</description>
38532              <bitRange>[13:13]</bitRange>
38533              <access>read-write</access>
38534            </field>
38535            <field>
38536              <name>S_NOT_READY_ADDR_NACK</name>
38537              <description>For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:
38538- EC_AM is '0', EC_OP is '0' and non EZ mode.
38539Functionality is as follows:
38540- 1: a received (matching) slave address is immediately NACK'd when the receiver FIFO is full.
38541- 0: clock stretching is performed (till the receiver FIFO is no longer full).
38542
38543For externally clocked logic (EC_AM is '1') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when (NOT used when EC_AM is '1' and EC_OP is '1' and address match and EZ mode):
38544- EC_AM is '1' and EC_OP is '0'.
38545- EC_AM is '1' and general call address match.
38546- EC_AM is '1' and non EZ mode.
38547Functionality is as follows:
38548- 1: a received (matching or general) slave address is always immediately NACK'd. There are two possibilities: 1). the internally clocked logic is enabled (we are in Active system power mode) and it handles the rest of the current transfer. In this case the I2C master will not observe the NACK. 2). the internally clocked logic is not enabled (we are in DeepSleep system power mode). In this case the I2C master will observe the NACK and may retry the transfer in the future (which gives the internally clocked logic the time to wake up from DeepSleep system power mode).
38549- 0: clock stretching is performed (till the internally clocked logic takes over). The internally clocked logic will handle the ongoing transfer as soon as it is enabled.</description>
38550              <bitRange>[14:14]</bitRange>
38551              <access>read-write</access>
38552            </field>
38553            <field>
38554              <name>S_NOT_READY_DATA_NACK</name>
38555              <description>For internally clocked logic only. Only used when:
38556- non EZ mode.
38557Functionality is as follows:
38558- 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full.
38559- 0: clock stretching is performed (till the receiver FIFO is no longer full).</description>
38560              <bitRange>[15:15]</bitRange>
38561              <access>read-write</access>
38562            </field>
38563            <field>
38564              <name>LOOPBACK</name>
38565              <description>Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0', the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1', I2C SCL and SDA lines are routed internally in the peripheral, and as a result unaffected by other I2C devices. This allows a SCB I2C peripheral to address itself.</description>
38566              <bitRange>[16:16]</bitRange>
38567              <access>read-write</access>
38568            </field>
38569            <field>
38570              <name>SLAVE_MODE</name>
38571              <description>Slave mode enabled ('1') or not ('0').</description>
38572              <bitRange>[30:30]</bitRange>
38573              <access>read-write</access>
38574            </field>
38575            <field>
38576              <name>MASTER_MODE</name>
38577              <description>Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself.</description>
38578              <bitRange>[31:31]</bitRange>
38579              <access>read-write</access>
38580            </field>
38581          </fields>
38582        </register>
38583        <register>
38584          <name>I2C_STATUS</name>
38585          <description>I2C status</description>
38586          <addressOffset>0x64</addressOffset>
38587          <size>32</size>
38588          <access>read-only</access>
38589          <resetValue>0x0</resetValue>
38590          <resetMask>0x31</resetMask>
38591          <fields>
38592            <field>
38593              <name>BUS_BUSY</name>
38594              <description>I2C bus is busy. The bus is considered busy ('1'), from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0'), from the time a STOP is detected. If the IP is disabled, BUS_BUSY is '0'. After enabling the IP, it takes time for the BUS_BUSY to detect a busy bus. This time is the maximum high time of the SCL line. For a 100 kHz interface frequency, this maximum high time may last roughly 5 us (half a bit period).
38595
38596For single master systems, BUS_BUSY does not have to be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START (no bus collisions).
38597
38598For multi-master systems, BUS_BUSY can be used to detect an idle bus before a master starts a transfer using I2C_M_CMD.M_START_ON_IDLE (to prevent bus collisions).</description>
38599              <bitRange>[0:0]</bitRange>
38600              <access>read-only</access>
38601            </field>
38602            <field>
38603              <name>I2C_EC_BUSY</name>
38604              <description>Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and CURR_EZ_ADDR are reliable.</description>
38605              <bitRange>[1:1]</bitRange>
38606              <access>read-only</access>
38607            </field>
38608            <field>
38609              <name>S_READ</name>
38610              <description>I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START, REPEATED START, STOP or an address, this field is '0''.</description>
38611              <bitRange>[4:4]</bitRange>
38612              <access>read-only</access>
38613            </field>
38614            <field>
38615              <name>M_READ</name>
38616              <description>I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START, REPEATED START, STOP or an address, this field is '0''.</description>
38617              <bitRange>[5:5]</bitRange>
38618              <access>read-only</access>
38619            </field>
38620            <field>
38621              <name>CURR_EZ_ADDR</name>
38622              <description>I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1'), as clock domain synchronization is not performed in the design.</description>
38623              <bitRange>[15:8]</bitRange>
38624              <access>read-only</access>
38625            </field>
38626            <field>
38627              <name>BASE_EZ_ADDR</name>
38628              <description>I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable, as clock domain synchronization is not performed in the design.</description>
38629              <bitRange>[23:16]</bitRange>
38630              <access>read-only</access>
38631            </field>
38632          </fields>
38633        </register>
38634        <register>
38635          <name>I2C_M_CMD</name>
38636          <description>I2C master command</description>
38637          <addressOffset>0x68</addressOffset>
38638          <size>32</size>
38639          <access>read-write</access>
38640          <resetValue>0x0</resetValue>
38641          <resetMask>0x1F</resetMask>
38642          <fields>
38643            <field>
38644              <name>M_START</name>
38645              <description>When '1', transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START is transmitted when the master state machine is not in the default state, but is working on an ongoing transaction. The REPEATED START can only be transmitted after a NACK or ACK has been received for a transmitted data element or after a NACK has been transmitted for a received data element. When this action is performed, the hardware sets this field to '0'.</description>
38646              <bitRange>[0:0]</bitRange>
38647              <access>read-write</access>
38648            </field>
38649            <field>
38650              <name>M_START_ON_IDLE</name>
38651              <description>When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been detected on the bus (default/reset value of BUSY is '0') . A START is only transmitted when the master state machine is in the default state. When this action is performed, the hardware sets this field to '0'.</description>
38652              <bitRange>[1:1]</bitRange>
38653              <access>read-write</access>
38654            </field>
38655            <field>
38656              <name>M_ACK</name>
38657              <description>When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'.</description>
38658              <bitRange>[2:2]</bitRange>
38659              <access>read-write</access>
38660            </field>
38661            <field>
38662              <name>M_NACK</name>
38663              <description>When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'.</description>
38664              <bitRange>[3:3]</bitRange>
38665              <access>read-write</access>
38666            </field>
38667            <field>
38668              <name>M_STOP</name>
38669              <description>When '1', attempt to transmit a STOP. When this action is performed, the hardware sets this field to '0'.
38670 I2C_M_CMD.M_START has a higher priority than this command: in situations where both a STOP and a REPEATED START could be transmitted, M_START takes precedence over M_STOP.</description>
38671              <bitRange>[4:4]</bitRange>
38672              <access>read-write</access>
38673            </field>
38674          </fields>
38675        </register>
38676        <register>
38677          <name>I2C_S_CMD</name>
38678          <description>I2C slave command</description>
38679          <addressOffset>0x6C</addressOffset>
38680          <size>32</size>
38681          <access>read-write</access>
38682          <resetValue>0x0</resetValue>
38683          <resetMask>0x3</resetMask>
38684          <fields>
38685            <field>
38686              <name>S_ACK</name>
38687              <description>When '1', attempt to transmit an acknowledgement (ACK). When this action is performed, the hardware sets this field to '0'. In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode).</description>
38688              <bitRange>[0:0]</bitRange>
38689              <access>read-write</access>
38690            </field>
38691            <field>
38692              <name>S_NACK</name>
38693              <description>When '1', attempt to transmit a negative acknowledgement (NACK). When this action is performed, the hardware sets this field to '0'.  In EZ mode, this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher priority than I2C_S_CMD.S_ACK, I2C_CTRL.S_READY_ADDR_ACK or I2C_CTRL.S_READY_DATA_ACK.</description>
38694              <bitRange>[1:1]</bitRange>
38695              <access>read-write</access>
38696            </field>
38697          </fields>
38698        </register>
38699        <register>
38700          <name>I2C_CFG</name>
38701          <description>I2C configuration</description>
38702          <addressOffset>0x70</addressOffset>
38703          <size>32</size>
38704          <access>read-write</access>
38705          <resetValue>0x2A1013</resetValue>
38706          <resetMask>0x303F1313</resetMask>
38707          <fields>
38708            <field>
38709              <name>SDA_IN_FILT_TRIM</name>
38710              <description>Trim bits for 'i2c_sda_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values.
38711
38712SDA_IN_FILT_TRIM[1] is used to enable I2CS_EC or SPIS_EC access to internal SRAM memory.
387131: enable clock_scb_en, has no effect on ec_busy_pp
387140: disable clock_scb_en, enable ec_busy_pp (grant I2CS_EC or SPIS_EC access)</description>
38715              <bitRange>[1:0]</bitRange>
38716              <access>read-write</access>
38717            </field>
38718            <field>
38719              <name>SDA_IN_FILT_SEL</name>
38720              <description>Selection of 'i2c_sda_in' filter delay:
38721'0': 0 ns.
38722'1: 50 ns (filter enabled).</description>
38723              <bitRange>[4:4]</bitRange>
38724              <access>read-write</access>
38725            </field>
38726            <field>
38727              <name>SCL_IN_FILT_TRIM</name>
38728              <description>Trim bits for 'i2c_scl_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values.</description>
38729              <bitRange>[9:8]</bitRange>
38730              <access>read-write</access>
38731            </field>
38732            <field>
38733              <name>SCL_IN_FILT_SEL</name>
38734              <description>Selection of 'i2c_scl_in' filter delay:
38735'0': 0 ns.
38736'1: 50 ns (filter enabled).</description>
38737              <bitRange>[12:12]</bitRange>
38738              <access>read-write</access>
38739            </field>
38740            <field>
38741              <name>SDA_OUT_FILT0_TRIM</name>
38742              <description>Trim bits for 'i2c_sda_out' 50 ns filter 0. See s8i2cs BROS (001-59539) for more details on the trim bit values.</description>
38743              <bitRange>[17:16]</bitRange>
38744              <access>read-write</access>
38745            </field>
38746            <field>
38747              <name>SDA_OUT_FILT1_TRIM</name>
38748              <description>Trim bits for 'i2c_sda_out' 50 ns filter 1. See s8i2cs BROS (001-59539) for more details on the trim bit values.</description>
38749              <bitRange>[19:18]</bitRange>
38750              <access>read-write</access>
38751            </field>
38752            <field>
38753              <name>SDA_OUT_FILT2_TRIM</name>
38754              <description>Trim bits for 'i2c_sda_out' 50 ns filter 2. See s8i2cs BROS (001-59539) for more details on the trim bit values.</description>
38755              <bitRange>[21:20]</bitRange>
38756              <access>read-write</access>
38757            </field>
38758            <field>
38759              <name>SDA_OUT_FILT_SEL</name>
38760              <description>Selection of cumulative 'i2c_sda_out' filter delay:
38761'0': 0 ns.
38762'1': 50 ns (filter 0 enabled).
38763'2': 100 ns (filters 0 and 1 enabled).
38764'3': 150 ns (filters 0, 1 and 2 enabled).</description>
38765              <bitRange>[29:28]</bitRange>
38766              <access>read-write</access>
38767            </field>
38768          </fields>
38769        </register>
38770        <register>
38771          <name>TX_CTRL</name>
38772          <description>Transmitter control</description>
38773          <addressOffset>0x200</addressOffset>
38774          <size>32</size>
38775          <access>read-write</access>
38776          <resetValue>0x107</resetValue>
38777          <resetMask>0x1010F</resetMask>
38778          <fields>
38779            <field>
38780              <name>DATA_WIDTH</name>
38781              <description>Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7.</description>
38782              <bitRange>[3:0]</bitRange>
38783              <access>read-write</access>
38784            </field>
38785            <field>
38786              <name>MSB_FIRST</name>
38787              <description>Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'.</description>
38788              <bitRange>[8:8]</bitRange>
38789              <access>read-write</access>
38790            </field>
38791            <field>
38792              <name>OPEN_DRAIN</name>
38793              <description>Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'.
38794'0': Normal operation mode. Typically, this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by a single IO cell. In this operation mode, for an IO cell 'xxx' that is used as an output, the 'xxx_out_en' output enable signal is typically constant '1' the 'xxx_out' output is the outputted value. In other words, in normal operation mode, the 'xxx_out' output is used to control the IO cell output value: 'xxx_out' is '0' to drive an IO cell output value of '0' and 'xxx_out' is '1' to drive an IO cell output value of '1'.
38795'1': Open drain operation mode. Typically this operation mode is used for IO cells that are connected to (board) wires/lines that are driven by multiple IO cells (possibly on multiple chips). In this operation mode, for and IO cell 'xxx' that is used as an output, the 'xxx_out_en' output controls the outputted value. Typically, open drain operation mode drives low/'0' and the 'xxx_out' output is constant '1'. In other words, in open drain operation mode, the 'xxx_out_en' output is used to control the IO cell output value: in drive low/'0' mode: 'xxx_out_en' is '1' (drive enabled) to drive an IO cell output value of '0' and 'xxx_out_en' is '1' (drive disabled) to not drive an IO cell output value (another IO cell can drive the wire/line or a pull up results in a wire/line value '1').
38796
38797The open drain mode is supported for:
38798- I2C mode, 'i2c_scl' and 'i2c_sda' IO cells.
38799- UART mode, 'uart_tx' IO cell.
38800- SPI mode, 'spi_miso' IO cell.</description>
38801              <bitRange>[16:16]</bitRange>
38802              <access>read-write</access>
38803            </field>
38804          </fields>
38805        </register>
38806        <register>
38807          <name>TX_FIFO_CTRL</name>
38808          <description>Transmitter FIFO control</description>
38809          <addressOffset>0x204</addressOffset>
38810          <size>32</size>
38811          <access>read-write</access>
38812          <resetValue>0x0</resetValue>
38813          <resetMask>0x300FF</resetMask>
38814          <fields>
38815            <field>
38816              <name>TRIGGER_LEVEL</name>
38817              <description>Trigger level. When the transmitter FIFO has less entries than the number of this field, a transmitter trigger event INTR_TX.TRIGGER is generated.</description>
38818              <bitRange>[7:0]</bitRange>
38819              <access>read-write</access>
38820            </field>
38821            <field>
38822              <name>CLEAR</name>
38823              <description>When '1', the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
38824              <bitRange>[16:16]</bitRange>
38825              <access>read-write</access>
38826            </field>
38827            <field>
38828              <name>FREEZE</name>
38829              <description>When '1', hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer.</description>
38830              <bitRange>[17:17]</bitRange>
38831              <access>read-write</access>
38832            </field>
38833          </fields>
38834        </register>
38835        <register>
38836          <name>TX_FIFO_STATUS</name>
38837          <description>Transmitter FIFO status</description>
38838          <addressOffset>0x208</addressOffset>
38839          <size>32</size>
38840          <access>read-only</access>
38841          <resetValue>0x0</resetValue>
38842          <resetMask>0xFFFF81FF</resetMask>
38843          <fields>
38844            <field>
38845              <name>USED</name>
38846              <description>Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2).</description>
38847              <bitRange>[8:0]</bitRange>
38848              <access>read-only</access>
38849            </field>
38850            <field>
38851              <name>SR_VALID</name>
38852              <description>Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working register and holds the data frame that is currently transmitted (when the protocol state machine is transmitting a data frame) or the data frame that is transmitted next (when the protocol state machine is not transmitting a data frame).</description>
38853              <bitRange>[15:15]</bitRange>
38854              <access>read-only</access>
38855            </field>
38856            <field>
38857              <name>RD_PTR</name>
38858              <description>FIFO read pointer: FIFO location from which a data frame is read by the hardware.</description>
38859              <bitRange>[23:16]</bitRange>
38860              <access>read-only</access>
38861            </field>
38862            <field>
38863              <name>WR_PTR</name>
38864              <description>FIFO write pointer: FIFO location at which a new data frame is written.</description>
38865              <bitRange>[31:24]</bitRange>
38866              <access>read-only</access>
38867            </field>
38868          </fields>
38869        </register>
38870        <register>
38871          <name>TX_FIFO_WR</name>
38872          <description>Transmitter FIFO write</description>
38873          <addressOffset>0x240</addressOffset>
38874          <size>32</size>
38875          <access>write-only</access>
38876          <resetValue>0x0</resetValue>
38877          <resetMask>0xFFFF</resetMask>
38878          <fields>
38879            <field>
38880              <name>DATA</name>
38881              <description>Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used.
38882
38883A write to a full TX FIFO sets INTR_TX.OVERFLOW to '1'.</description>
38884              <bitRange>[15:0]</bitRange>
38885              <access>write-only</access>
38886            </field>
38887          </fields>
38888        </register>
38889        <register>
38890          <name>RX_CTRL</name>
38891          <description>Receiver control</description>
38892          <addressOffset>0x300</addressOffset>
38893          <size>32</size>
38894          <access>read-write</access>
38895          <resetValue>0x107</resetValue>
38896          <resetMask>0x30F</resetMask>
38897          <fields>
38898            <field>
38899              <name>DATA_WIDTH</name>
38900              <description>Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start, parity and stop bits. For UART mode, the valid range is [3, 8]. For SPI, the valid range is [3, 15]. For I2C the only valid value is 7. In EZ mode (for both SPI and I2C), the only valid value is 7.</description>
38901              <bitRange>[3:0]</bitRange>
38902              <access>read-write</access>
38903            </field>
38904            <field>
38905              <name>MSB_FIRST</name>
38906              <description>Least significant bit first ('0') or most significant bit first ('1'). For I2C, this field should be '1'.</description>
38907              <bitRange>[8:8]</bitRange>
38908              <access>read-write</access>
38909            </field>
38910            <field>
38911              <name>MEDIAN</name>
38912              <description>Median filter. When '1', a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However, its requires higher oversampling values. For UART IrDA submode, this field should always be '1'.</description>
38913              <bitRange>[9:9]</bitRange>
38914              <access>read-write</access>
38915            </field>
38916          </fields>
38917        </register>
38918        <register>
38919          <name>RX_FIFO_CTRL</name>
38920          <description>Receiver FIFO control</description>
38921          <addressOffset>0x304</addressOffset>
38922          <size>32</size>
38923          <access>read-write</access>
38924          <resetValue>0x0</resetValue>
38925          <resetMask>0x300FF</resetMask>
38926          <fields>
38927            <field>
38928              <name>TRIGGER_LEVEL</name>
38929              <description>Trigger level. When the receiver FIFO has more entries than the number of this field, a receiver trigger event INTR_RX.TRIGGER is generated.</description>
38930              <bitRange>[7:0]</bitRange>
38931              <access>read-write</access>
38932            </field>
38933            <field>
38934              <name>CLEAR</name>
38935              <description>When '1', the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
38936              <bitRange>[16:16]</bitRange>
38937              <access>read-write</access>
38938            </field>
38939            <field>
38940              <name>FREEZE</name>
38941              <description>When '1', hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer.</description>
38942              <bitRange>[17:17]</bitRange>
38943              <access>read-write</access>
38944            </field>
38945          </fields>
38946        </register>
38947        <register>
38948          <name>RX_FIFO_STATUS</name>
38949          <description>Receiver FIFO status</description>
38950          <addressOffset>0x308</addressOffset>
38951          <size>32</size>
38952          <access>read-only</access>
38953          <resetValue>0x0</resetValue>
38954          <resetMask>0xFFFF81FF</resetMask>
38955          <fields>
38956            <field>
38957              <name>USED</name>
38958              <description>Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2).</description>
38959              <bitRange>[8:0]</bitRange>
38960              <access>read-only</access>
38961            </field>
38962            <field>
38963              <name>SR_VALID</name>
38964              <description>Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register is a working register and holds the data frame that is currently being received (when the protocol state machine is receiving a data frame).</description>
38965              <bitRange>[15:15]</bitRange>
38966              <access>read-only</access>
38967            </field>
38968            <field>
38969              <name>RD_PTR</name>
38970              <description>FIFO read pointer: FIFO location from which a data frame is read.</description>
38971              <bitRange>[23:16]</bitRange>
38972              <access>read-only</access>
38973            </field>
38974            <field>
38975              <name>WR_PTR</name>
38976              <description>FIFO write pointer: FIFO location at which a new data frame is written by the hardware.</description>
38977              <bitRange>[31:24]</bitRange>
38978              <access>read-only</access>
38979            </field>
38980          </fields>
38981        </register>
38982        <register>
38983          <name>RX_MATCH</name>
38984          <description>Slave address and mask</description>
38985          <addressOffset>0x310</addressOffset>
38986          <size>32</size>
38987          <access>read-write</access>
38988          <resetValue>0x0</resetValue>
38989          <resetMask>0xFF00FF</resetMask>
38990          <fields>
38991            <field>
38992              <name>ADDR</name>
38993              <description>Slave device address.
38994
38995In UART multi-processor mode, all 8 bits are used.
38996
38997In I2C slave mode, only bits 7 down to 1 are used. This reflects the organization of the first transmitted byte in a I2C transfer: the first 7 bits represent the address of the addressed slave, and the last 1 bit is a read/write indicator ('0': write, '1': read).</description>
38998              <bitRange>[7:0]</bitRange>
38999              <access>read-write</access>
39000            </field>
39001            <field>
39002              <name>MASK</name>
39003              <description>Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR &amp; MASK) == ('slave address' &amp; MASK)).</description>
39004              <bitRange>[23:16]</bitRange>
39005              <access>read-write</access>
39006            </field>
39007          </fields>
39008        </register>
39009        <register>
39010          <name>RX_FIFO_RD</name>
39011          <description>Receiver FIFO read</description>
39012          <addressOffset>0x340</addressOffset>
39013          <size>32</size>
39014          <access>read-only</access>
39015          <resetValue>0x0</resetValue>
39016          <resetMask>0x0</resetMask>
39017          <fields>
39018            <field>
39019              <name>DATA</name>
39020              <description>Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used.
39021
39022This register has a side effect when read by software: a data frame is removed from the FIFO. This may be undesirable during debug; i.e. a read during debug should NOT have a side effect. To this end, the IP uses the AHB-Lite 'hmaster[0]' input signal. When this signal is '1' in the address cycle of a bus transfer, a read transfer will not have a side effect. As a result, a read from this register will not remove a data frame from the FIFO. As a result, a read from this register behaves as a read from the SCB_RX_FIFO_RD_SILENT register.
39023
39024A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'.</description>
39025              <bitRange>[15:0]</bitRange>
39026              <access>read-only</access>
39027            </field>
39028          </fields>
39029        </register>
39030        <register>
39031          <name>RX_FIFO_RD_SILENT</name>
39032          <description>Receiver FIFO read silent</description>
39033          <addressOffset>0x344</addressOffset>
39034          <size>32</size>
39035          <access>read-only</access>
39036          <resetValue>0x0</resetValue>
39037          <resetMask>0x0</resetMask>
39038          <fields>
39039            <field>
39040              <name>DATA</name>
39041              <description>Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.BYTE_MODE is '1', only DATA[7:0] are used.
39042
39043A read from an empty RX FIFO sets INTR_RX.UNDERFLOW to '1'.</description>
39044              <bitRange>[15:0]</bitRange>
39045              <access>read-only</access>
39046            </field>
39047          </fields>
39048        </register>
39049        <register>
39050          <name>INTR_CAUSE</name>
39051          <description>Active clocked interrupt signal</description>
39052          <addressOffset>0xE00</addressOffset>
39053          <size>32</size>
39054          <access>read-only</access>
39055          <resetValue>0x0</resetValue>
39056          <resetMask>0x3F</resetMask>
39057          <fields>
39058            <field>
39059              <name>M</name>
39060              <description>Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0.</description>
39061              <bitRange>[0:0]</bitRange>
39062              <access>read-only</access>
39063            </field>
39064            <field>
39065              <name>S</name>
39066              <description>Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0.</description>
39067              <bitRange>[1:1]</bitRange>
39068              <access>read-only</access>
39069            </field>
39070            <field>
39071              <name>TX</name>
39072              <description>Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0.</description>
39073              <bitRange>[2:2]</bitRange>
39074              <access>read-only</access>
39075            </field>
39076            <field>
39077              <name>RX</name>
39078              <description>Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0.</description>
39079              <bitRange>[3:3]</bitRange>
39080              <access>read-only</access>
39081            </field>
39082            <field>
39083              <name>I2C_EC</name>
39084              <description>Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0.</description>
39085              <bitRange>[4:4]</bitRange>
39086              <access>read-only</access>
39087            </field>
39088            <field>
39089              <name>SPI_EC</name>
39090              <description>Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0.</description>
39091              <bitRange>[5:5]</bitRange>
39092              <access>read-only</access>
39093            </field>
39094          </fields>
39095        </register>
39096        <register>
39097          <name>INTR_I2C_EC</name>
39098          <description>Externally clocked I2C interrupt request</description>
39099          <addressOffset>0xE80</addressOffset>
39100          <size>32</size>
39101          <access>read-write</access>
39102          <resetValue>0x0</resetValue>
39103          <resetMask>0xF</resetMask>
39104          <fields>
39105            <field>
39106              <name>WAKE_UP</name>
39107              <description>Wake up request. Active on incoming slave request (with address match).
39108
39109Only used when EC_AM is '1'.</description>
39110              <bitRange>[0:0]</bitRange>
39111              <access>read-write</access>
39112            </field>
39113            <field>
39114              <name>EZ_STOP</name>
39115              <description>STOP detection. Activated on the end of a every transfer (I2C STOP).
39116
39117Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'.</description>
39118              <bitRange>[1:1]</bitRange>
39119              <access>read-write</access>
39120            </field>
39121            <field>
39122              <name>EZ_WRITE_STOP</name>
39123              <description>STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a  transfer that only writes the base address does NOT activate this event.
39124
39125Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'.</description>
39126              <bitRange>[2:2]</bitRange>
39127              <access>read-write</access>
39128            </field>
39129            <field>
39130              <name>EZ_READ_STOP</name>
39131              <description>STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from.
39132
39133Only available for a slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is '1'.</description>
39134              <bitRange>[3:3]</bitRange>
39135              <access>read-write</access>
39136            </field>
39137          </fields>
39138        </register>
39139        <register>
39140          <name>INTR_I2C_EC_MASK</name>
39141          <description>Externally clocked I2C interrupt mask</description>
39142          <addressOffset>0xE88</addressOffset>
39143          <size>32</size>
39144          <access>read-write</access>
39145          <resetValue>0x0</resetValue>
39146          <resetMask>0xF</resetMask>
39147          <fields>
39148            <field>
39149              <name>WAKE_UP</name>
39150              <description>Mask bit for corresponding bit in interrupt request register.</description>
39151              <bitRange>[0:0]</bitRange>
39152              <access>read-write</access>
39153            </field>
39154            <field>
39155              <name>EZ_STOP</name>
39156              <description>Mask bit for corresponding bit in interrupt request register.</description>
39157              <bitRange>[1:1]</bitRange>
39158              <access>read-write</access>
39159            </field>
39160            <field>
39161              <name>EZ_WRITE_STOP</name>
39162              <description>Mask bit for corresponding bit in interrupt request register.</description>
39163              <bitRange>[2:2]</bitRange>
39164              <access>read-write</access>
39165            </field>
39166            <field>
39167              <name>EZ_READ_STOP</name>
39168              <description>Mask bit for corresponding bit in interrupt request register.</description>
39169              <bitRange>[3:3]</bitRange>
39170              <access>read-write</access>
39171            </field>
39172          </fields>
39173        </register>
39174        <register>
39175          <name>INTR_I2C_EC_MASKED</name>
39176          <description>Externally clocked I2C interrupt masked</description>
39177          <addressOffset>0xE8C</addressOffset>
39178          <size>32</size>
39179          <access>read-only</access>
39180          <resetValue>0x0</resetValue>
39181          <resetMask>0xF</resetMask>
39182          <fields>
39183            <field>
39184              <name>WAKE_UP</name>
39185              <description>Logical and of corresponding request and mask bits.</description>
39186              <bitRange>[0:0]</bitRange>
39187              <access>read-only</access>
39188            </field>
39189            <field>
39190              <name>EZ_STOP</name>
39191              <description>Logical and of corresponding request and mask bits.</description>
39192              <bitRange>[1:1]</bitRange>
39193              <access>read-only</access>
39194            </field>
39195            <field>
39196              <name>EZ_WRITE_STOP</name>
39197              <description>Logical and of corresponding request and mask bits.</description>
39198              <bitRange>[2:2]</bitRange>
39199              <access>read-only</access>
39200            </field>
39201            <field>
39202              <name>EZ_READ_STOP</name>
39203              <description>Logical and of corresponding request and mask bits.</description>
39204              <bitRange>[3:3]</bitRange>
39205              <access>read-only</access>
39206            </field>
39207          </fields>
39208        </register>
39209        <register>
39210          <name>INTR_SPI_EC</name>
39211          <description>Externally clocked SPI interrupt request</description>
39212          <addressOffset>0xEC0</addressOffset>
39213          <size>32</size>
39214          <access>read-write</access>
39215          <resetValue>0x0</resetValue>
39216          <resetMask>0xF</resetMask>
39217          <fields>
39218            <field>
39219              <name>WAKE_UP</name>
39220              <description>Wake up request. Active on incoming slave request when externally clocked selection is '1'.
39221
39222Only used when EC_AM is '1'.</description>
39223              <bitRange>[0:0]</bitRange>
39224              <access>read-write</access>
39225            </field>
39226            <field>
39227              <name>EZ_STOP</name>
39228              <description>STOP detection. Activated on the end of a every transfer (SPI deselection).
39229
39230Only available in EZ and CMD_RESP mode and when EC_OP is '1'.</description>
39231              <bitRange>[1:1]</bitRange>
39232              <access>read-write</access>
39233            </field>
39234            <field>
39235              <name>EZ_WRITE_STOP</name>
39236              <description>STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a  transfer that only writes the base address does NOT activate this event.
39237
39238Only used in EZ and CMD_RESP modes and when EC_OP is '1'.</description>
39239              <bitRange>[2:2]</bitRange>
39240              <access>read-write</access>
39241            </field>
39242            <field>
39243              <name>EZ_READ_STOP</name>
39244              <description>STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from.
39245
39246Only used in EZ and CMD_RESP modes and when EC_OP is '1'.</description>
39247              <bitRange>[3:3]</bitRange>
39248              <access>read-write</access>
39249            </field>
39250          </fields>
39251        </register>
39252        <register>
39253          <name>INTR_SPI_EC_MASK</name>
39254          <description>Externally clocked SPI interrupt mask</description>
39255          <addressOffset>0xEC8</addressOffset>
39256          <size>32</size>
39257          <access>read-write</access>
39258          <resetValue>0x0</resetValue>
39259          <resetMask>0xF</resetMask>
39260          <fields>
39261            <field>
39262              <name>WAKE_UP</name>
39263              <description>Mask bit for corresponding bit in interrupt request register.</description>
39264              <bitRange>[0:0]</bitRange>
39265              <access>read-write</access>
39266            </field>
39267            <field>
39268              <name>EZ_STOP</name>
39269              <description>Mask bit for corresponding bit in interrupt request register.</description>
39270              <bitRange>[1:1]</bitRange>
39271              <access>read-write</access>
39272            </field>
39273            <field>
39274              <name>EZ_WRITE_STOP</name>
39275              <description>Mask bit for corresponding bit in interrupt request register.</description>
39276              <bitRange>[2:2]</bitRange>
39277              <access>read-write</access>
39278            </field>
39279            <field>
39280              <name>EZ_READ_STOP</name>
39281              <description>Mask bit for corresponding bit in interrupt request register.</description>
39282              <bitRange>[3:3]</bitRange>
39283              <access>read-write</access>
39284            </field>
39285          </fields>
39286        </register>
39287        <register>
39288          <name>INTR_SPI_EC_MASKED</name>
39289          <description>Externally clocked SPI interrupt masked</description>
39290          <addressOffset>0xECC</addressOffset>
39291          <size>32</size>
39292          <access>read-only</access>
39293          <resetValue>0x0</resetValue>
39294          <resetMask>0xF</resetMask>
39295          <fields>
39296            <field>
39297              <name>WAKE_UP</name>
39298              <description>Logical and of corresponding request and mask bits.</description>
39299              <bitRange>[0:0]</bitRange>
39300              <access>read-only</access>
39301            </field>
39302            <field>
39303              <name>EZ_STOP</name>
39304              <description>Logical and of corresponding request and mask bits.</description>
39305              <bitRange>[1:1]</bitRange>
39306              <access>read-only</access>
39307            </field>
39308            <field>
39309              <name>EZ_WRITE_STOP</name>
39310              <description>Logical and of corresponding request and mask bits.</description>
39311              <bitRange>[2:2]</bitRange>
39312              <access>read-only</access>
39313            </field>
39314            <field>
39315              <name>EZ_READ_STOP</name>
39316              <description>Logical and of corresponding request and mask bits.</description>
39317              <bitRange>[3:3]</bitRange>
39318              <access>read-only</access>
39319            </field>
39320          </fields>
39321        </register>
39322        <register>
39323          <name>INTR_M</name>
39324          <description>Master interrupt request</description>
39325          <addressOffset>0xF00</addressOffset>
39326          <size>32</size>
39327          <access>read-write</access>
39328          <resetValue>0x0</resetValue>
39329          <resetMask>0x317</resetMask>
39330          <fields>
39331            <field>
39332              <name>I2C_ARB_LOST</name>
39333              <description>I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line.</description>
39334              <bitRange>[0:0]</bitRange>
39335              <access>read-write</access>
39336            </field>
39337            <field>
39338              <name>I2C_NACK</name>
39339              <description>I2C master negative acknowledgement. Set to '1', when the master receives a NACK (typically after the master transmitted the slave address or TX data).</description>
39340              <bitRange>[1:1]</bitRange>
39341              <access>read-write</access>
39342            </field>
39343            <field>
39344              <name>I2C_ACK</name>
39345              <description>I2C master acknowledgement. Set to '1', when the master receives a ACK (typically after the master transmitted the slave address or TX data).</description>
39346              <bitRange>[2:2]</bitRange>
39347              <access>read-write</access>
39348            </field>
39349            <field>
39350              <name>I2C_STOP</name>
39351              <description>I2C master STOP. Set to '1', when the master has transmitted a STOP.</description>
39352              <bitRange>[4:4]</bitRange>
39353              <access>read-write</access>
39354            </field>
39355            <field>
39356              <name>I2C_BUS_ERROR</name>
39357              <description>I2C master bus error (unexpected detection of START or STOP condition).</description>
39358              <bitRange>[8:8]</bitRange>
39359              <access>read-write</access>
39360            </field>
39361            <field>
39362              <name>SPI_DONE</name>
39363              <description>SPI master transfer done event: all data frames in the transmit FIFO are sent, the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty), and SPI select output pin is deselected.</description>
39364              <bitRange>[9:9]</bitRange>
39365              <access>read-write</access>
39366            </field>
39367          </fields>
39368        </register>
39369        <register>
39370          <name>INTR_M_SET</name>
39371          <description>Master interrupt set request</description>
39372          <addressOffset>0xF04</addressOffset>
39373          <size>32</size>
39374          <access>read-write</access>
39375          <resetValue>0x0</resetValue>
39376          <resetMask>0x317</resetMask>
39377          <fields>
39378            <field>
39379              <name>I2C_ARB_LOST</name>
39380              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39381              <bitRange>[0:0]</bitRange>
39382              <access>read-write</access>
39383            </field>
39384            <field>
39385              <name>I2C_NACK</name>
39386              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39387              <bitRange>[1:1]</bitRange>
39388              <access>read-write</access>
39389            </field>
39390            <field>
39391              <name>I2C_ACK</name>
39392              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39393              <bitRange>[2:2]</bitRange>
39394              <access>read-write</access>
39395            </field>
39396            <field>
39397              <name>I2C_STOP</name>
39398              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39399              <bitRange>[4:4]</bitRange>
39400              <access>read-write</access>
39401            </field>
39402            <field>
39403              <name>I2C_BUS_ERROR</name>
39404              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39405              <bitRange>[8:8]</bitRange>
39406              <access>read-write</access>
39407            </field>
39408            <field>
39409              <name>SPI_DONE</name>
39410              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39411              <bitRange>[9:9]</bitRange>
39412              <access>read-write</access>
39413            </field>
39414          </fields>
39415        </register>
39416        <register>
39417          <name>INTR_M_MASK</name>
39418          <description>Master interrupt mask</description>
39419          <addressOffset>0xF08</addressOffset>
39420          <size>32</size>
39421          <access>read-write</access>
39422          <resetValue>0x0</resetValue>
39423          <resetMask>0x317</resetMask>
39424          <fields>
39425            <field>
39426              <name>I2C_ARB_LOST</name>
39427              <description>Mask bit for corresponding bit in interrupt request register.</description>
39428              <bitRange>[0:0]</bitRange>
39429              <access>read-write</access>
39430            </field>
39431            <field>
39432              <name>I2C_NACK</name>
39433              <description>Mask bit for corresponding bit in interrupt request register.</description>
39434              <bitRange>[1:1]</bitRange>
39435              <access>read-write</access>
39436            </field>
39437            <field>
39438              <name>I2C_ACK</name>
39439              <description>Mask bit for corresponding bit in interrupt request register.</description>
39440              <bitRange>[2:2]</bitRange>
39441              <access>read-write</access>
39442            </field>
39443            <field>
39444              <name>I2C_STOP</name>
39445              <description>Mask bit for corresponding bit in interrupt request register.</description>
39446              <bitRange>[4:4]</bitRange>
39447              <access>read-write</access>
39448            </field>
39449            <field>
39450              <name>I2C_BUS_ERROR</name>
39451              <description>Mask bit for corresponding bit in interrupt request register.</description>
39452              <bitRange>[8:8]</bitRange>
39453              <access>read-write</access>
39454            </field>
39455            <field>
39456              <name>SPI_DONE</name>
39457              <description>Mask bit for corresponding bit in interrupt request register.</description>
39458              <bitRange>[9:9]</bitRange>
39459              <access>read-write</access>
39460            </field>
39461          </fields>
39462        </register>
39463        <register>
39464          <name>INTR_M_MASKED</name>
39465          <description>Master interrupt masked request</description>
39466          <addressOffset>0xF0C</addressOffset>
39467          <size>32</size>
39468          <access>read-only</access>
39469          <resetValue>0x0</resetValue>
39470          <resetMask>0x317</resetMask>
39471          <fields>
39472            <field>
39473              <name>I2C_ARB_LOST</name>
39474              <description>Logical and of corresponding request and mask bits.</description>
39475              <bitRange>[0:0]</bitRange>
39476              <access>read-only</access>
39477            </field>
39478            <field>
39479              <name>I2C_NACK</name>
39480              <description>Logical and of corresponding request and mask bits.</description>
39481              <bitRange>[1:1]</bitRange>
39482              <access>read-only</access>
39483            </field>
39484            <field>
39485              <name>I2C_ACK</name>
39486              <description>Logical and of corresponding request and mask bits.</description>
39487              <bitRange>[2:2]</bitRange>
39488              <access>read-only</access>
39489            </field>
39490            <field>
39491              <name>I2C_STOP</name>
39492              <description>Logical and of corresponding request and mask bits.</description>
39493              <bitRange>[4:4]</bitRange>
39494              <access>read-only</access>
39495            </field>
39496            <field>
39497              <name>I2C_BUS_ERROR</name>
39498              <description>Logical and of corresponding request and mask bits.</description>
39499              <bitRange>[8:8]</bitRange>
39500              <access>read-only</access>
39501            </field>
39502            <field>
39503              <name>SPI_DONE</name>
39504              <description>Logical and of corresponding request and mask bits.</description>
39505              <bitRange>[9:9]</bitRange>
39506              <access>read-only</access>
39507            </field>
39508          </fields>
39509        </register>
39510        <register>
39511          <name>INTR_S</name>
39512          <description>Slave interrupt request</description>
39513          <addressOffset>0xF40</addressOffset>
39514          <size>32</size>
39515          <access>read-write</access>
39516          <resetValue>0x0</resetValue>
39517          <resetMask>0xFFF</resetMask>
39518          <fields>
39519            <field>
39520              <name>I2C_ARB_LOST</name>
39521              <description>I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur, it represents erroneous I2C bus behavior. In case of lost arbitration, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error.</description>
39522              <bitRange>[0:0]</bitRange>
39523              <access>read-write</access>
39524            </field>
39525            <field>
39526              <name>I2C_NACK</name>
39527              <description>I2C slave negative acknowledgement received. Set to '1', when the slave receives a NACK (typically after the slave transmitted TX data).</description>
39528              <bitRange>[1:1]</bitRange>
39529              <access>read-write</access>
39530            </field>
39531            <field>
39532              <name>I2C_ACK</name>
39533              <description>I2C slave acknowledgement received. Set to '1', when the slave receives a ACK (typically after the slave transmitted TX data).</description>
39534              <bitRange>[2:2]</bitRange>
39535              <access>read-write</access>
39536            </field>
39537            <field>
39538              <name>I2C_WRITE_STOP</name>
39539              <description>I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address.
39540
39541In non EZ mode, the event is detected on any I2C write transfer intended for this slave. Note that a I2C write address intended for the slave (address is matching and a it is a write transfer) will result in a I2C_WRITE_STOP event independent of whether the I2C address is ACK'd or NACK'd.
39542
39543In EZ mode, the event is detected only on I2C write transfers that have EZ data written to the memory structure (an I2C write transfer that only communicates an I2C address and EZ address, will not result in this event being detected).</description>
39544              <bitRange>[3:3]</bitRange>
39545              <access>read-write</access>
39546            </field>
39547            <field>
39548              <name>I2C_STOP</name>
39549              <description>I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1', when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially treated separately by the Firmware. Note that the second I2C transfer (after a REPEATED START) may be to a different slave address.
39550
39551The event is detected on any I2C transfer intended for this slave. Note that a I2C address intended for the slave (address is matching) will result in a I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd.</description>
39552              <bitRange>[4:4]</bitRange>
39553              <access>read-write</access>
39554            </field>
39555            <field>
39556              <name>I2C_START</name>
39557              <description>I2C slave START received. Set to '1', when START or REPEATED START event is detected.
39558
39559In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (till the internally clocked logic takes over) (I2C_CTRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set. The Firmware should use INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH and INTR_S.I2C_GENERAL.</description>
39560              <bitRange>[5:5]</bitRange>
39561              <access>read-write</access>
39562            </field>
39563            <field>
39564              <name>I2C_ADDR_MATCH</name>
39565              <description>I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected.</description>
39566              <bitRange>[6:6]</bitRange>
39567              <access>read-write</access>
39568            </field>
39569            <field>
39570              <name>I2C_GENERAL</name>
39571              <description>I2C slave general call address received.  If CTRL.ADDR_ACCEPT, the received address 0x00 (including the R/W bit) is available in the RX FIFO.   In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the event is detected.</description>
39572              <bitRange>[7:7]</bitRange>
39573              <access>read-write</access>
39574            </field>
39575            <field>
39576              <name>I2C_BUS_ERROR</name>
39577              <description>I2C slave bus error (unexpected detection of START or STOP condition). This should not occur, it represents erroneous I2C bus behavior. In case of a bus error, the I2C slave state machine abort the ongoing transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error.</description>
39578              <bitRange>[8:8]</bitRange>
39579              <access>read-write</access>
39580            </field>
39581            <field>
39582              <name>SPI_EZ_WRITE_STOP</name>
39583              <description>SPI slave deselected after a write EZ SPI transfer occurred.</description>
39584              <bitRange>[9:9]</bitRange>
39585              <access>read-write</access>
39586            </field>
39587            <field>
39588              <name>SPI_EZ_STOP</name>
39589              <description>SPI slave deselected after any EZ SPI transfer occurred.</description>
39590              <bitRange>[10:10]</bitRange>
39591              <access>read-write</access>
39592            </field>
39593            <field>
39594              <name>SPI_BUS_ERROR</name>
39595              <description>SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error.</description>
39596              <bitRange>[11:11]</bitRange>
39597              <access>read-write</access>
39598            </field>
39599          </fields>
39600        </register>
39601        <register>
39602          <name>INTR_S_SET</name>
39603          <description>Slave interrupt set request</description>
39604          <addressOffset>0xF44</addressOffset>
39605          <size>32</size>
39606          <access>read-write</access>
39607          <resetValue>0x0</resetValue>
39608          <resetMask>0xFFF</resetMask>
39609          <fields>
39610            <field>
39611              <name>I2C_ARB_LOST</name>
39612              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39613              <bitRange>[0:0]</bitRange>
39614              <access>read-write</access>
39615            </field>
39616            <field>
39617              <name>I2C_NACK</name>
39618              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39619              <bitRange>[1:1]</bitRange>
39620              <access>read-write</access>
39621            </field>
39622            <field>
39623              <name>I2C_ACK</name>
39624              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39625              <bitRange>[2:2]</bitRange>
39626              <access>read-write</access>
39627            </field>
39628            <field>
39629              <name>I2C_WRITE_STOP</name>
39630              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39631              <bitRange>[3:3]</bitRange>
39632              <access>read-write</access>
39633            </field>
39634            <field>
39635              <name>I2C_STOP</name>
39636              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39637              <bitRange>[4:4]</bitRange>
39638              <access>read-write</access>
39639            </field>
39640            <field>
39641              <name>I2C_START</name>
39642              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39643              <bitRange>[5:5]</bitRange>
39644              <access>read-write</access>
39645            </field>
39646            <field>
39647              <name>I2C_ADDR_MATCH</name>
39648              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39649              <bitRange>[6:6]</bitRange>
39650              <access>read-write</access>
39651            </field>
39652            <field>
39653              <name>I2C_GENERAL</name>
39654              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39655              <bitRange>[7:7]</bitRange>
39656              <access>read-write</access>
39657            </field>
39658            <field>
39659              <name>I2C_BUS_ERROR</name>
39660              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39661              <bitRange>[8:8]</bitRange>
39662              <access>read-write</access>
39663            </field>
39664            <field>
39665              <name>SPI_EZ_WRITE_STOP</name>
39666              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39667              <bitRange>[9:9]</bitRange>
39668              <access>read-write</access>
39669            </field>
39670            <field>
39671              <name>SPI_EZ_STOP</name>
39672              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39673              <bitRange>[10:10]</bitRange>
39674              <access>read-write</access>
39675            </field>
39676            <field>
39677              <name>SPI_BUS_ERROR</name>
39678              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39679              <bitRange>[11:11]</bitRange>
39680              <access>read-write</access>
39681            </field>
39682          </fields>
39683        </register>
39684        <register>
39685          <name>INTR_S_MASK</name>
39686          <description>Slave interrupt mask</description>
39687          <addressOffset>0xF48</addressOffset>
39688          <size>32</size>
39689          <access>read-write</access>
39690          <resetValue>0x0</resetValue>
39691          <resetMask>0xFFF</resetMask>
39692          <fields>
39693            <field>
39694              <name>I2C_ARB_LOST</name>
39695              <description>Mask bit for corresponding bit in interrupt request register.</description>
39696              <bitRange>[0:0]</bitRange>
39697              <access>read-write</access>
39698            </field>
39699            <field>
39700              <name>I2C_NACK</name>
39701              <description>Mask bit for corresponding bit in interrupt request register.</description>
39702              <bitRange>[1:1]</bitRange>
39703              <access>read-write</access>
39704            </field>
39705            <field>
39706              <name>I2C_ACK</name>
39707              <description>Mask bit for corresponding bit in interrupt request register.</description>
39708              <bitRange>[2:2]</bitRange>
39709              <access>read-write</access>
39710            </field>
39711            <field>
39712              <name>I2C_WRITE_STOP</name>
39713              <description>Mask bit for corresponding bit in interrupt request register.</description>
39714              <bitRange>[3:3]</bitRange>
39715              <access>read-write</access>
39716            </field>
39717            <field>
39718              <name>I2C_STOP</name>
39719              <description>Mask bit for corresponding bit in interrupt request register.</description>
39720              <bitRange>[4:4]</bitRange>
39721              <access>read-write</access>
39722            </field>
39723            <field>
39724              <name>I2C_START</name>
39725              <description>Mask bit for corresponding bit in interrupt request register.</description>
39726              <bitRange>[5:5]</bitRange>
39727              <access>read-write</access>
39728            </field>
39729            <field>
39730              <name>I2C_ADDR_MATCH</name>
39731              <description>Mask bit for corresponding bit in interrupt request register.</description>
39732              <bitRange>[6:6]</bitRange>
39733              <access>read-write</access>
39734            </field>
39735            <field>
39736              <name>I2C_GENERAL</name>
39737              <description>Mask bit for corresponding bit in interrupt request register.</description>
39738              <bitRange>[7:7]</bitRange>
39739              <access>read-write</access>
39740            </field>
39741            <field>
39742              <name>I2C_BUS_ERROR</name>
39743              <description>Mask bit for corresponding bit in interrupt request register.</description>
39744              <bitRange>[8:8]</bitRange>
39745              <access>read-write</access>
39746            </field>
39747            <field>
39748              <name>SPI_EZ_WRITE_STOP</name>
39749              <description>Mask bit for corresponding bit in interrupt request register.</description>
39750              <bitRange>[9:9]</bitRange>
39751              <access>read-write</access>
39752            </field>
39753            <field>
39754              <name>SPI_EZ_STOP</name>
39755              <description>Mask bit for corresponding bit in interrupt request register.</description>
39756              <bitRange>[10:10]</bitRange>
39757              <access>read-write</access>
39758            </field>
39759            <field>
39760              <name>SPI_BUS_ERROR</name>
39761              <description>Mask bit for corresponding bit in interrupt request register.</description>
39762              <bitRange>[11:11]</bitRange>
39763              <access>read-write</access>
39764            </field>
39765          </fields>
39766        </register>
39767        <register>
39768          <name>INTR_S_MASKED</name>
39769          <description>Slave interrupt masked request</description>
39770          <addressOffset>0xF4C</addressOffset>
39771          <size>32</size>
39772          <access>read-only</access>
39773          <resetValue>0x0</resetValue>
39774          <resetMask>0xFFF</resetMask>
39775          <fields>
39776            <field>
39777              <name>I2C_ARB_LOST</name>
39778              <description>Logical and of corresponding request and mask bits.</description>
39779              <bitRange>[0:0]</bitRange>
39780              <access>read-only</access>
39781            </field>
39782            <field>
39783              <name>I2C_NACK</name>
39784              <description>Logical and of corresponding request and mask bits.</description>
39785              <bitRange>[1:1]</bitRange>
39786              <access>read-only</access>
39787            </field>
39788            <field>
39789              <name>I2C_ACK</name>
39790              <description>Logical and of corresponding request and mask bits.</description>
39791              <bitRange>[2:2]</bitRange>
39792              <access>read-only</access>
39793            </field>
39794            <field>
39795              <name>I2C_WRITE_STOP</name>
39796              <description>Logical and of corresponding request and mask bits.</description>
39797              <bitRange>[3:3]</bitRange>
39798              <access>read-only</access>
39799            </field>
39800            <field>
39801              <name>I2C_STOP</name>
39802              <description>Logical and of corresponding request and mask bits.</description>
39803              <bitRange>[4:4]</bitRange>
39804              <access>read-only</access>
39805            </field>
39806            <field>
39807              <name>I2C_START</name>
39808              <description>Logical and of corresponding request and mask bits.</description>
39809              <bitRange>[5:5]</bitRange>
39810              <access>read-only</access>
39811            </field>
39812            <field>
39813              <name>I2C_ADDR_MATCH</name>
39814              <description>Logical and of corresponding request and mask bits.</description>
39815              <bitRange>[6:6]</bitRange>
39816              <access>read-only</access>
39817            </field>
39818            <field>
39819              <name>I2C_GENERAL</name>
39820              <description>Logical and of corresponding request and mask bits.</description>
39821              <bitRange>[7:7]</bitRange>
39822              <access>read-only</access>
39823            </field>
39824            <field>
39825              <name>I2C_BUS_ERROR</name>
39826              <description>Logical and of corresponding request and mask bits.</description>
39827              <bitRange>[8:8]</bitRange>
39828              <access>read-only</access>
39829            </field>
39830            <field>
39831              <name>SPI_EZ_WRITE_STOP</name>
39832              <description>Logical and of corresponding request and mask bits.</description>
39833              <bitRange>[9:9]</bitRange>
39834              <access>read-only</access>
39835            </field>
39836            <field>
39837              <name>SPI_EZ_STOP</name>
39838              <description>Logical and of corresponding request and mask bits.</description>
39839              <bitRange>[10:10]</bitRange>
39840              <access>read-only</access>
39841            </field>
39842            <field>
39843              <name>SPI_BUS_ERROR</name>
39844              <description>Logical and of corresponding request and mask bits.</description>
39845              <bitRange>[11:11]</bitRange>
39846              <access>read-only</access>
39847            </field>
39848          </fields>
39849        </register>
39850        <register>
39851          <name>INTR_TX</name>
39852          <description>Transmitter interrupt request</description>
39853          <addressOffset>0xF80</addressOffset>
39854          <size>32</size>
39855          <access>read-write</access>
39856          <resetValue>0x0</resetValue>
39857          <resetMask>0x7F3</resetMask>
39858          <fields>
39859            <field>
39860              <name>TRIGGER</name>
39861              <description>Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL.
39862
39863Only used in FIFO mode.</description>
39864              <bitRange>[0:0]</bitRange>
39865              <access>read-write</access>
39866            </field>
39867            <field>
39868              <name>NOT_FULL</name>
39869              <description>TX FIFO is not full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2)
39870BYTE_MODE is '0': # entries != FF_DATA_NR/2.
39871BYTE_MODE is '1': # entries != FF_DATA_NR.
39872
39873Only used in FIFO mode.</description>
39874              <bitRange>[1:1]</bitRange>
39875              <access>read-write</access>
39876            </field>
39877            <field>
39878              <name>EMPTY</name>
39879              <description>TX FIFO is empty; i.e. it has 0 entries.
39880
39881Only used in FIFO mode.</description>
39882              <bitRange>[4:4]</bitRange>
39883              <access>read-write</access>
39884            </field>
39885            <field>
39886              <name>OVERFLOW</name>
39887              <description>Attempt to write to a full TX FIFO.
39888
39889Only used in FIFO mode.</description>
39890              <bitRange>[5:5]</bitRange>
39891              <access>read-write</access>
39892            </field>
39893            <field>
39894              <name>UNDERFLOW</name>
39895              <description>Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'.
39896
39897Only used in FIFO mode.</description>
39898              <bitRange>[6:6]</bitRange>
39899              <access>read-write</access>
39900            </field>
39901            <field>
39902              <name>BLOCKED</name>
39903              <description>AHB-Lite write transfer can not get access to the EZ memory (EZ data access), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'.</description>
39904              <bitRange>[7:7]</bitRange>
39905              <access>read-write</access>
39906            </field>
39907            <field>
39908              <name>UART_NACK</name>
39909              <description>UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1', when event is detected. Write with '1' to clear bit.</description>
39910              <bitRange>[8:8]</bitRange>
39911              <access>read-write</access>
39912            </field>
39913            <field>
39914              <name>UART_DONE</name>
39915              <description>UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO, and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1', when event is detected. Write with '1' to clear bit.</description>
39916              <bitRange>[9:9]</bitRange>
39917              <access>read-write</access>
39918            </field>
39919            <field>
39920              <name>UART_ARB_LOST</name>
39921              <description>UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to '1', when event is detected. Write with '1' to clear bit.</description>
39922              <bitRange>[10:10]</bitRange>
39923              <access>read-write</access>
39924            </field>
39925          </fields>
39926        </register>
39927        <register>
39928          <name>INTR_TX_SET</name>
39929          <description>Transmitter interrupt set request</description>
39930          <addressOffset>0xF84</addressOffset>
39931          <size>32</size>
39932          <access>read-write</access>
39933          <resetValue>0x0</resetValue>
39934          <resetMask>0x7F3</resetMask>
39935          <fields>
39936            <field>
39937              <name>TRIGGER</name>
39938              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39939              <bitRange>[0:0]</bitRange>
39940              <access>read-write</access>
39941            </field>
39942            <field>
39943              <name>NOT_FULL</name>
39944              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39945              <bitRange>[1:1]</bitRange>
39946              <access>read-write</access>
39947            </field>
39948            <field>
39949              <name>EMPTY</name>
39950              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39951              <bitRange>[4:4]</bitRange>
39952              <access>read-write</access>
39953            </field>
39954            <field>
39955              <name>OVERFLOW</name>
39956              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39957              <bitRange>[5:5]</bitRange>
39958              <access>read-write</access>
39959            </field>
39960            <field>
39961              <name>UNDERFLOW</name>
39962              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39963              <bitRange>[6:6]</bitRange>
39964              <access>read-write</access>
39965            </field>
39966            <field>
39967              <name>BLOCKED</name>
39968              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39969              <bitRange>[7:7]</bitRange>
39970              <access>read-write</access>
39971            </field>
39972            <field>
39973              <name>UART_NACK</name>
39974              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39975              <bitRange>[8:8]</bitRange>
39976              <access>read-write</access>
39977            </field>
39978            <field>
39979              <name>UART_DONE</name>
39980              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39981              <bitRange>[9:9]</bitRange>
39982              <access>read-write</access>
39983            </field>
39984            <field>
39985              <name>UART_ARB_LOST</name>
39986              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
39987              <bitRange>[10:10]</bitRange>
39988              <access>read-write</access>
39989            </field>
39990          </fields>
39991        </register>
39992        <register>
39993          <name>INTR_TX_MASK</name>
39994          <description>Transmitter interrupt mask</description>
39995          <addressOffset>0xF88</addressOffset>
39996          <size>32</size>
39997          <access>read-write</access>
39998          <resetValue>0x0</resetValue>
39999          <resetMask>0x7F3</resetMask>
40000          <fields>
40001            <field>
40002              <name>TRIGGER</name>
40003              <description>Mask bit for corresponding bit in interrupt request register.</description>
40004              <bitRange>[0:0]</bitRange>
40005              <access>read-write</access>
40006            </field>
40007            <field>
40008              <name>NOT_FULL</name>
40009              <description>Mask bit for corresponding bit in interrupt request register.</description>
40010              <bitRange>[1:1]</bitRange>
40011              <access>read-write</access>
40012            </field>
40013            <field>
40014              <name>EMPTY</name>
40015              <description>Mask bit for corresponding bit in interrupt request register.</description>
40016              <bitRange>[4:4]</bitRange>
40017              <access>read-write</access>
40018            </field>
40019            <field>
40020              <name>OVERFLOW</name>
40021              <description>Mask bit for corresponding bit in interrupt request register.</description>
40022              <bitRange>[5:5]</bitRange>
40023              <access>read-write</access>
40024            </field>
40025            <field>
40026              <name>UNDERFLOW</name>
40027              <description>Mask bit for corresponding bit in interrupt request register.</description>
40028              <bitRange>[6:6]</bitRange>
40029              <access>read-write</access>
40030            </field>
40031            <field>
40032              <name>BLOCKED</name>
40033              <description>Mask bit for corresponding bit in interrupt request register.</description>
40034              <bitRange>[7:7]</bitRange>
40035              <access>read-write</access>
40036            </field>
40037            <field>
40038              <name>UART_NACK</name>
40039              <description>Mask bit for corresponding bit in interrupt request register.</description>
40040              <bitRange>[8:8]</bitRange>
40041              <access>read-write</access>
40042            </field>
40043            <field>
40044              <name>UART_DONE</name>
40045              <description>Mask bit for corresponding bit in interrupt request register.</description>
40046              <bitRange>[9:9]</bitRange>
40047              <access>read-write</access>
40048            </field>
40049            <field>
40050              <name>UART_ARB_LOST</name>
40051              <description>Mask bit for corresponding bit in interrupt request register.</description>
40052              <bitRange>[10:10]</bitRange>
40053              <access>read-write</access>
40054            </field>
40055          </fields>
40056        </register>
40057        <register>
40058          <name>INTR_TX_MASKED</name>
40059          <description>Transmitter interrupt masked request</description>
40060          <addressOffset>0xF8C</addressOffset>
40061          <size>32</size>
40062          <access>read-only</access>
40063          <resetValue>0x0</resetValue>
40064          <resetMask>0x7F3</resetMask>
40065          <fields>
40066            <field>
40067              <name>TRIGGER</name>
40068              <description>Logical and of corresponding request and mask bits.</description>
40069              <bitRange>[0:0]</bitRange>
40070              <access>read-only</access>
40071            </field>
40072            <field>
40073              <name>NOT_FULL</name>
40074              <description>Logical and of corresponding request and mask bits.</description>
40075              <bitRange>[1:1]</bitRange>
40076              <access>read-only</access>
40077            </field>
40078            <field>
40079              <name>EMPTY</name>
40080              <description>Logical and of corresponding request and mask bits.</description>
40081              <bitRange>[4:4]</bitRange>
40082              <access>read-only</access>
40083            </field>
40084            <field>
40085              <name>OVERFLOW</name>
40086              <description>Logical and of corresponding request and mask bits.</description>
40087              <bitRange>[5:5]</bitRange>
40088              <access>read-only</access>
40089            </field>
40090            <field>
40091              <name>UNDERFLOW</name>
40092              <description>Logical and of corresponding request and mask bits.</description>
40093              <bitRange>[6:6]</bitRange>
40094              <access>read-only</access>
40095            </field>
40096            <field>
40097              <name>BLOCKED</name>
40098              <description>Logical and of corresponding request and mask bits.</description>
40099              <bitRange>[7:7]</bitRange>
40100              <access>read-only</access>
40101            </field>
40102            <field>
40103              <name>UART_NACK</name>
40104              <description>Logical and of corresponding request and mask bits.</description>
40105              <bitRange>[8:8]</bitRange>
40106              <access>read-only</access>
40107            </field>
40108            <field>
40109              <name>UART_DONE</name>
40110              <description>Logical and of corresponding request and mask bits.</description>
40111              <bitRange>[9:9]</bitRange>
40112              <access>read-only</access>
40113            </field>
40114            <field>
40115              <name>UART_ARB_LOST</name>
40116              <description>Logical and of corresponding request and mask bits.</description>
40117              <bitRange>[10:10]</bitRange>
40118              <access>read-only</access>
40119            </field>
40120          </fields>
40121        </register>
40122        <register>
40123          <name>INTR_RX</name>
40124          <description>Receiver interrupt request</description>
40125          <addressOffset>0xFC0</addressOffset>
40126          <size>32</size>
40127          <access>read-write</access>
40128          <resetValue>0x0</resetValue>
40129          <resetMask>0xFED</resetMask>
40130          <fields>
40131            <field>
40132              <name>TRIGGER</name>
40133              <description>More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL.
40134
40135Only used in FIFO mode.</description>
40136              <bitRange>[0:0]</bitRange>
40137              <access>read-write</access>
40138            </field>
40139            <field>
40140              <name>NOT_EMPTY</name>
40141              <description>RX FIFO is not empty.
40142
40143Only used in FIFO mode.</description>
40144              <bitRange>[2:2]</bitRange>
40145              <access>read-write</access>
40146            </field>
40147            <field>
40148              <name>FULL</name>
40149              <description>RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2)
40150BYTE_MODE is '0': # entries == FF_DATA_NR/2.
40151BYTE_MODE is '1': # entries == FF_DATA_NR.
40152
40153Only used in FIFO mode.</description>
40154              <bitRange>[3:3]</bitRange>
40155              <access>read-write</access>
40156            </field>
40157            <field>
40158              <name>OVERFLOW</name>
40159              <description>Attempt to write to a full RX FIFO. Note: in I2C mode, the OVERFLOW is set when a data frame is received and the RX FIFO is full, independent of whether it is ACK'd or NACK'd.
40160
40161Only used in FIFO mode.</description>
40162              <bitRange>[5:5]</bitRange>
40163              <access>read-write</access>
40164            </field>
40165            <field>
40166              <name>UNDERFLOW</name>
40167              <description>Attempt to read from an empty RX FIFO.
40168
40169Only used in FIFO mode.</description>
40170              <bitRange>[6:6]</bitRange>
40171              <access>read-write</access>
40172            </field>
40173            <field>
40174              <name>BLOCKED</name>
40175              <description>AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses), due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'.</description>
40176              <bitRange>[7:7]</bitRange>
40177              <access>read-write</access>
40178            </field>
40179            <field>
40180              <name>FRAME_ERROR</name>
40181              <description>Frame error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:
40182Start bit error: after the detection of the beginning of a start bit period (RX line changes from '1' to '0'), the middle of the start bit period is sampled erroneously (RX line is '1').  Note: a start bit error is detected BEFORE a data frame is received.
40183Stop bit error: the RX line is sampled as '0', but a '1' was expected. Note: a stop bit error may result in failure to receive successive data frame(s). Note: a stop bit error is detected AFTER a data frame is received.
40184
40185A stop bit error is detected after a data frame is received, and the UART_RX_CTL.DROP_ON_FRAME_ERROR field specifies whether the received frame is dropped or send to the RX FIFO. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '1', the received data frame is dropped. If UART_RX_CTL.DROP_ON_FRAME_ERROR is '0', the received data frame is send to the RX FIFO. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO; i.e. the RX FIFO does not have error flags to tag erroneous data frames.</description>
40186              <bitRange>[8:8]</bitRange>
40187              <access>read-write</access>
40188            </field>
40189            <field>
40190              <name>PARITY_ERROR</name>
40191              <description>Parity error in received data frame. Set to '1', when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1', the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0', the received frame is send to the RX FIFO. In SmartCard submode, negatively acknowledged data frames generate a parity error. Note that Firmware can only identify the erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data frame into the RX FIFO.</description>
40192              <bitRange>[9:9]</bitRange>
40193              <access>read-write</access>
40194            </field>
40195            <field>
40196              <name>BAUD_DETECT</name>
40197              <description>LIN baudrate detection is completed.  The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchronization byte. Set to '1', when event is detected. Write with '1' to clear bit.</description>
40198              <bitRange>[10:10]</bitRange>
40199              <access>read-write</access>
40200            </field>
40201            <field>
40202              <name>BREAK_DETECT</name>
40203              <description>Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and LIN submodes. For the UART standard submodes, ongoing receipt of data frames is NOT affected; i.e. Firmware is expected to take the proper action. For the LIN submode, possible ongoing receipt of a data frame is stopped and the (partially) received data frame is dropped and baud rate detection is started. Set to '1', when event is detected. Write with '1' to clear bit.</description>
40204              <bitRange>[11:11]</bitRange>
40205              <access>read-write</access>
40206            </field>
40207          </fields>
40208        </register>
40209        <register>
40210          <name>INTR_RX_SET</name>
40211          <description>Receiver interrupt set request</description>
40212          <addressOffset>0xFC4</addressOffset>
40213          <size>32</size>
40214          <access>read-write</access>
40215          <resetValue>0x0</resetValue>
40216          <resetMask>0xFED</resetMask>
40217          <fields>
40218            <field>
40219              <name>TRIGGER</name>
40220              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
40221              <bitRange>[0:0]</bitRange>
40222              <access>read-write</access>
40223            </field>
40224            <field>
40225              <name>NOT_EMPTY</name>
40226              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
40227              <bitRange>[2:2]</bitRange>
40228              <access>read-write</access>
40229            </field>
40230            <field>
40231              <name>FULL</name>
40232              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
40233              <bitRange>[3:3]</bitRange>
40234              <access>read-write</access>
40235            </field>
40236            <field>
40237              <name>OVERFLOW</name>
40238              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
40239              <bitRange>[5:5]</bitRange>
40240              <access>read-write</access>
40241            </field>
40242            <field>
40243              <name>UNDERFLOW</name>
40244              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
40245              <bitRange>[6:6]</bitRange>
40246              <access>read-write</access>
40247            </field>
40248            <field>
40249              <name>BLOCKED</name>
40250              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
40251              <bitRange>[7:7]</bitRange>
40252              <access>read-write</access>
40253            </field>
40254            <field>
40255              <name>FRAME_ERROR</name>
40256              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
40257              <bitRange>[8:8]</bitRange>
40258              <access>read-write</access>
40259            </field>
40260            <field>
40261              <name>PARITY_ERROR</name>
40262              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
40263              <bitRange>[9:9]</bitRange>
40264              <access>read-write</access>
40265            </field>
40266            <field>
40267              <name>BAUD_DETECT</name>
40268              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
40269              <bitRange>[10:10]</bitRange>
40270              <access>read-write</access>
40271            </field>
40272            <field>
40273              <name>BREAK_DETECT</name>
40274              <description>Write with '1' to set corresponding bit in interrupt status register.</description>
40275              <bitRange>[11:11]</bitRange>
40276              <access>read-write</access>
40277            </field>
40278          </fields>
40279        </register>
40280        <register>
40281          <name>INTR_RX_MASK</name>
40282          <description>Receiver interrupt mask</description>
40283          <addressOffset>0xFC8</addressOffset>
40284          <size>32</size>
40285          <access>read-write</access>
40286          <resetValue>0x0</resetValue>
40287          <resetMask>0xFED</resetMask>
40288          <fields>
40289            <field>
40290              <name>TRIGGER</name>
40291              <description>Mask bit for corresponding bit in interrupt request register.</description>
40292              <bitRange>[0:0]</bitRange>
40293              <access>read-write</access>
40294            </field>
40295            <field>
40296              <name>NOT_EMPTY</name>
40297              <description>Mask bit for corresponding bit in interrupt request register.</description>
40298              <bitRange>[2:2]</bitRange>
40299              <access>read-write</access>
40300            </field>
40301            <field>
40302              <name>FULL</name>
40303              <description>Mask bit for corresponding bit in interrupt request register.</description>
40304              <bitRange>[3:3]</bitRange>
40305              <access>read-write</access>
40306            </field>
40307            <field>
40308              <name>OVERFLOW</name>
40309              <description>Mask bit for corresponding bit in interrupt request register.</description>
40310              <bitRange>[5:5]</bitRange>
40311              <access>read-write</access>
40312            </field>
40313            <field>
40314              <name>UNDERFLOW</name>
40315              <description>Mask bit for corresponding bit in interrupt request register.</description>
40316              <bitRange>[6:6]</bitRange>
40317              <access>read-write</access>
40318            </field>
40319            <field>
40320              <name>BLOCKED</name>
40321              <description>Mask bit for corresponding bit in interrupt request register.</description>
40322              <bitRange>[7:7]</bitRange>
40323              <access>read-write</access>
40324            </field>
40325            <field>
40326              <name>FRAME_ERROR</name>
40327              <description>Mask bit for corresponding bit in interrupt request register.</description>
40328              <bitRange>[8:8]</bitRange>
40329              <access>read-write</access>
40330            </field>
40331            <field>
40332              <name>PARITY_ERROR</name>
40333              <description>Mask bit for corresponding bit in interrupt request register.</description>
40334              <bitRange>[9:9]</bitRange>
40335              <access>read-write</access>
40336            </field>
40337            <field>
40338              <name>BAUD_DETECT</name>
40339              <description>Mask bit for corresponding bit in interrupt request register.</description>
40340              <bitRange>[10:10]</bitRange>
40341              <access>read-write</access>
40342            </field>
40343            <field>
40344              <name>BREAK_DETECT</name>
40345              <description>Mask bit for corresponding bit in interrupt request register.</description>
40346              <bitRange>[11:11]</bitRange>
40347              <access>read-write</access>
40348            </field>
40349          </fields>
40350        </register>
40351        <register>
40352          <name>INTR_RX_MASKED</name>
40353          <description>Receiver interrupt masked request</description>
40354          <addressOffset>0xFCC</addressOffset>
40355          <size>32</size>
40356          <access>read-only</access>
40357          <resetValue>0x0</resetValue>
40358          <resetMask>0xFED</resetMask>
40359          <fields>
40360            <field>
40361              <name>TRIGGER</name>
40362              <description>Logical and of corresponding request and mask bits.</description>
40363              <bitRange>[0:0]</bitRange>
40364              <access>read-only</access>
40365            </field>
40366            <field>
40367              <name>NOT_EMPTY</name>
40368              <description>Logical and of corresponding request and mask bits.</description>
40369              <bitRange>[2:2]</bitRange>
40370              <access>read-only</access>
40371            </field>
40372            <field>
40373              <name>FULL</name>
40374              <description>Logical and of corresponding request and mask bits.</description>
40375              <bitRange>[3:3]</bitRange>
40376              <access>read-only</access>
40377            </field>
40378            <field>
40379              <name>OVERFLOW</name>
40380              <description>Logical and of corresponding request and mask bits.</description>
40381              <bitRange>[5:5]</bitRange>
40382              <access>read-only</access>
40383            </field>
40384            <field>
40385              <name>UNDERFLOW</name>
40386              <description>Logical and of corresponding request and mask bits.</description>
40387              <bitRange>[6:6]</bitRange>
40388              <access>read-only</access>
40389            </field>
40390            <field>
40391              <name>BLOCKED</name>
40392              <description>Logical and of corresponding request and mask bits.</description>
40393              <bitRange>[7:7]</bitRange>
40394              <access>read-only</access>
40395            </field>
40396            <field>
40397              <name>FRAME_ERROR</name>
40398              <description>Logical and of corresponding request and mask bits.</description>
40399              <bitRange>[8:8]</bitRange>
40400              <access>read-only</access>
40401            </field>
40402            <field>
40403              <name>PARITY_ERROR</name>
40404              <description>Logical and of corresponding request and mask bits.</description>
40405              <bitRange>[9:9]</bitRange>
40406              <access>read-only</access>
40407            </field>
40408            <field>
40409              <name>BAUD_DETECT</name>
40410              <description>Logical and of corresponding request and mask bits.</description>
40411              <bitRange>[10:10]</bitRange>
40412              <access>read-only</access>
40413            </field>
40414            <field>
40415              <name>BREAK_DETECT</name>
40416              <description>Logical and of corresponding request and mask bits.</description>
40417              <bitRange>[11:11]</bitRange>
40418              <access>read-only</access>
40419            </field>
40420          </fields>
40421        </register>
40422      </registers>
40423    </peripheral>
40424    <peripheral derivedFrom="SCB0">
40425      <name>SCB1</name>
40426      <baseAddress>0x40610000</baseAddress>
40427    </peripheral>
40428    <peripheral derivedFrom="SCB0">
40429      <name>SCB2</name>
40430      <baseAddress>0x40620000</baseAddress>
40431    </peripheral>
40432    <peripheral derivedFrom="SCB0">
40433      <name>SCB3</name>
40434      <baseAddress>0x40630000</baseAddress>
40435    </peripheral>
40436    <peripheral derivedFrom="SCB0">
40437      <name>SCB4</name>
40438      <baseAddress>0x40640000</baseAddress>
40439    </peripheral>
40440    <peripheral derivedFrom="SCB0">
40441      <name>SCB5</name>
40442      <baseAddress>0x40650000</baseAddress>
40443    </peripheral>
40444    <peripheral derivedFrom="SCB0">
40445      <name>SCB6</name>
40446      <baseAddress>0x40660000</baseAddress>
40447    </peripheral>
40448    <peripheral derivedFrom="SCB0">
40449      <name>SCB7</name>
40450      <baseAddress>0x40670000</baseAddress>
40451    </peripheral>
40452    <peripheral derivedFrom="SCB0">
40453      <name>SCB8</name>
40454      <baseAddress>0x40680000</baseAddress>
40455    </peripheral>
40456    <peripheral derivedFrom="SCB0">
40457      <name>SCB9</name>
40458      <baseAddress>0x40690000</baseAddress>
40459    </peripheral>
40460    <peripheral derivedFrom="SCB0">
40461      <name>SCB10</name>
40462      <baseAddress>0x406A0000</baseAddress>
40463    </peripheral>
40464    <peripheral derivedFrom="SCB0">
40465      <name>SCB11</name>
40466      <baseAddress>0x406B0000</baseAddress>
40467    </peripheral>
40468    <peripheral derivedFrom="SCB0">
40469      <name>SCB12</name>
40470      <baseAddress>0x406C0000</baseAddress>
40471    </peripheral>
40472    <peripheral>
40473      <name>SAR</name>
40474      <description>SAR ADC with Sequencer</description>
40475      <baseAddress>0x409D0000</baseAddress>
40476      <addressBlock>
40477        <offset>0</offset>
40478        <size>65536</size>
40479        <usage>registers</usage>
40480      </addressBlock>
40481      <registers>
40482        <register>
40483          <name>CTRL</name>
40484          <description>Analog control register.</description>
40485          <addressOffset>0x0</addressOffset>
40486          <size>32</size>
40487          <access>read-write</access>
40488          <resetValue>0x10000000</resetValue>
40489          <resetMask>0xFF3FEEF7</resetMask>
40490          <fields>
40491            <field>
40492              <name>PWR_CTRL_VREF</name>
40493              <description>VREF buffer low power mode.</description>
40494              <bitRange>[2:0]</bitRange>
40495              <access>read-write</access>
40496              <enumeratedValues>
40497                <enumeratedValue>
40498                  <name>PWR_100</name>
40499                  <description>full power  (100 percent) (default), bypass cap, max clk_sar is 18MHz.</description>
40500                  <value>0</value>
40501                </enumeratedValue>
40502                <enumeratedValue>
40503                  <name>PWR_80</name>
40504                  <description>80 percent power</description>
40505                  <value>1</value>
40506                </enumeratedValue>
40507                <enumeratedValue>
40508                  <name>PWR_60</name>
40509                  <description>60 percent power</description>
40510                  <value>2</value>
40511                </enumeratedValue>
40512                <enumeratedValue>
40513                  <name>PWR_50</name>
40514                  <description>50 percent power</description>
40515                  <value>3</value>
40516                </enumeratedValue>
40517                <enumeratedValue>
40518                  <name>PWR_40</name>
40519                  <description>40 percent power</description>
40520                  <value>4</value>
40521                </enumeratedValue>
40522                <enumeratedValue>
40523                  <name>PWR_30</name>
40524                  <description>30 percent power</description>
40525                  <value>5</value>
40526                </enumeratedValue>
40527                <enumeratedValue>
40528                  <name>PWR_20</name>
40529                  <description>20 percent power</description>
40530                  <value>6</value>
40531                </enumeratedValue>
40532                <enumeratedValue>
40533                  <name>PWR_10</name>
40534                  <description>10 percent power</description>
40535                  <value>7</value>
40536                </enumeratedValue>
40537              </enumeratedValues>
40538            </field>
40539            <field>
40540              <name>VREF_SEL</name>
40541              <description>SARADC internal VREF selection.</description>
40542              <bitRange>[6:4]</bitRange>
40543              <access>read-write</access>
40544              <enumeratedValues>
40545                <enumeratedValue>
40546                  <name>VREF0</name>
40547                  <description>VREF0 from PRB (VREF buffer on)</description>
40548                  <value>0</value>
40549                </enumeratedValue>
40550                <enumeratedValue>
40551                  <name>VREF1</name>
40552                  <description>VREF1 from PRB (VREF buffer on)</description>
40553                  <value>1</value>
40554                </enumeratedValue>
40555                <enumeratedValue>
40556                  <name>VREF2</name>
40557                  <description>VREF2 from PRB (VREF buffer on)</description>
40558                  <value>2</value>
40559                </enumeratedValue>
40560                <enumeratedValue>
40561                  <name>VREF_AROUTE</name>
40562                  <description>VREF from AROUTE (VREF buffer on)</description>
40563                  <value>3</value>
40564                </enumeratedValue>
40565                <enumeratedValue>
40566                  <name>VBGR</name>
40567                  <description>1.024V from BandGap (VREF buffer on)</description>
40568                  <value>4</value>
40569                </enumeratedValue>
40570                <enumeratedValue>
40571                  <name>VREF_EXT</name>
40572                  <description>External precision Vref direct from a pin (low impedance path).</description>
40573                  <value>5</value>
40574                </enumeratedValue>
40575                <enumeratedValue>
40576                  <name>VDDA_DIV_2</name>
40577                  <description>Vdda/2  (VREF buffer on)</description>
40578                  <value>6</value>
40579                </enumeratedValue>
40580                <enumeratedValue>
40581                  <name>VDDA</name>
40582                  <description>Vdda.</description>
40583                  <value>7</value>
40584                </enumeratedValue>
40585              </enumeratedValues>
40586            </field>
40587            <field>
40588              <name>VREF_BYP_CAP_EN</name>
40589              <description>VREF bypass cap enable for when VREF buffer is on</description>
40590              <bitRange>[7:7]</bitRange>
40591              <access>read-write</access>
40592            </field>
40593            <field>
40594              <name>NEG_SEL</name>
40595              <description>SARADC internal NEG selection for Single ended conversion</description>
40596              <bitRange>[11:9]</bitRange>
40597              <access>read-write</access>
40598              <enumeratedValues>
40599                <enumeratedValue>
40600                  <name>VSSA_KELVIN</name>
40601                  <description>NEG input of SARADC is connected to 'vssa_kelvin', gives more precision around zero. Note this opens both SARADC internal switches, therefore use this value to insert a break-before-make cycle on those switches when SWITCH_DISABLE is high.</description>
40602                  <value>0</value>
40603                </enumeratedValue>
40604                <enumeratedValue>
40605                  <name>ART_VSSA</name>
40606                  <description>NEG input of SARADC is connected to VSSA in AROUTE close to the SARADC</description>
40607                  <value>1</value>
40608                </enumeratedValue>
40609                <enumeratedValue>
40610                  <name>P1</name>
40611                  <description>NEG input of SARADC is connected to P1 pin of SARMUX</description>
40612                  <value>2</value>
40613                </enumeratedValue>
40614                <enumeratedValue>
40615                  <name>P3</name>
40616                  <description>NEG input of SARADC is connected to P3 pin of SARMUX</description>
40617                  <value>3</value>
40618                </enumeratedValue>
40619                <enumeratedValue>
40620                  <name>P5</name>
40621                  <description>NEG input of SARADC is connected to P5 pin of SARMUX</description>
40622                  <value>4</value>
40623                </enumeratedValue>
40624                <enumeratedValue>
40625                  <name>P7</name>
40626                  <description>NEG input of SARADC is connected to P7 pin of SARMUX</description>
40627                  <value>5</value>
40628                </enumeratedValue>
40629                <enumeratedValue>
40630                  <name>ACORE</name>
40631                  <description>NEG input of SARADC is connected to an ACORE in AROUTE</description>
40632                  <value>6</value>
40633                </enumeratedValue>
40634                <enumeratedValue>
40635                  <name>VREF</name>
40636                  <description>NEG input of SARADC is shorted with VREF input of SARADC.</description>
40637                  <value>7</value>
40638                </enumeratedValue>
40639              </enumeratedValues>
40640            </field>
40641            <field>
40642              <name>SAR_HW_CTRL_NEGVREF</name>
40643              <description>Hardware control: 0=only firmware control, 1=hardware control masked by firmware setting for VREF to NEG switch.</description>
40644              <bitRange>[13:13]</bitRange>
40645              <access>read-write</access>
40646            </field>
40647            <field>
40648              <name>COMP_DLY</name>
40649              <description>Set the comparator latch delay in accordance with SAR conversion rate</description>
40650              <bitRange>[15:14]</bitRange>
40651              <access>read-write</access>
40652              <enumeratedValues>
40653                <enumeratedValue>
40654                  <name>D2P5</name>
40655                  <description>2.5ns delay, use this for 2.5Msps</description>
40656                  <value>0</value>
40657                </enumeratedValue>
40658                <enumeratedValue>
40659                  <name>D4</name>
40660                  <description>4.0ns delay, use this for 2.0Msps</description>
40661                  <value>1</value>
40662                </enumeratedValue>
40663                <enumeratedValue>
40664                  <name>D10</name>
40665                  <description>10ns delay, use this for 1.5Msps</description>
40666                  <value>2</value>
40667                </enumeratedValue>
40668                <enumeratedValue>
40669                  <name>D12</name>
40670                  <description>12ns delay, use this for 1.0Msps or less</description>
40671                  <value>3</value>
40672                </enumeratedValue>
40673              </enumeratedValues>
40674            </field>
40675            <field>
40676              <name>SPARE</name>
40677              <description>Spare controls, not yet designated, for late changes done with an ECO</description>
40678              <bitRange>[19:16]</bitRange>
40679              <access>read-write</access>
40680            </field>
40681            <field>
40682              <name>BOOSTPUMP_EN</name>
40683              <description>deprecated</description>
40684              <bitRange>[20:20]</bitRange>
40685              <access>read-write</access>
40686            </field>
40687            <field>
40688              <name>REFBUF_EN</name>
40689              <description>For normal ADC operation this bit must be set, for all reference choices - internal, external or vdda based reference.
40690Setting this bit is critical to proper function of switches inside SARREF block.</description>
40691              <bitRange>[21:21]</bitRange>
40692              <access>read-write</access>
40693            </field>
40694            <field>
40695              <name>COMP_PWR</name>
40696              <description>Comparator power mode.</description>
40697              <bitRange>[26:24]</bitRange>
40698              <access>read-write</access>
40699              <enumeratedValues>
40700                <enumeratedValue>
40701                  <name>P100</name>
40702                  <description>Power = 100 percent, Use this for SAR Clock Frequency greater than 18MHz</description>
40703                  <value>0</value>
40704                </enumeratedValue>
40705                <enumeratedValue>
40706                  <name>P80</name>
40707                  <description>N/A</description>
40708                  <value>1</value>
40709                </enumeratedValue>
40710                <enumeratedValue>
40711                  <name>P60</name>
40712                  <description>Power = 60 percent, Use this for SAR Clock Frequency greater than 1.8MHz up to 18MHz.</description>
40713                  <value>2</value>
40714                </enumeratedValue>
40715                <enumeratedValue>
40716                  <name>P50</name>
40717                  <description>N/A</description>
40718                  <value>3</value>
40719                </enumeratedValue>
40720                <enumeratedValue>
40721                  <name>P40</name>
40722                  <description>N/A</description>
40723                  <value>4</value>
40724                </enumeratedValue>
40725                <enumeratedValue>
40726                  <name>P30</name>
40727                  <description>N/A</description>
40728                  <value>5</value>
40729                </enumeratedValue>
40730                <enumeratedValue>
40731                  <name>P20</name>
40732                  <description>Power = 20 percent, Use this for SAR Clock Frequency less than or equal to 1.8MHz</description>
40733                  <value>6</value>
40734                </enumeratedValue>
40735                <enumeratedValue>
40736                  <name>P10</name>
40737                  <description>N/A</description>
40738                  <value>7</value>
40739                </enumeratedValue>
40740              </enumeratedValues>
40741            </field>
40742            <field>
40743              <name>DEEPSLEEP_ON</name>
40744              <description>- 0: SARMUX IP disabled off during DeepSleep power mode
40745- 1: SARMUX IP remains enabled during DeepSleep power mode (if ENABLED=1)</description>
40746              <bitRange>[27:27]</bitRange>
40747              <access>read-write</access>
40748            </field>
40749            <field>
40750              <name>DSI_SYNC_CONFIG</name>
40751              <description>- 0: bypass clock domain synchronization of the DSI config signals.
40752- 1: synchronize the DSI config signals to peripheral clock domain.</description>
40753              <bitRange>[28:28]</bitRange>
40754              <access>read-write</access>
40755            </field>
40756            <field>
40757              <name>DSI_MODE</name>
40758              <description>SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1)
40759- 0: Normal mode, SAR sequencer operates according to CHAN_EN enables and CHAN_CONFIG channel configurations
40760- 1: CHAN_EN, INJ_START_EN and channel configurations in CHAN_CONFIG and INJ_CHAN_CONFIG are ignored</description>
40761              <bitRange>[29:29]</bitRange>
40762              <access>read-write</access>
40763            </field>
40764            <field>
40765              <name>SWITCH_DISABLE</name>
40766              <description>Disable SAR sequencer from enabling routing switches (note DSI and firmware can always close switches independent of this control)
40767- 0: Normal mode, SAR sequencer changes switches according to pin address in channel configurations
40768- 1: Switches disabled, SAR sequencer does not enable any switches, it is the responsibility of the firmware or UDBs (through DSI) to set the switches to route the signal to be converted through the SARMUX</description>
40769              <bitRange>[30:30]</bitRange>
40770              <access>read-write</access>
40771            </field>
40772            <field>
40773              <name>ENABLED</name>
40774              <description>- 0: SAR IP disabled (put analog in power down and stop clocks), also can clear FW_TRIGGER and INJ_START_EN (if not tailgating) on write.
40775- 1: SAR IP enabled.</description>
40776              <bitRange>[31:31]</bitRange>
40777              <access>read-write</access>
40778            </field>
40779          </fields>
40780        </register>
40781        <register>
40782          <name>SAMPLE_CTRL</name>
40783          <description>Sample control register.</description>
40784          <addressOffset>0x4</addressOffset>
40785          <size>32</size>
40786          <access>read-write</access>
40787          <resetValue>0x80008</resetValue>
40788          <resetMask>0xDFCF01FE</resetMask>
40789          <fields>
40790            <field>
40791              <name>LEFT_ALIGN</name>
40792              <description>Left align data in data[15:0], default data is right aligned in data[11:0], with sign extension to 16 bits if the channel is differential.</description>
40793              <bitRange>[1:1]</bitRange>
40794              <access>read-write</access>
40795            </field>
40796            <field>
40797              <name>SINGLE_ENDED_SIGNED</name>
40798              <description>Output data from a single ended conversion as a signed value
40799
40800If AVG_MODE = 1 (Interleaved averaging), then SINGLE_ENDED_SIGNED must be configured identically to DIFFERENTIAL_SIGNED.</description>
40801              <bitRange>[2:2]</bitRange>
40802              <access>read-write</access>
40803              <enumeratedValues>
40804                <enumeratedValue>
40805                  <name>UNSIGNED</name>
40806                  <description>Default: result data is unsigned (zero extended if needed)</description>
40807                  <value>0</value>
40808                </enumeratedValue>
40809                <enumeratedValue>
40810                  <name>SIGNED</name>
40811                  <description>result data is signed (sign extended if needed)</description>
40812                  <value>1</value>
40813                </enumeratedValue>
40814              </enumeratedValues>
40815            </field>
40816            <field>
40817              <name>DIFFERENTIAL_SIGNED</name>
40818              <description>Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NEG_ADDR_EN is set to 1
40819
40820If AVG_MODE = 1 (Interleaved averaging), then DIFFERENTIAL_SIGNED must be configured identically to SINGLE_ENDED_SIGNED.</description>
40821              <bitRange>[3:3]</bitRange>
40822              <access>read-write</access>
40823              <enumeratedValues>
40824                <enumeratedValue>
40825                  <name>UNSIGNED</name>
40826                  <description>result data is unsigned (zero extended if needed)</description>
40827                  <value>0</value>
40828                </enumeratedValue>
40829                <enumeratedValue>
40830                  <name>SIGNED</name>
40831                  <description>Default: result data is signed (sign extended if needed)</description>
40832                  <value>1</value>
40833                </enumeratedValue>
40834              </enumeratedValues>
40835            </field>
40836            <field>
40837              <name>AVG_CNT</name>
40838              <description>Averaging Count for channels that have averaging enabled (AVG_EN). A channel will be sampled (1&lt;&lt;(AVG_CNT+1)) = [2..256] times.
40839- In ACCUNDUMP mode  (1st order accumulate and dump filter) a channel will be sampled back to back, the average result is calculated and stored and then the next enabled channel is sampled. If shifting is not enabled (AVG_SHIFT=0) then the result is forced to shift right so that is fits in 16 bits, so right shift is done by max(0,AVG_CNT-3).
40840- In INTERLEAVED mode one sample is taken per triggered scan, only in the scan where the final averaging count is reached a valid average is calculated and stored in the RESULT register (by definition the same scan for all the channels that have averaging enabled). In all other scans the RESULT register for averaged channels will have an invalid result and the intermediate accumulated value is stored in the 16-bit WORK register. In this mode make sure that the averaging count is low enough to ensure that the intermediate value does not exceed 16-bits otherwise the MSBs will be lost. So for a 12-bit resolution the averaging count should be set to 16 or less (AVG_CNT=&lt;3).</description>
40841              <bitRange>[6:4]</bitRange>
40842              <access>read-write</access>
40843            </field>
40844            <field>
40845              <name>AVG_SHIFT</name>
40846              <description>Averaging shifting: after averaging the result is shifted right to fit in 12 bits.</description>
40847              <bitRange>[7:7]</bitRange>
40848              <access>read-write</access>
40849            </field>
40850            <field>
40851              <name>AVG_MODE</name>
40852              <description>Averaging mode,  in DSI mode this bit is ignored and only AccuNDump mode is available.</description>
40853              <bitRange>[8:8]</bitRange>
40854              <access>read-write</access>
40855              <enumeratedValues>
40856                <enumeratedValue>
40857                  <name>ACCUNDUMP</name>
40858                  <description>Accumulate and Dump (1st order accumulate and dump filter): a channel will be sampled back to back and averaged</description>
40859                  <value>0</value>
40860                </enumeratedValue>
40861                <enumeratedValue>
40862                  <name>INTERLEAVED</name>
40863                  <description>Interleaved: Each scan (trigger) one sample is taken per channel and averaged over several scans.</description>
40864                  <value>1</value>
40865                </enumeratedValue>
40866              </enumeratedValues>
40867            </field>
40868            <field>
40869              <name>CONTINUOUS</name>
40870              <description>- 0: Wait for next FW_TRIGGER (one shot) or hardware trigger (e.g. from TPWM for periodic triggering) before scanning enabled channels.
40871- 1: Continuously scan enabled channels, ignore triggers.</description>
40872              <bitRange>[16:16]</bitRange>
40873              <access>read-write</access>
40874            </field>
40875            <field>
40876              <name>DSI_TRIGGER_EN</name>
40877              <description>- 0: firmware trigger only: disable hardware trigger tr_sar_in.
40878- 1: enable hardware trigger tr_sar_in (e.g. from TCPWM, GPIO or UDB).</description>
40879              <bitRange>[17:17]</bitRange>
40880              <access>read-write</access>
40881            </field>
40882            <field>
40883              <name>DSI_TRIGGER_LEVEL</name>
40884              <description>- 0: trigger signal is a pulse input, a positive edge detected on the trigger signal triggers a new scan.
40885- 1: trigger signal is a level input, as long as the trigger signal remains high the SAR will do continuous scans.</description>
40886              <bitRange>[18:18]</bitRange>
40887              <access>read-write</access>
40888            </field>
40889            <field>
40890              <name>DSI_SYNC_TRIGGER</name>
40891              <description>- 0: bypass clock domain synchronization of the trigger signal.
40892- 1: synchronize the trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain.</description>
40893              <bitRange>[19:19]</bitRange>
40894              <access>read-write</access>
40895            </field>
40896            <field>
40897              <name>UAB_SCAN_MODE</name>
40898              <description>Select whether UABs are scheduled or unscheduled. When no UAB is scanned this selection is ignored.</description>
40899              <bitRange>[22:22]</bitRange>
40900              <access>read-write</access>
40901              <enumeratedValues>
40902                <enumeratedValue>
40903                  <name>UNSCHEDULED</name>
40904                  <description>Unscheduled UABs: one or more of the UABs scanned by the SAR is not scheduled, for each channel that scans a UAB the SAR will wait for a positive edge on the trigger output of that UAB. Caveat: in this mode the length of SAR scan can be variable.</description>
40905                  <value>0</value>
40906                </enumeratedValue>
40907                <enumeratedValue>
40908                  <name>SCHEDULED</name>
40909                  <description>Scheduled UABs: All UABs scanned by the SAR are assumed to be properly scheduled, i.e. their output is assumed to be valid when sampled by the SAR and the SAR does not wait. In this mode the length of the SAR scan is constant.
40910This mode requires that the SAR scans strictly periodically, i.e. the SAR has to either run continuously or has to be triggered by a periodic hardware trigger (TCPWM or UDB timer). It also requires that the end of the UAB valid phase is precisely aligned with the end of the SAR sample period (using UAB.STARTUP_DELAY). Normally this scheduling is done by Creator.</description>
40911                  <value>1</value>
40912                </enumeratedValue>
40913              </enumeratedValues>
40914            </field>
40915            <field>
40916              <name>REPEAT_INVALID</name>
40917              <description>For unscheduled UAB_SCAN_MODE only, do the following if an invalid sample is received:
40918- 0: use the last known valid sample for that channel and clear the NEWVALUE flag
40919- 1: repeat the conversions until a valid sample is received (caveat: could be never if the UAB valid window is incorrectly schedule w.r.t. SAR sampling)</description>
40920              <bitRange>[23:23]</bitRange>
40921              <access>read-write</access>
40922            </field>
40923            <field>
40924              <name>VALID_SEL</name>
40925              <description>Static UAB Valid select
409260=UAB0 half 0 Valid output
409271=UAB0 half 1 Valid output
409282=UAB1 half 0 Valid output
409293=UAB1 half 1 Valid output
409304=UAB2 half 0 Valid output
409315=UAB2 half 1 Valid output
409326=UAB3 half 0 Valid output
409337=UAB3 half 1 Valid output</description>
40934              <bitRange>[26:24]</bitRange>
40935              <access>read-write</access>
40936            </field>
40937            <field>
40938              <name>VALID_SEL_EN</name>
40939              <description>Enable static UAB Valid selection (override Hardware)</description>
40940              <bitRange>[27:27]</bitRange>
40941              <access>read-write</access>
40942            </field>
40943            <field>
40944              <name>VALID_IGNORE</name>
40945              <description>Ignore UAB valid signal, including the dynamic/Hardware from AROUTE and the static Valid selection from the VALID_SEL fields above</description>
40946              <bitRange>[28:28]</bitRange>
40947              <access>read-write</access>
40948            </field>
40949            <field>
40950              <name>TRIGGER_OUT_EN</name>
40951              <description>SAR output trigger enable (used for UAB synchronization). To ensure multiple UABs starting at the same trigger it is recommended to use this bit to temporarily disable the trigger output until all those UABs are set to run (UAB.SRAM_CTRL.RUN=1).</description>
40952              <bitRange>[30:30]</bitRange>
40953              <access>read-write</access>
40954            </field>
40955            <field>
40956              <name>EOS_DSI_OUT_EN</name>
40957              <description>Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardware also a trigger pulse is send on the tr_sar_out signal.</description>
40958              <bitRange>[31:31]</bitRange>
40959              <access>read-write</access>
40960            </field>
40961          </fields>
40962        </register>
40963        <register>
40964          <name>SAMPLE_TIME01</name>
40965          <description>Sample time specification ST0 and ST1</description>
40966          <addressOffset>0x10</addressOffset>
40967          <size>32</size>
40968          <access>read-write</access>
40969          <resetValue>0x30003</resetValue>
40970          <resetMask>0x3FF03FF</resetMask>
40971          <fields>
40972            <field>
40973              <name>SAMPLE_TIME0</name>
40974              <description>Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is one clock less than specified here. The minimum sample time is 167ns, which is 3.0 cycles (4 in this field) with an 18MHz clock. Minimum legal value in this register is 2.</description>
40975              <bitRange>[9:0]</bitRange>
40976              <access>read-write</access>
40977            </field>
40978            <field>
40979              <name>SAMPLE_TIME1</name>
40980              <description>Sample time1</description>
40981              <bitRange>[25:16]</bitRange>
40982              <access>read-write</access>
40983            </field>
40984          </fields>
40985        </register>
40986        <register>
40987          <name>SAMPLE_TIME23</name>
40988          <description>Sample time specification ST2 and ST3</description>
40989          <addressOffset>0x14</addressOffset>
40990          <size>32</size>
40991          <access>read-write</access>
40992          <resetValue>0x30003</resetValue>
40993          <resetMask>0x3FF03FF</resetMask>
40994          <fields>
40995            <field>
40996              <name>SAMPLE_TIME2</name>
40997              <description>Sample time2</description>
40998              <bitRange>[9:0]</bitRange>
40999              <access>read-write</access>
41000            </field>
41001            <field>
41002              <name>SAMPLE_TIME3</name>
41003              <description>Sample time3</description>
41004              <bitRange>[25:16]</bitRange>
41005              <access>read-write</access>
41006            </field>
41007          </fields>
41008        </register>
41009        <register>
41010          <name>RANGE_THRES</name>
41011          <description>Global range detect threshold register.</description>
41012          <addressOffset>0x18</addressOffset>
41013          <size>32</size>
41014          <access>read-write</access>
41015          <resetValue>0x0</resetValue>
41016          <resetMask>0xFFFFFFFF</resetMask>
41017          <fields>
41018            <field>
41019              <name>RANGE_LOW</name>
41020              <description>Low threshold for range detect.</description>
41021              <bitRange>[15:0]</bitRange>
41022              <access>read-write</access>
41023            </field>
41024            <field>
41025              <name>RANGE_HIGH</name>
41026              <description>High threshold for range detect.</description>
41027              <bitRange>[31:16]</bitRange>
41028              <access>read-write</access>
41029            </field>
41030          </fields>
41031        </register>
41032        <register>
41033          <name>RANGE_COND</name>
41034          <description>Global range detect mode register.</description>
41035          <addressOffset>0x1C</addressOffset>
41036          <size>32</size>
41037          <access>read-write</access>
41038          <resetValue>0x0</resetValue>
41039          <resetMask>0xC0000000</resetMask>
41040          <fields>
41041            <field>
41042              <name>RANGE_COND</name>
41043              <description>Range condition select.</description>
41044              <bitRange>[31:30]</bitRange>
41045              <access>read-write</access>
41046              <enumeratedValues>
41047                <enumeratedValue>
41048                  <name>BELOW</name>
41049                  <description>result &lt; RANGE_LOW</description>
41050                  <value>0</value>
41051                </enumeratedValue>
41052                <enumeratedValue>
41053                  <name>INSIDE</name>
41054                  <description>RANGE_LOW &lt;= result &lt; RANGE_HIGH</description>
41055                  <value>1</value>
41056                </enumeratedValue>
41057                <enumeratedValue>
41058                  <name>ABOVE</name>
41059                  <description>RANGE_HIGH &lt;= result</description>
41060                  <value>2</value>
41061                </enumeratedValue>
41062                <enumeratedValue>
41063                  <name>OUTSIDE</name>
41064                  <description>result &lt; RANGE_LOW || RANGE_HIGH &lt;= result</description>
41065                  <value>3</value>
41066                </enumeratedValue>
41067              </enumeratedValues>
41068            </field>
41069          </fields>
41070        </register>
41071        <register>
41072          <name>CHAN_EN</name>
41073          <description>Enable bits for the channels</description>
41074          <addressOffset>0x20</addressOffset>
41075          <size>32</size>
41076          <access>read-write</access>
41077          <resetValue>0x0</resetValue>
41078          <resetMask>0xFFFF</resetMask>
41079          <fields>
41080            <field>
41081              <name>CHAN_EN</name>
41082              <description>Channel enable.
41083- 0: the corresponding channel is disabled.
41084- 1: the corresponding channel is enabled, it will be included in the next scan.</description>
41085              <bitRange>[15:0]</bitRange>
41086              <access>read-write</access>
41087            </field>
41088          </fields>
41089        </register>
41090        <register>
41091          <name>START_CTRL</name>
41092          <description>Start control register (firmware trigger).</description>
41093          <addressOffset>0x24</addressOffset>
41094          <size>32</size>
41095          <access>read-write</access>
41096          <resetValue>0x0</resetValue>
41097          <resetMask>0x1</resetMask>
41098          <fields>
41099            <field>
41100              <name>FW_TRIGGER</name>
41101              <description>When firmware writes a 1 here it will trigger the next scan of enabled channels, hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after the next scan is done. This bit is also cleared when the SAR is disabled.</description>
41102              <bitRange>[0:0]</bitRange>
41103              <access>read-write</access>
41104            </field>
41105          </fields>
41106        </register>
41107        <register>
41108          <dim>16</dim>
41109          <dimIncrement>4</dimIncrement>
41110          <name>CHAN_CONFIG[%s]</name>
41111          <description>Channel configuration register.</description>
41112          <addressOffset>0x80</addressOffset>
41113          <size>32</size>
41114          <access>read-write</access>
41115          <resetValue>0x0</resetValue>
41116          <resetMask>0x81773577</resetMask>
41117          <fields>
41118            <field>
41119              <name>POS_PIN_ADDR</name>
41120              <description>Address of the pin to be sampled by this channel (connected to Vplus)</description>
41121              <bitRange>[2:0]</bitRange>
41122              <access>read-write</access>
41123            </field>
41124            <field>
41125              <name>POS_PORT_ADDR</name>
41126              <description>Address of the port that contains the pin to be sampled by this channel (connected to Vplus)</description>
41127              <bitRange>[6:4]</bitRange>
41128              <access>read-write</access>
41129              <enumeratedValues>
41130                <enumeratedValue>
41131                  <name>SARMUX</name>
41132                  <description>SARMUX pins.</description>
41133                  <value>0</value>
41134                </enumeratedValue>
41135                <enumeratedValue>
41136                  <name>CTB0</name>
41137                  <description>CTB0</description>
41138                  <value>1</value>
41139                </enumeratedValue>
41140                <enumeratedValue>
41141                  <name>CTB1</name>
41142                  <description>CTB1</description>
41143                  <value>2</value>
41144                </enumeratedValue>
41145                <enumeratedValue>
41146                  <name>CTB2</name>
41147                  <description>CTB2</description>
41148                  <value>3</value>
41149                </enumeratedValue>
41150                <enumeratedValue>
41151                  <name>CTB3</name>
41152                  <description>CTB3</description>
41153                  <value>4</value>
41154                </enumeratedValue>
41155                <enumeratedValue>
41156                  <name>AROUTE_VIRT2</name>
41157                  <description>AROUTE virtual port2 (VPORT2)</description>
41158                  <value>5</value>
41159                </enumeratedValue>
41160                <enumeratedValue>
41161                  <name>AROUTE_VIRT1</name>
41162                  <description>AROUTE virtual port1 (VPORT1)</description>
41163                  <value>6</value>
41164                </enumeratedValue>
41165                <enumeratedValue>
41166                  <name>SARMUX_VIRT</name>
41167                  <description>SARMUX virtual port (VPORT0)</description>
41168                  <value>7</value>
41169                </enumeratedValue>
41170              </enumeratedValues>
41171            </field>
41172            <field>
41173              <name>DIFFERENTIAL_EN</name>
41174              <description>Differential enable for this channel.
41175If NEG_ADDR_EN=0 and this bit is 1 then POS_PIN_ADDR[0] is ignored and considered to be 0, i.e. POS_PIN_ADDR points to the even pin of a pin pair. In that case the even pin of the pair is connected to Vplus and the odd pin of the pair is connected to Vminus. POS_PORT_ADDR is used to identify the port that contains the pins.
41176- 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register.
41177- 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (if NEG_ADDR_EN=0 then POS_PIN_ADDR[0] is ignored).</description>
41178              <bitRange>[8:8]</bitRange>
41179              <access>read-write</access>
41180            </field>
41181            <field>
41182              <name>AVG_EN</name>
41183              <description>Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)</description>
41184              <bitRange>[10:10]</bitRange>
41185              <access>read-write</access>
41186            </field>
41187            <field>
41188              <name>SAMPLE_TIME_SEL</name>
41189              <description>Sample time select: select which of the 4 global sample times to use for this channel</description>
41190              <bitRange>[13:12]</bitRange>
41191              <access>read-write</access>
41192            </field>
41193            <field>
41194              <name>NEG_PIN_ADDR</name>
41195              <description>Address of the neg pin to be sampled by this channel.</description>
41196              <bitRange>[18:16]</bitRange>
41197              <access>read-write</access>
41198            </field>
41199            <field>
41200              <name>NEG_PORT_ADDR</name>
41201              <description>Address of the neg port that contains the pin to be sampled by this channel.</description>
41202              <bitRange>[22:20]</bitRange>
41203              <access>read-write</access>
41204              <enumeratedValues>
41205                <enumeratedValue>
41206                  <name>SARMUX</name>
41207                  <description>SARMUX pins.</description>
41208                  <value>0</value>
41209                </enumeratedValue>
41210                <enumeratedValue>
41211                  <name>AROUTE_VIRT2</name>
41212                  <description>AROUTE virtual port2 (VPORT2)</description>
41213                  <value>5</value>
41214                </enumeratedValue>
41215                <enumeratedValue>
41216                  <name>AROUTE_VIRT1</name>
41217                  <description>AROUTE virtual port1 (VPORT1)</description>
41218                  <value>6</value>
41219                </enumeratedValue>
41220                <enumeratedValue>
41221                  <name>SARMUX_VIRT</name>
41222                  <description>SARMUX virtual port (VPORT0)</description>
41223                  <value>7</value>
41224                </enumeratedValue>
41225              </enumeratedValues>
41226            </field>
41227            <field>
41228              <name>NEG_ADDR_EN</name>
41229              <description>1 - The NEG_PIN_ADDR and NEG_PORT_ADDR determines what drives the Vminus pin. This is a variation of differential mode with no even-odd pair limitation                                                                                                                                0 -  The NEG_SEL determines what drives the Vminus pin.</description>
41230              <bitRange>[24:24]</bitRange>
41231              <access>read-write</access>
41232            </field>
41233            <field>
41234              <name>DSI_OUT_EN</name>
41235              <description>DSI data output enable for this channel.
41236- 0: the conversion result for this channel is only stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set.
41237- 1: the conversion result for this channel is stored in the channel data register and the corresponding CHAN_DATA_VALID bit is set. The same data (same formatting), together with the channel number, is sent out on the DSI communication channel for processing in UDBs.</description>
41238              <bitRange>[31:31]</bitRange>
41239              <access>read-write</access>
41240            </field>
41241          </fields>
41242        </register>
41243        <register>
41244          <dim>16</dim>
41245          <dimIncrement>4</dimIncrement>
41246          <name>CHAN_WORK[%s]</name>
41247          <description>Channel working data register</description>
41248          <addressOffset>0x100</addressOffset>
41249          <size>32</size>
41250          <access>read-only</access>
41251          <resetValue>0x0</resetValue>
41252          <resetMask>0x88000000</resetMask>
41253          <fields>
41254            <field>
41255              <name>WORK</name>
41256              <description>SAR conversion working data of the channel. The data is written here right after sampling this channel.</description>
41257              <bitRange>[15:0]</bitRange>
41258              <access>read-only</access>
41259            </field>
41260            <field>
41261              <name>CHAN_WORK_NEWVALUE_MIR</name>
41262              <description>mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register</description>
41263              <bitRange>[27:27]</bitRange>
41264              <access>read-only</access>
41265            </field>
41266            <field>
41267              <name>CHAN_WORK_UPDATED_MIR</name>
41268              <description>mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register</description>
41269              <bitRange>[31:31]</bitRange>
41270              <access>read-only</access>
41271            </field>
41272          </fields>
41273        </register>
41274        <register>
41275          <dim>16</dim>
41276          <dimIncrement>4</dimIncrement>
41277          <name>CHAN_RESULT[%s]</name>
41278          <description>Channel result data register</description>
41279          <addressOffset>0x180</addressOffset>
41280          <size>32</size>
41281          <access>read-only</access>
41282          <resetValue>0x0</resetValue>
41283          <resetMask>0xE8000000</resetMask>
41284          <fields>
41285            <field>
41286              <name>RESULT</name>
41287              <description>SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled.</description>
41288              <bitRange>[15:0]</bitRange>
41289              <access>read-only</access>
41290            </field>
41291            <field>
41292              <name>CHAN_RESULT_NEWVALUE_MIR</name>
41293              <description>mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register</description>
41294              <bitRange>[27:27]</bitRange>
41295              <access>read-only</access>
41296            </field>
41297            <field>
41298              <name>SATURATE_INTR_MIR</name>
41299              <description>mirror bit of corresponding bit in SAR_SATURATE_INTR register</description>
41300              <bitRange>[29:29]</bitRange>
41301              <access>read-only</access>
41302            </field>
41303            <field>
41304              <name>RANGE_INTR_MIR</name>
41305              <description>mirror bit of corresponding bit in SAR_RANGE_INTR register</description>
41306              <bitRange>[30:30]</bitRange>
41307              <access>read-only</access>
41308            </field>
41309            <field>
41310              <name>CHAN_RESULT_UPDATED_MIR</name>
41311              <description>mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register</description>
41312              <bitRange>[31:31]</bitRange>
41313              <access>read-only</access>
41314            </field>
41315          </fields>
41316        </register>
41317        <register>
41318          <name>CHAN_WORK_UPDATED</name>
41319          <description>Channel working data register 'updated' bits</description>
41320          <addressOffset>0x200</addressOffset>
41321          <size>32</size>
41322          <access>read-only</access>
41323          <resetValue>0x0</resetValue>
41324          <resetMask>0xFFFF</resetMask>
41325          <fields>
41326            <field>
41327              <name>CHAN_WORK_UPDATED</name>
41328              <description>If set the corresponding WORK register was updated, i.e. was already sampled during the current scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging.</description>
41329              <bitRange>[15:0]</bitRange>
41330              <access>read-only</access>
41331            </field>
41332          </fields>
41333        </register>
41334        <register>
41335          <name>CHAN_RESULT_UPDATED</name>
41336          <description>Channel result data register 'updated' bits</description>
41337          <addressOffset>0x204</addressOffset>
41338          <size>32</size>
41339          <access>read-only</access>
41340          <resetValue>0x0</resetValue>
41341          <resetMask>0xFFFF</resetMask>
41342          <fields>
41343            <field>
41344              <name>CHAN_RESULT_UPDATED</name>
41345              <description>If set the corresponding RESULT register was updated, i.e. was sampled during the previous scan and, in case of Interleaved averaging, reached the averaging count. If this bit is low then either the channel is not enabled or the averaging count is not yet reached for Interleaved averaging.</description>
41346              <bitRange>[15:0]</bitRange>
41347              <access>read-only</access>
41348            </field>
41349          </fields>
41350        </register>
41351        <register>
41352          <name>CHAN_WORK_NEWVALUE</name>
41353          <description>Channel working data register 'new value' bits</description>
41354          <addressOffset>0x208</addressOffset>
41355          <size>32</size>
41356          <access>read-only</access>
41357          <resetValue>0x0</resetValue>
41358          <resetMask>0xFFFF</resetMask>
41359          <fields>
41360            <field>
41361              <name>CHAN_WORK_NEWVALUE</name>
41362              <description>If set the corresponding WORK data received a new value, i.e. was already sampled during the current scan and data was valid.
41363In case of  a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid.
41364In case of averaging this New Value bit is an OR of all the valid bits received by each conversion.</description>
41365              <bitRange>[15:0]</bitRange>
41366              <access>read-only</access>
41367            </field>
41368          </fields>
41369        </register>
41370        <register>
41371          <name>CHAN_RESULT_NEWVALUE</name>
41372          <description>Channel result data register 'new value' bits</description>
41373          <addressOffset>0x20C</addressOffset>
41374          <size>32</size>
41375          <access>read-only</access>
41376          <resetValue>0x0</resetValue>
41377          <resetMask>0xFFFF</resetMask>
41378          <fields>
41379            <field>
41380              <name>CHAN_RESULT_NEWVALUE</name>
41381              <description>If set the corresponding RESULT data received a new value, i.e. was sampled during the last scan and data was valid.
41382In case of  a UAB this New Value bit reflects the value of UAB.valid output, for anything else the data is always valid.
41383In case of averaging this New Value bit is an OR of all the valid bits received by each conversion.</description>
41384              <bitRange>[15:0]</bitRange>
41385              <access>read-only</access>
41386            </field>
41387          </fields>
41388        </register>
41389        <register>
41390          <name>INTR</name>
41391          <description>Interrupt request register.</description>
41392          <addressOffset>0x210</addressOffset>
41393          <size>32</size>
41394          <access>read-write</access>
41395          <resetValue>0x0</resetValue>
41396          <resetMask>0xFF</resetMask>
41397          <fields>
41398            <field>
41399              <name>EOS_INTR</name>
41400              <description>End Of Scan Interrupt: hardware sets this interrupt after completing a scan of all the enabled channels. Write with '1' to clear bit.</description>
41401              <bitRange>[0:0]</bitRange>
41402              <access>read-write</access>
41403            </field>
41404            <field>
41405              <name>OVERFLOW_INTR</name>
41406              <description>Overflow Interrupt: hardware sets this interrupt when it sets a new EOS_INTR while that bit was not yet cleared by the firmware. Write with '1' to clear bit.</description>
41407              <bitRange>[1:1]</bitRange>
41408              <access>read-write</access>
41409            </field>
41410            <field>
41411              <name>FW_COLLISION_INTR</name>
41412              <description>Firmware Collision Interrupt: hardware sets this interrupt when FW_TRIGGER is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the FW_TRIGGER has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit.</description>
41413              <bitRange>[2:2]</bitRange>
41414              <access>read-write</access>
41415            </field>
41416            <field>
41417              <name>DSI_COLLISION_INTR</name>
41418              <description>DSI Collision Interrupt: hardware sets this interrupt when the DSI trigger signal is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the DSI trigger has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the channels were sampled later than was intended (jitter). Write with '1' to clear bit.</description>
41419              <bitRange>[3:3]</bitRange>
41420              <access>read-write</access>
41421            </field>
41422            <field>
41423              <name>INJ_EOC_INTR</name>
41424              <description>Injection End of Conversion Interrupt: hardware sets this interrupt after completing the conversion for the injection channel (irrespective of if tailgating was used). Write with '1' to clear bit.</description>
41425              <bitRange>[4:4]</bitRange>
41426              <access>read-write</access>
41427            </field>
41428            <field>
41429              <name>INJ_SATURATE_INTR</name>
41430              <description>Injection Saturation Interrupt: hardware sets this interrupt if an injection conversion result (before averaging) is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit.</description>
41431              <bitRange>[5:5]</bitRange>
41432              <access>read-write</access>
41433            </field>
41434            <field>
41435              <name>INJ_RANGE_INTR</name>
41436              <description>Injection Range detect Interrupt: hardware sets this interrupt if the injection conversion result (after averaging) met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit.</description>
41437              <bitRange>[6:6]</bitRange>
41438              <access>read-write</access>
41439            </field>
41440            <field>
41441              <name>INJ_COLLISION_INTR</name>
41442              <description>Injection Collision Interrupt: hardware sets this interrupt when the injection trigger signal is asserted (INJ_START_EN==1 &amp;&amp; INJ_TAILGATING==0) while the SAR is BUSY. Raising this interrupt is delayed to when the sampling of the injection channel has been completed, i.e. not when the preceding scan with which this trigger collided is completed. When this interrupt is set it implies that the injection channel was sampled later than was intended. Write with '1' to clear bit.</description>
41443              <bitRange>[7:7]</bitRange>
41444              <access>read-write</access>
41445            </field>
41446          </fields>
41447        </register>
41448        <register>
41449          <name>INTR_SET</name>
41450          <description>Interrupt set request register</description>
41451          <addressOffset>0x214</addressOffset>
41452          <size>32</size>
41453          <access>read-write</access>
41454          <resetValue>0x0</resetValue>
41455          <resetMask>0xFF</resetMask>
41456          <fields>
41457            <field>
41458              <name>EOS_SET</name>
41459              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41460              <bitRange>[0:0]</bitRange>
41461              <access>read-write</access>
41462            </field>
41463            <field>
41464              <name>OVERFLOW_SET</name>
41465              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41466              <bitRange>[1:1]</bitRange>
41467              <access>read-write</access>
41468            </field>
41469            <field>
41470              <name>FW_COLLISION_SET</name>
41471              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41472              <bitRange>[2:2]</bitRange>
41473              <access>read-write</access>
41474            </field>
41475            <field>
41476              <name>DSI_COLLISION_SET</name>
41477              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41478              <bitRange>[3:3]</bitRange>
41479              <access>read-write</access>
41480            </field>
41481            <field>
41482              <name>INJ_EOC_SET</name>
41483              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41484              <bitRange>[4:4]</bitRange>
41485              <access>read-write</access>
41486            </field>
41487            <field>
41488              <name>INJ_SATURATE_SET</name>
41489              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41490              <bitRange>[5:5]</bitRange>
41491              <access>read-write</access>
41492            </field>
41493            <field>
41494              <name>INJ_RANGE_SET</name>
41495              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41496              <bitRange>[6:6]</bitRange>
41497              <access>read-write</access>
41498            </field>
41499            <field>
41500              <name>INJ_COLLISION_SET</name>
41501              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41502              <bitRange>[7:7]</bitRange>
41503              <access>read-write</access>
41504            </field>
41505          </fields>
41506        </register>
41507        <register>
41508          <name>INTR_MASK</name>
41509          <description>Interrupt mask register.</description>
41510          <addressOffset>0x218</addressOffset>
41511          <size>32</size>
41512          <access>read-write</access>
41513          <resetValue>0x0</resetValue>
41514          <resetMask>0xFF</resetMask>
41515          <fields>
41516            <field>
41517              <name>EOS_MASK</name>
41518              <description>Mask bit for corresponding bit in interrupt request register.</description>
41519              <bitRange>[0:0]</bitRange>
41520              <access>read-write</access>
41521            </field>
41522            <field>
41523              <name>OVERFLOW_MASK</name>
41524              <description>Mask bit for corresponding bit in interrupt request register.</description>
41525              <bitRange>[1:1]</bitRange>
41526              <access>read-write</access>
41527            </field>
41528            <field>
41529              <name>FW_COLLISION_MASK</name>
41530              <description>Mask bit for corresponding bit in interrupt request register.</description>
41531              <bitRange>[2:2]</bitRange>
41532              <access>read-write</access>
41533            </field>
41534            <field>
41535              <name>DSI_COLLISION_MASK</name>
41536              <description>Mask bit for corresponding bit in interrupt request register.</description>
41537              <bitRange>[3:3]</bitRange>
41538              <access>read-write</access>
41539            </field>
41540            <field>
41541              <name>INJ_EOC_MASK</name>
41542              <description>Mask bit for corresponding bit in interrupt request register.</description>
41543              <bitRange>[4:4]</bitRange>
41544              <access>read-write</access>
41545            </field>
41546            <field>
41547              <name>INJ_SATURATE_MASK</name>
41548              <description>Mask bit for corresponding bit in interrupt request register.</description>
41549              <bitRange>[5:5]</bitRange>
41550              <access>read-write</access>
41551            </field>
41552            <field>
41553              <name>INJ_RANGE_MASK</name>
41554              <description>Mask bit for corresponding bit in interrupt request register.</description>
41555              <bitRange>[6:6]</bitRange>
41556              <access>read-write</access>
41557            </field>
41558            <field>
41559              <name>INJ_COLLISION_MASK</name>
41560              <description>Mask bit for corresponding bit in interrupt request register.</description>
41561              <bitRange>[7:7]</bitRange>
41562              <access>read-write</access>
41563            </field>
41564          </fields>
41565        </register>
41566        <register>
41567          <name>INTR_MASKED</name>
41568          <description>Interrupt masked request register</description>
41569          <addressOffset>0x21C</addressOffset>
41570          <size>32</size>
41571          <access>read-only</access>
41572          <resetValue>0x0</resetValue>
41573          <resetMask>0xFF</resetMask>
41574          <fields>
41575            <field>
41576              <name>EOS_MASKED</name>
41577              <description>Logical and of corresponding request and mask bits.</description>
41578              <bitRange>[0:0]</bitRange>
41579              <access>read-only</access>
41580            </field>
41581            <field>
41582              <name>OVERFLOW_MASKED</name>
41583              <description>Logical and of corresponding request and mask bits.</description>
41584              <bitRange>[1:1]</bitRange>
41585              <access>read-only</access>
41586            </field>
41587            <field>
41588              <name>FW_COLLISION_MASKED</name>
41589              <description>Logical and of corresponding request and mask bits.</description>
41590              <bitRange>[2:2]</bitRange>
41591              <access>read-only</access>
41592            </field>
41593            <field>
41594              <name>DSI_COLLISION_MASKED</name>
41595              <description>Logical and of corresponding request and mask bits.</description>
41596              <bitRange>[3:3]</bitRange>
41597              <access>read-only</access>
41598            </field>
41599            <field>
41600              <name>INJ_EOC_MASKED</name>
41601              <description>Logical and of corresponding request and mask bits.</description>
41602              <bitRange>[4:4]</bitRange>
41603              <access>read-only</access>
41604            </field>
41605            <field>
41606              <name>INJ_SATURATE_MASKED</name>
41607              <description>Logical and of corresponding request and mask bits.</description>
41608              <bitRange>[5:5]</bitRange>
41609              <access>read-only</access>
41610            </field>
41611            <field>
41612              <name>INJ_RANGE_MASKED</name>
41613              <description>Logical and of corresponding request and mask bits.</description>
41614              <bitRange>[6:6]</bitRange>
41615              <access>read-only</access>
41616            </field>
41617            <field>
41618              <name>INJ_COLLISION_MASKED</name>
41619              <description>Logical and of corresponding request and mask bits.</description>
41620              <bitRange>[7:7]</bitRange>
41621              <access>read-only</access>
41622            </field>
41623          </fields>
41624        </register>
41625        <register>
41626          <name>SATURATE_INTR</name>
41627          <description>Saturate interrupt request register.</description>
41628          <addressOffset>0x220</addressOffset>
41629          <size>32</size>
41630          <access>read-write</access>
41631          <resetValue>0x0</resetValue>
41632          <resetMask>0xFFFF</resetMask>
41633          <fields>
41634            <field>
41635              <name>SATURATE_INTR</name>
41636              <description>Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF, this is an indication that the ADC likely saturated. Write with '1' to clear bit.</description>
41637              <bitRange>[15:0]</bitRange>
41638              <access>read-write</access>
41639            </field>
41640          </fields>
41641        </register>
41642        <register>
41643          <name>SATURATE_INTR_SET</name>
41644          <description>Saturate interrupt set request register</description>
41645          <addressOffset>0x224</addressOffset>
41646          <size>32</size>
41647          <access>read-write</access>
41648          <resetValue>0x0</resetValue>
41649          <resetMask>0xFFFF</resetMask>
41650          <fields>
41651            <field>
41652              <name>SATURATE_SET</name>
41653              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41654              <bitRange>[15:0]</bitRange>
41655              <access>read-write</access>
41656            </field>
41657          </fields>
41658        </register>
41659        <register>
41660          <name>SATURATE_INTR_MASK</name>
41661          <description>Saturate interrupt mask register.</description>
41662          <addressOffset>0x228</addressOffset>
41663          <size>32</size>
41664          <access>read-write</access>
41665          <resetValue>0x0</resetValue>
41666          <resetMask>0xFFFF</resetMask>
41667          <fields>
41668            <field>
41669              <name>SATURATE_MASK</name>
41670              <description>Mask bit for corresponding bit in interrupt request register.</description>
41671              <bitRange>[15:0]</bitRange>
41672              <access>read-write</access>
41673            </field>
41674          </fields>
41675        </register>
41676        <register>
41677          <name>SATURATE_INTR_MASKED</name>
41678          <description>Saturate interrupt masked request register</description>
41679          <addressOffset>0x22C</addressOffset>
41680          <size>32</size>
41681          <access>read-only</access>
41682          <resetValue>0x0</resetValue>
41683          <resetMask>0xFFFF</resetMask>
41684          <fields>
41685            <field>
41686              <name>SATURATE_MASKED</name>
41687              <description>Logical and of corresponding request and mask bits.</description>
41688              <bitRange>[15:0]</bitRange>
41689              <access>read-only</access>
41690            </field>
41691          </fields>
41692        </register>
41693        <register>
41694          <name>RANGE_INTR</name>
41695          <description>Range detect interrupt request register.</description>
41696          <addressOffset>0x230</addressOffset>
41697          <size>32</size>
41698          <access>read-write</access>
41699          <resetValue>0x0</resetValue>
41700          <resetMask>0xFFFF</resetMask>
41701          <fields>
41702            <field>
41703              <name>RANGE_INTR</name>
41704              <description>Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit.</description>
41705              <bitRange>[15:0]</bitRange>
41706              <access>read-write</access>
41707            </field>
41708          </fields>
41709        </register>
41710        <register>
41711          <name>RANGE_INTR_SET</name>
41712          <description>Range detect interrupt set request register</description>
41713          <addressOffset>0x234</addressOffset>
41714          <size>32</size>
41715          <access>read-write</access>
41716          <resetValue>0x0</resetValue>
41717          <resetMask>0xFFFF</resetMask>
41718          <fields>
41719            <field>
41720              <name>RANGE_SET</name>
41721              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
41722              <bitRange>[15:0]</bitRange>
41723              <access>read-write</access>
41724            </field>
41725          </fields>
41726        </register>
41727        <register>
41728          <name>RANGE_INTR_MASK</name>
41729          <description>Range detect interrupt mask register.</description>
41730          <addressOffset>0x238</addressOffset>
41731          <size>32</size>
41732          <access>read-write</access>
41733          <resetValue>0x0</resetValue>
41734          <resetMask>0xFFFF</resetMask>
41735          <fields>
41736            <field>
41737              <name>RANGE_MASK</name>
41738              <description>Mask bit for corresponding bit in interrupt request register.</description>
41739              <bitRange>[15:0]</bitRange>
41740              <access>read-write</access>
41741            </field>
41742          </fields>
41743        </register>
41744        <register>
41745          <name>RANGE_INTR_MASKED</name>
41746          <description>Range interrupt masked request register</description>
41747          <addressOffset>0x23C</addressOffset>
41748          <size>32</size>
41749          <access>read-only</access>
41750          <resetValue>0x0</resetValue>
41751          <resetMask>0xFFFF</resetMask>
41752          <fields>
41753            <field>
41754              <name>RANGE_MASKED</name>
41755              <description>Logical and of corresponding request and mask bits.</description>
41756              <bitRange>[15:0]</bitRange>
41757              <access>read-only</access>
41758            </field>
41759          </fields>
41760        </register>
41761        <register>
41762          <name>INTR_CAUSE</name>
41763          <description>Interrupt cause register</description>
41764          <addressOffset>0x240</addressOffset>
41765          <size>32</size>
41766          <access>read-only</access>
41767          <resetValue>0x0</resetValue>
41768          <resetMask>0xC00000FF</resetMask>
41769          <fields>
41770            <field>
41771              <name>EOS_MASKED_MIR</name>
41772              <description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
41773              <bitRange>[0:0]</bitRange>
41774              <access>read-only</access>
41775            </field>
41776            <field>
41777              <name>OVERFLOW_MASKED_MIR</name>
41778              <description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
41779              <bitRange>[1:1]</bitRange>
41780              <access>read-only</access>
41781            </field>
41782            <field>
41783              <name>FW_COLLISION_MASKED_MIR</name>
41784              <description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
41785              <bitRange>[2:2]</bitRange>
41786              <access>read-only</access>
41787            </field>
41788            <field>
41789              <name>DSI_COLLISION_MASKED_MIR</name>
41790              <description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
41791              <bitRange>[3:3]</bitRange>
41792              <access>read-only</access>
41793            </field>
41794            <field>
41795              <name>INJ_EOC_MASKED_MIR</name>
41796              <description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
41797              <bitRange>[4:4]</bitRange>
41798              <access>read-only</access>
41799            </field>
41800            <field>
41801              <name>INJ_SATURATE_MASKED_MIR</name>
41802              <description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
41803              <bitRange>[5:5]</bitRange>
41804              <access>read-only</access>
41805            </field>
41806            <field>
41807              <name>INJ_RANGE_MASKED_MIR</name>
41808              <description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
41809              <bitRange>[6:6]</bitRange>
41810              <access>read-only</access>
41811            </field>
41812            <field>
41813              <name>INJ_COLLISION_MASKED_MIR</name>
41814              <description>Mirror copy of corresponding bit in SAR_INTR_MASKED</description>
41815              <bitRange>[7:7]</bitRange>
41816              <access>read-only</access>
41817            </field>
41818            <field>
41819              <name>SATURATE_MASKED_RED</name>
41820              <description>Reduction OR of all SAR_SATURATION_INTR_MASKED bits</description>
41821              <bitRange>[30:30]</bitRange>
41822              <access>read-only</access>
41823            </field>
41824            <field>
41825              <name>RANGE_MASKED_RED</name>
41826              <description>Reduction OR of all SAR_RANGE_INTR_MASKED bits</description>
41827              <bitRange>[31:31]</bitRange>
41828              <access>read-only</access>
41829            </field>
41830          </fields>
41831        </register>
41832        <register>
41833          <name>INJ_CHAN_CONFIG</name>
41834          <description>Injection channel configuration register.</description>
41835          <addressOffset>0x280</addressOffset>
41836          <size>32</size>
41837          <access>read-write</access>
41838          <resetValue>0x0</resetValue>
41839          <resetMask>0xC0003577</resetMask>
41840          <fields>
41841            <field>
41842              <name>INJ_PIN_ADDR</name>
41843              <description>Address of the pin to be sampled by this injection channel. If differential is enabled then INJ_PIN_ADDR[0] is ignored and considered to be 0, i.e. INJ_PIN_ADDR points to the even pin of a pin pair.</description>
41844              <bitRange>[2:0]</bitRange>
41845              <access>read-write</access>
41846            </field>
41847            <field>
41848              <name>INJ_PORT_ADDR</name>
41849              <description>Address of the port that contains the pin to be sampled by this channel.</description>
41850              <bitRange>[6:4]</bitRange>
41851              <access>read-write</access>
41852              <enumeratedValues>
41853                <enumeratedValue>
41854                  <name>SARMUX</name>
41855                  <description>SARMUX pins.</description>
41856                  <value>0</value>
41857                </enumeratedValue>
41858                <enumeratedValue>
41859                  <name>CTB0</name>
41860                  <description>CTB0</description>
41861                  <value>1</value>
41862                </enumeratedValue>
41863                <enumeratedValue>
41864                  <name>CTB1</name>
41865                  <description>CTB1</description>
41866                  <value>2</value>
41867                </enumeratedValue>
41868                <enumeratedValue>
41869                  <name>CTB2</name>
41870                  <description>CTB2</description>
41871                  <value>3</value>
41872                </enumeratedValue>
41873                <enumeratedValue>
41874                  <name>CTB3</name>
41875                  <description>CTB3</description>
41876                  <value>4</value>
41877                </enumeratedValue>
41878                <enumeratedValue>
41879                  <name>AROUTE_VIRT</name>
41880                  <description>AROUTE virtual port</description>
41881                  <value>6</value>
41882                </enumeratedValue>
41883                <enumeratedValue>
41884                  <name>SARMUX_VIRT</name>
41885                  <description>SARMUX virtual port</description>
41886                  <value>7</value>
41887                </enumeratedValue>
41888              </enumeratedValues>
41889            </field>
41890            <field>
41891              <name>INJ_DIFFERENTIAL_EN</name>
41892              <description>Differential enable for this channel.
41893- 0: The voltage on the addressed pin is measured (Single-ended) and the resulting value is stored in the corresponding data register.
41894- 1: The differential voltage on the addressed pin pair is measured and the resulting value is stored in the corresponding data register. (INJ_PIN_ADDR[0] is ignored).</description>
41895              <bitRange>[8:8]</bitRange>
41896              <access>read-write</access>
41897            </field>
41898            <field>
41899              <name>INJ_AVG_EN</name>
41900              <description>Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)</description>
41901              <bitRange>[10:10]</bitRange>
41902              <access>read-write</access>
41903            </field>
41904            <field>
41905              <name>INJ_SAMPLE_TIME_SEL</name>
41906              <description>Injection sample time select: select which of the 4 global sample times to use for this channel</description>
41907              <bitRange>[13:12]</bitRange>
41908              <access>read-write</access>
41909            </field>
41910            <field>
41911              <name>INJ_TAILGATING</name>
41912              <description>Injection channel tailgating.
41913- 0: no tailgating for this channel, SAR is immediately triggered when the INJ_START_EN bit is set if the SAR is not busy.  If the SAR is busy, the INJ channel addressed pin is sampled at the end of the current scan.
41914- 1: injection channel tailgating. The addressed pin is sampled after the next trigger and after all enabled channels have been scanned.</description>
41915              <bitRange>[30:30]</bitRange>
41916              <access>read-write</access>
41917            </field>
41918            <field>
41919              <name>INJ_START_EN</name>
41920              <description>Set by firmware to enable the injection channel. If INJ_TAILGATING is not set this bit also functions as trigger for this channel. Cleared by hardware after this channel has been sampled (i.e. this channel is always one shot even if CONTINUOUS is set). Also cleared if the SAR is disabled.</description>
41921              <bitRange>[31:31]</bitRange>
41922              <access>read-write</access>
41923            </field>
41924          </fields>
41925        </register>
41926        <register>
41927          <name>INJ_RESULT</name>
41928          <description>Injection channel result register</description>
41929          <addressOffset>0x290</addressOffset>
41930          <size>32</size>
41931          <access>read-only</access>
41932          <resetValue>0x0</resetValue>
41933          <resetMask>0xF8000000</resetMask>
41934          <fields>
41935            <field>
41936              <name>INJ_RESULT</name>
41937              <description>SAR conversion result of the channel.</description>
41938              <bitRange>[15:0]</bitRange>
41939              <access>read-only</access>
41940            </field>
41941            <field>
41942              <name>INJ_NEWVALUE</name>
41943              <description>The data in this register received a new value (only relevant for UAB, this bit shows the value of the UAB valid bit)</description>
41944              <bitRange>[27:27]</bitRange>
41945              <access>read-only</access>
41946            </field>
41947            <field>
41948              <name>INJ_COLLISION_INTR_MIR</name>
41949              <description>mirror bit of corresponding bit in SAR_INTR register</description>
41950              <bitRange>[28:28]</bitRange>
41951              <access>read-only</access>
41952            </field>
41953            <field>
41954              <name>INJ_SATURATE_INTR_MIR</name>
41955              <description>mirror bit of corresponding bit in SAR_INTR register</description>
41956              <bitRange>[29:29]</bitRange>
41957              <access>read-only</access>
41958            </field>
41959            <field>
41960              <name>INJ_RANGE_INTR_MIR</name>
41961              <description>mirror bit of corresponding bit in SAR_INTR register</description>
41962              <bitRange>[30:30]</bitRange>
41963              <access>read-only</access>
41964            </field>
41965            <field>
41966              <name>INJ_EOC_INTR_MIR</name>
41967              <description>mirror bit of corresponding bit in SAR_INTR register</description>
41968              <bitRange>[31:31]</bitRange>
41969              <access>read-only</access>
41970            </field>
41971          </fields>
41972        </register>
41973        <register>
41974          <name>STATUS</name>
41975          <description>Current status of internal SAR registers (mostly for debug)</description>
41976          <addressOffset>0x2A0</addressOffset>
41977          <size>32</size>
41978          <access>read-only</access>
41979          <resetValue>0x0</resetValue>
41980          <resetMask>0xC000001F</resetMask>
41981          <fields>
41982            <field>
41983              <name>CUR_CHAN</name>
41984              <description>current channel being sampled (channel 16 indicates the injection channel), only valid if BUSY.</description>
41985              <bitRange>[4:0]</bitRange>
41986              <access>read-only</access>
41987            </field>
41988            <field>
41989              <name>SW_VREF_NEG</name>
41990              <description>the current switch status, including DSI and sequencer controls, of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL).</description>
41991              <bitRange>[30:30]</bitRange>
41992              <access>read-only</access>
41993            </field>
41994            <field>
41995              <name>BUSY</name>
41996              <description>If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down.</description>
41997              <bitRange>[31:31]</bitRange>
41998              <access>read-only</access>
41999            </field>
42000          </fields>
42001        </register>
42002        <register>
42003          <name>AVG_STAT</name>
42004          <description>Current averaging status (for debug)</description>
42005          <addressOffset>0x2A4</addressOffset>
42006          <size>32</size>
42007          <access>read-only</access>
42008          <resetValue>0x0</resetValue>
42009          <resetMask>0xFF8FFFFF</resetMask>
42010          <fields>
42011            <field>
42012              <name>CUR_AVG_ACCU</name>
42013              <description>the current value of the averaging accumulator</description>
42014              <bitRange>[19:0]</bitRange>
42015              <access>read-only</access>
42016            </field>
42017            <field>
42018              <name>INTRLV_BUSY</name>
42019              <description>If high then the SAR is in the middle of Interleaved averaging spanning several scans. While this bit is high the Firmware should not make any changes to the configuration registers otherwise some results may be incorrect. Note that the CUR_AVG_CNT status register below gives an indication how many more scans need to be done to complete the Interleaved averaging.
42020This bit can be cleared by changing the averaging mode to ACCUNDUMP or by disabling the SAR.</description>
42021              <bitRange>[23:23]</bitRange>
42022              <access>read-only</access>
42023            </field>
42024            <field>
42025              <name>CUR_AVG_CNT</name>
42026              <description>the current value of the averaging counter. Note that the value shown is updated after the sampling time and therefore runs ahead of the accumulator update.</description>
42027              <bitRange>[31:24]</bitRange>
42028              <access>read-only</access>
42029            </field>
42030          </fields>
42031        </register>
42032        <register>
42033          <name>MUX_SWITCH0</name>
42034          <description>SARMUX Firmware switch controls</description>
42035          <addressOffset>0x300</addressOffset>
42036          <size>32</size>
42037          <access>read-write</access>
42038          <resetValue>0x0</resetValue>
42039          <resetMask>0x3FFFFFFF</resetMask>
42040          <fields>
42041            <field>
42042              <name>MUX_FW_P0_VPLUS</name>
42043              <description>Firmware control: 0=open, 1=close switch between pin P0 and vplus signal. Write with '1' to set bit.</description>
42044              <bitRange>[0:0]</bitRange>
42045              <access>read-write</access>
42046            </field>
42047            <field>
42048              <name>MUX_FW_P1_VPLUS</name>
42049              <description>Firmware control: 0=open, 1=close switch between pin P1 and vplus signal. Write with '1' to set bit.</description>
42050              <bitRange>[1:1]</bitRange>
42051              <access>read-write</access>
42052            </field>
42053            <field>
42054              <name>MUX_FW_P2_VPLUS</name>
42055              <description>Firmware control: 0=open, 1=close switch between pin P2 and vplus signal. Write with '1' to set bit.</description>
42056              <bitRange>[2:2]</bitRange>
42057              <access>read-write</access>
42058            </field>
42059            <field>
42060              <name>MUX_FW_P3_VPLUS</name>
42061              <description>Firmware control: 0=open, 1=close switch between pin P3 and vplus signal. Write with '1' to set bit.</description>
42062              <bitRange>[3:3]</bitRange>
42063              <access>read-write</access>
42064            </field>
42065            <field>
42066              <name>MUX_FW_P4_VPLUS</name>
42067              <description>Firmware control: 0=open, 1=close switch between pin P4 and vplus signal. Write with '1' to set bit.</description>
42068              <bitRange>[4:4]</bitRange>
42069              <access>read-write</access>
42070            </field>
42071            <field>
42072              <name>MUX_FW_P5_VPLUS</name>
42073              <description>Firmware control: 0=open, 1=close switch between pin P5 and vplus signal. Write with '1' to set bit.</description>
42074              <bitRange>[5:5]</bitRange>
42075              <access>read-write</access>
42076            </field>
42077            <field>
42078              <name>MUX_FW_P6_VPLUS</name>
42079              <description>Firmware control: 0=open, 1=close switch between pin P6 and vplus signal. Write with '1' to set bit.</description>
42080              <bitRange>[6:6]</bitRange>
42081              <access>read-write</access>
42082            </field>
42083            <field>
42084              <name>MUX_FW_P7_VPLUS</name>
42085              <description>Firmware control: 0=open, 1=close switch between pin P7 and vplus signal. Write with '1' to set bit.</description>
42086              <bitRange>[7:7]</bitRange>
42087              <access>read-write</access>
42088            </field>
42089            <field>
42090              <name>MUX_FW_P0_VMINUS</name>
42091              <description>Firmware control: 0=open, 1=close switch between pin P0 and vminus signal. Write with '1' to set bit.</description>
42092              <bitRange>[8:8]</bitRange>
42093              <access>read-write</access>
42094            </field>
42095            <field>
42096              <name>MUX_FW_P1_VMINUS</name>
42097              <description>Firmware control: 0=open, 1=close switch between pin P1 and vminus signal. Write with '1' to set bit.</description>
42098              <bitRange>[9:9]</bitRange>
42099              <access>read-write</access>
42100            </field>
42101            <field>
42102              <name>MUX_FW_P2_VMINUS</name>
42103              <description>Firmware control: 0=open, 1=close switch between pin P2 and vminus signal. Write with '1' to set bit.</description>
42104              <bitRange>[10:10]</bitRange>
42105              <access>read-write</access>
42106            </field>
42107            <field>
42108              <name>MUX_FW_P3_VMINUS</name>
42109              <description>Firmware control: 0=open, 1=close switch between pin P3 and vminus signal. Write with '1' to set bit.</description>
42110              <bitRange>[11:11]</bitRange>
42111              <access>read-write</access>
42112            </field>
42113            <field>
42114              <name>MUX_FW_P4_VMINUS</name>
42115              <description>Firmware control: 0=open, 1=close switch between pin P4 and vminus signal. Write with '1' to set bit.</description>
42116              <bitRange>[12:12]</bitRange>
42117              <access>read-write</access>
42118            </field>
42119            <field>
42120              <name>MUX_FW_P5_VMINUS</name>
42121              <description>Firmware control: 0=open, 1=close switch between pin P5 and vminus signal. Write with '1' to set bit.</description>
42122              <bitRange>[13:13]</bitRange>
42123              <access>read-write</access>
42124            </field>
42125            <field>
42126              <name>MUX_FW_P6_VMINUS</name>
42127              <description>Firmware control: 0=open, 1=close switch between pin P6 and vminus signal. Write with '1' to set bit.</description>
42128              <bitRange>[14:14]</bitRange>
42129              <access>read-write</access>
42130            </field>
42131            <field>
42132              <name>MUX_FW_P7_VMINUS</name>
42133              <description>Firmware control: 0=open, 1=close switch between pin P7 and vminus signal. Write with '1' to set bit.</description>
42134              <bitRange>[15:15]</bitRange>
42135              <access>read-write</access>
42136            </field>
42137            <field>
42138              <name>MUX_FW_VSSA_VMINUS</name>
42139              <description>Firmware control: 0=open, 1=close switch between vssa_kelvin and vminus signal. Write with '1' to set bit.</description>
42140              <bitRange>[16:16]</bitRange>
42141              <access>read-write</access>
42142            </field>
42143            <field>
42144              <name>MUX_FW_TEMP_VPLUS</name>
42145              <description>Firmware control: 0=open, 1=close switch between temperature sensor and vplus signal, also powers on the temperature sensor. Write with '1' to set bit.</description>
42146              <bitRange>[17:17]</bitRange>
42147              <access>read-write</access>
42148            </field>
42149            <field>
42150              <name>MUX_FW_AMUXBUSA_VPLUS</name>
42151              <description>Firmware control: 0=open, 1=close switch between amuxbusa and vplus signal. Write with '1' to set bit.</description>
42152              <bitRange>[18:18]</bitRange>
42153              <access>read-write</access>
42154            </field>
42155            <field>
42156              <name>MUX_FW_AMUXBUSB_VPLUS</name>
42157              <description>Firmware control: 0=open, 1=close switch between amuxbusb and vplus signal. Write with '1' to set bit.</description>
42158              <bitRange>[19:19]</bitRange>
42159              <access>read-write</access>
42160            </field>
42161            <field>
42162              <name>MUX_FW_AMUXBUSA_VMINUS</name>
42163              <description>Firmware control: 0=open, 1=close switch between amuxbusa and vminus signal. Write with '1' to set bit.</description>
42164              <bitRange>[20:20]</bitRange>
42165              <access>read-write</access>
42166            </field>
42167            <field>
42168              <name>MUX_FW_AMUXBUSB_VMINUS</name>
42169              <description>Firmware control: 0=open, 1=close switch between amuxbusb and vminus signal. Write with '1' to set bit.</description>
42170              <bitRange>[21:21]</bitRange>
42171              <access>read-write</access>
42172            </field>
42173            <field>
42174              <name>MUX_FW_SARBUS0_VPLUS</name>
42175              <description>Firmware control: 0=open, 1=close switch between sarbus0 and vplus signal. Write with '1' to set bit.</description>
42176              <bitRange>[22:22]</bitRange>
42177              <access>read-write</access>
42178            </field>
42179            <field>
42180              <name>MUX_FW_SARBUS1_VPLUS</name>
42181              <description>Firmware control: 0=open, 1=close switch between sarbus1 and vplus signal. Write with '1' to set bit.</description>
42182              <bitRange>[23:23]</bitRange>
42183              <access>read-write</access>
42184            </field>
42185            <field>
42186              <name>MUX_FW_SARBUS0_VMINUS</name>
42187              <description>Firmware control: 0=open, 1=close switch between sarbus0 and vminus signal. Write with '1' to set bit.</description>
42188              <bitRange>[24:24]</bitRange>
42189              <access>read-write</access>
42190            </field>
42191            <field>
42192              <name>MUX_FW_SARBUS1_VMINUS</name>
42193              <description>Firmware control: 0=open, 1=close switch between sarbus1 and vminus signal. Write with '1' to set bit.</description>
42194              <bitRange>[25:25]</bitRange>
42195              <access>read-write</access>
42196            </field>
42197            <field>
42198              <name>MUX_FW_P4_COREIO0</name>
42199              <description>Firmware control: 0=open, 1=close switch between P4 and coreio0 signal. Write with '1' to set bit.</description>
42200              <bitRange>[26:26]</bitRange>
42201              <access>read-write</access>
42202            </field>
42203            <field>
42204              <name>MUX_FW_P5_COREIO1</name>
42205              <description>Firmware control: 0=open, 1=close switch between P5 and coreio1 signal. Write with '1' to set bit.</description>
42206              <bitRange>[27:27]</bitRange>
42207              <access>read-write</access>
42208            </field>
42209            <field>
42210              <name>MUX_FW_P6_COREIO2</name>
42211              <description>Firmware control: 0=open, 1=close switch between P6 and coreio2 signal. Write with '1' to set bit.</description>
42212              <bitRange>[28:28]</bitRange>
42213              <access>read-write</access>
42214            </field>
42215            <field>
42216              <name>MUX_FW_P7_COREIO3</name>
42217              <description>Firmware control: 0=open, 1=close switch between P7 and coreio3 signal. Write with '1' to set bit.</description>
42218              <bitRange>[29:29]</bitRange>
42219              <access>read-write</access>
42220            </field>
42221          </fields>
42222        </register>
42223        <register>
42224          <name>MUX_SWITCH_CLEAR0</name>
42225          <description>SARMUX Firmware switch control clear</description>
42226          <addressOffset>0x304</addressOffset>
42227          <size>32</size>
42228          <access>read-write</access>
42229          <resetValue>0x0</resetValue>
42230          <resetMask>0x3FFFFFFF</resetMask>
42231          <fields>
42232            <field>
42233              <name>MUX_FW_P0_VPLUS</name>
42234              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42235              <bitRange>[0:0]</bitRange>
42236              <access>read-write</access>
42237            </field>
42238            <field>
42239              <name>MUX_FW_P1_VPLUS</name>
42240              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42241              <bitRange>[1:1]</bitRange>
42242              <access>read-write</access>
42243            </field>
42244            <field>
42245              <name>MUX_FW_P2_VPLUS</name>
42246              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42247              <bitRange>[2:2]</bitRange>
42248              <access>read-write</access>
42249            </field>
42250            <field>
42251              <name>MUX_FW_P3_VPLUS</name>
42252              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42253              <bitRange>[3:3]</bitRange>
42254              <access>read-write</access>
42255            </field>
42256            <field>
42257              <name>MUX_FW_P4_VPLUS</name>
42258              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42259              <bitRange>[4:4]</bitRange>
42260              <access>read-write</access>
42261            </field>
42262            <field>
42263              <name>MUX_FW_P5_VPLUS</name>
42264              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42265              <bitRange>[5:5]</bitRange>
42266              <access>read-write</access>
42267            </field>
42268            <field>
42269              <name>MUX_FW_P6_VPLUS</name>
42270              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42271              <bitRange>[6:6]</bitRange>
42272              <access>read-write</access>
42273            </field>
42274            <field>
42275              <name>MUX_FW_P7_VPLUS</name>
42276              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42277              <bitRange>[7:7]</bitRange>
42278              <access>read-write</access>
42279            </field>
42280            <field>
42281              <name>MUX_FW_P0_VMINUS</name>
42282              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42283              <bitRange>[8:8]</bitRange>
42284              <access>read-write</access>
42285            </field>
42286            <field>
42287              <name>MUX_FW_P1_VMINUS</name>
42288              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42289              <bitRange>[9:9]</bitRange>
42290              <access>read-write</access>
42291            </field>
42292            <field>
42293              <name>MUX_FW_P2_VMINUS</name>
42294              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42295              <bitRange>[10:10]</bitRange>
42296              <access>read-write</access>
42297            </field>
42298            <field>
42299              <name>MUX_FW_P3_VMINUS</name>
42300              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42301              <bitRange>[11:11]</bitRange>
42302              <access>read-write</access>
42303            </field>
42304            <field>
42305              <name>MUX_FW_P4_VMINUS</name>
42306              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42307              <bitRange>[12:12]</bitRange>
42308              <access>read-write</access>
42309            </field>
42310            <field>
42311              <name>MUX_FW_P5_VMINUS</name>
42312              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42313              <bitRange>[13:13]</bitRange>
42314              <access>read-write</access>
42315            </field>
42316            <field>
42317              <name>MUX_FW_P6_VMINUS</name>
42318              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42319              <bitRange>[14:14]</bitRange>
42320              <access>read-write</access>
42321            </field>
42322            <field>
42323              <name>MUX_FW_P7_VMINUS</name>
42324              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42325              <bitRange>[15:15]</bitRange>
42326              <access>read-write</access>
42327            </field>
42328            <field>
42329              <name>MUX_FW_VSSA_VMINUS</name>
42330              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42331              <bitRange>[16:16]</bitRange>
42332              <access>read-write</access>
42333            </field>
42334            <field>
42335              <name>MUX_FW_TEMP_VPLUS</name>
42336              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42337              <bitRange>[17:17]</bitRange>
42338              <access>read-write</access>
42339            </field>
42340            <field>
42341              <name>MUX_FW_AMUXBUSA_VPLUS</name>
42342              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42343              <bitRange>[18:18]</bitRange>
42344              <access>read-write</access>
42345            </field>
42346            <field>
42347              <name>MUX_FW_AMUXBUSB_VPLUS</name>
42348              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42349              <bitRange>[19:19]</bitRange>
42350              <access>read-write</access>
42351            </field>
42352            <field>
42353              <name>MUX_FW_AMUXBUSA_VMINUS</name>
42354              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42355              <bitRange>[20:20]</bitRange>
42356              <access>read-write</access>
42357            </field>
42358            <field>
42359              <name>MUX_FW_AMUXBUSB_VMINUS</name>
42360              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42361              <bitRange>[21:21]</bitRange>
42362              <access>read-write</access>
42363            </field>
42364            <field>
42365              <name>MUX_FW_SARBUS0_VPLUS</name>
42366              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42367              <bitRange>[22:22]</bitRange>
42368              <access>read-write</access>
42369            </field>
42370            <field>
42371              <name>MUX_FW_SARBUS1_VPLUS</name>
42372              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42373              <bitRange>[23:23]</bitRange>
42374              <access>read-write</access>
42375            </field>
42376            <field>
42377              <name>MUX_FW_SARBUS0_VMINUS</name>
42378              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42379              <bitRange>[24:24]</bitRange>
42380              <access>read-write</access>
42381            </field>
42382            <field>
42383              <name>MUX_FW_SARBUS1_VMINUS</name>
42384              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42385              <bitRange>[25:25]</bitRange>
42386              <access>read-write</access>
42387            </field>
42388            <field>
42389              <name>MUX_FW_P4_COREIO0</name>
42390              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42391              <bitRange>[26:26]</bitRange>
42392              <access>read-write</access>
42393            </field>
42394            <field>
42395              <name>MUX_FW_P5_COREIO1</name>
42396              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42397              <bitRange>[27:27]</bitRange>
42398              <access>read-write</access>
42399            </field>
42400            <field>
42401              <name>MUX_FW_P6_COREIO2</name>
42402              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42403              <bitRange>[28:28]</bitRange>
42404              <access>read-write</access>
42405            </field>
42406            <field>
42407              <name>MUX_FW_P7_COREIO3</name>
42408              <description>Write '1' to clear corresponding bit in MUX_SWITCH0</description>
42409              <bitRange>[29:29]</bitRange>
42410              <access>read-write</access>
42411            </field>
42412          </fields>
42413        </register>
42414        <register>
42415          <name>MUX_SWITCH_DS_CTRL</name>
42416          <description>SARMUX switch DSI control</description>
42417          <addressOffset>0x340</addressOffset>
42418          <size>32</size>
42419          <access>read-write</access>
42420          <resetValue>0x0</resetValue>
42421          <resetMask>0xCF00FF</resetMask>
42422          <fields>
42423            <field>
42424              <name>MUX_DS_CTRL_P0</name>
42425              <description>for P0 switches</description>
42426              <bitRange>[0:0]</bitRange>
42427              <access>read-write</access>
42428            </field>
42429            <field>
42430              <name>MUX_DS_CTRL_P1</name>
42431              <description>for P1 switches</description>
42432              <bitRange>[1:1]</bitRange>
42433              <access>read-write</access>
42434            </field>
42435            <field>
42436              <name>MUX_DS_CTRL_P2</name>
42437              <description>for P2 switches</description>
42438              <bitRange>[2:2]</bitRange>
42439              <access>read-write</access>
42440            </field>
42441            <field>
42442              <name>MUX_DS_CTRL_P3</name>
42443              <description>for P3 switches</description>
42444              <bitRange>[3:3]</bitRange>
42445              <access>read-write</access>
42446            </field>
42447            <field>
42448              <name>MUX_DS_CTRL_P4</name>
42449              <description>for P4 switches</description>
42450              <bitRange>[4:4]</bitRange>
42451              <access>read-write</access>
42452            </field>
42453            <field>
42454              <name>MUX_DS_CTRL_P5</name>
42455              <description>for P5 switches</description>
42456              <bitRange>[5:5]</bitRange>
42457              <access>read-write</access>
42458            </field>
42459            <field>
42460              <name>MUX_DS_CTRL_P6</name>
42461              <description>for P6 switches</description>
42462              <bitRange>[6:6]</bitRange>
42463              <access>read-write</access>
42464            </field>
42465            <field>
42466              <name>MUX_DS_CTRL_P7</name>
42467              <description>for P7 switches</description>
42468              <bitRange>[7:7]</bitRange>
42469              <access>read-write</access>
42470            </field>
42471            <field>
42472              <name>MUX_DS_CTRL_VSSA</name>
42473              <description>for vssa switch</description>
42474              <bitRange>[16:16]</bitRange>
42475              <access>read-write</access>
42476            </field>
42477            <field>
42478              <name>MUX_DS_CTRL_TEMP</name>
42479              <description>for temp switch</description>
42480              <bitRange>[17:17]</bitRange>
42481              <access>read-write</access>
42482            </field>
42483            <field>
42484              <name>MUX_DS_CTRL_AMUXBUSA</name>
42485              <description>for amuxbusa switch</description>
42486              <bitRange>[18:18]</bitRange>
42487              <access>read-write</access>
42488            </field>
42489            <field>
42490              <name>MUX_DS_CTRL_AMUXBUSB</name>
42491              <description>for amuxbusb switches</description>
42492              <bitRange>[19:19]</bitRange>
42493              <access>read-write</access>
42494            </field>
42495            <field>
42496              <name>MUX_DS_CTRL_SARBUS0</name>
42497              <description>for sarbus0 switch</description>
42498              <bitRange>[22:22]</bitRange>
42499              <access>read-write</access>
42500            </field>
42501            <field>
42502              <name>MUX_DS_CTRL_SARBUS1</name>
42503              <description>for sarbus1 switch</description>
42504              <bitRange>[23:23]</bitRange>
42505              <access>read-write</access>
42506            </field>
42507          </fields>
42508        </register>
42509        <register>
42510          <name>MUX_SWITCH_SQ_CTRL</name>
42511          <description>SARMUX switch Sar Sequencer control</description>
42512          <addressOffset>0x344</addressOffset>
42513          <size>32</size>
42514          <access>read-write</access>
42515          <resetValue>0x0</resetValue>
42516          <resetMask>0xCF00FF</resetMask>
42517          <fields>
42518            <field>
42519              <name>MUX_SQ_CTRL_P0</name>
42520              <description>for P0 switches</description>
42521              <bitRange>[0:0]</bitRange>
42522              <access>read-write</access>
42523            </field>
42524            <field>
42525              <name>MUX_SQ_CTRL_P1</name>
42526              <description>for P1 switches</description>
42527              <bitRange>[1:1]</bitRange>
42528              <access>read-write</access>
42529            </field>
42530            <field>
42531              <name>MUX_SQ_CTRL_P2</name>
42532              <description>for P2 switches</description>
42533              <bitRange>[2:2]</bitRange>
42534              <access>read-write</access>
42535            </field>
42536            <field>
42537              <name>MUX_SQ_CTRL_P3</name>
42538              <description>for P3 switches</description>
42539              <bitRange>[3:3]</bitRange>
42540              <access>read-write</access>
42541            </field>
42542            <field>
42543              <name>MUX_SQ_CTRL_P4</name>
42544              <description>for P4 switches</description>
42545              <bitRange>[4:4]</bitRange>
42546              <access>read-write</access>
42547            </field>
42548            <field>
42549              <name>MUX_SQ_CTRL_P5</name>
42550              <description>for P5 switches</description>
42551              <bitRange>[5:5]</bitRange>
42552              <access>read-write</access>
42553            </field>
42554            <field>
42555              <name>MUX_SQ_CTRL_P6</name>
42556              <description>for P6 switches</description>
42557              <bitRange>[6:6]</bitRange>
42558              <access>read-write</access>
42559            </field>
42560            <field>
42561              <name>MUX_SQ_CTRL_P7</name>
42562              <description>for P7 switches</description>
42563              <bitRange>[7:7]</bitRange>
42564              <access>read-write</access>
42565            </field>
42566            <field>
42567              <name>MUX_SQ_CTRL_VSSA</name>
42568              <description>for vssa switch</description>
42569              <bitRange>[16:16]</bitRange>
42570              <access>read-write</access>
42571            </field>
42572            <field>
42573              <name>MUX_SQ_CTRL_TEMP</name>
42574              <description>for temp switch</description>
42575              <bitRange>[17:17]</bitRange>
42576              <access>read-write</access>
42577            </field>
42578            <field>
42579              <name>MUX_SQ_CTRL_AMUXBUSA</name>
42580              <description>for amuxbusa switch</description>
42581              <bitRange>[18:18]</bitRange>
42582              <access>read-write</access>
42583            </field>
42584            <field>
42585              <name>MUX_SQ_CTRL_AMUXBUSB</name>
42586              <description>for amuxbusb switches</description>
42587              <bitRange>[19:19]</bitRange>
42588              <access>read-write</access>
42589            </field>
42590            <field>
42591              <name>MUX_SQ_CTRL_SARBUS0</name>
42592              <description>for sarbus0 switch</description>
42593              <bitRange>[22:22]</bitRange>
42594              <access>read-write</access>
42595            </field>
42596            <field>
42597              <name>MUX_SQ_CTRL_SARBUS1</name>
42598              <description>for sarbus1 switch</description>
42599              <bitRange>[23:23]</bitRange>
42600              <access>read-write</access>
42601            </field>
42602          </fields>
42603        </register>
42604        <register>
42605          <name>MUX_SWITCH_STATUS</name>
42606          <description>SARMUX switch status</description>
42607          <addressOffset>0x348</addressOffset>
42608          <size>32</size>
42609          <access>read-only</access>
42610          <resetValue>0x0</resetValue>
42611          <resetMask>0x3FFFFFF</resetMask>
42612          <fields>
42613            <field>
42614              <name>MUX_FW_P0_VPLUS</name>
42615              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42616              <bitRange>[0:0]</bitRange>
42617              <access>read-only</access>
42618            </field>
42619            <field>
42620              <name>MUX_FW_P1_VPLUS</name>
42621              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42622              <bitRange>[1:1]</bitRange>
42623              <access>read-only</access>
42624            </field>
42625            <field>
42626              <name>MUX_FW_P2_VPLUS</name>
42627              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42628              <bitRange>[2:2]</bitRange>
42629              <access>read-only</access>
42630            </field>
42631            <field>
42632              <name>MUX_FW_P3_VPLUS</name>
42633              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42634              <bitRange>[3:3]</bitRange>
42635              <access>read-only</access>
42636            </field>
42637            <field>
42638              <name>MUX_FW_P4_VPLUS</name>
42639              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42640              <bitRange>[4:4]</bitRange>
42641              <access>read-only</access>
42642            </field>
42643            <field>
42644              <name>MUX_FW_P5_VPLUS</name>
42645              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42646              <bitRange>[5:5]</bitRange>
42647              <access>read-only</access>
42648            </field>
42649            <field>
42650              <name>MUX_FW_P6_VPLUS</name>
42651              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42652              <bitRange>[6:6]</bitRange>
42653              <access>read-only</access>
42654            </field>
42655            <field>
42656              <name>MUX_FW_P7_VPLUS</name>
42657              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42658              <bitRange>[7:7]</bitRange>
42659              <access>read-only</access>
42660            </field>
42661            <field>
42662              <name>MUX_FW_P0_VMINUS</name>
42663              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42664              <bitRange>[8:8]</bitRange>
42665              <access>read-only</access>
42666            </field>
42667            <field>
42668              <name>MUX_FW_P1_VMINUS</name>
42669              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42670              <bitRange>[9:9]</bitRange>
42671              <access>read-only</access>
42672            </field>
42673            <field>
42674              <name>MUX_FW_P2_VMINUS</name>
42675              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42676              <bitRange>[10:10]</bitRange>
42677              <access>read-only</access>
42678            </field>
42679            <field>
42680              <name>MUX_FW_P3_VMINUS</name>
42681              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42682              <bitRange>[11:11]</bitRange>
42683              <access>read-only</access>
42684            </field>
42685            <field>
42686              <name>MUX_FW_P4_VMINUS</name>
42687              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42688              <bitRange>[12:12]</bitRange>
42689              <access>read-only</access>
42690            </field>
42691            <field>
42692              <name>MUX_FW_P5_VMINUS</name>
42693              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42694              <bitRange>[13:13]</bitRange>
42695              <access>read-only</access>
42696            </field>
42697            <field>
42698              <name>MUX_FW_P6_VMINUS</name>
42699              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42700              <bitRange>[14:14]</bitRange>
42701              <access>read-only</access>
42702            </field>
42703            <field>
42704              <name>MUX_FW_P7_VMINUS</name>
42705              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42706              <bitRange>[15:15]</bitRange>
42707              <access>read-only</access>
42708            </field>
42709            <field>
42710              <name>MUX_FW_VSSA_VMINUS</name>
42711              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42712              <bitRange>[16:16]</bitRange>
42713              <access>read-only</access>
42714            </field>
42715            <field>
42716              <name>MUX_FW_TEMP_VPLUS</name>
42717              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42718              <bitRange>[17:17]</bitRange>
42719              <access>read-only</access>
42720            </field>
42721            <field>
42722              <name>MUX_FW_AMUXBUSA_VPLUS</name>
42723              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42724              <bitRange>[18:18]</bitRange>
42725              <access>read-only</access>
42726            </field>
42727            <field>
42728              <name>MUX_FW_AMUXBUSB_VPLUS</name>
42729              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42730              <bitRange>[19:19]</bitRange>
42731              <access>read-only</access>
42732            </field>
42733            <field>
42734              <name>MUX_FW_AMUXBUSA_VMINUS</name>
42735              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42736              <bitRange>[20:20]</bitRange>
42737              <access>read-only</access>
42738            </field>
42739            <field>
42740              <name>MUX_FW_AMUXBUSB_VMINUS</name>
42741              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42742              <bitRange>[21:21]</bitRange>
42743              <access>read-only</access>
42744            </field>
42745            <field>
42746              <name>MUX_FW_SARBUS0_VPLUS</name>
42747              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42748              <bitRange>[22:22]</bitRange>
42749              <access>read-only</access>
42750            </field>
42751            <field>
42752              <name>MUX_FW_SARBUS1_VPLUS</name>
42753              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42754              <bitRange>[23:23]</bitRange>
42755              <access>read-only</access>
42756            </field>
42757            <field>
42758              <name>MUX_FW_SARBUS0_VMINUS</name>
42759              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42760              <bitRange>[24:24]</bitRange>
42761              <access>read-only</access>
42762            </field>
42763            <field>
42764              <name>MUX_FW_SARBUS1_VMINUS</name>
42765              <description>switch status of corresponding bit in MUX_SWITCH0</description>
42766              <bitRange>[25:25]</bitRange>
42767              <access>read-only</access>
42768            </field>
42769          </fields>
42770        </register>
42771        <register>
42772          <name>ANA_TRIM0</name>
42773          <description>Analog trim register.</description>
42774          <addressOffset>0xF00</addressOffset>
42775          <size>32</size>
42776          <access>read-write</access>
42777          <resetValue>0x0</resetValue>
42778          <resetMask>0x3F</resetMask>
42779          <fields>
42780            <field>
42781              <name>CAP_TRIM</name>
42782              <description>Attenuation cap trimming</description>
42783              <bitRange>[4:0]</bitRange>
42784              <access>read-write</access>
42785            </field>
42786            <field>
42787              <name>TRIMUNIT</name>
42788              <description>Attenuation cap trimming</description>
42789              <bitRange>[5:5]</bitRange>
42790              <access>read-write</access>
42791            </field>
42792          </fields>
42793        </register>
42794        <register>
42795          <name>ANA_TRIM1</name>
42796          <description>Analog trim register.</description>
42797          <addressOffset>0xF04</addressOffset>
42798          <size>32</size>
42799          <access>read-write</access>
42800          <resetValue>0x0</resetValue>
42801          <resetMask>0x3F</resetMask>
42802          <fields>
42803            <field>
42804              <name>SAR_REF_BUF_TRIM</name>
42805              <description>SAR Reference buffer trim</description>
42806              <bitRange>[5:0]</bitRange>
42807              <access>read-write</access>
42808            </field>
42809          </fields>
42810        </register>
42811      </registers>
42812    </peripheral>
42813    <peripheral>
42814      <name>PASS</name>
42815      <description>PASS top-level MMIO (DSABv2, INTR)</description>
42816      <baseAddress>0x409F0000</baseAddress>
42817      <addressBlock>
42818        <offset>0</offset>
42819        <size>65536</size>
42820        <usage>registers</usage>
42821      </addressBlock>
42822      <registers>
42823        <register>
42824          <name>INTR_CAUSE</name>
42825          <description>Interrupt cause register</description>
42826          <addressOffset>0x0</addressOffset>
42827          <size>32</size>
42828          <access>read-only</access>
42829          <resetValue>0x0</resetValue>
42830          <resetMask>0xFF</resetMask>
42831          <fields>
42832            <field>
42833              <name>CTB0_INT</name>
42834              <description>CTB0 interrupt pending</description>
42835              <bitRange>[0:0]</bitRange>
42836              <access>read-only</access>
42837            </field>
42838            <field>
42839              <name>CTB1_INT</name>
42840              <description>CTB1 interrupt pending</description>
42841              <bitRange>[1:1]</bitRange>
42842              <access>read-only</access>
42843            </field>
42844            <field>
42845              <name>CTB2_INT</name>
42846              <description>CTB2 interrupt pending</description>
42847              <bitRange>[2:2]</bitRange>
42848              <access>read-only</access>
42849            </field>
42850            <field>
42851              <name>CTB3_INT</name>
42852              <description>CTB3 interrupt pending</description>
42853              <bitRange>[3:3]</bitRange>
42854              <access>read-only</access>
42855            </field>
42856            <field>
42857              <name>CTDAC0_INT</name>
42858              <description>CTDAC0 interrupt pending</description>
42859              <bitRange>[4:4]</bitRange>
42860              <access>read-only</access>
42861            </field>
42862            <field>
42863              <name>CTDAC1_INT</name>
42864              <description>CTDAC1 interrupt pending</description>
42865              <bitRange>[5:5]</bitRange>
42866              <access>read-only</access>
42867            </field>
42868            <field>
42869              <name>CTDAC2_INT</name>
42870              <description>CTDAC2 interrupt pending</description>
42871              <bitRange>[6:6]</bitRange>
42872              <access>read-only</access>
42873            </field>
42874            <field>
42875              <name>CTDAC3_INT</name>
42876              <description>CTDAC3 interrupt pending</description>
42877              <bitRange>[7:7]</bitRange>
42878              <access>read-only</access>
42879            </field>
42880          </fields>
42881        </register>
42882        <cluster>
42883          <name>AREF</name>
42884          <description>AREF configuration</description>
42885          <addressOffset>0x00000E00</addressOffset>
42886          <register>
42887            <name>AREF_CTRL</name>
42888            <description>global AREF control</description>
42889            <addressOffset>0x0</addressOffset>
42890            <size>32</size>
42891            <access>read-write</access>
42892            <resetValue>0x0</resetValue>
42893            <resetMask>0xF039FFFD</resetMask>
42894            <fields>
42895              <field>
42896                <name>AREF_MODE</name>
42897                <description>Control bit to trade off AREF settling and noise performance</description>
42898                <bitRange>[0:0]</bitRange>
42899                <access>read-write</access>
42900                <enumeratedValues>
42901                  <enumeratedValue>
42902                    <name>NORMAL</name>
42903                    <description>Nominal noise normal startup mode (meets normal mode settling and noise specifications)</description>
42904                    <value>0</value>
42905                  </enumeratedValue>
42906                  <enumeratedValue>
42907                    <name>FAST_START</name>
42908                    <description>High noise fast startup mode (meets fast mode settling and noise specifications)</description>
42909                    <value>1</value>
42910                  </enumeratedValue>
42911                </enumeratedValues>
42912              </field>
42913              <field>
42914                <name>AREF_BIAS_SCALE</name>
42915                <description>BIAS Current Control for all AREF Amplifiers.  (These are risk mitigation bits that should not be touched by the customer:  the impact on IDDA/noise/startup still needs to be characterized)
429160: 125nA (reduced bias: reduction in total AREF IDDA, higher noise and longer startup times)
429171: 250nA ('default' setting to meet bandgap performance (noise/startup) and IDDA specifications)
429182: 375nA (increased bias: increase in total AREF IDDA, lower noise and shorter startup times)
429193: 500nA (further increased bias: increase in total AREF IDDA, lower noise and shorter startup times)</description>
42920                <bitRange>[3:2]</bitRange>
42921                <access>read-write</access>
42922              </field>
42923              <field>
42924                <name>AREF_RMB</name>
42925                <description>AREF control signals (RMB).
42926
42927Bit 0: Manual VBG startup circuit enable
42928         0: normal VBG startup circuit operation
42929         1: VBG startup circuit is forced 'always on'
42930
42931Bit 1: Manual disable of IPTAT2 DAC
42932         0: normal IPTAT2 DAC operation
42933         1: PTAT2 DAC is disabled while VBG startup is active
42934
42935Bit 2: Manual enable of VBG offset correction DAC
42936         0: normal VBG offset correction DAC operation
42937         1: VBG offset correction DAC is enabled while VBG startup is active</description>
42938                <bitRange>[6:4]</bitRange>
42939                <access>read-write</access>
42940              </field>
42941              <field>
42942                <name>CTB_IPTAT_SCALE</name>
42943                <description>CTB IPTAT current scaler.  This bit must be set in order to operate the CTB amplifiers in the lowest power mode.  This bit is chip-wide (controls all CTB amplifiers).
429440: 1uA
429451: 100nA</description>
42946                <bitRange>[7:7]</bitRange>
42947                <access>read-write</access>
42948              </field>
42949              <field>
42950                <name>CTB_IPTAT_REDIRECT</name>
42951                <description>Re-direct the CTB IPTAT output current. This can be used to reduce amplifier bias glitches during power mode transitions (for PSoC4A/B DSAB backwards compatibility).
429520: Opamp&lt;n&gt;.IPTAT = AREF.IPTAT and Opamp&lt;n&gt;.IZTAT= AREF.IZTAT
429531: Opamp&lt;n&gt;.IPTAT = HiZ and Opamp&lt;n&gt;.IZTAT= AREF.IPTAT
42954
42955*Note that in Deep Sleep, the AREF IZTAT and/or IPTAT currents can be disabled and therefore the corresponding Opamp&lt;n&gt;.IZTAT/IPTAT will be HiZ.</description>
42956                <bitRange>[15:8]</bitRange>
42957                <access>read-write</access>
42958              </field>
42959              <field>
42960                <name>IZTAT_SEL</name>
42961                <description>iztat current select control</description>
42962                <bitRange>[16:16]</bitRange>
42963                <access>read-write</access>
42964                <enumeratedValues>
42965                  <enumeratedValue>
42966                    <name>SRSS</name>
42967                    <description>Use 250nA IZTAT from SRSS</description>
42968                    <value>0</value>
42969                  </enumeratedValue>
42970                  <enumeratedValue>
42971                    <name>LOCAL</name>
42972                    <description>Use locally generated 250nA</description>
42973                    <value>1</value>
42974                  </enumeratedValue>
42975                </enumeratedValues>
42976              </field>
42977              <field>
42978                <name>CLOCK_PUMP_PERI_SEL</name>
42979                <description>CTBm charge pump clock source select. This field has nothing to do with the AREF.
429800: Use the dedicated pump clock from SRSS (default)
429811: Use one of the CLK_PERI dividers</description>
42982                <bitRange>[19:19]</bitRange>
42983                <access>read-write</access>
42984              </field>
42985              <field>
42986                <name>VREF_SEL</name>
42987                <description>bandgap voltage select control</description>
42988                <bitRange>[21:20]</bitRange>
42989                <access>read-write</access>
42990                <enumeratedValues>
42991                  <enumeratedValue>
42992                    <name>SRSS</name>
42993                    <description>Use 0.8V Vref from SRSS</description>
42994                    <value>0</value>
42995                  </enumeratedValue>
42996                  <enumeratedValue>
42997                    <name>LOCAL</name>
42998                    <description>Use locally generated Vref</description>
42999                    <value>1</value>
43000                  </enumeratedValue>
43001                  <enumeratedValue>
43002                    <name>EXTERNAL</name>
43003                    <description>Use externally supplied Vref (aref_ext_vref)</description>
43004                    <value>2</value>
43005                  </enumeratedValue>
43006                </enumeratedValues>
43007              </field>
43008              <field>
43009                <name>DEEPSLEEP_MODE</name>
43010                <description>AREF DeepSleep Operation Modes (only applies if DEEPSLEEP_ON = 1)</description>
43011                <bitRange>[29:28]</bitRange>
43012                <access>read-write</access>
43013                <enumeratedValues>
43014                  <enumeratedValue>
43015                    <name>OFF</name>
43016                    <description>All blocks 'OFF' in DeepSleep</description>
43017                    <value>0</value>
43018                  </enumeratedValue>
43019                  <enumeratedValue>
43020                    <name>IPTAT</name>
43021                    <description>IPTAT bias generator 'ON' in DeepSleep (used for fast AREF wakeup only: IPTAT outputs not available)</description>
43022                    <value>1</value>
43023                  </enumeratedValue>
43024                  <enumeratedValue>
43025                    <name>IPTAT_IZTAT</name>
43026                    <description>IPTAT bias generator and outputs 'ON' in DeepSleep (used for biasing the CTBm with a PTAT current only in deep sleep)
43027
43028*Note that this mode also requires that the CTB_IPTAT_REDIRECT be set if the CTBm opamp is to operate in DeepSleep</description>
43029                    <value>2</value>
43030                  </enumeratedValue>
43031                  <enumeratedValue>
43032                    <name>IPTAT_IZTAT_VREF</name>
43033                    <description>IPTAT, VREF, and IZTAT generators 'ON' in DeepSleep. This mode provides identical AREF functionality in DeepSleep as in the Active mode.</description>
43034                    <value>3</value>
43035                  </enumeratedValue>
43036                </enumeratedValues>
43037              </field>
43038              <field>
43039                <name>DEEPSLEEP_ON</name>
43040                <description>- 0: AREF IP disabled/off during DeepSleep power mode
43041- 1: AREF IP remains enabled during DeepSleep power mode (if ENABLED=1)</description>
43042                <bitRange>[30:30]</bitRange>
43043                <access>read-write</access>
43044              </field>
43045              <field>
43046                <name>ENABLED</name>
43047                <description>Disable AREF</description>
43048                <bitRange>[31:31]</bitRange>
43049                <access>read-write</access>
43050              </field>
43051            </fields>
43052          </register>
43053        </cluster>
43054        <register>
43055          <name>VREF_TRIM0</name>
43056          <description>VREF Trim bits</description>
43057          <addressOffset>0xF00</addressOffset>
43058          <size>32</size>
43059          <access>read-write</access>
43060          <resetValue>0x0</resetValue>
43061          <resetMask>0xFF</resetMask>
43062          <fields>
43063            <field>
43064              <name>VREF_ABS_TRIM</name>
43065              <description>N/A</description>
43066              <bitRange>[7:0]</bitRange>
43067              <access>read-write</access>
43068            </field>
43069          </fields>
43070        </register>
43071        <register>
43072          <name>VREF_TRIM1</name>
43073          <description>VREF Trim bits</description>
43074          <addressOffset>0xF04</addressOffset>
43075          <size>32</size>
43076          <access>read-write</access>
43077          <resetValue>0x0</resetValue>
43078          <resetMask>0xFF</resetMask>
43079          <fields>
43080            <field>
43081              <name>VREF_TEMPCO_TRIM</name>
43082              <description>N/A</description>
43083              <bitRange>[7:0]</bitRange>
43084              <access>read-write</access>
43085            </field>
43086          </fields>
43087        </register>
43088        <register>
43089          <name>VREF_TRIM2</name>
43090          <description>VREF Trim bits</description>
43091          <addressOffset>0xF08</addressOffset>
43092          <size>32</size>
43093          <access>read-write</access>
43094          <resetValue>0x0</resetValue>
43095          <resetMask>0xFF</resetMask>
43096          <fields>
43097            <field>
43098              <name>VREF_CURV_TRIM</name>
43099              <description>N/A</description>
43100              <bitRange>[7:0]</bitRange>
43101              <access>read-write</access>
43102            </field>
43103          </fields>
43104        </register>
43105        <register>
43106          <name>VREF_TRIM3</name>
43107          <description>VREF Trim bits</description>
43108          <addressOffset>0xF0C</addressOffset>
43109          <size>32</size>
43110          <access>read-write</access>
43111          <resetValue>0x0</resetValue>
43112          <resetMask>0xF</resetMask>
43113          <fields>
43114            <field>
43115              <name>VREF_ATTEN_TRIM</name>
43116              <description>Obsolete</description>
43117              <bitRange>[3:0]</bitRange>
43118              <access>read-write</access>
43119            </field>
43120          </fields>
43121        </register>
43122        <register>
43123          <name>IZTAT_TRIM0</name>
43124          <description>IZTAT Trim bits</description>
43125          <addressOffset>0xF10</addressOffset>
43126          <size>32</size>
43127          <access>read-write</access>
43128          <resetValue>0x0</resetValue>
43129          <resetMask>0xFF</resetMask>
43130          <fields>
43131            <field>
43132              <name>IZTAT_ABS_TRIM</name>
43133              <description>N/A</description>
43134              <bitRange>[7:0]</bitRange>
43135              <access>read-write</access>
43136            </field>
43137          </fields>
43138        </register>
43139        <register>
43140          <name>IZTAT_TRIM1</name>
43141          <description>IZTAT Trim bits</description>
43142          <addressOffset>0xF14</addressOffset>
43143          <size>32</size>
43144          <access>read-write</access>
43145          <resetValue>0x0</resetValue>
43146          <resetMask>0xFF</resetMask>
43147          <fields>
43148            <field>
43149              <name>IZTAT_TC_TRIM</name>
43150              <description>IZTAT temperature correction trim (RMB)
431510x00 : No IZTAT temperature correction
431520xFF : Maximum IZTAT temperature correction
43153
43154As this is a Risk Mitigation Register, it should be loaded with 0x08.</description>
43155              <bitRange>[7:0]</bitRange>
43156              <access>read-write</access>
43157            </field>
43158          </fields>
43159        </register>
43160        <register>
43161          <name>IPTAT_TRIM0</name>
43162          <description>IPTAT Trim bits</description>
43163          <addressOffset>0xF18</addressOffset>
43164          <size>32</size>
43165          <access>read-write</access>
43166          <resetValue>0x0</resetValue>
43167          <resetMask>0xFF</resetMask>
43168          <fields>
43169            <field>
43170              <name>IPTAT_CORE_TRIM</name>
43171              <description>IPTAT trim
431720x0 : Minimum IPTAT current (~150nA at room)
431730xF : Maximum IPTAT current (~350nA at room)</description>
43174              <bitRange>[3:0]</bitRange>
43175              <access>read-write</access>
43176            </field>
43177            <field>
43178              <name>IPTAT_CTBM_TRIM</name>
43179              <description>CTMB PTAT Current Trim
431800x0 : Minimum CTMB IPTAT Current (~875nA)
431810xF : Maximum CTMB IPTAT Current (~1.1uA)</description>
43182              <bitRange>[7:4]</bitRange>
43183              <access>read-write</access>
43184            </field>
43185          </fields>
43186        </register>
43187        <register>
43188          <name>ICTAT_TRIM0</name>
43189          <description>ICTAT Trim bits</description>
43190          <addressOffset>0xF1C</addressOffset>
43191          <size>32</size>
43192          <access>read-write</access>
43193          <resetValue>0x0</resetValue>
43194          <resetMask>0xF</resetMask>
43195          <fields>
43196            <field>
43197              <name>ICTAT_TRIM</name>
43198              <description>ICTAT trim
431990x00 : Minimum ICTAT current (~150nA at room)
432000x0F : Maximum ICTAT current (~350nA at room)</description>
43201              <bitRange>[3:0]</bitRange>
43202              <access>read-write</access>
43203            </field>
43204          </fields>
43205        </register>
43206      </registers>
43207    </peripheral>
43208    <peripheral>
43209      <name>PDM0</name>
43210      <description>PDM registers</description>
43211      <headerStructName>PDM</headerStructName>
43212      <baseAddress>0x40A00000</baseAddress>
43213      <addressBlock>
43214        <offset>0</offset>
43215        <size>4096</size>
43216        <usage>registers</usage>
43217      </addressBlock>
43218      <registers>
43219        <register>
43220          <name>CTL</name>
43221          <description>Control</description>
43222          <addressOffset>0x0</addressOffset>
43223          <size>32</size>
43224          <access>read-write</access>
43225          <resetValue>0x20808</resetValue>
43226          <resetMask>0x80030F0F</resetMask>
43227          <fields>
43228            <field>
43229              <name>PGA_R</name>
43230              <description>Right channel PGA gain:
43231+1.5dB/step, -12dB ~ +10.5dB
43232'0': -12 dB
43233'1': -10.5 dB
43234...
43235'15' +10.5 dB
43236(Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_R)</description>
43237              <bitRange>[3:0]</bitRange>
43238              <access>read-write</access>
43239            </field>
43240            <field>
43241              <name>PGA_L</name>
43242              <description>Left channel PGA gain:
43243+1.5dB/step, -12dB ~ +10.5dB
43244'0': -12 dB
43245'1': -10.5 dB
43246...
43247'15': +10.5 dB
43248(Note: These bits are connected to AR36U12.PDM_CORE_CFG.PGA_L)</description>
43249              <bitRange>[11:8]</bitRange>
43250              <access>read-write</access>
43251            </field>
43252            <field>
43253              <name>SOFT_MUTE</name>
43254              <description>Soft mute function to mute the volume smoothly
43255'0': Disabled.
43256'1': Enabled.
43257(Note: This bit is connected to AR36U12.PDM_CORE_CFG.SOFT_MUTE)</description>
43258              <bitRange>[16:16]</bitRange>
43259              <access>read-write</access>
43260            </field>
43261            <field>
43262              <name>STEP_SEL</name>
43263              <description>Set fine gain step for smooth PGA or Soft-Mute attenuation transition.
43264'0': 0.13dB
43265'1': 0.26dB
43266(Note: This bit is connected to AR36U12.PDM_CORE2_CFG.SEL_STEP)</description>
43267              <bitRange>[17:17]</bitRange>
43268              <access>read-write</access>
43269            </field>
43270            <field>
43271              <name>ENABLED</name>
43272              <description>Enables the PDM component:
43273'0': Disabled.
43274'1': Enabled.</description>
43275              <bitRange>[31:31]</bitRange>
43276              <access>read-write</access>
43277            </field>
43278          </fields>
43279        </register>
43280        <register>
43281          <name>CLOCK_CTL</name>
43282          <description>Clock control</description>
43283          <addressOffset>0x10</addressOffset>
43284          <size>32</size>
43285          <access>read-write</access>
43286          <resetValue>0x200310</resetValue>
43287          <resetMask>0x7F0F33</resetMask>
43288          <fields>
43289            <field>
43290              <name>CLK_CLOCK_DIV</name>
43291              <description>PDM CLK (FPDM_CLK) (1st divider):
43292This configures a frequency of PDM CLK. The configured frequency is used to operate PDM core. I.e. the frequency is input to MCLKQ_CLOCK_DIV register.
43293
43294Note: configure a frequency of PDM CLK as lower than or equal 50MHz with this divider.</description>
43295              <bitRange>[1:0]</bitRange>
43296              <access>read-write</access>
43297              <enumeratedValues>
43298                <enumeratedValue>
43299                  <name>DIVBY1</name>
43300                  <description>Divide by 1</description>
43301                  <value>0</value>
43302                </enumeratedValue>
43303                <enumeratedValue>
43304                  <name>DIVBY2</name>
43305                  <description>Divide by 2 (no 50 percent duty cycle)</description>
43306                  <value>1</value>
43307                </enumeratedValue>
43308                <enumeratedValue>
43309                  <name>DIVBY3</name>
43310                  <description>Divide by 3 (no 50 percent duty cycle)</description>
43311                  <value>2</value>
43312                </enumeratedValue>
43313                <enumeratedValue>
43314                  <name>DIVBY4</name>
43315                  <description>Divide by 4 (no 50 percent duty cycle)</description>
43316                  <value>3</value>
43317                </enumeratedValue>
43318              </enumeratedValues>
43319            </field>
43320            <field>
43321              <name>MCLKQ_CLOCK_DIV</name>
43322              <description>MCLKQ divider (2nd divider)
43323
43324(Note: These bits are connected to
43325AR36U12.PDM_CORE2_CFG.DIV_MCLKQ)</description>
43326              <bitRange>[5:4]</bitRange>
43327              <access>read-write</access>
43328              <enumeratedValues>
43329                <enumeratedValue>
43330                  <name>DIVBY1</name>
43331                  <description>Divide by 1</description>
43332                  <value>0</value>
43333                </enumeratedValue>
43334                <enumeratedValue>
43335                  <name>DIVBY2</name>
43336                  <description>Divide by 2 (no 50 percent duty cycle)</description>
43337                  <value>1</value>
43338                </enumeratedValue>
43339                <enumeratedValue>
43340                  <name>DIVBY3</name>
43341                  <description>Divide by 3 (no 50 percent duty cycle)</description>
43342                  <value>2</value>
43343                </enumeratedValue>
43344                <enumeratedValue>
43345                  <name>DIVBY4</name>
43346                  <description>Divide by 4 (no 50 percent duty cycle)</description>
43347                  <value>3</value>
43348                </enumeratedValue>
43349              </enumeratedValues>
43350            </field>
43351            <field>
43352              <name>CKO_CLOCK_DIV</name>
43353              <description>PDM CKO (FPDM_CKO) clock divider (3rd divider):
43354FPDM_CKO = MCLKQ / (CKO_CLOCK_DIV + 1)
43355
43356Note: To configure '0' to this field is prohibited.
43357(Note: PDM_CKO is configured by MCLKQ_CLOCK_DIV,  CLK_CLOCK_DIV and CKO_CLOCK_DIV. )
43358(Note: These bits are connected to
43359AR36U12.PDM_CORE_CFG.MCLKDIV)</description>
43360              <bitRange>[11:8]</bitRange>
43361              <access>read-write</access>
43362            </field>
43363            <field>
43364              <name>SINC_RATE</name>
43365              <description>SINC Decimation Rate. For details, see the data sheet provided by Archband.
43366Oversampling Ratio = Decimation Rate = 2 X SINC_RATE
43367(Note: These bits are connected to AR36U12.PDM_CORE_CFG.SINC_RATE)</description>
43368              <bitRange>[22:16]</bitRange>
43369              <access>read-write</access>
43370            </field>
43371          </fields>
43372        </register>
43373        <register>
43374          <name>MODE_CTL</name>
43375          <description>Mode control</description>
43376          <addressOffset>0x14</addressOffset>
43377          <size>32</size>
43378          <access>read-write</access>
43379          <resetValue>0x1B000103</resetValue>
43380          <resetMask>0x1F070707</resetMask>
43381          <fields>
43382            <field>
43383              <name>PCM_CH_SET</name>
43384              <description>Specifies PCM output channels as mono or stereo:
43385
43386(Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_CHSET)</description>
43387              <bitRange>[1:0]</bitRange>
43388              <access>read-write</access>
43389              <enumeratedValues>
43390                <enumeratedValue>
43391                  <name>DISABLED</name>
43392                  <description>Channel disabled</description>
43393                  <value>0</value>
43394                </enumeratedValue>
43395                <enumeratedValue>
43396                  <name>MONO_L</name>
43397                  <description>Mono left channel enable</description>
43398                  <value>1</value>
43399                </enumeratedValue>
43400                <enumeratedValue>
43401                  <name>MONO_R</name>
43402                  <description>Mono right channel enable</description>
43403                  <value>2</value>
43404                </enumeratedValue>
43405                <enumeratedValue>
43406                  <name>STEREO</name>
43407                  <description>Stereo channel enable</description>
43408                  <value>3</value>
43409                </enumeratedValue>
43410              </enumeratedValues>
43411            </field>
43412            <field>
43413              <name>SWAP_LR</name>
43414              <description>Input data L/R channel swap:
43415'1': Right/Left channel recording swap
43416'0': No Swap
43417(Note: This bit is connected to AR36U12.PDM_CORE_CFG.LRSWAP)</description>
43418              <bitRange>[2:2]</bitRange>
43419              <access>read-write</access>
43420            </field>
43421            <field>
43422              <name>S_CYCLES</name>
43423              <description>Set time step for gain change during PGA or soft mute operation in
43424number of 1/a sampling rate.
43425(Note: These bits are connected to AR36U12.PDM_CORE_CFG.S_CYCLES)</description>
43426              <bitRange>[10:8]</bitRange>
43427              <access>read-write</access>
43428              <enumeratedValues>
43429                <enumeratedValue>
43430                  <name>STEP_NUM64</name>
43431                  <description>64steps</description>
43432                  <value>0</value>
43433                </enumeratedValue>
43434                <enumeratedValue>
43435                  <name>STEP_NUM96</name>
43436                  <description>96steps</description>
43437                  <value>1</value>
43438                </enumeratedValue>
43439                <enumeratedValue>
43440                  <name>STEP_NUM128</name>
43441                  <description>128steps</description>
43442                  <value>2</value>
43443                </enumeratedValue>
43444                <enumeratedValue>
43445                  <name>STEP_NUM160</name>
43446                  <description>160steps</description>
43447                  <value>3</value>
43448                </enumeratedValue>
43449                <enumeratedValue>
43450                  <name>STEP_NUM192</name>
43451                  <description>192steps</description>
43452                  <value>4</value>
43453                </enumeratedValue>
43454                <enumeratedValue>
43455                  <name>STEP_NUM256</name>
43456                  <description>256steps</description>
43457                  <value>5</value>
43458                </enumeratedValue>
43459                <enumeratedValue>
43460                  <name>STEP_NUM384</name>
43461                  <description>384steps</description>
43462                  <value>6</value>
43463                </enumeratedValue>
43464                <enumeratedValue>
43465                  <name>STEP_NUM512</name>
43466                  <description>512steps</description>
43467                  <value>7</value>
43468                </enumeratedValue>
43469              </enumeratedValues>
43470            </field>
43471            <field>
43472              <name>CKO_DELAY</name>
43473              <description>Phase difference from the rising edge of internal sampler clock (CLK_IS) to that of PDM_CKO clock:
43474
43475(Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PDMCKO_DLY)</description>
43476              <bitRange>[18:16]</bitRange>
43477              <access>read-write</access>
43478              <enumeratedValues>
43479                <enumeratedValue>
43480                  <name>ADV3</name>
43481                  <description>CLK_IS is 3*PDM_CLK period early</description>
43482                  <value>0</value>
43483                </enumeratedValue>
43484                <enumeratedValue>
43485                  <name>ADV2</name>
43486                  <description>CLK_IS is 2*PDM_CLK period early</description>
43487                  <value>1</value>
43488                </enumeratedValue>
43489                <enumeratedValue>
43490                  <name>ADV1</name>
43491                  <description>CLK_IS is 1*PDM_CLK period early</description>
43492                  <value>2</value>
43493                </enumeratedValue>
43494                <enumeratedValue>
43495                  <name>NO_DELAY</name>
43496                  <description>CLK_IS is the same as PDM_CKO</description>
43497                  <value>3</value>
43498                </enumeratedValue>
43499                <enumeratedValue>
43500                  <name>DLY1</name>
43501                  <description>CLK_IS is 1*PDM_CLK period late</description>
43502                  <value>4</value>
43503                </enumeratedValue>
43504                <enumeratedValue>
43505                  <name>DLY2</name>
43506                  <description>CLK_IS is 2*PDM_CLK period late</description>
43507                  <value>5</value>
43508                </enumeratedValue>
43509                <enumeratedValue>
43510                  <name>DLY3</name>
43511                  <description>CLK_IS is 3*PDM_CLK period late</description>
43512                  <value>6</value>
43513                </enumeratedValue>
43514                <enumeratedValue>
43515                  <name>DLY4</name>
43516                  <description>CLK_IS is 4*PDM_CLK period late</description>
43517                  <value>7</value>
43518                </enumeratedValue>
43519              </enumeratedValues>
43520            </field>
43521            <field>
43522              <name>HPF_GAIN</name>
43523              <description>Adjust high pass filter coefficients.
43524H(Z) = (1 - Z-1 ) / [1 - (1- 2 -HPF_GAIN) Z-1 ]
43525(Note: These bits are connected to AR36U12.PDM_CORE_CFG.HPGAIN)</description>
43526              <bitRange>[27:24]</bitRange>
43527              <access>read-write</access>
43528            </field>
43529            <field>
43530              <name>HPF_EN_N</name>
43531              <description>Enable high pass filter (active low)
43532'1': Disabled.
43533'0': Enabled.
43534(Note: This bit is connected to AR36U12.PDM_CORE_CFG.ADCHPD)</description>
43535              <bitRange>[28:28]</bitRange>
43536              <access>read-write</access>
43537            </field>
43538          </fields>
43539        </register>
43540        <register>
43541          <name>DATA_CTL</name>
43542          <description>Data control</description>
43543          <addressOffset>0x18</addressOffset>
43544          <size>32</size>
43545          <access>read-write</access>
43546          <resetValue>0x0</resetValue>
43547          <resetMask>0x103</resetMask>
43548          <fields>
43549            <field>
43550              <name>WORD_LEN</name>
43551              <description>PCM Word Length in number of bits:
43552
43553(Note: These bits are connected to AR36U12.PDM_CORE2_CFG.PCM_IWL)</description>
43554              <bitRange>[1:0]</bitRange>
43555              <access>read-write</access>
43556              <enumeratedValues>
43557                <enumeratedValue>
43558                  <name>BIT_LEN16</name>
43559                  <description>16-bit</description>
43560                  <value>0</value>
43561                </enumeratedValue>
43562                <enumeratedValue>
43563                  <name>BIT_LEN18</name>
43564                  <description>18-bit</description>
43565                  <value>1</value>
43566                </enumeratedValue>
43567                <enumeratedValue>
43568                  <name>BIT_LEN20</name>
43569                  <description>20-bit</description>
43570                  <value>2</value>
43571                </enumeratedValue>
43572                <enumeratedValue>
43573                  <name>BIT_LEN24</name>
43574                  <description>24-bit</description>
43575                  <value>3</value>
43576                </enumeratedValue>
43577              </enumeratedValues>
43578            </field>
43579            <field>
43580              <name>BIT_EXTENSION</name>
43581              <description>When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set.
43582'0': Extended by '0'
43583'1': Extended by sign bit (if MSB word is '1', then it is extended by '1', if MSB is '0' then it is extended by '0')</description>
43584              <bitRange>[8:8]</bitRange>
43585              <access>read-write</access>
43586            </field>
43587          </fields>
43588        </register>
43589        <register>
43590          <name>CMD</name>
43591          <description>Command</description>
43592          <addressOffset>0x20</addressOffset>
43593          <size>32</size>
43594          <access>read-write</access>
43595          <resetValue>0x0</resetValue>
43596          <resetMask>0x1</resetMask>
43597          <fields>
43598            <field>
43599              <name>STREAM_EN</name>
43600              <description>Enable data streaming flow:
43601'0': Disabled.
43602'1': Enabled.
43603(Note: This bit is connected to AR36U12.PDM_CORE_CFG.PDMA_EN)</description>
43604              <bitRange>[0:0]</bitRange>
43605              <access>read-write</access>
43606            </field>
43607          </fields>
43608        </register>
43609        <register>
43610          <name>TR_CTL</name>
43611          <description>Trigger control</description>
43612          <addressOffset>0x40</addressOffset>
43613          <size>32</size>
43614          <access>read-write</access>
43615          <resetValue>0x0</resetValue>
43616          <resetMask>0x10000</resetMask>
43617          <fields>
43618            <field>
43619              <name>RX_REQ_EN</name>
43620              <description>Trigger output ('tr_pdm_rx_req') enable for requests of DMA transfer
43621'0': Disabled.
43622'1': Enabled.</description>
43623              <bitRange>[16:16]</bitRange>
43624              <access>read-write</access>
43625            </field>
43626          </fields>
43627        </register>
43628        <register>
43629          <name>RX_FIFO_CTL</name>
43630          <description>RX FIFO control</description>
43631          <addressOffset>0x300</addressOffset>
43632          <size>32</size>
43633          <access>read-write</access>
43634          <resetValue>0x0</resetValue>
43635          <resetMask>0x300FF</resetMask>
43636          <fields>
43637            <field>
43638              <name>TRIGGER_LEVEL</name>
43639              <description>Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated.
43640Note: software can configure up to 254 in Mono channel enabled (MODE_CTL.PCM_CH_SET = '1' or '2'), up to 253 in Stereo channel enabled (MODE_CTL.PCM_CH_SET = '3').</description>
43641              <bitRange>[7:0]</bitRange>
43642              <access>read-write</access>
43643            </field>
43644            <field>
43645              <name>CLEAR</name>
43646              <description>When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
43647              <bitRange>[16:16]</bitRange>
43648              <access>read-write</access>
43649            </field>
43650            <field>
43651              <name>FREEZE</name>
43652              <description>When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer.This field is used only for debugging purposes.</description>
43653              <bitRange>[17:17]</bitRange>
43654              <access>read-write</access>
43655            </field>
43656          </fields>
43657        </register>
43658        <register>
43659          <name>RX_FIFO_STATUS</name>
43660          <description>RX FIFO status</description>
43661          <addressOffset>0x304</addressOffset>
43662          <size>32</size>
43663          <access>read-only</access>
43664          <resetValue>0x0</resetValue>
43665          <resetMask>0xFFFF00FF</resetMask>
43666          <fields>
43667            <field>
43668              <name>USED</name>
43669              <description>Number of entries in the RX FIFO. The field value is in the range [0, 255]. When this is zero, the RX FIFO is empty.</description>
43670              <bitRange>[7:0]</bitRange>
43671              <access>read-only</access>
43672            </field>
43673            <field>
43674              <name>RD_PTR</name>
43675              <description>RX FIFO read pointer: RX FIFO location from which a data frame is read by the host.This field is used only for debugging purposes.</description>
43676              <bitRange>[23:16]</bitRange>
43677              <access>read-only</access>
43678            </field>
43679            <field>
43680              <name>WR_PTR</name>
43681              <description>RX FIFO write pointer: RX FIFO location at which a new data frame is written by the hardware.This field is used only for debugging purposes.</description>
43682              <bitRange>[31:24]</bitRange>
43683              <access>read-only</access>
43684            </field>
43685          </fields>
43686        </register>
43687        <register>
43688          <name>RX_FIFO_RD</name>
43689          <description>RX FIFO read</description>
43690          <addressOffset>0x308</addressOffset>
43691          <size>32</size>
43692          <access>read-only</access>
43693          <resetValue>0x0</resetValue>
43694          <resetMask>0xFFFFFFFF</resetMask>
43695          <fields>
43696            <field>
43697              <name>DATA</name>
43698              <description>Data read from the RX FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation.
43699Note: Don't access to this bit while RX_FIFO_CTL.CLEAR is '1'.</description>
43700              <bitRange>[31:0]</bitRange>
43701              <access>read-only</access>
43702            </field>
43703          </fields>
43704        </register>
43705        <register>
43706          <name>RX_FIFO_RD_SILENT</name>
43707          <description>RX FIFO silent read</description>
43708          <addressOffset>0x30C</addressOffset>
43709          <size>32</size>
43710          <access>read-only</access>
43711          <resetValue>0x0</resetValue>
43712          <resetMask>0xFFFFFFFF</resetMask>
43713          <fields>
43714            <field>
43715              <name>DATA</name>
43716              <description>Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes.
43717Note: Don't access to this bit while RX_FIFO_CTL.CLEAR is '1'.</description>
43718              <bitRange>[31:0]</bitRange>
43719              <access>read-only</access>
43720            </field>
43721          </fields>
43722        </register>
43723        <register>
43724          <name>INTR</name>
43725          <description>Interrupt register</description>
43726          <addressOffset>0xF00</addressOffset>
43727          <size>32</size>
43728          <access>read-write</access>
43729          <resetValue>0x0</resetValue>
43730          <resetMask>0x650000</resetMask>
43731          <fields>
43732            <field>
43733              <name>RX_TRIGGER</name>
43734              <description>More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTL.</description>
43735              <bitRange>[16:16]</bitRange>
43736              <access>read-write</access>
43737            </field>
43738            <field>
43739              <name>RX_NOT_EMPTY</name>
43740              <description>RX FIFO is not empty.</description>
43741              <bitRange>[18:18]</bitRange>
43742              <access>read-write</access>
43743            </field>
43744            <field>
43745              <name>RX_OVERFLOW</name>
43746              <description>Attempt to write to a full RX FIFO</description>
43747              <bitRange>[21:21]</bitRange>
43748              <access>read-write</access>
43749            </field>
43750            <field>
43751              <name>RX_UNDERFLOW</name>
43752              <description>Attempt to read from an empty RX FIFO</description>
43753              <bitRange>[22:22]</bitRange>
43754              <access>read-write</access>
43755            </field>
43756          </fields>
43757        </register>
43758        <register>
43759          <name>INTR_SET</name>
43760          <description>Interrupt set register</description>
43761          <addressOffset>0xF04</addressOffset>
43762          <size>32</size>
43763          <access>read-write</access>
43764          <resetValue>0x0</resetValue>
43765          <resetMask>0x650000</resetMask>
43766          <fields>
43767            <field>
43768              <name>RX_TRIGGER</name>
43769              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
43770              <bitRange>[16:16]</bitRange>
43771              <access>read-write</access>
43772            </field>
43773            <field>
43774              <name>RX_NOT_EMPTY</name>
43775              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
43776              <bitRange>[18:18]</bitRange>
43777              <access>read-write</access>
43778            </field>
43779            <field>
43780              <name>RX_OVERFLOW</name>
43781              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
43782              <bitRange>[21:21]</bitRange>
43783              <access>read-write</access>
43784            </field>
43785            <field>
43786              <name>RX_UNDERFLOW</name>
43787              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
43788              <bitRange>[22:22]</bitRange>
43789              <access>read-write</access>
43790            </field>
43791          </fields>
43792        </register>
43793        <register>
43794          <name>INTR_MASK</name>
43795          <description>Interrupt mask register</description>
43796          <addressOffset>0xF08</addressOffset>
43797          <size>32</size>
43798          <access>read-write</access>
43799          <resetValue>0x0</resetValue>
43800          <resetMask>0x650000</resetMask>
43801          <fields>
43802            <field>
43803              <name>RX_TRIGGER</name>
43804              <description>Mask bit for corresponding bit in interrupt request register.</description>
43805              <bitRange>[16:16]</bitRange>
43806              <access>read-write</access>
43807            </field>
43808            <field>
43809              <name>RX_NOT_EMPTY</name>
43810              <description>Mask bit for corresponding bit in interrupt request register.</description>
43811              <bitRange>[18:18]</bitRange>
43812              <access>read-write</access>
43813            </field>
43814            <field>
43815              <name>RX_OVERFLOW</name>
43816              <description>Mask bit for corresponding bit in interrupt request register.</description>
43817              <bitRange>[21:21]</bitRange>
43818              <access>read-write</access>
43819            </field>
43820            <field>
43821              <name>RX_UNDERFLOW</name>
43822              <description>Mask bit for corresponding bit in interrupt request register.</description>
43823              <bitRange>[22:22]</bitRange>
43824              <access>read-write</access>
43825            </field>
43826          </fields>
43827        </register>
43828        <register>
43829          <name>INTR_MASKED</name>
43830          <description>Interrupt masked register</description>
43831          <addressOffset>0xF0C</addressOffset>
43832          <size>32</size>
43833          <access>read-only</access>
43834          <resetValue>0x0</resetValue>
43835          <resetMask>0x650000</resetMask>
43836          <fields>
43837            <field>
43838              <name>RX_TRIGGER</name>
43839              <description>Logical and of corresponding request and mask bits.</description>
43840              <bitRange>[16:16]</bitRange>
43841              <access>read-only</access>
43842            </field>
43843            <field>
43844              <name>RX_NOT_EMPTY</name>
43845              <description>Logical and of corresponding request and mask bits.</description>
43846              <bitRange>[18:18]</bitRange>
43847              <access>read-only</access>
43848            </field>
43849            <field>
43850              <name>RX_OVERFLOW</name>
43851              <description>Logical and of corresponding request and mask bits.</description>
43852              <bitRange>[21:21]</bitRange>
43853              <access>read-only</access>
43854            </field>
43855            <field>
43856              <name>RX_UNDERFLOW</name>
43857              <description>Logical and of corresponding request and mask bits.</description>
43858              <bitRange>[22:22]</bitRange>
43859              <access>read-only</access>
43860            </field>
43861          </fields>
43862        </register>
43863      </registers>
43864    </peripheral>
43865    <peripheral>
43866      <name>I2S0</name>
43867      <description>I2S registers</description>
43868      <headerStructName>I2S</headerStructName>
43869      <baseAddress>0x40A10000</baseAddress>
43870      <addressBlock>
43871        <offset>0</offset>
43872        <size>4096</size>
43873        <usage>registers</usage>
43874      </addressBlock>
43875      <registers>
43876        <register>
43877          <name>CTL</name>
43878          <description>Control</description>
43879          <addressOffset>0x0</addressOffset>
43880          <size>32</size>
43881          <access>read-write</access>
43882          <resetValue>0x0</resetValue>
43883          <resetMask>0xC0000000</resetMask>
43884          <fields>
43885            <field>
43886              <name>TX_ENABLED</name>
43887              <description>Enables the I2S TX component:
43888'0': Disabled.
43889'1': Enabled.</description>
43890              <bitRange>[30:30]</bitRange>
43891              <access>read-write</access>
43892            </field>
43893            <field>
43894              <name>RX_ENABLED</name>
43895              <description>Enables the I2S RX component:
43896'0': Disabled.
43897'1': Enabled.</description>
43898              <bitRange>[31:31]</bitRange>
43899              <access>read-write</access>
43900            </field>
43901          </fields>
43902        </register>
43903        <register>
43904          <name>CLOCK_CTL</name>
43905          <description>Clock control</description>
43906          <addressOffset>0x10</addressOffset>
43907          <size>32</size>
43908          <access>read-write</access>
43909          <resetValue>0x0</resetValue>
43910          <resetMask>0x13F</resetMask>
43911          <fields>
43912            <field>
43913              <name>CLOCK_DIV</name>
43914              <description>Frequency divisor for generating I2S clock frequency.
43915The selected clock with CLOCK_SEL is divided by this.
43916'0': Bypass
43917'1': 2 x
43918'2': 3 x
43919'3': 4 x
43920...
43921'62': 63 x
43922'63': 64 x</description>
43923              <bitRange>[5:0]</bitRange>
43924              <access>read-write</access>
43925            </field>
43926            <field>
43927              <name>CLOCK_SEL</name>
43928              <description>Selects clock to be used by I2S:
43929'0': Internal clock ('clk_audio_i2s')
43930'1': External clock ('clk_i2s_if')</description>
43931              <bitRange>[8:8]</bitRange>
43932              <access>read-write</access>
43933            </field>
43934          </fields>
43935        </register>
43936        <register>
43937          <name>CMD</name>
43938          <description>Command</description>
43939          <addressOffset>0x20</addressOffset>
43940          <size>32</size>
43941          <access>read-write</access>
43942          <resetValue>0x0</resetValue>
43943          <resetMask>0x10101</resetMask>
43944          <fields>
43945            <field>
43946              <name>TX_START</name>
43947              <description>Transmitter enable:
43948'0': Disabled.
43949'1': Enabled.</description>
43950              <bitRange>[0:0]</bitRange>
43951              <access>read-write</access>
43952            </field>
43953            <field>
43954              <name>TX_PAUSE</name>
43955              <description>Pause enable:
43956'0': Disabled (TX FIFO data is sent over I2S).
43957'1': Enabled ('0' data is sent over I2S, instead of TX FIFO data).</description>
43958              <bitRange>[8:8]</bitRange>
43959              <access>read-write</access>
43960            </field>
43961            <field>
43962              <name>RX_START</name>
43963              <description>Receiver enable:
43964'0': Disabled.
43965'1': Enabled.</description>
43966              <bitRange>[16:16]</bitRange>
43967              <access>read-write</access>
43968            </field>
43969          </fields>
43970        </register>
43971        <register>
43972          <name>TR_CTL</name>
43973          <description>Trigger control</description>
43974          <addressOffset>0x40</addressOffset>
43975          <size>32</size>
43976          <access>read-write</access>
43977          <resetValue>0x0</resetValue>
43978          <resetMask>0x10001</resetMask>
43979          <fields>
43980            <field>
43981              <name>TX_REQ_EN</name>
43982              <description>Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission
43983'0': Disabled.
43984'1': Enabled.</description>
43985              <bitRange>[0:0]</bitRange>
43986              <access>read-write</access>
43987            </field>
43988            <field>
43989              <name>RX_REQ_EN</name>
43990              <description>Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception
43991'0': Disabled.
43992'1': Enabled.</description>
43993              <bitRange>[16:16]</bitRange>
43994              <access>read-write</access>
43995            </field>
43996          </fields>
43997        </register>
43998        <register>
43999          <name>TX_CTL</name>
44000          <description>Transmitter control</description>
44001          <addressOffset>0x80</addressOffset>
44002          <size>32</size>
44003          <access>read-write</access>
44004          <resetValue>0x440510</resetValue>
44005          <resetMask>0x37737F8</resetMask>
44006          <fields>
44007            <field>
44008              <name>B_CLOCK_INV</name>
44009              <description>Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode.
44010When set to '1', the serial data will be transmitted 0.5 SCK cycles earlier than when set to '0'.
44011
440121) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK falling edge
440132) TX_CTL.SCKI_POL=0 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK rising edge that is 0.5 SCK cycles before the SCK falling edge in 1)
440143) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=0: Serial data will be transmitted off the SCK rising edge
440154) TX_CTL.SCKI_POL=1 and TX_CTL.B_CLOCK_INV=1: Serial data will be transmitted off the SCK falling edge that is 0.5 SCK cycles before the SCK rising edge in 3)
44016
44017(Note that this is only the appearance w.r.t. SCK edge, the actual timing is generated by an internal clock that runs 8x the SCK frequency). The word sync (TX_WS) signal is not affected by this bit setting.
44018Note: When Master mode, must be '0'.
44019(Note: This bit is connected to AR38U12.TX_CFG.TX_BCLKINV)</description>
44020              <bitRange>[3:3]</bitRange>
44021              <access>read-write</access>
44022              <enumeratedValues>
44023                <enumeratedValue>
44024                  <name>FALLING_EDGE_TX</name>
44025                  <description>SDO transmitted at SCK falling edge when TX_CTL.SCKI_POL=0</description>
44026                  <value>0</value>
44027                </enumeratedValue>
44028                <enumeratedValue>
44029                  <name>RISING_EDGE_TX</name>
44030                  <description>SDO transmitted at SCK rising edge when TX_CTL.SCKI_POL=0</description>
44031                  <value>1</value>
44032                </enumeratedValue>
44033              </enumeratedValues>
44034            </field>
44035            <field>
44036              <name>CH_NR</name>
44037              <description>Specifies number of channels per frame:
44038
44039Note: only '2channels' is supported during Left Justfied or I2S mode. Hence software must set '1' to this field in the modes.
44040(Note: These bits are connected to AR38U12.TX_CFG.TX_CHSET)</description>
44041              <bitRange>[6:4]</bitRange>
44042              <access>read-write</access>
44043              <enumeratedValues>
44044                <enumeratedValue>
44045                  <name>CH_NUM1</name>
44046                  <description>1 channel</description>
44047                  <value>0</value>
44048                </enumeratedValue>
44049                <enumeratedValue>
44050                  <name>CH_NUM2</name>
44051                  <description>2 channels</description>
44052                  <value>1</value>
44053                </enumeratedValue>
44054                <enumeratedValue>
44055                  <name>CH_NUM3</name>
44056                  <description>3 channels</description>
44057                  <value>2</value>
44058                </enumeratedValue>
44059                <enumeratedValue>
44060                  <name>CH_NUM4</name>
44061                  <description>4 channels</description>
44062                  <value>3</value>
44063                </enumeratedValue>
44064                <enumeratedValue>
44065                  <name>CH_NUM5</name>
44066                  <description>5 channels</description>
44067                  <value>4</value>
44068                </enumeratedValue>
44069                <enumeratedValue>
44070                  <name>CH_NUM6</name>
44071                  <description>6 channels</description>
44072                  <value>5</value>
44073                </enumeratedValue>
44074                <enumeratedValue>
44075                  <name>CH_NUM7</name>
44076                  <description>7 channels</description>
44077                  <value>6</value>
44078                </enumeratedValue>
44079                <enumeratedValue>
44080                  <name>CH_NUM8</name>
44081                  <description>8 channels</description>
44082                  <value>7</value>
44083                </enumeratedValue>
44084              </enumeratedValues>
44085            </field>
44086            <field>
44087              <name>MS</name>
44088              <description>Set interface in master or slave mode:
44089
44090(Note: This bit is connected to AR38U12.TX_CFG.TX_MS)</description>
44091              <bitRange>[7:7]</bitRange>
44092              <access>read-write</access>
44093              <enumeratedValues>
44094                <enumeratedValue>
44095                  <name>SLAVE</name>
44096                  <description>Slave</description>
44097                  <value>0</value>
44098                </enumeratedValue>
44099                <enumeratedValue>
44100                  <name>MASTER</name>
44101                  <description>Master</description>
44102                  <value>1</value>
44103                </enumeratedValue>
44104              </enumeratedValues>
44105            </field>
44106            <field>
44107              <name>I2S_MODE</name>
44108              <description>Select I2S, left-justified or TDM:
44109
44110(Note: These bits are connected to AR38U12.TX_CFG.TX_I2S_MODE)</description>
44111              <bitRange>[9:8]</bitRange>
44112              <access>read-write</access>
44113              <enumeratedValues>
44114                <enumeratedValue>
44115                  <name>LEFT_JUSTIFIED</name>
44116                  <description>Left Justified</description>
44117                  <value>0</value>
44118                </enumeratedValue>
44119                <enumeratedValue>
44120                  <name>I2S</name>
44121                  <description>I2S mode</description>
44122                  <value>1</value>
44123                </enumeratedValue>
44124                <enumeratedValue>
44125                  <name>TDM_A</name>
44126                  <description>TDM mode A, the 1st Channel align to WSO
44127Rising Edge</description>
44128                  <value>2</value>
44129                </enumeratedValue>
44130                <enumeratedValue>
44131                  <name>TDM_B</name>
44132                  <description>TDM mode B, the 1st Channel align to WSO
44133Rising edge with1 SCK Delay</description>
44134                  <value>3</value>
44135                </enumeratedValue>
44136              </enumeratedValues>
44137            </field>
44138            <field>
44139              <name>WS_PULSE</name>
44140              <description>Set WS pulse width in TDM mode:
44141
44142(Note: This bit is connected to AR38U12.TX_CFG.TX_WS_PULSE)
44143Note: When not TDM mode, must be '1'.</description>
44144              <bitRange>[10:10]</bitRange>
44145              <access>read-write</access>
44146              <enumeratedValues>
44147                <enumeratedValue>
44148                  <name>SCK_PERIOD</name>
44149                  <description>Pulse width is 1 SCK period</description>
44150                  <value>0</value>
44151                </enumeratedValue>
44152                <enumeratedValue>
44153                  <name>CH_LENGTH</name>
44154                  <description>Pulse width is 1 channel length</description>
44155                  <value>1</value>
44156                </enumeratedValue>
44157              </enumeratedValues>
44158            </field>
44159            <field>
44160              <name>OVHDATA</name>
44161              <description>Set overhead value:
44162'0': Set to '0'
44163'1': Set to '1'
44164(Note: This bit is connected to AR38U12.TX_CFG.TX_OVHDATA)</description>
44165              <bitRange>[12:12]</bitRange>
44166              <access>read-write</access>
44167            </field>
44168            <field>
44169              <name>WD_EN</name>
44170              <description>Set watchdog for 'tx_ws_in':
44171'0': Disabled.
44172'1': Enabled.</description>
44173              <bitRange>[13:13]</bitRange>
44174              <access>read-write</access>
44175            </field>
44176            <field>
44177              <name>CH_LEN</name>
44178              <description>Channel length in number of bits:
44179
44180Note:
44181- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5').
44182- When TDM mode, must be 32-bit length to this field.
44183(Note: These bits are connected to AR38U12.TX_CFG.TX_CHLEN)</description>
44184              <bitRange>[18:16]</bitRange>
44185              <access>read-write</access>
44186              <enumeratedValues>
44187                <enumeratedValue>
44188                  <name>BIT_LEN8</name>
44189                  <description>8-bit</description>
44190                  <value>0</value>
44191                </enumeratedValue>
44192                <enumeratedValue>
44193                  <name>BIT_LEN16</name>
44194                  <description>16-bit</description>
44195                  <value>1</value>
44196                </enumeratedValue>
44197                <enumeratedValue>
44198                  <name>BIT_LEN18</name>
44199                  <description>18-bit</description>
44200                  <value>2</value>
44201                </enumeratedValue>
44202                <enumeratedValue>
44203                  <name>BIT_LEN20</name>
44204                  <description>20-bit</description>
44205                  <value>3</value>
44206                </enumeratedValue>
44207                <enumeratedValue>
44208                  <name>BIT_LEN24</name>
44209                  <description>24-bit</description>
44210                  <value>4</value>
44211                </enumeratedValue>
44212                <enumeratedValue>
44213                  <name>BIT_LEN32</name>
44214                  <description>32-bit</description>
44215                  <value>5</value>
44216                </enumeratedValue>
44217              </enumeratedValues>
44218            </field>
44219            <field>
44220              <name>WORD_LEN</name>
44221              <description>Word length in number of bits:
44222
44223Note:
44224- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5').
44225- Don't configure this field as beyond Channel length.
44226(Note: These bits are connected to AR38U12.TX_CFG.TX_IWL)</description>
44227              <bitRange>[22:20]</bitRange>
44228              <access>read-write</access>
44229              <enumeratedValues>
44230                <enumeratedValue>
44231                  <name>BIT_LEN8</name>
44232                  <description>8-bit</description>
44233                  <value>0</value>
44234                </enumeratedValue>
44235                <enumeratedValue>
44236                  <name>BIT_LEN16</name>
44237                  <description>16-bit</description>
44238                  <value>1</value>
44239                </enumeratedValue>
44240                <enumeratedValue>
44241                  <name>BIT_LEN18</name>
44242                  <description>18-bit</description>
44243                  <value>2</value>
44244                </enumeratedValue>
44245                <enumeratedValue>
44246                  <name>BIT_LEN20</name>
44247                  <description>20-bit</description>
44248                  <value>3</value>
44249                </enumeratedValue>
44250                <enumeratedValue>
44251                  <name>BIT_LEN24</name>
44252                  <description>24-bit</description>
44253                  <value>4</value>
44254                </enumeratedValue>
44255                <enumeratedValue>
44256                  <name>BIT_LEN32</name>
44257                  <description>32-bit</description>
44258                  <value>5</value>
44259                </enumeratedValue>
44260              </enumeratedValues>
44261            </field>
44262            <field>
44263              <name>SCKO_POL</name>
44264              <description>TX master bit clock polarity.
44265When this bit is 1, the outgoing tx_sck signal is inverted after it has been transmitted from the I2S transceiver core. This bit does not affect the internal serial data transmission timing. The word sync (TX_WS) signal is not affected by this bit setting.
44266'0': When transmitter is in master mode, serial data is transmitted from the falling bit clock edge
44267'1': When transmitter is in master mode, serial data is transmitted from the rising bit clock edge</description>
44268              <bitRange>[24:24]</bitRange>
44269              <access>read-write</access>
44270            </field>
44271            <field>
44272              <name>SCKI_POL</name>
44273              <description>TX slave bit clock polarity.
44274When this bit is 1, the incoming tx_sck signal is inverted before it is received by the I2S transceiver core. This bit does not affect the internal serial data transmission timing. The word sync (TX_WS) signal is not affected by this bit setting. See TX_CTL.B_CLOCK_INV for more details.</description>
44275              <bitRange>[25:25]</bitRange>
44276              <access>read-write</access>
44277            </field>
44278          </fields>
44279        </register>
44280        <register>
44281          <name>TX_WATCHDOG</name>
44282          <description>Transmitter watchdog</description>
44283          <addressOffset>0x84</addressOffset>
44284          <size>32</size>
44285          <access>read-write</access>
44286          <resetValue>0x0</resetValue>
44287          <resetMask>0xFFFFFFFF</resetMask>
44288          <fields>
44289            <field>
44290              <name>WD_COUNTER</name>
44291              <description>Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'.</description>
44292              <bitRange>[31:0]</bitRange>
44293              <access>read-write</access>
44294            </field>
44295          </fields>
44296        </register>
44297        <register>
44298          <name>RX_CTL</name>
44299          <description>Receiver control</description>
44300          <addressOffset>0xA0</addressOffset>
44301          <size>32</size>
44302          <access>read-write</access>
44303          <resetValue>0x440510</resetValue>
44304          <resetMask>0x3F727F8</resetMask>
44305          <fields>
44306            <field>
44307              <name>B_CLOCK_INV</name>
44308              <description>Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode.
44309When set to '1', the serial data will be captured 0.5 SCK cycles later than when set to '0'.
44310
443111) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK rising edge
443122) RX_CTL.SCKO_POL=0 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK falling edge that is 0.5 SCK cycles after the SCK rising edge in 1)
443133) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=0: Serial data will be captured by the SCK falling edge
443144) RX_CTL.SCKO_POL=1 and RX_CTL.B_CLOCK_INV=1: Serial data will be captured by the SCK rising edge that is 0.5 SCK cycles after the SCK falling edge in 3)
44315
44316(Note that this is only the appearance w.r.t. SCK edge, the actual capture timing is derived from an internal clock that runs 8x the SCK frequency). The word sync (RX_WS) signal is not affected by this bit setting.
44317Note: When Slave mode, must be '0'.
44318(Note: This bit is connected to AR38U12.TX_CFG.RX_BCLKINV)</description>
44319              <bitRange>[3:3]</bitRange>
44320              <access>read-write</access>
44321              <enumeratedValues>
44322                <enumeratedValue>
44323                  <name>RISING_EDGE_RX</name>
44324                  <description>SDI received at SCK rising edge when RX_CTL.SCKO_POL=0</description>
44325                  <value>0</value>
44326                </enumeratedValue>
44327                <enumeratedValue>
44328                  <name>FALLING_EDGE_RX</name>
44329                  <description>SDI received at SCK falling edge when RX_CTL.SCKO_POL=0</description>
44330                  <value>1</value>
44331                </enumeratedValue>
44332              </enumeratedValues>
44333            </field>
44334            <field>
44335              <name>CH_NR</name>
44336              <description>Specifies number of channels per frame:
44337
44338Note: only '2channels' is supported during Left Justfied or I2S mode. Hence software must set '1' to this field in the modes.
44339(Note: These bits are connected to AR38U12.RX_CFG.RX_CHSET)</description>
44340              <bitRange>[6:4]</bitRange>
44341              <access>read-write</access>
44342              <enumeratedValues>
44343                <enumeratedValue>
44344                  <name>CH_NUM1</name>
44345                  <description>1 channel</description>
44346                  <value>0</value>
44347                </enumeratedValue>
44348                <enumeratedValue>
44349                  <name>CH_NUM2</name>
44350                  <description>2 channels</description>
44351                  <value>1</value>
44352                </enumeratedValue>
44353                <enumeratedValue>
44354                  <name>CH_NUM3</name>
44355                  <description>3 channels</description>
44356                  <value>2</value>
44357                </enumeratedValue>
44358                <enumeratedValue>
44359                  <name>CH_NUM4</name>
44360                  <description>4 channels</description>
44361                  <value>3</value>
44362                </enumeratedValue>
44363                <enumeratedValue>
44364                  <name>CH_NUM5</name>
44365                  <description>5 channels</description>
44366                  <value>4</value>
44367                </enumeratedValue>
44368                <enumeratedValue>
44369                  <name>CH_NUM6</name>
44370                  <description>6 channels</description>
44371                  <value>5</value>
44372                </enumeratedValue>
44373                <enumeratedValue>
44374                  <name>CH_NUM7</name>
44375                  <description>7 channels</description>
44376                  <value>6</value>
44377                </enumeratedValue>
44378                <enumeratedValue>
44379                  <name>CH_NUM8</name>
44380                  <description>8 channels</description>
44381                  <value>7</value>
44382                </enumeratedValue>
44383              </enumeratedValues>
44384            </field>
44385            <field>
44386              <name>MS</name>
44387              <description>Set interface in master or slave mode:
44388
44389(Note: This bit is connected to AR38U12.TX_CFG.RX_MS)</description>
44390              <bitRange>[7:7]</bitRange>
44391              <access>read-write</access>
44392              <enumeratedValues>
44393                <enumeratedValue>
44394                  <name>SLAVE</name>
44395                  <description>Slave</description>
44396                  <value>0</value>
44397                </enumeratedValue>
44398                <enumeratedValue>
44399                  <name>MASTER</name>
44400                  <description>Master</description>
44401                  <value>1</value>
44402                </enumeratedValue>
44403              </enumeratedValues>
44404            </field>
44405            <field>
44406              <name>I2S_MODE</name>
44407              <description>Select I2S, left-justified or TDM:
44408
44409(Note: These bits are connected to AR38U12.RX_CFG.RX_I2S_MODE)</description>
44410              <bitRange>[9:8]</bitRange>
44411              <access>read-write</access>
44412              <enumeratedValues>
44413                <enumeratedValue>
44414                  <name>LEFT_JUSTIFIED</name>
44415                  <description>Left Justified</description>
44416                  <value>0</value>
44417                </enumeratedValue>
44418                <enumeratedValue>
44419                  <name>I2S</name>
44420                  <description>I2S mode</description>
44421                  <value>1</value>
44422                </enumeratedValue>
44423                <enumeratedValue>
44424                  <name>TDM_A</name>
44425                  <description>TDM mode A, the 1st Channel align to WSO
44426Rising Edge</description>
44427                  <value>2</value>
44428                </enumeratedValue>
44429                <enumeratedValue>
44430                  <name>TDM_B</name>
44431                  <description>TDM mode B, the 1st Channel align to WSO
44432Rising edge with1 SCK Delay</description>
44433                  <value>3</value>
44434                </enumeratedValue>
44435              </enumeratedValues>
44436            </field>
44437            <field>
44438              <name>WS_PULSE</name>
44439              <description>Set WS pulse width in TDM mode:
44440
44441(Note: This bit is connected to AR38U12.RX_CFG.RX_WS_PULSE)
44442Note: When not TDM mode, must be '1'.</description>
44443              <bitRange>[10:10]</bitRange>
44444              <access>read-write</access>
44445              <enumeratedValues>
44446                <enumeratedValue>
44447                  <name>SCK_PERIOD</name>
44448                  <description>Pulse width is 1 SCK period</description>
44449                  <value>0</value>
44450                </enumeratedValue>
44451                <enumeratedValue>
44452                  <name>CH_LENGTH</name>
44453                  <description>Pulse width is 1 channel length</description>
44454                  <value>1</value>
44455                </enumeratedValue>
44456              </enumeratedValues>
44457            </field>
44458            <field>
44459              <name>WD_EN</name>
44460              <description>Set watchdog for 'rx_ws_in'
44461'0': Disabled.
44462'1': Enabled.</description>
44463              <bitRange>[13:13]</bitRange>
44464              <access>read-write</access>
44465            </field>
44466            <field>
44467              <name>CH_LEN</name>
44468              <description>Channel length in number of bits:
44469
44470Note:
44471- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5').
44472- When TDM mode, must be 32-bit length to this field.
44473(Note: These bits are connected to AR38U12.RX_CFG.RX_CHLEN)</description>
44474              <bitRange>[18:16]</bitRange>
44475              <access>read-write</access>
44476              <enumeratedValues>
44477                <enumeratedValue>
44478                  <name>BIT_LEN8</name>
44479                  <description>8-bit</description>
44480                  <value>0</value>
44481                </enumeratedValue>
44482                <enumeratedValue>
44483                  <name>BIT_LEN16</name>
44484                  <description>16-bit</description>
44485                  <value>1</value>
44486                </enumeratedValue>
44487                <enumeratedValue>
44488                  <name>BIT_LEN18</name>
44489                  <description>18-bit</description>
44490                  <value>2</value>
44491                </enumeratedValue>
44492                <enumeratedValue>
44493                  <name>BIT_LEN20</name>
44494                  <description>20-bit</description>
44495                  <value>3</value>
44496                </enumeratedValue>
44497                <enumeratedValue>
44498                  <name>BIT_LEN24</name>
44499                  <description>24-bit</description>
44500                  <value>4</value>
44501                </enumeratedValue>
44502                <enumeratedValue>
44503                  <name>BIT_LEN32</name>
44504                  <description>32-bit</description>
44505                  <value>5</value>
44506                </enumeratedValue>
44507              </enumeratedValues>
44508            </field>
44509            <field>
44510              <name>WORD_LEN</name>
44511              <description>Word length in number of bits:
44512
44513Note:
44514- When this field is configured to '6' or '7', the length is set to 32-bit (same as '5').
44515- Don't configure this field as beyond Channel length.
44516(Note: These bits are connected to AR38U12.RX_CFG.RX_IWL)</description>
44517              <bitRange>[22:20]</bitRange>
44518              <access>read-write</access>
44519              <enumeratedValues>
44520                <enumeratedValue>
44521                  <name>BIT_LEN8</name>
44522                  <description>8-bit</description>
44523                  <value>0</value>
44524                </enumeratedValue>
44525                <enumeratedValue>
44526                  <name>BIT_LEN16</name>
44527                  <description>16-bit</description>
44528                  <value>1</value>
44529                </enumeratedValue>
44530                <enumeratedValue>
44531                  <name>BIT_LEN18</name>
44532                  <description>18-bit</description>
44533                  <value>2</value>
44534                </enumeratedValue>
44535                <enumeratedValue>
44536                  <name>BIT_LEN20</name>
44537                  <description>20-bit</description>
44538                  <value>3</value>
44539                </enumeratedValue>
44540                <enumeratedValue>
44541                  <name>BIT_LEN24</name>
44542                  <description>24-bit</description>
44543                  <value>4</value>
44544                </enumeratedValue>
44545                <enumeratedValue>
44546                  <name>BIT_LEN32</name>
44547                  <description>32-bit</description>
44548                  <value>5</value>
44549                </enumeratedValue>
44550              </enumeratedValues>
44551            </field>
44552            <field>
44553              <name>BIT_EXTENSION</name>
44554              <description>When reception word length is shorter than the word length of RX_FIFO_RD, extension mode of upper bit should be set.
44555'0': Extended by '0'
44556'1': Extended by sign bit (if MSB word is '1', then it is extended by '1', if MSB is '0' then it is extended by '0')</description>
44557              <bitRange>[23:23]</bitRange>
44558              <access>read-write</access>
44559            </field>
44560            <field>
44561              <name>SCKO_POL</name>
44562              <description>RX master bit clock polarity.
44563When this bit is 1, the outgoing rx_sck signal is inverted after it has been transmitted from the I2S receiver core. This bit does not affect the internal serial data capture timing. The word sync (RX_WS) signal is not affected by this bit setting.See RX_CTL.B_CLOCK_INV for more details.</description>
44564              <bitRange>[24:24]</bitRange>
44565              <access>read-write</access>
44566            </field>
44567            <field>
44568              <name>SCKI_POL</name>
44569              <description>RX slave bit clock polarity.
44570When this bit is 1, the incoming rx_sck signal is inverted before it is received by the I2S receiver core. This bit does not affect the internal serial data capture timing. The word sync (RX_WS) signal is not affected by this bit setting.
44571'0': When receiver is in slave mode, serial data is sampled on the rising bit clock edge
44572'1': When receiver is in slave mode, serial data is sampled on the falling bit clock edge</description>
44573              <bitRange>[25:25]</bitRange>
44574              <access>read-write</access>
44575            </field>
44576          </fields>
44577        </register>
44578        <register>
44579          <name>RX_WATCHDOG</name>
44580          <description>Receiver watchdog</description>
44581          <addressOffset>0xA4</addressOffset>
44582          <size>32</size>
44583          <access>read-write</access>
44584          <resetValue>0x0</resetValue>
44585          <resetMask>0xFFFFFFFF</resetMask>
44586          <fields>
44587            <field>
44588              <name>WD_COUNTER</name>
44589              <description>Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'.</description>
44590              <bitRange>[31:0]</bitRange>
44591              <access>read-write</access>
44592            </field>
44593          </fields>
44594        </register>
44595        <register>
44596          <name>TX_FIFO_CTL</name>
44597          <description>TX FIFO control</description>
44598          <addressOffset>0x200</addressOffset>
44599          <size>32</size>
44600          <access>read-write</access>
44601          <resetValue>0x0</resetValue>
44602          <resetMask>0x300FF</resetMask>
44603          <fields>
44604            <field>
44605              <name>TRIGGER_LEVEL</name>
44606              <description>Trigger level. When the TX FIFO has less entries than the number of this field, a transmitter trigger event is generated.</description>
44607              <bitRange>[7:0]</bitRange>
44608              <access>read-write</access>
44609            </field>
44610            <field>
44611              <name>CLEAR</name>
44612              <description>When '1', the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
44613              <bitRange>[16:16]</bitRange>
44614              <access>read-write</access>
44615            </field>
44616            <field>
44617              <name>FREEZE</name>
44618              <description>When '1', hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. This field is used only for debugging purposes.</description>
44619              <bitRange>[17:17]</bitRange>
44620              <access>read-write</access>
44621            </field>
44622          </fields>
44623        </register>
44624        <register>
44625          <name>TX_FIFO_STATUS</name>
44626          <description>TX FIFO status</description>
44627          <addressOffset>0x204</addressOffset>
44628          <size>32</size>
44629          <access>read-only</access>
44630          <resetValue>0x0</resetValue>
44631          <resetMask>0xFFFF01FF</resetMask>
44632          <fields>
44633            <field>
44634              <name>USED</name>
44635              <description>Number of entries in the TX FIFO. The field value is in the range [0, 256].</description>
44636              <bitRange>[8:0]</bitRange>
44637              <access>read-only</access>
44638            </field>
44639            <field>
44640              <name>RD_PTR</name>
44641              <description>TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes.</description>
44642              <bitRange>[23:16]</bitRange>
44643              <access>read-only</access>
44644            </field>
44645            <field>
44646              <name>WR_PTR</name>
44647              <description>TX FIFO write pointer: FIFO location at which a new data frame is written by the host. This field is used only for debugging purposes.</description>
44648              <bitRange>[31:24]</bitRange>
44649              <access>read-only</access>
44650            </field>
44651          </fields>
44652        </register>
44653        <register>
44654          <name>TX_FIFO_WR</name>
44655          <description>TX FIFO write</description>
44656          <addressOffset>0x208</addressOffset>
44657          <size>32</size>
44658          <access>write-only</access>
44659          <resetValue>0x0</resetValue>
44660          <resetMask>0xFFFFFFFF</resetMask>
44661          <fields>
44662            <field>
44663              <name>DATA</name>
44664              <description>Data written into the TX FIFO. Behavior is similar to that of a PUSH operation.
44665Note: Don't access to this register while TX_FIFO_CTL.CLEAR is '1'.</description>
44666              <bitRange>[31:0]</bitRange>
44667              <access>write-only</access>
44668            </field>
44669          </fields>
44670        </register>
44671        <register>
44672          <name>RX_FIFO_CTL</name>
44673          <description>RX FIFO control</description>
44674          <addressOffset>0x300</addressOffset>
44675          <size>32</size>
44676          <access>read-write</access>
44677          <resetValue>0x0</resetValue>
44678          <resetMask>0x300FF</resetMask>
44679          <fields>
44680            <field>
44681              <name>TRIGGER_LEVEL</name>
44682              <description>Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated.
44683Note: software can configure up to 253 in I2S mode or Left Justified (RX_CTL.I2S_MODE = '0' or '1'). In TDM mode (RX_CTL.I2S_MODE = '2' or '3'), it can configure up to [256 - (RX_CTL.CH_NR+2)].</description>
44684              <bitRange>[7:0]</bitRange>
44685              <access>read-write</access>
44686            </field>
44687            <field>
44688              <name>CLEAR</name>
44689              <description>When '1', the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required, the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is required for an extended time period, the field should be set to '1' during the complete time period.</description>
44690              <bitRange>[16:16]</bitRange>
44691              <access>read-write</access>
44692            </field>
44693            <field>
44694              <name>FREEZE</name>
44695              <description>When '1', hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee.</description>
44696              <bitRange>[17:17]</bitRange>
44697              <access>read-write</access>
44698            </field>
44699          </fields>
44700        </register>
44701        <register>
44702          <name>RX_FIFO_STATUS</name>
44703          <description>RX FIFO status</description>
44704          <addressOffset>0x304</addressOffset>
44705          <size>32</size>
44706          <access>read-only</access>
44707          <resetValue>0x0</resetValue>
44708          <resetMask>0xFFFF01FF</resetMask>
44709          <fields>
44710            <field>
44711              <name>USED</name>
44712              <description>Number of entries in the RX FIFO. The field value is in the range [0, 256].</description>
44713              <bitRange>[8:0]</bitRange>
44714              <access>read-only</access>
44715            </field>
44716            <field>
44717              <name>RD_PTR</name>
44718              <description>RX FIFO read pointer: FIFO location from which a data frame is read by the host. This field is used only for debugging purposes.</description>
44719              <bitRange>[23:16]</bitRange>
44720              <access>read-only</access>
44721            </field>
44722            <field>
44723              <name>WR_PTR</name>
44724              <description>RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware. This field is used only for debugging purposes.</description>
44725              <bitRange>[31:24]</bitRange>
44726              <access>read-only</access>
44727            </field>
44728          </fields>
44729        </register>
44730        <register>
44731          <name>RX_FIFO_RD</name>
44732          <description>RX FIFO read</description>
44733          <addressOffset>0x308</addressOffset>
44734          <size>32</size>
44735          <access>read-only</access>
44736          <resetValue>0x0</resetValue>
44737          <resetMask>0xFFFFFFFF</resetMask>
44738          <fields>
44739            <field>
44740              <name>DATA</name>
44741              <description>Data read from the RX FIFO. Reading a data frame will remove the data frame from the RX FIFO; i.e. behavior is similar to that of a POP operation.
44742Notes:
44743 - Don't access to this register while RX_FIFO_CTL.CLEAR is '1'.
44744 - Two stored data may be not valid after CMD.RX_START is set '1'. Therefore we recommend software discard those data.</description>
44745              <bitRange>[31:0]</bitRange>
44746              <access>read-only</access>
44747            </field>
44748          </fields>
44749        </register>
44750        <register>
44751          <name>RX_FIFO_RD_SILENT</name>
44752          <description>RX FIFO silent read</description>
44753          <addressOffset>0x30C</addressOffset>
44754          <size>32</size>
44755          <access>read-only</access>
44756          <resetValue>0x0</resetValue>
44757          <resetMask>0xFFFFFFFF</resetMask>
44758          <fields>
44759            <field>
44760              <name>DATA</name>
44761              <description>Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes.
44762Notes:
44763 - Don't access to this register while RX_FIFO_CTL.CLEAR is '1'.
44764 - Two stored data may be not valid after CMD.RX_START is set '1'. Therefore we recommend software discard those data.</description>
44765              <bitRange>[31:0]</bitRange>
44766              <access>read-only</access>
44767            </field>
44768          </fields>
44769        </register>
44770        <register>
44771          <name>INTR</name>
44772          <description>Interrupt register</description>
44773          <addressOffset>0xF00</addressOffset>
44774          <size>32</size>
44775          <access>read-write</access>
44776          <resetValue>0x0</resetValue>
44777          <resetMask>0x16D0173</resetMask>
44778          <fields>
44779            <field>
44780              <name>TX_TRIGGER</name>
44781              <description>Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL.</description>
44782              <bitRange>[0:0]</bitRange>
44783              <access>read-write</access>
44784            </field>
44785            <field>
44786              <name>TX_NOT_FULL</name>
44787              <description>TX FIFO is not full.</description>
44788              <bitRange>[1:1]</bitRange>
44789              <access>read-write</access>
44790            </field>
44791            <field>
44792              <name>TX_EMPTY</name>
44793              <description>TX FIFO is empty; i.e. it has 0 entries.</description>
44794              <bitRange>[4:4]</bitRange>
44795              <access>read-write</access>
44796            </field>
44797            <field>
44798              <name>TX_OVERFLOW</name>
44799              <description>Attempt to write to a full TX FIFO.</description>
44800              <bitRange>[5:5]</bitRange>
44801              <access>read-write</access>
44802            </field>
44803            <field>
44804              <name>TX_UNDERFLOW</name>
44805              <description>Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and TX_EMPTY is '1'.</description>
44806              <bitRange>[6:6]</bitRange>
44807              <access>read-write</access>
44808            </field>
44809            <field>
44810              <name>TX_WD</name>
44811              <description>Triggers (sets to '1') when the Tx watchdog event occurs.</description>
44812              <bitRange>[8:8]</bitRange>
44813              <access>read-write</access>
44814            </field>
44815            <field>
44816              <name>RX_TRIGGER</name>
44817              <description>More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL.</description>
44818              <bitRange>[16:16]</bitRange>
44819              <access>read-write</access>
44820            </field>
44821            <field>
44822              <name>RX_NOT_EMPTY</name>
44823              <description>RX FIFO is not empty.</description>
44824              <bitRange>[18:18]</bitRange>
44825              <access>read-write</access>
44826            </field>
44827            <field>
44828              <name>RX_FULL</name>
44829              <description>RX FIFO is full.</description>
44830              <bitRange>[19:19]</bitRange>
44831              <access>read-write</access>
44832            </field>
44833            <field>
44834              <name>RX_OVERFLOW</name>
44835              <description>Attempt to write to a full RX FIFO.</description>
44836              <bitRange>[21:21]</bitRange>
44837              <access>read-write</access>
44838            </field>
44839            <field>
44840              <name>RX_UNDERFLOW</name>
44841              <description>Attempt to read from an empty RX FIFO.</description>
44842              <bitRange>[22:22]</bitRange>
44843              <access>read-write</access>
44844            </field>
44845            <field>
44846              <name>RX_WD</name>
44847              <description>Triggers (sets to '1') when the Rx watchdog event occurs.</description>
44848              <bitRange>[24:24]</bitRange>
44849              <access>read-write</access>
44850            </field>
44851          </fields>
44852        </register>
44853        <register>
44854          <name>INTR_SET</name>
44855          <description>Interrupt set register</description>
44856          <addressOffset>0xF04</addressOffset>
44857          <size>32</size>
44858          <access>read-write</access>
44859          <resetValue>0x0</resetValue>
44860          <resetMask>0x16D0173</resetMask>
44861          <fields>
44862            <field>
44863              <name>TX_TRIGGER</name>
44864              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
44865              <bitRange>[0:0]</bitRange>
44866              <access>read-write</access>
44867            </field>
44868            <field>
44869              <name>TX_NOT_FULL</name>
44870              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
44871              <bitRange>[1:1]</bitRange>
44872              <access>read-write</access>
44873            </field>
44874            <field>
44875              <name>TX_EMPTY</name>
44876              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
44877              <bitRange>[4:4]</bitRange>
44878              <access>read-write</access>
44879            </field>
44880            <field>
44881              <name>TX_OVERFLOW</name>
44882              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
44883              <bitRange>[5:5]</bitRange>
44884              <access>read-write</access>
44885            </field>
44886            <field>
44887              <name>TX_UNDERFLOW</name>
44888              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
44889              <bitRange>[6:6]</bitRange>
44890              <access>read-write</access>
44891            </field>
44892            <field>
44893              <name>TX_WD</name>
44894              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
44895              <bitRange>[8:8]</bitRange>
44896              <access>read-write</access>
44897            </field>
44898            <field>
44899              <name>RX_TRIGGER</name>
44900              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
44901              <bitRange>[16:16]</bitRange>
44902              <access>read-write</access>
44903            </field>
44904            <field>
44905              <name>RX_NOT_EMPTY</name>
44906              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
44907              <bitRange>[18:18]</bitRange>
44908              <access>read-write</access>
44909            </field>
44910            <field>
44911              <name>RX_FULL</name>
44912              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
44913              <bitRange>[19:19]</bitRange>
44914              <access>read-write</access>
44915            </field>
44916            <field>
44917              <name>RX_OVERFLOW</name>
44918              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
44919              <bitRange>[21:21]</bitRange>
44920              <access>read-write</access>
44921            </field>
44922            <field>
44923              <name>RX_UNDERFLOW</name>
44924              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
44925              <bitRange>[22:22]</bitRange>
44926              <access>read-write</access>
44927            </field>
44928            <field>
44929              <name>RX_WD</name>
44930              <description>Write with '1' to set corresponding bit in interrupt request register.</description>
44931              <bitRange>[24:24]</bitRange>
44932              <access>read-write</access>
44933            </field>
44934          </fields>
44935        </register>
44936        <register>
44937          <name>INTR_MASK</name>
44938          <description>Interrupt mask register</description>
44939          <addressOffset>0xF08</addressOffset>
44940          <size>32</size>
44941          <access>read-write</access>
44942          <resetValue>0x0</resetValue>
44943          <resetMask>0x16D0173</resetMask>
44944          <fields>
44945            <field>
44946              <name>TX_TRIGGER</name>
44947              <description>Mask bit for corresponding bit in interrupt request register.</description>
44948              <bitRange>[0:0]</bitRange>
44949              <access>read-write</access>
44950            </field>
44951            <field>
44952              <name>TX_NOT_FULL</name>
44953              <description>Mask bit for corresponding bit in interrupt request register.</description>
44954              <bitRange>[1:1]</bitRange>
44955              <access>read-write</access>
44956            </field>
44957            <field>
44958              <name>TX_EMPTY</name>
44959              <description>Mask bit for corresponding bit in interrupt request register.</description>
44960              <bitRange>[4:4]</bitRange>
44961              <access>read-write</access>
44962            </field>
44963            <field>
44964              <name>TX_OVERFLOW</name>
44965              <description>Mask bit for corresponding bit in interrupt request register.</description>
44966              <bitRange>[5:5]</bitRange>
44967              <access>read-write</access>
44968            </field>
44969            <field>
44970              <name>TX_UNDERFLOW</name>
44971              <description>Mask bit for corresponding bit in interrupt request register.</description>
44972              <bitRange>[6:6]</bitRange>
44973              <access>read-write</access>
44974            </field>
44975            <field>
44976              <name>TX_WD</name>
44977              <description>Mask bit for corresponding bit in interrupt request register.</description>
44978              <bitRange>[8:8]</bitRange>
44979              <access>read-write</access>
44980            </field>
44981            <field>
44982              <name>RX_TRIGGER</name>
44983              <description>Mask bit for corresponding bit in interrupt request register.</description>
44984              <bitRange>[16:16]</bitRange>
44985              <access>read-write</access>
44986            </field>
44987            <field>
44988              <name>RX_NOT_EMPTY</name>
44989              <description>Mask bit for corresponding bit in interrupt request register.</description>
44990              <bitRange>[18:18]</bitRange>
44991              <access>read-write</access>
44992            </field>
44993            <field>
44994              <name>RX_FULL</name>
44995              <description>Mask bit for corresponding bit in interrupt request register.</description>
44996              <bitRange>[19:19]</bitRange>
44997              <access>read-write</access>
44998            </field>
44999            <field>
45000              <name>RX_OVERFLOW</name>
45001              <description>Mask bit for corresponding bit in interrupt request register.</description>
45002              <bitRange>[21:21]</bitRange>
45003              <access>read-write</access>
45004            </field>
45005            <field>
45006              <name>RX_UNDERFLOW</name>
45007              <description>Mask bit for corresponding bit in interrupt request register.</description>
45008              <bitRange>[22:22]</bitRange>
45009              <access>read-write</access>
45010            </field>
45011            <field>
45012              <name>RX_WD</name>
45013              <description>Mask bit for corresponding bit in interrupt request register.</description>
45014              <bitRange>[24:24]</bitRange>
45015              <access>read-write</access>
45016            </field>
45017          </fields>
45018        </register>
45019        <register>
45020          <name>INTR_MASKED</name>
45021          <description>Interrupt masked register</description>
45022          <addressOffset>0xF0C</addressOffset>
45023          <size>32</size>
45024          <access>read-only</access>
45025          <resetValue>0x0</resetValue>
45026          <resetMask>0x16D0173</resetMask>
45027          <fields>
45028            <field>
45029              <name>TX_TRIGGER</name>
45030              <description>Logical and of corresponding request and mask bits.</description>
45031              <bitRange>[0:0]</bitRange>
45032              <access>read-only</access>
45033            </field>
45034            <field>
45035              <name>TX_NOT_FULL</name>
45036              <description>Logical and of corresponding request and mask bits.</description>
45037              <bitRange>[1:1]</bitRange>
45038              <access>read-only</access>
45039            </field>
45040            <field>
45041              <name>TX_EMPTY</name>
45042              <description>Logical and of corresponding request and mask bits.</description>
45043              <bitRange>[4:4]</bitRange>
45044              <access>read-only</access>
45045            </field>
45046            <field>
45047              <name>TX_OVERFLOW</name>
45048              <description>Logical and of corresponding request and mask bits.</description>
45049              <bitRange>[5:5]</bitRange>
45050              <access>read-only</access>
45051            </field>
45052            <field>
45053              <name>TX_UNDERFLOW</name>
45054              <description>Logical and of corresponding request and mask bits.</description>
45055              <bitRange>[6:6]</bitRange>
45056              <access>read-only</access>
45057            </field>
45058            <field>
45059              <name>TX_WD</name>
45060              <description>Logical and of corresponding request and mask bits.</description>
45061              <bitRange>[8:8]</bitRange>
45062              <access>read-only</access>
45063            </field>
45064            <field>
45065              <name>RX_TRIGGER</name>
45066              <description>Logical and of corresponding request and mask bits.</description>
45067              <bitRange>[16:16]</bitRange>
45068              <access>read-only</access>
45069            </field>
45070            <field>
45071              <name>RX_NOT_EMPTY</name>
45072              <description>Logical and of corresponding request and mask bits.</description>
45073              <bitRange>[18:18]</bitRange>
45074              <access>read-only</access>
45075            </field>
45076            <field>
45077              <name>RX_FULL</name>
45078              <description>Logical and of corresponding request and mask bits.</description>
45079              <bitRange>[19:19]</bitRange>
45080              <access>read-only</access>
45081            </field>
45082            <field>
45083              <name>RX_OVERFLOW</name>
45084              <description>Logical and of corresponding request and mask bits.</description>
45085              <bitRange>[21:21]</bitRange>
45086              <access>read-only</access>
45087            </field>
45088            <field>
45089              <name>RX_UNDERFLOW</name>
45090              <description>Logical and of corresponding request and mask bits.</description>
45091              <bitRange>[22:22]</bitRange>
45092              <access>read-only</access>
45093            </field>
45094            <field>
45095              <name>RX_WD</name>
45096              <description>Logical and of corresponding request and mask bits.</description>
45097              <bitRange>[24:24]</bitRange>
45098              <access>read-only</access>
45099            </field>
45100          </fields>
45101        </register>
45102      </registers>
45103    </peripheral>
45104    <peripheral derivedFrom="I2S0">
45105      <name>I2S1</name>
45106      <baseAddress>0x40A11000</baseAddress>
45107    </peripheral>
45108  </peripherals>
45109</device>