1 /***************************************************************************//** 2 * \file cyip_tcpwm_v2.h 3 * 4 * \brief 5 * TCPWM IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_TCPWM_V2_H_ 28 #define _CYIP_TCPWM_V2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * TCPWM 34 *******************************************************************************/ 35 36 #define TCPWM_GRP_CNT_V2_SECTION_SIZE 0x00000080UL 37 #define TCPWM_GRP_V2_SECTION_SIZE 0x00008000UL 38 #define TCPWM_V2_SECTION_SIZE 0x00020000UL 39 40 /** 41 * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT) 42 */ 43 typedef struct { 44 __IOM uint32_t CTRL; /*!< 0x00000000 Counter control register */ 45 __IM uint32_t STATUS; /*!< 0x00000004 Counter status register */ 46 __IOM uint32_t COUNTER; /*!< 0x00000008 Counter count register */ 47 __IM uint32_t RESERVED; 48 __IOM uint32_t CC0; /*!< 0x00000010 Counter compare/capture 0 register */ 49 __IOM uint32_t CC0_BUFF; /*!< 0x00000014 Counter buffered compare/capture 0 register */ 50 __IOM uint32_t CC1; /*!< 0x00000018 Counter compare/capture 1 register */ 51 __IOM uint32_t CC1_BUFF; /*!< 0x0000001C Counter buffered compare/capture 1 register */ 52 __IOM uint32_t PERIOD; /*!< 0x00000020 Counter period register */ 53 __IOM uint32_t PERIOD_BUFF; /*!< 0x00000024 Counter buffered period register */ 54 __IOM uint32_t LINE_SEL; /*!< 0x00000028 Counter line selection register */ 55 __IOM uint32_t LINE_SEL_BUFF; /*!< 0x0000002C Counter buffered line selection register */ 56 __IOM uint32_t DT; /*!< 0x00000030 Counter PWM dead time register */ 57 __IM uint32_t RESERVED1[3]; 58 __IOM uint32_t TR_CMD; /*!< 0x00000040 Counter trigger command register */ 59 __IOM uint32_t TR_IN_SEL0; /*!< 0x00000044 Counter input trigger selection register 0 */ 60 __IOM uint32_t TR_IN_SEL1; /*!< 0x00000048 Counter input trigger selection register 1 */ 61 __IOM uint32_t TR_IN_EDGE_SEL; /*!< 0x0000004C Counter input trigger edge selection register */ 62 __IOM uint32_t TR_PWM_CTRL; /*!< 0x00000050 Counter trigger PWM control register */ 63 __IOM uint32_t TR_OUT_SEL; /*!< 0x00000054 Counter output trigger selection register */ 64 __IM uint32_t RESERVED2[6]; 65 __IOM uint32_t INTR; /*!< 0x00000070 Interrupt request register */ 66 __IOM uint32_t INTR_SET; /*!< 0x00000074 Interrupt set request register */ 67 __IOM uint32_t INTR_MASK; /*!< 0x00000078 Interrupt mask register */ 68 __IM uint32_t INTR_MASKED; /*!< 0x0000007C Interrupt masked request register */ 69 } TCPWM_GRP_CNT_V2_Type; /*!< Size = 128 (0x80) */ 70 71 /** 72 * \brief Group of counters (TCPWM_GRP) 73 */ 74 typedef struct { 75 TCPWM_GRP_CNT_V2_Type CNT[256]; /*!< 0x00000000 Timer/Counter/PWM Counter Module */ 76 } TCPWM_GRP_V2_Type; /*!< Size = 32768 (0x8000) */ 77 78 /** 79 * \brief Timer/Counter/PWM (TCPWM) 80 */ 81 typedef struct { 82 TCPWM_GRP_V2_Type GRP[4]; /*!< 0x00000000 Group of counters */ 83 } TCPWM_V2_Type; /*!< Size = 131072 (0x20000) */ 84 85 86 /* TCPWM_GRP_CNT.CTRL */ 87 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Pos 0UL 88 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Msk 0x1UL 89 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Pos 1UL 90 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Msk 0x2UL 91 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Pos 2UL 92 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Msk 0x4UL 93 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Pos 3UL 94 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Msk 0x8UL 95 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Pos 4UL 96 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Msk 0x10UL 97 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Pos 5UL 98 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Msk 0x20UL 99 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Pos 6UL 100 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Msk 0x40UL 101 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Pos 7UL 102 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Msk 0x80UL 103 #define TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Pos 8UL 104 #define TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Msk 0x100UL 105 #define TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Pos 9UL 106 #define TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Msk 0x200UL 107 #define TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Pos 10UL 108 #define TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Msk 0x400UL 109 #define TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Pos 12UL 110 #define TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Msk 0x3000UL 111 #define TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Pos 16UL 112 #define TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Msk 0x30000UL 113 #define TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Pos 18UL 114 #define TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Msk 0x40000UL 115 #define TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Pos 20UL 116 #define TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Msk 0x300000UL 117 #define TCPWM_GRP_CNT_V2_CTRL_MODE_Pos 24UL 118 #define TCPWM_GRP_CNT_V2_CTRL_MODE_Msk 0x7000000UL 119 #define TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Pos 30UL 120 #define TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Msk 0x40000000UL 121 #define TCPWM_GRP_CNT_V2_CTRL_ENABLED_Pos 31UL 122 #define TCPWM_GRP_CNT_V2_CTRL_ENABLED_Msk 0x80000000UL 123 /* TCPWM_GRP_CNT.STATUS */ 124 #define TCPWM_GRP_CNT_V2_STATUS_DOWN_Pos 0UL 125 #define TCPWM_GRP_CNT_V2_STATUS_DOWN_Msk 0x1UL 126 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Pos 4UL 127 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Msk 0x10UL 128 #define TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Pos 5UL 129 #define TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Msk 0x20UL 130 #define TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Pos 6UL 131 #define TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Msk 0x40UL 132 #define TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Pos 7UL 133 #define TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Msk 0x80UL 134 #define TCPWM_GRP_CNT_V2_STATUS_TR_START_Pos 8UL 135 #define TCPWM_GRP_CNT_V2_STATUS_TR_START_Msk 0x100UL 136 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Pos 9UL 137 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Msk 0x200UL 138 #define TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Pos 10UL 139 #define TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Msk 0x400UL 140 #define TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Pos 11UL 141 #define TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Msk 0x800UL 142 #define TCPWM_GRP_CNT_V2_STATUS_RUNNING_Pos 15UL 143 #define TCPWM_GRP_CNT_V2_STATUS_RUNNING_Msk 0x8000UL 144 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Pos 16UL 145 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Msk 0xFF0000UL 146 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Pos 24UL 147 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Msk 0xFF000000UL 148 /* TCPWM_GRP_CNT.COUNTER */ 149 #define TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Pos 0UL 150 #define TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Msk 0xFFFFFFFFUL 151 /* TCPWM_GRP_CNT.CC0 */ 152 #define TCPWM_GRP_CNT_V2_CC0_CC_Pos 0UL 153 #define TCPWM_GRP_CNT_V2_CC0_CC_Msk 0xFFFFFFFFUL 154 /* TCPWM_GRP_CNT.CC0_BUFF */ 155 #define TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Pos 0UL 156 #define TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Msk 0xFFFFFFFFUL 157 /* TCPWM_GRP_CNT.CC1 */ 158 #define TCPWM_GRP_CNT_V2_CC1_CC_Pos 0UL 159 #define TCPWM_GRP_CNT_V2_CC1_CC_Msk 0xFFFFFFFFUL 160 /* TCPWM_GRP_CNT.CC1_BUFF */ 161 #define TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Pos 0UL 162 #define TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Msk 0xFFFFFFFFUL 163 /* TCPWM_GRP_CNT.PERIOD */ 164 #define TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Pos 0UL 165 #define TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Msk 0xFFFFFFFFUL 166 /* TCPWM_GRP_CNT.PERIOD_BUFF */ 167 #define TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Pos 0UL 168 #define TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Msk 0xFFFFFFFFUL 169 /* TCPWM_GRP_CNT.LINE_SEL */ 170 #define TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Pos 0UL 171 #define TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Msk 0x7UL 172 #define TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Pos 4UL 173 #define TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Msk 0x70UL 174 /* TCPWM_GRP_CNT.LINE_SEL_BUFF */ 175 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Pos 0UL 176 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Msk 0x7UL 177 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos 4UL 178 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk 0x70UL 179 /* TCPWM_GRP_CNT.DT */ 180 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Pos 0UL 181 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Msk 0xFFUL 182 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Pos 8UL 183 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Msk 0xFF00UL 184 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Pos 16UL 185 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Msk 0xFFFF0000UL 186 /* TCPWM_GRP_CNT.TR_CMD */ 187 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Pos 0UL 188 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Msk 0x1UL 189 #define TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Pos 2UL 190 #define TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Msk 0x4UL 191 #define TCPWM_GRP_CNT_V2_TR_CMD_STOP_Pos 3UL 192 #define TCPWM_GRP_CNT_V2_TR_CMD_STOP_Msk 0x8UL 193 #define TCPWM_GRP_CNT_V2_TR_CMD_START_Pos 4UL 194 #define TCPWM_GRP_CNT_V2_TR_CMD_START_Msk 0x10UL 195 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Pos 5UL 196 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Msk 0x20UL 197 /* TCPWM_GRP_CNT.TR_IN_SEL0 */ 198 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Pos 0UL 199 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Msk 0xFFUL 200 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Pos 8UL 201 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Msk 0xFF00UL 202 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Pos 16UL 203 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Msk 0xFF0000UL 204 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Pos 24UL 205 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Msk 0xFF000000UL 206 /* TCPWM_GRP_CNT.TR_IN_SEL1 */ 207 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Pos 0UL 208 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Msk 0xFFUL 209 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Pos 8UL 210 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Msk 0xFF00UL 211 /* TCPWM_GRP_CNT.TR_IN_EDGE_SEL */ 212 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos 0UL 213 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk 0x3UL 214 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Pos 2UL 215 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Msk 0xCUL 216 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos 4UL 217 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk 0x30UL 218 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Pos 6UL 219 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Msk 0xC0UL 220 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Pos 8UL 221 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Msk 0x300UL 222 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos 10UL 223 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk 0xC00UL 224 /* TCPWM_GRP_CNT.TR_PWM_CTRL */ 225 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Pos 0UL 226 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Msk 0x3UL 227 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Pos 2UL 228 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Msk 0xCUL 229 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Pos 4UL 230 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Msk 0x30UL 231 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Pos 6UL 232 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Msk 0xC0UL 233 /* TCPWM_GRP_CNT.TR_OUT_SEL */ 234 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Pos 0UL 235 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Msk 0x7UL 236 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Pos 4UL 237 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Msk 0x70UL 238 /* TCPWM_GRP_CNT.INTR */ 239 #define TCPWM_GRP_CNT_V2_INTR_TC_Pos 0UL 240 #define TCPWM_GRP_CNT_V2_INTR_TC_Msk 0x1UL 241 #define TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Pos 1UL 242 #define TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Msk 0x2UL 243 #define TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Pos 2UL 244 #define TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Msk 0x4UL 245 /* TCPWM_GRP_CNT.INTR_SET */ 246 #define TCPWM_GRP_CNT_V2_INTR_SET_TC_Pos 0UL 247 #define TCPWM_GRP_CNT_V2_INTR_SET_TC_Msk 0x1UL 248 #define TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Pos 1UL 249 #define TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Msk 0x2UL 250 #define TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Pos 2UL 251 #define TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Msk 0x4UL 252 /* TCPWM_GRP_CNT.INTR_MASK */ 253 #define TCPWM_GRP_CNT_V2_INTR_MASK_TC_Pos 0UL 254 #define TCPWM_GRP_CNT_V2_INTR_MASK_TC_Msk 0x1UL 255 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Pos 1UL 256 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Msk 0x2UL 257 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Pos 2UL 258 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Msk 0x4UL 259 /* TCPWM_GRP_CNT.INTR_MASKED */ 260 #define TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Pos 0UL 261 #define TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Msk 0x1UL 262 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Pos 1UL 263 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Msk 0x2UL 264 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Pos 2UL 265 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Msk 0x4UL 266 267 268 #endif /* _CYIP_TCPWM_V2_H_ */ 269 270 271 /* [] END OF FILE */ 272
