1 /***************************************************************************//** 2 * \file cyip_ipc.h 3 * 4 * \brief 5 * IPC IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_IPC_H_ 28 #define _CYIP_IPC_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * IPC 34 *******************************************************************************/ 35 36 #define IPC_STRUCT_SECTION_SIZE 0x00000020UL 37 #define IPC_INTR_STRUCT_SECTION_SIZE 0x00000020UL 38 #define IPC_SECTION_SIZE 0x00010000UL 39 40 /** 41 * \brief IPC structure (IPC_STRUCT) 42 */ 43 typedef struct { 44 __IM uint32_t ACQUIRE; /*!< 0x00000000 IPC acquire */ 45 __OM uint32_t RELEASE; /*!< 0x00000004 IPC release */ 46 __OM uint32_t NOTIFY; /*!< 0x00000008 IPC notification */ 47 __IOM uint32_t DATA; /*!< 0x0000000C IPC data */ 48 __IM uint32_t LOCK_STATUS; /*!< 0x00000010 IPC lock status */ 49 __IM uint32_t RESERVED[3]; 50 } IPC_STRUCT_V1_Type; /*!< Size = 32 (0x20) */ 51 52 /** 53 * \brief IPC interrupt structure (IPC_INTR_STRUCT) 54 */ 55 typedef struct { 56 __IOM uint32_t INTR; /*!< 0x00000000 Interrupt */ 57 __IOM uint32_t INTR_SET; /*!< 0x00000004 Interrupt set */ 58 __IOM uint32_t INTR_MASK; /*!< 0x00000008 Interrupt mask */ 59 __IM uint32_t INTR_MASKED; /*!< 0x0000000C Interrupt masked */ 60 __IM uint32_t RESERVED[4]; 61 } IPC_INTR_STRUCT_V1_Type; /*!< Size = 32 (0x20) */ 62 63 /** 64 * \brief IPC (IPC) 65 */ 66 typedef struct { 67 IPC_STRUCT_V1_Type STRUCT[16]; /*!< 0x00000000 IPC structure */ 68 __IM uint32_t RESERVED[896]; 69 IPC_INTR_STRUCT_V1_Type INTR_STRUCT[16]; /*!< 0x00001000 IPC interrupt structure */ 70 } IPC_V1_Type; /*!< Size = 4608 (0x1200) */ 71 72 73 /* IPC_STRUCT.ACQUIRE */ 74 #define IPC_STRUCT_ACQUIRE_P_Pos 0UL 75 #define IPC_STRUCT_ACQUIRE_P_Msk 0x1UL 76 #define IPC_STRUCT_ACQUIRE_NS_Pos 1UL 77 #define IPC_STRUCT_ACQUIRE_NS_Msk 0x2UL 78 #define IPC_STRUCT_ACQUIRE_PC_Pos 4UL 79 #define IPC_STRUCT_ACQUIRE_PC_Msk 0xF0UL 80 #define IPC_STRUCT_ACQUIRE_MS_Pos 8UL 81 #define IPC_STRUCT_ACQUIRE_MS_Msk 0xF00UL 82 #define IPC_STRUCT_ACQUIRE_SUCCESS_Pos 31UL 83 #define IPC_STRUCT_ACQUIRE_SUCCESS_Msk 0x80000000UL 84 /* IPC_STRUCT.RELEASE */ 85 #define IPC_STRUCT_RELEASE_INTR_RELEASE_Pos 0UL 86 #define IPC_STRUCT_RELEASE_INTR_RELEASE_Msk 0xFFFFUL 87 /* IPC_STRUCT.NOTIFY */ 88 #define IPC_STRUCT_NOTIFY_INTR_NOTIFY_Pos 0UL 89 #define IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk 0xFFFFUL 90 /* IPC_STRUCT.DATA */ 91 #define IPC_STRUCT_DATA_DATA_Pos 0UL 92 #define IPC_STRUCT_DATA_DATA_Msk 0xFFFFFFFFUL 93 /* IPC_STRUCT.LOCK_STATUS */ 94 #define IPC_STRUCT_LOCK_STATUS_P_Pos 0UL 95 #define IPC_STRUCT_LOCK_STATUS_P_Msk 0x1UL 96 #define IPC_STRUCT_LOCK_STATUS_NS_Pos 1UL 97 #define IPC_STRUCT_LOCK_STATUS_NS_Msk 0x2UL 98 #define IPC_STRUCT_LOCK_STATUS_PC_Pos 4UL 99 #define IPC_STRUCT_LOCK_STATUS_PC_Msk 0xF0UL 100 #define IPC_STRUCT_LOCK_STATUS_MS_Pos 8UL 101 #define IPC_STRUCT_LOCK_STATUS_MS_Msk 0xF00UL 102 #define IPC_STRUCT_LOCK_STATUS_ACQUIRED_Pos 31UL 103 #define IPC_STRUCT_LOCK_STATUS_ACQUIRED_Msk 0x80000000UL 104 105 106 /* IPC_INTR_STRUCT.INTR */ 107 #define IPC_INTR_STRUCT_INTR_RELEASE_Pos 0UL 108 #define IPC_INTR_STRUCT_INTR_RELEASE_Msk 0xFFFFUL 109 #define IPC_INTR_STRUCT_INTR_NOTIFY_Pos 16UL 110 #define IPC_INTR_STRUCT_INTR_NOTIFY_Msk 0xFFFF0000UL 111 /* IPC_INTR_STRUCT.INTR_SET */ 112 #define IPC_INTR_STRUCT_INTR_SET_RELEASE_Pos 0UL 113 #define IPC_INTR_STRUCT_INTR_SET_RELEASE_Msk 0xFFFFUL 114 #define IPC_INTR_STRUCT_INTR_SET_NOTIFY_Pos 16UL 115 #define IPC_INTR_STRUCT_INTR_SET_NOTIFY_Msk 0xFFFF0000UL 116 /* IPC_INTR_STRUCT.INTR_MASK */ 117 #define IPC_INTR_STRUCT_INTR_MASK_RELEASE_Pos 0UL 118 #define IPC_INTR_STRUCT_INTR_MASK_RELEASE_Msk 0xFFFFUL 119 #define IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Pos 16UL 120 #define IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Msk 0xFFFF0000UL 121 /* IPC_INTR_STRUCT.INTR_MASKED */ 122 #define IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Pos 0UL 123 #define IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Msk 0xFFFFUL 124 #define IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Pos 16UL 125 #define IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Msk 0xFFFF0000UL 126 127 128 #endif /* _CYIP_IPC_H_ */ 129 130 131 /* [] END OF FILE */ 132
