1 /***************************************************************************//** 2 * \file cyip_hsiom.h 3 * 4 * \brief 5 * HSIOM IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_HSIOM_H_ 28 #define _CYIP_HSIOM_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * HSIOM 34 *******************************************************************************/ 35 36 #define HSIOM_PRT_SECTION_SIZE 0x00000010UL 37 #define HSIOM_SECTION_SIZE 0x00004000UL 38 39 /** 40 * \brief HSIOM port registers (HSIOM_PRT) 41 */ 42 typedef struct { 43 __IOM uint32_t PORT_SEL0; /*!< 0x00000000 Port selection 0 */ 44 __IOM uint32_t PORT_SEL1; /*!< 0x00000004 Port selection 1 */ 45 __IM uint32_t RESERVED[2]; 46 } HSIOM_PRT_V1_Type; /*!< Size = 16 (0x10) */ 47 48 /** 49 * \brief High Speed IO Matrix (HSIOM) (HSIOM) 50 */ 51 typedef struct { 52 HSIOM_PRT_V1_Type PRT[128]; /*!< 0x00000000 HSIOM port registers */ 53 __IM uint32_t RESERVED[1536]; 54 __IOM uint32_t AMUX_SPLIT_CTL[64]; /*!< 0x00002000 AMUX splitter cell control */ 55 } HSIOM_V1_Type; /*!< Size = 8448 (0x2100) */ 56 57 58 /* HSIOM_PRT.PORT_SEL0 */ 59 #define HSIOM_PRT_PORT_SEL0_IO0_SEL_Pos 0UL 60 #define HSIOM_PRT_PORT_SEL0_IO0_SEL_Msk 0x1FUL 61 #define HSIOM_PRT_PORT_SEL0_IO1_SEL_Pos 8UL 62 #define HSIOM_PRT_PORT_SEL0_IO1_SEL_Msk 0x1F00UL 63 #define HSIOM_PRT_PORT_SEL0_IO2_SEL_Pos 16UL 64 #define HSIOM_PRT_PORT_SEL0_IO2_SEL_Msk 0x1F0000UL 65 #define HSIOM_PRT_PORT_SEL0_IO3_SEL_Pos 24UL 66 #define HSIOM_PRT_PORT_SEL0_IO3_SEL_Msk 0x1F000000UL 67 /* HSIOM_PRT.PORT_SEL1 */ 68 #define HSIOM_PRT_PORT_SEL1_IO4_SEL_Pos 0UL 69 #define HSIOM_PRT_PORT_SEL1_IO4_SEL_Msk 0x1FUL 70 #define HSIOM_PRT_PORT_SEL1_IO5_SEL_Pos 8UL 71 #define HSIOM_PRT_PORT_SEL1_IO5_SEL_Msk 0x1F00UL 72 #define HSIOM_PRT_PORT_SEL1_IO6_SEL_Pos 16UL 73 #define HSIOM_PRT_PORT_SEL1_IO6_SEL_Msk 0x1F0000UL 74 #define HSIOM_PRT_PORT_SEL1_IO7_SEL_Pos 24UL 75 #define HSIOM_PRT_PORT_SEL1_IO7_SEL_Msk 0x1F000000UL 76 77 78 /* HSIOM.AMUX_SPLIT_CTL */ 79 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos 0UL 80 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk 0x1UL 81 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Pos 1UL 82 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk 0x2UL 83 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Pos 2UL 84 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Msk 0x4UL 85 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos 4UL 86 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk 0x10UL 87 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Pos 5UL 88 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk 0x20UL 89 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Pos 6UL 90 #define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Msk 0x40UL 91 92 93 #endif /* _CYIP_HSIOM_H_ */ 94 95 96 /* [] END OF FILE */ 97
