1 /***************************************************************************//** 2 * \file cyip_flashc_v2_ect.h 3 * 4 * \brief 5 * FLASHC IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_FLASHC_V2_ECT_H_ 28 #define _CYIP_FLASHC_V2_ECT_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * FLASHC 34 *******************************************************************************/ 35 36 #define FLASHC_FM_CTL_ECT_V2_SECTION_SIZE 0x00001000UL 37 #define FLASHC_V2_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief Flash Macro Registers (FLASHC_FM_CTL_ECT) 41 */ 42 typedef struct { 43 __IOM uint32_t FM_CTL; /*!< 0x00000000 Flash Macro Control */ 44 __IOM uint32_t FM_CODE_MARGIN; /*!< 0x00000004 Flash Macro Margin Mode on Code Flash */ 45 __OM uint32_t FM_ADDR; /*!< 0x00000008 Flash Macro Address */ 46 __IM uint32_t RESERVED[5]; 47 __IOM uint32_t INTR; /*!< 0x00000020 Interrupt */ 48 __IOM uint32_t INTR_SET; /*!< 0x00000024 Interrupt Set */ 49 __IOM uint32_t INTR_MASK; /*!< 0x00000028 Interrupt Mask */ 50 __IM uint32_t INTR_MASKED; /*!< 0x0000002C Interrupt Masked */ 51 __OM uint32_t ECC_OVERRIDE; /*!< 0x00000030 ECC Data In override information and control bits */ 52 __IM uint32_t RESERVED1[3]; 53 __OM uint32_t FM_DATA; /*!< 0x00000040 Flash macro data_in[31 to 0] both Code and Work Flash */ 54 __IM uint32_t RESERVED2[8]; 55 __IOM uint32_t BOOKMARK; /*!< 0x00000064 Bookmark register - keeps the current FW HV seq */ 56 __IM uint32_t RESERVED3[230]; 57 __IOM uint32_t MAIN_FLASH_SAFETY; /*!< 0x00000400 Main (Code) Flash Security enable */ 58 __IM uint32_t STATUS; /*!< 0x00000404 Status read from Flash Macro */ 59 __IM uint32_t RESERVED4[62]; 60 __IOM uint32_t WORK_FLASH_SAFETY; /*!< 0x00000500 Work Flash Security enable */ 61 __IM uint32_t RESERVED5[703]; 62 } FLASHC_FM_CTL_ECT_V2_Type; /*!< Size = 4096 (0x1000) */ 63 64 /** 65 * \brief Flash controller (FLASHC) 66 */ 67 typedef struct { 68 __IOM uint32_t FLASH_CTL; /*!< 0x00000000 Control */ 69 __IOM uint32_t FLASH_PWR_CTL; /*!< 0x00000004 Flash power control */ 70 __IOM uint32_t FLASH_CMD; /*!< 0x00000008 Command */ 71 __IM uint32_t RESERVED[165]; 72 __IOM uint32_t ECC_CTL; /*!< 0x000002A0 ECC control */ 73 __IM uint32_t RESERVED1[3]; 74 __IOM uint32_t FM_SRAM_ECC_CTL0; /*!< 0x000002B0 eCT Flash SRAM ECC control 0 */ 75 __IOM uint32_t FM_SRAM_ECC_CTL1; /*!< 0x000002B4 eCT Flash SRAM ECC control 1 */ 76 __IM uint32_t FM_SRAM_ECC_CTL2; /*!< 0x000002B8 eCT Flash SRAM ECC control 2 */ 77 __IOM uint32_t FM_SRAM_ECC_CTL3; /*!< 0x000002BC eCT Flash SRAM ECC control 3 */ 78 __IM uint32_t RESERVED2[80]; 79 __IOM uint32_t CM0_CA_CTL0; /*!< 0x00000400 CM0+ cache control */ 80 __IOM uint32_t CM0_CA_CTL1; /*!< 0x00000404 CM0+ cache control */ 81 __IOM uint32_t CM0_CA_CTL2; /*!< 0x00000408 CM0+ cache control */ 82 __IM uint32_t RESERVED3[13]; 83 __IM uint32_t CM0_CA_STATUS0; /*!< 0x00000440 CM0+ cache status 0 */ 84 __IM uint32_t CM0_CA_STATUS1; /*!< 0x00000444 CM0+ cache status 1 */ 85 __IM uint32_t CM0_CA_STATUS2; /*!< 0x00000448 CM0+ cache status 2 */ 86 __IM uint32_t RESERVED4[5]; 87 __IOM uint32_t CM0_STATUS; /*!< 0x00000460 CM0+ interface status */ 88 __IM uint32_t RESERVED5[7]; 89 __IOM uint32_t CM4_CA_CTL0; /*!< 0x00000480 CM4 cache control */ 90 __IOM uint32_t CM4_CA_CTL1; /*!< 0x00000484 CM4 cache control */ 91 __IOM uint32_t CM4_CA_CTL2; /*!< 0x00000488 CM4 cache control */ 92 __IM uint32_t RESERVED6[13]; 93 __IM uint32_t CM4_CA_STATUS0; /*!< 0x000004C0 CM4 cache status 0 */ 94 __IM uint32_t CM4_CA_STATUS1; /*!< 0x000004C4 CM4 cache status 1 */ 95 __IM uint32_t CM4_CA_STATUS2; /*!< 0x000004C8 CM4 cache status 2 */ 96 __IM uint32_t RESERVED7[5]; 97 __IOM uint32_t CM4_STATUS; /*!< 0x000004E0 CM4 interface status */ 98 __IM uint32_t RESERVED8[7]; 99 __IOM uint32_t CRYPTO_BUFF_CTL; /*!< 0x00000500 Cryptography buffer control */ 100 __IM uint32_t RESERVED9[31]; 101 __IOM uint32_t DW0_BUFF_CTL; /*!< 0x00000580 Datawire 0 buffer control */ 102 __IM uint32_t RESERVED10[31]; 103 __IOM uint32_t DW1_BUFF_CTL; /*!< 0x00000600 Datawire 1 buffer control */ 104 __IM uint32_t RESERVED11[31]; 105 __IOM uint32_t DMAC_BUFF_CTL; /*!< 0x00000680 DMA controller buffer control */ 106 __IM uint32_t RESERVED12[31]; 107 __IOM uint32_t EXT_MS0_BUFF_CTL; /*!< 0x00000700 External master 0 buffer control */ 108 __IM uint32_t RESERVED13[31]; 109 __IOM uint32_t EXT_MS1_BUFF_CTL; /*!< 0x00000780 External master 1 buffer control */ 110 __IM uint32_t RESERVED14[14879]; 111 FLASHC_FM_CTL_ECT_V2_Type FM_CTL_ECT; /*!< 0x0000F000 Flash Macro Registers */ 112 } FLASHC_V2_Type; /*!< Size = 65536 (0x10000) */ 113 114 115 /* FLASHC_FM_CTL_ECT.FM_CTL */ 116 #define FLASHC_FM_CTL_ECT_V2_FM_CTL_FM_MODE_Pos 0UL 117 #define FLASHC_FM_CTL_ECT_V2_FM_CTL_FM_MODE_Msk 0x1FUL 118 #define FLASHC_FM_CTL_ECT_V2_FM_CTL_EMB_START_Pos 31UL 119 #define FLASHC_FM_CTL_ECT_V2_FM_CTL_EMB_START_Msk 0x80000000UL 120 /* FLASHC_FM_CTL_ECT.FM_CODE_MARGIN */ 121 #define FLASHC_FM_CTL_ECT_V2_FM_CODE_MARGIN_MARGIN_DCS_TRIM_Pos 0UL 122 #define FLASHC_FM_CTL_ECT_V2_FM_CODE_MARGIN_MARGIN_DCS_TRIM_Msk 0x1FFUL 123 #define FLASHC_FM_CTL_ECT_V2_FM_CODE_MARGIN_MARGIN_DCS_TRIM_EN_Pos 9UL 124 #define FLASHC_FM_CTL_ECT_V2_FM_CODE_MARGIN_MARGIN_DCS_TRIM_EN_Msk 0x200UL 125 #define FLASHC_FM_CTL_ECT_V2_FM_CODE_MARGIN_MARGIN_RDREG_TRIM_Pos 10UL 126 #define FLASHC_FM_CTL_ECT_V2_FM_CODE_MARGIN_MARGIN_RDREG_TRIM_Msk 0xFC00UL 127 #define FLASHC_FM_CTL_ECT_V2_FM_CODE_MARGIN_MARGIN_PGM_ERS_B_Pos 29UL 128 #define FLASHC_FM_CTL_ECT_V2_FM_CODE_MARGIN_MARGIN_PGM_ERS_B_Msk 0x20000000UL 129 #define FLASHC_FM_CTL_ECT_V2_FM_CODE_MARGIN_MARGIN_MODE_RDREG_CHNG_EN_Pos 30UL 130 #define FLASHC_FM_CTL_ECT_V2_FM_CODE_MARGIN_MARGIN_MODE_RDREG_CHNG_EN_Msk 0x40000000UL 131 #define FLASHC_FM_CTL_ECT_V2_FM_CODE_MARGIN_MARGIN_MODE_EN_Pos 31UL 132 #define FLASHC_FM_CTL_ECT_V2_FM_CODE_MARGIN_MARGIN_MODE_EN_Msk 0x80000000UL 133 /* FLASHC_FM_CTL_ECT.FM_ADDR */ 134 #define FLASHC_FM_CTL_ECT_V2_FM_ADDR_FM_ADDR_Pos 0UL 135 #define FLASHC_FM_CTL_ECT_V2_FM_ADDR_FM_ADDR_Msk 0xFFFFFFFFUL 136 /* FLASHC_FM_CTL_ECT.INTR */ 137 #define FLASHC_FM_CTL_ECT_V2_INTR_INTR_Pos 0UL 138 #define FLASHC_FM_CTL_ECT_V2_INTR_INTR_Msk 0x1UL 139 /* FLASHC_FM_CTL_ECT.INTR_SET */ 140 #define FLASHC_FM_CTL_ECT_V2_INTR_SET_INTR_SET_Pos 0UL 141 #define FLASHC_FM_CTL_ECT_V2_INTR_SET_INTR_SET_Msk 0x1UL 142 /* FLASHC_FM_CTL_ECT.INTR_MASK */ 143 #define FLASHC_FM_CTL_ECT_V2_INTR_MASK_INTR_MASK_Pos 0UL 144 #define FLASHC_FM_CTL_ECT_V2_INTR_MASK_INTR_MASK_Msk 0x1UL 145 /* FLASHC_FM_CTL_ECT.INTR_MASKED */ 146 #define FLASHC_FM_CTL_ECT_V2_INTR_MASKED_INTR_MASKED_Pos 0UL 147 #define FLASHC_FM_CTL_ECT_V2_INTR_MASKED_INTR_MASKED_Msk 0x1UL 148 /* FLASHC_FM_CTL_ECT.ECC_OVERRIDE */ 149 #define FLASHC_FM_CTL_ECT_V2_ECC_OVERRIDE_ECC_OVERRIDE_SYNDROME_Pos 0UL 150 #define FLASHC_FM_CTL_ECT_V2_ECC_OVERRIDE_ECC_OVERRIDE_SYNDROME_Msk 0xFFUL 151 #define FLASHC_FM_CTL_ECT_V2_ECC_OVERRIDE_ECC_OVERRIDE_WORK_Pos 30UL 152 #define FLASHC_FM_CTL_ECT_V2_ECC_OVERRIDE_ECC_OVERRIDE_WORK_Msk 0x40000000UL 153 #define FLASHC_FM_CTL_ECT_V2_ECC_OVERRIDE_ECC_OVERRIDE_CODE_Pos 31UL 154 #define FLASHC_FM_CTL_ECT_V2_ECC_OVERRIDE_ECC_OVERRIDE_CODE_Msk 0x80000000UL 155 /* FLASHC_FM_CTL_ECT.FM_DATA */ 156 #define FLASHC_FM_CTL_ECT_V2_FM_DATA_FM_DATA_Pos 0UL 157 #define FLASHC_FM_CTL_ECT_V2_FM_DATA_FM_DATA_Msk 0xFFFFFFFFUL 158 /* FLASHC_FM_CTL_ECT.BOOKMARK */ 159 #define FLASHC_FM_CTL_ECT_V2_BOOKMARK_BOOKMARK_Pos 0UL 160 #define FLASHC_FM_CTL_ECT_V2_BOOKMARK_BOOKMARK_Msk 0xFFFFFFFFUL 161 /* FLASHC_FM_CTL_ECT.MAIN_FLASH_SAFETY */ 162 #define FLASHC_FM_CTL_ECT_V2_MAIN_FLASH_SAFETY_MAINFLASHWRITEENABLE_Pos 0UL 163 #define FLASHC_FM_CTL_ECT_V2_MAIN_FLASH_SAFETY_MAINFLASHWRITEENABLE_Msk 0x1UL 164 /* FLASHC_FM_CTL_ECT.STATUS */ 165 #define FLASHC_FM_CTL_ECT_V2_STATUS_PGM_CODE_Pos 0UL 166 #define FLASHC_FM_CTL_ECT_V2_STATUS_PGM_CODE_Msk 0x1UL 167 #define FLASHC_FM_CTL_ECT_V2_STATUS_PGM_WORK_Pos 1UL 168 #define FLASHC_FM_CTL_ECT_V2_STATUS_PGM_WORK_Msk 0x2UL 169 #define FLASHC_FM_CTL_ECT_V2_STATUS_ERASE_CODE_Pos 2UL 170 #define FLASHC_FM_CTL_ECT_V2_STATUS_ERASE_CODE_Msk 0x4UL 171 #define FLASHC_FM_CTL_ECT_V2_STATUS_ERASE_WORK_Pos 3UL 172 #define FLASHC_FM_CTL_ECT_V2_STATUS_ERASE_WORK_Msk 0x8UL 173 #define FLASHC_FM_CTL_ECT_V2_STATUS_ERS_SUSPEND_Pos 4UL 174 #define FLASHC_FM_CTL_ECT_V2_STATUS_ERS_SUSPEND_Msk 0x10UL 175 #define FLASHC_FM_CTL_ECT_V2_STATUS_BLANK_CHECK_WORK_Pos 5UL 176 #define FLASHC_FM_CTL_ECT_V2_STATUS_BLANK_CHECK_WORK_Msk 0x20UL 177 #define FLASHC_FM_CTL_ECT_V2_STATUS_BLANK_CHCEK_PASS_Pos 6UL 178 #define FLASHC_FM_CTL_ECT_V2_STATUS_BLANK_CHCEK_PASS_Msk 0x40UL 179 #define FLASHC_FM_CTL_ECT_V2_STATUS_POR_1B_ECC_CORRECTED_Pos 27UL 180 #define FLASHC_FM_CTL_ECT_V2_STATUS_POR_1B_ECC_CORRECTED_Msk 0x8000000UL 181 #define FLASHC_FM_CTL_ECT_V2_STATUS_POR_2B_ECC_ERROR_Pos 28UL 182 #define FLASHC_FM_CTL_ECT_V2_STATUS_POR_2B_ECC_ERROR_Msk 0x10000000UL 183 #define FLASHC_FM_CTL_ECT_V2_STATUS_NATIVE_POR_Pos 29UL 184 #define FLASHC_FM_CTL_ECT_V2_STATUS_NATIVE_POR_Msk 0x20000000UL 185 #define FLASHC_FM_CTL_ECT_V2_STATUS_HANG_Pos 30UL 186 #define FLASHC_FM_CTL_ECT_V2_STATUS_HANG_Msk 0x40000000UL 187 #define FLASHC_FM_CTL_ECT_V2_STATUS_BUSY_Pos 31UL 188 #define FLASHC_FM_CTL_ECT_V2_STATUS_BUSY_Msk 0x80000000UL 189 /* FLASHC_FM_CTL_ECT.WORK_FLASH_SAFETY */ 190 #define FLASHC_FM_CTL_ECT_V2_WORK_FLASH_SAFETY_WORKFLASHWRITEENABLE_Pos 0UL 191 #define FLASHC_FM_CTL_ECT_V2_WORK_FLASH_SAFETY_WORKFLASHWRITEENABLE_Msk 0x1UL 192 193 194 /* FLASHC.FLASH_CTL */ 195 #define FLASHC_V2_FLASH_CTL_MAIN_WS_Pos 0UL 196 #define FLASHC_V2_FLASH_CTL_MAIN_WS_Msk 0xFUL 197 #define FLASHC_V2_FLASH_CTL_MAIN_MAP_Pos 8UL 198 #define FLASHC_V2_FLASH_CTL_MAIN_MAP_Msk 0x100UL 199 #define FLASHC_V2_FLASH_CTL_WORK_MAP_Pos 9UL 200 #define FLASHC_V2_FLASH_CTL_WORK_MAP_Msk 0x200UL 201 #define FLASHC_V2_FLASH_CTL_MAIN_BANK_MODE_Pos 12UL 202 #define FLASHC_V2_FLASH_CTL_MAIN_BANK_MODE_Msk 0x1000UL 203 #define FLASHC_V2_FLASH_CTL_WORK_BANK_MODE_Pos 13UL 204 #define FLASHC_V2_FLASH_CTL_WORK_BANK_MODE_Msk 0x2000UL 205 #define FLASHC_V2_FLASH_CTL_MAIN_ECC_EN_Pos 16UL 206 #define FLASHC_V2_FLASH_CTL_MAIN_ECC_EN_Msk 0x10000UL 207 #define FLASHC_V2_FLASH_CTL_MAIN_ECC_INJ_EN_Pos 17UL 208 #define FLASHC_V2_FLASH_CTL_MAIN_ECC_INJ_EN_Msk 0x20000UL 209 #define FLASHC_V2_FLASH_CTL_MAIN_ERR_SILENT_Pos 18UL 210 #define FLASHC_V2_FLASH_CTL_MAIN_ERR_SILENT_Msk 0x40000UL 211 #define FLASHC_V2_FLASH_CTL_WORK_ECC_EN_Pos 20UL 212 #define FLASHC_V2_FLASH_CTL_WORK_ECC_EN_Msk 0x100000UL 213 #define FLASHC_V2_FLASH_CTL_WORK_ECC_INJ_EN_Pos 21UL 214 #define FLASHC_V2_FLASH_CTL_WORK_ECC_INJ_EN_Msk 0x200000UL 215 #define FLASHC_V2_FLASH_CTL_WORK_ERR_SILENT_Pos 22UL 216 #define FLASHC_V2_FLASH_CTL_WORK_ERR_SILENT_Msk 0x400000UL 217 /* FLASHC.FLASH_PWR_CTL */ 218 #define FLASHC_V2_FLASH_PWR_CTL_ENABLE_Pos 0UL 219 #define FLASHC_V2_FLASH_PWR_CTL_ENABLE_Msk 0x1UL 220 #define FLASHC_V2_FLASH_PWR_CTL_ENABLE_HV_Pos 1UL 221 #define FLASHC_V2_FLASH_PWR_CTL_ENABLE_HV_Msk 0x2UL 222 /* FLASHC.FLASH_CMD */ 223 #define FLASHC_V2_FLASH_CMD_INV_Pos 0UL 224 #define FLASHC_V2_FLASH_CMD_INV_Msk 0x1UL 225 #define FLASHC_V2_FLASH_CMD_BUFF_INV_Pos 1UL 226 #define FLASHC_V2_FLASH_CMD_BUFF_INV_Msk 0x2UL 227 /* FLASHC.ECC_CTL */ 228 #define FLASHC_V2_ECC_CTL_WORD_ADDR_Pos 0UL 229 #define FLASHC_V2_ECC_CTL_WORD_ADDR_Msk 0xFFFFFFUL 230 #define FLASHC_V2_ECC_CTL_PARITY_Pos 24UL 231 #define FLASHC_V2_ECC_CTL_PARITY_Msk 0xFF000000UL 232 /* FLASHC.FM_SRAM_ECC_CTL0 */ 233 #define FLASHC_V2_FM_SRAM_ECC_CTL0_ECC_INJ_DATA_Pos 0UL 234 #define FLASHC_V2_FM_SRAM_ECC_CTL0_ECC_INJ_DATA_Msk 0xFFFFFFFFUL 235 /* FLASHC.FM_SRAM_ECC_CTL1 */ 236 #define FLASHC_V2_FM_SRAM_ECC_CTL1_ECC_INJ_PARITY_Pos 0UL 237 #define FLASHC_V2_FM_SRAM_ECC_CTL1_ECC_INJ_PARITY_Msk 0x7FUL 238 /* FLASHC.FM_SRAM_ECC_CTL2 */ 239 #define FLASHC_V2_FM_SRAM_ECC_CTL2_CORRECTED_DATA_Pos 0UL 240 #define FLASHC_V2_FM_SRAM_ECC_CTL2_CORRECTED_DATA_Msk 0xFFFFFFFFUL 241 /* FLASHC.FM_SRAM_ECC_CTL3 */ 242 #define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_ENABLE_Pos 0UL 243 #define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_ENABLE_Msk 0x1UL 244 #define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_INJ_EN_Pos 4UL 245 #define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_INJ_EN_Msk 0x10UL 246 #define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_TEST_FAIL_Pos 8UL 247 #define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_TEST_FAIL_Msk 0x100UL 248 /* FLASHC.CM0_CA_CTL0 */ 249 #define FLASHC_V2_CM0_CA_CTL0_RAM_ECC_EN_Pos 0UL 250 #define FLASHC_V2_CM0_CA_CTL0_RAM_ECC_EN_Msk 0x1UL 251 #define FLASHC_V2_CM0_CA_CTL0_RAM_ECC_INJ_EN_Pos 1UL 252 #define FLASHC_V2_CM0_CA_CTL0_RAM_ECC_INJ_EN_Msk 0x2UL 253 #define FLASHC_V2_CM0_CA_CTL0_WAY_Pos 16UL 254 #define FLASHC_V2_CM0_CA_CTL0_WAY_Msk 0x30000UL 255 #define FLASHC_V2_CM0_CA_CTL0_SET_ADDR_Pos 24UL 256 #define FLASHC_V2_CM0_CA_CTL0_SET_ADDR_Msk 0x7000000UL 257 #define FLASHC_V2_CM0_CA_CTL0_PREF_EN_Pos 30UL 258 #define FLASHC_V2_CM0_CA_CTL0_PREF_EN_Msk 0x40000000UL 259 #define FLASHC_V2_CM0_CA_CTL0_CA_EN_Pos 31UL 260 #define FLASHC_V2_CM0_CA_CTL0_CA_EN_Msk 0x80000000UL 261 /* FLASHC.CM0_CA_CTL1 */ 262 #define FLASHC_V2_CM0_CA_CTL1_PWR_MODE_Pos 0UL 263 #define FLASHC_V2_CM0_CA_CTL1_PWR_MODE_Msk 0x3UL 264 #define FLASHC_V2_CM0_CA_CTL1_VECTKEYSTAT_Pos 16UL 265 #define FLASHC_V2_CM0_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL 266 /* FLASHC.CM0_CA_CTL2 */ 267 #define FLASHC_V2_CM0_CA_CTL2_PWRUP_DELAY_Pos 0UL 268 #define FLASHC_V2_CM0_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL 269 /* FLASHC.CM0_CA_STATUS0 */ 270 #define FLASHC_V2_CM0_CA_STATUS0_VALID32_Pos 0UL 271 #define FLASHC_V2_CM0_CA_STATUS0_VALID32_Msk 0xFFFFFFFFUL 272 /* FLASHC.CM0_CA_STATUS1 */ 273 #define FLASHC_V2_CM0_CA_STATUS1_TAG_Pos 0UL 274 #define FLASHC_V2_CM0_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL 275 /* FLASHC.CM0_CA_STATUS2 */ 276 #define FLASHC_V2_CM0_CA_STATUS2_LRU_Pos 0UL 277 #define FLASHC_V2_CM0_CA_STATUS2_LRU_Msk 0x3FUL 278 /* FLASHC.CM0_STATUS */ 279 #define FLASHC_V2_CM0_STATUS_MAIN_INTERNAL_ERR_Pos 0UL 280 #define FLASHC_V2_CM0_STATUS_MAIN_INTERNAL_ERR_Msk 0x1UL 281 #define FLASHC_V2_CM0_STATUS_WORK_INTERNAL_ERR_Pos 1UL 282 #define FLASHC_V2_CM0_STATUS_WORK_INTERNAL_ERR_Msk 0x2UL 283 /* FLASHC.CM4_CA_CTL0 */ 284 #define FLASHC_V2_CM4_CA_CTL0_RAM_ECC_EN_Pos 0UL 285 #define FLASHC_V2_CM4_CA_CTL0_RAM_ECC_EN_Msk 0x1UL 286 #define FLASHC_V2_CM4_CA_CTL0_RAM_ECC_INJ_EN_Pos 1UL 287 #define FLASHC_V2_CM4_CA_CTL0_RAM_ECC_INJ_EN_Msk 0x2UL 288 #define FLASHC_V2_CM4_CA_CTL0_WAY_Pos 16UL 289 #define FLASHC_V2_CM4_CA_CTL0_WAY_Msk 0x30000UL 290 #define FLASHC_V2_CM4_CA_CTL0_SET_ADDR_Pos 24UL 291 #define FLASHC_V2_CM4_CA_CTL0_SET_ADDR_Msk 0x7000000UL 292 #define FLASHC_V2_CM4_CA_CTL0_PREF_EN_Pos 30UL 293 #define FLASHC_V2_CM4_CA_CTL0_PREF_EN_Msk 0x40000000UL 294 #define FLASHC_V2_CM4_CA_CTL0_CA_EN_Pos 31UL 295 #define FLASHC_V2_CM4_CA_CTL0_CA_EN_Msk 0x80000000UL 296 /* FLASHC.CM4_CA_CTL1 */ 297 #define FLASHC_V2_CM4_CA_CTL1_PWR_MODE_Pos 0UL 298 #define FLASHC_V2_CM4_CA_CTL1_PWR_MODE_Msk 0x3UL 299 #define FLASHC_V2_CM4_CA_CTL1_VECTKEYSTAT_Pos 16UL 300 #define FLASHC_V2_CM4_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL 301 /* FLASHC.CM4_CA_CTL2 */ 302 #define FLASHC_V2_CM4_CA_CTL2_PWRUP_DELAY_Pos 0UL 303 #define FLASHC_V2_CM4_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL 304 /* FLASHC.CM4_CA_STATUS0 */ 305 #define FLASHC_V2_CM4_CA_STATUS0_VALID32_Pos 0UL 306 #define FLASHC_V2_CM4_CA_STATUS0_VALID32_Msk 0xFFFFFFFFUL 307 /* FLASHC.CM4_CA_STATUS1 */ 308 #define FLASHC_V2_CM4_CA_STATUS1_TAG_Pos 0UL 309 #define FLASHC_V2_CM4_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL 310 /* FLASHC.CM4_CA_STATUS2 */ 311 #define FLASHC_V2_CM4_CA_STATUS2_LRU_Pos 0UL 312 #define FLASHC_V2_CM4_CA_STATUS2_LRU_Msk 0x3FUL 313 /* FLASHC.CM4_STATUS */ 314 #define FLASHC_V2_CM4_STATUS_MAIN_INTERNAL_ERR_Pos 0UL 315 #define FLASHC_V2_CM4_STATUS_MAIN_INTERNAL_ERR_Msk 0x1UL 316 #define FLASHC_V2_CM4_STATUS_WORK_INTERNAL_ERR_Pos 1UL 317 #define FLASHC_V2_CM4_STATUS_WORK_INTERNAL_ERR_Msk 0x2UL 318 /* FLASHC.CRYPTO_BUFF_CTL */ 319 #define FLASHC_V2_CRYPTO_BUFF_CTL_PREF_EN_Pos 30UL 320 #define FLASHC_V2_CRYPTO_BUFF_CTL_PREF_EN_Msk 0x40000000UL 321 /* FLASHC.DW0_BUFF_CTL */ 322 #define FLASHC_V2_DW0_BUFF_CTL_PREF_EN_Pos 30UL 323 #define FLASHC_V2_DW0_BUFF_CTL_PREF_EN_Msk 0x40000000UL 324 /* FLASHC.DW1_BUFF_CTL */ 325 #define FLASHC_V2_DW1_BUFF_CTL_PREF_EN_Pos 30UL 326 #define FLASHC_V2_DW1_BUFF_CTL_PREF_EN_Msk 0x40000000UL 327 /* FLASHC.DMAC_BUFF_CTL */ 328 #define FLASHC_V2_DMAC_BUFF_CTL_PREF_EN_Pos 30UL 329 #define FLASHC_V2_DMAC_BUFF_CTL_PREF_EN_Msk 0x40000000UL 330 /* FLASHC.EXT_MS0_BUFF_CTL */ 331 #define FLASHC_V2_EXT_MS0_BUFF_CTL_PREF_EN_Pos 30UL 332 #define FLASHC_V2_EXT_MS0_BUFF_CTL_PREF_EN_Msk 0x40000000UL 333 /* FLASHC.EXT_MS1_BUFF_CTL */ 334 #define FLASHC_V2_EXT_MS1_BUFF_CTL_PREF_EN_Pos 30UL 335 #define FLASHC_V2_EXT_MS1_BUFF_CTL_PREF_EN_Msk 0x40000000UL 336 337 338 #endif /* _CYIP_FLASHC_V2_ECT_H_ */ 339 340 341 /* [] END OF FILE */ 342
