1 /***************************************************************************//** 2 * \file cyip_fault_v2.h 3 * 4 * \brief 5 * FAULT IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_FAULT_V2_H_ 28 #define _CYIP_FAULT_V2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * FAULT 34 *******************************************************************************/ 35 36 #define FAULT_STRUCT_V2_SECTION_SIZE 0x00000100UL 37 #define FAULT_V2_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief Fault structure (FAULT_STRUCT) 41 */ 42 typedef struct { 43 __IOM uint32_t CTL; /*!< 0x00000000 Fault control */ 44 __IM uint32_t RESERVED[2]; 45 __IOM uint32_t STATUS; /*!< 0x0000000C Fault status */ 46 __IOM uint32_t DATA[4]; /*!< 0x00000010 Fault data */ 47 __IM uint32_t RESERVED1[8]; 48 __IM uint32_t PENDING0; /*!< 0x00000040 Fault pending 0 */ 49 __IM uint32_t PENDING1; /*!< 0x00000044 Fault pending 1 */ 50 __IM uint32_t PENDING2; /*!< 0x00000048 Fault pending 2 */ 51 __IM uint32_t RESERVED2; 52 __IOM uint32_t MASK0; /*!< 0x00000050 Fault mask 0 */ 53 __IOM uint32_t MASK1; /*!< 0x00000054 Fault mask 1 */ 54 __IOM uint32_t MASK2; /*!< 0x00000058 Fault mask 2 */ 55 __IM uint32_t RESERVED3[25]; 56 __IOM uint32_t INTR; /*!< 0x000000C0 Interrupt */ 57 __IOM uint32_t INTR_SET; /*!< 0x000000C4 Interrupt set */ 58 __IOM uint32_t INTR_MASK; /*!< 0x000000C8 Interrupt mask */ 59 __IM uint32_t INTR_MASKED; /*!< 0x000000CC Interrupt masked */ 60 __IM uint32_t RESERVED4[12]; 61 } FAULT_STRUCT_V2_Type; /*!< Size = 256 (0x100) */ 62 63 /** 64 * \brief Fault structures (FAULT) 65 */ 66 typedef struct { 67 FAULT_STRUCT_V2_Type STRUCT[4]; /*!< 0x00000000 Fault structure */ 68 } FAULT_V2_Type; /*!< Size = 1024 (0x400) */ 69 70 71 /* FAULT_STRUCT.CTL */ 72 #define FAULT_STRUCT_V2_CTL_TR_EN_Pos 0UL 73 #define FAULT_STRUCT_V2_CTL_TR_EN_Msk 0x1UL 74 #define FAULT_STRUCT_V2_CTL_OUT_EN_Pos 1UL 75 #define FAULT_STRUCT_V2_CTL_OUT_EN_Msk 0x2UL 76 #define FAULT_STRUCT_V2_CTL_RESET_REQ_EN_Pos 2UL 77 #define FAULT_STRUCT_V2_CTL_RESET_REQ_EN_Msk 0x4UL 78 /* FAULT_STRUCT.STATUS */ 79 #define FAULT_STRUCT_V2_STATUS_IDX_Pos 0UL 80 #define FAULT_STRUCT_V2_STATUS_IDX_Msk 0x7FUL 81 #define FAULT_STRUCT_V2_STATUS_VALID_Pos 31UL 82 #define FAULT_STRUCT_V2_STATUS_VALID_Msk 0x80000000UL 83 /* FAULT_STRUCT.DATA */ 84 #define FAULT_STRUCT_V2_DATA_DATA_Pos 0UL 85 #define FAULT_STRUCT_V2_DATA_DATA_Msk 0xFFFFFFFFUL 86 /* FAULT_STRUCT.PENDING0 */ 87 #define FAULT_STRUCT_V2_PENDING0_SOURCE_Pos 0UL 88 #define FAULT_STRUCT_V2_PENDING0_SOURCE_Msk 0xFFFFFFFFUL 89 /* FAULT_STRUCT.PENDING1 */ 90 #define FAULT_STRUCT_V2_PENDING1_SOURCE_Pos 0UL 91 #define FAULT_STRUCT_V2_PENDING1_SOURCE_Msk 0xFFFFFFFFUL 92 /* FAULT_STRUCT.PENDING2 */ 93 #define FAULT_STRUCT_V2_PENDING2_SOURCE_Pos 0UL 94 #define FAULT_STRUCT_V2_PENDING2_SOURCE_Msk 0xFFFFFFFFUL 95 /* FAULT_STRUCT.MASK0 */ 96 #define FAULT_STRUCT_V2_MASK0_SOURCE_Pos 0UL 97 #define FAULT_STRUCT_V2_MASK0_SOURCE_Msk 0xFFFFFFFFUL 98 /* FAULT_STRUCT.MASK1 */ 99 #define FAULT_STRUCT_V2_MASK1_SOURCE_Pos 0UL 100 #define FAULT_STRUCT_V2_MASK1_SOURCE_Msk 0xFFFFFFFFUL 101 /* FAULT_STRUCT.MASK2 */ 102 #define FAULT_STRUCT_V2_MASK2_SOURCE_Pos 0UL 103 #define FAULT_STRUCT_V2_MASK2_SOURCE_Msk 0xFFFFFFFFUL 104 /* FAULT_STRUCT.INTR */ 105 #define FAULT_STRUCT_V2_INTR_FAULT_Pos 0UL 106 #define FAULT_STRUCT_V2_INTR_FAULT_Msk 0x1UL 107 /* FAULT_STRUCT.INTR_SET */ 108 #define FAULT_STRUCT_V2_INTR_SET_FAULT_Pos 0UL 109 #define FAULT_STRUCT_V2_INTR_SET_FAULT_Msk 0x1UL 110 /* FAULT_STRUCT.INTR_MASK */ 111 #define FAULT_STRUCT_V2_INTR_MASK_FAULT_Pos 0UL 112 #define FAULT_STRUCT_V2_INTR_MASK_FAULT_Msk 0x1UL 113 /* FAULT_STRUCT.INTR_MASKED */ 114 #define FAULT_STRUCT_V2_INTR_MASKED_FAULT_Pos 0UL 115 #define FAULT_STRUCT_V2_INTR_MASKED_FAULT_Msk 0x1UL 116 117 118 /** 119 * \brief Instances of Fault data register. 120 */ 121 typedef enum 122 { 123 CY_SYSFAULT_MPU_0 = 0, /* Bus master 0 MPU/SMPU. */ 124 CY_SYSFAULT_MPU_1 = 1, /* Bus master 1 MPU. See MPU_0 description. */ 125 CY_SYSFAULT_MPU_2 = 2, /* Bus master 2 MPU. See MPU_0 description. */ 126 CY_SYSFAULT_MPU_3 = 3, /* Bus master 3 MPU. See MPU_0 description. */ 127 CY_SYSFAULT_MPU_4 = 4, /* Bus master 4 MPU. See MPU_0 description. */ 128 CY_SYSFAULT_MPU_5 = 5, /* Bus master 5 MPU. See MPU_0 description. */ 129 CY_SYSFAULT_MPU_6 = 6, /* Bus master 6 MPU. See MPU_0 description. */ 130 CY_SYSFAULT_MPU_7 = 7, /* Bus master 7 MPU. See MPU_0 description. */ 131 CY_SYSFAULT_MPU_8 = 8, /* Bus master 8 MPU. See MPU_0 description. */ 132 CY_SYSFAULT_MPU_9 = 9, /* Bus master 9 MPU. See MPU_0 description. */ 133 CY_SYSFAULT_MPU_10 = 10, /* Bus master 10 MPU. See MPU_0 description. */ 134 CY_SYSFAULT_MPU_11 = 11, /* Bus master 11 MPU. See MPU_0 description. */ 135 CY_SYSFAULT_MPU_12 = 12, /* Bus master 12 MPU. See MPU_0 description. */ 136 CY_SYSFAULT_MPU_13 = 13, /* Bus master 13 MPU. See MPU_0 description. */ 137 CY_SYSFAULT_MPU_14 = 14, /* Bus master 14 MPU. See MPU_0 description. */ 138 CY_SYSFAULT_MPU_15 = 15, /* Bus master 15 MPU. See MPU_0 description. */ 139 CY_SYSFAULT_CM4_SYS_MPU = 16, /* CM4 system bus AHB-Lite interface MPU. See MPU_0 description. */ 140 CY_SYSFAULT_CM4_CODE_MPU = 17, /* CM4 code bus AHB-Lite interface MPU for non flash controller accesses. See MPU_0 description. */ 141 CY_SYSFAULT_CM4_CODE_FLASHC_MPU = 18, /* CM4 code bus AHB-Lite interface MPU for flash controller accesses. See MPU_0 description. */ 142 CY_SYSFAULT_MS_PPU_4 = 25, /* Peripheral interconnect, master interface 4 PPU. See MS_PPU_0 description. */ 143 CY_SYSFAULT_PERI_ECC = 26, /* Peripheral interconnect, protection structures SRAM, correctable ECC error: */ 144 CY_SYSFAULT_PERI_NC_ECC = 27, /* Peripheral interconnect, protection structures SRAM, non-correctable ECC error. See PERI_ECC description. */ 145 CY_SYSFAULT_MS_PPU_0 = 28, /* Peripheral interconnect, master interface 0 PPU. */ 146 CY_SYSFAULT_MS_PPU_1 = 29, /* Peripheral interconnect, master interface 1 PPU. See MS_PPU_0 description. */ 147 CY_SYSFAULT_MS_PPU_2 = 30, /* Peripheral interconnect, master interface 2 PPU. See MS_PPU_0 description. */ 148 CY_SYSFAULT_MS_PPU_3 = 31, /* Peripheral interconnect, master interface 3 PPU. See MS_PPU_0 description. */ 149 CY_SYSFAULT_GROUP_FAULT_0 = 32, /* Peripheral group 0 fault detection. */ 150 CY_SYSFAULT_GROUP_FAULT_1 = 33, /* Peripheral group 1 fault detection. See GROUP_FAULT_0 description. */ 151 CY_SYSFAULT_GROUP_FAULT_2 = 34, /* Peripheral group 2 fault detection. See GROUP_FAULT_0 description. */ 152 CY_SYSFAULT_GROUP_FAULT_3 = 35, /* Peripheral group 3 fault detection. See GROUP_FAULT_0 description. */ 153 CY_SYSFAULT_GROUP_FAULT_4 = 36, /* Peripheral group 4 fault detection. See GROUP_FAULT_0 description. */ 154 CY_SYSFAULT_GROUP_FAULT_5 = 37, /* Peripheral group 5 fault detection. See GROUP_FAULT_0 description. */ 155 CY_SYSFAULT_GROUP_FAULT_6 = 38, /* Peripheral group 6 fault detection. See GROUP_FAULT_0 description. */ 156 CY_SYSFAULT_GROUP_FAULT_7 = 39, /* Peripheral group 7 fault detection. See GROUP_FAULT_0 description. */ 157 CY_SYSFAULT_GROUP_FAULT_8 = 40, /* Peripheral group 8 fault detection. See GROUP_FAULT_0 description. */ 158 CY_SYSFAULT_GROUP_FAULT_9 = 41, /* Peripheral group 9 fault detection. See GROUP_FAULT_0 description. */ 159 CY_SYSFAULT_GROUP_FAULT_10 = 42, /* Peripheral group 10 fault detection. See GROUP_FAULT_0 description. */ 160 CY_SYSFAULT_GROUP_FAULT_11 = 43, /* Peripheral group 11 fault detection. See GROUP_FAULT_0 description. */ 161 CY_SYSFAULT_GROUP_FAULT_12 = 44, /* Peripheral group 12 fault detection. See GROUP_FAULT_0 description. */ 162 CY_SYSFAULT_GROUP_FAULT_13 = 45, /* Peripheral group 13 fault detection. See GROUP_FAULT_0 description. */ 163 CY_SYSFAULT_GROUP_FAULT_14 = 46, /* Peripheral group 14 fault detection. See GROUP_FAULT_0 description. */ 164 CY_SYSFAULT_GROUP_FAULT_15 = 47, /* Peripheral group 15 fault detection. See GROUP_FAULT_0 description. */ 165 CY_SYSFAULT_FLASHC_MAIN_BUS_ERROR = 48, /* Flash controller, main interface, bus error: */ 166 CY_SYSFAULT_FLASHC_MAIN_C_ECC = 49, /* Flash controller, main interface, correctable ECC error: */ 167 CY_SYSFAULT_FLASHC_MAIN_NC_ECC = 50, /* Flash controller, main interface, non-correctable ECC error. See FLASHC_MAIN_C_ECC description. */ 168 CY_SYSFAULT_FLASHC_WORK_BUS_ERROR = 51, /* Flash controller, work interface, bus error. */ 169 CY_SYSFAULT_FLASHC_WORK_C_ECC = 52, /* Flash controller, work interface, correctable ECC error: */ 170 CY_SYSFAULT_FLASHC_WORK_NC_ECC = 53, /* Flash controller, work interface, non-correctable ECC error. See FLASHC_WORK_C_ECC description. */ 171 CY_SYSFAULT_FLASHC_CM0_CA_C_ECC = 54, /* Flash controller, CM0+ cache, correctable ECC error: */ 172 CY_SYSFAULT_FLASHC_CM0_CA_NC_ECC = 55, /* Flash controller, CM0+ cache, non-correctable ECC error. See FLASHC_CM0_CA_C_ECC description. */ 173 CY_SYSFAULT_FLASHC_CM4_CA_C_ECC = 56, /* Flash controller, CM4 cache, correctable ECC error. See FLASHC_CM0_CA_C_ECC description. */ 174 CY_SYSFAULT_FLASHC_CM4_CA_NC_ECC = 57, /* Flash controller, CM4 cache, non-correctable ECC error. See FLASHC_CM0_CA_C_ECC description. */ 175 CY_SYSFAULT_RAMC0_C_ECC = 58, /* System SRAM 0 correctable ECC error: */ 176 CY_SYSFAULT_RAMC0_NC_ECC = 59, /* System SRAM 0 non-correctable ECC error. See RAMC0_C_ECC description. */ 177 CY_SYSFAULT_RAMC1_C_ECC = 60, /* System SRAM 1 correctable ECC error. See RAMC0_C_ECC description. */ 178 CY_SYSFAULT_RAMC1_NC_ECC = 61, /* System SRAM 1 non-correctable ECC error. See RAMC0_C_ECC description. */ 179 CY_SYSFAULT_RAMC2_C_ECC = 62, /* System SRAM 2 correctable ECC error. See RAMC0_C_ECC description. */ 180 CY_SYSFAULT_RAMC2_NC_ECC = 63, /* System SRAM 2 non-correctable ECC error. See RAMC0_C_ECC description. */ 181 CY_SYSFAULT_CRYPTO_C_ECC = 64, /* Cryptography SRAM correctable ECC error. */ 182 CY_SYSFAULT_CRYPTO_NC_ECC = 65, /* Cryptography SRAM non-correctable ECC error. See CRYPTO_C_ECC description. */ 183 CY_SYSFAULT_DW0_C_ECC = 70, /* DataWire 0 SRAM 1 correctable ECC error: */ 184 CY_SYSFAULT_DW0_NC_ECC = 71, /* DataWire 0 SRAM 1 non-correctable ECC error. See DW0_C_ECC description. */ 185 CY_SYSFAULT_DW1_C_ECC = 72, /* DataWire 1 SRAM 1 correctable ECC error. See DW0_C_ECC description. */ 186 CY_SYSFAULT_DW1_NC_ECC = 73, /* DataWire 1 SRAM 1 non-correctable ECC error. See DW0_C_ECC description. */ 187 CY_SYSFAULT_FM_SRAM_C_ECC = 74, /* eCT Flash SRAM (for embedded operations) correctable ECC error: */ 188 CY_SYSFAULT_FM_SRAM_NC_ECC = 75, /* eCT Flash SRAM non-correctable ECC error: See FM_SRAM_C_ECC description. */ 189 CY_SYSFAULT_CAN0_C_ECC = 80, /* CAN controller 0 MRAM correctable ECC error: */ 190 CY_SYSFAULT_CAN0_NC_ECC = 81, /* CAN controller 0 MRAM non-correctable ECC error: */ 191 CY_SYSFAULT_CAN1_C_ECC = 82, /* CAN controller 1 MRAM correctable ECC error. See CAN0_C_ECC description. */ 192 CY_SYSFAULT_CAN1_NC_ECC = 83, /* CAN controller 1 MRAM non-correctable ECC error. See CAN0_NC_ECC description. */ 193 CY_SYSFAULT_CAN2_C_ECC = 84, /* CAN controller 2 MRAM correctable ECC error. See CAN0_C_ECC description. */ 194 CY_SYSFAULT_CAN2_NC_ECC = 85, /* CAN controller 2 MRAM non-correctable ECC error. See CAN0_NC_ECC description. */ 195 CY_SYSFAULT_SRSS_CSV = 90, /* SRSS Clock SuperVisor (CSV) violation detected. Multiple CSV can detect a violation at the same time. */ 196 CY_SYSFAULT_SRSS_SSV = 91, /* SRSS Supply SuperVisor (SSV) violation detected. Multiple SSV can detect a violation at the same time. */ 197 CY_SYSFAULT_SRSS_MCWDT0 = 92, /* SRSS Multi-Counter Watch Dog Timer (MCWDT) #0 violation detected. Multiple counters can detect a violation at the same time. */ 198 CY_SYSFAULT_SRSS_MCWDT1 = 93, /* SRSS Multi-Counter Watch Dog Timer (MCWDT) #1 violation detected. See SRSS_MCWDT0 description. */ 199 CY_SYSFAULT_SRSS_MCWDT2 = 94, /* SRSS Multi-Counter Watch Dog Timer (MCWDT) #2 violation detected. See SRSS_MCWDT0 description. */ 200 CY_SYSFAULT_SRSS_MCWDT3 = 95, /* SRSS Multi-Counter Watch Dog Timer (MCWDT) #3 violation detected. See SRSS_MCWDT0 description. */ 201 CY_SYSFAULT_NO_FAULT = 96 202 } cy_en_SysFault_source_t; 203 204 #endif /* _CYIP_FAULT_V2_H_ */ 205 206 207 /* [] END OF FILE */ 208
