1 /***************************************************************************//** 2 * \file cyip_crypto_v2.h 3 * 4 * \brief 5 * CRYPTO IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_CRYPTO_V2_H_ 28 #define _CYIP_CRYPTO_V2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * CRYPTO 34 *******************************************************************************/ 35 36 #define CRYPTO_V2_SECTION_SIZE 0x00010000UL 37 38 /** 39 * \brief Cryptography component (CRYPTO) 40 */ 41 typedef struct { 42 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 43 __IM uint32_t RESERVED; 44 __IOM uint32_t RAM_PWR_CTL; /*!< 0x00000008 SRAM power control */ 45 __IOM uint32_t RAM_PWR_DELAY_CTL; /*!< 0x0000000C SRAM power delay control */ 46 __IOM uint32_t ECC_CTL; /*!< 0x00000010 ECC control */ 47 __IM uint32_t RESERVED1[3]; 48 __IM uint32_t ERROR_STATUS0; /*!< 0x00000020 Error status 0 */ 49 __IOM uint32_t ERROR_STATUS1; /*!< 0x00000024 Error status 1 */ 50 __IM uint32_t RESERVED2[54]; 51 __IOM uint32_t INTR; /*!< 0x00000100 Interrupt register */ 52 __IOM uint32_t INTR_SET; /*!< 0x00000104 Interrupt set register */ 53 __IOM uint32_t INTR_MASK; /*!< 0x00000108 Interrupt mask register */ 54 __IM uint32_t INTR_MASKED; /*!< 0x0000010C Interrupt masked register */ 55 __IM uint32_t RESERVED3[60]; 56 __IOM uint32_t PR_LFSR_CTL0; /*!< 0x00000200 Pseudo random LFSR control 0 */ 57 __IOM uint32_t PR_LFSR_CTL1; /*!< 0x00000204 Pseudo random LFSR control 1 */ 58 __IOM uint32_t PR_LFSR_CTL2; /*!< 0x00000208 Pseudo random LFSR control 2 */ 59 __IOM uint32_t PR_MAX_CTL; /*!< 0x0000020C Pseudo random maximum control */ 60 __IOM uint32_t PR_CMD; /*!< 0x00000210 Pseudo random command */ 61 __IM uint32_t RESERVED4; 62 __IOM uint32_t PR_RESULT; /*!< 0x00000218 Pseudo random result */ 63 __IM uint32_t RESERVED5[25]; 64 __IOM uint32_t TR_CTL0; /*!< 0x00000280 True random control 0 */ 65 __IOM uint32_t TR_CTL1; /*!< 0x00000284 True random control 1 */ 66 __IOM uint32_t TR_CTL2; /*!< 0x00000288 True random control 2 */ 67 __IM uint32_t TR_STATUS; /*!< 0x0000028C True random status */ 68 __IOM uint32_t TR_CMD; /*!< 0x00000290 True random command */ 69 __IM uint32_t RESERVED6; 70 __IOM uint32_t TR_RESULT; /*!< 0x00000298 True random result */ 71 __IM uint32_t RESERVED7; 72 __IOM uint32_t TR_GARO_CTL; /*!< 0x000002A0 True random GARO control */ 73 __IOM uint32_t TR_FIRO_CTL; /*!< 0x000002A4 True random FIRO control */ 74 __IM uint32_t RESERVED8[6]; 75 __IOM uint32_t TR_MON_CTL; /*!< 0x000002C0 True random monitor control */ 76 __IM uint32_t RESERVED9; 77 __IOM uint32_t TR_MON_CMD; /*!< 0x000002C8 True random monitor command */ 78 __IM uint32_t RESERVED10; 79 __IOM uint32_t TR_MON_RC_CTL; /*!< 0x000002D0 True random monitor RC control */ 80 __IM uint32_t RESERVED11; 81 __IM uint32_t TR_MON_RC_STATUS0; /*!< 0x000002D8 True random monitor RC status 0 */ 82 __IM uint32_t TR_MON_RC_STATUS1; /*!< 0x000002DC True random monitor RC status 1 */ 83 __IOM uint32_t TR_MON_AP_CTL; /*!< 0x000002E0 True random monitor AP control */ 84 __IM uint32_t RESERVED12; 85 __IM uint32_t TR_MON_AP_STATUS0; /*!< 0x000002E8 True random monitor AP status 0 */ 86 __IM uint32_t TR_MON_AP_STATUS1; /*!< 0x000002EC True random monitor AP status 1 */ 87 __IM uint32_t RESERVED13[837]; 88 __IM uint32_t STATUS; /*!< 0x00001004 Status */ 89 __IM uint32_t RESERVED14[14]; 90 __IOM uint32_t INSTR_FF_CTL; /*!< 0x00001040 Instruction FIFO control */ 91 __IM uint32_t INSTR_FF_STATUS; /*!< 0x00001044 Instruction FIFO status */ 92 __OM uint32_t INSTR_FF_WR; /*!< 0x00001048 Instruction FIFO write */ 93 __IM uint32_t RESERVED15[29]; 94 __IM uint32_t LOAD0_FF_STATUS; /*!< 0x000010C0 Load 0 FIFO status */ 95 __IM uint32_t RESERVED16[3]; 96 __IM uint32_t LOAD1_FF_STATUS; /*!< 0x000010D0 Load 1 FIFO status */ 97 __IM uint32_t RESERVED17[7]; 98 __IM uint32_t STORE_FF_STATUS; /*!< 0x000010F0 Store FIFO status */ 99 __IM uint32_t RESERVED18[3]; 100 __IOM uint32_t AES_CTL; /*!< 0x00001100 AES control */ 101 __IM uint32_t RESERVED19[31]; 102 __IOM uint32_t RESULT; /*!< 0x00001180 Result */ 103 __IM uint32_t RESERVED20[159]; 104 __IOM uint32_t CRC_CTL; /*!< 0x00001400 CRC control */ 105 __IM uint32_t RESERVED21[3]; 106 __IOM uint32_t CRC_DATA_CTL; /*!< 0x00001410 CRC data control */ 107 __IM uint32_t RESERVED22[3]; 108 __IOM uint32_t CRC_POL_CTL; /*!< 0x00001420 CRC polynomial control */ 109 __IM uint32_t RESERVED23[7]; 110 __IOM uint32_t CRC_REM_CTL; /*!< 0x00001440 CRC remainder control */ 111 __IM uint32_t RESERVED24; 112 __IM uint32_t CRC_REM_RESULT; /*!< 0x00001448 CRC remainder result */ 113 __IM uint32_t RESERVED25[13]; 114 __IOM uint32_t VU_CTL0; /*!< 0x00001480 Vector unit control 0 */ 115 __IOM uint32_t VU_CTL1; /*!< 0x00001484 Vector unit control 1 */ 116 __IOM uint32_t VU_CTL2; /*!< 0x00001488 Vector unit control 2 */ 117 __IM uint32_t RESERVED26; 118 __IM uint32_t VU_STATUS; /*!< 0x00001490 Vector unit status */ 119 __IM uint32_t RESERVED27[11]; 120 __IM uint32_t VU_RF_DATA[16]; /*!< 0x000014C0 Vector unit register-file */ 121 __IM uint32_t RESERVED28[704]; 122 __IOM uint32_t DEV_KEY_ADDR0_CTL; /*!< 0x00002000 Device key address 0 control */ 123 __IOM uint32_t DEV_KEY_ADDR0; /*!< 0x00002004 Device key address 0 */ 124 __IM uint32_t RESERVED29[6]; 125 __IOM uint32_t DEV_KEY_ADDR1_CTL; /*!< 0x00002020 Device key address 1 control */ 126 __IOM uint32_t DEV_KEY_ADDR1; /*!< 0x00002024 Device key address 1 control */ 127 __IM uint32_t RESERVED30[22]; 128 __IM uint32_t DEV_KEY_STATUS; /*!< 0x00002080 Device key status */ 129 __IM uint32_t RESERVED31[31]; 130 __IOM uint32_t DEV_KEY_CTL0; /*!< 0x00002100 Device key control 0 */ 131 __IM uint32_t RESERVED32[7]; 132 __IOM uint32_t DEV_KEY_CTL1; /*!< 0x00002120 Device key control 1 */ 133 __IM uint32_t RESERVED33[6071]; 134 __IOM uint32_t MEM_BUFF[8192]; /*!< 0x00008000 Memory buffer */ 135 } CRYPTO_V2_Type; /*!< Size = 65536 (0x10000) */ 136 137 138 /* CRYPTO.CTL */ 139 #define CRYPTO_V2_CTL_P_Pos 0UL 140 #define CRYPTO_V2_CTL_P_Msk 0x1UL 141 #define CRYPTO_V2_CTL_NS_Pos 1UL 142 #define CRYPTO_V2_CTL_NS_Msk 0x2UL 143 #define CRYPTO_V2_CTL_PC_Pos 4UL 144 #define CRYPTO_V2_CTL_PC_Msk 0xF0UL 145 #define CRYPTO_V2_CTL_ECC_EN_Pos 16UL 146 #define CRYPTO_V2_CTL_ECC_EN_Msk 0x10000UL 147 #define CRYPTO_V2_CTL_ECC_INJ_EN_Pos 17UL 148 #define CRYPTO_V2_CTL_ECC_INJ_EN_Msk 0x20000UL 149 #define CRYPTO_V2_CTL_ENABLED_Pos 31UL 150 #define CRYPTO_V2_CTL_ENABLED_Msk 0x80000000UL 151 /* CRYPTO.RAM_PWR_CTL */ 152 #define CRYPTO_V2_RAM_PWR_CTL_PWR_MODE_Pos 0UL 153 #define CRYPTO_V2_RAM_PWR_CTL_PWR_MODE_Msk 0x3UL 154 /* CRYPTO.RAM_PWR_DELAY_CTL */ 155 #define CRYPTO_V2_RAM_PWR_DELAY_CTL_UP_Pos 0UL 156 #define CRYPTO_V2_RAM_PWR_DELAY_CTL_UP_Msk 0x3FFUL 157 /* CRYPTO.ECC_CTL */ 158 #define CRYPTO_V2_ECC_CTL_WORD_ADDR_Pos 0UL 159 #define CRYPTO_V2_ECC_CTL_WORD_ADDR_Msk 0x1FFFUL 160 #define CRYPTO_V2_ECC_CTL_PARITY_Pos 25UL 161 #define CRYPTO_V2_ECC_CTL_PARITY_Msk 0xFE000000UL 162 /* CRYPTO.ERROR_STATUS0 */ 163 #define CRYPTO_V2_ERROR_STATUS0_DATA32_Pos 0UL 164 #define CRYPTO_V2_ERROR_STATUS0_DATA32_Msk 0xFFFFFFFFUL 165 /* CRYPTO.ERROR_STATUS1 */ 166 #define CRYPTO_V2_ERROR_STATUS1_DATA24_Pos 0UL 167 #define CRYPTO_V2_ERROR_STATUS1_DATA24_Msk 0xFFFFFFUL 168 #define CRYPTO_V2_ERROR_STATUS1_IDX_Pos 24UL 169 #define CRYPTO_V2_ERROR_STATUS1_IDX_Msk 0x7000000UL 170 #define CRYPTO_V2_ERROR_STATUS1_VALID_Pos 31UL 171 #define CRYPTO_V2_ERROR_STATUS1_VALID_Msk 0x80000000UL 172 /* CRYPTO.INTR */ 173 #define CRYPTO_V2_INTR_INSTR_FF_LEVEL_Pos 0UL 174 #define CRYPTO_V2_INTR_INSTR_FF_LEVEL_Msk 0x1UL 175 #define CRYPTO_V2_INTR_INSTR_FF_OVERFLOW_Pos 1UL 176 #define CRYPTO_V2_INTR_INSTR_FF_OVERFLOW_Msk 0x2UL 177 #define CRYPTO_V2_INTR_TR_INITIALIZED_Pos 2UL 178 #define CRYPTO_V2_INTR_TR_INITIALIZED_Msk 0x4UL 179 #define CRYPTO_V2_INTR_TR_DATA_AVAILABLE_Pos 3UL 180 #define CRYPTO_V2_INTR_TR_DATA_AVAILABLE_Msk 0x8UL 181 #define CRYPTO_V2_INTR_PR_DATA_AVAILABLE_Pos 4UL 182 #define CRYPTO_V2_INTR_PR_DATA_AVAILABLE_Msk 0x10UL 183 #define CRYPTO_V2_INTR_INSTR_OPC_ERROR_Pos 16UL 184 #define CRYPTO_V2_INTR_INSTR_OPC_ERROR_Msk 0x10000UL 185 #define CRYPTO_V2_INTR_INSTR_CC_ERROR_Pos 17UL 186 #define CRYPTO_V2_INTR_INSTR_CC_ERROR_Msk 0x20000UL 187 #define CRYPTO_V2_INTR_BUS_ERROR_Pos 18UL 188 #define CRYPTO_V2_INTR_BUS_ERROR_Msk 0x40000UL 189 #define CRYPTO_V2_INTR_TR_AP_DETECT_ERROR_Pos 19UL 190 #define CRYPTO_V2_INTR_TR_AP_DETECT_ERROR_Msk 0x80000UL 191 #define CRYPTO_V2_INTR_TR_RC_DETECT_ERROR_Pos 20UL 192 #define CRYPTO_V2_INTR_TR_RC_DETECT_ERROR_Msk 0x100000UL 193 #define CRYPTO_V2_INTR_INSTR_DEV_KEY_ERROR_Pos 21UL 194 #define CRYPTO_V2_INTR_INSTR_DEV_KEY_ERROR_Msk 0x200000UL 195 /* CRYPTO.INTR_SET */ 196 #define CRYPTO_V2_INTR_SET_INSTR_FF_LEVEL_Pos 0UL 197 #define CRYPTO_V2_INTR_SET_INSTR_FF_LEVEL_Msk 0x1UL 198 #define CRYPTO_V2_INTR_SET_INSTR_FF_OVERFLOW_Pos 1UL 199 #define CRYPTO_V2_INTR_SET_INSTR_FF_OVERFLOW_Msk 0x2UL 200 #define CRYPTO_V2_INTR_SET_TR_INITIALIZED_Pos 2UL 201 #define CRYPTO_V2_INTR_SET_TR_INITIALIZED_Msk 0x4UL 202 #define CRYPTO_V2_INTR_SET_TR_DATA_AVAILABLE_Pos 3UL 203 #define CRYPTO_V2_INTR_SET_TR_DATA_AVAILABLE_Msk 0x8UL 204 #define CRYPTO_V2_INTR_SET_PR_DATA_AVAILABLE_Pos 4UL 205 #define CRYPTO_V2_INTR_SET_PR_DATA_AVAILABLE_Msk 0x10UL 206 #define CRYPTO_V2_INTR_SET_INSTR_OPC_ERROR_Pos 16UL 207 #define CRYPTO_V2_INTR_SET_INSTR_OPC_ERROR_Msk 0x10000UL 208 #define CRYPTO_V2_INTR_SET_INSTR_CC_ERROR_Pos 17UL 209 #define CRYPTO_V2_INTR_SET_INSTR_CC_ERROR_Msk 0x20000UL 210 #define CRYPTO_V2_INTR_SET_BUS_ERROR_Pos 18UL 211 #define CRYPTO_V2_INTR_SET_BUS_ERROR_Msk 0x40000UL 212 #define CRYPTO_V2_INTR_SET_TR_AP_DETECT_ERROR_Pos 19UL 213 #define CRYPTO_V2_INTR_SET_TR_AP_DETECT_ERROR_Msk 0x80000UL 214 #define CRYPTO_V2_INTR_SET_TR_RC_DETECT_ERROR_Pos 20UL 215 #define CRYPTO_V2_INTR_SET_TR_RC_DETECT_ERROR_Msk 0x100000UL 216 #define CRYPTO_V2_INTR_SET_INSTR_DEV_KEY_ERROR_Pos 21UL 217 #define CRYPTO_V2_INTR_SET_INSTR_DEV_KEY_ERROR_Msk 0x200000UL 218 /* CRYPTO.INTR_MASK */ 219 #define CRYPTO_V2_INTR_MASK_INSTR_FF_LEVEL_Pos 0UL 220 #define CRYPTO_V2_INTR_MASK_INSTR_FF_LEVEL_Msk 0x1UL 221 #define CRYPTO_V2_INTR_MASK_INSTR_FF_OVERFLOW_Pos 1UL 222 #define CRYPTO_V2_INTR_MASK_INSTR_FF_OVERFLOW_Msk 0x2UL 223 #define CRYPTO_V2_INTR_MASK_TR_INITIALIZED_Pos 2UL 224 #define CRYPTO_V2_INTR_MASK_TR_INITIALIZED_Msk 0x4UL 225 #define CRYPTO_V2_INTR_MASK_TR_DATA_AVAILABLE_Pos 3UL 226 #define CRYPTO_V2_INTR_MASK_TR_DATA_AVAILABLE_Msk 0x8UL 227 #define CRYPTO_V2_INTR_MASK_PR_DATA_AVAILABLE_Pos 4UL 228 #define CRYPTO_V2_INTR_MASK_PR_DATA_AVAILABLE_Msk 0x10UL 229 #define CRYPTO_V2_INTR_MASK_INSTR_OPC_ERROR_Pos 16UL 230 #define CRYPTO_V2_INTR_MASK_INSTR_OPC_ERROR_Msk 0x10000UL 231 #define CRYPTO_V2_INTR_MASK_INSTR_CC_ERROR_Pos 17UL 232 #define CRYPTO_V2_INTR_MASK_INSTR_CC_ERROR_Msk 0x20000UL 233 #define CRYPTO_V2_INTR_MASK_BUS_ERROR_Pos 18UL 234 #define CRYPTO_V2_INTR_MASK_BUS_ERROR_Msk 0x40000UL 235 #define CRYPTO_V2_INTR_MASK_TR_AP_DETECT_ERROR_Pos 19UL 236 #define CRYPTO_V2_INTR_MASK_TR_AP_DETECT_ERROR_Msk 0x80000UL 237 #define CRYPTO_V2_INTR_MASK_TR_RC_DETECT_ERROR_Pos 20UL 238 #define CRYPTO_V2_INTR_MASK_TR_RC_DETECT_ERROR_Msk 0x100000UL 239 #define CRYPTO_V2_INTR_MASK_INSTR_DEV_KEY_ERROR_Pos 21UL 240 #define CRYPTO_V2_INTR_MASK_INSTR_DEV_KEY_ERROR_Msk 0x200000UL 241 /* CRYPTO.INTR_MASKED */ 242 #define CRYPTO_V2_INTR_MASKED_INSTR_FF_LEVEL_Pos 0UL 243 #define CRYPTO_V2_INTR_MASKED_INSTR_FF_LEVEL_Msk 0x1UL 244 #define CRYPTO_V2_INTR_MASKED_INSTR_FF_OVERFLOW_Pos 1UL 245 #define CRYPTO_V2_INTR_MASKED_INSTR_FF_OVERFLOW_Msk 0x2UL 246 #define CRYPTO_V2_INTR_MASKED_TR_INITIALIZED_Pos 2UL 247 #define CRYPTO_V2_INTR_MASKED_TR_INITIALIZED_Msk 0x4UL 248 #define CRYPTO_V2_INTR_MASKED_TR_DATA_AVAILABLE_Pos 3UL 249 #define CRYPTO_V2_INTR_MASKED_TR_DATA_AVAILABLE_Msk 0x8UL 250 #define CRYPTO_V2_INTR_MASKED_PR_DATA_AVAILABLE_Pos 4UL 251 #define CRYPTO_V2_INTR_MASKED_PR_DATA_AVAILABLE_Msk 0x10UL 252 #define CRYPTO_V2_INTR_MASKED_INSTR_OPC_ERROR_Pos 16UL 253 #define CRYPTO_V2_INTR_MASKED_INSTR_OPC_ERROR_Msk 0x10000UL 254 #define CRYPTO_V2_INTR_MASKED_INSTR_CC_ERROR_Pos 17UL 255 #define CRYPTO_V2_INTR_MASKED_INSTR_CC_ERROR_Msk 0x20000UL 256 #define CRYPTO_V2_INTR_MASKED_BUS_ERROR_Pos 18UL 257 #define CRYPTO_V2_INTR_MASKED_BUS_ERROR_Msk 0x40000UL 258 #define CRYPTO_V2_INTR_MASKED_TR_AP_DETECT_ERROR_Pos 19UL 259 #define CRYPTO_V2_INTR_MASKED_TR_AP_DETECT_ERROR_Msk 0x80000UL 260 #define CRYPTO_V2_INTR_MASKED_TR_RC_DETECT_ERROR_Pos 20UL 261 #define CRYPTO_V2_INTR_MASKED_TR_RC_DETECT_ERROR_Msk 0x100000UL 262 #define CRYPTO_V2_INTR_MASKED_INSTR_DEV_KEY_ERROR_Pos 21UL 263 #define CRYPTO_V2_INTR_MASKED_INSTR_DEV_KEY_ERROR_Msk 0x200000UL 264 /* CRYPTO.PR_LFSR_CTL0 */ 265 #define CRYPTO_V2_PR_LFSR_CTL0_LFSR32_Pos 0UL 266 #define CRYPTO_V2_PR_LFSR_CTL0_LFSR32_Msk 0xFFFFFFFFUL 267 /* CRYPTO.PR_LFSR_CTL1 */ 268 #define CRYPTO_V2_PR_LFSR_CTL1_LFSR31_Pos 0UL 269 #define CRYPTO_V2_PR_LFSR_CTL1_LFSR31_Msk 0x7FFFFFFFUL 270 /* CRYPTO.PR_LFSR_CTL2 */ 271 #define CRYPTO_V2_PR_LFSR_CTL2_LFSR29_Pos 0UL 272 #define CRYPTO_V2_PR_LFSR_CTL2_LFSR29_Msk 0x1FFFFFFFUL 273 /* CRYPTO.PR_MAX_CTL */ 274 #define CRYPTO_V2_PR_MAX_CTL_DATA32_Pos 0UL 275 #define CRYPTO_V2_PR_MAX_CTL_DATA32_Msk 0xFFFFFFFFUL 276 /* CRYPTO.PR_CMD */ 277 #define CRYPTO_V2_PR_CMD_START_Pos 0UL 278 #define CRYPTO_V2_PR_CMD_START_Msk 0x1UL 279 /* CRYPTO.PR_RESULT */ 280 #define CRYPTO_V2_PR_RESULT_DATA32_Pos 0UL 281 #define CRYPTO_V2_PR_RESULT_DATA32_Msk 0xFFFFFFFFUL 282 /* CRYPTO.TR_CTL0 */ 283 #define CRYPTO_V2_TR_CTL0_SAMPLE_CLOCK_DIV_Pos 0UL 284 #define CRYPTO_V2_TR_CTL0_SAMPLE_CLOCK_DIV_Msk 0xFFUL 285 #define CRYPTO_V2_TR_CTL0_RED_CLOCK_DIV_Pos 8UL 286 #define CRYPTO_V2_TR_CTL0_RED_CLOCK_DIV_Msk 0xFF00UL 287 #define CRYPTO_V2_TR_CTL0_INIT_DELAY_Pos 16UL 288 #define CRYPTO_V2_TR_CTL0_INIT_DELAY_Msk 0xFF0000UL 289 #define CRYPTO_V2_TR_CTL0_VON_NEUMANN_CORR_Pos 24UL 290 #define CRYPTO_V2_TR_CTL0_VON_NEUMANN_CORR_Msk 0x1000000UL 291 #define CRYPTO_V2_TR_CTL0_STOP_ON_AP_DETECT_Pos 28UL 292 #define CRYPTO_V2_TR_CTL0_STOP_ON_AP_DETECT_Msk 0x10000000UL 293 #define CRYPTO_V2_TR_CTL0_STOP_ON_RC_DETECT_Pos 29UL 294 #define CRYPTO_V2_TR_CTL0_STOP_ON_RC_DETECT_Msk 0x20000000UL 295 /* CRYPTO.TR_CTL1 */ 296 #define CRYPTO_V2_TR_CTL1_RO11_EN_Pos 0UL 297 #define CRYPTO_V2_TR_CTL1_RO11_EN_Msk 0x1UL 298 #define CRYPTO_V2_TR_CTL1_RO15_EN_Pos 1UL 299 #define CRYPTO_V2_TR_CTL1_RO15_EN_Msk 0x2UL 300 #define CRYPTO_V2_TR_CTL1_GARO15_EN_Pos 2UL 301 #define CRYPTO_V2_TR_CTL1_GARO15_EN_Msk 0x4UL 302 #define CRYPTO_V2_TR_CTL1_GARO31_EN_Pos 3UL 303 #define CRYPTO_V2_TR_CTL1_GARO31_EN_Msk 0x8UL 304 #define CRYPTO_V2_TR_CTL1_FIRO15_EN_Pos 4UL 305 #define CRYPTO_V2_TR_CTL1_FIRO15_EN_Msk 0x10UL 306 #define CRYPTO_V2_TR_CTL1_FIRO31_EN_Pos 5UL 307 #define CRYPTO_V2_TR_CTL1_FIRO31_EN_Msk 0x20UL 308 /* CRYPTO.TR_CTL2 */ 309 #define CRYPTO_V2_TR_CTL2_SIZE_Pos 0UL 310 #define CRYPTO_V2_TR_CTL2_SIZE_Msk 0x3FUL 311 /* CRYPTO.TR_STATUS */ 312 #define CRYPTO_V2_TR_STATUS_INITIALIZED_Pos 0UL 313 #define CRYPTO_V2_TR_STATUS_INITIALIZED_Msk 0x1UL 314 /* CRYPTO.TR_CMD */ 315 #define CRYPTO_V2_TR_CMD_START_Pos 0UL 316 #define CRYPTO_V2_TR_CMD_START_Msk 0x1UL 317 /* CRYPTO.TR_RESULT */ 318 #define CRYPTO_V2_TR_RESULT_DATA32_Pos 0UL 319 #define CRYPTO_V2_TR_RESULT_DATA32_Msk 0xFFFFFFFFUL 320 /* CRYPTO.TR_GARO_CTL */ 321 #define CRYPTO_V2_TR_GARO_CTL_POLYNOMIAL31_Pos 0UL 322 #define CRYPTO_V2_TR_GARO_CTL_POLYNOMIAL31_Msk 0x7FFFFFFFUL 323 /* CRYPTO.TR_FIRO_CTL */ 324 #define CRYPTO_V2_TR_FIRO_CTL_POLYNOMIAL31_Pos 0UL 325 #define CRYPTO_V2_TR_FIRO_CTL_POLYNOMIAL31_Msk 0x7FFFFFFFUL 326 /* CRYPTO.TR_MON_CTL */ 327 #define CRYPTO_V2_TR_MON_CTL_BITSTREAM_SEL_Pos 0UL 328 #define CRYPTO_V2_TR_MON_CTL_BITSTREAM_SEL_Msk 0x3UL 329 /* CRYPTO.TR_MON_CMD */ 330 #define CRYPTO_V2_TR_MON_CMD_START_AP_Pos 0UL 331 #define CRYPTO_V2_TR_MON_CMD_START_AP_Msk 0x1UL 332 #define CRYPTO_V2_TR_MON_CMD_START_RC_Pos 1UL 333 #define CRYPTO_V2_TR_MON_CMD_START_RC_Msk 0x2UL 334 /* CRYPTO.TR_MON_RC_CTL */ 335 #define CRYPTO_V2_TR_MON_RC_CTL_CUTOFF_COUNT8_Pos 0UL 336 #define CRYPTO_V2_TR_MON_RC_CTL_CUTOFF_COUNT8_Msk 0xFFUL 337 /* CRYPTO.TR_MON_RC_STATUS0 */ 338 #define CRYPTO_V2_TR_MON_RC_STATUS0_BIT_Pos 0UL 339 #define CRYPTO_V2_TR_MON_RC_STATUS0_BIT_Msk 0x1UL 340 /* CRYPTO.TR_MON_RC_STATUS1 */ 341 #define CRYPTO_V2_TR_MON_RC_STATUS1_REP_COUNT_Pos 0UL 342 #define CRYPTO_V2_TR_MON_RC_STATUS1_REP_COUNT_Msk 0xFFUL 343 /* CRYPTO.TR_MON_AP_CTL */ 344 #define CRYPTO_V2_TR_MON_AP_CTL_CUTOFF_COUNT16_Pos 0UL 345 #define CRYPTO_V2_TR_MON_AP_CTL_CUTOFF_COUNT16_Msk 0xFFFFUL 346 #define CRYPTO_V2_TR_MON_AP_CTL_WINDOW_SIZE_Pos 16UL 347 #define CRYPTO_V2_TR_MON_AP_CTL_WINDOW_SIZE_Msk 0xFFFF0000UL 348 /* CRYPTO.TR_MON_AP_STATUS0 */ 349 #define CRYPTO_V2_TR_MON_AP_STATUS0_BIT_Pos 0UL 350 #define CRYPTO_V2_TR_MON_AP_STATUS0_BIT_Msk 0x1UL 351 /* CRYPTO.TR_MON_AP_STATUS1 */ 352 #define CRYPTO_V2_TR_MON_AP_STATUS1_OCC_COUNT_Pos 0UL 353 #define CRYPTO_V2_TR_MON_AP_STATUS1_OCC_COUNT_Msk 0xFFFFUL 354 #define CRYPTO_V2_TR_MON_AP_STATUS1_WINDOW_INDEX_Pos 16UL 355 #define CRYPTO_V2_TR_MON_AP_STATUS1_WINDOW_INDEX_Msk 0xFFFF0000UL 356 /* CRYPTO.STATUS */ 357 #define CRYPTO_V2_STATUS_BUSY_Pos 31UL 358 #define CRYPTO_V2_STATUS_BUSY_Msk 0x80000000UL 359 /* CRYPTO.INSTR_FF_CTL */ 360 #define CRYPTO_V2_INSTR_FF_CTL_EVENT_LEVEL_Pos 0UL 361 #define CRYPTO_V2_INSTR_FF_CTL_EVENT_LEVEL_Msk 0x7UL 362 #define CRYPTO_V2_INSTR_FF_CTL_CLEAR_Pos 16UL 363 #define CRYPTO_V2_INSTR_FF_CTL_CLEAR_Msk 0x10000UL 364 #define CRYPTO_V2_INSTR_FF_CTL_BLOCK_Pos 17UL 365 #define CRYPTO_V2_INSTR_FF_CTL_BLOCK_Msk 0x20000UL 366 /* CRYPTO.INSTR_FF_STATUS */ 367 #define CRYPTO_V2_INSTR_FF_STATUS_USED_Pos 0UL 368 #define CRYPTO_V2_INSTR_FF_STATUS_USED_Msk 0xFUL 369 #define CRYPTO_V2_INSTR_FF_STATUS_EVENT_Pos 16UL 370 #define CRYPTO_V2_INSTR_FF_STATUS_EVENT_Msk 0x10000UL 371 /* CRYPTO.INSTR_FF_WR */ 372 #define CRYPTO_V2_INSTR_FF_WR_DATA32_Pos 0UL 373 #define CRYPTO_V2_INSTR_FF_WR_DATA32_Msk 0xFFFFFFFFUL 374 /* CRYPTO.LOAD0_FF_STATUS */ 375 #define CRYPTO_V2_LOAD0_FF_STATUS_USED5_Pos 0UL 376 #define CRYPTO_V2_LOAD0_FF_STATUS_USED5_Msk 0x1FUL 377 #define CRYPTO_V2_LOAD0_FF_STATUS_BUSY_Pos 31UL 378 #define CRYPTO_V2_LOAD0_FF_STATUS_BUSY_Msk 0x80000000UL 379 /* CRYPTO.LOAD1_FF_STATUS */ 380 #define CRYPTO_V2_LOAD1_FF_STATUS_USED5_Pos 0UL 381 #define CRYPTO_V2_LOAD1_FF_STATUS_USED5_Msk 0x1FUL 382 #define CRYPTO_V2_LOAD1_FF_STATUS_BUSY_Pos 31UL 383 #define CRYPTO_V2_LOAD1_FF_STATUS_BUSY_Msk 0x80000000UL 384 /* CRYPTO.STORE_FF_STATUS */ 385 #define CRYPTO_V2_STORE_FF_STATUS_USED5_Pos 0UL 386 #define CRYPTO_V2_STORE_FF_STATUS_USED5_Msk 0x1FUL 387 #define CRYPTO_V2_STORE_FF_STATUS_BUSY_Pos 31UL 388 #define CRYPTO_V2_STORE_FF_STATUS_BUSY_Msk 0x80000000UL 389 /* CRYPTO.AES_CTL */ 390 #define CRYPTO_V2_AES_CTL_KEY_SIZE_Pos 0UL 391 #define CRYPTO_V2_AES_CTL_KEY_SIZE_Msk 0x3UL 392 /* CRYPTO.RESULT */ 393 #define CRYPTO_V2_RESULT_DATA_Pos 0UL 394 #define CRYPTO_V2_RESULT_DATA_Msk 0xFFFFFFFFUL 395 /* CRYPTO.CRC_CTL */ 396 #define CRYPTO_V2_CRC_CTL_DATA_REVERSE_Pos 0UL 397 #define CRYPTO_V2_CRC_CTL_DATA_REVERSE_Msk 0x1UL 398 #define CRYPTO_V2_CRC_CTL_REM_REVERSE_Pos 8UL 399 #define CRYPTO_V2_CRC_CTL_REM_REVERSE_Msk 0x100UL 400 /* CRYPTO.CRC_DATA_CTL */ 401 #define CRYPTO_V2_CRC_DATA_CTL_DATA_XOR_Pos 0UL 402 #define CRYPTO_V2_CRC_DATA_CTL_DATA_XOR_Msk 0xFFUL 403 /* CRYPTO.CRC_POL_CTL */ 404 #define CRYPTO_V2_CRC_POL_CTL_POLYNOMIAL_Pos 0UL 405 #define CRYPTO_V2_CRC_POL_CTL_POLYNOMIAL_Msk 0xFFFFFFFFUL 406 /* CRYPTO.CRC_REM_CTL */ 407 #define CRYPTO_V2_CRC_REM_CTL_REM_XOR_Pos 0UL 408 #define CRYPTO_V2_CRC_REM_CTL_REM_XOR_Msk 0xFFFFFFFFUL 409 /* CRYPTO.CRC_REM_RESULT */ 410 #define CRYPTO_V2_CRC_REM_RESULT_REM_Pos 0UL 411 #define CRYPTO_V2_CRC_REM_RESULT_REM_Msk 0xFFFFFFFFUL 412 /* CRYPTO.VU_CTL0 */ 413 #define CRYPTO_V2_VU_CTL0_ALWAYS_EXECUTE_Pos 0UL 414 #define CRYPTO_V2_VU_CTL0_ALWAYS_EXECUTE_Msk 0x1UL 415 /* CRYPTO.VU_CTL1 */ 416 #define CRYPTO_V2_VU_CTL1_ADDR24_Pos 8UL 417 #define CRYPTO_V2_VU_CTL1_ADDR24_Msk 0xFFFFFF00UL 418 /* CRYPTO.VU_CTL2 */ 419 #define CRYPTO_V2_VU_CTL2_MASK_Pos 8UL 420 #define CRYPTO_V2_VU_CTL2_MASK_Msk 0x7F00UL 421 /* CRYPTO.VU_STATUS */ 422 #define CRYPTO_V2_VU_STATUS_CARRY_Pos 0UL 423 #define CRYPTO_V2_VU_STATUS_CARRY_Msk 0x1UL 424 #define CRYPTO_V2_VU_STATUS_EVEN_Pos 1UL 425 #define CRYPTO_V2_VU_STATUS_EVEN_Msk 0x2UL 426 #define CRYPTO_V2_VU_STATUS_ZERO_Pos 2UL 427 #define CRYPTO_V2_VU_STATUS_ZERO_Msk 0x4UL 428 #define CRYPTO_V2_VU_STATUS_ONE_Pos 3UL 429 #define CRYPTO_V2_VU_STATUS_ONE_Msk 0x8UL 430 /* CRYPTO.VU_RF_DATA */ 431 #define CRYPTO_V2_VU_RF_DATA_DATA32_Pos 0UL 432 #define CRYPTO_V2_VU_RF_DATA_DATA32_Msk 0xFFFFFFFFUL 433 /* CRYPTO.DEV_KEY_ADDR0_CTL */ 434 #define CRYPTO_V2_DEV_KEY_ADDR0_CTL_VALID_Pos 31UL 435 #define CRYPTO_V2_DEV_KEY_ADDR0_CTL_VALID_Msk 0x80000000UL 436 /* CRYPTO.DEV_KEY_ADDR0 */ 437 #define CRYPTO_V2_DEV_KEY_ADDR0_ADDR32_Pos 0UL 438 #define CRYPTO_V2_DEV_KEY_ADDR0_ADDR32_Msk 0xFFFFFFFFUL 439 /* CRYPTO.DEV_KEY_ADDR1_CTL */ 440 #define CRYPTO_V2_DEV_KEY_ADDR1_CTL_VALID_Pos 31UL 441 #define CRYPTO_V2_DEV_KEY_ADDR1_CTL_VALID_Msk 0x80000000UL 442 /* CRYPTO.DEV_KEY_ADDR1 */ 443 #define CRYPTO_V2_DEV_KEY_ADDR1_ADDR32_Pos 0UL 444 #define CRYPTO_V2_DEV_KEY_ADDR1_ADDR32_Msk 0xFFFFFFFFUL 445 /* CRYPTO.DEV_KEY_STATUS */ 446 #define CRYPTO_V2_DEV_KEY_STATUS_LOADED_Pos 0UL 447 #define CRYPTO_V2_DEV_KEY_STATUS_LOADED_Msk 0x1UL 448 /* CRYPTO.DEV_KEY_CTL0 */ 449 #define CRYPTO_V2_DEV_KEY_CTL0_ALLOWED_Pos 0UL 450 #define CRYPTO_V2_DEV_KEY_CTL0_ALLOWED_Msk 0x1UL 451 /* CRYPTO.DEV_KEY_CTL1 */ 452 #define CRYPTO_V2_DEV_KEY_CTL1_ALLOWED_Pos 0UL 453 #define CRYPTO_V2_DEV_KEY_CTL1_ALLOWED_Msk 0x1UL 454 /* CRYPTO.MEM_BUFF */ 455 #define CRYPTO_V2_MEM_BUFF_DATA32_Pos 0UL 456 #define CRYPTO_V2_MEM_BUFF_DATA32_Msk 0xFFFFFFFFUL 457 458 459 #endif /* _CYIP_CRYPTO_V2_H_ */ 460 461 462 /* [] END OF FILE */ 463
