1 /***************************************************************************//** 2 * \file gpio_psoc6_03_49_wlcsp.h 3 * 4 * \brief 5 * PSoC6_03 device GPIO header for 49-WLCSP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_PSOC6_03_49_WLCSP_H_ 28 #define _GPIO_PSOC6_03_49_WLCSP_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_WLCSP 44 #define CY_GPIO_PIN_COUNT 49u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_ANALOG_VDDD, 50 AMUXBUS_CSD0, 51 AMUXBUS_CSD1, 52 AMUXBUS_SAR, 53 AMUXBUS_VDDIO_1, 54 AMUXBUS_VSSA, 55 AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, 56 AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, 57 }; 58 59 /* AMUX Splitter Controls */ 60 typedef enum 61 { 62 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ 63 AMUX_SPLIT_CTL_3 = 0x0003u /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ 64 } cy_en_amux_split_t; 65 66 /* Port List */ 67 /* PORT 0 (GPIO) */ 68 #define P0_0_PORT GPIO_PRT0 69 #define P0_0_PIN 0u 70 #define P0_0_NUM 0u 71 #define P0_1_PORT GPIO_PRT0 72 #define P0_1_PIN 1u 73 #define P0_1_NUM 1u 74 #define P0_4_PORT GPIO_PRT0 75 #define P0_4_PIN 4u 76 #define P0_4_NUM 4u 77 78 /* PORT 2 (GPIO) */ 79 #define P2_0_PORT GPIO_PRT2 80 #define P2_0_PIN 0u 81 #define P2_0_NUM 0u 82 #define P2_1_PORT GPIO_PRT2 83 #define P2_1_PIN 1u 84 #define P2_1_NUM 1u 85 #define P2_2_PORT GPIO_PRT2 86 #define P2_2_PIN 2u 87 #define P2_2_NUM 2u 88 #define P2_3_PORT GPIO_PRT2 89 #define P2_3_PIN 3u 90 #define P2_3_NUM 3u 91 #define P2_4_PORT GPIO_PRT2 92 #define P2_4_PIN 4u 93 #define P2_4_NUM 4u 94 #define P2_5_PORT GPIO_PRT2 95 #define P2_5_PIN 5u 96 #define P2_5_NUM 5u 97 98 /* PORT 5 (GPIO) */ 99 #define P5_0_PORT GPIO_PRT5 100 #define P5_0_PIN 0u 101 #define P5_0_NUM 0u 102 #define P5_1_PORT GPIO_PRT5 103 #define P5_1_PIN 1u 104 #define P5_1_NUM 1u 105 106 /* PORT 6 (GPIO) */ 107 #define P6_2_PORT GPIO_PRT6 108 #define P6_2_PIN 2u 109 #define P6_2_NUM 2u 110 #define P6_3_PORT GPIO_PRT6 111 #define P6_3_PIN 3u 112 #define P6_3_NUM 3u 113 #define P6_4_PORT GPIO_PRT6 114 #define P6_4_PIN 4u 115 #define P6_4_NUM 4u 116 #define P6_5_PORT GPIO_PRT6 117 #define P6_5_PIN 5u 118 #define P6_5_NUM 5u 119 #define P6_6_PORT GPIO_PRT6 120 #define P6_6_PIN 6u 121 #define P6_6_NUM 6u 122 #define P6_7_PORT GPIO_PRT6 123 #define P6_7_PIN 7u 124 #define P6_7_NUM 7u 125 126 /* PORT 7 (GPIO) */ 127 #define P7_0_PORT GPIO_PRT7 128 #define P7_0_PIN 0u 129 #define P7_0_NUM 0u 130 #define P7_0_AMUXSEGMENT AMUXBUS_CSD0 131 #define P7_1_PORT GPIO_PRT7 132 #define P7_1_PIN 1u 133 #define P7_1_NUM 1u 134 #define P7_1_AMUXSEGMENT AMUXBUS_CSD0 135 #define P7_2_PORT GPIO_PRT7 136 #define P7_2_PIN 2u 137 #define P7_2_NUM 2u 138 #define P7_2_AMUXSEGMENT AMUXBUS_CSD0 139 #define P7_3_PORT GPIO_PRT7 140 #define P7_3_PIN 3u 141 #define P7_3_NUM 3u 142 #define P7_3_AMUXSEGMENT AMUXBUS_CSD0 143 #define P7_4_PORT GPIO_PRT7 144 #define P7_4_PIN 4u 145 #define P7_4_NUM 4u 146 #define P7_4_AMUXSEGMENT AMUXBUS_CSD0 147 148 /* PORT 9 (GPIO) */ 149 #define P9_0_PORT GPIO_PRT9 150 #define P9_0_PIN 0u 151 #define P9_0_NUM 0u 152 #define P9_0_AMUXSEGMENT AMUXBUS_SAR 153 #define P9_1_PORT GPIO_PRT9 154 #define P9_1_PIN 1u 155 #define P9_1_NUM 1u 156 #define P9_1_AMUXSEGMENT AMUXBUS_SAR 157 #define P9_2_PORT GPIO_PRT9 158 #define P9_2_PIN 2u 159 #define P9_2_NUM 2u 160 #define P9_2_AMUXSEGMENT AMUXBUS_SAR 161 #define P9_3_PORT GPIO_PRT9 162 #define P9_3_PIN 3u 163 #define P9_3_NUM 3u 164 #define P9_3_AMUXSEGMENT AMUXBUS_SAR 165 166 /* PORT 10 (GPIO) */ 167 #define P10_0_PORT GPIO_PRT10 168 #define P10_0_PIN 0u 169 #define P10_0_NUM 0u 170 #define P10_1_PORT GPIO_PRT10 171 #define P10_1_PIN 1u 172 #define P10_1_NUM 1u 173 #define P10_2_PORT GPIO_PRT10 174 #define P10_2_PIN 2u 175 #define P10_2_NUM 2u 176 #define P10_3_PORT GPIO_PRT10 177 #define P10_3_PIN 3u 178 #define P10_3_NUM 3u 179 #define P10_4_PORT GPIO_PRT10 180 #define P10_4_PIN 4u 181 #define P10_4_NUM 4u 182 #define P10_5_PORT GPIO_PRT10 183 #define P10_5_PIN 5u 184 #define P10_5_NUM 5u 185 186 /* PORT 11 (GPIO) */ 187 #define P11_2_PORT GPIO_PRT11 188 #define P11_2_PIN 2u 189 #define P11_2_NUM 2u 190 #define P11_3_PORT GPIO_PRT11 191 #define P11_3_PIN 3u 192 #define P11_3_NUM 3u 193 #define P11_4_PORT GPIO_PRT11 194 #define P11_4_PIN 4u 195 #define P11_4_NUM 4u 196 #define P11_5_PORT GPIO_PRT11 197 #define P11_5_PIN 5u 198 #define P11_5_NUM 5u 199 #define P11_6_PORT GPIO_PRT11 200 #define P11_6_PIN 6u 201 #define P11_6_NUM 6u 202 #define P11_7_PORT GPIO_PRT11 203 #define P11_7_PIN 7u 204 #define P11_7_NUM 7u 205 206 /* Analog Connections */ 207 #define CSD_CMODPADD_PORT 7u 208 #define CSD_CMODPADD_PIN 1u 209 #define CSD_CMODPADS_PORT 7u 210 #define CSD_CMODPADS_PIN 1u 211 #define CSD_CSH_TANKPADD_PORT 7u 212 #define CSD_CSH_TANKPADD_PIN 2u 213 #define CSD_CSH_TANKPADS_PORT 7u 214 #define CSD_CSH_TANKPADS_PIN 2u 215 #define CSD_VREF_EXT_PORT 7u 216 #define CSD_VREF_EXT_PIN 3u 217 #define IOSS_ADFT0_NET_PORT 10u 218 #define IOSS_ADFT0_NET_PIN 0u 219 #define IOSS_ADFT1_NET_PORT 10u 220 #define IOSS_ADFT1_NET_PIN 1u 221 #define LPCOMP_INN_COMP1_PORT 6u 222 #define LPCOMP_INN_COMP1_PIN 3u 223 #define LPCOMP_INP_COMP1_PORT 6u 224 #define LPCOMP_INP_COMP1_PIN 2u 225 #define PASS_AREF_EXT_VREF_PORT 9u 226 #define PASS_AREF_EXT_VREF_PIN 3u 227 #define PASS_SARMUX_PADS0_PORT 10u 228 #define PASS_SARMUX_PADS0_PIN 0u 229 #define PASS_SARMUX_PADS1_PORT 10u 230 #define PASS_SARMUX_PADS1_PIN 1u 231 #define PASS_SARMUX_PADS2_PORT 10u 232 #define PASS_SARMUX_PADS2_PIN 2u 233 #define PASS_SARMUX_PADS3_PORT 10u 234 #define PASS_SARMUX_PADS3_PIN 3u 235 #define PASS_SARMUX_PADS4_PORT 10u 236 #define PASS_SARMUX_PADS4_PIN 4u 237 #define PASS_SARMUX_PADS5_PORT 10u 238 #define PASS_SARMUX_PADS5_PIN 5u 239 #define SRSS_ADFT_PIN0_PORT 10u 240 #define SRSS_ADFT_PIN0_PIN 0u 241 #define SRSS_ADFT_PIN1_PORT 10u 242 #define SRSS_ADFT_PIN1_PIN 1u 243 #define SRSS_WCO_IN_PORT 0u 244 #define SRSS_WCO_IN_PIN 0u 245 #define SRSS_WCO_OUT_PORT 0u 246 #define SRSS_WCO_OUT_PIN 1u 247 248 /* HSIOM Connections */ 249 typedef enum 250 { 251 /* Generic HSIOM connections */ 252 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 253 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 254 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 255 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 256 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 257 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 258 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 259 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 260 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 261 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 262 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 263 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 264 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 265 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 266 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 267 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 268 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 269 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 270 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 271 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 272 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 273 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 274 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 275 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 276 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 277 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 278 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 279 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 280 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 281 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 282 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 283 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 284 285 /* P0.0 */ 286 P0_0_GPIO = 0, /* GPIO controls 'out' */ 287 P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 288 P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ 289 P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ 290 P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ 291 P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ 292 P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ 293 P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 294 P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ 295 P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 296 297 /* P0.1 */ 298 P0_1_GPIO = 0, /* GPIO controls 'out' */ 299 P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 300 P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ 301 P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ 302 P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ 303 P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ 304 P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ 305 P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ 306 P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ 307 P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 308 309 /* P0.4 */ 310 P0_4_GPIO = 0, /* GPIO controls 'out' */ 311 P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 312 P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ 313 P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ 314 P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ 315 P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ 316 P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ 317 P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ 318 P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ 319 P0_4_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ 320 P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 321 322 /* P2.0 */ 323 P2_0_GPIO = 0, /* GPIO controls 'out' */ 324 P2_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 325 P2_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ 326 P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ 327 P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ 328 P2_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ 329 P2_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ 330 P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ 331 P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ 332 P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ 333 P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ 334 P2_0_SDHC0_CARD_DAT_3TO00 = 26, /* Digital Active - sdhc[0].card_dat_3to0[0] */ 335 336 /* P2.1 */ 337 P2_1_GPIO = 0, /* GPIO controls 'out' */ 338 P2_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 339 P2_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ 340 P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ 341 P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ 342 P2_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ 343 P2_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ 344 P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ 345 P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ 346 P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ 347 P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ 348 P2_1_SDHC0_CARD_DAT_3TO01 = 26, /* Digital Active - sdhc[0].card_dat_3to0[1] */ 349 350 /* P2.2 */ 351 P2_2_GPIO = 0, /* GPIO controls 'out' */ 352 P2_2_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 353 P2_2_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ 354 P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */ 355 P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */ 356 P2_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ 357 P2_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ 358 P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ 359 P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ 360 P2_2_SDHC0_CARD_DAT_3TO02 = 26, /* Digital Active - sdhc[0].card_dat_3to0[2] */ 361 362 /* P2.3 */ 363 P2_3_GPIO = 0, /* GPIO controls 'out' */ 364 P2_3_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 365 P2_3_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ 366 P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ 367 P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ 368 P2_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ 369 P2_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ 370 P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ 371 P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ 372 P2_3_SDHC0_CARD_DAT_3TO03 = 26, /* Digital Active - sdhc[0].card_dat_3to0[3] */ 373 374 /* P2.4 */ 375 P2_4_GPIO = 0, /* GPIO controls 'out' */ 376 P2_4_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 377 P2_4_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ 378 P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ 379 P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ 380 P2_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ 381 P2_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ 382 P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ 383 P2_4_SDHC0_CARD_CMD = 26, /* Digital Active - sdhc[0].card_cmd */ 384 385 /* P2.5 */ 386 P2_5_GPIO = 0, /* GPIO controls 'out' */ 387 P2_5_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 388 P2_5_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ 389 P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ 390 P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ 391 P2_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ 392 P2_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ 393 P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ 394 P2_5_SDHC0_CLK_CARD = 26, /* Digital Active - sdhc[0].clk_card */ 395 396 /* P5.0 */ 397 P5_0_GPIO = 0, /* GPIO controls 'out' */ 398 P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 399 P5_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ 400 P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ 401 P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ 402 P5_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ 403 P5_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ 404 P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ 405 P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ 406 P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ 407 P5_0_CANFD0_TTCAN_RX0 = 22, /* Digital Active - canfd[0].ttcan_rx[0] */ 408 P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ 409 410 /* P5.1 */ 411 P5_1_GPIO = 0, /* GPIO controls 'out' */ 412 P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 413 P5_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ 414 P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ 415 P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ 416 P5_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ 417 P5_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ 418 P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ 419 P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ 420 P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ 421 P5_1_CANFD0_TTCAN_TX0 = 22, /* Digital Active - canfd[0].ttcan_tx[0] */ 422 P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ 423 424 /* P6.2 */ 425 P6_2_GPIO = 0, /* GPIO controls 'out' */ 426 P6_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ 427 P6_2_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ 428 P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ 429 P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:22 */ 430 P6_2_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:0 */ 431 P6_2_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:0 */ 432 P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ 433 P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ 434 435 /* P6.3 */ 436 P6_3_GPIO = 0, /* GPIO controls 'out' */ 437 P6_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ 438 P6_3_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ 439 P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ 440 P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:23 */ 441 P6_3_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:0 */ 442 P6_3_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:0 */ 443 P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ 444 P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ 445 446 /* P6.4 */ 447 P6_4_GPIO = 0, /* GPIO controls 'out' */ 448 P6_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 449 P6_4_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ 450 P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ 451 P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:24 */ 452 P6_4_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:0 */ 453 P6_4_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:0 */ 454 P6_4_SCB6_I2C_SCL = 14, /* Digital Deep Sleep - scb[6].i2c_scl:0 */ 455 P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 456 P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 457 P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 458 P6_4_SCB6_SPI_MOSI = 30, /* Digital Deep Sleep - scb[6].spi_mosi:0 */ 459 P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 460 461 /* P6.5 */ 462 P6_5_GPIO = 0, /* GPIO controls 'out' */ 463 P6_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ 464 P6_5_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ 465 P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ 466 P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:25 */ 467 P6_5_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:0 */ 468 P6_5_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:0 */ 469 P6_5_SCB6_I2C_SDA = 14, /* Digital Deep Sleep - scb[6].i2c_sda:0 */ 470 P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 471 P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 472 P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 473 P6_5_SCB6_SPI_MISO = 30, /* Digital Deep Sleep - scb[6].spi_miso:0 */ 474 P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 475 476 /* P6.6 */ 477 P6_6_GPIO = 0, /* GPIO controls 'out' */ 478 P6_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 479 P6_6_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ 480 P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ 481 P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:26 */ 482 P6_6_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:0 */ 483 P6_6_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:0 */ 484 P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 485 P6_6_SCB6_SPI_CLK = 30, /* Digital Deep Sleep - scb[6].spi_clk:0 */ 486 487 /* P6.7 */ 488 P6_7_GPIO = 0, /* GPIO controls 'out' */ 489 P6_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 490 P6_7_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ 491 P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ 492 P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:27 */ 493 P6_7_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:0 */ 494 P6_7_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:0 */ 495 P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 496 P6_7_SCB6_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[6].spi_select0:0 */ 497 498 /* P7.0 */ 499 P7_0_GPIO = 0, /* GPIO controls 'out' */ 500 P7_0_AMUXA = 4, /* Analog mux bus A */ 501 P7_0_AMUXB = 5, /* Analog mux bus B */ 502 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 503 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 504 P7_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ 505 P7_0_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ 506 P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:28 */ 507 P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:28 */ 508 P7_0_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:0 */ 509 P7_0_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:0 */ 510 P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 511 P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 512 P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 513 P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 514 P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ 515 516 /* P7.1 */ 517 P7_1_GPIO = 0, /* GPIO controls 'out' */ 518 P7_1_AMUXA = 4, /* Analog mux bus A */ 519 P7_1_AMUXB = 5, /* Analog mux bus B */ 520 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 521 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 522 P7_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ 523 P7_1_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ 524 P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:29 */ 525 P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:29 */ 526 P7_1_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:0 */ 527 P7_1_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:0 */ 528 P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 529 P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 530 P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 531 P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 532 533 /* P7.2 */ 534 P7_2_GPIO = 0, /* GPIO controls 'out' */ 535 P7_2_AMUXA = 4, /* Analog mux bus A */ 536 P7_2_AMUXB = 5, /* Analog mux bus B */ 537 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 538 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 539 P7_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ 540 P7_2_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ 541 P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ 542 P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ 543 P7_2_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ 544 P7_2_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ 545 P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ 546 P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ 547 548 /* P7.3 */ 549 P7_3_GPIO = 0, /* GPIO controls 'out' */ 550 P7_3_AMUXA = 4, /* Analog mux bus A */ 551 P7_3_AMUXB = 5, /* Analog mux bus B */ 552 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 553 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 554 P7_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ 555 P7_3_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ 556 P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ 557 P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ 558 P7_3_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ 559 P7_3_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ 560 P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ 561 P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ 562 563 /* P7.4 */ 564 P7_4_GPIO = 0, /* GPIO controls 'out' */ 565 P7_4_AMUXA = 4, /* Analog mux bus A */ 566 P7_4_AMUXB = 5, /* Analog mux bus B */ 567 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 568 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 569 P7_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ 570 P7_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:2 */ 571 P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ 572 P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ 573 P7_4_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */ 574 P7_4_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */ 575 P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:1 */ 576 P7_4_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */ 577 578 /* P9.0 */ 579 P9_0_GPIO = 0, /* GPIO controls 'out' */ 580 P9_0_AMUXA = 4, /* Analog mux bus A */ 581 P9_0_AMUXB = 5, /* Analog mux bus B */ 582 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 583 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 584 P9_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ 585 P9_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:2 */ 586 P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ 587 P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ 588 P9_0_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ 589 P9_0_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ 590 P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 591 P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 592 P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ 593 P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 594 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 595 596 /* P9.1 */ 597 P9_1_GPIO = 0, /* GPIO controls 'out' */ 598 P9_1_AMUXA = 4, /* Analog mux bus A */ 599 P9_1_AMUXB = 5, /* Analog mux bus B */ 600 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 601 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 602 P9_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ 603 P9_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:2 */ 604 P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ 605 P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ 606 P9_1_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ 607 P9_1_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ 608 P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 609 P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 610 P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ 611 P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 612 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 613 P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 614 615 /* P9.2 */ 616 P9_2_GPIO = 0, /* GPIO controls 'out' */ 617 P9_2_AMUXA = 4, /* Analog mux bus A */ 618 P9_2_AMUXB = 5, /* Analog mux bus B */ 619 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 620 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 621 P9_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ 622 P9_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:2 */ 623 P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ 624 P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ 625 P9_2_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ 626 P9_2_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ 627 P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 628 P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ 629 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 630 631 /* P9.3 */ 632 P9_3_GPIO = 0, /* GPIO controls 'out' */ 633 P9_3_AMUXA = 4, /* Analog mux bus A */ 634 P9_3_AMUXB = 5, /* Analog mux bus B */ 635 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 636 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 637 P9_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ 638 P9_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:2 */ 639 P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ 640 P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ 641 P9_3_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ 642 P9_3_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ 643 P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 644 P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ 645 P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 646 P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 647 648 /* P10.0 */ 649 P10_0_GPIO = 0, /* GPIO controls 'out' */ 650 P10_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:5 */ 651 P10_0_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:2 */ 652 P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ 653 P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ 654 P10_0_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ 655 P10_0_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ 656 P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 657 P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 658 P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 659 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 660 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 661 662 /* P10.1 */ 663 P10_1_GPIO = 0, /* GPIO controls 'out' */ 664 P10_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:5 */ 665 P10_1_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:2 */ 666 P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ 667 P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ 668 P10_1_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ 669 P10_1_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ 670 P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 671 P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 672 P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 673 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 674 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 675 676 /* P10.2 */ 677 P10_2_GPIO = 0, /* GPIO controls 'out' */ 678 P10_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ 679 P10_2_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:2 */ 680 P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ 681 P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ 682 P10_2_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ 683 P10_2_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ 684 P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ 685 P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ 686 P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 687 688 /* P10.3 */ 689 P10_3_GPIO = 0, /* GPIO controls 'out' */ 690 P10_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ 691 P10_3_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:2 */ 692 P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ 693 P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ 694 P10_3_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ 695 P10_3_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ 696 P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ 697 P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ 698 P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 699 700 /* P10.4 */ 701 P10_4_GPIO = 0, /* GPIO controls 'out' */ 702 P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ 703 P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:3 */ 704 P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ 705 P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ 706 P10_4_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ 707 P10_4_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ 708 P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ 709 710 /* P10.5 */ 711 P10_5_GPIO = 0, /* GPIO controls 'out' */ 712 P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ 713 P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:3 */ 714 P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ 715 P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ 716 P10_5_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ 717 P10_5_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ 718 P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ 719 720 /* P11.2 */ 721 P11_2_GPIO = 0, /* GPIO controls 'out' */ 722 P11_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:6 */ 723 P11_2_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:3 */ 724 P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ 725 P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ 726 P11_2_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ 727 P11_2_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ 728 P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 729 P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ 730 P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ 731 732 /* P11.3 */ 733 P11_3_GPIO = 0, /* GPIO controls 'out' */ 734 P11_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:6 */ 735 P11_3_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:3 */ 736 P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ 737 P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ 738 P11_3_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ 739 P11_3_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ 740 P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 741 P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ 742 P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ 743 P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 744 745 /* P11.4 */ 746 P11_4_GPIO = 0, /* GPIO controls 'out' */ 747 P11_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:7 */ 748 P11_4_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:3 */ 749 P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ 750 P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ 751 P11_4_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ 752 P11_4_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ 753 P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 754 P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ 755 P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ 756 757 /* P11.5 */ 758 P11_5_GPIO = 0, /* GPIO controls 'out' */ 759 P11_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:7 */ 760 P11_5_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:3 */ 761 P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ 762 P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ 763 P11_5_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ 764 P11_5_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ 765 P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 766 P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ 767 768 /* P11.6 */ 769 P11_6_GPIO = 0, /* GPIO controls 'out' */ 770 P11_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:7 */ 771 P11_6_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:3 */ 772 P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ 773 P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ 774 P11_6_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ 775 P11_6_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ 776 P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 777 P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ 778 779 /* P11.7 */ 780 P11_7_GPIO = 0, /* GPIO controls 'out' */ 781 P11_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:7 */ 782 P11_7_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:3 */ 783 P11_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ 784 P11_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ 785 P11_7_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ 786 P11_7_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ 787 P11_7_SMIF_SPI_CLK = 17 /* Digital Active - smif.spi_clk */ 788 } en_hsiom_sel_t; 789 790 #endif /* _GPIO_PSOC6_03_49_WLCSP_H_ */ 791 792 793 /* [] END OF FILE */ 794
