1 /***************************************************************************//** 2 * \file gpio_psoc6_01_80_wlcsp.h 3 * 4 * \brief 5 * PSoC6_01 device GPIO header for 80-WLCSP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_PSOC6_01_80_WLCSP_H_ 28 #define _GPIO_PSOC6_01_80_WLCSP_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_WLCSP 44 #define CY_GPIO_PIN_COUNT 80u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_ADFT0_VDDD, 50 AMUXBUS_ADFT1_VDDD, 51 AMUXBUS_ANALOG_VDDA, 52 AMUXBUS_ANALOG_VDDD, 53 AMUXBUS_CSD0, 54 AMUXBUS_CSD1, 55 AMUXBUS_MAIN, 56 AMUXBUS_NOISY, 57 AMUXBUS_SAR, 58 AMUXBUS_VDDIO_1, 59 }; 60 61 /* AMUX Splitter Controls */ 62 typedef enum 63 { 64 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ 65 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ 66 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD0; Right = AMUXBUS_NOISY */ 67 AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ 68 AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ 69 AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ 70 AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ 71 AMUX_SPLIT_CTL_7 = 0x0007u, /* Left = AMUXBUS_ADFT1_VDDD; Right = AMUXBUS_NOISY */ 72 AMUX_SPLIT_CTL_8 = 0x0008u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ 73 } cy_en_amux_split_t; 74 75 /* Port List */ 76 /* PORT 0 (GPIO) */ 77 #define P0_0_PORT GPIO_PRT0 78 #define P0_0_PIN 0u 79 #define P0_0_NUM 0u 80 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 81 #define P0_1_PORT GPIO_PRT0 82 #define P0_1_PIN 1u 83 #define P0_1_NUM 1u 84 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 85 #define P0_2_PORT GPIO_PRT0 86 #define P0_2_PIN 2u 87 #define P0_2_NUM 2u 88 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 89 #define P0_3_PORT GPIO_PRT0 90 #define P0_3_PIN 3u 91 #define P0_3_NUM 3u 92 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 93 #define P0_4_PORT GPIO_PRT0 94 #define P0_4_PIN 4u 95 #define P0_4_NUM 4u 96 #define P0_4_AMUXSEGMENT AMUXBUS_MAIN 97 #define P0_5_PORT GPIO_PRT0 98 #define P0_5_PIN 5u 99 #define P0_5_NUM 5u 100 #define P0_5_AMUXSEGMENT AMUXBUS_MAIN 101 102 /* PORT 1 (GPIO_OVT) */ 103 #define P1_0_PORT GPIO_PRT1 104 #define P1_0_PIN 0u 105 #define P1_0_NUM 0u 106 #define P1_0_AMUXSEGMENT AMUXBUS_NOISY 107 #define P1_1_PORT GPIO_PRT1 108 #define P1_1_PIN 1u 109 #define P1_1_NUM 1u 110 #define P1_1_AMUXSEGMENT AMUXBUS_NOISY 111 #define P1_4_PORT GPIO_PRT1 112 #define P1_4_PIN 4u 113 #define P1_4_NUM 4u 114 #define P1_4_AMUXSEGMENT AMUXBUS_NOISY 115 #define P1_5_PORT GPIO_PRT1 116 #define P1_5_PIN 5u 117 #define P1_5_NUM 5u 118 #define P1_5_AMUXSEGMENT AMUXBUS_NOISY 119 120 /* PORT 5 (GPIO) */ 121 #define P5_0_PORT GPIO_PRT5 122 #define P5_0_PIN 0u 123 #define P5_0_NUM 0u 124 #define P5_0_AMUXSEGMENT AMUXBUS_CSD0 125 #define P5_1_PORT GPIO_PRT5 126 #define P5_1_PIN 1u 127 #define P5_1_NUM 1u 128 #define P5_1_AMUXSEGMENT AMUXBUS_CSD0 129 #define P5_2_PORT GPIO_PRT5 130 #define P5_2_PIN 2u 131 #define P5_2_NUM 2u 132 #define P5_2_AMUXSEGMENT AMUXBUS_CSD0 133 #define P5_3_PORT GPIO_PRT5 134 #define P5_3_PIN 3u 135 #define P5_3_NUM 3u 136 #define P5_3_AMUXSEGMENT AMUXBUS_CSD0 137 #define P5_4_PORT GPIO_PRT5 138 #define P5_4_PIN 4u 139 #define P5_4_NUM 4u 140 #define P5_4_AMUXSEGMENT AMUXBUS_CSD0 141 #define P5_5_PORT GPIO_PRT5 142 #define P5_5_PIN 5u 143 #define P5_5_NUM 5u 144 #define P5_5_AMUXSEGMENT AMUXBUS_CSD0 145 #define P5_6_PORT GPIO_PRT5 146 #define P5_6_PIN 6u 147 #define P5_6_NUM 6u 148 #define P5_6_AMUXSEGMENT AMUXBUS_CSD0 149 #define P5_7_PORT GPIO_PRT5 150 #define P5_7_PIN 7u 151 #define P5_7_NUM 7u 152 #define P5_7_AMUXSEGMENT AMUXBUS_CSD0 153 154 /* PORT 6 (GPIO) */ 155 #define P6_0_PORT GPIO_PRT6 156 #define P6_0_PIN 0u 157 #define P6_0_NUM 0u 158 #define P6_0_AMUXSEGMENT AMUXBUS_CSD0 159 #define P6_1_PORT GPIO_PRT6 160 #define P6_1_PIN 1u 161 #define P6_1_NUM 1u 162 #define P6_1_AMUXSEGMENT AMUXBUS_CSD0 163 #define P6_2_PORT GPIO_PRT6 164 #define P6_2_PIN 2u 165 #define P6_2_NUM 2u 166 #define P6_2_AMUXSEGMENT AMUXBUS_CSD0 167 #define P6_3_PORT GPIO_PRT6 168 #define P6_3_PIN 3u 169 #define P6_3_NUM 3u 170 #define P6_3_AMUXSEGMENT AMUXBUS_CSD0 171 #define P6_4_PORT GPIO_PRT6 172 #define P6_4_PIN 4u 173 #define P6_4_NUM 4u 174 #define P6_4_AMUXSEGMENT AMUXBUS_CSD0 175 #define P6_5_PORT GPIO_PRT6 176 #define P6_5_PIN 5u 177 #define P6_5_NUM 5u 178 #define P6_5_AMUXSEGMENT AMUXBUS_CSD0 179 #define P6_6_PORT GPIO_PRT6 180 #define P6_6_PIN 6u 181 #define P6_6_NUM 6u 182 #define P6_6_AMUXSEGMENT AMUXBUS_CSD0 183 #define P6_7_PORT GPIO_PRT6 184 #define P6_7_PIN 7u 185 #define P6_7_NUM 7u 186 #define P6_7_AMUXSEGMENT AMUXBUS_CSD0 187 188 /* PORT 7 (GPIO) */ 189 #define P7_0_PORT GPIO_PRT7 190 #define P7_0_PIN 0u 191 #define P7_0_NUM 0u 192 #define P7_0_AMUXSEGMENT AMUXBUS_CSD0 193 #define P7_1_PORT GPIO_PRT7 194 #define P7_1_PIN 1u 195 #define P7_1_NUM 1u 196 #define P7_1_AMUXSEGMENT AMUXBUS_CSD0 197 #define P7_2_PORT GPIO_PRT7 198 #define P7_2_PIN 2u 199 #define P7_2_NUM 2u 200 #define P7_2_AMUXSEGMENT AMUXBUS_CSD0 201 #define P7_3_PORT GPIO_PRT7 202 #define P7_3_PIN 3u 203 #define P7_3_NUM 3u 204 #define P7_3_AMUXSEGMENT AMUXBUS_CSD0 205 #define P7_7_PORT GPIO_PRT7 206 #define P7_7_PIN 7u 207 #define P7_7_NUM 7u 208 #define P7_7_AMUXSEGMENT AMUXBUS_CSD0 209 210 /* PORT 8 (GPIO) */ 211 #define P8_0_PORT GPIO_PRT8 212 #define P8_0_PIN 0u 213 #define P8_0_NUM 0u 214 #define P8_0_AMUXSEGMENT AMUXBUS_CSD0 215 #define P8_1_PORT GPIO_PRT8 216 #define P8_1_PIN 1u 217 #define P8_1_NUM 1u 218 #define P8_1_AMUXSEGMENT AMUXBUS_CSD0 219 #define P8_2_PORT GPIO_PRT8 220 #define P8_2_PIN 2u 221 #define P8_2_NUM 2u 222 #define P8_2_AMUXSEGMENT AMUXBUS_CSD0 223 #define P8_3_PORT GPIO_PRT8 224 #define P8_3_PIN 3u 225 #define P8_3_NUM 3u 226 #define P8_3_AMUXSEGMENT AMUXBUS_CSD0 227 #define P8_4_PORT GPIO_PRT8 228 #define P8_4_PIN 4u 229 #define P8_4_NUM 4u 230 #define P8_4_AMUXSEGMENT AMUXBUS_CSD0 231 232 /* PORT 9 (GPIO) */ 233 #define P9_0_PORT GPIO_PRT9 234 #define P9_0_PIN 0u 235 #define P9_0_NUM 0u 236 #define P9_0_AMUXSEGMENT AMUXBUS_SAR 237 #define P9_1_PORT GPIO_PRT9 238 #define P9_1_PIN 1u 239 #define P9_1_NUM 1u 240 #define P9_1_AMUXSEGMENT AMUXBUS_SAR 241 #define P9_2_PORT GPIO_PRT9 242 #define P9_2_PIN 2u 243 #define P9_2_NUM 2u 244 #define P9_2_AMUXSEGMENT AMUXBUS_SAR 245 #define P9_3_PORT GPIO_PRT9 246 #define P9_3_PIN 3u 247 #define P9_3_NUM 3u 248 #define P9_3_AMUXSEGMENT AMUXBUS_SAR 249 #define P9_4_PORT GPIO_PRT9 250 #define P9_4_PIN 4u 251 #define P9_4_NUM 4u 252 #define P9_4_AMUXSEGMENT AMUXBUS_SAR 253 #define P9_7_PORT GPIO_PRT9 254 #define P9_7_PIN 7u 255 #define P9_7_NUM 7u 256 #define P9_7_AMUXSEGMENT AMUXBUS_SAR 257 258 /* PORT 10 (GPIO) */ 259 #define P10_0_PORT GPIO_PRT10 260 #define P10_0_PIN 0u 261 #define P10_0_NUM 0u 262 #define P10_0_AMUXSEGMENT AMUXBUS_SAR 263 #define P10_1_PORT GPIO_PRT10 264 #define P10_1_PIN 1u 265 #define P10_1_NUM 1u 266 #define P10_1_AMUXSEGMENT AMUXBUS_SAR 267 #define P10_4_PORT GPIO_PRT10 268 #define P10_4_PIN 4u 269 #define P10_4_NUM 4u 270 #define P10_4_AMUXSEGMENT AMUXBUS_SAR 271 #define P10_5_PORT GPIO_PRT10 272 #define P10_5_PIN 5u 273 #define P10_5_NUM 5u 274 #define P10_5_AMUXSEGMENT AMUXBUS_SAR 275 276 /* PORT 11 (GPIO) */ 277 #define P11_0_PORT GPIO_PRT11 278 #define P11_0_PIN 0u 279 #define P11_0_NUM 0u 280 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 281 #define P11_1_PORT GPIO_PRT11 282 #define P11_1_PIN 1u 283 #define P11_1_NUM 1u 284 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 285 #define P11_2_PORT GPIO_PRT11 286 #define P11_2_PIN 2u 287 #define P11_2_NUM 2u 288 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 289 #define P11_3_PORT GPIO_PRT11 290 #define P11_3_PIN 3u 291 #define P11_3_NUM 3u 292 #define P11_3_AMUXSEGMENT AMUXBUS_MAIN 293 #define P11_4_PORT GPIO_PRT11 294 #define P11_4_PIN 4u 295 #define P11_4_NUM 4u 296 #define P11_4_AMUXSEGMENT AMUXBUS_MAIN 297 #define P11_5_PORT GPIO_PRT11 298 #define P11_5_PIN 5u 299 #define P11_5_NUM 5u 300 #define P11_5_AMUXSEGMENT AMUXBUS_MAIN 301 #define P11_6_PORT GPIO_PRT11 302 #define P11_6_PIN 6u 303 #define P11_6_NUM 6u 304 #define P11_6_AMUXSEGMENT AMUXBUS_MAIN 305 #define P11_7_PORT GPIO_PRT11 306 #define P11_7_PIN 7u 307 #define P11_7_NUM 7u 308 #define P11_7_AMUXSEGMENT AMUXBUS_MAIN 309 310 /* PORT 12 (GPIO) */ 311 #define P12_0_PORT GPIO_PRT12 312 #define P12_0_PIN 0u 313 #define P12_0_NUM 0u 314 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 315 #define P12_1_PORT GPIO_PRT12 316 #define P12_1_PIN 1u 317 #define P12_1_NUM 1u 318 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 319 #define P12_2_PORT GPIO_PRT12 320 #define P12_2_PIN 2u 321 #define P12_2_NUM 2u 322 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 323 #define P12_3_PORT GPIO_PRT12 324 #define P12_3_PIN 3u 325 #define P12_3_NUM 3u 326 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 327 #define P12_4_PORT GPIO_PRT12 328 #define P12_4_PIN 4u 329 #define P12_4_NUM 4u 330 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 331 #define P12_5_PORT GPIO_PRT12 332 #define P12_5_PIN 5u 333 #define P12_5_NUM 5u 334 #define P12_5_AMUXSEGMENT AMUXBUS_MAIN 335 #define P12_6_PORT GPIO_PRT12 336 #define P12_6_PIN 6u 337 #define P12_6_NUM 6u 338 #define P12_6_AMUXSEGMENT AMUXBUS_MAIN 339 #define P12_7_PORT GPIO_PRT12 340 #define P12_7_PIN 7u 341 #define P12_7_NUM 7u 342 #define P12_7_AMUXSEGMENT AMUXBUS_MAIN 343 344 /* PORT 14 (AUX) */ 345 #define USBDP_PORT GPIO_PRT14 346 #define USBDP_PIN 0u 347 #define USBDP_NUM 0u 348 #define USBDP_AMUXSEGMENT AMUXBUS_NOISY 349 #define P14_0_PORT GPIO_PRT14 350 #define P14_0_PIN 0u 351 #define P14_0_NUM 0u 352 #define P14_0_AMUXSEGMENT AMUXBUS_NOISY 353 #define USBDM_PORT GPIO_PRT14 354 #define USBDM_PIN 1u 355 #define USBDM_NUM 1u 356 #define USBDM_AMUXSEGMENT AMUXBUS_NOISY 357 #define P14_1_PORT GPIO_PRT14 358 #define P14_1_PIN 1u 359 #define P14_1_NUM 1u 360 #define P14_1_AMUXSEGMENT AMUXBUS_NOISY 361 362 /* Analog Connections */ 363 #define CSD_CMODPADD_PORT 7u 364 #define CSD_CMODPADD_PIN 1u 365 #define CSD_CMODPADS_PORT 7u 366 #define CSD_CMODPADS_PIN 1u 367 #define CSD_CSH_TANKPADD_PORT 7u 368 #define CSD_CSH_TANKPADD_PIN 2u 369 #define CSD_CSH_TANKPADS_PORT 7u 370 #define CSD_CSH_TANKPADS_PIN 2u 371 #define CSD_CSHIELDPADS_PORT 7u 372 #define CSD_CSHIELDPADS_PIN 7u 373 #define CSD_VREF_EXT_PORT 7u 374 #define CSD_VREF_EXT_PIN 3u 375 #define IOSS_ADFT0_NET_PORT 10u 376 #define IOSS_ADFT0_NET_PIN 0u 377 #define IOSS_ADFT1_NET_PORT 10u 378 #define IOSS_ADFT1_NET_PIN 1u 379 #define LPCOMP_INN_COMP0_PORT 5u 380 #define LPCOMP_INN_COMP0_PIN 7u 381 #define LPCOMP_INN_COMP1_PORT 6u 382 #define LPCOMP_INN_COMP1_PIN 3u 383 #define LPCOMP_INP_COMP0_PORT 5u 384 #define LPCOMP_INP_COMP0_PIN 6u 385 #define LPCOMP_INP_COMP1_PORT 6u 386 #define LPCOMP_INP_COMP1_PIN 2u 387 #define PASS_AREF_EXT_VREF_PORT 9u 388 #define PASS_AREF_EXT_VREF_PIN 7u 389 #define PASS_CTB_OA0_OUT_10X_PORT 9u 390 #define PASS_CTB_OA0_OUT_10X_PIN 2u 391 #define PASS_CTB_OA1_OUT_10X_PORT 9u 392 #define PASS_CTB_OA1_OUT_10X_PIN 3u 393 #define PASS_CTB_PADS0_PORT 9u 394 #define PASS_CTB_PADS0_PIN 0u 395 #define PASS_CTB_PADS1_PORT 9u 396 #define PASS_CTB_PADS1_PIN 1u 397 #define PASS_CTB_PADS2_PORT 9u 398 #define PASS_CTB_PADS2_PIN 2u 399 #define PASS_CTB_PADS3_PORT 9u 400 #define PASS_CTB_PADS3_PIN 3u 401 #define PASS_CTB_PADS4_PORT 9u 402 #define PASS_CTB_PADS4_PIN 4u 403 #define PASS_CTB_PADS7_PORT 9u 404 #define PASS_CTB_PADS7_PIN 7u 405 #define PASS_SARMUX_PADS0_PORT 10u 406 #define PASS_SARMUX_PADS0_PIN 0u 407 #define PASS_SARMUX_PADS1_PORT 10u 408 #define PASS_SARMUX_PADS1_PIN 1u 409 #define PASS_SARMUX_PADS4_PORT 10u 410 #define PASS_SARMUX_PADS4_PIN 4u 411 #define PASS_SARMUX_PADS5_PORT 10u 412 #define PASS_SARMUX_PADS5_PIN 5u 413 #define SRSS_ADFT_PIN0_PORT 10u 414 #define SRSS_ADFT_PIN0_PIN 0u 415 #define SRSS_ADFT_PIN1_PORT 10u 416 #define SRSS_ADFT_PIN1_PIN 1u 417 #define SRSS_ECO_IN_PORT 12u 418 #define SRSS_ECO_IN_PIN 6u 419 #define SRSS_ECO_OUT_PORT 12u 420 #define SRSS_ECO_OUT_PIN 7u 421 #define SRSS_WCO_IN_PORT 0u 422 #define SRSS_WCO_IN_PIN 0u 423 #define SRSS_WCO_OUT_PORT 0u 424 #define SRSS_WCO_OUT_PIN 1u 425 426 /* HSIOM Connections */ 427 typedef enum 428 { 429 /* Generic HSIOM connections */ 430 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 431 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 432 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 433 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 434 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 435 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 436 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 437 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 438 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 439 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 440 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 441 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 442 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 443 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 444 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 445 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 446 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 447 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 448 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 449 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 450 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 451 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 452 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 453 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 454 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 455 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 456 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 457 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 458 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 459 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 460 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 461 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 462 463 /* P0.0 */ 464 P0_0_GPIO = 0, /* GPIO controls 'out' */ 465 P0_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 466 P0_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 467 P0_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 468 P0_0_AMUXA = 4, /* Analog mux bus A */ 469 P0_0_AMUXB = 5, /* Analog mux bus B */ 470 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 471 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 472 P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 473 P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ 474 P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ 475 P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ 476 P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ 477 P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ 478 P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 479 P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ 480 P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 481 482 /* P0.1 */ 483 P0_1_GPIO = 0, /* GPIO controls 'out' */ 484 P0_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 485 P0_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 486 P0_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 487 P0_1_AMUXA = 4, /* Analog mux bus A */ 488 P0_1_AMUXB = 5, /* Analog mux bus B */ 489 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 490 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 491 P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 492 P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ 493 P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ 494 P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ 495 P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ 496 P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ 497 P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ 498 P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ 499 P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 500 501 /* P0.2 */ 502 P0_2_GPIO = 0, /* GPIO controls 'out' */ 503 P0_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 504 P0_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 505 P0_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 506 P0_2_AMUXA = 4, /* Analog mux bus A */ 507 P0_2_AMUXB = 5, /* Analog mux bus B */ 508 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 509 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 510 P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 511 P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ 512 P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ 513 P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ 514 P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ 515 P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ 516 P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ 517 P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ 518 P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ 519 520 /* P0.3 */ 521 P0_3_GPIO = 0, /* GPIO controls 'out' */ 522 P0_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 523 P0_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 524 P0_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 525 P0_3_AMUXA = 4, /* Analog mux bus A */ 526 P0_3_AMUXB = 5, /* Analog mux bus B */ 527 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 528 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 529 P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 530 P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ 531 P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ 532 P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ 533 P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ 534 P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ 535 P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ 536 P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ 537 P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ 538 539 /* P0.4 */ 540 P0_4_GPIO = 0, /* GPIO controls 'out' */ 541 P0_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 542 P0_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 543 P0_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 544 P0_4_AMUXA = 4, /* Analog mux bus A */ 545 P0_4_AMUXB = 5, /* Analog mux bus B */ 546 P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 547 P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 548 P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 549 P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ 550 P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ 551 P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ 552 P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ 553 P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ 554 P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ 555 P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ 556 P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 557 558 /* P0.5 */ 559 P0_5_GPIO = 0, /* GPIO controls 'out' */ 560 P0_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 561 P0_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 562 P0_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 563 P0_5_AMUXA = 4, /* Analog mux bus A */ 564 P0_5_AMUXB = 5, /* Analog mux bus B */ 565 P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 566 P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 567 P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 568 P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ 569 P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ 570 P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ 571 P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ 572 P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ 573 P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 574 P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ 575 P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ 576 P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ 577 578 /* P1.0 */ 579 P1_0_GPIO = 0, /* GPIO controls 'out' */ 580 P1_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 581 P1_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 582 P1_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 583 P1_0_AMUXA = 4, /* Analog mux bus A */ 584 P1_0_AMUXB = 5, /* Analog mux bus B */ 585 P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 586 P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 587 P1_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 588 P1_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ 589 P1_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ 590 P1_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ 591 P1_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ 592 P1_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ 593 P1_0_SCB7_UART_RX = 18, /* Digital Active - scb[7].uart_rx:0 */ 594 P1_0_SCB7_I2C_SCL = 19, /* Digital Active - scb[7].i2c_scl:0 */ 595 P1_0_SCB7_SPI_MOSI = 20, /* Digital Active - scb[7].spi_mosi:0 */ 596 P1_0_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ 597 598 /* P1.1 */ 599 P1_1_GPIO = 0, /* GPIO controls 'out' */ 600 P1_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 601 P1_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 602 P1_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 603 P1_1_AMUXA = 4, /* Analog mux bus A */ 604 P1_1_AMUXB = 5, /* Analog mux bus B */ 605 P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 606 P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 607 P1_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 608 P1_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ 609 P1_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ 610 P1_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ 611 P1_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ 612 P1_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ 613 P1_1_SCB7_UART_TX = 18, /* Digital Active - scb[7].uart_tx:0 */ 614 P1_1_SCB7_I2C_SDA = 19, /* Digital Active - scb[7].i2c_sda:0 */ 615 P1_1_SCB7_SPI_MISO = 20, /* Digital Active - scb[7].spi_miso:0 */ 616 P1_1_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ 617 618 /* P1.4 */ 619 P1_4_GPIO = 0, /* GPIO controls 'out' */ 620 P1_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 621 P1_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 622 P1_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 623 P1_4_AMUXA = 4, /* Analog mux bus A */ 624 P1_4_AMUXB = 5, /* Analog mux bus B */ 625 P1_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 626 P1_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 627 P1_4_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:4 */ 628 P1_4_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:1 */ 629 P1_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ 630 P1_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ 631 P1_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ 632 P1_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ 633 P1_4_SCB7_SPI_SELECT1 = 20, /* Digital Active - scb[7].spi_select1:0 */ 634 635 /* P1.5 */ 636 P1_5_GPIO = 0, /* GPIO controls 'out' */ 637 P1_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 638 P1_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 639 P1_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 640 P1_5_AMUXA = 4, /* Analog mux bus A */ 641 P1_5_AMUXB = 5, /* Analog mux bus B */ 642 P1_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 643 P1_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 644 P1_5_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:4 */ 645 P1_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:1 */ 646 P1_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ 647 P1_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ 648 P1_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ 649 P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ 650 P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ 651 652 /* P5.0 */ 653 P5_0_GPIO = 0, /* GPIO controls 'out' */ 654 P5_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 655 P5_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 656 P5_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 657 P5_0_AMUXA = 4, /* Analog mux bus A */ 658 P5_0_AMUXB = 5, /* Analog mux bus B */ 659 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 660 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 661 P5_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */ 662 P5_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ 663 P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ 664 P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ 665 P5_0_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ 666 P5_0_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ 667 P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ 668 P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ 669 P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ 670 P5_0_AUDIOSS_CLK_I2S_IF = 22, /* Digital Active - audioss.clk_i2s_if */ 671 P5_0_AUDIOSS0_CLK_I2S_IF = 22, /* Digital Active - audioss[0].clk_i2s_if:0 */ 672 P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ 673 674 /* P5.1 */ 675 P5_1_GPIO = 0, /* GPIO controls 'out' */ 676 P5_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 677 P5_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 678 P5_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 679 P5_1_AMUXA = 4, /* Analog mux bus A */ 680 P5_1_AMUXB = 5, /* Analog mux bus B */ 681 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 682 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 683 P5_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:0 */ 684 P5_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ 685 P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ 686 P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ 687 P5_1_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ 688 P5_1_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ 689 P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ 690 P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ 691 P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ 692 P5_1_AUDIOSS_TX_SCK = 22, /* Digital Active - audioss.tx_sck */ 693 P5_1_AUDIOSS0_TX_SCK = 22, /* Digital Active - audioss[0].tx_sck:0 */ 694 P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ 695 696 /* P5.2 */ 697 P5_2_GPIO = 0, /* GPIO controls 'out' */ 698 P5_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 699 P5_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 700 P5_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 701 P5_2_AMUXA = 4, /* Analog mux bus A */ 702 P5_2_AMUXB = 5, /* Analog mux bus B */ 703 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 704 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 705 P5_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:0 */ 706 P5_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ 707 P5_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ 708 P5_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ 709 P5_2_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */ 710 P5_2_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */ 711 P5_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ 712 P5_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ 713 P5_2_AUDIOSS_TX_WS = 22, /* Digital Active - audioss.tx_ws */ 714 P5_2_AUDIOSS0_TX_WS = 22, /* Digital Active - audioss[0].tx_ws:0 */ 715 716 /* P5.3 */ 717 P5_3_GPIO = 0, /* GPIO controls 'out' */ 718 P5_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 719 P5_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 720 P5_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 721 P5_3_AMUXA = 4, /* Analog mux bus A */ 722 P5_3_AMUXB = 5, /* Analog mux bus B */ 723 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 724 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 725 P5_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:0 */ 726 P5_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ 727 P5_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ 728 P5_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ 729 P5_3_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:0 */ 730 P5_3_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:0 */ 731 P5_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ 732 P5_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ 733 P5_3_AUDIOSS_TX_SDO = 22, /* Digital Active - audioss.tx_sdo */ 734 P5_3_AUDIOSS0_TX_SDO = 22, /* Digital Active - audioss[0].tx_sdo:0 */ 735 736 /* P5.4 */ 737 P5_4_GPIO = 0, /* GPIO controls 'out' */ 738 P5_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 739 P5_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 740 P5_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 741 P5_4_AMUXA = 4, /* Analog mux bus A */ 742 P5_4_AMUXB = 5, /* Analog mux bus B */ 743 P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 744 P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 745 P5_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:0 */ 746 P5_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */ 747 P5_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:34 */ 748 P5_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:34 */ 749 P5_4_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:0 */ 750 P5_4_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:0 */ 751 P5_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ 752 P5_4_AUDIOSS_RX_SCK = 22, /* Digital Active - audioss.rx_sck */ 753 P5_4_AUDIOSS0_RX_SCK = 22, /* Digital Active - audioss[0].rx_sck:0 */ 754 755 /* P5.5 */ 756 P5_5_GPIO = 0, /* GPIO controls 'out' */ 757 P5_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 758 P5_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 759 P5_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 760 P5_5_AMUXA = 4, /* Analog mux bus A */ 761 P5_5_AMUXB = 5, /* Analog mux bus B */ 762 P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 763 P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 764 P5_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:0 */ 765 P5_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ 766 P5_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ 767 P5_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ 768 P5_5_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ 769 P5_5_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ 770 P5_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ 771 P5_5_AUDIOSS_RX_WS = 22, /* Digital Active - audioss.rx_ws */ 772 P5_5_AUDIOSS0_RX_WS = 22, /* Digital Active - audioss[0].rx_ws:0 */ 773 774 /* P5.6 */ 775 P5_6_GPIO = 0, /* GPIO controls 'out' */ 776 P5_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 777 P5_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 778 P5_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 779 P5_6_AMUXA = 4, /* Analog mux bus A */ 780 P5_6_AMUXB = 5, /* Analog mux bus B */ 781 P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 782 P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 783 P5_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:0 */ 784 P5_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ 785 P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ 786 P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ 787 P5_6_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ 788 P5_6_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ 789 P5_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ 790 P5_6_AUDIOSS_RX_SDI = 22, /* Digital Active - audioss.rx_sdi */ 791 P5_6_AUDIOSS0_RX_SDI = 22, /* Digital Active - audioss[0].rx_sdi:0 */ 792 793 /* P5.7 */ 794 P5_7_GPIO = 0, /* GPIO controls 'out' */ 795 P5_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 796 P5_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 797 P5_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 798 P5_7_AMUXA = 4, /* Analog mux bus A */ 799 P5_7_AMUXB = 5, /* Analog mux bus B */ 800 P5_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 801 P5_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 802 P5_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:0 */ 803 P5_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */ 804 P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ 805 P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ 806 P5_7_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ 807 P5_7_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ 808 P5_7_SCB3_SPI_SELECT3 = 20, /* Digital Active - scb[3].spi_select3:0 */ 809 810 /* P6.0 */ 811 P6_0_GPIO = 0, /* GPIO controls 'out' */ 812 P6_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 813 P6_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 814 P6_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 815 P6_0_AMUXA = 4, /* Analog mux bus A */ 816 P6_0_AMUXB = 5, /* Analog mux bus B */ 817 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 818 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 819 P6_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 820 P6_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:0 */ 821 P6_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ 822 P6_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ 823 P6_0_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:0 */ 824 P6_0_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:0 */ 825 P6_0_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:0 */ 826 P6_0_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */ 827 P6_0_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */ 828 P6_0_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi:0 */ 829 P6_0_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ 830 P6_0_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:0 */ 831 832 /* P6.1 */ 833 P6_1_GPIO = 0, /* GPIO controls 'out' */ 834 P6_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 835 P6_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 836 P6_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 837 P6_1_AMUXA = 4, /* Analog mux bus A */ 838 P6_1_AMUXB = 5, /* Analog mux bus B */ 839 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 840 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 841 P6_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 842 P6_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */ 843 P6_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ 844 P6_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ 845 P6_1_LCD_COM39 = 12, /* Digital Deep Sleep - lcd.com[39]:0 */ 846 P6_1_LCD_SEG39 = 13, /* Digital Deep Sleep - lcd.seg[39]:0 */ 847 P6_1_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:0 */ 848 P6_1_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */ 849 P6_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */ 850 P6_1_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso:0 */ 851 P6_1_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ 852 P6_1_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:0 */ 853 854 /* P6.2 */ 855 P6_2_GPIO = 0, /* GPIO controls 'out' */ 856 P6_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 857 P6_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 858 P6_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 859 P6_2_AMUXA = 4, /* Analog mux bus A */ 860 P6_2_AMUXB = 5, /* Analog mux bus B */ 861 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 862 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 863 P6_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 864 P6_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:0 */ 865 P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ 866 P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ 867 P6_2_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ 868 P6_2_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ 869 P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ 870 P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ 871 P6_2_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:0 */ 872 873 /* P6.3 */ 874 P6_3_GPIO = 0, /* GPIO controls 'out' */ 875 P6_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 876 P6_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 877 P6_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 878 P6_3_AMUXA = 4, /* Analog mux bus A */ 879 P6_3_AMUXB = 5, /* Analog mux bus B */ 880 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 881 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 882 P6_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 883 P6_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ 884 P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ 885 P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ 886 P6_3_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ 887 P6_3_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ 888 P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ 889 P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ 890 P6_3_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:0 */ 891 892 /* P6.4 */ 893 P6_4_GPIO = 0, /* GPIO controls 'out' */ 894 P6_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 895 P6_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 896 P6_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 897 P6_4_AMUXA = 4, /* Analog mux bus A */ 898 P6_4_AMUXB = 5, /* Analog mux bus B */ 899 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 900 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 901 P6_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ 902 P6_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:0 */ 903 P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ 904 P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ 905 P6_4_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ 906 P6_4_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ 907 P6_4_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:1 */ 908 P6_4_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:2 */ 909 P6_4_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:2 */ 910 P6_4_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:2 */ 911 P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 912 P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 913 P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 914 P6_4_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:1 */ 915 P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 916 917 /* P6.5 */ 918 P6_5_GPIO = 0, /* GPIO controls 'out' */ 919 P6_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 920 P6_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 921 P6_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 922 P6_5_AMUXA = 4, /* Analog mux bus A */ 923 P6_5_AMUXB = 5, /* Analog mux bus B */ 924 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 925 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 926 P6_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 927 P6_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ 928 P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ 929 P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ 930 P6_5_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ 931 P6_5_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ 932 P6_5_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:1 */ 933 P6_5_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:2 */ 934 P6_5_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:2 */ 935 P6_5_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:2 */ 936 P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 937 P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 938 P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 939 P6_5_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:1 */ 940 P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 941 942 /* P6.6 */ 943 P6_6_GPIO = 0, /* GPIO controls 'out' */ 944 P6_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 945 P6_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 946 P6_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 947 P6_6_AMUXA = 4, /* Analog mux bus A */ 948 P6_6_AMUXB = 5, /* Analog mux bus B */ 949 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 950 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 951 P6_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 952 P6_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:0 */ 953 P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ 954 P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ 955 P6_6_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ 956 P6_6_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ 957 P6_6_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:2 */ 958 P6_6_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:2 */ 959 P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 960 P6_6_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:1 */ 961 962 /* P6.7 */ 963 P6_7_GPIO = 0, /* GPIO controls 'out' */ 964 P6_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 965 P6_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 966 P6_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 967 P6_7_AMUXA = 4, /* Analog mux bus A */ 968 P6_7_AMUXB = 5, /* Analog mux bus B */ 969 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 970 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 971 P6_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ 972 P6_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ 973 P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ 974 P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ 975 P6_7_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ 976 P6_7_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ 977 P6_7_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:2 */ 978 P6_7_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:2 */ 979 P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 980 P6_7_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:1 */ 981 982 /* P7.0 */ 983 P7_0_GPIO = 0, /* GPIO controls 'out' */ 984 P7_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 985 P7_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 986 P7_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 987 P7_0_AMUXA = 4, /* Analog mux bus A */ 988 P7_0_AMUXB = 5, /* Analog mux bus B */ 989 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 990 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 991 P7_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ 992 P7_0_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:0 */ 993 P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ 994 P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ 995 P7_0_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ 996 P7_0_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ 997 P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 998 P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 999 P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 1000 P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 1001 P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ 1002 1003 /* P7.1 */ 1004 P7_1_GPIO = 0, /* GPIO controls 'out' */ 1005 P7_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1006 P7_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1007 P7_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1008 P7_1_AMUXA = 4, /* Analog mux bus A */ 1009 P7_1_AMUXB = 5, /* Analog mux bus B */ 1010 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1011 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1012 P7_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:1 */ 1013 P7_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ 1014 P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ 1015 P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ 1016 P7_1_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ 1017 P7_1_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ 1018 P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 1019 P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 1020 P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 1021 P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 1022 1023 /* P7.2 */ 1024 P7_2_GPIO = 0, /* GPIO controls 'out' */ 1025 P7_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1026 P7_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1027 P7_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1028 P7_2_AMUXA = 4, /* Analog mux bus A */ 1029 P7_2_AMUXB = 5, /* Analog mux bus B */ 1030 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1031 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1032 P7_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ 1033 P7_2_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:0 */ 1034 P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ 1035 P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ 1036 P7_2_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ 1037 P7_2_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ 1038 P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ 1039 P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ 1040 1041 /* P7.3 */ 1042 P7_3_GPIO = 0, /* GPIO controls 'out' */ 1043 P7_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1044 P7_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1045 P7_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1046 P7_3_AMUXA = 4, /* Analog mux bus A */ 1047 P7_3_AMUXB = 5, /* Analog mux bus B */ 1048 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1049 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1050 P7_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:1 */ 1051 P7_3_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ 1052 P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ 1053 P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ 1054 P7_3_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ 1055 P7_3_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ 1056 P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ 1057 P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ 1058 1059 /* P7.7 */ 1060 P7_7_GPIO = 0, /* GPIO controls 'out' */ 1061 P7_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1062 P7_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1063 P7_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1064 P7_7_AMUXA = 4, /* Analog mux bus A */ 1065 P7_7_AMUXB = 5, /* Analog mux bus B */ 1066 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1067 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1068 P7_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 1069 P7_7_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ 1070 P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ 1071 P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ 1072 P7_7_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ 1073 P7_7_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ 1074 P7_7_SCB3_SPI_SELECT1 = 20, /* Digital Active - scb[3].spi_select1:0 */ 1075 P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ 1076 P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ 1077 1078 /* P8.0 */ 1079 P8_0_GPIO = 0, /* GPIO controls 'out' */ 1080 P8_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1081 P8_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1082 P8_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1083 P8_0_AMUXA = 4, /* Analog mux bus A */ 1084 P8_0_AMUXB = 5, /* Analog mux bus B */ 1085 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1086 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1087 P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 1088 P8_0_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:0 */ 1089 P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ 1090 P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ 1091 P8_0_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ 1092 P8_0_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ 1093 P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ 1094 P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ 1095 P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ 1096 P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ 1097 1098 /* P8.1 */ 1099 P8_1_GPIO = 0, /* GPIO controls 'out' */ 1100 P8_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1101 P8_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1102 P8_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1103 P8_1_AMUXA = 4, /* Analog mux bus A */ 1104 P8_1_AMUXB = 5, /* Analog mux bus B */ 1105 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1106 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1107 P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 1108 P8_1_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ 1109 P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ 1110 P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ 1111 P8_1_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ 1112 P8_1_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ 1113 P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ 1114 P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ 1115 P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ 1116 P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ 1117 1118 /* P8.2 */ 1119 P8_2_GPIO = 0, /* GPIO controls 'out' */ 1120 P8_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1121 P8_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1122 P8_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1123 P8_2_AMUXA = 4, /* Analog mux bus A */ 1124 P8_2_AMUXB = 5, /* Analog mux bus B */ 1125 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1126 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1127 P8_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ 1128 P8_2_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:0 */ 1129 P8_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ 1130 P8_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ 1131 P8_2_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ 1132 P8_2_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ 1133 P8_2_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ 1134 P8_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ 1135 P8_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ 1136 1137 /* P8.3 */ 1138 P8_3_GPIO = 0, /* GPIO controls 'out' */ 1139 P8_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1140 P8_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1141 P8_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1142 P8_3_AMUXA = 4, /* Analog mux bus A */ 1143 P8_3_AMUXB = 5, /* Analog mux bus B */ 1144 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1145 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1146 P8_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ 1147 P8_3_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:0 */ 1148 P8_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ 1149 P8_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ 1150 P8_3_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ 1151 P8_3_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ 1152 P8_3_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ 1153 P8_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ 1154 P8_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ 1155 1156 /* P8.4 */ 1157 P8_4_GPIO = 0, /* GPIO controls 'out' */ 1158 P8_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1159 P8_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1160 P8_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1161 P8_4_AMUXA = 4, /* Analog mux bus A */ 1162 P8_4_AMUXB = 5, /* Analog mux bus B */ 1163 P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1164 P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1165 P8_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ 1166 P8_4_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:0 */ 1167 P8_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ 1168 P8_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ 1169 P8_4_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ 1170 P8_4_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ 1171 P8_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:0 */ 1172 1173 /* P9.0 */ 1174 P9_0_GPIO = 0, /* GPIO controls 'out' */ 1175 P9_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1176 P9_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1177 P9_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1178 P9_0_AMUXA = 4, /* Analog mux bus A */ 1179 P9_0_AMUXB = 5, /* Analog mux bus B */ 1180 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1181 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1182 P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:2 */ 1183 P9_0_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:0 */ 1184 P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ 1185 P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ 1186 P9_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */ 1187 P9_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */ 1188 P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 1189 P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 1190 P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ 1191 P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 1192 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 1193 1194 /* P9.1 */ 1195 P9_1_GPIO = 0, /* GPIO controls 'out' */ 1196 P9_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1197 P9_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1198 P9_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1199 P9_1_AMUXA = 4, /* Analog mux bus A */ 1200 P9_1_AMUXB = 5, /* Analog mux bus B */ 1201 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1202 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1203 P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:2 */ 1204 P9_1_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ 1205 P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ 1206 P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ 1207 P9_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */ 1208 P9_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */ 1209 P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 1210 P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 1211 P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ 1212 P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 1213 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 1214 P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 1215 1216 /* P9.2 */ 1217 P9_2_GPIO = 0, /* GPIO controls 'out' */ 1218 P9_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1219 P9_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1220 P9_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1221 P9_2_AMUXA = 4, /* Analog mux bus A */ 1222 P9_2_AMUXB = 5, /* Analog mux bus B */ 1223 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1224 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1225 P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:2 */ 1226 P9_2_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:0 */ 1227 P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:64 */ 1228 P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:64 */ 1229 P9_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ 1230 P9_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ 1231 P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 1232 P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ 1233 P9_2_PASS_DSI_CTB_CMP0 = 22, /* Digital Active - pass.dsi_ctb_cmp0:1 */ 1234 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 1235 1236 /* P9.3 */ 1237 P9_3_GPIO = 0, /* GPIO controls 'out' */ 1238 P9_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1239 P9_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1240 P9_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1241 P9_3_AMUXA = 4, /* Analog mux bus A */ 1242 P9_3_AMUXB = 5, /* Analog mux bus B */ 1243 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1244 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1245 P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:2 */ 1246 P9_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ 1247 P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:65 */ 1248 P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:65 */ 1249 P9_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ 1250 P9_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ 1251 P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 1252 P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ 1253 P9_3_PASS_DSI_CTB_CMP1 = 22, /* Digital Active - pass.dsi_ctb_cmp1:1 */ 1254 P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 1255 P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 1256 1257 /* P9.4 */ 1258 P9_4_GPIO = 0, /* GPIO controls 'out' */ 1259 P9_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1260 P9_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1261 P9_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1262 P9_4_AMUXA = 4, /* Analog mux bus A */ 1263 P9_4_AMUXB = 5, /* Analog mux bus B */ 1264 P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1265 P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1266 P9_4_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:5 */ 1267 P9_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:2 */ 1268 P9_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:66 */ 1269 P9_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:66 */ 1270 P9_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:1 */ 1271 P9_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:1 */ 1272 P9_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:0 */ 1273 1274 /* P9.7 */ 1275 P9_7_GPIO = 0, /* GPIO controls 'out' */ 1276 P9_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1277 P9_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1278 P9_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1279 P9_7_AMUXA = 4, /* Analog mux bus A */ 1280 P9_7_AMUXB = 5, /* Analog mux bus B */ 1281 P9_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1282 P9_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1283 P9_7_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ 1284 P9_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:2 */ 1285 P9_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:69 */ 1286 P9_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:69 */ 1287 P9_7_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:1 */ 1288 P9_7_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:1 */ 1289 1290 /* P10.0 */ 1291 P10_0_GPIO = 0, /* GPIO controls 'out' */ 1292 P10_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1293 P10_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1294 P10_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1295 P10_0_AMUXA = 4, /* Analog mux bus A */ 1296 P10_0_AMUXB = 5, /* Analog mux bus B */ 1297 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1298 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1299 P10_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:2 */ 1300 P10_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:0 */ 1301 P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:70 */ 1302 P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:70 */ 1303 P10_0_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:1 */ 1304 P10_0_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:1 */ 1305 P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 1306 P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 1307 P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 1308 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 1309 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 1310 1311 /* P10.1 */ 1312 P10_1_GPIO = 0, /* GPIO controls 'out' */ 1313 P10_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1314 P10_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1315 P10_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1316 P10_1_AMUXA = 4, /* Analog mux bus A */ 1317 P10_1_AMUXB = 5, /* Analog mux bus B */ 1318 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1319 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1320 P10_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:2 */ 1321 P10_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ 1322 P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:71 */ 1323 P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:71 */ 1324 P10_1_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:1 */ 1325 P10_1_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:1 */ 1326 P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 1327 P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 1328 P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 1329 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 1330 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 1331 1332 /* P10.4 */ 1333 P10_4_GPIO = 0, /* GPIO controls 'out' */ 1334 P10_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1335 P10_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1336 P10_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1337 P10_4_AMUXA = 4, /* Analog mux bus A */ 1338 P10_4_AMUXB = 5, /* Analog mux bus B */ 1339 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1340 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1341 P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 1342 P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ 1343 P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:74 */ 1344 P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:74 */ 1345 P10_4_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:1 */ 1346 P10_4_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:1 */ 1347 P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ 1348 P10_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk:0 */ 1349 P10_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:0:0 */ 1350 1351 /* P10.5 */ 1352 P10_5_GPIO = 0, /* GPIO controls 'out' */ 1353 P10_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1354 P10_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1355 P10_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1356 P10_5_AMUXA = 4, /* Analog mux bus A */ 1357 P10_5_AMUXB = 5, /* Analog mux bus B */ 1358 P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1359 P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1360 P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ 1361 P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ 1362 P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:75 */ 1363 P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:75 */ 1364 P10_5_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:1 */ 1365 P10_5_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:1 */ 1366 P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ 1367 P10_5_AUDIOSS_PDM_DATA = 21, /* Digital Active - audioss.pdm_data:0 */ 1368 P10_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:0:0 */ 1369 1370 /* P11.0 */ 1371 P11_0_GPIO = 0, /* GPIO controls 'out' */ 1372 P11_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1373 P11_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1374 P11_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1375 P11_0_AMUXA = 4, /* Analog mux bus A */ 1376 P11_0_AMUXB = 5, /* Analog mux bus B */ 1377 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1378 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1379 P11_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 1380 P11_0_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ 1381 P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:78 */ 1382 P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:78 */ 1383 P11_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:1 */ 1384 P11_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:1 */ 1385 P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ 1386 P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ 1387 P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ 1388 P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ 1389 P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ 1390 1391 /* P11.1 */ 1392 P11_1_GPIO = 0, /* GPIO controls 'out' */ 1393 P11_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1394 P11_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1395 P11_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1396 P11_1_AMUXA = 4, /* Analog mux bus A */ 1397 P11_1_AMUXB = 5, /* Analog mux bus B */ 1398 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1399 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1400 P11_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 1401 P11_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ 1402 P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:79 */ 1403 P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:79 */ 1404 P11_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:1 */ 1405 P11_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:1 */ 1406 P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ 1407 P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ 1408 P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ 1409 P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ 1410 P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ 1411 1412 /* P11.2 */ 1413 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1414 P11_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1415 P11_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1416 P11_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1417 P11_2_AMUXA = 4, /* Analog mux bus A */ 1418 P11_2_AMUXB = 5, /* Analog mux bus B */ 1419 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1420 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1421 P11_2_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ 1422 P11_2_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */ 1423 P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:80 */ 1424 P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:80 */ 1425 P11_2_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:1 */ 1426 P11_2_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:1 */ 1427 P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 1428 P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:1 */ 1429 P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:1 */ 1430 1431 /* P11.3 */ 1432 P11_3_GPIO = 0, /* GPIO controls 'out' */ 1433 P11_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1434 P11_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1435 P11_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1436 P11_3_AMUXA = 4, /* Analog mux bus A */ 1437 P11_3_AMUXB = 5, /* Analog mux bus B */ 1438 P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1439 P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1440 P11_3_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ 1441 P11_3_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ 1442 P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:81 */ 1443 P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:81 */ 1444 P11_3_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:1 */ 1445 P11_3_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:1 */ 1446 P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 1447 P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:1 */ 1448 P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:1 */ 1449 P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 1450 1451 /* P11.4 */ 1452 P11_4_GPIO = 0, /* GPIO controls 'out' */ 1453 P11_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1454 P11_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1455 P11_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1456 P11_4_AMUXA = 4, /* Analog mux bus A */ 1457 P11_4_AMUXB = 5, /* Analog mux bus B */ 1458 P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1459 P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1460 P11_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ 1461 P11_4_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ 1462 P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:82 */ 1463 P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:82 */ 1464 P11_4_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:1 */ 1465 P11_4_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:1 */ 1466 P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 1467 P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:1 */ 1468 P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ 1469 1470 /* P11.5 */ 1471 P11_5_GPIO = 0, /* GPIO controls 'out' */ 1472 P11_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1473 P11_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1474 P11_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1475 P11_5_AMUXA = 4, /* Analog mux bus A */ 1476 P11_5_AMUXB = 5, /* Analog mux bus B */ 1477 P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1478 P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1479 P11_5_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ 1480 P11_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ 1481 P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:83 */ 1482 P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:83 */ 1483 P11_5_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:1 */ 1484 P11_5_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:1 */ 1485 P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 1486 P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:1 */ 1487 1488 /* P11.6 */ 1489 P11_6_GPIO = 0, /* GPIO controls 'out' */ 1490 P11_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1491 P11_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1492 P11_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1493 P11_6_AMUXA = 4, /* Analog mux bus A */ 1494 P11_6_AMUXB = 5, /* Analog mux bus B */ 1495 P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1496 P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1497 P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:84 */ 1498 P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:84 */ 1499 P11_6_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:1 */ 1500 P11_6_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:1 */ 1501 P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 1502 P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:1 */ 1503 1504 /* P11.7 */ 1505 P11_7_GPIO = 0, /* GPIO controls 'out' */ 1506 P11_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1507 P11_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1508 P11_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1509 P11_7_AMUXA = 4, /* Analog mux bus A */ 1510 P11_7_AMUXB = 5, /* Analog mux bus B */ 1511 P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1512 P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1513 P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ 1514 1515 /* P12.0 */ 1516 P12_0_GPIO = 0, /* GPIO controls 'out' */ 1517 P12_0_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1518 P12_0_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1519 P12_0_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1520 P12_0_AMUXA = 4, /* Analog mux bus A */ 1521 P12_0_AMUXB = 5, /* Analog mux bus B */ 1522 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1523 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1524 P12_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:3 */ 1525 P12_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ 1526 P12_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:85 */ 1527 P12_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:85 */ 1528 P12_0_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:1 */ 1529 P12_0_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:1 */ 1530 P12_0_SMIF_SPI_DATA4 = 17, /* Digital Active - smif.spi_data4 */ 1531 P12_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:0 */ 1532 P12_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:0 */ 1533 P12_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:0 */ 1534 P12_0_PERI_TR_IO_INPUT24 = 24, /* Digital Active - peri.tr_io_input[24]:0 */ 1535 1536 /* P12.1 */ 1537 P12_1_GPIO = 0, /* GPIO controls 'out' */ 1538 P12_1_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1539 P12_1_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1540 P12_1_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1541 P12_1_AMUXA = 4, /* Analog mux bus A */ 1542 P12_1_AMUXB = 5, /* Analog mux bus B */ 1543 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1544 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1545 P12_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:3 */ 1546 P12_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ 1547 P12_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:86 */ 1548 P12_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:86 */ 1549 P12_1_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:1 */ 1550 P12_1_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:1 */ 1551 P12_1_SMIF_SPI_DATA5 = 17, /* Digital Active - smif.spi_data5 */ 1552 P12_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:0 */ 1553 P12_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:0 */ 1554 P12_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:0 */ 1555 P12_1_PERI_TR_IO_INPUT25 = 24, /* Digital Active - peri.tr_io_input[25]:0 */ 1556 1557 /* P12.2 */ 1558 P12_2_GPIO = 0, /* GPIO controls 'out' */ 1559 P12_2_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1560 P12_2_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1561 P12_2_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1562 P12_2_AMUXA = 4, /* Analog mux bus A */ 1563 P12_2_AMUXB = 5, /* Analog mux bus B */ 1564 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1565 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1566 P12_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:3 */ 1567 P12_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ 1568 P12_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:87 */ 1569 P12_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:87 */ 1570 P12_2_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:1 */ 1571 P12_2_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:1 */ 1572 P12_2_SMIF_SPI_DATA6 = 17, /* Digital Active - smif.spi_data6 */ 1573 P12_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:0 */ 1574 P12_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:0 */ 1575 1576 /* P12.3 */ 1577 P12_3_GPIO = 0, /* GPIO controls 'out' */ 1578 P12_3_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1579 P12_3_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1580 P12_3_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1581 P12_3_AMUXA = 4, /* Analog mux bus A */ 1582 P12_3_AMUXB = 5, /* Analog mux bus B */ 1583 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1584 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1585 P12_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:3 */ 1586 P12_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ 1587 P12_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:88 */ 1588 P12_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:88 */ 1589 P12_3_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:1 */ 1590 P12_3_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:1 */ 1591 P12_3_SMIF_SPI_DATA7 = 17, /* Digital Active - smif.spi_data7 */ 1592 P12_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:0 */ 1593 P12_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:0 */ 1594 1595 /* P12.4 */ 1596 P12_4_GPIO = 0, /* GPIO controls 'out' */ 1597 P12_4_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1598 P12_4_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1599 P12_4_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1600 P12_4_AMUXA = 4, /* Analog mux bus A */ 1601 P12_4_AMUXB = 5, /* Analog mux bus B */ 1602 P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1603 P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1604 P12_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:3 */ 1605 P12_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ 1606 P12_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:89 */ 1607 P12_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:89 */ 1608 P12_4_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:1 */ 1609 P12_4_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:1 */ 1610 P12_4_SMIF_SPI_SELECT3 = 17, /* Digital Active - smif.spi_select3 */ 1611 P12_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:0 */ 1612 P12_4_AUDIOSS_PDM_CLK = 21, /* Digital Active - audioss.pdm_clk:1 */ 1613 P12_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:1:0 */ 1614 1615 /* P12.5 */ 1616 P12_5_GPIO = 0, /* GPIO controls 'out' */ 1617 P12_5_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1618 P12_5_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1619 P12_5_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1620 P12_5_AMUXA = 4, /* Analog mux bus A */ 1621 P12_5_AMUXB = 5, /* Analog mux bus B */ 1622 P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1623 P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1624 P12_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:3 */ 1625 P12_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ 1626 P12_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:90 */ 1627 P12_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:90 */ 1628 P12_5_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:1 */ 1629 P12_5_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:1 */ 1630 P12_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:0 */ 1631 P12_5_AUDIOSS_PDM_DATA = 21, /* Digital Active - audioss.pdm_data:1 */ 1632 P12_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:1:0 */ 1633 1634 /* P12.6 */ 1635 P12_6_GPIO = 0, /* GPIO controls 'out' */ 1636 P12_6_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1637 P12_6_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1638 P12_6_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1639 P12_6_AMUXA = 4, /* Analog mux bus A */ 1640 P12_6_AMUXB = 5, /* Analog mux bus B */ 1641 P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1642 P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1643 P12_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:3 */ 1644 P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ 1645 P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:91 */ 1646 P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:91 */ 1647 P12_6_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:1 */ 1648 P12_6_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:1 */ 1649 P12_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */ 1650 1651 /* P12.7 */ 1652 P12_7_GPIO = 0, /* GPIO controls 'out' */ 1653 P12_7_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 1654 P12_7_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 1655 P12_7_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 1656 P12_7_AMUXA = 4, /* Analog mux bus A */ 1657 P12_7_AMUXB = 5, /* Analog mux bus B */ 1658 P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1659 P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1660 P12_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:3 */ 1661 P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ 1662 P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */ 1663 P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ 1664 P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ 1665 P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */ 1666 1667 /* USBDP */ 1668 USBDP_GPIO = 0, /* GPIO controls 'out' */ 1669 1670 /* USBDM */ 1671 USBDM_GPIO = 0 /* GPIO controls 'out' */ 1672 } en_hsiom_sel_t; 1673 1674 #endif /* _GPIO_PSOC6_01_80_WLCSP_H_ */ 1675 1676 1677 /* [] END OF FILE */ 1678
