1 /***************************************************************************//** 2 * \file gpio_fx3g2_169_bga.h 3 * 4 * \brief 5 * FX3G2 device GPIO header for 169-BGA package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_FX3G2_169_BGA_H_ 28 #define _GPIO_FX3G2_169_BGA_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_LGA, 36 CY_GPIO_PACKAGE_CSP, 37 CY_GPIO_PACKAGE_WLCSP, 38 CY_GPIO_PACKAGE_LQFP, 39 CY_GPIO_PACKAGE_TQFP, 40 CY_GPIO_PACKAGE_TEQFP, 41 CY_GPIO_PACKAGE_SMT, 42 }; 43 44 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_BGA 45 #define CY_GPIO_PIN_COUNT 169u 46 47 /* AMUXBUS Segments */ 48 enum 49 { 50 AMUXBUS_FLASH, 51 AMUXBUS_LVDS, 52 AMUXBUS_MAIN, 53 AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, 54 AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, 55 }; 56 57 /* AMUX Splitter Controls */ 58 typedef enum 59 { 60 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_LVDS */ 61 AMUX_SPLIT_CTL_2 = 0x0002u /* Left = AMUXBUS_FLASH; Right = AMUXBUS_MAIN */ 62 } cy_en_amux_split_t; 63 64 /* Port List */ 65 /* PORT 0 (GPIO) */ 66 #define P0_0_PORT GPIO_PRT0 67 #define P0_0_PIN 0u 68 #define P0_0_NUM 0u 69 #define P0_1_PORT GPIO_PRT0 70 #define P0_1_PIN 1u 71 #define P0_1_NUM 1u 72 73 /* PORT 1 (GPIO) */ 74 #define P1_0_PORT GPIO_PRT1 75 #define P1_0_PIN 0u 76 #define P1_0_NUM 0u 77 #define P1_0_AMUXSEGMENT AMUXBUS_MAIN 78 #define P1_1_PORT GPIO_PRT1 79 #define P1_1_PIN 1u 80 #define P1_1_NUM 1u 81 #define P1_1_AMUXSEGMENT AMUXBUS_MAIN 82 83 /* PORT 4 (GPIO) */ 84 #define P4_0_PORT GPIO_PRT4 85 #define P4_0_PIN 0u 86 #define P4_0_NUM 0u 87 #define P4_1_PORT GPIO_PRT4 88 #define P4_1_PIN 1u 89 #define P4_1_NUM 1u 90 #define P4_2_PORT GPIO_PRT4 91 #define P4_2_PIN 2u 92 #define P4_2_NUM 2u 93 #define P4_3_PORT GPIO_PRT4 94 #define P4_3_PIN 3u 95 #define P4_3_NUM 3u 96 #define P4_4_PORT GPIO_PRT4 97 #define P4_4_PIN 4u 98 #define P4_4_NUM 4u 99 100 /* PORT 5 (GPIO) */ 101 #define P5_0_PORT GPIO_PRT5 102 #define P5_0_PIN 0u 103 #define P5_0_NUM 0u 104 #define P5_1_PORT GPIO_PRT5 105 #define P5_1_PIN 1u 106 #define P5_1_NUM 1u 107 108 /* PORT 6 (GPIO) */ 109 #define P6_0_PORT GPIO_PRT6 110 #define P6_0_PIN 0u 111 #define P6_0_NUM 0u 112 #define P6_0_AMUXSEGMENT AMUXBUS_MAIN 113 #define P6_1_PORT GPIO_PRT6 114 #define P6_1_PIN 1u 115 #define P6_1_NUM 1u 116 #define P6_1_AMUXSEGMENT AMUXBUS_MAIN 117 #define P6_2_PORT GPIO_PRT6 118 #define P6_2_PIN 2u 119 #define P6_2_NUM 2u 120 #define P6_2_AMUXSEGMENT AMUXBUS_MAIN 121 #define P6_3_PORT GPIO_PRT6 122 #define P6_3_PIN 3u 123 #define P6_3_NUM 3u 124 #define P6_3_AMUXSEGMENT AMUXBUS_MAIN 125 #define P6_4_PORT GPIO_PRT6 126 #define P6_4_PIN 4u 127 #define P6_4_NUM 4u 128 #define P6_4_AMUXSEGMENT AMUXBUS_MAIN 129 130 /* PORT 7 (GPIO) */ 131 #define P7_0_PORT GPIO_PRT7 132 #define P7_0_PIN 0u 133 #define P7_0_NUM 0u 134 #define P7_0_AMUXSEGMENT AMUXBUS_MAIN 135 #define P7_1_PORT GPIO_PRT7 136 #define P7_1_PIN 1u 137 #define P7_1_NUM 1u 138 #define P7_1_AMUXSEGMENT AMUXBUS_MAIN 139 #define P7_2_PORT GPIO_PRT7 140 #define P7_2_PIN 2u 141 #define P7_2_NUM 2u 142 #define P7_2_AMUXSEGMENT AMUXBUS_MAIN 143 #define P7_3_PORT GPIO_PRT7 144 #define P7_3_PIN 3u 145 #define P7_3_NUM 3u 146 #define P7_3_AMUXSEGMENT AMUXBUS_MAIN 147 #define P7_4_PORT GPIO_PRT7 148 #define P7_4_PIN 4u 149 #define P7_4_NUM 4u 150 #define P7_4_AMUXSEGMENT AMUXBUS_MAIN 151 #define P7_5_PORT GPIO_PRT7 152 #define P7_5_PIN 5u 153 #define P7_5_NUM 5u 154 #define P7_5_AMUXSEGMENT AMUXBUS_MAIN 155 #define P7_6_PORT GPIO_PRT7 156 #define P7_6_PIN 6u 157 #define P7_6_NUM 6u 158 #define P7_6_AMUXSEGMENT AMUXBUS_MAIN 159 #define P7_7_PORT GPIO_PRT7 160 #define P7_7_PIN 7u 161 #define P7_7_NUM 7u 162 #define P7_7_AMUXSEGMENT AMUXBUS_MAIN 163 164 /* PORT 8 (GPIO) */ 165 #define P8_0_PORT GPIO_PRT8 166 #define P8_0_PIN 0u 167 #define P8_0_NUM 0u 168 #define P8_1_PORT GPIO_PRT8 169 #define P8_1_PIN 1u 170 #define P8_1_NUM 1u 171 #define P8_2_PORT GPIO_PRT8 172 #define P8_2_PIN 2u 173 #define P8_2_NUM 2u 174 #define P8_3_PORT GPIO_PRT8 175 #define P8_3_PIN 3u 176 #define P8_3_NUM 3u 177 #define P8_4_PORT GPIO_PRT8 178 #define P8_4_PIN 4u 179 #define P8_4_NUM 4u 180 #define P8_5_PORT GPIO_PRT8 181 #define P8_5_PIN 5u 182 #define P8_5_NUM 5u 183 #define P8_6_PORT GPIO_PRT8 184 #define P8_6_PIN 6u 185 #define P8_6_NUM 6u 186 #define P8_6_AMUXSEGMENT AMUXBUS_MAIN 187 #define P8_7_PORT GPIO_PRT8 188 #define P8_7_PIN 7u 189 #define P8_7_NUM 7u 190 #define P8_7_AMUXSEGMENT AMUXBUS_MAIN 191 192 /* PORT 9 (GPIO) */ 193 #define P9_0_PORT GPIO_PRT9 194 #define P9_0_PIN 0u 195 #define P9_0_NUM 0u 196 #define P9_1_PORT GPIO_PRT9 197 #define P9_1_PIN 1u 198 #define P9_1_NUM 1u 199 #define P9_2_PORT GPIO_PRT9 200 #define P9_2_PIN 2u 201 #define P9_2_NUM 2u 202 #define P9_3_PORT GPIO_PRT9 203 #define P9_3_PIN 3u 204 #define P9_3_NUM 3u 205 #define P9_4_PORT GPIO_PRT9 206 #define P9_4_PIN 4u 207 #define P9_4_NUM 4u 208 #define P9_5_PORT GPIO_PRT9 209 #define P9_5_PIN 5u 210 #define P9_5_NUM 5u 211 #define P9_6_PORT GPIO_PRT9 212 #define P9_6_PIN 6u 213 #define P9_6_NUM 6u 214 #define P9_7_PORT GPIO_PRT9 215 #define P9_7_PIN 7u 216 #define P9_7_NUM 7u 217 218 /* PORT 10 (GPIO_OVT) */ 219 #define P10_0_PORT GPIO_PRT10 220 #define P10_0_PIN 0u 221 #define P10_0_NUM 0u 222 #define P10_1_PORT GPIO_PRT10 223 #define P10_1_PIN 1u 224 #define P10_1_NUM 1u 225 226 /* PORT 11 (GPIO) */ 227 #define P11_0_PORT GPIO_PRT11 228 #define P11_0_PIN 0u 229 #define P11_0_NUM 0u 230 #define P11_1_PORT GPIO_PRT11 231 #define P11_1_PIN 1u 232 #define P11_1_NUM 1u 233 #define P11_2_PORT GPIO_PRT11 234 #define P11_2_PIN 2u 235 #define P11_2_NUM 2u 236 #define P11_3_PORT GPIO_PRT11 237 #define P11_3_PIN 3u 238 #define P11_3_NUM 3u 239 #define P11_4_PORT GPIO_PRT11 240 #define P11_4_PIN 4u 241 #define P11_4_NUM 4u 242 #define P11_5_PORT GPIO_PRT11 243 #define P11_5_PIN 5u 244 #define P11_5_NUM 5u 245 246 /* PORT 12 (AUX) */ 247 #define USBDM_PORT GPIO_PRT12 248 #define USBDM_PIN 0u 249 #define USBDM_NUM 0u 250 #define P12_0_PORT GPIO_PRT12 251 #define P12_0_PIN 0u 252 #define P12_0_NUM 0u 253 #define USBDP_PORT GPIO_PRT12 254 #define USBDP_PIN 1u 255 #define USBDP_NUM 1u 256 #define P12_1_PORT GPIO_PRT12 257 #define P12_1_PIN 1u 258 #define P12_1_NUM 1u 259 260 /* PORT 13 (GPIO) */ 261 #define P13_0_PORT GPIO_PRT13 262 #define P13_0_PIN 0u 263 #define P13_0_NUM 0u 264 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 265 #define P13_1_PORT GPIO_PRT13 266 #define P13_1_PIN 1u 267 #define P13_1_NUM 1u 268 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 269 270 /* Analog Connections */ 271 #define LVDS2USB32SS_ADC_A_IN0_PORT 1u 272 #define LVDS2USB32SS_ADC_A_IN0_PIN 0u 273 #define LVDS2USB32SS_ADC_A_IN1_PORT 1u 274 #define LVDS2USB32SS_ADC_A_IN1_PIN 1u 275 #define SRSS_ADFT_PIN0_PORT 13u 276 #define SRSS_ADFT_PIN0_PIN 0u 277 #define SRSS_ADFT_PIN1_PORT 13u 278 #define SRSS_ADFT_PIN1_PIN 1u 279 #define SRSS_ECO_IN_PORT 5u 280 #define SRSS_ECO_IN_PIN 0u 281 #define SRSS_ECO_OUT_PORT 5u 282 #define SRSS_ECO_OUT_PIN 1u 283 284 /* HSIOM Connections */ 285 typedef enum 286 { 287 /* Generic HSIOM connections */ 288 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 289 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 290 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 291 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 292 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 293 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 294 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 295 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 296 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 297 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 298 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 299 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 300 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 301 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 302 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 303 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 304 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 305 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 306 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 307 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 308 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 309 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 310 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 311 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 312 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 313 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 314 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 315 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 316 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 317 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 318 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 319 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 320 321 /* P0.0 */ 322 P0_0_GPIO = 0, /* GPIO controls 'out' */ 323 P0_0_AMUXA = 4, /* Analog mux bus A */ 324 P0_0_AMUXB = 5, /* Analog mux bus B */ 325 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 326 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 327 P0_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 328 P0_0_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 329 P0_0_LVDS2USB32SS_LNK1_L3_ENTRY_GPIO_I = 28, /* Digital Deep Sleep - lvds2usb32ss.lnk1_l3_entry_gpio_i:3 */ 330 331 /* P0.1 */ 332 P0_1_GPIO = 0, /* GPIO controls 'out' */ 333 P0_1_AMUXA = 4, /* Analog mux bus A */ 334 P0_1_AMUXB = 5, /* Analog mux bus B */ 335 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 336 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 337 P0_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 338 P0_1_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 339 340 /* P1.0 */ 341 P1_0_GPIO = 0, /* GPIO controls 'out' */ 342 P1_0_AMUXA = 4, /* Analog mux bus A */ 343 P1_0_AMUXB = 5, /* Analog mux bus B */ 344 P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 345 P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 346 P1_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3] */ 347 P1_0_TDM_TDM_RX_FSYNC = 16, /* Digital Active - tdm.tdm_rx_fsync:1 */ 348 P1_0_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ 349 P1_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ 350 P1_0_USBHSDEV_GPIO_DDFT0 = 23, /* Digital Active - usbhsdev.gpio_ddft0 */ 351 P1_0_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:2 */ 352 353 /* P1.1 */ 354 P1_1_GPIO = 0, /* GPIO controls 'out' */ 355 P1_1_AMUXA = 4, /* Analog mux bus A */ 356 P1_1_AMUXB = 5, /* Analog mux bus B */ 357 P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 358 P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 359 P1_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3] */ 360 P1_1_TDM_TDM_RX_MCK = 16, /* Digital Active - tdm.tdm_rx_mck:1 */ 361 P1_1_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ 362 P1_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ 363 P1_1_USBHSDEV_GPIO_DDFT1 = 23, /* Digital Active - usbhsdev.gpio_ddft1 */ 364 P1_1_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:2 */ 365 366 /* P4.0 */ 367 P4_0_GPIO = 0, /* GPIO controls 'out' */ 368 P4_0_AMUXA = 4, /* Analog mux bus A */ 369 P4_0_AMUXB = 5, /* Analog mux bus B */ 370 P4_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 371 P4_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 372 P4_0_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ 373 P4_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 374 P4_0_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 375 P4_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 376 377 /* P4.1 */ 378 P4_1_GPIO = 0, /* GPIO controls 'out' */ 379 P4_1_AMUXA = 4, /* Analog mux bus A */ 380 P4_1_AMUXB = 5, /* Analog mux bus B */ 381 P4_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 382 P4_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 383 P4_1_PDM0_PDM_CLK0 = 17, /* Digital Active - pdm[0].pdm_clk[0]:0 */ 384 P4_1_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:1 */ 385 P4_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:1 */ 386 P4_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ 387 P4_1_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ 388 P4_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 389 390 /* P4.2 */ 391 P4_2_GPIO = 0, /* GPIO controls 'out' */ 392 P4_2_AMUXA = 4, /* Analog mux bus A */ 393 P4_2_AMUXB = 5, /* Analog mux bus B */ 394 P4_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 395 P4_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 396 P4_2_PDM0_PDM_DATA0 = 17, /* Digital Active - pdm[0].pdm_data[0]:0 */ 397 P4_2_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:1 */ 398 P4_2_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:1 */ 399 P4_2_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ 400 P4_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0]:0 */ 401 P4_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 402 403 /* P4.3 */ 404 P4_3_GPIO = 0, /* GPIO controls 'out' */ 405 P4_3_AMUXA = 4, /* Analog mux bus A */ 406 P4_3_AMUXB = 5, /* Analog mux bus B */ 407 P4_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 408 P4_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 409 P4_3_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ 410 P4_3_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ 411 P4_3_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk */ 412 P4_3_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ 413 P4_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1]:0 */ 414 P4_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 415 P4_3_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 416 417 /* P4.4 */ 418 P4_4_GPIO = 0, /* GPIO controls 'out' */ 419 P4_4_AMUXA = 4, /* Analog mux bus A */ 420 P4_4_AMUXB = 5, /* Analog mux bus B */ 421 P4_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 422 P4_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 423 P4_4_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ 424 P4_4_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ 425 P4_4_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0 */ 426 P4_4_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ 427 P4_4_CANFD0_TTCAN_RX = 22, /* Digital Active - canfd[0].ttcan_rx:1 */ 428 P4_4_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock:0 */ 429 P4_4_LVDS2USB32SS_LNK0_L3_ENTRY_GPIO_I = 28, /* Digital Deep Sleep - lvds2usb32ss.lnk0_l3_entry_gpio_i:3 */ 430 P4_4_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 431 432 /* P5.0 */ 433 P5_0_GPIO = 0, /* GPIO controls 'out' */ 434 P5_0_AMUXA = 4, /* Analog mux bus A */ 435 P5_0_AMUXB = 5, /* Analog mux bus B */ 436 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 437 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 438 P5_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 439 440 /* P5.1 */ 441 P5_1_GPIO = 0, /* GPIO controls 'out' */ 442 P5_1_AMUXA = 4, /* Analog mux bus A */ 443 P5_1_AMUXB = 5, /* Analog mux bus B */ 444 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 445 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 446 P5_1_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 447 P5_1_USBHSDEV_TEST_PLL_REFCLK_I = 18, /* Digital Active - usbhsdev.test_pll_refclk_i */ 448 449 /* P6.0 */ 450 P6_0_GPIO = 0, /* GPIO controls 'out' */ 451 P6_0_AMUXA = 4, /* Analog mux bus A */ 452 P6_0_AMUXB = 5, /* Analog mux bus B */ 453 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 454 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 455 P6_0_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ 456 P6_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:1 */ 457 P6_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:1 */ 458 P6_0_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk */ 459 P6_0_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ 460 P6_0_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 461 P6_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:4 */ 462 463 /* P6.1 */ 464 P6_1_GPIO = 0, /* GPIO controls 'out' */ 465 P6_1_AMUXA = 4, /* Analog mux bus A */ 466 P6_1_AMUXB = 5, /* Analog mux bus B */ 467 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 468 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 469 P6_1_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 470 P6_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:1 */ 471 P6_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:1 */ 472 P6_1_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0 */ 473 P6_1_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ 474 P6_1_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 475 P6_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:4 */ 476 477 /* P6.2 */ 478 P6_2_GPIO = 0, /* GPIO controls 'out' */ 479 P6_2_AMUXA = 4, /* Analog mux bus A */ 480 P6_2_AMUXB = 5, /* Analog mux bus B */ 481 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 482 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 483 P6_2_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ 484 P6_2_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi */ 485 P6_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0]:1 */ 486 P6_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:4 */ 487 488 /* P6.3 */ 489 P6_3_GPIO = 0, /* GPIO controls 'out' */ 490 P6_3_AMUXA = 4, /* Analog mux bus A */ 491 P6_3_AMUXB = 5, /* Analog mux bus B */ 492 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 493 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 494 P6_3_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ 495 P6_3_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso */ 496 P6_3_LVDS2USB32SS_LVDS_USEC_PULSE_O = 23, /* Digital Active - lvds2usb32ss.lvds_usec_pulse_o:2 */ 497 P6_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1]:1 */ 498 P6_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:4 */ 499 500 /* P6.4 */ 501 P6_4_GPIO = 0, /* GPIO controls 'out' */ 502 P6_4_SMIF_SPI_SELECT3 = 17, /* Digital Active - smif.spi_select3 */ 503 P6_4_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock:4 */ 504 505 /* P7.0 */ 506 P7_0_GPIO = 0, /* GPIO controls 'out' */ 507 P7_0_SCB0_I2C_SCL = 13, /* Digital Deep Sleep - scb[0].i2c_scl:1 */ 508 P7_0_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 509 P7_0_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:1 */ 510 P7_0_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk */ 511 512 /* P7.1 */ 513 P7_1_GPIO = 0, /* GPIO controls 'out' */ 514 P7_1_AMUXA = 4, /* Analog mux bus A */ 515 P7_1_AMUXB = 5, /* Analog mux bus B */ 516 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 517 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 518 P7_1_SCB0_I2C_SDA = 13, /* Digital Deep Sleep - scb[0].i2c_sda:1 */ 519 P7_1_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 520 P7_1_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:1 */ 521 P7_1_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0 */ 522 P7_1_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ 523 P7_1_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 524 525 /* P7.2 */ 526 P7_2_GPIO = 0, /* GPIO controls 'out' */ 527 P7_2_AMUXA = 4, /* Analog mux bus A */ 528 P7_2_AMUXB = 5, /* Analog mux bus B */ 529 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 530 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 531 P7_2_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 532 P7_2_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ 533 P7_2_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi */ 534 P7_2_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ 535 P7_2_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ 536 537 /* P7.3 */ 538 P7_3_GPIO = 0, /* GPIO controls 'out' */ 539 P7_3_AMUXA = 4, /* Analog mux bus A */ 540 P7_3_AMUXB = 5, /* Analog mux bus B */ 541 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 542 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 543 P7_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 544 P7_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ 545 P7_3_SCB0_UART_RTS = 19, /* Digital Active - scb[0].uart_rts:0 */ 546 P7_3_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso */ 547 P7_3_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ 548 P7_3_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0]:2 */ 549 550 /* P7.4 */ 551 P7_4_GPIO = 0, /* GPIO controls 'out' */ 552 P7_4_AMUXA = 4, /* Analog mux bus A */ 553 P7_4_AMUXB = 5, /* Analog mux bus B */ 554 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 555 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 556 P7_4_SMIF_SPI_DATA4 = 17, /* Digital Active - smif.spi_data4 */ 557 P7_4_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 558 P7_4_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ 559 P7_4_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1]:2 */ 560 561 /* P7.5 */ 562 P7_5_GPIO = 0, /* GPIO controls 'out' */ 563 P7_5_AMUXA = 4, /* Analog mux bus A */ 564 P7_5_AMUXB = 5, /* Analog mux bus B */ 565 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 566 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 567 P7_5_SMIF_SPI_DATA5 = 17, /* Digital Active - smif.spi_data5 */ 568 569 /* P7.6 */ 570 P7_6_GPIO = 0, /* GPIO controls 'out' */ 571 P7_6_AMUXA = 4, /* Analog mux bus A */ 572 P7_6_AMUXB = 5, /* Analog mux bus B */ 573 P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 574 P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 575 P7_6_SMIF_SPI_DATA6 = 17, /* Digital Active - smif.spi_data6 */ 576 P7_6_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 577 P7_6_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 578 579 /* P7.7 */ 580 P7_7_GPIO = 0, /* GPIO controls 'out' */ 581 P7_7_AMUXA = 4, /* Analog mux bus A */ 582 P7_7_AMUXB = 5, /* Analog mux bus B */ 583 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 584 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 585 P7_7_SMIF_SPI_DATA7 = 17, /* Digital Active - smif.spi_data7 */ 586 P7_7_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 587 P7_7_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 588 589 /* P8.0 */ 590 P8_0_GPIO = 0, /* GPIO controls 'out' */ 591 P8_0_AMUXA = 4, /* Analog mux bus A */ 592 P8_0_AMUXB = 5, /* Analog mux bus B */ 593 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 594 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 595 P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0] */ 596 P8_0_TDM_TDM_TX_SCK = 16, /* Digital Active - tdm.tdm_tx_sck:1 */ 597 P8_0_PDM0_PDM_CLK0 = 17, /* Digital Active - pdm[0].pdm_clk[0]:1 */ 598 P8_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ 599 P8_0_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ 600 P8_0_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ 601 P8_0_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ 602 P8_0_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:3 */ 603 P8_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 604 605 /* P8.1 */ 606 P8_1_GPIO = 0, /* GPIO controls 'out' */ 607 P8_1_AMUXA = 4, /* Analog mux bus A */ 608 P8_1_AMUXB = 5, /* Analog mux bus B */ 609 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 610 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 611 P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0] */ 612 P8_1_TDM_TDM_RX_SCK = 16, /* Digital Active - tdm.tdm_rx_sck:1 */ 613 P8_1_PDM0_PDM_DATA0 = 17, /* Digital Active - pdm[0].pdm_data[0]:1 */ 614 P8_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ 615 P8_1_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ 616 P8_1_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ 617 P8_1_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 618 P8_1_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:3 */ 619 P8_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 620 621 /* P8.2 */ 622 P8_2_GPIO = 0, /* GPIO controls 'out' */ 623 P8_2_AMUXA = 4, /* Analog mux bus A */ 624 P8_2_AMUXB = 5, /* Analog mux bus B */ 625 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 626 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 627 P8_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1] */ 628 P8_2_TDM_TDM_TX_FSYNC = 16, /* Digital Active - tdm.tdm_tx_fsync:1 */ 629 P8_2_PDM0_PDM_CLK1 = 17, /* Digital Active - pdm[0].pdm_clk[1]:1 */ 630 P8_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ 631 P8_2_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ 632 P8_2_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 633 P8_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0]:3 */ 634 P8_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 635 P8_2_LVDS2USB32SS_LNK0_L3_ENTRY_GPIO_I = 28, /* Digital Deep Sleep - lvds2usb32ss.lnk0_l3_entry_gpio_i:2 */ 636 637 /* P8.3 */ 638 P8_3_GPIO = 0, /* GPIO controls 'out' */ 639 P8_3_AMUXA = 4, /* Analog mux bus A */ 640 P8_3_AMUXB = 5, /* Analog mux bus B */ 641 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 642 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 643 P8_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1] */ 644 P8_3_TDM_TDM_TX_MCK = 16, /* Digital Active - tdm.tdm_tx_mck:1 */ 645 P8_3_PDM0_PDM_DATA1 = 17, /* Digital Active - pdm[0].pdm_data[1]:1 */ 646 P8_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ 647 P8_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ 648 P8_3_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 649 P8_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1]:3 */ 650 P8_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 651 P8_3_LVDS2USB32SS_LNK1_L3_ENTRY_GPIO_I = 28, /* Digital Deep Sleep - lvds2usb32ss.lnk1_l3_entry_gpio_i:2 */ 652 653 /* P8.4 */ 654 P8_4_GPIO = 0, /* GPIO controls 'out' */ 655 P8_4_AMUXA = 4, /* Analog mux bus A */ 656 P8_4_AMUXB = 5, /* Analog mux bus B */ 657 P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 658 P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 659 P8_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2] */ 660 P8_4_TDM_TDM_RX_SD = 16, /* Digital Active - tdm.tdm_rx_sd:1 */ 661 P8_4_PDM0_PDM_CLK1 = 17, /* Digital Active - pdm[0].pdm_clk[1]:0 */ 662 P8_4_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ 663 P8_4_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ 664 P8_4_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ 665 P8_4_CANFD0_TTCAN_RX = 22, /* Digital Active - canfd[0].ttcan_rx:0 */ 666 P8_4_PERI_TR_IO_INPUT25 = 24, /* Digital Active - peri.tr_io_input[25]:0 */ 667 P8_4_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock:1 */ 668 669 /* P8.5 */ 670 P8_5_GPIO = 0, /* GPIO controls 'out' */ 671 P8_5_AMUXA = 4, /* Analog mux bus A */ 672 P8_5_AMUXB = 5, /* Analog mux bus B */ 673 P8_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 674 P8_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 675 P8_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2] */ 676 P8_5_TDM_TDM_TX_SD = 16, /* Digital Active - tdm.tdm_tx_sd:1 */ 677 P8_5_PDM0_PDM_DATA1 = 17, /* Digital Active - pdm[0].pdm_data[1]:0 */ 678 P8_5_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ 679 P8_5_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ 680 P8_5_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ 681 P8_5_CANFD0_TTCAN_TX = 22, /* Digital Active - canfd[0].ttcan_tx:0 */ 682 683 /* P8.6 */ 684 P8_6_GPIO = 0, /* GPIO controls 'out' */ 685 P8_6_AMUXA = 4, /* Analog mux bus A */ 686 P8_6_AMUXB = 5, /* Analog mux bus B */ 687 P8_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 688 P8_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 689 P8_6_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */ 690 P8_6_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */ 691 692 /* P8.7 */ 693 P8_7_GPIO = 0, /* GPIO controls 'out' */ 694 P8_7_AMUXA = 4, /* Analog mux bus A */ 695 P8_7_AMUXB = 5, /* Analog mux bus B */ 696 P8_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 697 P8_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 698 P8_7_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */ 699 P8_7_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */ 700 701 /* P9.0 */ 702 P9_0_GPIO = 0, /* GPIO controls 'out' */ 703 P9_0_AMUXA = 4, /* Analog mux bus A */ 704 P9_0_AMUXB = 5, /* Analog mux bus B */ 705 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 706 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 707 P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4] */ 708 P9_0_TDM_TDM_TX_SCK = 16, /* Digital Active - tdm.tdm_tx_sck:0 */ 709 P9_0_PDM0_PDM_CLK0 = 17, /* Digital Active - pdm[0].pdm_clk[0]:2 */ 710 P9_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:0 */ 711 P9_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:0 */ 712 P9_0_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:0 */ 713 P9_0_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 714 P9_0_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:4 */ 715 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */ 716 P9_0_LVDS2USB32SS_LNK0_L3_ENTRY_GPIO_I = 28, /* Digital Deep Sleep - lvds2usb32ss.lnk0_l3_entry_gpio_i:1 */ 717 718 /* P9.1 */ 719 P9_1_GPIO = 0, /* GPIO controls 'out' */ 720 P9_1_AMUXA = 4, /* Analog mux bus A */ 721 P9_1_AMUXB = 5, /* Analog mux bus B */ 722 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 723 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 724 P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4] */ 725 P9_1_TDM_TDM_RX_SCK = 16, /* Digital Active - tdm.tdm_rx_sck:0 */ 726 P9_1_PDM0_PDM_DATA0 = 17, /* Digital Active - pdm[0].pdm_data[0]:2 */ 727 P9_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:0 */ 728 P9_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:0 */ 729 P9_1_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:0 */ 730 P9_1_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ 731 P9_1_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:4 */ 732 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:2 */ 733 P9_1_LVDS2USB32SS_LNK1_L3_ENTRY_GPIO_I = 28, /* Digital Deep Sleep - lvds2usb32ss.lnk1_l3_entry_gpio_i:1 */ 734 735 /* P9.2 */ 736 P9_2_GPIO = 0, /* GPIO controls 'out' */ 737 P9_2_AMUXA = 4, /* Analog mux bus A */ 738 P9_2_AMUXB = 5, /* Analog mux bus B */ 739 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 740 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 741 P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5] */ 742 P9_2_TDM_TDM_TX_FSYNC = 16, /* Digital Active - tdm.tdm_tx_fsync:0 */ 743 P9_2_PDM0_PDM_CLK1 = 17, /* Digital Active - pdm[0].pdm_clk[1]:2 */ 744 P9_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:0 */ 745 P9_2_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:0 */ 746 P9_2_LVDS2USB32SS_USB32_GPIO_DDFT_O0 = 23, /* Digital Active - lvds2usb32ss.usb32_gpio_ddft_o[0] */ 747 P9_2_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ 748 P9_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0]:4 */ 749 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:2 */ 750 751 /* P9.3 */ 752 P9_3_GPIO = 0, /* GPIO controls 'out' */ 753 P9_3_AMUXA = 4, /* Analog mux bus A */ 754 P9_3_AMUXB = 5, /* Analog mux bus B */ 755 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 756 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 757 P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5] */ 758 P9_3_TDM_TDM_TX_MCK = 16, /* Digital Active - tdm.tdm_tx_mck:0 */ 759 P9_3_PDM0_PDM_DATA1 = 17, /* Digital Active - pdm[0].pdm_data[1]:2 */ 760 P9_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:0 */ 761 P9_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:0 */ 762 P9_3_LVDS2USB32SS_USB32_GPIO_DDFT_O1 = 23, /* Digital Active - lvds2usb32ss.usb32_gpio_ddft_o[1] */ 763 P9_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1]:4 */ 764 P9_3_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock:2 */ 765 766 /* P9.4 */ 767 P9_4_GPIO = 0, /* GPIO controls 'out' */ 768 P9_4_AMUXA = 4, /* Analog mux bus A */ 769 P9_4_AMUXB = 5, /* Analog mux bus B */ 770 P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 771 P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 772 P9_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6] */ 773 P9_4_TDM_TDM_RX_SD = 16, /* Digital Active - tdm.tdm_rx_sd:0 */ 774 P9_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:0 */ 775 P9_4_LVDS2USB32SS_LVDS_GPIO_DDFT_O0 = 23, /* Digital Active - lvds2usb32ss.lvds_gpio_ddft_o[0] */ 776 P9_4_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 777 P9_4_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ 778 779 /* P9.5 */ 780 P9_5_GPIO = 0, /* GPIO controls 'out' */ 781 P9_5_AMUXA = 4, /* Analog mux bus A */ 782 P9_5_AMUXB = 5, /* Analog mux bus B */ 783 P9_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 784 P9_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 785 P9_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6] */ 786 P9_5_TDM_TDM_TX_SD = 16, /* Digital Active - tdm.tdm_tx_sd:0 */ 787 P9_5_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 788 P9_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:0 */ 789 P9_5_CANFD0_TTCAN_RX = 22, /* Digital Active - canfd[0].ttcan_rx:2 */ 790 P9_5_LVDS2USB32SS_LVDS_GPIO_DDFT_O1 = 23, /* Digital Active - lvds2usb32ss.lvds_gpio_ddft_o[1] */ 791 P9_5_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 792 793 /* P9.6 */ 794 P9_6_GPIO = 0, /* GPIO controls 'out' */ 795 P9_6_AMUXA = 4, /* Analog mux bus A */ 796 P9_6_AMUXB = 5, /* Analog mux bus B */ 797 P9_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 798 P9_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 799 P9_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7] */ 800 P9_6_TDM_TDM_RX_FSYNC = 16, /* Digital Active - tdm.tdm_rx_fsync:0 */ 801 P9_6_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ 802 P9_6_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ 803 P9_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */ 804 P9_6_CANFD0_TTCAN_TX = 22, /* Digital Active - canfd[0].ttcan_tx:2 */ 805 806 /* P9.7 */ 807 P9_7_GPIO = 0, /* GPIO controls 'out' */ 808 P9_7_AMUXA = 4, /* Analog mux bus A */ 809 P9_7_AMUXB = 5, /* Analog mux bus B */ 810 P9_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 811 P9_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 812 P9_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7] */ 813 P9_7_TDM_TDM_RX_MCK = 16, /* Digital Active - tdm.tdm_rx_mck:0 */ 814 P9_7_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ 815 P9_7_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ 816 817 /* P10.0 */ 818 P10_0_GPIO = 0, /* GPIO controls 'out' */ 819 P10_0_AMUXA = 4, /* Analog mux bus A */ 820 P10_0_AMUXB = 5, /* Analog mux bus B */ 821 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 822 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 823 P10_0_SCB0_I2C_SCL = 13, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ 824 P10_0_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ 825 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 826 P10_0_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:5 */ 827 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:3 */ 828 829 /* P10.1 */ 830 P10_1_GPIO = 0, /* GPIO controls 'out' */ 831 P10_1_AMUXA = 4, /* Analog mux bus A */ 832 P10_1_AMUXB = 5, /* Analog mux bus B */ 833 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 834 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 835 P10_1_SCB0_I2C_SDA = 13, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ 836 P10_1_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ 837 P10_1_LVDS2USB32SS_LVDS_USEC_PULSE_O = 23, /* Digital Active - lvds2usb32ss.lvds_usec_pulse_o:1 */ 838 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 839 P10_1_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:5 */ 840 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:3 */ 841 842 /* P11.0 */ 843 P11_0_GPIO = 0, /* GPIO controls 'out' */ 844 P11_0_AMUXA = 4, /* Analog mux bus A */ 845 P11_0_AMUXB = 5, /* Analog mux bus B */ 846 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 847 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 848 P11_0_PDM0_PDM_CLK0 = 17, /* Digital Active - pdm[0].pdm_clk[0]:3 */ 849 P11_0_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 850 P11_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 851 P11_0_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ 852 P11_0_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ 853 P11_0_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:6 */ 854 P11_0_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:3 */ 855 P11_0_LVDS2USB32SS_LNK0_L3_ENTRY_GPIO_I = 28, /* Digital Deep Sleep - lvds2usb32ss.lnk0_l3_entry_gpio_i:0 */ 856 P11_0_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 857 P11_0_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 858 859 /* P11.1 */ 860 P11_1_GPIO = 0, /* GPIO controls 'out' */ 861 P11_1_AMUXA = 4, /* Analog mux bus A */ 862 P11_1_AMUXB = 5, /* Analog mux bus B */ 863 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 864 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 865 P11_1_PDM0_PDM_DATA0 = 17, /* Digital Active - pdm[0].pdm_data[0]:3 */ 866 P11_1_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 867 P11_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 868 P11_1_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ 869 P11_1_PERI_TR_IO_INPUT24 = 24, /* Digital Active - peri.tr_io_input[24]:0 */ 870 P11_1_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:6 */ 871 P11_1_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:3 */ 872 P11_1_LVDS2USB32SS_LNK1_L3_ENTRY_GPIO_I = 28, /* Digital Deep Sleep - lvds2usb32ss.lnk1_l3_entry_gpio_i:0 */ 873 P11_1_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 874 P11_1_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 875 876 /* P11.2 */ 877 P11_2_GPIO = 0, /* GPIO controls 'out' */ 878 P11_2_AMUXA = 4, /* Analog mux bus A */ 879 P11_2_AMUXB = 5, /* Analog mux bus B */ 880 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 881 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 882 P11_2_PDM0_PDM_CLK1 = 17, /* Digital Active - pdm[0].pdm_clk[1]:3 */ 883 P11_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ 884 P11_2_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 885 P11_2_LVDS2USB32SS_LVDS_USEC_PULSE_O = 23, /* Digital Active - lvds2usb32ss.lvds_usec_pulse_o:0 */ 886 P11_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0]:5 */ 887 P11_2_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 888 889 /* P11.3 */ 890 P11_3_GPIO = 0, /* GPIO controls 'out' */ 891 P11_3_AMUXA = 4, /* Analog mux bus A */ 892 P11_3_AMUXB = 5, /* Analog mux bus B */ 893 P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 894 P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 895 P11_3_PDM0_PDM_DATA1 = 17, /* Digital Active - pdm[0].pdm_data[1]:3 */ 896 P11_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ 897 P11_3_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 898 P11_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1]:5 */ 899 P11_3_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 900 901 /* P11.4 */ 902 P11_4_GPIO = 0, /* GPIO controls 'out' */ 903 P11_4_AMUXA = 4, /* Analog mux bus A */ 904 P11_4_AMUXB = 5, /* Analog mux bus B */ 905 P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 906 P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 907 P11_4_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ 908 P11_4_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ 909 P11_4_CANFD0_TTCAN_RX = 22, /* Digital Active - canfd[0].ttcan_rx:3 */ 910 P11_4_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 911 912 /* P11.5 */ 913 P11_5_GPIO = 0, /* GPIO controls 'out' */ 914 P11_5_AMUXA = 4, /* Analog mux bus A */ 915 P11_5_AMUXB = 5, /* Analog mux bus B */ 916 P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 917 P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 918 P11_5_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ 919 P11_5_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ 920 P11_5_CANFD0_TTCAN_TX = 22, /* Digital Active - canfd[0].ttcan_tx:3 */ 921 P11_5_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ 922 P11_5_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock:3 */ 923 924 /* USBDM */ 925 USBDM_AMUXA = 4, /* Analog mux bus A */ 926 USBDM_AMUXB = 5, /* Analog mux bus B */ 927 USBDM_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 928 USBDM_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 929 930 /* USBDP */ 931 USBDP_AMUXA = 4, /* Analog mux bus A */ 932 USBDP_AMUXB = 5, /* Analog mux bus B */ 933 USBDP_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 934 USBDP_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 935 936 /* P13.0 */ 937 P13_0_GPIO = 0, /* GPIO controls 'out' */ 938 P13_0_AMUXA = 4, /* Analog mux bus A */ 939 P13_0_AMUXB = 5, /* Analog mux bus B */ 940 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 941 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 942 P13_0_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ 943 P13_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi */ 944 P13_0_CANFD0_TTCAN_TX = 22, /* Digital Active - canfd[0].ttcan_tx:1 */ 945 946 /* P13.1 */ 947 P13_1_GPIO = 0, /* GPIO controls 'out' */ 948 P13_1_AMUXA = 4, /* Analog mux bus A */ 949 P13_1_AMUXB = 5, /* Analog mux bus B */ 950 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 951 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 952 P13_1_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ 953 P13_1_SCB5_SPI_MISO = 20 /* Digital Active - scb[5].spi_miso */ 954 } en_hsiom_sel_t; 955 956 #endif /* _GPIO_FX3G2_169_BGA_H_ */ 957 958 959 /* [] END OF FILE */ 960
