1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file timerclk.cypersonality 6* \version 3.0 7* 8* \brief 9* CLK_TIMER personality description file. 10* This supports CAT1A, CAT1B and CAT1C devices. 11* 12******************************************************************************** 13* \copyright 14* Copyright (c) 2022, Cypress Semiconductor Corporation (an Infineon company) or 15* an affiliate of Cypress Semiconductor Corporation. 16* SPDX-License-Identifier: Apache-2.0 17* 18* Licensed under the Apache License, Version 2.0 (the "License"); 19* you may not use this file except in compliance with the License. 20* You may obtain a copy of the License at 21* 22* http://www.apache.org/licenses/LICENSE-2.0 23* 24* Unless required by applicable law or agreed to in writing, software 25* distributed under the License is distributed on an "AS IS" BASIS, 26* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 27* See the License for the specific language governing permissions and 28* limitations under the License. 29*****************************************************************************--> 30 31<Personality id="timerclk" name="CLK_TIMER" version="3.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 32 <Dependencies> 33 <IpBlock name="mxs40srss,mxs40ssrss,mxs40srss_ver3,mxs22srss,mxs40srss_ver2" /> 34 <Resource name="srss\.clock\.timerclk" /> 35 </Dependencies> 36 <ExposedMembers> 37 <ExposedMember key="frequency" paramId="frequency" /> 38 <ExposedMember key="accuracy" paramId="accuracy" /> 39 <ExposedMember key="sourceClockDisplayName" paramId="sourceClockDisplayName" /> 40 </ExposedMembers> 41 <Parameters> 42 <!-- PDL documentation --> 43 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__sysclk__clk__timer.html" linkText="Open Timer Clock Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 44 45 <ParamChoice id="sourceClock" name="Source Clock" group="General" default="`${"mxs22srss" eq getIpBlockName() ? "iho" : "imo"}`" visible="`${"mxs40srss" eq getIpBlockName() ? "true" : "false"}`" editable="`${"mxs40srss" eq getIpBlockName() ? "true" : "false"}`" desc="The source clock for the CLK_TIMER"> 46 <Entry name="IMO" value="imo" visible="true"/> 47 <Entry name="CLK_HF0" value="hfclk" visible="true"/> 48 <Entry name="IHO" value="iho" visible="true"/> 49 </ParamChoice> 50 <ParamString id="sourceClockDisplayName" name="Source Clock Display Name" group="Internal" default="`${getParamValueDisplay("sourceClock")}`" visible="false" editable="false" desc="" /> 51 <ParamString id="sourceClockRsc" name="Source Clock Resource" group="Internal" default="`${"srss[0].clock[0]." . sourceClock . "[0]"}`" visible="false" editable="false" desc="" /> 52 <ParamBool id="error" name="Clock Error" group="Internal" default="false" visible="false" editable="false" desc="" /> 53 <ParamRange id="sourceFreq" name="sourceFrequency" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, "frequency") : 0}`" min="0" max="400000000" resolution="1" visible="false" editable="false" desc="" /> 54 <ParamString id="accuracy" name="Accuracy" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, "accuracy") : 0}`" visible="false" editable="false" desc="" /> 55 <ParamString id="sourceFrequencyInfo" name="Source Frequency" group="General" default="`${formatFrequency(sourceFreq,accuracy)}`" visible="`${"mxs40srss" eq getIpBlockName() ? "true" : "false"}`" editable="false" desc="Source clock frequency" /> 56 <ParamChoice id="hf0Div" name="CLK_HF0 Divider" group="General" default="1" visible="`${"mxs40srss" eq getIpBlockName() ? "true" : "false"}`" editable="`${sourceClock eq hfclk}`" desc="CLK_HF0 can be additionaly divided before it is connected to the timer divider. If CLK_HF0 frequency is less than 100 MHz and has approximately 50% duty cycle, then no division is required. Otherwise, select a divide ratio of 2, 4, or 8."> 57 <Entry name="1" value="1" visible="true"/> 58 <Entry name="2" value="2" visible="true"/> 59 <Entry name="4" value="4" visible="true"/> 60 <Entry name="8" value="8" visible="true"/> 61 </ParamChoice> 62 <!-- Set an error if the source clock is not enabled --> 63 64 <ParamRange id="timerDivider" name="Timer Divider" group="General" default="1" min="1" max="256" resolution="1" visible="`${"mxs40srss" eq getIpBlockName() ? "true" : "false"}`" editable="`${"mxs40srss" eq getIpBlockName() ? "true" : "false"}`" desc="" /> 65 <ParamRange id="frequency" name="Frequency (MHz)" group="Internal" default="`${"mxs22srss" eq getIpBlockName() ? 1000000 : (sourceFreq / (sourceClock eq imo ? timerDivider : hf0Div))}`" min="0" max="400000000" resolution="1" visible="false" editable="false" desc="" /> 66 <!-- If the frequency is less than one MHz, display its value in kHz --> 67 <ParamString id="frequencyInfo" name="Frequency" group="General" default="`${"mxs40srss" eq getIpBlockName() ? formatFrequency(frequency,accuracy) : formatFrequency(1000000)}`" visible="true" editable="false" desc="The resulting CLK_TIMER output clock frequency" /> 68 </Parameters> 69 <DRCs> 70 <DRC type="ERROR" text="Source clock for CLK_TIMER is not enabled" condition="`${error}`" > 71 <FixIt action="ENABLE_BLOCK" target="`${sourceClockRsc}`" value="" valid="true" /> 72 </DRC> 73 </DRCs> 74 <ConfigFirmware> 75 <ConfigInclude value="cy_sysclk.h" include="`${"mxs40srss" eq getIpBlockName() ? "true" : "false"}`" /> 76 <ConfigDefine name="CY_CFG_SYSCLK_CLKTIMER_ENABLED" value="1" public="false" include="`${"mxs40srss" eq getIpBlockName() ? "true" : "false"}`" /> 77 <ConfigDefine name="CY_CFG_SYSCLK_CLKTIMER_SOURCE" value="CY_SYSCLK_CLKTIMER_IN_`${sourceClock eq imo ? "IMO" : "HF0" . (hf0Div == 1 ? "_NODIV" : "_DIV" . hf0Div)}`" public="false" include="`${"mxs40srss" eq getIpBlockName() ? "true" : "false"}`" /> 78 <ConfigDefine name="CY_CFG_SYSCLK_CLKTIMER_DIVIDER" value="`${timerDivider-1}`U" public="false" include="`${"mxs40srss" eq getIpBlockName() ? "true" : "false"}`" /> 79 <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_ClkTimerInit()" body=" Cy_SysClk_ClkTimerDisable();
 Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_`${sourceClock eq imo ? "IMO" : "HF0" . (hf0Div == 1 ? "_NODIV" : "_DIV" . hf0Div)}`);
 Cy_SysClk_ClkTimerSetDivider(`${timerDivider-1}`U);
 Cy_SysClk_ClkTimerEnable();" public="false" include="`${"mxs40srss" eq getIpBlockName() ? "true" : "false"}`" guard="(!defined(CY_DEVICE_SECURE))" /> 80 </ConfigFirmware> 81</Personality> 82
