1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file pll.cypersonality 6* \version 3.0 7* 8* \brief 9* PLL personality description file. It supports CAT1A, CAT1B, CAT1C and 10* CAT1D devices. 11* 12******************************************************************************** 13* \copyright 14* Copyright 2018-2022 Cypress Semiconductor Corporation 15* SPDX-License-Identifier: Apache-2.0 16* 17* Licensed under the Apache License, Version 2.0 (the "License"); 18* you may not use this file except in compliance with the License. 19* You may obtain a copy of the License at 20* 21* http://www.apache.org/licenses/LICENSE-2.0 22* 23* Unless required by applicable law or agreed to in writing, software 24* distributed under the License is distributed on an "AS IS" BASIS, 25* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26* See the License for the specific language governing permissions and 27* limitations under the License. 28*****************************************************************************--> 29 30<Personality id="pll" name="PLL" version="3.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 31 <Dependencies> 32 <IpBlock name="mxs40srss,mxs40srss_ver3,mxs40srss_ver2" /> 33 <Resource name="srss\.clock\.pll" /> 34 </Dependencies> 35 <ExposedMembers> 36 <ExposedMember key="frequency" paramId="frequencyDisplay" /> 37 <ExposedMember key="accuracy" paramId="accuracy" /> 38 <ExposedMember key="error" paramId="error" /> 39 </ExposedMembers> 40 <Parameters> 41 <!-- PDL documentation --> 42 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__sysclk__pll.html" linkText="Open PLL Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 43 44 <!-- Parameters for SRSS conditions --> 45 <ParamBool 46 id="is40srss_ver2or3Available" name="is40srss_ver2or3Available" group="" 47 default="`${(("mxs40srss_ver2" eq getIpBlockName()) || ("mxs40srss_ver3" eq getIpBlockName()))}`" 48 visible="false" editable="false" desc="" /> 49 50 <!-- PLL source clock and max device frequency --> 51 <ParamRange id="clockInst" name="PLL Instance" group="Internal" default="`${getInstNumber("pll")}`" min="0" max="`${NUM_PLL-1}`" resolution="1" visible="false" editable="false" desc="" /> 52 <ParamRange id="pll400Inst" name="PLL400M Instance" group="Internal" default="`${lookupExpression("NUM_PLL400M", 0)}`" min="0" max="10" resolution="1" visible="false" editable="false" desc="" /> 53 <ParamString id="sourceClockRsc" name="Source Clock" group="Internal" default="srss[0].clock[0].pathmux[`${clockInst+1+pll400Inst}`]" visible="false" editable="false" desc="" /> 54 <ParamBool id="srcNotUsed" name="Clock Source Enabled" group="Internal" default="`${!isBlockUsed(sourceClockRsc)}`" visible="false" editable="false" desc="" /> 55 <ParamBool id="srcError" name="Source Error" group="Internal" default="`${srcNotUsed || getExposedMember(sourceClockRsc, "error")}`" visible="false" editable="false" desc="" /> 56 <ParamRange id="sourceFrequencyActual" name="Source Frequency" group="Internal" default="`${srcError ? 0 : getExposedMember(sourceClockRsc, "frequency")}`" min="0" max="100000000" resolution="1" visible="false" editable="false" desc="" /> 57 <ParamString id="accuracy" name="accuracy" group="Internal" default="`${!srcError ? getExposedMember(sourceClockRsc, "accuracy") : 0}`" visible="false" editable="false" desc="" /> 58 59 <ParamString id="sourceFrequencyInfo" name="Source Frequency" group="General" default="`${formatFrequency(sourceFrequencyActual,accuracy)}`" visible="true" editable="false" desc="Source clock frequency" /> 60 <!-- For ULP mode, Fpll_max = 50 MHz --> 61 <ParamBool id="usingUlp" name="usingUlp" group="Internal" default="`${isBlockUsed("srss[0].power[0]") && getExposedMember("srss[0].power[0]", "usingUlp")}`" visible="false" editable="false" desc="" /> 62 <ParamString id="maxFrequency" name="maxFrequency" group="Internal" default="`${getDeviceAttr("CPU_MAX_MHZ")}`" visible="false" editable="false" desc="The maximum device frequency" /> 63 64 <ParamBool id="lowFrequencyMode" name="Low Frequency Mode" group="General" default="false" visible="true" editable="true" desc="VCO frequency range selection" /> 65 <ParamChoice id="configuration" name="Configuration" group="General" default="auto" visible="true" editable="true" desc="Choose the automatic or manual PLL tuning"> 66 <Entry name="Automatic" value="auto" visible="true"/> 67 <Entry name="Manual" value="manual" visible="true"/> 68 </ParamChoice> 69 <ParamBool id="manConfig" name="Manual PLL Configuration" group="Internal" default="`${configuration eq manual}`" visible="false" editable="false" desc="" /> 70 <ParamRange id="desiredFrequency" name="Desired Frequency (MHz)" group="General" default="`${maxFrequency > 100 ? 100 : maxFrequency}`" min="`${lowFrequencyMode ? 10.625 : 12.5}`" max="`${maxFrequency}`" resolution="0.001" visible="`${!manConfig}`" editable="true" desc="" /> 71 <ParamChoice id="optimization" name="Optimization" group="General" default="MinPower" visible="`${!manConfig}`" editable="true" desc="The feedback tuning options"> 72 <Entry name="Min Power" value="MinPower" visible="true" /> 73 <Entry name="Min Jitter" value="MinJitter" visible="true" /> 74 </ParamChoice> 75 76 <!-- Set an error if the source clock is not enabled, contains an error or the source frequency is outside the valid range --> 77 <ParamBool id="sourceFrequencyOutRange" name="sourceFrequencyOutRange" group="Internal" default="`${(sourceFrequencyActual < 4000000) || (sourceFrequencyActual > 64000000)}`" visible="false" editable="false" desc="" /> 78 <ParamBool id="error" name="Clock Error" group="Internal" default="`${srcError || sourceFrequencyOutRange}`" visible="false" editable="false" desc="" /> 79 80 <!-- Source Frequency --> 81 <ParamRange id="sourceFrequency" name="sourceFrequency" group="Internal" default="`${!sourceFrequencyOutRange ? sourceFrequencyActual : 4000000}`" min="4000000" max="64000000" resolution="1" visible="false" editable="false" desc="" /> 82 83 <ParamString id="callSolver" name="callSolver" group="Internal" default="`${runTcl("pll_solver-2.0.tcl", sourceFrequency / 1000000.0, desiredFrequency, lowFrequencyMode, optimization eq MinPower)}`" visible="false" editable="false" desc="PLL clock solver" /> 84 <ParamRange id="feedback" name="Feedback (22-`${lowFrequencyMode ? "56" : "112"}`)" group="General" default="`${getTclVar("feedbackDiv", callSolver)}`" min="22" max="`${lowFrequencyMode ? "56" : "112"}`" resolution="1" visible="true" editable="`${manConfig}`" desc="The feedback clock divider" /> 85 <ParamRange id="reference" name="Reference (1-18)" group="General" default="`${getTclVar("referenceDiv", callSolver)}`" min="1" max="18" resolution="1" visible="true" editable="`${manConfig}`" desc="The reference clock divider" /> 86 <ParamRange id="output" name="Output (2-16)" group="General" default="`${getTclVar("outputDiv", callSolver)}`" min="2" max="16" resolution="1" visible="true" editable="`${manConfig}`" desc="The output clock divider" /> 87 <ParamRange id="frequency" name="Frequency" group="Internal" default="`${sourceFrequency * feedback / reference / output}`" min="10625000" max="200000000" resolution="1" visible="false" editable="false" desc="" /> 88 <ParamRange id="frequencyDisplay" name="Display Frequency" group="Internal" default="`${(sourceFrequencyActual eq 0) ? sourceFrequencyActual : frequency}`" min="0" max="200000000" resolution="1" visible="false" editable="false" desc="" /> 89 <ParamString id="frequencyInfo" name="Actual Frequency" group="General" default="`${formatFrequency(!error ? frequency : 0,accuracy)}`" visible="true" editable="false" desc="The calculated resulting PLL output frequency" /> 90 91 <!-- Manual DRC verify params --> 92 <ParamRange id="pfdFreq" name="PFD Frequency" group="internal" default="`${sourceFrequency / reference / 1000000.0}`" min="0" max="10000" resolution="0.001" visible="false" editable="false" desc="" /> 93 <ParamRange id="vcoFreq" name="VCO Frequency" group="internal" default="`${pfdFreq * feedback}`" min="0" max="10000" resolution="0.001" visible="false" editable="false" desc="" /> 94 <ParamRange id="vcoMin" name="VCO Min" group="internal" default="`${lowFrequencyMode ? 170 : 200}`" min="170" max="200" resolution="1" visible="false" editable="false" desc="" /> 95 <ParamRange id="vcoMax" name="VCO Max" group="internal" default="`${lowFrequencyMode ? 200 : 400}`" min="200" max="400" resolution="1" visible="false" editable="false" desc="" /> 96 97 </Parameters> 98 <DRCs> 99 <DRC type="ERROR" text="Source clock for PLL is not enabled" condition="`${srcNotUsed && !hasBlock("srss[0].clock[0].pll[1]")}`" > 100 <FixIt action="ENABLE_BLOCK" target="`${sourceClockRsc}`" value="" valid="true" /> 101 </DRC> 102 <DRC type="ERROR" text="Source clock for PLL`${clockInst}` is not enabled" condition="`${srcNotUsed && hasBlock("srss[0].clock[0].pll[1]")}`" > 103 <FixIt action="ENABLE_BLOCK" target="`${sourceClockRsc}`" value="" valid="true" /> 104 </DRC> 105 <DRC type="ERROR" text="The desired PLL frequency `${desiredFrequency}` MHz is higher than the maximum operating frequency `${maxFrequency}` MHz of the device" condition="`${!usingUlp && desiredFrequency > maxFrequency}`" paramId="desiredFrequency" /> 106 <DRC type="ERROR" text="The desired PLL frequency `${desiredFrequency}` MHz exceeds the maximum of 50 MHz when the ULP mode is used" condition="`${usingUlp && desiredFrequency > 50}`" paramId="desiredFrequency" /> 107 <DRC type="ERROR" text="Source clock for PLL is outside the valid range of 4 MHz - 64 MHz" condition="`${!srcError && sourceFrequencyOutRange}`" paramId="sourceFrequencyInfo"/> 108 <!-- Manual mode DRCs --> 109 <DRC type="ERROR" text="VCO frequency out of range. VCO frequency (sourceFrequency * Feedback / Reference) of `${vcoFreq}` MHz is outside valid range of `${vcoMin}` MHz - `${vcoMax}` MHz" condition="`${manConfig && (vcoFreq < vcoMin || vcoFreq > vcoMax)}`" /> 110 <DRC type="ERROR" text="PFD reference frequency out of range. PFD reference frequency (sourceFrequency / Reference) of `${pfdFreq}` MHz is outside valid range of 4 MHz - 8 MHz" condition="`${manConfig && (pfdFreq < 4 || pfdFreq > 8)}`" /> 111 112 </DRCs> 113 <ConfigFirmware> 114 <ConfigInclude value="cy_sysclk.h" include="true" /> 115 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_ENABLED" value="1" public="false" include="`${("mxs40srss" eq getIpBlockName())}`" /> 116 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_FEEDBACK_DIV" value="`${feedback}`" public="false" include="`${("mxs40srss" eq getIpBlockName())}`" /> 117 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_REFERENCE_DIV" value="`${reference}`" public="false" include="`${("mxs40srss" eq getIpBlockName())}`" /> 118 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_OUTPUT_DIV" value="`${output}`" public="false" include="`${("mxs40srss" eq getIpBlockName())}`" /> 119 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_LF_MODE" value="`${lowFrequencyMode}`" public="false" include="`${("mxs40srss" eq getIpBlockName())}`" /> 120 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_OUTPUT_MODE" value="CY_SYSCLK_FLLPLL_OUTPUT_AUTO" public="false" include="`${("mxs40srss" eq getIpBlockName())}`" /> 121 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_OUTPUT_FREQ" value="`${frequency}`" public="false" include="`${("mxs40srss" eq getIpBlockName())}`" /> 122 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${(("mxs40srss" eq getIpBlockName()) ? (clockInst) : (clockInst+pll400Inst))}`_ENABLED" value="1" public="false" include="`${(is40srss_ver2or3Available) || ("mxs22srss" eq getIpBlockName())}`" /> 123 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${(("mxs40srss" eq getIpBlockName()) ? (clockInst) : (clockInst+pll400Inst))}`_FEEDBACK_DIV" value="`${feedback}`" public="false" include="`${(is40srss_ver2or3Available) || ("mxs22srss" eq getIpBlockName())}`" /> 124 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${(("mxs40srss" eq getIpBlockName()) ? (clockInst) : (clockInst+pll400Inst))}`_REFERENCE_DIV" value="`${reference}`" public="false" include="`${(is40srss_ver2or3Available) || ("mxs22srss" eq getIpBlockName())}`" /> 125 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${(("mxs40srss" eq getIpBlockName()) ? (clockInst) : (clockInst+pll400Inst))}`_OUTPUT_DIV" value="`${output}`" public="false" include="`${(is40srss_ver2or3Available) || ("mxs22srss" eq getIpBlockName())}`" /> 126 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${(("mxs40srss" eq getIpBlockName()) ? (clockInst) : (clockInst+pll400Inst))}`_LF_MODE" value="`${lowFrequencyMode}`" public="false" include="`${(is40srss_ver2or3Available) || ("mxs22srss" eq getIpBlockName())}`" /> 127 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${(("mxs40srss" eq getIpBlockName()) ? (clockInst) : (clockInst+pll400Inst))}`_OUTPUT_MODE" value="CY_SYSCLK_FLLPLL_OUTPUT_AUTO" public="false" include="`${(is40srss_ver2or3Available) || ("mxs22srss" eq getIpBlockName())}`" /> 128 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${(("mxs40srss" eq getIpBlockName()) ? (clockInst) : (clockInst+pll400Inst))}`_OUTPUT_FREQ" value="`${frequency}`" public="false" include="`${(is40srss_ver2or3Available) || ("mxs22srss" eq getIpBlockName())}`" /> 129 <ConfigStruct name="`${INST_NAME . "_pllConfig"}`" type="cy_stc_pll_manual_config_t" const="true" public="false" include="true" guard="(!defined(CY_DEVICE_SECURE))"> 130 <Member name="feedbackDiv" value="`${feedback}`" /> 131 <Member name="referenceDiv" value="`${reference}`" /> 132 <Member name="outputDiv" value="`${output}`" /> 133 <Member name="lfMode" value="`${lowFrequencyMode}`" /> 134 <Member name="outputMode" value="CY_SYSCLK_FLLPLL_OUTPUT_AUTO" /> 135 </ConfigStruct> 136 <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_Pll`${clockInst}`Init()" body=" if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(`${clockInst + 1}`U, &`${INST_NAME}`_pllConfig))
 {
 cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
 }
 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(`${clockInst + 1}`U, 10000u))
 {
 cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
 }" public="false" include="`${("mxs40srss" eq getIpBlockName())}`" guard="(!defined(CY_DEVICE_SECURE))" /> 137 <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_Pll`${clockInst+pll400Inst}`Init()" body=" Cy_SysClk_PllDisable(SRSS_PLL_200M_`${clockInst}`_PATH_NUM);

 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(SRSS_PLL_200M_`${clockInst}`_PATH_NUM, &`${INST_NAME}`_pllConfig))
 {
 cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
 }
 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_PLL_200M_`${clockInst}`_PATH_NUM, 10000u))
 {
 cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
 }" public="false" include="`${(is40srss_ver2or3Available) || ("mxs22srss" eq getIpBlockName())}`" /> 138 </ConfigFirmware> 139</Personality> 140
