1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file uart.cypersonality 6* \version 3.0 7* 8* \brief 9* UART personality description file. It Supports CAT1A, CAT1B and CAT1C family of devices. 10* 11******************************************************************************** 12* \copyright 13* Copyright 2022 Cypress Semiconductor Corporation 14* SPDX-License-Identifier: Apache-2.0 15* 16* Licensed under the Apache License, Version 2.0 (the "License"); 17* you may not use this file except in compliance with the License. 18* You may obtain a copy of the License at 19* 20* http://www.apache.org/licenses/LICENSE-2.0 21* 22* Unless required by applicable law or agreed to in writing, software 23* distributed under the License is distributed on an "AS IS" BASIS, 24* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25* See the License for the specific language governing permissions and 26* limitations under the License. 27*****************************************************************************--> 28 29<Personality id="uart" name="UART" version="3.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v8"> 30 <Dependencies> 31 <IpBlock name="mxscb,mxscb_ver2_s40e,mxs22scb"> 32 <Version major="1"/> 33 <Version major="2" /> 34 <Version major="4" /> 35 <Param name="UART" value="1" /> 36 </IpBlock> 37 <Resource name="scb" /> 38 <OperatingMode value="MCU"/> 39 </Dependencies> 40 <ExposedMembers /> 41 42 <Parameters> 43 <!-- PDL documentation --> 44 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__scb__uart.html" linkText="Open UART (SCB) Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 45 46 <!-- Internal --> 47 <ParamString id="version" name="version number" group="Internal" default="`${getVersion()}`" visible="false" editable="false" desc="" /> 48 <ParamString id="ipName" name="IP name" group="Internal" default="`${getIpBlockName()}`" visible="false" editable="false" desc="" /> 49 50 <!-- General --> 51 <ParamChoice id="ComMode" name="Com Mode" group="General" default="CY_SCB_UART_STANDARD" visible="true" editable="true" desc="This parameter defines the sub-mode of UART as: Standard, SmartCard or IrDA."> 52 <Entry name="Standard" value="CY_SCB_UART_STANDARD" visible="true" /> 53 <Entry name="SmartCard" value="CY_SCB_UART_SMARTCARD" visible="true" /> 54 <Entry name="IrDA" value="CY_SCB_UART_IRDA" visible="true" /> 55 </ParamChoice> 56 <ParamBool id="Standard" name="Standard" group="Internal" default="`${ComMode eq CY_SCB_UART_STANDARD}`" visible="false" editable="false" desc="This parameter defines SmartCard." /> 57 <ParamBool id="SmartCard" name="SmartCard" group="Internal" default="`${ComMode eq CY_SCB_UART_SMARTCARD}`" visible="false" editable="false" desc="This parameter defines SmartCard." /> 58 <ParamBool id="IrDA" name="IrDA" group="Internal" default="`${ComMode eq CY_SCB_UART_IRDA}`" visible="false" editable="false" desc="This parameter defines SmartCard." /> 59 60 <ParamBool id="IrdaLowPower" name="Low Power Receiving" group="General" default="false" visible="`${IrDA}`" editable="true" desc="This parameter enables the low-power receiver option. Only applicable when Com Mode is IrDA."/> 61 62 <ParamRange id="BaudRate" name="Baud Rate (bps)" group="General" default="115200" min="1" max="8000000" resolution="1" visible="true" editable="true" desc="Baud rate that UART operates. Maximum baud rate is 8 Mbps in LP mode." /> 63 64 <!--Oversample--> 65 <ParamChoice id="Oversample" name="Oversample" group="General" default="8" visible="`${!IrDA}`" editable="true" desc="This parameter defines how many SCB clocks oversample the selected baud rate."> 66 <Entry name="8" value="8" visible="true" /> 67 <Entry name="9" value="9" visible="true" /> 68 <Entry name="10" value="10" visible="true" /> 69 <Entry name="11" value="11" visible="true" /> 70 <Entry name="12" value="12" visible="true" /> 71 <Entry name="13" value="13" visible="true" /> 72 <Entry name="14" value="14" visible="true" /> 73 <Entry name="15" value="15" visible="true" /> 74 <Entry name="16" value="16" visible="true" /> 75 </ParamChoice> 76 77 <ParamRange id="IrDAOversample" name="Oversample" group="General" default="16" min="16" max="16" resolution="1" visible="`${IrDA && !IrdaLowPower}`" editable="false" desc="This parameter defines how many SCB clocks oversample the selected baud rate."/> 78 79 <ParamRange id="IrDALpOversample" name="Oversample" group="General" default="`${(BaudRate eq 1200) ? 1536 : (BaudRate eq 2400) ? 768 : (BaudRate eq 9600) ? 192 : (BaudRate eq 19200) ? 96 : (BaudRate eq 38400) ? 48 : (BaudRate eq 57600) ? 32 : 16}`" min="16" max="1536" resolution="1" visible="`${IrDA && IrdaLowPower}`" editable="false" desc="This parameter defines how many SCB clocks oversample the selected baud rate."/> 80 81 <ParamString id="IrDAOversampleDefine" name="IrDAOversampleDefine" group="General" default="`${(BaudRate eq 1200) ? "CY_SCB_UART_IRDA_LP_OVS1536" : (BaudRate eq 2400) ? "CY_SCB_UART_IRDA_LP_OVS768" : (BaudRate eq 9600) ? "CY_SCB_UART_IRDA_LP_OVS192" : (BaudRate eq 19200) ? "CY_SCB_UART_IRDA_LP_OVS96" : (BaudRate eq 38400) ? "CY_SCB_UART_IRDA_LP_OVS48" : (BaudRate eq 57600) ? "CY_SCB_UART_IRDA_LP_OVS32" : "CY_SCB_UART_IRDA_LP_OVS16"}`" visible="false" editable="false" desc="This parameter provides define for oversample in IrDA low receiver power mode."/> 82 83 <ParamRange id="OversampleFinal" name="OversampleFinal" group="Internal" default="`${(Standard || SmartCard) ? Oversample : (IrDA && !IrdaLowPower) ? IrDAOversample : IrDALpOversample}`" min="1" max="1536" resolution="1" visible="false" editable="false" desc="This parameter defines how many SCB clocks oversample the selected baud rate."/> 84 85 <ParamChoice id="BitsOrder" name="Bit Order" group="General" default="CY_SCB_UART_LSB_FIRST" visible="true" editable="true" desc="This parameter defines the direction in which the serial data is transmitted. When set to the MSB first, the most-significant bit is transmitted first. When set to the LSB first, the least-significant bit is transmitted first."> 86 <Entry name="MSB First" value="CY_SCB_UART_MSB_FIRST" visible="true" /> 87 <Entry name="LSB First" value="CY_SCB_UART_LSB_FIRST" visible="true" /> 88 </ParamChoice> 89 <ParamChoice id="DataWidth" name="Data Width" group="General" default="8" visible="true" editable="true" desc="This option defines the width of a single data element in bits. The range: 5-9."> 90 <Entry name="5 bits" value="5" visible="true" /> 91 <Entry name="6 bits" value="6" visible="true" /> 92 <Entry name="7 bits" value="7" visible="true" /> 93 <Entry name="8 bits" value="8" visible="true" /> 94 <Entry name="9 bits" value="9" visible="true" /> 95 </ParamChoice> 96 <ParamChoice id="ParityType" name="Parity" group="General" default="CY_SCB_UART_PARITY_NONE" visible="`${Standard && (DataWidth ne 9)}`" editable="true" desc="This parameter defines the functionality of the parity bit location in the transfer as None, Odd or Even."> 97 <Entry name="Even" value="CY_SCB_UART_PARITY_EVEN" visible="true" /> 98 <Entry name="Odd" value="CY_SCB_UART_PARITY_ODD" visible="true" /> 99 <Entry name="None" value="CY_SCB_UART_PARITY_NONE" visible="true" /> 100 </ParamChoice> 101 <ParamBool id="MultiProcParityCheck" name="Parity" group="General" default="`${Standard && (DataWidth eq 9)}`" visible="false" editable="false" desc="" /> 102 <ParamString id="MultiProcParity" name="Parity" group="General" default="None" visible="`${MultiProcParityCheck}`" editable="false" desc="Multi Processor Mode supports Parity = None" /> 103 <ParamString id="SmartCardParity" name="Parity" group="General" default="Even" visible="`${SmartCard}`" editable="false" desc="SmartCard supports Parity = Even" /> 104 <ParamString id="IrdaCardParity" name="Parity" group="General" default="None" visible="`${IrDA}`" editable="false" desc="IrDA supports Parity = None" /> 105 <ParamChoice id="StopBits" name="Stop Bits" group="General" default="CY_SCB_UART_STOP_BITS_1" visible="`${!SmartCard}`" editable="true" desc="This parameter defines the number of stop bits."> 106 <Entry name="1 bit" value="CY_SCB_UART_STOP_BITS_1" visible="true" /> 107 <Entry name="1.5 bits" value="CY_SCB_UART_STOP_BITS_1_5" visible="true" /> 108 <Entry name="2 bits" value="CY_SCB_UART_STOP_BITS_2" visible="true" /> 109 <Entry name="2.5 bits" value="CY_SCB_UART_STOP_BITS_2_5" visible="true" /> 110 <Entry name="3 bits" value="CY_SCB_UART_STOP_BITS_3" visible="true" /> 111 <Entry name="3.5 bits" value="CY_SCB_UART_STOP_BITS_3_5" visible="true" /> 112 <Entry name="4 bits" value="CY_SCB_UART_STOP_BITS_4" visible="true" /> 113 </ParamChoice> 114 <ParamString id="SmartCardStopBits" name="Stop Bits" group="General" default="2 bits" visible="`${SmartCard}`" editable="false" desc="SmartCard supports Stop Bits = 2 bits." /> 115 116 <!-- EnableInputFilter --> 117 <ParamBool id="EnableInputFilter" name="Enable Digital Filter" group="General" default="`${false}`" visible="`${ComMode ne CY_SCB_UART_IRDA}`" editable="true" desc="This parameter applies a digital 3-tap median filter to the UART input lines." /> 118 <ParamBool id="IrDAInputFilter" name="Enable Digital Filter" group="General" default="`${true}`" visible="`${IrDA}`" editable="false" desc="IrDA mode always enables digital filter." /> 119 120 <!-- Support RS-485 --> 121 <ParamBool id="EnableTxEn" name="TX-Enable" group="Support RS-485" default="false" visible="`${!SmartCard}`" editable="true" desc="This parameter enables TX_EN output." /> 122 123 <!-- Single Wire Half-Duplex Mode --> 124 <ParamBool id="EnableHalfDuplex" name="Half-Duplex Mode Enable" group="Single Wire Half-Duplex Mode" default="false" visible="`${Standard &&((version > 3) && (ipName eq "mxscb"))}`" editable="true" desc="This parameter enables Single Wire Half-Duplex Mode." /> 125 126 <!-- Hardware buffer size (defines FIFO size) --> 127 <ParamRange id="hwBufferSize" name="Hardware Buffer Size" group="Internal" default="`${lookupExpression("EZ_DATA_NR")}`" min="0" max="512" resolution="1" visible="false" editable="false" desc="Hardware buffer size." /> 128 <ParamRange id="FifoLevelByte" name="FIFO Level (Byte)" group="Internal" default="`${(hwBufferSize / 2) - 1}`" min="1" max="512" resolution="1" visible="false" editable="false" desc="FIFO Level for byte entry." /> 129 <ParamRange id="FifoLevelHalfword" name="FIFO Level (Halfword)" group="Internal" default="`${(hwBufferSize / 4) - 1}`" min="1" max="512" resolution="1" visible="false" editable="false" desc="FIFO Level for byte entry." /> 130 <ParamRange id="FifoLevelMax" name="FIFO Level Max" group="Internal" default="`${(DataWidth <= 8) ? FifoLevelByte : FifoLevelHalfword}`" min="1" max="512" resolution="1" visible="false" editable="false" desc="FIFO Level for byte entry." /> 131 132 <!--Flow Control--> 133 <ParamBool id="FlowControl" name="Enable Flow Control" group="Flow Control" default="false" visible="`${!SmartCard}`" editable="true" desc="This parameter enables the cts input." /> 134 <ParamChoice id="CtsPolarity" name="CTS Polarity" group="Flow Control" default="CY_SCB_UART_ACTIVE_LOW" visible="`${!SmartCard}`" editable="true" desc="This parameter defines the active polarity of the CTS output signal as Active Low or Active High."> 135 <Entry name="Active Low" value="CY_SCB_UART_ACTIVE_LOW" visible="true" /> 136 <Entry name="Active High" value="CY_SCB_UART_ACTIVE_HIGH" visible="true" /> 137 </ParamChoice> 138 <ParamChoice id="RtsPolarity" name="RTS Polarity" group="Flow Control" default="CY_SCB_UART_ACTIVE_LOW" visible="`${!SmartCard}`" editable="true" desc="This parameter defines the active polarity of the RTS output signal as Active Low or Active High."> 139 <Entry name="Active Low" value="CY_SCB_UART_ACTIVE_LOW" visible="true" /> 140 <Entry name="Active High" value="CY_SCB_UART_ACTIVE_HIGH" visible="true" /> 141 </ParamChoice> 142 <ParamRange id="RtsTriggerLevel" name="RTS Activation Level" group="Flow Control" default="63" min="0" max="`${FifoLevelMax}`" resolution="1" visible="`${!SmartCard}`" editable="true" desc="This parameter determines the behavior of the RTS signal as follows: while the RX FIFO has fewer entries than the RTS Active When, the signal remains active; otherwise, the signal becomes inactive. The range: 0 – `${FifoLevelByte}` (when Data Width is less than or equal 8), and 0 - `${FifoLevelHalfword}` otherwise." /> 143 144 <ParamString id="Tx_out_descr" name="tx_out description" group="Internal" default="The transmitter output drives the output serial data to another device on the serial bus." visible="false" editable="false" desc="tx_out description" /> 145 <ParamString id="Rx_tx_out_descr_smartcard" name="rx_tx_out description for Smartcard Mode" group="Internal" default="The receive and transmit output receives and transmits data from/to another device on the bus. This pin presents if the Com Mode parameter is SmartCard. Note that Drive Mode of the connected pin must be Open Drain Drives Low." visible="false" editable="false" desc="rx_tx_out description for Smartcard Mode" /> 146 <ParamString id="Rx_tx_out_descr_halfDuplex" name="rx_tx_out description for Half Duplex Mode" group="Internal" default="The receive and transmit output receives and transmits data from/to another device on the bus. This pin presents if the Com Mode parameter is Standard Single Wire Half-Duplex Mode. Note that Drive Mode of the connected pin must be Strong Drive" visible="false" editable="false" desc="rx_tx_out description for Half Duplex Mode" /> 147 148 <ParamString id="Rts_out_descr" name="rts_out description" group="Internal" default="The request to send output notifies another device that this device is ready to receive data." visible="false" editable="false" desc="rts_out description" /> 149 <ParamString id="Tx_out_en_descr" name="tx_out_en description" group="Internal" default="The transmitter enable keeps the output level high during serial data transfer." visible="false" editable="false" desc="tx_out_en description" /> 150 151 <!-- Clock Constraint --> 152 <ParamRange id="uartClkHz" name="uartClkHz" group="Internal" default="`${BaudRate * OversampleFinal}`" min="0" max="400000000" resolution="1" visible="false" editable="false" desc="SCB UART clock to operate with desired baud rate." /> 153 154 <ParamString id="hfclockperi" name="PCLK Destination Clock" group="Internal" default="srss[0].clock[0].periclk[0]" visible="false" editable="false" desc="String variable used for source peri clock." /> 155 <ParamString id="hfclock1" name="PCLK Destination Clock" group="Internal" default="srss[0].clock[0].hfclk[1]" visible="false" editable="false" desc="String variable used for source HF clock1." /> 156 <ParamString id="hfclock2" name="PCLK Destination Clock" group="Internal" default="srss[0].clock[0].hfclk[2]" visible="false" editable="false" desc="String variable used for source HF clock2." /> 157 <ParamString id="hfclock10" name="PCLK Destination Clock" group="Internal" default="srss[0].clock[0].hfclk[10]" visible="false" editable="false" desc="String variable used for source HF clock10." /> 158 159 <ParamString id="hfclocksource" name="PCLK Destination" group="Internal" default="`${((ipName ne "mxs22scb") ? ((version eq 1) ? hfclockperi : ((version eq 4) ? hfclock1 : hfclock2)) : hfclock10) }`" visible="false" editable="false" desc="Generates PCLK connection define." /> 160 161 <ParamRange id="clkPeriHz" name="clkPeriHz" group="Internal" default="`${getExposedMember(hfclocksource, "frequency")}`" min="0" max="400000000" resolution="1" visible="false" editable="false" desc="Clk_Peri frequency." /> 162 <ParamRange id="uartDiv" name="uartDiv" group="Internal" default="`${clkPeriHz / cast(float, uartClkHz)}`" min="1" max="16777216" resolution="1" visible="false" editable="false" desc="UART pclk divider value." /> 163 <ParamBool id="useUartDiv8" name="useUartDiv8" group="Internal" default="`${(uartDiv <= pow(2, 8))}`" visible="false" editable="false" desc="Checks whether 8-bit divider can be used for UART operation." /> 164 165 <ParamSignal port="clock[0]" name="Clock" group="Connections" visible="`${hasVisibleOption("clock[0]")}`" desc="Clock that operates this block." canBeEmpty="false" > 166 <Constraint type="ACCEPT" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_8.*" valid="`${useUartDiv8}`" > 167 <Parameter id="intDivider" severity="ERROR" reason="Clock frequency does not match desired `${uartClkHz / 1000.0}` kHz."> 168 <Fixed 169 value="`${((getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) - floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) >= 0.5) ? ceil(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) : floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz)}`" /> 170 </Parameter> 171 </Constraint> 172 <Constraint type="ACCEPT" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_16\[.*" valid="true" > 173 <Parameter id="intDivider" severity="ERROR" reason="Clock frequency does not match desired `${uartClkHz / 1000.0}`kHz." > 174 <Fixed 175 value="`${((getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) - floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) >= 0.5) ? ceil(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) : floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz)}`" /> 176 </Parameter> 177 </Constraint> 178 <Constraint type="ACCEPT" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_(16.5|24.5).*" valid="true" > 179 <Parameter id="intDivider" severity="ERROR" reason="Update integer divider. Clock frequency does not match desired `${uartClkHz / 1000.0}`kHz." > 180 <Fixed 181 value="`${floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / cast(float, uartClkHz))}`" /> 182 </Parameter> 183 <Parameter id="fracDivider" severity="ERROR" reason="Update fractional divider. Clock frequency does not match desired `${uartClkHz / 1000.0}`kHz." > 184 <Fixed 185 value="`${((((getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) - floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz)) * 32.0) - floor(((getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) - floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz)) * 32.0) >= 0.5) ? (ceil(((getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) - floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz)) * 32.0) == 32 ? 31 : ceil(((getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) - floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz)) * 32.0)) : floor(((getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) - floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz)) * 32.0)}`" /> 186 </Parameter> 187 </Constraint> 188 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 189 </ParamSignal> 190 191 <ParamSignal port="clock_scb_en[0]" name="Clock" group="Connections" visible="`${hasVisibleOption("clock_scb_en[0]")}`" desc="Clock that operates this block." canBeEmpty="false" > 192 <Constraint type="ACCEPT" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_8.*" valid="`${useUartDiv8}`" > 193 <Parameter id="intDivider" severity="ERROR" reason="Clock frequency does not match desired `${uartClkHz / 1000.0}` kHz."> 194 <Fixed 195 value="`${((getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) - floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) >= 0.5) ? ceil(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) : floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz)}`" /> 196 </Parameter> 197 </Constraint> 198 <Constraint type="ACCEPT" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_16\[.*" valid="true" > 199 <Parameter id="intDivider" severity="ERROR" reason="Clock frequency does not match desired `${uartClkHz / 1000.0}`kHz." > 200 <Fixed 201 value="`${((getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) - floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) >= 0.5) ? ceil(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) : floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz)}`" /> 202 </Parameter> 203 </Constraint> 204 <Constraint type="ACCEPT" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_(16.5|24.5).*" valid="true" > 205 <Parameter id="intDivider" severity="ERROR" reason="Update integer divider. Clock frequency does not match desired `${uartClkHz / 1000.0}`kHz." > 206 <Fixed 207 value="`${floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / cast(float, uartClkHz))}`" /> 208 </Parameter> 209 <Parameter id="fracDivider" severity="ERROR" reason="Update fractional divider. Clock frequency does not match desired `${uartClkHz / 1000.0}`kHz." > 210 <Fixed 211 value="`${((((getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) - floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz)) * 32.0) - floor(((getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) - floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz)) * 32.0) >= 0.5) ? (ceil(((getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) - floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz)) * 32.0) == 32 ? 31 : ceil(((getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) - floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz)) * 32.0)) : floor(((getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz) - floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / uartClkHz)) * 32.0)}`" /> 212 </Parameter> 213 </Constraint> 214 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 215 </ParamSignal> 216 217 <ParamString id="sourceClock" name="sourceClock" group="Internal" default="`${(hasVisibleOption("clock[0]")) ? (getBlockFromSignal("clock[0]")) : (getBlockFromSignal("clock_scb_en[0]"))}`" visible="false" editable="false" desc="Source Clock Resource" /> 218 <ParamRange id="scbClkHz" name="scbClkHz" group="Internal" default="`${(sourceClock ne "") ? getExposedMember(sourceClock, "frequency") : "1"}`" min="0" max="200000000" resolution="1" visible="false" editable="false" desc="SCB clock frequency in kHz" /> 219 <ParamBool id="pClkDiv8" name="pClkDiv8" group="Internal" default="`${getExposedMember(sourceClock, "type") eq "CY_SYSCLK_DIV_8_BIT"}`" visible="false" editable="false" desc="Source clock uses 8-bit divider." /> 220 221 <ParamSignal port="uart_rx[0]" name="RX" group="Connections" visible="`${!(SmartCard || EnableHalfDuplex) && hasVisibleOption("uart_rx[0]")}`" desc="The receive input receives the serial data from another device on the serial bus." canBeEmpty="true"> 222 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="`${!SmartCard}`" > 223 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 224 <Fixed value="CY_GPIO_DM_HIGHZ" /> 225 </Parameter> 226 </Constraint> 227 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="`${!SmartCard}`" > 228 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 229 <Fixed value="CY_GPIO_DM_HIGHZ" /> 230 </Parameter> 231 </Constraint> 232 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 233 </ParamSignal> 234 235 <ParamSignal port="uart_cts[0]" name="`${EnableTxEn ? "TX_EN" : "CTS"}`" group="Connections" visible="`${!SmartCard && (FlowControl || EnableTxEn) && hasVisibleOption("uart_cts[0]")}`" desc="The clear to send input accepts notification that another device is ready to receive data." canBeEmpty="true"> 236 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="`${!SmartCard && (FlowControl || EnableTxEn)}`" > 237 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 238 <Fixed value="`${EnableTxEn ? "CY_GPIO_DM_STRONG_IN_OFF" : "CY_GPIO_DM_HIGHZ"}`" /> 239 </Parameter> 240 </Constraint> 241 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="`${!SmartCard && (FlowControl || EnableTxEn)}`" > 242 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 243 <Fixed value="`${EnableTxEn ? "CY_GPIO_DM_STRONG_IN_OFF" : "CY_GPIO_DM_HIGHZ"}`" /> 244 </Parameter> 245 </Constraint> 246 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 247 </ParamSignal> 248 <ParamString id="ctsPin" name="ctsPin" group="Internal" default="`${getBlockFromSignal("uart_cts[0]")}`" visible="false" editable="false" desc="" /> 249 250 <ParamSignal port="uart_tx[0]" name="`${(SmartCard || EnableHalfDuplex) ? "RX_TX" : "TX"}`" group="Connections" visible="`${hasVisibleOption("uart_tx[0]")}`" desc="`${SmartCard ? Rx_tx_out_descr_smartcard : ( EnableHalfDuplex ? Rx_tx_out_descr_halfDuplex : Tx_out_descr)}`" canBeEmpty="`${!SmartCard}`"> 251 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 252 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 253 <Fixed value="`${SmartCard ? "CY_GPIO_DM_OD_DRIVESLOW" : (EnableHalfDuplex ? "CY_GPIO_DM_PULLUP" : "CY_GPIO_DM_STRONG_IN_OFF")}`" /> 254 </Parameter> 255 </Constraint> 256 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 257 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 258 <Fixed value="`${SmartCard ? "CY_GPIO_DM_OD_DRIVESLOW" : (EnableHalfDuplex ? "CY_GPIO_DM_PULLUP" : "CY_GPIO_DM_STRONG_IN_OFF")}`" /> 259 </Parameter> 260 </Constraint> 261 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 262 </ParamSignal> 263 <ParamString id="txPin" name="txPin" group="Internal" default="`${getBlockFromSignal("uart_tx[0]")}`" visible="false" editable="false" desc="" /> 264 265 <ParamSignal port="uart_rts[0]" name="RTS" group="Connections" visible="`${!SmartCard && FlowControl && hasVisibleOption("uart_rts[0]")}`" desc="`${Rts_out_descr}`" canBeEmpty="true"> 266 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="`${!SmartCard && FlowControl}`" > 267 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 268 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 269 </Parameter> 270 </Constraint> 271 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="`${!SmartCard && FlowControl}`" > 272 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 273 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 274 </Parameter> 275 </Constraint> 276 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 277 </ParamSignal> 278 <ParamString id="rtsPin" name="rtsPin" group="Internal" default="`${getBlockFromSignal("uart_rts[0]")}`" visible="false" editable="false" desc="" /> 279 280 <ParamSignal port="tr_rx_req[0]" name="RX Trigger Output" group="Connections" visible="`${hasVisibleOption("uart_rx[0]")}`" desc="Connects SCB RX trigger output to the DMA. Configure RX FIFO Level to define this output behavior." canBeEmpty="true" > 281 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 282 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 283 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 284 </Parameter> 285 </Constraint> 286 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 287 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 288 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 289 </Parameter> 290 </Constraint> 291 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 292 </ParamSignal> 293 <ParamSignal port="tr_tx_req[0]" name="TX Trigger Output" group="Connections" visible="`${hasVisibleOption("uart_tx[0]")}`" desc="Connects SCB TX trigger output to the DMA. Configure TX FIFO Level to define this output behavior." canBeEmpty="true" > 294 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 295 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 296 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 297 </Parameter> 298 </Constraint> 299 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 300 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 301 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 302 </Parameter> 303 </Constraint> 304 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 305 </ParamSignal> 306 307 <!--Baud Rate--> 308 <ParamRange id="actualBaudRate" name="Actual Baud Rate (bps)" group="Actual Baud Rate" default="`${scbClkHz/OversampleFinal}`" min="0" max="4294967295" resolution="1" visible="true" editable="false" desc="The actual baud rate displays the baud rate at which the UART operates with current settings." /> 309 <ParamRange id="BaudRateAccuracy" name="Baud Rate Accuracy (%)" group="Actual Baud Rate" default="`${(sourceClock ne "") ? ((abs(BaudRate - actualBaudRate) / BaudRate) * 100) : ((abs(BaudRate) / BaudRate) * 100)}`" min="0" max="200000000" resolution="0.001" visible="true" editable="false" desc="Deviation of actual baud rate from desired baud rate (does not include Clk_Peri accuracy)." /> 310 <ParamString id="ClkFreq" name="Clock Frequency" group="Actual Baud Rate" default="`${(scbClkHz < 1000000) ? (scbClkHz / 1000.0) . " kHz" : (scbClkHz / 1000000.0) . " MHz"}`" visible="true" editable="false" desc="Frequency of the connected clock" /> 311 312 <ParamRange id="RxTriggerLevel" name="RX FIFO Level" group="Trigger Level" default="63" min="0" max="`${FifoLevelMax}`" resolution="1" visible="true" editable="true" desc="This parameter determines the behavior of the signal which drives the RX FIFO Above Level interrupt source and the RX Trigger Output as follows: the signal remains active until the number of data elements in the RX FIFO is greater than the value of the RX FIFO Level. For example, the RX FIFO has 8 data elements and the RX FIFO level is 0. The signal remains active until all data elements are read from the RX FIFO. The range: 0 – `${FifoLevelByte}` (when Data Width is less or equal 8), and 0 - `${FifoLevelHalfword}` otherwise." /> 313 314 <ParamRange id="TxTriggerLevel" name="TX FIFO Level" group="Trigger Level" default="63" min="0" max="`${FifoLevelMax}`" resolution="1" visible="true" editable="true" desc="This parameter determines the behavior of the signal which drives the TX FIFO below-level interrupt source and TX Trigger Output as follows: until the number of data elements in the TX FIFO is less than the value of TX FIFO level. For example, the TX FIFO has 0 data elements (empty) and the TX FIFO level is 7. The signal remains active until TX FIFO has 7 data elements. The range: 0 – `${FifoLevelByte}` (when Data Width is less or equal 8), and 0 - `${FifoLevelHalfword}` otherwise." /> 315 316 <!--Multi Processor Mode--> 317 <ParamBool id="MultiProc" name="Enable Multi Processor Mode" group="Multi Processor Mode" default="false" visible="`${!SmartCard}`" editable="true" desc="This parameter enables the UART multi-processor mode. Only applicable when Com Mode is Standard." /> 318 <ParamRange id="MpRxAddress" name="Address" group="Multi Processor Mode" default="0" min="0" max="255" resolution="1" visible="`${!SmartCard}`" editable="true" desc="This parameter specifies the UART address. Only applicable when the Enable Multi Processor Mode parameter is true." /> 319 <ParamRange id="MpRxAddressMask" name="Mask" group="Multi Processor Mode" default="255" min="0" max="255" resolution="1" visible="`${!SmartCard}`" editable="true" desc="This parameter specifies the UART address mask. Only applicable when the Enable Multi Processor Mode parameter is true. 320 - Bit value 0 – excludes a bit from the address comparison. 321 - Bit value 1 – the bit needs to match with the corresponding bit of the UART address." /> 322 <ParamBool id="MpRxAcceptAddress" name="Accept Matching Address in RX FIFO" group="Multi Processor Mode" default="false" visible="`${!SmartCard}`" editable="true" desc="This parameter determines whether to put the matched UART address into the RX FIFO. Only applicable when the Enable Multi Processor Mode parameter is true." /> 323 324 <!-- Drop options --> 325 <ParamBool id="DropOnFrameErr" name="Drop on Frame Error" group="Advanced" default="false" visible="true" editable="true" desc="This parameter determines if the data is dropped from the RX FIFO on a frame error event." /> 326 <ParamBool id="DropOnParityErr" name="Drop on Parity Error" group="Advanced" default="false" visible="true" editable="true" desc="This parameter determines if the data is dropped from the RX FIFO on a parity error event." /> 327 328 <!--Break Width--> 329 <ParamRange id="BreakSignalBits" name="Break Signal Bits" group="Advanced" default="11" min="7" max="16" resolution="1" visible="`${Standard}`" editable="true" desc="This parameter specifies the break width in bits. The range: 7-16." /> 330 331 <!--Break Level--> 332 <ParamChoice id="BreakLevel" name="Break Level" group="Advanced" default="0" visible="`${(((version > 1) || (ipName eq "mxs22scb")) && (Standard))}`" editable="true" desc="This parameter specifies the low or high level pulse detection for break condition."> 333 <Entry name="Low Level Pulse Detection" value="0" visible="true" /> 334 <Entry name="High Level Pulse Detection" value="1" visible="true" /> 335 </ParamChoice> 336 337 <!--Smart Card--> 338 <ParamBool id="SmCardRetryOnNack" name="Retry on Nack" group="Advanced" default="false" visible="`${SmartCard}`" editable="true" desc="This parameter defines whether to send a message again when a NACK response is received. Only applicable when Com Mode is SmartCard." /> 339 340 <!--IrDA--> 341 <ParamChoice id="IrdaPolarity" name="Invert RX" group="Advanced" default="NON_INVERTING" visible="`${IrDA}`" editable="true" desc="This parameter enables the inversion of the incoming RX line signal. Only applicable when Com Mode is IrDA."> 342 <Entry name="Non-Inverting" value="NON_INVERTING" visible="true" /> 343 <Entry name="Inverting" value="INVERTING" visible="true" /> 344 </ParamChoice> 345 346 <ParamBool id="inFlash" name="Store Config in Flash" group="Advanced" default="true" visible="true" editable="true" desc="Controls whether the configuration structure is stored in flash (const, true) or SRAM (not const, false)." /> 347 348 <!-- API Mode --> 349 <ParamChoice id="ApiMode" name="API Mode" group="API Mode" default="HIGH_LEVEL" visible="true" editable="true" desc="This parameter defines which API set will be used during driver operation. High Level means driver controls interrupt sources and Cy_SCB_UART_Interrupt function must be called in the interrupt handler hooked to NVIC. Low Level means that the user configures interrupt sources and implements own interrupt handler or do not use interrupt at all."> 350 <Entry name="High Level" value="HIGH_LEVEL" visible="true" /> 351 <Entry name="Low Level" value="LOW_LEVEL" visible="true" /> 352 </ParamChoice> 353 <ParamBool id="ConfigIntr" name="ConfigIntr" group="Internal" default="`${ApiMode eq LOW_LEVEL}`" visible="false" editable="false" desc="This parameter specifies the visibility of all RX Interrupt Sources parameter." /> 354 355 <!--RX Interrupt Sources--> 356 <ParamBool id="IntrRxNotEmpty" name="RX FIFO not Empty" group="RX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the RX FIFO not-empty interrupt source to trigger the interrupt output." /> 357 <ParamBool id="IntrRxFull" name="RX FIFO Full" group="RX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the RX FIFO full interrupt source to trigger the interrupt output." /> 358 <ParamBool id="IntrRxOverflow" name="RX FIFO Overflow" group="RX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the RX FIFO overflow interrupt source to trigger the interrupt output." /> 359 <ParamBool id="IntrRxUnderflow" name="RX FIFO Underflow" group="RX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the RX FIFO underflow interrupt source to trigger the interrupt output." /> 360 <ParamBool id="IntrRxFrameErr" name="RX Frame Error" group="RX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the RX frame error interrupt source to trigger the interrupt output." /> 361 <ParamBool id="IntrRxParityErr" name="RX Parity Error" group="RX Interrupt Sources" default="false" visible="`${ConfigIntr && (ParityType ne CY_SCB_UART_PARITY_NONE) && (!IrDA) && (!MultiProcParityCheck)}`" editable="true" desc="This parameter enables the RX parity error interrupt source to trigger the interrupt output." /> 362 <ParamBool id="IntrRxBreakDetected" name="Break Detected" group="RX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the RX break detection interrupt source to trigger the interrupt output." /> 363 <ParamBool id="IntrRxTrigger" name="RX FIFO Above Level" group="RX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the RX FIFO above-level interrupt source to trigger the interrupt output." /> 364 365 <ParamRange id="RxIntrMask" name="RxIntrMask" group="RX Interrupt Sources" default="`${ConfigIntr ? (IntrRxTrigger ? 0x1 : 0) + (IntrRxNotEmpty ? 0x4 : 0) + (IntrRxFull ? 0x08 : 0) + (IntrRxOverflow ? 0x20 : 0) + (IntrRxUnderflow ? 0x40 : 0) + (IntrRxFrameErr ? 0x100 : 0) + (((ParityType ne CY_SCB_UART_PARITY_NONE) && IntrRxParityErr) ? 0x200 : 0) + (IntrRxBreakDetected ? 0x800 : 0) : 0}`" min="0" max="4294967295" resolution="1" visible="false" editable="false" desc="This parameter defines the RX interrupt mask to be written into the SCB.INTR_RX_MASK register." /> 366 367 <!--TX Interrupt Sources--> 368 <ParamBool id="IntrTxUartDone" name="UART Done" group="TX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the UART done interrupt source to trigger the interrupt output." /> 369 <ParamBool id="IntrTxUartLostArb" name="TX Lost Arbitration" group="TX Interrupt Sources" default="false" visible="`${ConfigIntr && SmartCard}`" editable="true" desc="This parameter enables the TX lost arbitration interrupt source to trigger the interrupt output." /> 370 <ParamBool id="IntrTxUartNack" name="TX NACK" group="TX Interrupt Sources" default="false" visible="`${ConfigIntr && SmartCard}`" editable="true" desc="This parameter enables the TX NACK interrupt source to trigger the interrupt output." /> 371 <ParamBool id="IntrTxEmpty" name="TX FIFO Empty" group="TX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the TX FIFO empty interrupt source to trigger the interrupt output." /> 372 <ParamBool id="IntrTxNotFull" name="TX FIFO not Full" group="TX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the TX FIFO not-full interrupt source to trigger the interrupt output." /> 373 <ParamBool id="IntrTxOverflow" name="TX FIFO Overflow" group="TX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the TX FIFO overflow interrupt source to trigger the interrupt output." /> 374 <ParamBool id="IntrTxUnderflow" name="TX FIFO Underflow" group="TX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the TX FIFO underflow interrupt source to trigger the interrupt output." /> 375 <ParamBool id="IntrTxTrigger" name="TX FIFO Below Level" group="TX Interrupt Sources" default="false" visible="`${ConfigIntr}`" editable="true" desc="This parameter enables the TX FIFO below-level interrupt source to trigger the interrupt output." /> 376 377 <ParamRange id="TxIntrMask" name="Tx Intr Masks" group="TX Interrupt Sources" default="`${ConfigIntr ? (IntrTxTrigger ? 0x1 : 0) + (IntrTxNotFull ? 0x2 : 0) + (IntrTxEmpty ? 0x10 : 0) + (IntrTxOverflow ? 0x20 : 0) + (IntrTxUnderflow ? 0x40 : 0) + (IntrTxUartDone ? 0x200 : 0) + (((SmartCard) && IntrTxUartNack) ? 0x100 : 0) + (((SmartCard) && IntrTxUartLostArb) ? 0x400 : 0) : 0}`" min="0" max="4294967295" resolution="1" visible="false" editable="false" desc="This parameter defines the TX interrupt mask to be written into the SCB.INTR_TX_MASK register." /> 378 379 <!-- SCB instance number --> 380 <ParamString id="InstNumber" name="InstNumber" group="Internal" default="`${getInstNumber("scb")}`" visible="false" editable="false" desc="SCB Instance name number." /> 381 382 <!-- Peripheral clock divider connection --> 383 <ParamBool id="pclkOk" name="PCLK Valid" group="Internal" default="`${(hasVisibleOption("clock[0]")) ? (hasConnection("clock", 0) && isBlockUsed(sourceClock)) : (hasConnection("clock_scb_en", 0) && isBlockUsed(sourceClock)) }`" visible="false" editable="false" desc="Checks whether there is a PCLK connected and enabled." /> 384 385 <ParamString id="pclkSCBClockString" name="PCLK Destination Clock" group="Internal" default="PCLK_SCB`${InstNumber}`_CLOCK" visible="false" editable="false" desc="String variable used for PCLK_SCB_CLOCK." /> 386 <ParamString id="pclkSCBClockSCBENString" name="PCLK Destination Clock" group="Internal" default="PCLK_SCB`${InstNumber}`_CLOCK_SCB_EN" visible="false" editable="false" desc="String variable used only for PCLK_SCB_CLOCK_SCB_EN." /> 387 388 <ParamString id="pclkDst" name="PCLK Destination" group="Internal" default="`${(hasVisibleOption("clock[0]")) ? pclkSCBClockString : pclkSCBClockSCBENString }`" visible="false" editable="false" desc="Generates PCLK connection define." /> 389 </Parameters> 390 391 <DRCs> 392 <!-- DRC: 8-bit clock divider must not be used --> 393 <DRC type="ERROR" text="Wider clock divider resolution is required for UART to operate with baud rate `${BaudRate}` bps." paramId="clock[0]" condition="`${!useUartDiv8 && pClkDiv8}`" /> 394 395 <!-- DRC: 8-bit clock divider must not be used --> 396 <DRC type="ERROR" text="Wider clock divider resolution is required for UART to operate with baud rate `${BaudRate}` bps." paramId="clock_scb_en[0]" condition="`${!useUartDiv8 && pClkDiv8}`" /> 397 398 <!-- DRC: BaudRate for IrDA mode --> 399 <DRC type="ERROR" text="The baud rate value must be 115200, 57600, 38400, 19200, 9600, 2400 or 1200 bps when the IrDA mode is selected." paramId="BaudRate" condition="`${(IrDA) ? !((BaudRate eq 1200) || (BaudRate eq 2400) || (BaudRate eq 9600) || (BaudRate eq 19200) || (BaudRate eq 38400) || (BaudRate eq 57600) || (BaudRate eq 115200)) : false}`" /> 400 401 <!-- DRC: checks DataWidth for Multi Processor --> 402 <DRC type="ERROR" text="To enable multi processor mode set Com Mode = Standard and Data Width = 9 bits." paramId="MultiProc" condition="`${MultiProc ? (!Standard || (DataWidth ne 9)) : false}`" /> 403 404 <!-- DRC: checks that DataWidth = 9 is valid --> 405 <DRC type="ERROR" text="Only Standard mode supports 9 bits data width." paramId="DataWidth" condition="`${(!Standard && (DataWidth eq 9))}`" /> 406 407 <!-- DRC: checks break signal length in bits --> 408 <DRC type="ERROR" text="The break signal bits value must be at least by 2 bits greater than Data Width and less than or equal 16." paramId="BreakSignalBits" condition="`${(BreakSignalBits < (DataWidth + 2)) ? true : false}`" /> 409 410 <!-- DRC: checks EnableTxEn and FlowControl usage --> 411 <DRC type="ERROR" paramId="EnableTxEn" text="The FlowControl and TX-Enable options are mutually exclusive." condition="`${(EnableTxEn && FlowControl) ? true : false}`" /> 412 413 <!-- DRC: checks pins availability for SmartCard mode --> 414 <DRC type="ERROR" paramId="ComMode" text="The SmartCard mode is not supported for the selected SCB (Serial Communication Block)." condition="`${SmartCard && !hasVisibleOption("uart_tx[0]")}`" /> 415 416 <!-- DRC: checks pins availability for EnableTxEn --> 417 <DRC type="ERROR" paramId="EnableTxEn" text="The TX-Enable option is not supported for the selected SCB (Serial Communication Block)." condition="`${EnableTxEn && !hasVisibleOption("uart_cts[0]")}`" /> 418 419 <!-- DRC: checks pins availability for SmartCard mode --> 420 <DRC type="ERROR" paramId="FlowControl" text="The Flow Control option is not supported for the selected SCB (Serial Communication Block)." condition="`${FlowControl && !hasVisibleOption("uart_rts[0]") && !hasVisibleOption("uart_cts[0]")}`" /> 421 </DRCs> 422 423 <ConfigFirmware> 424 <ConfigInclude value="cy_scb_uart.h" include="true" /> 425 <ConfigInclude value="cy_sysclk.h" include="`${pclkOk}`" /> 426 <ConfigInclude value="cyhal_hwmgr.h" include="true" guard="defined (CY_USING_HAL)" /> 427 <ConfigInclude value="cyhal.h" include="true" guard="defined (CY_USING_HAL)" /> 428 <ConfigInclude value="cyhal_hw_types.h" include="true" guard="defined (CY_USING_HAL_LITE)" /> 429 430 <ConfigDefine name="`${INST_NAME}`_HW" value="SCB`${InstNumber}`" public="true" include="true" /> 431 <ConfigDefine name="`${INST_NAME}`_IRQ" value="scb_`${InstNumber}`_interrupt_IRQn" public="true" include="true" /> 432 <ConfigStruct name="`${INST_NAME}`_config" type="cy_stc_scb_uart_config_t" const="`${inFlash}`" public="true" include="true" > 433 <Member name="uartMode" value="`${ComMode}`" /> 434 <Member name="enableMutliProcessorMode" value="`${MultiProc ? "true" : "false"}`" /> 435 <Member name="smartCardRetryOnNack" value="`${(SmartCard && SmCardRetryOnNack) ? "true" : "false"}`" /> 436 <Member name="irdaInvertRx" value="`${(IrDA && (IrdaPolarity eq INVERTING)) ? "true" : "false"}`" /> 437 <Member name="irdaEnableLowPowerReceiver" value="`${(IrDA && IrdaLowPower) ? "true" : "false"}`" /> 438 439 <Member name="halfDuplexMode" value="`${EnableHalfDuplex}`" include="`${(version > 3) && (ipName eq "mxscb")}`" /> 440 441 <Member name="oversample" value="`${(Standard || SmartCard) ? Oversample : (IrDA && !IrdaLowPower) ? IrDAOversample : IrDAOversampleDefine}`" /> 442 443 <Member name="enableMsbFirst" value="`${(BitsOrder eq CY_SCB_UART_MSB_FIRST) ? "true" : "false"}`" /> 444 <Member name="dataWidth" value="`${DataWidth}`UL" /> 445 <Member name="parity" value="`${(Standard && (DataWidth ne 9)) ? ParityType : (SmartCard) ? "CY_SCB_UART_PARITY_EVEN" : "CY_SCB_UART_PARITY_NONE"}`" /> 446 <Member name="stopBits" value="`${StopBits}`" /> 447 <Member name="enableInputFilter" value="`${((IrDA) ? "true" : EnableInputFilter) ? "true" : "false"}`" /> 448 <Member name="breakWidth" value="`${BreakSignalBits}`UL" /> 449 <Member name="dropOnFrameError" value="`${DropOnFrameErr}`" /> 450 <Member name="dropOnParityError" value="`${((ParityType ne CY_SCB_UART_PARITY_NONE) && DropOnParityErr) ? "true" : "false"}`" /> 451 <Member name="breaklevel" value="`${BreakLevel ? "true" : "false"}`" include="`${(version > 1) || (ipName eq "mxs22scb")}`" /> 452 453 <Member name="receiverAddress" value="`${MultiProc ? MpRxAddress : "0x0UL"}`" /> 454 <Member name="receiverAddressMask" value="`${MultiProc ? MpRxAddressMask : "0x0UL"}`" /> 455 <Member name="acceptAddrInFifo" value="`${(MultiProc && MpRxAcceptAddress) ? "true" : "false"}`" /> 456 457 <Member name="enableCts" value="`${FlowControl ? "true" : "false"}`" /> 458 <Member name="ctsPolarity" value="`${FlowControl ? CtsPolarity : "CY_SCB_UART_ACTIVE_LOW"}`" /> 459 <Member name="rtsRxFifoLevel" value="`${FlowControl ? RtsTriggerLevel : "0UL"}`" /> 460 <Member name="rtsPolarity" value="`${FlowControl ? RtsPolarity : "CY_SCB_UART_ACTIVE_LOW"}`" /> 461 462 <Member name="rxFifoTriggerLevel" value="`${RxTriggerLevel}`UL" /> 463 <Member name="rxFifoIntEnableMask" value="`${RxIntrMask}`UL" /> 464 465 <Member name="txFifoTriggerLevel" value="`${TxTriggerLevel}`UL" /> 466 <Member name="txFifoIntEnableMask" value="`${TxIntrMask}`UL" /> 467 </ConfigStruct> 468 469 <ConfigStruct name="`${INST_NAME}`_obj" type="cyhal_resource_inst_t" const="true" public="true" include="true" guard="defined (CY_USING_HAL) || defined(CY_USING_HAL_LITE)"> 470 <Member name="type" value="CYHAL_RSC_SCB" /> 471 <Member name="block_num" value="`${getInstNumber("scb")}`U" /> 472 <Member name="channel_num" value="0U" /> 473 </ConfigStruct> 474 475 <ConfigStruct name="`${INST_NAME}`_clock" type="cyhal_clock_t" const="`${inFlash}`" public="true" include="true" guard="defined(CY_USING_HAL_LITE) || defined (CY_USING_HAL)"> 476 <Member name="block" value="`${getExposedMember(sourceClock, "hal_block")}`" /> 477 <Member name="channel" value="`${getExposedMember(sourceClock, "number")}`" /> 478 <Member name="reserved" value="false" guard="defined (CY_USING_HAL)" /> 479 <Member name="funcs" value="NULL" guard="defined (CY_USING_HAL)" /> 480 </ConfigStruct> 481 482 <ConfigStruct name="`${INST_NAME}`_hal_config" type="cyhal_uart_configurator_t" const="`${inFlash}`" public="true" include="true" guard="defined (CY_USING_HAL) || defined(CY_USING_HAL_LITE)"> 483 <Member name="resource" value="&`${INST_NAME}`_obj" /> 484 <Member name="config" value="&`${INST_NAME}`_config" /> 485 <Member name="clock" value="&`${INST_NAME}`_clock" /> 486 <Member name="gpios" value="{.pin_tx = `${txPin && hasExposedMember(txPin, "halPortPin") ? getExposedMember(txPin, "halPortPin") : "NC"}`, .pin_rts = `${rtsPin && hasExposedMember(rtsPin, "halPortPin") ? getExposedMember(rtsPin, "halPortPin") : "NC"}`, .pin_cts = `${ctsPin && hasExposedMember(ctsPin, "halPortPin") ? getExposedMember(ctsPin, "halPortPin") : "NC"}`}" guard="defined (CY_USING_HAL)" /> 487 </ConfigStruct> 488 489 <ConfigInstruction purpose="INITIALIZE" value="Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB`${InstNumber}`_PERI_NR, CY_MMIO_SCB`${InstNumber}`_GROUP_NR, CY_MMIO_SCB`${InstNumber}`_SLAVE_NR, CY_MMIO_SCB`${InstNumber}`_CLK_HF_NR);" include="`${(ipName eq "mxs22scb")}`" /> 490 <ConfigInstruction purpose="INITIALIZE" value="Cy_SysClk_PeriPclkAssignDivider(`${pclkDst}`, `${getExposedMember(sourceClock, "clockSel")}`);" include="`${(((version > 1) || (ipName eq "mxs22scb")) && pclkOk)}`" /> 491 <ConfigInstruction purpose="INITIALIZE" value="Cy_SysClk_PeriphAssignDivider(`${pclkDst}`, `${getExposedMember(sourceClock, "clockSel")}`);" include="`${((version eq 1) && pclkOk && (ipName ne "mxs22scb"))}`" /> 492 493 <ConfigInstruction purpose="RESERVE" value="cyhal_hwmgr_reserve(&`${INST_NAME}`_obj);" include="true" guard="defined (CY_USING_HAL)" /> 494 </ConfigFirmware> 495</Personality> 496
