1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file tdm.cypersonality 6* \version 1.1 7* 8* \brief 9* TDM personality description file. It Supports CAT1B family of devices. 10* 11* 12******************************************************************************** 13* \copyright 14* Copyright (c) (2022-2023), Cypress Semiconductor Corporation (an Infineon company) or 15* an affiliate of Cypress Semiconductor Corporation. 16* SPDX-License-Identifier: Apache-2.0 17* 18* Licensed under the Apache License, Version 2.0 (the "License"); 19* you may not use this file except in compliance with the License. 20* You may obtain a copy of the License at 21* 22* http://www.apache.org/licenses/LICENSE-2.0 23* 24* Unless required by applicable law or agreed to in writing, software 25* distributed under the License is distributed on an "AS IS" BASIS, 26* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 27* See the License for the specific language governing permissions and 28* limitations under the License. 29*****************************************************************************--> 30 31<Personality id="tdm" name="TDM" version="1.1" xmlns="http://cypress.com/xsd/cyhwpersonality_v8"> 32 <Dependencies> 33 <IpBlock name="mxtdm"> 34 <Version major="1" /> 35 <Version major="2" /> 36 </IpBlock> 37 <Resource name="tdm" /> 38 <OperatingMode value="MCU"/> 39 </Dependencies> 40 <ExposedMembers /> 41 <Parameters> 42 <!-- PDL documentation --> 43 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__tdm.html" linkText="Open TDM Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 44 45 <!-- TX --> 46 <ParamBool id="txEnabled" name="Enable" group="TX" default="true" visible="true" editable="true" desc="Enables the transmitter" /> 47 <ParamChoice id="txMode" name="Mode" group="TX" default="CY_TDM_DEVICE_MASTER" visible="`${txEnabled}`" editable="true" desc="Sets mode to master or slave"> 48 <Entry name="Slave" value="CY_TDM_DEVICE_SLAVE" visible="true" /> 49 <Entry name="Master" value="CY_TDM_DEVICE_MASTER" visible="true" /> 50 </ParamChoice> 51 52 <ParamChoice id="txclockselect" name="Clock Select" group="TX" default="CY_TDM_SEL_SRSS_CLK0" visible="`${txEnabled}`" editable="true" desc="Set interface source clock: SRSS[0], SRSS[1], SRSS[2], SRSS[3], MCLK_IN"> 53 <Entry name="Interface Clock 0" value="CY_TDM_SEL_SRSS_CLK0" visible="true" /> 54 <Entry name="Interface Clock 1" value="CY_TDM_SEL_SRSS_CLK1" visible="false" /> 55 <Entry name="Interface Clock 2" value="CY_TDM_SEL_SRSS_CLK2" visible="false" /> 56 <Entry name="Interface Clock 3" value="CY_TDM_SEL_SRSS_CLK3" visible="false" /> 57 <Entry name="Interface Clock MCLK" value="CY_TDM_SEL_MCLK_IN" visible="true" /> 58 </ParamChoice> 59 <ParamRange id="txclockDiv" name="Clock Divider" group="TX" default="16" min="1" max="256" resolution="1" visible="`${txEnabled}`" editable="true" desc="Sets the input Clock Divider. Set to an even value ({2, 4, 6, ..., 256}), to ensure a 50/50% duty cycle clock." /> 60 61 <ParamChoice id="txInterfaceMode" name="Interface Mode" group="TX" default="true" visible="false" editable="false" desc="Set interface transfer mode: I2S mode, TDM mode"> 62 <Entry name="I2S mode" value="true" visible="true" /> 63 <Entry name="TDM mode" value="false" visible="true" /> 64 </ParamChoice> 65 66 <ParamChoice id="txAlignment" name="Alignment Format" group="TX" default="CY_TDM_LEFT_DELAYED" visible="`${txEnabled}`" editable="true" desc="Set Alignment format: CY_TDM_LEFT_DELAYED, CY_TDM_LEFT, CY_TDM_RIGHT_DELAYED, CY_TDM_RIGHT"> 67 <Entry name="Left-aligned delayed" value="CY_TDM_LEFT_DELAYED" visible="true" /> 68 <Entry name="Left-aligned" value="CY_TDM_LEFT" visible="true" /> 69 <Entry name="Right-aligned delayed" value="CY_TDM_RIGHT_DELAYED" visible="true" /> 70 <Entry name="Right-aligned" value="CY_TDM_RIGHT" visible="true" /> 71 </ParamChoice> 72 73 <ParamChoice id="txsyncformat" name="Frame Sync" group="TX" default="CY_TDM_BIT_PERIOD" visible="`${txEnabled}`" editable="true" desc="Set interface transfer mode: CY_TDM_BIT_PERIOD, CY_TDM_CH_PERIOD"> 74 <Entry name="Single Bit" value="CY_TDM_BIT_PERIOD" visible="true" /> 75 <Entry name="Channel Length" value="CY_TDM_CH_PERIOD" visible="true" /> 76 </ParamChoice> 77 78 <ParamRange id="txChannels" name="Channels" group="TX" default="2" min="1" max="8" resolution="1" visible="`${txEnabled}`" editable="true" desc="Number of channels per frame (2 is the only valid value for Left Justified and I2S modes)" /> 79 80 <ParamChoice id="txChannelsEnabled" name="Channels Enabled" group="TX" default="0x3" visible="`${!txInterfaceMode && txEnabled}`" editable="true" desc="Set channels enabled (Total 8 Channels can be enabled)"> 81 <Entry name="1" value="0x1" visible="true" /> 82 <Entry name="2" value="0x3" visible="true" /> 83 <Entry name="3" value="0x7" visible="true" /> 84 <Entry name="4" value="0xF" visible="true" /> 85 <Entry name="5" value="0x1F" visible="true" /> 86 <Entry name="6" value="0x3F" visible="true" /> 87 <Entry name="7" value="0x7F" visible="true" /> 88 <Entry name="8" value="0xFF" visible="true" /> 89 </ParamChoice> 90 91 <ParamChoice id="txChannelLength" name="Channel Size" group="TX" default="16" visible="`${!txInterfaceMode && txEnabled}`" editable="true" desc="Set channel length in bits (32 bit is the only valid value for TDM modes)"> 92 <Entry name="8" value="8" visible="true" /> 93 <Entry name="16" value="16" visible="true" /> 94 <Entry name="18" value="18" visible="true" /> 95 <Entry name="20" value="20" visible="true" /> 96 <Entry name="24" value="24" visible="true" /> 97 <Entry name="32" value="32" visible="true" /> 98 </ParamChoice> 99 <ParamChoice id="txWordLength" name="Word Size" group="TX" default="16" visible="`${!txInterfaceMode && txEnabled}`" editable="true" desc="Set word length (in bits)"> 100 <Entry name="8" value="8" visible="true" /> 101 <Entry name="16" value="16" visible="true" /> 102 <Entry name="18" value="18" visible="true" /> 103 <Entry name="20" value="20" visible="true" /> 104 <Entry name="24" value="24" visible="true" /> 105 <Entry name="32" value="32" visible="true" /> 106 </ParamChoice> 107 108 <ParamChoice id="txsignalInput" name="Signal Input" group="TX" default="0" visible="false" editable="true" desc="Controls routing to the TX slave signalling inputs (FSYNC/SCK):'0': TX slave signaling independent from RX signaling: '1': TX slave signalling inputs driven by RX Slave: '2': TX slave signalling inputs driven by RX Master:"> 109 <Entry name="0" value="0" visible="true" /> 110 <Entry name="1" value="1" visible="true" /> 111 <Entry name="2" value="2" visible="true" /> 112 </ParamChoice> 113 114 <ParamChoice id="txsyncFormatPolarity" name="Sync Format Polarity" group="TX" default="CY_TDM_SIGN" visible="`${txEnabled}`" editable="true" desc="Channel synchronization polarity"> 115 <Entry name="Normal" value="CY_TDM_SIGN" visible="true" /> 116 <Entry name="Inverted" value="CY_TDM_SIGN_INVERTED" visible="true" /> 117 </ParamChoice> 118 <ParamChoice id="txSckoPolarity" name="Output Serial Clock Polarity" group="TX" default="CY_TDM_CLK" visible="`${txEnabled}`" editable="true" desc="Polarity of the output SCK signal (available only in master mode)"> 119 <Entry name="Normal" value="CY_TDM_CLK" visible="true" /> 120 <Entry name="Inverted" value="CY_TDM_CLK_INVERTED" visible="true" /> 121 </ParamChoice> 122 <ParamRange id="txFifoTriggerLevel" name="FIFO Trigger Level" group="TX" default="0" min="0" max="255" resolution="1" visible="`${txEnabled}`" editable="true" desc="Set FIFO level to trigger an event (interrupt or DMA request)." /> 123 <ParamBool id="txDmaTrigger" name="DMA Trigger" group="TX" default="false" visible="`${txEnabled}`" editable="true" desc="Enables DMA trigger" /> 124 125 <!-- RX --> 126 <ParamBool id="rxEnabled" name="Enable" group="RX" default="true" visible="true" editable="true" desc="Enables the receiver" /> 127 <ParamChoice id="rxMode" name="Mode" group="RX" default="CY_TDM_DEVICE_SLAVE" visible="`${rxEnabled}`" editable="true" desc="Sets mode to master or slave"> 128 <Entry name="Slave" value="CY_TDM_DEVICE_SLAVE" visible="true" /> 129 <Entry name="Master" value="CY_TDM_DEVICE_MASTER" visible="true" /> 130 </ParamChoice> 131 132 <ParamChoice id="rxclockselect" name="Clock Select" group="RX" default="CY_TDM_SEL_SRSS_CLK0" visible="`${rxEnabled}`" editable="true" desc="Set interface source clock: SRSS[0], SRSS[1], SRSS[2], SRSS[3], MCLK_IN"> 133 <Entry name="Interface Clock 0" value="CY_TDM_SEL_SRSS_CLK0" visible="true" /> 134 <Entry name="Interface Clock 1" value="CY_TDM_SEL_SRSS_CLK1" visible="false" /> 135 <Entry name="Interface Clock 2" value="CY_TDM_SEL_SRSS_CLK2" visible="false" /> 136 <Entry name="Interface Clock 3" value="CY_TDM_SEL_SRSS_CLK3" visible="false" /> 137 <Entry name="Interface Clock MCLK" value="CY_TDM_SEL_MCLK_IN" visible="true" /> 138 </ParamChoice> 139 <ParamRange id="rxclockDiv" name="Clock Divider" group="RX" default="16" min="1" max="256" resolution="1" visible="`${rxEnabled}`" editable="true" desc="Sets the input Clock Divider. Set to an even value ({2, 4, 6, ..., 256}), to ensure a 50/50% duty cycle clock." /> 140 141 <ParamChoice id="rxInterfaceMode" name="Interface Mode" group="RX" default="true" visible="false" editable="false" desc="Set interface transfer mode: I2S mode, TDM mode"> 142 <Entry name="I2S mode" value="true" visible="true" /> 143 <Entry name="TDM mode" value="false" visible="true" /> 144 </ParamChoice> 145 146 <ParamChoice id="rxAlignment" name="Alignment Format" group="RX" default="CY_TDM_LEFT_DELAYED" visible="`${rxEnabled}`" editable="true" desc="Set Alignment format: CY_TDM_LEFT_DELAYED, CY_TDM_LEFT, CY_TDM_RIGHT_DELAYED, CY_TDM_RIGHT"> 147 <Entry name="Left-aligned delayed" value="CY_TDM_LEFT_DELAYED" visible="true" /> 148 <Entry name="Left-aligned" value="CY_TDM_LEFT" visible="true" /> 149 <Entry name="Right-aligned delayed" value="CY_TDM_RIGHT_DELAYED" visible="true" /> 150 <Entry name="Right-aligned" value="CY_TDM_RIGHT" visible="true" /> 151 </ParamChoice> 152 153 <ParamChoice id="rxsyncformat" name="Frame Sync" group="RX" default="CY_TDM_BIT_PERIOD" visible="`${rxEnabled}`" editable="true" desc="Set interface transfer mode: CY_TDM_BIT_PERIOD, CY_TDM_CH_PERIOD"> 154 <Entry name="Single Bit" value="CY_TDM_BIT_PERIOD" visible="true" /> 155 <Entry name="Channel Length" value="CY_TDM_CH_PERIOD" visible="true" /> 156 </ParamChoice> 157 158 <ParamRange id="rxChannels" name="Channels" group="RX" default="2" min="1" max="8" resolution="1" visible="`${rxEnabled}`" editable="true" desc="Number of channels per frame (2 is the only valid value for Left Justified and I2S modes)" /> 159 160 <ParamChoice id="rxChannelsEnabled" name="Channels Enabled" group="RX" default="0x3" visible="`${!rxInterfaceMode && rxEnabled}`" editable="true" desc="Set channels enabled (Total 8 Channels can be enabled)"> 161 <Entry name="1" value="0x1" visible="true" /> 162 <Entry name="2" value="0x3" visible="true" /> 163 <Entry name="3" value="0x7" visible="true" /> 164 <Entry name="4" value="0xF" visible="true" /> 165 <Entry name="5" value="0x1F" visible="true" /> 166 <Entry name="6" value="0x3F" visible="true" /> 167 <Entry name="7" value="0x7F" visible="true" /> 168 <Entry name="8" value="0xFF" visible="true" /> 169 </ParamChoice> 170 171 <ParamChoice id="rxChannelLength" name="Channel Size" group="RX" default="16" visible="`${!rxInterfaceMode && rxEnabled}`" editable="true" desc="Set channel length in bits (32 bit is the only valid value for TDM modes)"> 172 <Entry name="8" value="8" visible="true" /> 173 <Entry name="16" value="16" visible="true" /> 174 <Entry name="18" value="18" visible="true" /> 175 <Entry name="20" value="20" visible="true" /> 176 <Entry name="24" value="24" visible="true" /> 177 <Entry name="32" value="32" visible="true" /> 178 </ParamChoice> 179 <ParamChoice id="rxWordLength" name="Word Size" group="RX" default="16" visible="`${!rxInterfaceMode && rxEnabled}`" editable="true" desc="Set word length (in bits)"> 180 <Entry name="8" value="8" visible="true" /> 181 <Entry name="16" value="16" visible="true" /> 182 <Entry name="18" value="18" visible="true" /> 183 <Entry name="20" value="20" visible="true" /> 184 <Entry name="24" value="24" visible="true" /> 185 <Entry name="32" value="32" visible="true" /> 186 </ParamChoice> 187 188 <ParamChoice id="rxsignalInput" name="Signal Input" group="RX" default="0" visible="false" editable="true" desc="Controls routing to the RX slave signalling inputs (FSYNC/SCK):'0': RX slave signaling independent from TX signaling: '1': RX slave signalling inputs driven by TX Slave: '2': RX slave signalling inputs driven by TX Master:"> 189 <Entry name="0" value="0" visible="true" /> 190 <Entry name="1" value="1" visible="true" /> 191 <Entry name="2" value="2" visible="true" /> 192 </ParamChoice> 193 194 <ParamChoice id="rxsignExtended" name="Word Extension" group="RX" default="CY_ZERO_EXTEND" visible="`${rxEnabled}`" editable="true" desc="Set Word Extension mode: ZERO EXTEND, SIGN EXTEND"> 195 <Entry name="ZERO EXTEND" value="CY_ZERO_EXTEND" visible="true" /> 196 <Entry name="SIGN EXTEND" value="CY_SIGN_EXTEND" visible="true" /> 197 </ParamChoice> 198 199 <ParamChoice id="rxlateSample" name="Sample On" group="RX" default="false" visible="`${rxEnabled}`" editable="true" desc="Sample PCM bit value on rising edge or falling edge of receiver."> 200 <Entry name="Sample on Rising Edge" value="false" visible="true" /> 201 <Entry name="Sample on Falling Edge" value="true" visible="true" /> 202 </ParamChoice> 203 204 <ParamChoice id="rxsyncFormatPolarity" name="Sync Format Polarity" group="RX" default="CY_TDM_SIGN" visible="`${rxEnabled}`" editable="true" desc="Channel synchronization polarity"> 205 <Entry name="Normal" value="CY_TDM_SIGN" visible="true" /> 206 <Entry name="Inverted" value="CY_TDM_SIGN_INVERTED" visible="true" /> 207 </ParamChoice> 208 <ParamChoice id="rxSckoPolarity" name="Output Serial Clock Polarity" group="RX" default="CY_TDM_CLK" visible="`${rxEnabled}`" editable="true" desc="Polarity of the output SCK signal (available only in master mode)"> 209 <Entry name="Normal" value="CY_TDM_CLK" visible="true" /> 210 <Entry name="Inverted" value="CY_TDM_CLK_INVERTED" visible="true" /> 211 </ParamChoice> 212 <ParamRange id="rxFifoTriggerLevel" name="FIFO Trigger Level" group="RX" default="0" min="0" max="`${255 - rxChannels}`" resolution="1" visible="`${rxEnabled}`" editable="true" desc="Set FIFO level to trigger an event (interrupt or DMA request). Should not be greater than [255 - (number of channels)]." /> 213 <ParamBool id="rxDmaTrigger" name="DMA Trigger" group="RX" default="false" visible="`${rxEnabled}`" editable="true" desc="Enables DMA trigger" /> 214 215 <!-- Connections --> 216 217 <ParamSignal port="tdm_tx_sck[0]" name="Tx Serial Clock" group="`${(txMode eq CY_TDM_DEVICE_MASTER) ? "Outputs" : "Inputs"}`" visible="`${txEnabled}`" desc="Tx serial clock (visible when Tx is enabled)." canBeEmpty="`${(txMode eq CY_TDM_DEVICE_MASTER) || !txEnabled}`" > 218 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 219 <Parameter id="DriveModes" severity="ERROR" reason=""> 220 <Fixed value="`${(txMode eq CY_TDM_DEVICE_MASTER) ? "CY_GPIO_DM_STRONG_IN_OFF" : "CY_GPIO_DM_HIGHZ"}`" /> 221 </Parameter> 222 </Constraint> 223 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 224 </ParamSignal> 225 <ParamSignal port="tdm_tx_fsync[0]" name="Tx Word Select" group="`${(txMode eq CY_TDM_DEVICE_MASTER) ? "Outputs" : "Inputs"}`" visible="`${txEnabled}`" desc="Tx word select (visible when Tx is enabled)." canBeEmpty="`${(txMode eq CY_TDM_DEVICE_MASTER) || !txEnabled}`" > 226 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 227 <Parameter id="DriveModes" severity="ERROR" reason=""> 228 <Fixed value="`${(txMode eq CY_TDM_DEVICE_MASTER) ? "CY_GPIO_DM_STRONG_IN_OFF" : "CY_GPIO_DM_HIGHZ"}`" /> 229 </Parameter> 230 </Constraint> 231 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 232 </ParamSignal> 233 <ParamSignal port="tdm_tx_sd[0]" name="Tx Serial Data" group="Outputs" visible="`${txEnabled}`" desc="Tx serial data output (visible when Tx is enabled)." canBeEmpty="true" > 234 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 235 <Parameter id="DriveModes" severity="ERROR" reason=""> 236 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 237 </Parameter> 238 </Constraint> 239 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 240 </ParamSignal> 241 <ParamSignal port="tdm_rx_sck[0]" name="Rx Serial Clock" group="`${(rxMode eq CY_TDM_DEVICE_MASTER) ? "Outputs" : "Inputs"}`" visible="`${rxEnabled}`" desc="Rx serial clock (visible when Rx is enabled)." canBeEmpty="`${(rxMode eq CY_TDM_DEVICE_MASTER) || !rxEnabled}`" > 242 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 243 <Parameter id="DriveModes" severity="ERROR" reason=""> 244 <Fixed value="`${(rxMode eq CY_TDM_DEVICE_MASTER) ? "CY_GPIO_DM_STRONG_IN_OFF" : "CY_GPIO_DM_HIGHZ"}`" /> 245 </Parameter> 246 </Constraint> 247 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 248 </ParamSignal> 249 <ParamSignal port="tdm_rx_fsync[0]" name="Rx Word Select" group="`${(rxMode eq CY_TDM_DEVICE_MASTER) ? "Outputs" : "Inputs"}`" visible="`${rxEnabled}`" desc="Rx word select (visible when Rx is enabled)." canBeEmpty="`${(rxMode eq CY_TDM_DEVICE_MASTER) || !rxEnabled}`" > 250 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 251 <Parameter id="DriveModes" severity="ERROR" reason=""> 252 <Fixed value="`${(rxMode eq CY_TDM_DEVICE_MASTER) ? "CY_GPIO_DM_STRONG_IN_OFF" : "CY_GPIO_DM_HIGHZ"}`" /> 253 </Parameter> 254 </Constraint> 255 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 256 </ParamSignal> 257 <ParamSignal port="tdm_rx_sd[0]" name="Rx Serial Data" group="Inputs" visible="`${rxEnabled}`" desc="Rx serial data input (visible when Rx is enabled)." canBeEmpty="`${!rxEnabled}`" > 258 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 259 <Parameter id="DriveModes" severity="ERROR" reason=""> 260 <Fixed value="CY_GPIO_DM_HIGHZ" /> 261 </Parameter> 262 </Constraint> 263 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 264 </ParamSignal> 265 <ParamSignal port="tr_tx_req[0]" name="Tx DMA Transfer Request Signal" group="Outputs" visible="`${txDmaTrigger && txEnabled}`" desc="Tx DMA transfer request signal (Available when Tx DMA trigger is enabled)." canBeEmpty="true" > 266 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 267 <Parameter id="DriveModes" severity="ERROR" reason=""> 268 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 269 </Parameter> 270 </Constraint> 271 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 272 </ParamSignal> 273 <ParamSignal port="tr_rx_req[0]" name="Rx DMA Transfer Request Signal" group="Outputs" visible="`${rxDmaTrigger && rxEnabled}`" desc="Rx DMA transfer request signal (Available when Rx DMA trigger is enabled)." canBeEmpty="true" > 274 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 275 <Parameter id="DriveModes" severity="ERROR" reason=""> 276 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 277 </Parameter> 278 </Constraint> 279 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 280 </ParamSignal> 281 282 <ParamSignal port="clk_if_srss[0]" name="Interface Clock" group="Inputs" visible="true" desc="Clock Input signal for TDM interface." canBeEmpty="false" > 283 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 284 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 285 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 286 </Parameter> 287 </Constraint> 288 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 289 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 290 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 291 </Parameter> 292 </Constraint> 293 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 294 </ParamSignal> 295 296 <ParamString id="sourceClock" name="sourceClock" group="Internal" default="`${getBlockFromSignal("clk_if_srss[0]")}`" visible="false" editable="false" desc="Source Clock Resource" /> 297 298 <ParamBool id="inFlash" name="Store Config in Flash" group="Advanced" default="true" visible="true" editable="true" desc="Controls whether the configuration structure is stored in flash (const, true) or SRAM (not const, false)." /> 299 300 <!-- TDM instance number --> 301 <ParamString id="InstNumber" name="Instance Number" group="Internal" default="`${getInstNumber("tdm")}`" visible="false" editable="false" desc="TDM Instance number." /> 302 <ParamBool id="hasTDM1" name="hasTDM1" group="Internal" default="`${hasBlock("tdm[1]")}`" visible="false" editable="false" desc="Check whether device has more than one TDM instance" /> 303 304 <!-- Peripheral clock divider connection --> 305 <ParamBool id="pclkOk" name="PCLK Valid" group="Internal" default="`${hasConnection("clk_if_srss", 0) && isBlockUsed(sourceClock)}`" visible="false" editable="false" desc="Checks whether there is a PCLK connected and enabled." /> 306 <ParamBool id="blockUsesPeriClock" name="PERI clock used" group="Internal" default="`${!hasMatch(sourceClock, ".*hfclk.*")}`" visible="false" editable="false" desc="Checks whether block uses a PERI derived clock." /> 307 <ParamString id="pclkDst" name="PCLK Destination" group="Internal" default="PCLK_TDM`${InstNumber}`_CLK_IF_SRSS0" visible="false" editable="false" desc="Generates PCLK connection define." /> 308 309 </Parameters> 310 311 <DRCs> 312 <!-- RX direction --> 313 <DRC type="ERROR" text="RX Word Length value must be less than or equal RX Channel Length." condition="`${rxEnabled && rxWordLength > rxChannelLength}`" /> 314 <DRC type="ERROR" text="I2S mode, No of Channels should not exceed 2." condition="`${rxInterfaceMode && rxChannels > 2}`" /> 315 316 <!-- TX direction --> 317 <DRC type="ERROR" text="TX Word Length value must be less than or equal TX Channel Length." condition="`${txEnabled && txWordLength > txChannelLength}`" /> 318 <DRC type="ERROR" text="I2S mode, No of Channels should not exceed 2." condition="`${txInterfaceMode && txChannels > 2}`" /> 319 320 </DRCs> 321 322 <ConfigFirmware> 323 <ConfigInclude value="cy_tdm.h" include="true" /> 324 <ConfigInclude value="cy_sysclk.h" include="`${pclkOk}`" /> 325 <ConfigInclude value="cyhal.h" include="true" guard="defined (CY_USING_HAL)" /> 326 327 <ConfigDefine name="`${INST_NAME}`_HW" value="TDM`${InstNumber}`" public="true" include="true" /> 328 <ConfigDefine name="`${INST_NAME}`_TX_HW" value="TDM_STRUCT`${InstNumber}`_TX" public="true" include="true" /> 329 <ConfigDefine name="`${INST_NAME}`_RX_HW" value="TDM_STRUCT`${InstNumber}`_RX" public="true" include="true" /> 330 <ConfigDefine name="`${INST_NAME}`_TX_IRQ" value="tdm_`${InstNumber}`_interrupts_tx_`${InstNumber}`_IRQn" public="true" include="true" /> 331 <ConfigDefine name="`${INST_NAME}`_RX_IRQ" value="tdm_`${InstNumber}`_interrupts_rx_`${InstNumber}`_IRQn" public="true" include="true" /> 332 333 <ConfigStruct name="`${INST_NAME . "_tx_config"}`" type="cy_stc_tdm_config_tx_t" const="false" public="true" include="true" > 334 <Member name="enable" value="`${txEnabled}`" /> 335 <Member name="masterMode" value="`${txMode}`" /> 336 <Member name="wordSize" value="CY_TDM_SIZE_`${txWordLength}`" /> 337 <Member name="format" value="`${txAlignment}`" /> 338 <Member name="clkDiv" value="`${txclockDiv}`" /> 339 <Member name="clkSel" value="`${txclockselect}`" /> 340 <Member name="sckPolarity" value="`${txSckoPolarity}`" /> 341 <Member name="fsyncPolarity" value="`${txsyncFormatPolarity}`" /> 342 <Member name="fsyncFormat" value="`${txsyncformat}`" /> 343 <Member name="channelNum" value="`${txChannels}`" /> 344 <Member name="channelSize" value="`${txChannelLength}`" /> 345 <Member name="fifoTriggerLevel" value="`${txFifoTriggerLevel}`" /> 346 <Member name="chEn" value="`${txChannelsEnabled}`" /> 347 <Member name="signalInput" value="`${txsignalInput}`" /> 348 <Member name="i2sMode" value="`${txInterfaceMode}`" /> 349 350 351 </ConfigStruct> 352 353 <ConfigStruct name="`${INST_NAME . "_rx_config"}`" type="cy_stc_tdm_config_rx_t" const="false" public="true" include="true" > 354 <Member name="enable" value="`${rxEnabled}`" /> 355 <Member name="masterMode" value="`${rxMode}`" /> 356 <Member name="wordSize" value="CY_TDM_SIZE_`${rxWordLength}`" /> 357 <Member name="signExtend" value="`${rxsignExtended}`" /> 358 <Member name="format" value="`${rxAlignment}`" /> 359 <Member name="clkDiv" value="`${rxclockDiv}`" /> 360 <Member name="clkSel" value="`${rxclockselect}`" /> 361 <Member name="sckPolarity" value="`${rxSckoPolarity}`" /> 362 <Member name="fsyncPolarity" value="`${rxsyncFormatPolarity}`" /> 363 <Member name="lateSample" value="`${rxlateSample}`" /> 364 <Member name="fsyncFormat" value="`${rxsyncformat}`" /> 365 <Member name="channelNum" value="`${rxChannels}`" /> 366 <Member name="channelSize" value="`${rxChannelLength}`" /> 367 <Member name="fifoTriggerLevel" value="`${rxFifoTriggerLevel}`" /> 368 <Member name="chEn" value="`${rxChannelsEnabled}`" /> 369 <Member name="signalInput" value="`${rxsignalInput}`" /> 370 <Member name="i2sMode" value="`${rxInterfaceMode}`" /> 371 372 </ConfigStruct> 373 374 <ConfigStruct name="`${INST_NAME}`_config" type="cy_stc_tdm_config_t" const="true" public="true" include="true" > 375 <Member name="tx_config" value="&`${INST_NAME . "_tx_config"}`" /> 376 <Member name="rx_config" value="&`${INST_NAME . "_rx_config"}`" /> 377 </ConfigStruct> 378 379 <ConfigStruct name="`${INST_NAME}`_obj" type="cyhal_resource_inst_t" const="true" public="true" include="true" guard="defined (CY_USING_HAL)"> 380 <Member name="type" value="CYHAL_RSC_TDM" /> 381 <Member name="block_num" value="`${InstNumber}`U" /> 382 <Member name="channel_num" value="0U" /> 383 </ConfigStruct> 384 385 <ConfigStruct name="`${INST_NAME}`_clock" type="cyhal_clock_t" const="`${inFlash}`" public="true" include="true" guard="defined (CY_USING_HAL)"> 386 <Member name="block" value="`${getExposedMember(sourceClock, "hal_block")}`" /> 387 <Member name="channel" value="`${getExposedMember(sourceClock, "number")}`" /> 388 <Member name="reserved" value="false" /> 389 <Member name="funcs" value="NULL" /> 390 </ConfigStruct> 391 392 <ConfigStruct name="`${INST_NAME}`_hal_config" type="cyhal_tdm_configurator_t" const="`${inFlash}`" public="true" include="true" guard="defined (CY_USING_HAL)"> 393 <Member name="resource" value="&`${INST_NAME}`_obj" /> 394 <Member name="config" value="&`${INST_NAME}`_config" /> 395 <Member name="clock" value="&`${INST_NAME}`_clock" /> 396 <Member name="mclk_hz_rx" value="0u" /> 397 <Member name="mclk_hz_tx" value="0u" /> 398 </ConfigStruct> 399 400 <ConfigInstruction purpose="INITIALIZE" value="Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TDM`${InstNumber}`_PERI_NR, CY_MMIO_TDM`${InstNumber}`_GROUP_NR, CY_MMIO_TDM`${InstNumber}`_SLAVE_NR, CY_MMIO_TDM`${InstNumber}`_CLK_HF_NR);" include="true" guard="defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE)" /> 401 <ConfigInstruction purpose="INITIALIZE" value="Cy_SysClk_PeriPclkAssignDivider(`${pclkDst}`, `${getExposedMember(sourceClock, "clockSel")}`);" include="`${blockUsesPeriClock}`" /> 402 403 </ConfigFirmware> 404 405</Personality> 406
