1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file lin.cypersonality 6* \version 1.1 7* 8* \brief 9* LIN personality description file. It Supports CAT1B family of devices. 10* 11******************************************************************************** 12* \copyright 13* Copyright (c) (2022), Cypress Semiconductor Corporation (an Infineon company) or 14* an affiliate of Cypress Semiconductor Corporation. 15* SPDX-License-Identifier: Apache-2.0 16* 17* Licensed under the Apache License, Version 2.0 (the "License"); 18* you may not use this file except in compliance with the License. 19* You may obtain a copy of the License at 20* 21* http://www.apache.org/licenses/LICENSE-2.0 22* 23* Unless required by applicable law or agreed to in writing, software 24* distributed under the License is distributed on an "AS IS" BASIS, 25* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26* See the License for the specific language governing permissions and 27* limitations under the License. 28*****************************************************************************--> 29 30<Personality id="lin" name="Local Interconnect Network (LIN)" version="1.1" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 31 <Dependencies> 32 <IpBlock name="mxlin" /> 33 <Resource name="lin" /> 34 </Dependencies> 35 <ExposedMembers /> 36 <Parameters> 37 <!-- PDL documentation --> 38 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__lin.html" linkText="Open LIN Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 39 40 <!-- Nodes --> 41 <ParamChoice id="Nodes" name="Nodes Enabled" group="No Of Nodes" default="1" visible="true" editable="true" desc="Set No of Nodes enabled (Total 2 nodes available). Both the nodes can be connected to an external master or one node can be made master and other as slave."> 42 <Entry name="1" value="1" visible="true" /> 43 <Entry name="2" value="2" visible="true" /> 44 </ParamChoice> 45 46 <!--Channel 1--> 47 <ParamBool id="MasterMode0" name="Master Mode" group="Node1" default="true" visible="true" editable="true" desc="If TRUE, corresponding channel = master mode, If FALSE, slave mode." /> 48 49 <ParamBool id="TransceiverAutoEnable0" name="Transceiver Auto Enable" group="Node1" default="true" visible="true" editable="true" desc="If TRUE, corresponding LIN channel transceiver is enabled automatically, If FALSE, firmware has to handle the transceiver enable signal manually." /> 50 51 <ParamRange id="breakFieldLength0" name="Break Field Length" group="Node1" default="13" min="0" max="31" resolution="1" visible="true" editable="true" desc="This field is used for transmission/reception of BOTH break and wakeup length (minus 1) in bit periods. Recommend 11 bit periods (break length for slave nodes), 13 bit periods (break length for master nodes)" /> 52 53 <ParamChoice id="breakDelimiterLength0" name="Break Delimiter Length" group="Node1" default="LIN_BREAK_DILIMITER_LENGTH_1BITS" visible="true" editable="true" desc="Break delimiter length. This field specifies the break delimiter length:(used in header transmission, not used in header reception). "> 54 <Entry name="1 Bit" value="LIN_BREAK_DILIMITER_LENGTH_1BITS" visible="true" /> 55 <Entry name="2 Bit" value="LIN_BREAK_DILIMITER_LENGTH_2BITS" visible="true" /> 56 <Entry name="3 Bit" value="LIN_BREAK_DILIMITER_LENGTH_3BITS" visible="true" /> 57 <Entry name="4 Bit" value="LIN_BREAK_DILIMITER_LENGTH_4BITS" visible="true" /> 58 </ParamChoice> 59 60 <ParamChoice id="stopBit0" name="Stop Bit" group="Node1" default="LIN_ONE_STOP_BIT" visible="true" editable="true" desc="Stop Bit periods. "> 61 <Entry name="1" value="LIN_ONE_STOP_BIT" visible="true" /> 62 <Entry name="2" value="LIN_TWO_STOP_BIT" visible="true" /> 63 </ParamChoice> 64 65 <ParamBool id="FilterEnable0" name="Filter Enable" group="Node1" default="true" visible="true" editable="true" desc="If enabled, lin rx filter operates. The sequences '000', '001', '010' and '100' result in a filtered value '0'. The sequences '111', '110', '101' and '011' result in a filtered value '1'." /> 66 67 <!--Channel 2--> 68 <ParamBool id="MasterMode1" name="Master Mode" group="Node2" default="true" visible="`${Nodes eq 2}`" editable="true" desc="If TRUE, corresponding channel = master mode, If FALSE, slave mode." /> 69 70 <ParamBool id="TransceiverAutoEnable1" name="Transceiver Auto Enable" group="Node2" default="true" visible="`${Nodes eq 2}`" editable="true" desc="If TRUE, corresponding LIN channel transceiver is enabled automatically, If FALSE, firmware has to handle the transceiver enable signal manually." /> 71 72 <ParamRange id="breakFieldLength1" name="Break Field Length" group="Node2" default="13" min="0" max="31" resolution="1" visible="`${Nodes eq 2}`" editable="true" desc="This field is used for transmission/reception of BOTH break and wakeup length (minus 1) in bit periods. Recommend 11 bit periods (break length for slave nodes), 13 bit periods (break length for master nodes)" /> 73 74 <ParamChoice id="breakDelimiterLength1" name="Break Delimiter Length" group="Node2" default="LIN_BREAK_DILIMITER_LENGTH_1BITS" visible="`${Nodes eq 2}`" editable="true" desc="Break delimiter length. This field specifies the break delimiter length:(used in header transmission, not used in header reception). "> 75 <Entry name="1 Bit" value="LIN_BREAK_DILIMITER_LENGTH_1BITS" visible="true" /> 76 <Entry name="2 Bit" value="LIN_BREAK_DILIMITER_LENGTH_2BITS" visible="true" /> 77 <Entry name="3 Bit" value="LIN_BREAK_DILIMITER_LENGTH_3BITS" visible="true" /> 78 <Entry name="4 Bit" value="LIN_BREAK_DILIMITER_LENGTH_4BITS" visible="true" /> 79 </ParamChoice> 80 81 <ParamChoice id="stopBit1" name="Stop Bit" group="Node2" default="LIN_ONE_STOP_BIT" visible="`${Nodes eq 2}`" editable="true" desc="Stop Bit periods. "> 82 <Entry name="1" value="LIN_ONE_STOP_BIT" visible="true" /> 83 <Entry name="2" value="LIN_TWO_STOP_BIT" visible="true" /> 84 </ParamChoice> 85 86 <ParamBool id="FilterEnable1" name="Filter Enable" group="Node2" default="true" visible="`${Nodes eq 2}`" editable="true" desc="If enabled, lin rx filter operates. The sequences '000', '001', '010' and '100' result in a filtered value '0'. The sequences '111', '110', '101' and '011' result in a filtered value '1'." /> 87 88 89 <!-- Connections --> 90 <ParamSignal port="lin_en[0]" name="LIN EN0" group="Outputs" visible="true" desc="LIN output signal to signal the transceiver." canBeEmpty="true" > 91 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 92 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 93 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 94 </Parameter> 95 </Constraint> 96 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 97 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 98 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 99 </Parameter> 100 </Constraint> 101 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 102 </ParamSignal> 103 <ParamSignal port="lin_rx[0]" name="LIN RX0" group="Inputs" visible="true" desc="LIN input signal Can be connected to digital input pin." canBeEmpty="true" > 104 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 105 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 106 <Fixed value="CY_GPIO_DM_HIGHZ" /> 107 </Parameter> 108 </Constraint> 109 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 110 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 111 <Fixed value="CY_GPIO_DM_HIGHZ" /> 112 </Parameter> 113 </Constraint> 114 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 115 </ParamSignal> 116 <ParamSignal port="lin_tx[0]" name="LIN TX0" group="Outputs" visible="true" desc="Output signal for LIN. Can be connected to digital output pin." canBeEmpty="true" > 117 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 118 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 119 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 120 </Parameter> 121 </Constraint> 122 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 123 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 124 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 125 </Parameter> 126 </Constraint> 127 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 128 </ParamSignal> 129 130 <ParamSignal port="lin_rx[1]" name="LIN RX1" group="Inputs" visible="`${Nodes eq 2}`" desc="LIN input signal Can be connected to digital input pin." canBeEmpty="true" > 131 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 132 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 133 <Fixed value="CY_GPIO_DM_HIGHZ" /> 134 </Parameter> 135 </Constraint> 136 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 137 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 138 <Fixed value="CY_GPIO_DM_HIGHZ" /> 139 </Parameter> 140 </Constraint> 141 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 142 </ParamSignal> 143 <ParamSignal port="lin_tx[1]" name="LIN TX1" group="Outputs" visible="`${Nodes eq 2}`" desc="Output signal for LIN. Can be connected to digital output pin." canBeEmpty="true" > 144 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 145 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 146 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 147 </Parameter> 148 </Constraint> 149 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 150 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 151 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 152 </Parameter> 153 </Constraint> 154 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 155 </ParamSignal> 156 <ParamSignal port="lin_en[1]" name="LIN EN1" group="Outputs" visible="`${Nodes eq 2}`" desc="LIN output signal to signal the transceiver." canBeEmpty="true" > 157 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 158 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 159 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 160 </Parameter> 161 </Constraint> 162 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 163 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 164 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 165 </Parameter> 166 </Constraint> 167 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 168 </ParamSignal> 169 <ParamSignal port="clock_ch_en[0]" name="Interface Clock Ch0" group="Inputs" visible="true" desc="Clock input signal for LIN Channel0." canBeEmpty="false" > 170 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 171 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 172 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 173 </Parameter> 174 </Constraint> 175 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 176 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 177 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 178 </Parameter> 179 </Constraint> 180 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 181 </ParamSignal> 182 183 <ParamSignal port="clock_ch_en[1]" name="Interface Clock Ch1" group="Inputs" visible="`${Nodes eq 2}`" desc="lock input signal for LIN Channel1." canBeEmpty="true" > 184 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 185 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 186 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 187 </Parameter> 188 </Constraint> 189 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 190 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 191 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 192 </Parameter> 193 </Constraint> 194 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 195 </ParamSignal> 196 197 <ParamBool id="inFlash" name="Store Config in Flash" group="Advanced" default="true" visible="true" editable="true" desc="Controls whether the configuration structure is stored in flash (const, true) or SRAM (not const, false)." /> 198 199 <ParamString id="InstNumber" name="Instance Number" group="Internal" default="`${getInstNumber("lin")}`" visible="false" editable="false" desc="LIN Instance number." /> 200 201 <ParamString id="sourceClock0" name="sourceClock0" group="Internal" default="`${getBlockFromSignal("clock_ch_en[0]")}`" visible="false" editable="false" desc="Source Clock Resource" /> 202 203 <ParamString id="sourceClock1" name="sourceClock1" group="Internal" default="`${getBlockFromSignal("clock_ch_en[1]")}`" visible="false" editable="false" desc="Source Clock Resource" /> 204 205 <ParamBool id="pclkOk0" name="PCLK Valid" group="Internal" default="`${hasConnection("clock_ch_en", 0) && isBlockUsed(sourceClock0)}`" visible="false" editable="false" desc="Checks whether there is a PCLK connected and enabled." /> 206 <ParamBool id="pclkOk1" name="PCLK Valid" group="Internal" default="`${hasConnection("clock_ch_en", 1) && isBlockUsed(sourceClock0)}`" visible="false" editable="false" desc="Checks whether there is a PCLK connected and enabled." /> 207 <ParamString id="pclkDst" name="PCLK Destination" group="Internal" default="PCLK_LIN`${InstNumber}`_CLOCK_CH_EN0" visible="false" editable="false" desc="Generates PCLK connection define." /> 208 <ParamString id="pclkDst1" name="PCLK Destination" group="Internal" default="PCLK_LIN`${InstNumber}`_CLOCK_CH_EN1" visible="false" editable="false" desc="Generates PCLK connection define." /> 209 210 </Parameters> 211 <!-- DRC --> 212 <DRCs> 213 <DRC type="ERROR" text="LIN TX has to be connected for each node." condition="`${!hasConnection("lin_tx", 0)}`" /> 214 <DRC type="ERROR" text="LIN RX has to be connected for each node." condition="`${!hasConnection("lin_rx", 0)}`" /> 215 <DRC type="ERROR" text="LIN TX has to be connected for each node." condition="`${(Nodes eq 2) && !hasConnection("lin_tx", 1)}`" /> 216 <DRC type="ERROR" text="LIN RX has to be connected for each node." condition="`${(Nodes eq 2) && !hasConnection("lin_rx", 1)}`" /> 217 </DRCs> 218 219 220 <ConfigFirmware> 221 <ConfigInclude value="cy_lin.h" include="true" /> 222 <ConfigInclude value="cy_sysclk.h" include="true" /> 223 224 <ConfigDefine name="`${INST_NAME}`_HW" value="LIN`${InstNumber}`" public="true" include="true" /> 225 <ConfigDefine name="`${INST_NAME}`_CHANNEL0" value="LIN`${InstNumber}`_CH0" public="true" include="true" /> 226 <ConfigDefine name="`${INST_NAME}`_CHANNEL1" value="LIN`${InstNumber}`_CH1" public="true" include="`${Nodes eq 2}`" /> 227 <ConfigDefine name="`${INST_NAME}`_IRQ_0" value="lin_`${InstNumber}`_interrupts_0_IRQn" public="true" include="true" /> 228 <ConfigDefine name="`${INST_NAME}`_IRQ_1" value="lin_`${InstNumber}`_interrupts_1_IRQn" public="true" include="`${Nodes eq 2}`" /> 229 <ConfigStruct name="`${INST_NAME}`_ch0_config" type="cy_stc_lin_config_t" const="`${inFlash}`" public="true" include="true" > 230 <Member name="masterMode" value="`${MasterMode0}`" /> 231 <Member name="linTransceiverAutoEnable" value="`${TransceiverAutoEnable0}`" /> 232 <Member name="breakFieldLength" value="`${breakFieldLength0}`" /> 233 <Member name="breakDelimiterLength" value="`${breakDelimiterLength0}`" /> 234 <Member name="stopBit" value="`${stopBit0}`" /> 235 <Member name="filterEnable" value="`${FilterEnable0}`" /> 236 </ConfigStruct> 237 238 <ConfigStruct name="`${INST_NAME}`_ch1_config" type="cy_stc_lin_config_t" const="`${inFlash}`" public="true" include="`${Nodes eq 2}`" > 239 <Member name="masterMode" value="`${MasterMode1}`" /> 240 <Member name="linTransceiverAutoEnable" value="`${TransceiverAutoEnable1}`" /> 241 <Member name="breakFieldLength" value="`${breakFieldLength1}`" /> 242 <Member name="breakDelimiterLength" value="`${breakDelimiterLength1}`" /> 243 <Member name="stopBit" value="`${stopBit1}`" /> 244 <Member name="filterEnable" value="`${FilterEnable1}`" /> 245 </ConfigStruct> 246 <ConfigInstruction value="Cy_SysClk_PeriPclkAssignDivider(`${pclkDst}`, `${getExposedMember(sourceClock0, "clockSel")}`);" include="true" /> 247 <ConfigInstruction value="Cy_SysClk_PeriPclkAssignDivider(`${pclkDst1}`, `${getExposedMember(sourceClock1, "clockSel")}`);" include="`${Nodes eq 2}`" /> 248 249 </ConfigFirmware> 250</Personality> 251
