1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file i2s.cypersonality 6* \version 2.0 7* 8* \brief 9* I2S personality description file. Supports CAT1A and CAT1C family of devices. 10* 11******************************************************************************** 12* \copyright 13* Copyright (c) (2022), Cypress Semiconductor Corporation (an Infineon company) or 14* an affiliate of Cypress Semiconductor Corporation. 15* SPDX-License-Identifier: Apache-2.0 16* 17* Licensed under the Apache License, Version 2.0 (the "License"); 18* you may not use this file except in compliance with the License. 19* You may obtain a copy of the License at 20* 21* http://www.apache.org/licenses/LICENSE-2.0 22* 23* Unless required by applicable law or agreed to in writing, software 24* distributed under the License is distributed on an "AS IS" BASIS, 25* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26* See the License for the specific language governing permissions and 27* limitations under the License. 28*****************************************************************************--> 29 30<Personality id="mxaudioss_i2s" name="I2S" version="2.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 31 <Dependencies> 32 <IpBlock name="mxaudioss_ver2_s40e,mxaudioss" /> 33 <Resource name="audioss\.i2s" /> 34 </Dependencies> 35 <ExposedMembers /> 36 <Parameters> 37 <!-- PDL documentation --> 38 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__i2s.html" linkText="Open I2S Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 39 <ParamString id="version" name="version number" group="Internal" default="`${getVersion()}`" visible="false" editable="false" desc="" /> 40 41 <!-- Timing --> 42 <ParamSignal port="clock[0]" name="Clock" group="Timing" visible="true" desc="Input clock source" canBeEmpty="false" /> 43 <ParamString id="sourceClock" name="sourceClock" group="General" default="`${getBlockFromSignal("clock[0]")}`" visible="false" editable="false" desc="" /> 44 <ParamRange id="sourceFreq" name="sourceFreq" group="General" default="`${isBlockUsed(sourceClock) ? getExposedMember(sourceClock, "frequency") : 0}`" min="0" max="400000000" resolution="1" visible="false" editable="false" desc="" /> 45 46 <ParamSignal port="clk_i2s_if[0]" name="External Interface Clock" group="Timing" visible="true" desc="External interface clock - if unassigned then the CLK_HF1 clock is used." canBeEmpty="true" > 47 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 48 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 49 <Fixed value="CY_GPIO_DM_HIGHZ" /> 50 </Parameter> 51 </Constraint> 52 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 53 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 54 <Fixed value="CY_GPIO_DM_HIGHZ" /> 55 </Parameter> 56 </Constraint> 57 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 58 </ParamSignal> 59 60 <ParamBool id="extClk" name="Clock From Terminal" group="Timing" default="`${hasConnection("clk_i2s_if", 0)}`" visible="false" editable="false" desc="Selects input clock source: external interface clock (from the clk_if terminal) or internal clock (CLK_HF1)" /> 61 62 <ParamBool id="mClk" name="Master Clock" group="Timing" default="`${hasConnection("clk_i2s_if", 0)}`" visible="`${(version > 1)}`" editable="true" desc="Enables Master clock : Enables MCLK divider operation. If disabled allows MCLK divider to reach all 0's state. " /> 63 64 <ParamRange id="i2sClk" name="Input Clock Frequency (kHz)" group="Timing" default="`${sourceFreq / 1000}`" min="0" max="400000000" resolution="0.001" visible="true" editable="`${extClk}`" desc="Shows the actual input clock frequency in case of internal I2S clock using (Clock From Terminal is unassigned), and is editable in case of using the external I2S interface clock from terminal - the expected external clock frequency should be entered in kHz." /> 65 66 <ParamRange id="clockDiv" name="Clock Divider" group="Timing" default="16" min="1" max="64" resolution="1" visible="true" editable="true" desc="Sets the input Clock Divider" /> 67 <ParamRange id="bitRate" name="Bit Rate (kbps)" group="Timing" default="`${i2sClk / clockDiv / 8}`" min="0" max="10000000" resolution="0.001" visible="true" editable="false" desc="Shows the actual bit rate" /> 68 69 <ParamChoice id="mclockDiv" name="Master Clock Divider" group="Timing" default="CY_I2S_MCLK_DIV_8" visible="`${(mClk) && (version > 1)}`" editable="true" desc="Selects clock divider for Master clock out." > 70 <Entry name="Divide by 1(Bypass)" value="CY_I2S_MCLK_DIV_1" visible="true" /> 71 <Entry name="Divide by 2" value="CY_I2S_MCLK_DIV_2" visible="true" /> 72 <Entry name="Divide by 4" value="CY_I2S_MCLK_DIV_4" visible="true" /> 73 <Entry name="Divide by 8" value="CY_I2S_MCLK_DIV_8" visible="true" /> 74 </ParamChoice> 75 76 <!-- TX --> 77 <ParamBool id="txEnabled" name="Enable" group="TX" default="true" visible="true" editable="true" desc="Enables the transmitter" /> 78 <ParamChoice id="txMode" name="Mode" group="TX" default="1" visible="`${txEnabled}`" editable="true" desc="Sets mode to master or slave"> 79 <Entry name="Slave" value="0" visible="true" /> 80 <Entry name="Master" value="1" visible="true" /> 81 </ParamChoice> 82 <ParamChoice id="txAlignment" name="Alignment" group="TX" default="CY_I2S_I2S_MODE" visible="`${txEnabled}`" editable="true" desc="Set interface transfer mode: I2S, Left Justified, TDM mode A, or TDM mode B"> 83 <Entry name="Left Justified" value="CY_I2S_LEFT_JUSTIFIED" visible="true" /> 84 <Entry name="I2S mode" value="CY_I2S_I2S_MODE" visible="true" /> 85 <Entry name="TDM mode A" value="CY_I2S_TDM_MODE_A" visible="true" /> 86 <Entry name="TDM mode B" value="CY_I2S_TDM_MODE_B" visible="true" /> 87 </ParamChoice> 88 <ParamRange id="txChannels" name="Channels" group="TX" default="2" min="1" max="8" resolution="1" visible="`${txEnabled}`" editable="true" desc="Number of channels per frame (2 is the only valid value for Left Justified and I2S modes)" /> 89 <ParamChoice id="txChannelLength" name="Channel Length" group="TX" default="16" visible="`${txEnabled}`" editable="true" desc="Set channel length in bits (32 bit is the only valid value for TDM modes)"> 90 <Entry name="8" value="8" visible="true" /> 91 <Entry name="16" value="16" visible="true" /> 92 <Entry name="18" value="18" visible="true" /> 93 <Entry name="20" value="20" visible="true" /> 94 <Entry name="24" value="24" visible="true" /> 95 <Entry name="32" value="32" visible="true" /> 96 </ParamChoice> 97 <ParamChoice id="txWordLength" name="Word Length" group="TX" default="16" visible="`${txEnabled}`" editable="true" desc="Set word length (in bits)"> 98 <Entry name="8" value="8" visible="true" /> 99 <Entry name="16" value="16" visible="true" /> 100 <Entry name="18" value="18" visible="true" /> 101 <Entry name="20" value="20" visible="true" /> 102 <Entry name="24" value="24" visible="true" /> 103 <Entry name="32" value="32" visible="true" /> 104 </ParamChoice> 105 106 <ParamRange id="txFrameRate" name="Frame Rate (ksps)" group="TX" default="`${((txAlignment eq CY_I2S_TDM_MODE_A) || (txAlignment eq CY_I2S_TDM_MODE_B)) ? (bitRate / 256) : (bitRate / txChannelLength / 2)}`" min="0" max="10000000" resolution="0.001" visible="`${txEnabled}`" editable="false" desc="Shows the actual frame rate" /> 107 108 <ParamChoice id="txOverheadValue" name="Overhead Value" group="TX" default="CY_I2S_OVHDATA_ZERO" visible="`${txEnabled}`" editable="true" desc="Set the overhead bits level (available only when word length is less than channel length). It fills all the channel LSBs (after the data LSB) on SDO wire by 1 or 0"> 109 <Entry name="0" value="CY_I2S_OVHDATA_ZERO" visible="true" /> 110 <Entry name="1" value="CY_I2S_OVHDATA_ONE" visible="true" /> 111 </ParamChoice> 112 <ParamChoice id="txWsPulseWidth" name="WS Pulse Width" group="TX" default="CY_I2S_WS_ONE_CHANNEL_LENGTH" visible="`${txEnabled}`" editable="true" desc="Pulse width of the WS signal: one SCK period or one channel length. The one channel length is the only valid value for I2S and Left Justified modes"> 113 <Entry name="1 SCK period" value="CY_I2S_WS_ONE_SCK_CYCLE" visible="true" /> 114 <Entry name="1 channel length" value="CY_I2S_WS_ONE_CHANNEL_LENGTH" visible="true" /> 115 </ParamChoice> 116 <ParamChoice id="txSdoLatchingTime" name="SDO Latching Time" group="TX" default="0" visible="`${txEnabled}`" editable="true" desc="Available only in Slave mode; should be Normal in master mode. If Normal – the TX output data is set/changed on the SDO wire at the falling SCK edge (accordingly to the I2S Standard, if TX Output clock polarity is Normal). If Half-clock advanced – the TX output data is set/changed on the SDO wire at the rising SCK edge (if TX Output clock polarity is Normal) which goes before that Normal falling SCK edge, i.e. the SDO waveform is advanced by 0.5 SCK period. If TX Output clock polarity is Inverted – the rising/falling edges just swaps in above explanations. The latching in terms of TX means the real time when the output TX trigger sets the data on SDO wire; that is, the data changing time."> 117 <Entry name="Normal" value="0" visible="true" /> 118 <Entry name="Half-clock advanced" value="1" visible="true" /> 119 </ParamChoice> 120 <ParamChoice id="txSckiPolarity" name="Input Serial Clock Polarity" group="TX" default="0" visible="`${txEnabled}`" editable="`${txMode == 0}`" desc="Polarity of the input SCK signal (available only in slave mode)"> 121 <Entry name="Normal" value="0" visible="true" /> 122 <Entry name="Inverted" value="1" visible="true" /> 123 </ParamChoice> 124 <ParamChoice id="txSckoPolarity" name="Output Serial Clock Polarity" group="TX" default="0" visible="`${txEnabled}`" editable="`${txMode == 1}`" desc="Polarity of the output SCK signal (available only in master mode)"> 125 <Entry name="Normal" value="0" visible="true" /> 126 <Entry name="Inverted" value="1" visible="true" /> 127 </ParamChoice> 128 <ParamRange id="txFifoTriggerLevel" name="FIFO Trigger Level" group="TX" default="0" min="0" max="255" resolution="1" visible="`${txEnabled}`" editable="true" desc="Set FIFO level to trigger an event (interrupt or DMA request)." /> 129 <ParamBool id="txDmaTrigger" name="DMA Trigger" group="TX" default="false" visible="`${txEnabled}`" editable="true" desc="Enables DMA trigger" /> 130 131 <ParamBool id="txWatchdogEnable" name="Watchdog Enable" group="TX" default="false" visible="`${txEnabled}`" editable="true" desc="Trigger interrupt if Watchdog timer value reaches zero" /> 132 <ParamRange id="txWatchdogValue" name="Watchdog Value" group="TX" default="4294967295" min="0" max="4294967295" resolution="1" visible="`${txEnabled && txWatchdogEnable}`" editable="true" desc="The reset value of the Watchdog timer" /> 133 134 <!-- RX --> 135 <ParamBool id="rxEnabled" name="Enable" group="RX" default="true" visible="true" editable="true" desc="Enables the receiver" /> 136 <ParamChoice id="rxMode" name="Mode" group="RX" default="1" visible="`${rxEnabled}`" editable="true" desc="Sets mode to master or slave"> 137 <Entry name="Slave" value="0" visible="true" /> 138 <Entry name="Master" value="1" visible="true" /> 139 </ParamChoice> 140 <ParamChoice id="rxAlignment" name="Alignment" group="RX" default="CY_I2S_I2S_MODE" visible="`${rxEnabled}`" editable="true" desc="Set interface transfer mode: I2S, Left Justified, TDM mode A, or TDM mode B"> 141 <Entry name="Left Justified" value="CY_I2S_LEFT_JUSTIFIED" visible="true" /> 142 <Entry name="I2S mode" value="CY_I2S_I2S_MODE" visible="true" /> 143 <Entry name="TDM mode A" value="CY_I2S_TDM_MODE_A" visible="true" /> 144 <Entry name="TDM mode B" value="CY_I2S_TDM_MODE_B" visible="true" /> 145 </ParamChoice> 146 <ParamRange id="rxChannels" name="Channels" group="RX" default="2" min="1" max="8" resolution="1" visible="`${rxEnabled}`" editable="true" desc="Number of channels per frame (2 is the only valid value for Left Justified and I2S modes)" /> 147 <ParamChoice id="rxChannelLength" name="Channel Length" group="RX" default="16" visible="`${rxEnabled}`" editable="true" desc="Set channel length in bits (32 bit is the only valid value for TDM modes)"> 148 <Entry name="8" value="8" visible="true" /> 149 <Entry name="16" value="16" visible="true" /> 150 <Entry name="18" value="18" visible="true" /> 151 <Entry name="20" value="20" visible="true" /> 152 <Entry name="24" value="24" visible="true" /> 153 <Entry name="32" value="32" visible="true" /> 154 </ParamChoice> 155 <ParamChoice id="rxWordLength" name="Word Length" group="RX" default="16" visible="`${rxEnabled}`" editable="true" desc="Set word length (in bits)"> 156 <Entry name="8" value="8" visible="true" /> 157 <Entry name="16" value="16" visible="true" /> 158 <Entry name="18" value="18" visible="true" /> 159 <Entry name="20" value="20" visible="true" /> 160 <Entry name="24" value="24" visible="true" /> 161 <Entry name="32" value="32" visible="true" /> 162 </ParamChoice> 163 164 <ParamRange id="rxFrameRate" name="Frame Rate (ksps)" group="RX" default="`${((rxAlignment eq CY_I2S_TDM_MODE_A) || (rxAlignment eq CY_I2S_TDM_MODE_B)) ? (bitRate / 256) : (bitRate / rxChannelLength / 2)}`" min="0" max="10000000" resolution="0.001" visible="`${rxEnabled}`" editable="false" desc="Shows the actual frame rate" /> 165 166 <ParamChoice id="rxSignExtension" name="Sign Extension" group="RX" default="0" visible="`${rxEnabled}`" editable="true" desc="Set the sign extension bits level (available only when word length is less than 32 bit). It fills all the RX FIFO word MSBs by the data word sign bit (MSB) or by 0"> 167 <Entry name="0" value="0" visible="true" /> 168 <Entry name="MSB" value="1" visible="true" /> 169 </ParamChoice> 170 <ParamChoice id="rxWsPulseWidth" name="WS Pulse Width" group="RX" default="CY_I2S_WS_ONE_CHANNEL_LENGTH" visible="`${rxEnabled}`" editable="true" desc="Pulse width of the WS signal: one SCK period or one channel length. The one channel length is the only valid value for I2S and Left Justified modes"> 171 <Entry name="1 SCK period" value="CY_I2S_WS_ONE_SCK_CYCLE" visible="true" /> 172 <Entry name="1 channel length" value="CY_I2S_WS_ONE_CHANNEL_LENGTH" visible="true" /> 173 </ParamChoice> 174 <ParamChoice id="rxSdiLatchingTime" name="SDI Latching Time" group="RX" default="0" visible="`${rxEnabled}`" editable="true" desc="Available only in Master mode; should be Normal in slave mode. If Normal – the RX input data is captured on the SDI wire at the rising SCK edge (accordingly to the I2S Standard, if RX Output clock polarity is Normal). If Half-clock delayed – the RX input data is captured on the SDI wire at the falling SCK edge (if RX Output clock polarity is Normal) which goes after that Normal rising SCK edge, i.e. the SDI waveform is delayed by 0.5 SCK period. If RX Output clock polarity is Inverted – the rising/falling edges just swaps in above explanations. The latching in terms of RX means the real time when the input RX trigger captures the data on SDI wire, i.e. about at a middle between the data changing edges."> 175 <Entry name="Normal" value="0" visible="true" /> 176 <Entry name="Half-clock delayed" value="1" visible="true" /> 177 </ParamChoice> 178 <ParamChoice id="rxSckiPolarity" name="Input Serial Clock Polarity" group="RX" default="0" visible="`${rxEnabled}`" editable="`${rxMode == 0}`" desc="Polarity of the input SCK signal (available only in slave mode)"> 179 <Entry name="Normal" value="0" visible="true" /> 180 <Entry name="Inverted" value="1" visible="true" /> 181 </ParamChoice> 182 <ParamChoice id="rxSckoPolarity" name="Output Serial Clock Polarity" group="RX" default="0" visible="`${rxEnabled}`" editable="`${rxMode == 1}`" desc="Polarity of the output SCK signal (available only in master mode)"> 183 <Entry name="Normal" value="0" visible="true" /> 184 <Entry name="Inverted" value="1" visible="true" /> 185 </ParamChoice> 186 <ParamRange id="rxFifoTriggerLevel" name="FIFO Trigger Level" group="RX" default="0" min="0" max="`${255 - rxChannels}`" resolution="1" visible="`${rxEnabled}`" editable="true" desc="Set FIFO level to trigger an event (interrupt or DMA request). Should not be greater than [255 - (number of channels)]." /> 187 <ParamBool id="rxDmaTrigger" name="DMA Trigger" group="RX" default="false" visible="`${rxEnabled}`" editable="true" desc="Enables DMA trigger" /> 188 189 <ParamBool id="rxWatchdogEnable" name="Watchdog Enable" group="RX" default="false" visible="`${rxEnabled}`" editable="true" desc="Trigger interrupt if Watchdog timer value reaches zero" /> 190 <ParamRange id="rxWatchdogValue" name="Watchdog Value" group="RX" default="4294967295" min="0" max="4294967295" resolution="1" visible="`${rxEnabled && rxWatchdogEnable}`" editable="true" desc="The reset value of the Watchdog timer" /> 191 192 <!-- Connections --> 193 194 <ParamSignal port="tx_sck[0]" name="Tx Serial Clock" group="`${txMode == 1 ? "Outputs" : "Inputs"}`" visible="`${txEnabled}`" desc="Tx serial clock (visible when Tx is enabled)." canBeEmpty="`${(txMode == 1) || !txEnabled}`" > 195 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 196 <Parameter id="DriveModes" severity="ERROR" reason=""> 197 <Fixed value="`${txMode == 1 ? "CY_GPIO_DM_STRONG_IN_OFF" : "CY_GPIO_DM_HIGHZ"}`" /> 198 </Parameter> 199 </Constraint> 200 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 201 </ParamSignal> 202 <ParamSignal port="tx_ws[0]" name="Tx Word Select" group="`${txMode == 1 ? "Outputs" : "Inputs"}`" visible="`${txEnabled}`" desc="Tx word select (visible when Tx is enabled)." canBeEmpty="`${(txMode == 1) || !txEnabled}`" > 203 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 204 <Parameter id="DriveModes" severity="ERROR" reason=""> 205 <Fixed value="`${txMode == 1 ? "CY_GPIO_DM_STRONG_IN_OFF" : "CY_GPIO_DM_HIGHZ"}`" /> 206 </Parameter> 207 </Constraint> 208 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 209 </ParamSignal> 210 <ParamSignal port="tx_sdo[0]" name="Tx Serial Data" group="Outputs" visible="`${txEnabled}`" desc="Tx serial data output (visible when Tx is enabled)." canBeEmpty="true" > 211 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 212 <Parameter id="DriveModes" severity="ERROR" reason=""> 213 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 214 </Parameter> 215 </Constraint> 216 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 217 </ParamSignal> 218 <ParamSignal port="rx_sck[0]" name="Rx Serial Clock" group="`${rxMode == 1 ? "Outputs" : "Inputs"}`" visible="`${rxEnabled}`" desc="Rx serial clock (visible when Rx is enabled)." canBeEmpty="`${(rxMode == 1) || !rxEnabled}`" > 219 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 220 <Parameter id="DriveModes" severity="ERROR" reason=""> 221 <Fixed value="`${rxMode == 1 ? "CY_GPIO_DM_STRONG_IN_OFF" : "CY_GPIO_DM_HIGHZ"}`" /> 222 </Parameter> 223 </Constraint> 224 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 225 </ParamSignal> 226 <ParamSignal port="rx_ws[0]" name="Rx Word Select" group="`${rxMode == 1 ? "Outputs" : "Inputs"}`" visible="`${rxEnabled}`" desc="Rx word select (visible when Rx is enabled)." canBeEmpty="`${(rxMode == 1) || !rxEnabled}`" > 227 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 228 <Parameter id="DriveModes" severity="ERROR" reason=""> 229 <Fixed value="`${rxMode == 1 ? "CY_GPIO_DM_STRONG_IN_OFF" : "CY_GPIO_DM_HIGHZ"}`" /> 230 </Parameter> 231 </Constraint> 232 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 233 </ParamSignal> 234 <ParamSignal port="rx_sdi[0]" name="Rx Serial Data" group="Inputs" visible="`${rxEnabled}`" desc="Rx serial data input (visible when Rx is enabled)." canBeEmpty="`${!rxEnabled}`" > 235 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 236 <Parameter id="DriveModes" severity="ERROR" reason=""> 237 <Fixed value="CY_GPIO_DM_HIGHZ" /> 238 </Parameter> 239 </Constraint> 240 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 241 </ParamSignal> 242 <ParamSignal port="tr_i2s_tx_req[0]" name="Tx DMA Transfer Request Signal" group="Outputs" visible="`${txDmaTrigger && txEnabled}`" desc="Tx DMA transfer request signal (visible when Tx DMA trigger is enabled)." canBeEmpty="true" > 243 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 244 <Parameter id="DriveModes" severity="ERROR" reason=""> 245 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 246 </Parameter> 247 </Constraint> 248 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 249 </ParamSignal> 250 <ParamSignal port="tr_i2s_rx_req[0]" name="Rx DMA Transfer Request Signal" group="Outputs" visible="`${rxDmaTrigger && rxEnabled}`" desc="Rx DMA transfer request signal (visible when Rx DMA trigger is enabled)." canBeEmpty="true" > 251 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 252 <Parameter id="DriveModes" severity="ERROR" reason=""> 253 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 254 </Parameter> 255 </Constraint> 256 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 257 </ParamSignal> 258 259 <ParamBool id="inFlash" name="Store Config in Flash" group="Advanced" default="true" visible="true" editable="true" desc="Controls whether the configuration structure is stored in flash (const, true) or SRAM (not const, false)." /> 260 261 <!-- I2S instance number --> 262 <ParamString id="InstNumber" name="Instance Number" group="Internal" default="`${getInstNumber("audioss")}`" visible="false" editable="false" desc="I2S Instance number." /> 263 <ParamBool id="hasAudioss1" name="hasAudioss1" group="Internal" default="`${hasBlock("audioss[1]")}`" visible="false" editable="false" desc="Check whether device has more than one audioss" /> 264 265 </Parameters> 266 267 <DRCs> 268 <!-- RX direction --> 269 <DRC type="ERROR" text="In TDM mode the channel length is fixed 32 bit" condition="`${rxEnabled && (((rxAlignment eq CY_I2S_TDM_MODE_A) || (rxAlignment eq CY_I2S_TDM_MODE_B)) && !(rxChannelLength eq 32))}`" /> 270 <DRC type="ERROR" text="Only "2 channels" is supported during Left Justified or I2S mode" condition="`${rxEnabled && ((rxAlignment eq CY_I2S_I2S_MODE) || (rxAlignment eq CY_I2S_LEFT_JUSTIFIED)) && (rxChannels != 2)}`" /> 271 <DRC type="ERROR" text="RX SDI latching time should be Normal in Slave mode" condition="`${rxEnabled && ((rxSdiLatchingTime != 0) && (rxMode == 0))}`" /> 272 <DRC type="ERROR" text="RX WS Pulse Width: only the "1 channel length" value is possible in I2S or Left Justified modes" condition="`${rxEnabled && (((rxAlignment eq CY_I2S_I2S_MODE) || (rxAlignment eq CY_I2S_LEFT_JUSTIFIED)) && !(rxWsPulseWidth eq CY_I2S_WS_ONE_CHANNEL_LENGTH))}`" /> 273 <DRC type="ERROR" text="RX Word Length value must be less than or equal RX Channel Length." condition="`${rxEnabled && rxWordLength > rxChannelLength}`" /> 274 275 <DRC type="WARNING" text="The Watchdog timer is effective only in slave mode, so it is recommended to uncheck RX Watchdog Enable checkbox in RX master mode" condition="`${rxEnabled && (rxMode == 1) && (rxWatchdogEnable == true)}`" /> 276 277 <!-- TX direction --> 278 <DRC type="ERROR" text="In TDM mode the channel length is fixed 32 bit" condition="`${txEnabled && (((txAlignment eq CY_I2S_TDM_MODE_A) || (txAlignment eq CY_I2S_TDM_MODE_B)) && !(txChannelLength eq 32))}`" /> 279 <DRC type="ERROR" text="Only "2 channels" is supported during Left Justified or I2S mode" condition="`${txEnabled && ((txAlignment eq CY_I2S_I2S_MODE) || (txAlignment eq CY_I2S_LEFT_JUSTIFIED)) && (txChannels != 2)}`" /> 280 <DRC type="ERROR" text="TX SDO latching time should be Normal in Master mode" condition="`${txEnabled && ((txSdoLatchingTime != 0) && (txMode == 1))}`" /> 281 <DRC type="ERROR" text="TX WS Pulse Width: only the "1 channel length" value is possible in I2S or Left Justified modes" condition="`${txEnabled && (((txAlignment eq CY_I2S_I2S_MODE) || (txAlignment eq CY_I2S_LEFT_JUSTIFIED)) && !(txWsPulseWidth eq CY_I2S_WS_ONE_CHANNEL_LENGTH))}`" /> 282 <DRC type="ERROR" text="TX Word Length value must be less than or equal TX Channel Length." condition="`${txEnabled && txWordLength > txChannelLength}`" /> 283 284 <DRC type="WARNING" text="The Watchdog timer is effective only in slave mode, so it is recommended to uncheck TX Watchdog Enable checkbox in TX master mode" condition="`${txEnabled && (txMode == 1) && (txWatchdogEnable == true)}`" /> 285 </DRCs> 286 287 <ConfigFirmware> 288 <ConfigInclude value="cy_i2s.h" include="true" /> 289 <ConfigInclude value="cyhal_hwmgr.h" include="true" guard="defined (CY_USING_HAL)" /> 290 <ConfigInclude value="cyhal.h" include="true" guard="defined (CY_USING_HAL)" /> 291 292 <ConfigDefine name="`${INST_NAME}`_HW" value="I2S`${hasAudioss1 ? InstNumber : ""}`" public="true" include="true" /> 293 <ConfigDefine name="`${INST_NAME}`_IRQ" value="audioss_`${hasAudioss1 ? InstNumber . "_" : ""}`interrupt_i2s_IRQn" public="true" include="true" /> 294 295 <ConfigStruct name="`${INST_NAME . "_config"}`" type="cy_stc_i2s_config_t" const="`${inFlash}`" public="true" include="true" > 296 <Member name="txEnabled" value="`${txEnabled}`" /> 297 <Member name="rxEnabled" value="`${rxEnabled}`" /> 298 <Member name="txDmaTrigger" value="`${txDmaTrigger}`" /> 299 <Member name="rxDmaTrigger" value="`${rxDmaTrigger}`" /> 300 <Member name="clkDiv" value="`${clockDiv}`" /> 301 <Member name="extClk" value="`${extClk}`" /> 302 <Member name="txMasterMode" value="`${txMode}`" /> 303 <Member name="txAlignment" value="`${txAlignment}`" /> 304 <Member name="txWsPulseWidth" value="`${txWsPulseWidth}`" /> 305 <Member name="txWatchdogEnable" value="`${txWatchdogEnable}`" /> 306 <Member name="txWatchdogValue" value="`${txWatchdogValue}`" /> 307 <Member name="txSdoLatchingTime" value="`${txSdoLatchingTime}`" /> 308 <Member name="txSckoInversion" value="`${txSckoPolarity}`" /> 309 <Member name="txSckiInversion" value="`${txSckiPolarity}`" /> 310 <Member name="txChannels" value="`${txChannels}`" /> 311 <Member name="txChannelLength" value="CY_I2S_LEN`${txChannelLength}`" /> 312 <Member name="txWordLength" value="CY_I2S_LEN`${txWordLength}`" /> 313 <Member name="txOverheadValue" value="`${txOverheadValue}`" /> 314 <Member name="txFifoTriggerLevel" value="`${txFifoTriggerLevel}`" /> 315 <Member name="rxMasterMode" value="`${rxMode}`" /> 316 <Member name="rxAlignment" value="`${rxAlignment}`" /> 317 <Member name="rxWsPulseWidth" value="`${rxWsPulseWidth}`" /> 318 <Member name="rxWatchdogEnable" value="`${rxWatchdogEnable}`" /> 319 <Member name="rxWatchdogValue" value="`${rxWatchdogValue}`" /> 320 <Member name="rxSdiLatchingTime" value="`${rxSdiLatchingTime}`" /> 321 <Member name="rxSckoInversion" value="`${rxSckoPolarity}`" /> 322 <Member name="rxSckiInversion" value="`${rxSckiPolarity}`" /> 323 <Member name="rxChannels" value="`${rxChannels}`" /> 324 <Member name="rxChannelLength" value="CY_I2S_LEN`${rxChannelLength}`" /> 325 <Member name="rxWordLength" value="CY_I2S_LEN`${rxWordLength}`" /> 326 <Member name="rxSignExtension" value="`${rxSignExtension}`" /> 327 <Member name="rxFifoTriggerLevel" value="`${rxFifoTriggerLevel}`" /> 328 <Member name="mclkEn" value="`${mClk}`" include="`${(version > 1)}`" /> 329 <Member name="mclkDiv" value="`${mclockDiv}`" include="`${(version > 1)}`" /> 330 </ConfigStruct> 331 332 <ConfigStruct name="`${INST_NAME}`_obj" type="cyhal_resource_inst_t" const="true" public="true" include="true" guard="defined (CY_USING_HAL)"> 333 <Member name="type" value="CYHAL_RSC_I2S" /> 334 <Member name="block_num" value="`${InstNumber}`U" /> 335 <Member name="channel_num" value="0U" /> 336 </ConfigStruct> 337 338 <ConfigStruct name="`${INST_NAME}`_hal_config" type="cyhal_i2s_configurator_t" const="`${inFlash}`" public="true" include="true" guard="defined (CY_USING_HAL)"> 339 <Member name="resource" value="&`${INST_NAME}`_obj" /> 340 <Member name="config" value="&`${INST_NAME . "_config"}`" /> 341 <Member name="clock" value="&CYHAL_CLOCK_HF[`${getInstFromLocation(sourceClock, "hfclk")}`]" /> 342 <Member name="mclk_hz_rx" value="`${extClk ? floor(i2sClk) : 0}`u" /> 343 <Member name="mclk_hz_tx" value="`${extClk ? floor(i2sClk) : 0}`u" /> 344 </ConfigStruct> 345 346 <ConfigInstruction value="cyhal_hwmgr_reserve(&`${INST_NAME}`_obj);" include="true" guard="defined (CY_USING_HAL)" /> 347 </ConfigFirmware> 348 349</Personality> 350
