1<?xml version="1.0" encoding="utf-8"?> 2 3<!--**************************************************************************** 4* \file dpslp.cypersonality 5* \version 1.0 6* 7* \brief 8* Deep Sleep Clock personality description file. 9* 10******************************************************************************** 11* \copyright 12* Copyright 2020-22 Cypress Semiconductor Corporation 13* SPDX-License-Identifier: Apache-2.0 14* 15* Licensed under the Apache License, Version 2.0 (the "License"); 16* you may not use this file except in compliance with the License. 17* You may obtain a copy of the License at 18* 19* http://www.apache.org/licenses/LICENSE-2.0 20* 21* Unless required by applicable law or agreed to in writing, software 22* distributed under the License is distributed on an "AS IS" BASIS, 23* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24* See the License for the specific language governing permissions and 25* limitations under the License. 26*****************************************************************************--> 27 28<Personality id="mxs40dpslp" name="Deep Sleep Clock" version="1.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 29 <Dependencies> 30 <IpBlock name="mxs40pass_ver2" /> 31 <Resource name="pass\.dpslp"/> 32 <!--DependentResource name="pass.sar" /--> 33 </Dependencies> 34 <ExposedMembers> 35 <ExposedMember key="frequency" paramId="frequency" /> 36 <ExposedMember key="accuracy" paramId="accuracy" /> 37 <ExposedMember key="error" paramId="error" /> 38 <ExposedMember key="clock" paramId="clock" /> 39 </ExposedMembers> 40 <Parameters> 41 <!-- PDL documentation --> 42 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__sysanalog.html" linkText="Open SysAnalog Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 43 44 <ParamChoice id="clock" name="Clock Source" group="General" default="CY_SYSANALOG_DEEPSLEEP_SRC_LPOSC" visible="true" editable="true" desc="Select the clock source for the opamp pump clock." > 45 <Entry name="LPOSC" value="CY_SYSANALOG_DEEPSLEEP_SRC_LPOSC" visible="true" /> 46 <Entry name="CLK_MF" value="CY_SYSANALOG_DEEPSLEEP_SRC_CLK_MF" visible="true" /> 47 </ParamChoice> 48 49 <ParamString id="sourceClockRsc" name="sourceClockRsc" group="Internal" default="`${clock eq CY_SYSANALOG_DEEPSLEEP_SRC_CLK_MF ? "srss[0].clock[0].mfclk[0]" : "pass[0].lposc[0]"}`" visible="false" editable="false" desc="" /> 50 <ParamBool id="error" name="Clock Error" group="Internal" default="`${!isBlockUsed(sourceClockRsc)}`" visible="false" editable="false" desc="" /> 51 <ParamRange id="sourceFreq" name="Source Frequency" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, "frequency") : 0}`" min="0" max="8000000" resolution="1" visible="false" editable="false" desc="" /> 52 <ParamString id="accuracy" name="accuracy" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, "accuracy") : 0}`" visible="false" editable="false" desc="" /> 53 <ParamString id="sourceFrequencyInfo" name="Source Frequency" group="General" default="`${formatFrequency(sourceFreq,accuracy)}`" visible="true" editable="false" desc="Source clock frequency" /> 54 55 <ParamChoice id="dsclkdiv" name="Clock Divider" group="General" default="CY_SYSANALOG_DEEPSLEEP_CLK_DIV_BY_4" visible="true" editable="true" desc="Select the clock source for the opamp pump clock." > 56 <Entry name="1" value="CY_SYSANALOG_DEEPSLEEP_CLK_NO_DIV" visible="`${clock eq CY_SYSANALOG_DEEPSLEEP_SRC_CLK_MF}`"/> 57 <Entry name="2" value="CY_SYSANALOG_DEEPSLEEP_CLK_DIV_BY_2" visible="`${clock eq CY_SYSANALOG_DEEPSLEEP_SRC_CLK_MF}`"/> 58 <Entry name="4" value="CY_SYSANALOG_DEEPSLEEP_CLK_DIV_BY_4" visible="true"/> 59 <Entry name="8" value="CY_SYSANALOG_DEEPSLEEP_CLK_DIV_BY_8" visible="true"/> 60 <Entry name="16" value="CY_SYSANALOG_DEEPSLEEP_CLK_DIV_BY_16" visible="true"/> 61 </ParamChoice> 62 63 <ParamRange id="divider" name="divider" group="Internal" default="`${dsclkdiv eq CY_SYSANALOG_DEEPSLEEP_CLK_DIV_BY_2 ? 2 : 64 dsclkdiv eq CY_SYSANALOG_DEEPSLEEP_CLK_DIV_BY_4 ? 4 : 65 dsclkdiv eq CY_SYSANALOG_DEEPSLEEP_CLK_DIV_BY_8 ? 8 : 66 dsclkdiv eq CY_SYSANALOG_DEEPSLEEP_CLK_DIV_BY_16 ? 16 : 1}`" min="1" max="16" resolution="1" visible="false" editable="false" desc="Sets divider value for the Deep Sleep clock source" /> 67 <ParamRange id="frequency" name="Frequency" group="Internal" default="`${!error ? sourceFreq / divider : 0}`" min="0" max="8000000" resolution="1" visible="false" editable="false" desc="" /> 68 <ParamString id="frequencyInfo" name="Frequency" group="General" default="`${formatFrequency(frequency,accuracy)}`" visible="true" editable="false" desc="The resulting Deep Sleep Clock frequency" /> 69 70 <ParamString id="mfoRcs" name="mfoRcs" group="Internal" default="srss[0].clock[0].mfo[0]" visible="false" editable="false" desc="" /> 71 72 </Parameters> 73 74 <DRCs> 75 <DRC type="ERROR" text="Source clock for Deep Sleep Clock is not enabled" condition="`${error}`" > 76 <FixIt action="ENABLE_BLOCK" target="`${sourceClockRsc}`" value="" valid="true" /> 77 </DRC> 78 79 <DRC type="ERROR" text="MFO Deep Sleep support should be enabled" condition="`${(clock eq "CY_SYSANALOG_DEEPSLEEP_SRC_CLK_MF") ? ((isBlockUsed(mfoRcs)) ? (!getExposedMember(mfoRcs, "dsen")) : false) : (false)}`" > 80 </DRC> 81 82 <DRC type="ERROR" text="The Deep Sleep Clock frequency should not be greater than 2 MHz" condition="`${frequency > 2000000}`" > 83 <FixIt action="SET_PARAM" target="dsclkdiv" value="CY_SYSANALOG_DEEPSLEEP_CLK_DIV_BY_4" valid="true" /> 84 </DRC> 85 </DRCs> 86 87 <ConfigFirmware> 88 <ConfigInclude value="cy_sysanalog.h" include="true" /> 89 <ConfigDefine name="CY_CFG_SYSANALOG_DEEPSLEEP_SRC" value="`${clock}`" public="true" include="true" /> 90 <ConfigDefine name="CY_CFG_SYSANALOG_DEEPSLEEP_DIV" value="`${dsclkdiv}`" public="true" include="true" /> 91 </ConfigFirmware> 92</Personality> 93
