1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file ctdac.cypersonality 6* \version 1.0 7* 8* \brief 9* CTDAC personality description file. 10* 11******************************************************************************** 12* \copyright 13* Copyright 2018-2022 Cypress Semiconductor Corporation 14* SPDX-License-Identifier: Apache-2.0 15* 16* Licensed under the Apache License, Version 2.0 (the "License"); 17* you may not use this file except in compliance with the License. 18* You may obtain a copy of the License at 19* 20* http://www.apache.org/licenses/LICENSE-2.0 21* 22* Unless required by applicable law or agreed to in writing, software 23* distributed under the License is distributed on an "AS IS" BASIS, 24* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25* See the License for the specific language governing permissions and 26* limitations under the License. 27*****************************************************************************--> 28 29<Personality id="mxs40pass_ctdac" name="CTDAC" version="1.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 30 <Dependencies> 31 <IpBlock name="mxs40pass,mxs40pass_ver2" /> 32 <Resource name="pass\.ctdac" /> 33 </Dependencies> 34 <ExposedMembers /> 35 <Parameters> 36 <!-- PDL documentation --> 37 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__ctdac.html" linkText="Open CTDAC Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 38 39 <!-- Internal variables to control visibility of other stuff --> 40 <ParamString id="ctdac_instance" name="ctdac_instance" group="Internal" default="`${getInstNumber("ctdac")}`" visible="false" editable="false" desc="Internal variable for the CTDAC instance on the device" /> 41 <ParamBool id="hasCTB" name="hasCTB" group="Internal" default="`${hasBlock("pass[0].ctb[0].oa[0]")}`" visible="false" editable="false" desc="Check whether device has CTBs" /> 42 <!-- Internal variables to control visibility of other stuff --> 43 44 <ParamChoice id="vref_source" name="Vref Source" group="General" default="vdda" visible="true" editable="true" desc="Configure the reference source for the CTDAC." > 45 <Entry name="Vdda" value="vdda" visible="true" /> 46 <Entry name="External" value="external_pin" visible="`${hasCTB}`" /> <!-- how to handle which pin the user selects? restrict to a set of pins?--> 47 <!-- MODUS-2327 filed to get Analog Reference as CTB.OA1 input 48 <Entry name="Analog reference" value="external_aref" visible="`${hasCTB}`" /> 49 --> 50 </ParamChoice> 51 52 <!-- 53 <ParamSignal name="External input" port="pass[0].ctb[`${ctdac_instance}`].oa[0].vplus[0]" group="General" visible="`${vref_source eq external_pin}`" desc="" canBeEmpty="false" /> 54 <ParamSignal name="External input 2" port="pass[0].ctb[0].oa[0].vplus[0]" group="General" visible="`${vref_source eq external_pin}`" desc="" canBeEmpty="true" /> 55--> 56 57 <ParamChoice id="output_buffer" name="Output Buffer" group="General" default="unbuffered_pin" visible="true" editable="true" desc="Configure the output to be buffered or unbuffered." > 58 <Entry name="Unbuffered to Pin" value="unbuffered_pin" visible="true" /> 59 <Entry name="Unbuffered Internal" value="unbuffered_internal" visible="true" /> 60 <Entry name="Buffered" value="buffered" visible="`${hasCTB}`" /> 61 </ParamChoice> 62 63 <!-- Internal variables to control visibility of other stuff --> 64 <ParamString id="vref_source_is_vdda" name="vref_source_is_vdda" group="Internal" default="`${vref_source eq vdda}`" visible="false" editable="false" desc="Internal variable to check if Vref source is Vdda" /> 65 <ParamString id="ctb_used" name="ctb_used" group="Internal" default="`${(vref_source ne vdda) || (output_buffer eq buffered)}`" visible="false" editable="false" desc="Internal variable to check if any CTB opamp is used" /> 66 <ParamString id="output_is_unbuffered" name="output_is_unbuffered" group="Internal" default="`${(output_buffer eq unbuffered_pin) || (output_buffer eq unbuffered_internal)}`" visible="false" editable="false" desc="Internal variable to check if output is unbuffered" /> 67 <!-- Internal variables to control visibility of other stuff --> 68 69 <ParamChoice id="format_mode" name="Format" group="General" default="CY_CTDAC_FORMAT_UNSIGNED" visible="true" editable="true" desc="Configure the format in which the DAC value register is decoded." > 70 <Entry name="12-bit Unsigned" value="CY_CTDAC_FORMAT_UNSIGNED" visible="true" /> 71 <Entry name="12-bit Two's-Complement (Signed)" value="CY_CTDAC_FORMAT_SIGNED" visible="true" /> 72 </ParamChoice> 73 74 <ParamRange id="initial_code" name="Initial Code" group="General" default="0" min="`${(format_mode eq CY_CTDAC_FORMAT_UNSIGNED) ? 0 : -2048}`" max="`${(format_mode eq CY_CTDAC_FORMAT_UNSIGNED) ? 4095 : 2047}`" resolution="1" visible="true" editable="true" desc="The initial code in the DAC value and buffered value registers." /> 75 76 <ParamChoice id="update_mode" name="Update Mode" group="General" default="CY_CTDAC_UPDATE_BUFFERED_WRITE" visible="true" editable="true" desc="Configure how the DAC value is updated." > 77 <Entry name="Direct Write" value="CY_CTDAC_UPDATE_DIRECT_WRITE" visible="true" /> 78 <Entry name="Buffered Write" value="CY_CTDAC_UPDATE_BUFFERED_WRITE" visible="true" /> 79 <!--<Entry name="Strobe edge sync" value="CY_CTDAC_UPDATE_STROBE_EDGE_SYNC" visible="true" /> 80 <Entry name="Strobe edge immediate" value="CY_CTDAC_UPDATE_STROBE_EDGE_IMMEDIATE" visible="true" /> 81 <Entry name="Strobe level" value="CY_CTDAC_UPDATE_STROBE_LEVEL" visible="true" />--> 82 </ParamChoice> 83 84 <ParamBool id="deep_sleep" name="Enable Deep Sleep Operation" group="General" default="false" visible="true" editable="true" desc="Configure whether the DAC is enabled in Deep Sleep mode." /> 85 86 <ParamSignal name="Clock" port="clock[0]" group="Connections" visible="`${update_mode ne CY_CTDAC_UPDATE_DIRECT_WRITE}`" desc="Clock that operates this block." canBeEmpty="`${update_mode eq CY_CTDAC_UPDATE_DIRECT_WRITE}`"> 87 <Constraint type="REQUIRE" targetLocation="peri\[\d+\]\.div_.*" valid="`${update_mode ne CY_CTDAC_UPDATE_DIRECT_WRITE}`" > 88 <Parameter id="intDivider" severity="ERROR" reason="Clock frequency is '`${getExposedMember("REF_LOCATION", "frequency") / 1000}` kHz', but must be less than 500 kHz for proper CTDAC operation."> 89 <Range min="`${ceil(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / 500000)}`" max="`${floor(getExposedMember("REF_LOCATION", "frequency") * getExposedMember("REF_LOCATION", "divider") / 1)}`" /> 90 </Parameter> 91 </Constraint> 92 </ParamSignal> 93 <ParamString id="source_clk" name="Source Clock Resource" group="Connections" default="`${getBlockFromSignal("clock[0]")}`" visible="false" editable="false" desc="Source Clock Resource" /> 94 <ParamString id="clk_freq_hz" name="clk_freq_hz" group="Connections" default="`${(update_mode ne CY_CTDAC_UPDATE_DIRECT_WRITE) ? getExposedMember(source_clk, "frequency") : 0}`" visible="false" editable="false" desc="CTDAC clock frequency in hertz" /> 95 <ParamString id="clk_freq_display" name="Clock Frequency" group="Connections" default="`${floor(clk_freq_hz / pow(10, 3))}` kHz" visible="`${update_mode ne CY_CTDAC_UPDATE_DIRECT_WRITE}`" editable="false" desc="Displayed CTDAC clock frequency in kHz" /> 96 97 <ParamSignal name="DAC Output" port="ctdvout[0]" group="Connections" visible="`${output_buffer ne unbuffered_pin}`" desc="Buffered DAC analog output connection." canBeEmpty="true" > 98 <Constraint type="REQUIRE" targetLocation="pass\[\d+\]\.ctb\[0\]\.oa\[0\]\.vplus\[0\]" valid="`${output_buffer eq buffered}`" > 99 </Constraint> 100 </ParamSignal> 101 102 <ParamSignal name="DAC Output Unbuffered" port="ctdvoutsw[0]" group="Connections" visible="`${output_buffer eq unbuffered_pin}`" desc="Unbuffered DAC analog output to pin." canBeEmpty="true" > 103 </ParamSignal> 104 105 <ParamSignal name="Reference Source" port="ctdrefdrive[0]" group="Connections" visible="`${vref_source eq external_pin}`" desc="External reference selection." canBeEmpty="true" > 106 <Constraint type="REQUIRE" targetLocation="pass\[\d+\]\.ctb\[0\]\.oa\[1\]\.(out_1x|vminus)\[0\]" valid="`${vref_source eq external_pin}`" > 107 </Constraint> 108 </ParamSignal> 109 110 <ParamSignal name="Trigger Output" port="tr_ctdac_empty[0]" group="Connections" visible="true" desc="DAC trigger output connection." canBeEmpty="true" > 111 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 112 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 113 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 114 </Parameter> 115 </Constraint> 116 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 117 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 118 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 119 </Parameter> 120 </Constraint> 121 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 122 </ParamSignal> 123 <!--<ParamSignal name="Strobe Input" port="dsi_ctdac_strobe[0]" group="Connections" visible="true" desc="DAC trigger output connection." canBeEmpty="`${update_mode < CY_CTDAC_UPDATE_STROBE_EDGE_SYNC}`" />--> 124 125 <!--Advanced--> 126 <ParamChoice id="output_mode" name="Output Mode" group="Advanced" default="CY_CTDAC_OUTPUT_VALUE" visible="true" editable="true" desc="Configure the DAC output mode to high-z, enabled and driving, or resisitve pulled to Vssa or Vref" > 127 <Entry name="Output the Code Value" value="CY_CTDAC_OUTPUT_VALUE" visible="true" /> 128 <Entry name="Output the Code Value Plus 1" value="CY_CTDAC_OUTPUT_VALUE_PLUS1" visible="true" /> 129 <Entry name="High-Z the Output" value="CY_CTDAC_OUTPUT_HIGHZ" visible="true" /> 130 <Entry name="Connect Output to Vssa" value="CY_CTDAC_OUTPUT_VSSA" visible="true" /> 131 <Entry name="Connect Output to Vref" value="CY_CTDAC_OUTPUT_VREF" visible="true" /> 132 </ParamChoice> 133 <ParamBool id="inFlash" name="Store Config in Flash" group="Advanced" default="true" visible="true" editable="true" desc="Controls whether the configuration structure is stored in flash (const, true) or SRAM (not const, false)." /> 134 135 <!-- Peripheral clock divider connection --> 136 <ParamString id="pclk" name="PCLK" group="Internal" default="`${getBlockFromSignal("clock[0]")}`" visible="false" editable="false" desc="Connected peripheral clock divider (PCLK)." /> 137 <ParamBool id="pclkOk" name="PCLK Valid" group="Internal" default="`${hasConnection("clock", 0) && isBlockUsed(pclk)}`" visible="false" editable="false" desc="Checks whether there is a PCLK connected and enabled." /> 138 <ParamString id="pclkDst" name="PCLK Destination" group="Internal" default="PCLK_PASS_CLOCK_CTDAC" visible="false" editable="false" desc="Generates PCLK connection define." /> 139 140 </Parameters> 141 142 <DRCs> 143 <!-- MODUS-2327 - An AREF personality is required which should have the DRC below 144 <DRC type="ERROR" text="The Vref must be enabled for Deep Sleep operation in the Programmable Analog resource." condition="`${deep_sleep && aref_used && (getExposedMember("pass[0]", "deep_sleep_mode") ne "CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF")}`" paramId="deep_sleep" /> 145 --> 146 </DRCs> 147 148 <ConfigFirmware> 149 <ConfigInclude value="cy_ctdac.h" include="true" /> 150 <ConfigInclude value="cy_sysclk.h" include="true" /> 151 <ConfigInclude value="cyhal_hwmgr.h" include="true" guard="defined (CY_USING_HAL)" /> 152 153 <ConfigDefine name="`${INST_NAME}`_HW" value="CTDAC`${ctdac_instance}`" public="true" include="true" /> 154 155 <ConfigStruct name="`${INST_NAME . "_config"}`" type="cy_stc_ctdac_config_t" const="`${inFlash}`" public="true" include="true" > 156 <Member name="refSource" value="`${vref_source_is_vdda ? "CY_CTDAC_REFSOURCE_VDDA" : "CY_CTDAC_REFSOURCE_EXTERNAL"}`" /> 157 <Member name="formatMode" value="`${format_mode}`" /> 158 <Member name="updateMode" value="`${update_mode}`"/> 159 <Member name="deglitchMode" value="`${output_is_unbuffered ? "CY_CTDAC_DEGLITCHMODE_UNBUFFERED" : "CY_CTDAC_DEGLITCHMODE_BUFFERED"}`"/> 160 <Member name="outputMode" value="`${output_mode}`"/> 161 <Member name="outputBuffer" value="`${output_is_unbuffered ? "CY_CTDAC_OUTPUT_UNBUFFERED" : "CY_CTDAC_OUTPUT_BUFFERED"}`"/> 162 <Member name="deepSleep" value="`${deep_sleep ? "CY_CTDAC_DEEPSLEEP_ENABLE" : "CY_CTDAC_DEEPSLEEP_DISABLE"}`"/> 163 <Member name="deglitchCycles" value="0"/> 164 <Member name="value" value="`${initial_code}`"/> 165 <Member name="nextValue" value="`${initial_code}`"/> 166 <Member name="enableInterrupt" value="true"/> 167 <Member name="configClock" value="false"/> 168 <Member name="dividerType" value="CY_SYSCLK_DIV_8_BIT"/> 169 <Member name="dividerNum" value="0"/> 170 <Member name="dividerIntValue" value="0"/> 171 <Member name="dividerFracValue" value="0"/> 172 </ConfigStruct> 173 174 <ConfigStruct name="`${INST_NAME}`_obj" type="cyhal_resource_inst_t" const="true" public="true" include="true" guard="defined (CY_USING_HAL)"> 175 <Member name="type" value="CYHAL_RSC_DAC" /> 176 <Member name="block_num" value="`${ctdac_instance}`U" /> 177 <Member name="channel_num" value="0U" /> 178 </ConfigStruct> 179 180 <ConfigStruct name="`${INST_NAME}`_hal_config" type="cyhal_dac_configurator_t" const="`${inFlash}`" public="true" include="true" guard="defined (CY_USING_HAL)"> 181 <Member name="resource" value="&`${INST_NAME}`_obj" /> 182 <Member name="config" value="&`${INST_NAME}`_config" /> 183 </ConfigStruct> 184 185 <ConfigInstruction value="Cy_SysClk_PeriphAssignDivider(`${pclkDst}`, `${getExposedMember(pclk, "clockSel")}`);" include="`${pclkOk}`" /> 186 <ConfigInstruction value="cyhal_hwmgr_reserve(&`${INST_NAME}`_obj);" include="true" guard="defined (CY_USING_HAL)" /> 187 </ConfigFirmware> 188</Personality> 189
