1<?xml version="1.0" encoding="utf-8"?>
2
3<!--****************************************************************************
4* \file ctbmclk.cypersonality
5* \version 1.0
6*
7* \brief
8* CTBm Pump Clock personality description file.
9*
10********************************************************************************
11* \copyright
12* Copyright 2020-2022 Cypress Semiconductor Corporation
13* SPDX-License-Identifier: Apache-2.0
14*
15* Licensed under the Apache License, Version 2.0 (the "License");
16* you may not use this file except in compliance with the License.
17* You may obtain a copy of the License at
18*
19*     http://www.apache.org/licenses/LICENSE-2.0
20*
21* Unless required by applicable law or agreed to in writing, software
22* distributed under the License is distributed on an "AS IS" BASIS,
23* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24* See the License for the specific language governing permissions and
25* limitations under the License.
26*****************************************************************************-->
27
28<Personality id="mxs40ctbmclk" name="CTBm Pump Clock" version="1.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v7">
29  <Dependencies>
30    <IpBlock name="mxs40pass_ver2" />
31    <Resource name="pass\.ctbmclk"/>
32    <DependentResource name="pass.ctb.oa" />
33  </Dependencies>
34  <ExposedMembers>
35    <ExposedMember key="frequency" paramId="frequency" />
36    <ExposedMember key="accuracy"  paramId="accuracy" />
37    <ExposedMember key="error"     paramId="error" />
38    <ExposedMember key="clock"     paramId="clock" />
39  </ExposedMembers>
40  <Parameters>
41    <!-- PDL documentation -->
42    <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__ctb.html" linkText="Open CTB Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" />
43
44    <ParamBool id="debug" name="debug" group="Internal" default="true" visible="false" editable="false" desc="" />
45    <ParamBool id="isClkPumpEnabled" name="Is Pump Clock Enabled" group="Internal" default="`${isBlockUsed(&quot;srss[0].clock[0].pumpclk[0]&quot;)}`" visible="false" editable="false" desc="Pump clock enabling state" />
46    <ParamBool id="hasCTB" name="hasCTB" group="Internal" default="`${hasBlock(&quot;pass[0].ctb[0].oa[0]&quot;)}`" visible="false" editable="false" desc="Check whether device has CTBs" />
47
48    <ParamChoice id="clock" name="Pump Clock Source" group="General" default="CY_CTB_CLK_PUMP_SRSS" visible="`${hasCTB}`" editable="true" desc="Select the clock source for the opamp pump clock." >
49      <Entry name="CLK_PUMP" value="CY_CTB_CLK_PUMP_SRSS" visible="true" />
50      <Entry name="Peri Clock Divider" value="CY_CTB_CLK_PUMP_PERI" visible="true" />
51      <Entry name="Deep Sleep Clock" value="CY_CTB_CLK_PUMP_DEEPSLEEP" visible="true" />
52    </ParamChoice>
53
54    <ParamSignal name="Peri Clock" port="clock_pump_peri[0]" group="Global Opamp Settings" visible="`${clock eq CY_CTB_CLK_PUMP_PERI}`" desc="Peri divider clock for the pump clock." canBeEmpty="`${clock ne CY_CTB_CLK_PUMP_PERI}`" />
55
56    <ParamString id="sourceClockRsc" name="sourceClockRsc" group="Internal" default="`${clock eq CY_CTB_CLK_PUMP_SRSS ? &quot;srss[0].clock[0].pumpclk[0]&quot; : clock eq CY_CTB_CLK_PUMP_DEEPSLEEP ? &quot;pass[0].dpslp[0]&quot; : getBlockFromSignal(&quot;clock_pump_peri[0]&quot;)}`" visible="false" editable="false" desc="" />
57    <ParamBool id="error" name="Clock Error" group="Internal" default="`${!isBlockUsed(sourceClockRsc)}`" visible="false" editable="false" desc="" />
58    <ParamRange id="frequency" name="Source Frequency" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, &quot;frequency&quot;) : 0}`" min="0" max="26400000" resolution="1" visible="false" editable="false" desc="" />
59    <ParamString id="accuracy" name="accuracy" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, &quot;accuracy&quot;) : 0}`" visible="false" editable="false" desc="" />
60    <ParamString id="sourceFrequencyInfo" name="Frequency" group="General" default="`${formatFrequency(frequency,accuracy)}`" visible="true" editable="false" desc="Source clock frequency" />
61
62    <!-- Peripheral clock divider connection -->
63    <ParamString id="pclk" name="pclk" group="Internal" default="`${getBlockFromSignal(&quot;clock_pump_peri[0]&quot;)}`" visible="false" editable="false" desc="Connected peripheral clock divider (PCLK)." />
64    <ParamBool id="pclkOk" name="pclkOk" group="Internal" default="`${hasConnection(&quot;clock_pump_peri&quot;, 0) &amp;&amp; isBlockUsed(pclk)}`" visible="false" editable="false" desc="Checks whether there is a PCLK connected and enabled." />
65    <ParamString id="pclkDst" name="pclkDst" group="Internal" default="PCLK_PASS_CLOCK_PUMP_PERI" visible="false" editable="false" desc="Generates PCLK connection define." />
66  </Parameters>
67
68  <DRCs>
69    <DRC type="ERROR" text="Pump clock (CLK_PUMP) resource must be enabled when the Opamp Pump Clock Source is set to SRSS." condition="`${hasCTB &amp;&amp; !isClkPumpEnabled &amp;&amp; clock eq CY_CTB_CLK_PUMP_SRSS}`"  location="srss[0].clock[0].pumpclk[0]">
70        <FixIt action="ENABLE_BLOCK" target="srss[0].clock[0].pumpclk[0]" value="pumpclk-3.0" valid="true" />
71    </DRC>
72  </DRCs>
73
74  <ConfigFirmware>
75      <ConfigInclude value="cy_ctb.h" include="true" />
76      <ConfigInclude value="cy_sysclk.h" include="`${pclkOk}`" />
77      <ConfigInstruction value="Cy_CTB_SetPumpClkSource(PASS, `${clock}`);" include="true" />
78      <ConfigInstruction value="Cy_SysClk_PeriphAssignDivider(`${pclkDst}`, `${getExposedMember(pclk, &quot;clockSel&quot;)}`);" include="`${clock eq CY_CTB_CLK_PUMP_PERI &amp;&amp; pclkOk}`" />
79  </ConfigFirmware>
80</Personality>
81