1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file pll400m.cypersonality 6* \version 1.0 7* 8* \brief 9* PLL400M personality description file.It supports only CAT1C devices. 10* 11******************************************************************************** 12* \copyright 13* Copyright 2021-2022 Cypress Semiconductor Corporation 14* SPDX-License-Identifier: Apache-2.0 15* 16* Licensed under the Apache License, Version 2.0 (the "License"); 17* you may not use this file except in compliance with the License. 18* You may obtain a copy of the License at 19* 20* http://www.apache.org/licenses/LICENSE-2.0 21* 22* Unless required by applicable law or agreed to in writing, software 23* distributed under the License is distributed on an "AS IS" BASIS, 24* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25* See the License for the specific language governing permissions and 26* limitations under the License. 27*****************************************************************************--> 28 29<Personality id="mxs40pll400" name="PLL400" version="1.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 30 <Dependencies> 31 <IpBlock name="mxs40srss_ver3,mxs40srss_ver2" /> 32 <Resource name="srss\.clock\.pll400m" /> 33 </Dependencies> 34 <ExposedMembers> 35 <ExposedMember key="frequency" paramId="frequencyDisplay" /> 36 <ExposedMember key="accuracy" paramId="accuracy" /> 37 <ExposedMember key="error" paramId="error" /> 38 </ExposedMembers> 39 <Parameters> 40 <!-- PDL documentation --> 41 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__sysclk__pll.html" linkText="Open PLL Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 42 43 <!-- PLL source clock and max device frequency --> 44 <ParamRange id="clockInst" name="PLL Instance" group="Internal" default="`${getInstNumber("pll400m")}`" min="0" max="`${NUM_PLL400M -1}`" resolution="1" visible="false" editable="false" desc="" /> 45 <ParamString id="sourceClockRsc" name="Source Clock" group="Internal" default="srss[0].clock[0].pathmux[`${clockInst+1}`]" visible="false" editable="false" desc="" /> 46 <ParamBool id="srcNotUsed" name="Clock Source Enabled" group="Internal" default="`${!isBlockUsed(sourceClockRsc)}`" visible="false" editable="false" desc="" /> 47 <ParamBool id="srcError" name="Source Error" group="Internal" default="`${srcNotUsed || getExposedMember(sourceClockRsc, "error")}`" visible="false" editable="false" desc="" /> 48 <ParamRange id="sourceFrequencyActual" name="Source Frequency" group="Internal" default="`${srcError ? 0 : getExposedMember(sourceClockRsc, "frequency")}`" min="0" max="100000000" resolution="1" visible="false" editable="false" desc="" /> 49 <ParamString id="accuracy" name="accuracy" group="Internal" default="`${!srcError ? getExposedMember(sourceClockRsc, "accuracy") : 0}`" visible="false" editable="false" desc="" /> 50 51 <ParamString id="sourceFrequencyInfo" name="Source Frequency" group="General" default="`${formatFrequency(sourceFrequencyActual,accuracy)}`" visible="true" editable="false" desc="Source clock frequency" /> 52 <!-- For ULP mode, Fpll_max = 50 MHz --> 53 <ParamBool id="usingUlp" name="usingUlp" group="Internal" default="`${isBlockUsed("srss[0].power[0]") && getExposedMember("srss[0].power[0]", "usingUlp")}`" visible="false" editable="false" desc="" /> 54 <ParamString id="maxFrequency" name="maxFrequency" group="Internal" default="`${getDeviceAttr("CPU_MAX_MHZ")}`" visible="false" editable="false" desc="The maximum device frequency" /> 55 56 <ParamBool id="lowFrequencyMode" name="Low Frequency Mode" group="General" default="false" visible="true" editable="false" desc="VCO frequency range selection" /> 57 <ParamChoice id="configuration" name="Configuration" group="General" default="auto" visible="true" editable="true" desc="Choose the automatic or manual PLL tuning"> 58 <Entry name="Automatic" value="auto" visible="true"/> 59 <Entry name="Manual" value="manual" visible="true"/> 60 </ParamChoice> 61 <ParamBool id="manConfig" name="Manual PLL Configuration" group="Internal" default="`${configuration eq manual}`" visible="false" editable="false" desc="" /> 62 <ParamRange id="desiredFrequency" name="Desired Frequency (MHz)" group="General" default="`${maxFrequency > 100 ? 100 : maxFrequency}`" min="25" max="`${maxFrequency}`" resolution="0.001" visible="`${!manConfig}`" editable="true" desc="" /> 63 <ParamChoice id="optimization" name="Optimization" group="General" default="MinPower" visible="`${!manConfig}`" editable="false" desc="The feedback tuning options"> 64 <Entry name="Min Power" value="MinPower" visible="true" /> 65 <Entry name="Min Jitter" value="MinJitter" visible="true" /> 66 </ParamChoice> 67 68 <!-- Set an error if the source clock is not enabled, contains an error or the source frequency is outside the valid range --> 69 <ParamBool id="sourceFrequencyOutRange" name="sourceFrequencyOutRange" group="Internal" default="`${(sourceFrequencyActual < 4000000) || (sourceFrequencyActual > 64000000)}`" visible="false" editable="false" desc="" /> 70 <ParamBool id="error" name="Clock Error" group="Internal" default="`${srcError || sourceFrequencyOutRange}`" visible="false" editable="false" desc="" /> 71 72 <!-- Source Frequency --> 73 <ParamRange id="sourceFrequency" name="sourceFrequency" group="Internal" default="`${!sourceFrequencyOutRange ? sourceFrequencyActual : 4000000}`" min="4000000" max="64000000" resolution="1" visible="false" editable="false" desc="" /> 74 75 <ParamString id="callSolver" name="callSolver" group="Internal" default="`${runTcl("pll_solver-3.0.tcl", sourceFrequency / 1000000.0, desiredFrequency, lowFrequencyMode, optimization eq MinPower)}`" visible="false" editable="false" desc="PLL clock solver" /> 76 <ParamRange id="feedback" name="Feedback (16-200)" group="General" default="`${getTclVar("feedbackDiv", callSolver)}`" min="16" max="200" resolution="1" visible="true" editable="`${manConfig}`" desc="The feedback clock divider" /> 77 <ParamRange id="reference" name="Reference (1-16)" group="General" default="`${getTclVar("referenceDiv", callSolver)}`" min="1" max="16" resolution="1" visible="true" editable="`${manConfig}`" desc="The reference clock divider" /> 78 <ParamRange id="output" name="Output (2-16)" group="General" default="`${getTclVar("outputDiv", callSolver)}`" min="2" max="16" resolution="1" visible="true" editable="`${manConfig}`" desc="The output clock divider" /> 79 <ParamRange id="frac" name="Fraction divider (0-16777215)" group="General" default="`${getTclVar("fracDiv", callSolver)}`" min="0" max="16777215" resolution="1" visible="true" editable="`${manConfig}`" desc="The fractional clock divider." /> 80 <ParamBool id="fracDitherEn" name="Fraction Dither" group="General" default="`${configuration eq manual}`" visible="true" editable="`${configuration eq manual}`" desc="Enables dithering during fractional operation." /> 81 <ParamBool id="fracEn" name="Fraction Enable" group="General" default="`${!(configuration eq manual)}`" visible="true" editable="`${configuration eq manual}`" desc="Enables fractional division mode." /> 82 <ParamRange id="frequency" name="Frequency" group="Internal" default="`${(sourceFrequency * ( (feedback << 24) + frac) / (reference * output)) >> 24}`" min="25000000" max="400000000" resolution="1" visible="false" editable="false" desc="" /> 83 <ParamRange id="frequencyDisplay" name="Display Frequency" group="Internal" default="`${(sourceFrequencyActual eq 0) ? sourceFrequencyActual : frequency}`" min="0" max="400000000" resolution="1" visible="false" editable="false" desc="" /> 84 <ParamString id="frequencyInfo" name="Actual Frequency" group="General" default="`${formatFrequency(!error ? frequency : 0,accuracy)}`" visible="true" editable="false" desc="The calculated resulting PLL output frequency" /> 85 86 <!-- Manual DRC verify params --> 87 <ParamRange id="pfdFreq" name="PFD Frequency" group="internal" default="`${sourceFrequency / reference / 1000000.0}`" min="0" max="10000" resolution="0.001" visible="false" editable="false" desc="" /> 88 89 </Parameters> 90 <DRCs> 91 <DRC type="ERROR" text="The Source clock for PLL400M `${clockInst}` has a error. Fix the source error." condition="`${srcError}`" /> 92 <DRC type="ERROR" text="The desired PLL frequency `${desiredFrequency}` MHz is higher than the maximum operating frequency `${maxFrequency}` MHz of the device" condition="`${!usingUlp && desiredFrequency > maxFrequency}`" paramId="desiredFrequency" /> 93 <DRC type="ERROR" text="The desired PLL frequency `${desiredFrequency}` MHz exceeds the maximum of 50 MHz when the ULP mode is used" condition="`${usingUlp && desiredFrequency > 50}`" paramId="desiredFrequency" /> 94 <DRC type="ERROR" text="Source clock for PLL is outside the valid range of 4 MHz - 64 MHz" condition="`${!srcError && sourceFrequencyOutRange}`" paramId="sourceFrequencyInfo"/> 95 <!-- Manual mode DRCs --> 96 <DRC type="ERROR" text="PFD reference frequency out of range. PFD reference frequency (sourceFrequency / Reference) of `${pfdFreq}` MHz is outside valid range of 4 MHz - 8 MHz" condition="`${manConfig && (pfdFreq < 4 || pfdFreq > 8)}`" /> 97 98 </DRCs> 99 <ConfigFirmware> 100 <ConfigInclude value="cy_sysclk.h" include="true" /> 101 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_ENABLED" value="1" public="false" include="true" /> 102 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_FEEDBACK_DIV" value="`${feedback}`" public="false" include="true" /> 103 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_REFERENCE_DIV" value="`${reference}`" public="false" include="true" /> 104 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_OUTPUT_DIV" value="`${output}`" public="false" include="true" /> 105 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_FRAC_DIV" value="`${frac}`" public="false" include="true" /> 106 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_FRAC_DITHER_EN" value="`${fracDitherEn}`" public="false" include="true" /> 107 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_FRAC_EN" value="`${fracEn}`" public="false" include="true" /> 108 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_LF_MODE" value="`${lowFrequencyMode}`" public="false" include="true" /> 109 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_OUTPUT_MODE" value="CY_SYSCLK_FLLPLL_OUTPUT_AUTO" public="false" include="true" /> 110 <ConfigDefine name="CY_CFG_SYSCLK_PLL`${clockInst}`_OUTPUT_FREQ" value="`${frequency}`" public="false" include="true" /> 111 <ConfigStruct name="`${INST_NAME . "_pllConfig"}`" type="cy_stc_pll_manual_config_t" const="true" public="false" include="true" > 112 <Member name="feedbackDiv" value="`${feedback}`" /> 113 <Member name="referenceDiv" value="`${reference}`" /> 114 <Member name="outputDiv" value="`${output}`" /> 115 <Member name="lfMode" value="`${lowFrequencyMode}`" /> 116 <Member name="outputMode" value="CY_SYSCLK_FLLPLL_OUTPUT_AUTO" /> 117 <Member name="fracDiv" value="`${frac}`" /> 118 <Member name="fracDitherEn" value="`${fracDitherEn}`" /> 119 <Member name="fracEn" value="`${fracEn}`" /> 120 </ConfigStruct> 121 <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_Pll`${clockInst}`Init()" body=" Cy_SysClk_PllDisable(SRSS_PLL_400M_`${clockInst}`_PATH_NUM);

 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(SRSS_PLL_400M_`${clockInst}`_PATH_NUM, &`${INST_NAME}`_pllConfig))
 {
 cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
 }
 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_PLL_400M_`${clockInst}`_PATH_NUM, 10000u))
 {
 cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
 }" public="false" include="true" /> 122 </ConfigFirmware> 123</Personality> 124
