1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file hfclk.cypersonality 6* \version 4.0 7* 8* \brief 9* CLK_HF personality description file. Supports CAT1D Device family. 10* 11******************************************************************************** 12* \copyright 13* Copyright 2022 Cypress Semiconductor Corporation 14* SPDX-License-Identifier: Apache-2.0 15* 16* Licensed under the Apache License, Version 2.0 (the "License"); 17* you may not use this file except in compliance with the License. 18* You may obtain a copy of the License at 19* 20* http://www.apache.org/licenses/LICENSE-2.0 21* 22* Unless required by applicable law or agreed to in writing, software 23* distributed under the License is distributed on an "AS IS" BASIS, 24* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25* See the License for the specific language governing permissions and 26* limitations under the License. 27*****************************************************************************--> 28 29<Personality id="hfclk_v2" name="CLK_HF" version="1.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 30 <Dependencies> 31 <IpBlock name="mxs22srss" /> 32 <Resource name="srss\.clock\.hfclk" /> 33 </Dependencies> 34 <ExposedMembers> 35 <ExposedMember key="frequency" paramId="frequency" /> 36 <ExposedMember key="accuracy" paramId="accuracy" /> 37 <ExposedMember key="error" paramId="error" /> 38 <ExposedMember key="clockInst" paramId="clockInst" /> 39 <ExposedMember key="sourceClockDisplayName" paramId="sourceClockDisplayName" /> 40 </ExposedMembers> 41 <Parameters> 42 <!-- PDL documentation --> 43 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__sysclk__clk__hf.html" linkText="Open High-Frequency Clocks Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 44 45 <ParamBool 46 id="is22srssAvailable" name="is22srssAvailable" group="" 47 default="`${("mxs22srss" eq getIpBlockName())}`" visible="false" editable="false" desc="" /> 48 49 <ParamRange id="clockInst" name="clockInst" group="Internal" default="`${getInstNumber("hfclk")}`" min="0" max="`${NUM_HFROOT-1}`" resolution="1" visible="false" editable="false" desc="" /> 50 <ParamChoice id="sourceClockNumber" name="Source Clock" group="General" default="0" visible="true" editable="true" desc="The clock source for CLK_HF`${clockInst}`"> 51 <Entry name="CLK_PATH0" value="0" visible="`${NUM_CLKPATH >= 1}`"/> 52 <Entry name="CLK_PATH1" value="1" visible="`${NUM_CLKPATH >= 2}`"/> 53 <Entry name="CLK_PATH2" value="2" visible="`${NUM_CLKPATH >= 3}`"/> 54 <Entry name="CLK_PATH3" value="3" visible="`${NUM_CLKPATH >= 4}`"/> 55 <Entry name="CLK_PATH4" value="4" visible="`${NUM_CLKPATH >= 5}`"/> 56 <Entry name="CLK_PATH5" value="5" visible="`${NUM_CLKPATH >= 6}`"/> 57 <Entry name="CLK_PATH6" value="6" visible="`${NUM_CLKPATH >= 7}`"/> 58 <Entry name="CLK_PATH7" value="7" visible="`${NUM_CLKPATH >= 8}`"/> 59 <Entry name="CLK_PATH8" value="8" visible="`${NUM_CLKPATH >= 9}`"/> 60 <Entry name="CLK_PATH9" value="9" visible="`${NUM_CLKPATH >= 10}`"/> 61 <Entry name="CLK_PATH10" value="10" visible="`${NUM_CLKPATH >= 11}`"/> 62 <Entry name="CLK_PATH11" value="11" visible="`${NUM_CLKPATH >= 12}`"/> 63 <Entry name="CLK_PATH12" value="12" visible="`${NUM_CLKPATH >= 13}`"/> 64 <Entry name="CLK_PATH13" value="13" visible="`${NUM_CLKPATH >= 14}`"/> 65 <Entry name="CLK_PATH14" value="14" visible="`${NUM_CLKPATH >= 15}`"/> 66 <Entry name="CLK_PATH15" value="15" visible="`${NUM_CLKPATH >= 16}`"/> 67 </ParamChoice> 68 69 <!-- If the FLL/PLL are enabled, their output drive the corresponding clock path --> 70 <ParamBool id="isPll250mUsed" name="Is PLL-250MHz Used" group="Internal" default="`${(sourceClockNumber < NUM_DPLL_LP) && isBlockUsed("srss[0].clock[0].pll250m[" . (sourceClockNumber) . "]")}`" visible="false" editable="false" desc="" /> 71 <ParamBool id="isPll500mUsed" name="Is PLL-500MHz Used" group="Internal" default="`${(sourceClockNumber eq NUM_DPLL_LP) && isBlockUsed("srss[0].clock[0].pll500m[" . (sourceClockNumber - (NUM_DPLL_LP)) . "]")}`" visible="false" editable="false" desc="" /> 72 73 <ParamString id="sourceClock" name="Source clock resource" group="Internal" default="`${isPll250mUsed ? "pll250m[" . (sourceClockNumber) . "]" : 74 (sourceClockNumber eq NUM_DPLL_LP) ? isPll500mUsed ? "pll500m[" . (sourceClockNumber - (NUM_DPLL_LP)) . "]" : 75 "pathmux[" . sourceClockNumber . "]" : 76 "pathmux[" . sourceClockNumber . "]"}`" visible="false" editable="false" desc="" /> 77 <ParamString id="sourceClockDisplayName" name="Source Clock Display Name" group="Internal" default="`${getParamValueDisplay("sourceClock")}`" visible="false" editable="false" desc="" /> 78 79 <ParamString id="sourceClockRsc" name="Source Clock" group="Internal" default="srss[0].clock[0].`${sourceClock}`" visible="false" editable="false" desc="" /> 80 81 <!-- Set an error if the source clock is not enabled or contains an error --> 82 <ParamBool id="srcNotUsed" name="Clock Source Enabled" group="Internal" default="`${!isBlockUsed(sourceClockRsc)}`" visible="false" editable="false" desc="" /> 83 <ParamBool id="error" name="Clock Error" group="Internal" default="`${srcNotUsed || getExposedMember(sourceClockRsc, "error")}`" visible="false" editable="false" desc="" /> 84 <ParamRange id="sourceFreq" name="sourceFrequency" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, "frequency") : 0}`" min="0" max="400000000" resolution="0.001" visible="false" editable="false" desc="" /> 85 <ParamString id="accuracy" name="accuracy" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, "accuracy") : 0}`" visible="false" editable="false" desc="" /> 86 <ParamString id="sourceFrequencyInfo" name="Source Frequency" group="General" default="`${formatFrequency(sourceFreq,accuracy)}`" visible="true" editable="false" desc="Source clock frequency" /> 87 88 89 <ParamChoice id="divider" name="Divider" group="General" default="1" visible="true" editable="true" desc="The source clock frequency divider"> 90 <Entry name="1" value="1" visible="true"/> 91 <Entry name="2" value="2" visible="true"/> 92 <Entry name="3" value="3" visible="true"/> 93 <Entry name="4" value="4" visible="true"/> 94 <Entry name="5" value="5" visible="true"/> 95 <Entry name="6" value="6" visible="true"/> 96 <Entry name="7" value="7" visible="true"/> 97 <Entry name="8" value="8" visible="true"/> 98 <Entry name="9" value="9" visible="true"/> 99 <Entry name="10" value="10" visible="true"/> 100 <Entry name="11" value="11" visible="true"/> 101 <Entry name="12" value="12" visible="true"/> 102 <Entry name="13" value="13" visible="true"/> 103 <Entry name="14" value="14" visible="true"/> 104 <Entry name="15" value="15" visible="true"/> 105 <Entry name="16" value="16" visible="true"/> 106 </ParamChoice> 107 <ParamRange id="frequency" name="Frequency" group="Internal" default="`${sourceFreq / divider}`" min="0" max="400000000" resolution="1" visible="false" editable="false" desc="" /> 108 <!-- If the frequency is less than one MHz, display its value in kHz --> 109 <ParamString id="frequencyInfo" name="Frequency" group="General" default="`${formatFrequency(frequency,accuracy)}`" visible="true" editable="false" desc="The resulting CLK_HF`${clockInst}` output clock frequency" /> 110 <ParamSignal port="root_clk[0]" name="Clock Output" group="General" visible="`${hasVisibleOption("root_clk[0]")}`" desc="A high-frequency clock output driving specific peripherals" canBeEmpty="true" > 111 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 112 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 113 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 114 </Parameter> 115 </Constraint> 116 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 117 <Parameter id="DriveModes" severity="WARNING" reason=""> 118 <Choice> 119 <Option value="CY_GPIO_DM_STRONG_IN_OFF"/> 120 <Option value="CY_GPIO_DM_STRONG"/> 121 <Option value="CY_GPIO_DM_OD_DRIVESLOW_IN_OFF"/> 122 <Option value="CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF"/> 123 <Option value="CY_GPIO_DM_OD_DRIVESLOW"/> 124 <Option value="CY_GPIO_DM_OD_DRIVESHIGH"/> 125 <Option value="CY_GPIO_DM_PULLUP_IN_OFF"/> 126 <Option value="CY_GPIO_DM_PULLDOWN_IN_OFF"/> 127 <Option value="CY_GPIO_DM_PULLUP_DOWN_IN_OFF"/> 128 <Option value="CY_GPIO_DM_PULLUP"/> 129 <Option value="CY_GPIO_DM_PULLDOWN"/> 130 <Option value="CY_GPIO_DM_PULLUP_DOWN"/> 131 </Choice> 132 </Parameter> 133 </Constraint> 134 <!--Constraint type="REQUIRE" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 135 <Parameter id="DriveModes" severity="ERROR" reason=""> 136 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 137 </Parameter> 138 </Constraint--> 139 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 140 </ParamSignal> 141 </Parameters> 142 <DRCs> 143 <DRC type="ERROR" text="Source clock for CLK_HF`${clockInst}` is not enabled" condition="`${srcNotUsed}`" > 144 <FixIt action="ENABLE_BLOCK" target="`${sourceClockRsc}`" value="" valid="true" /> 145 </DRC> 146 <DRC type="ERROR" text="CLK_HF0 is slower than legal min 200 kHz." condition="`${!error && ((clockInst == 0) && (sourceFreq < 200000))}`" /> 147 <DRC type="ERROR" text="CLK_HF0 is greater than legal max 200 MHz." condition="`${!error && ((clockInst == 0) && (frequency > 200000000)) && is22srssAvailable}`" /> 148 <DRC type="INFO" text="The top-level System Clocks must be enabled to generate the clock initialization code" condition="`${!isBlockUsed("srss[0].clock[0]") && clockInst == 0}`" location="srss[0].clock[0]" > 149 <FixIt action="ENABLE_BLOCK" target="srss[0].clock[0]" value="" valid="true" /> 150 </DRC> 151 <!--DRC type="ERROR" text="Only one connection between the clock system and GPIO pins is possible, either EXTCLK or CLK_HF4." condition="`${hasConnection("root_clk", 0) && isBlockUsed("srss[0].clock[0].ext[0]")}`" /--> 152 </DRCs> 153 <ConfigFirmware> 154 <ConfigInclude value="cy_sysclk.h" include="true" /> 155 <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`_ENABLED" public="false" value="1" include="true" /> 156 <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`_DIVIDER" public="false" value="CY_SYSCLK_CLKHF_`${divider == 1 ? "NO_DIVIDE" : (("DIVIDE_BY_") . divider)}`" include="true" /> 157 <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`" public="true" value="`${clockInst}`UL" include="true" /> 158 <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`_FREQ_MHZ" public="false" value="`${frequency / 1000000}`UL" include="true" /> 159 <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`_CLKPATH" public="false" value="CY_SYSCLK_CLKHF_IN_CLKPATH`${sourceClockNumber}`" include="true" /> 160 <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`_CLKPATH_NUM" public="true" value="`${sourceClockNumber}`UL" include="true" /> 161 <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_ClkHf`${clockInst}`Init()" body=" Cy_SysClk_ClkHfSetDivider(`${clockInst}`U, CY_SYSCLK_CLKHF_`${divider == 1 ? "NO_DIVIDE" : (("DIVIDE_BY_") . divider)}`);
 Cy_SysClk_ClkHfSetSource(`${clockInst}`U, CY_CFG_SYSCLK_CLKHF`${clockInst}`_CLKPATH);" public="false" include="`${clockInst eq 0}`" guard="defined(CORE_NAME_CM33_0)"/> 162 <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_ClkHf`${clockInst}`Init()" body=" Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF`${clockInst}`, CY_CFG_SYSCLK_CLKHF`${clockInst}`_CLKPATH);
 Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF`${clockInst}`, CY_SYSCLK_CLKHF_`${divider == 1 ? "NO_DIVIDE" : (("DIVIDE_BY_") . divider)}`);
 Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF`${clockInst}`);" public="false" include="`${clockInst gt 0}`" guard="defined(CORE_NAME_CM33_0)" /> 163 </ConfigFirmware> 164</Personality> 165
