1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file hfclk.cypersonality 6* \version 3.0 7* 8* \brief 9* CLK_HF personality description file. It Supports CAT1A, CAT1B and CAT1C family of devices. 10* 11******************************************************************************** 12* \copyright 13* Copyright 2022 Cypress Semiconductor Corporation 14* SPDX-License-Identifier: Apache-2.0 15* 16* Licensed under the Apache License, Version 2.0 (the "License"); 17* you may not use this file except in compliance with the License. 18* You may obtain a copy of the License at 19* 20* http://www.apache.org/licenses/LICENSE-2.0 21* 22* Unless required by applicable law or agreed to in writing, software 23* distributed under the License is distributed on an "AS IS" BASIS, 24* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 25* See the License for the specific language governing permissions and 26* limitations under the License. 27*****************************************************************************--> 28 29<Personality id="hfclk" name="CLK_HF" version="3.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 30 <Dependencies> 31 <IpBlock name="mxs40srss,mxs40ssrss,mxs40srss_ver3,mxs40srss_ver2" /> 32 <Resource name="srss\.clock\.hfclk" /> 33 </Dependencies> 34 <ExposedMembers> 35 <ExposedMember key="frequency" paramId="frequency" /> 36 <ExposedMember key="accuracy" paramId="accuracy" /> 37 <ExposedMember key="error" paramId="error" /> 38 <ExposedMember key="clockInst" paramId="clockInst" /> 39 <ExposedMember key="sourceClockDisplayName" paramId="sourceClockDisplayName" /> 40 </ExposedMembers> 41 <Parameters> 42 <!-- PDL documentation --> 43 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__sysclk__clk__hf.html" linkText="Open High-Frequency Clocks Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 44 45 <ParamRange id="clockInst" name="clockInst" group="Internal" default="`${getInstNumber("hfclk")}`" min="0" max="`${NUM_HFROOT-1}`" resolution="1" visible="false" editable="false" desc="" /> 46 <ParamChoice id="sourceClockNumber" name="Source Clock" group="General" default="0" visible="true" editable="true" desc="The clock source for CLK_HF`${clockInst}`"> 47 <Entry name="CLK_PATH0" value="0" visible="`${NUM_CLKPATH >= 1}`"/> 48 <Entry name="CLK_PATH1" value="1" visible="`${NUM_CLKPATH >= 2}`"/> 49 <Entry name="CLK_PATH2" value="2" visible="`${NUM_CLKPATH >= 3}`"/> 50 <Entry name="CLK_PATH3" value="3" visible="`${NUM_CLKPATH >= 4}`"/> 51 <Entry name="CLK_PATH4" value="4" visible="`${NUM_CLKPATH >= 5}`"/> 52 <Entry name="CLK_PATH5" value="5" visible="`${NUM_CLKPATH >= 6}`"/> 53 <Entry name="CLK_PATH6" value="6" visible="`${NUM_CLKPATH >= 7}`"/> 54 <Entry name="CLK_PATH7" value="7" visible="`${NUM_CLKPATH >= 8}`"/> 55 <Entry name="CLK_PATH8" value="8" visible="`${NUM_CLKPATH >= 9}`"/> 56 <Entry name="CLK_PATH9" value="9" visible="`${NUM_CLKPATH >= 10}`"/> 57 <Entry name="CLK_PATH10" value="10" visible="`${NUM_CLKPATH >= 11}`"/> 58 <Entry name="CLK_PATH11" value="11" visible="`${NUM_CLKPATH >= 12}`"/> 59 <Entry name="CLK_PATH12" value="12" visible="`${NUM_CLKPATH >= 13}`"/> 60 <Entry name="CLK_PATH13" value="13" visible="`${NUM_CLKPATH >= 14}`"/> 61 <Entry name="CLK_PATH14" value="14" visible="`${NUM_CLKPATH >= 15}`"/> 62 <Entry name="CLK_PATH15" value="15" visible="`${NUM_CLKPATH >= 16}`"/> 63 </ParamChoice> 64 65 <!-- If the FLL/PLL are enabled, their output drive the corresponding clock path --> 66 67 <ParamBool id="is40srss_ver3Available" name="is40srss_ver3Available" group="" default="`${("mxs40srss_ver3" eq getIpBlockName())}`" visible="false" editable="false" desc="" /> 68 69 <ParamBool id="is40srss_ver2or3Available" name="is40srss_ver2or3Available" group="" default="`${(("mxs40srss_ver2" eq getIpBlockName()) || ("mxs40srss_ver3" eq getIpBlockName()))}`" visible="false" editable="false" desc="" /> 70 71 <ParamRange id="numPll400M" name="NUM_PLL400M_ALL" group="Internal" desc="Variable that can be used for all categories" editable="false" 72 default="`${lookupExpression("NUM_PLL400M", 0)}`" min="0" max="14" resolution="1" visible="false" /> 73 74 <ParamRange id="numTotalPll" name="NUM_TOTAL_PLL_ALL" group="Internal" desc="Variable that can be used for all categories" editable="false" 75 default="`${lookupExpression("NUM_TOTAL_PLL", lookupExpression("NUM_PLL") + numPll400M)}`" min="0" max="29" resolution="1" visible="false" /> 76 77 <ParamBool id="isFllUsed" name="Is FLL Used" group="Internal" default="`${(sourceClockNumber eq 0) && isBlockUsed("srss[0].clock[0].fll[0]")}`" visible="false" editable="false" desc="" /> 78 79 <ParamBool id="isPll400mUsed" name="Is PLL-400MHz Used" group="Internal" 80 default="`${(("mxs40srss_ver3" eq getIpBlockName())) && ((sourceClockNumber > 0) && (sourceClockNumber <= NUM_PLL400M) && 81 isBlockUsed("srss[0].clock[0].pll400m[" . (sourceClockNumber-1) . "]"))}`" visible="false" editable="false" desc="" /> 82 83 <ParamBool id="isPllUsed" name="Is PLL Used" group="Internal" 84 default="`${ ("mxs40ssrss" eq getIpBlockName()) ? 0 : 85 (sourceClockNumber > numPll400M) && (sourceClockNumber <= numTotalPll) && 86 isBlockUsed("srss[0].clock[0].pll[" . (sourceClockNumber - 1 - numPll400M) . "]") }`" 87 visible="false" editable="false" desc="" /> 88 89 <ParamBool id="isPll250mUsed" name="Is PLL-250MHz Used" group="Internal" default="`${("mxs40ssrss" eq getIpBlockName()) ? (NUM_TOTAL_PLL ne 0 ? ((sourceClockNumber ne 0 && sourceClockNumber <= NUM_DPLL250) && isBlockUsed("srss[0].clock[0].dpll250[" . (sourceClockNumber - 1 ) . "]")) : false) : false}`" visible="false" editable="false" desc="" /> 90 91 <!-- 92 The clock paths are always arranged in this order: [FLL] [PLL400s/DPLL250s] [PLLs] 93 - FLL clock path indexing will always be just the sourceClockNumber, which will always be zero. Only one FLL is supported here. 94 - PLL400 indexing always comes after FLL, so just needs to subtract 1 for the FLL. 95 - PLL indexing needs to subtract 1 for FLL, and then also subtract the number of PLL400s that may be in front of the PLL clock paths (for devices with PLL but no PLL400, this will subtract zero.) 96 - PLL250 indexing always comes after the FLL, so just needs to subtract 1 for the FLL. 97 As written, sourceClock indexing does not support the combination of PLL250 and PLL400. Update indexing below if a new device requires this combination. 98 --> 99 <ParamString id="sourceClock" name="Source clock resource" group="Internal" default="`${isFllUsed ? "fll[0]" : 100 isPll400mUsed ? "pll400m[" . (sourceClockNumber-1) . "]" : 101 isPllUsed ? "pll[" . (sourceClockNumber - 1 - numPll400M) . "]" : 102 isPll250mUsed && ("mxs40ssrss" eq getIpBlockName()) ? "dpll250[" . (sourceClockNumber-1) . "]" : 103 "pathmux[" . sourceClockNumber . "]"}`" visible="false" editable="false" desc="" /> 104 <ParamString id="sourceClockDisplayName" name="Source Clock Display Name" group="Internal" default="`${getParamValueDisplay("sourceClock")}`" visible="false" editable="false" desc="" /> 105 <ParamString id="sourceClockRsc" name="Source Clock" group="Internal" default="srss[0].clock[0].`${sourceClock}`" visible="false" editable="false" desc="" /> 106 107 <!-- Set an error if the source clock is not enabled or contains an error --> 108 <ParamBool id="srcNotUsed" name="Clock Source Enabled" group="Internal" default="`${!isBlockUsed(sourceClockRsc)}`" visible="false" editable="false" desc="" /> 109 <ParamBool id="error" name="Clock Error" group="Internal" default="`${srcNotUsed || getExposedMember(sourceClockRsc, "error")}`" visible="false" editable="false" desc="" /> 110 <ParamRange id="sourceFreq" name="sourceFrequency" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, "frequency") : 0}`" min="0" max="400000000" resolution="0.001" visible="false" editable="false" desc="" /> 111 <ParamString id="accuracy" name="accuracy" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, "accuracy") : 0}`" visible="false" editable="false" desc="" /> 112 <ParamString id="sourceFrequencyInfo" name="Source Frequency" group="General" default="`${formatFrequency(sourceFreq,accuracy)}`" visible="true" editable="false" desc="Source clock frequency" /> 113 114 115 <ParamChoice id="divider" name="Divider" group="General" default="1" visible="true" editable="true" desc="The source clock frequency divider"> 116 <Entry name="1" value="1" visible="true"/> 117 <Entry name="2" value="2" visible="true"/> 118 <Entry name="3" value="3" visible="`${("mxs40ssrss" eq getIpBlockName()) ? (NUM_TOTAL_PLL ne 0 ? true : false) : false}`"/> 119 <Entry name="4" value="4" visible="true"/> 120 <Entry name="5" value="5" visible="`${("mxs40ssrss" eq getIpBlockName()) ? (NUM_TOTAL_PLL ne 0 ? true : false) : false}`"/> 121 <Entry name="6" value="6" visible="`${("mxs40ssrss" eq getIpBlockName()) ? (NUM_TOTAL_PLL ne 0 ? true : false) : false}`"/> 122 <Entry name="7" value="7" visible="`${("mxs40ssrss" eq getIpBlockName()) ? (NUM_TOTAL_PLL ne 0 ? true : false) : false}`"/> 123 <Entry name="8" value="8" visible="true"/> 124 <Entry name="9" value="9" visible="`${("mxs40ssrss" eq getIpBlockName()) ? (NUM_TOTAL_PLL ne 0 ? true : false) : false}`"/> 125 <Entry name="10" value="10" visible="`${("mxs40ssrss" eq getIpBlockName()) ? (NUM_TOTAL_PLL ne 0 ? true : false) : false}`"/> 126 <Entry name="11" value="11" visible="`${("mxs40ssrss" eq getIpBlockName()) ? (NUM_TOTAL_PLL ne 0 ? true : false) : false}`"/> 127 <Entry name="12" value="12" visible="`${("mxs40ssrss" eq getIpBlockName()) ? (NUM_TOTAL_PLL ne 0 ? true : false) : false}`"/> 128 <Entry name="13" value="13" visible="`${("mxs40ssrss" eq getIpBlockName()) ? (NUM_TOTAL_PLL ne 0 ? true : false) : false}`"/> 129 <Entry name="14" value="14" visible="`${("mxs40ssrss" eq getIpBlockName()) ? (NUM_TOTAL_PLL ne 0 ? true : false) : false}`"/> 130 <Entry name="15" value="15" visible="`${("mxs40ssrss" eq getIpBlockName()) ? (NUM_TOTAL_PLL ne 0 ? true : false) : false}`"/> 131 <Entry name="16" value="16" visible="`${("mxs40ssrss" eq getIpBlockName()) ? (NUM_TOTAL_PLL ne 0 ? true : false) : false}`"/> 132 </ParamChoice> 133 <ParamRange id="frequency" name="Frequency" group="Internal" default="`${sourceFreq / divider}`" min="0" max="400000000" resolution="1" visible="false" editable="false" desc="" /> 134 <!-- If the frequency is less than one MHz, display its value in kHz --> 135 <ParamString id="frequencyInfo" name="Frequency" group="General" default="`${formatFrequency(frequency,accuracy)}`" visible="true" editable="false" desc="The resulting CLK_HF`${clockInst}` output clock frequency" /> 136 <ParamSignal port="root_clk[0]" name="Clock Output" group="General" visible="`${hasVisibleOption("root_clk[0]")}`" desc="A high-frequency clock output driving specific peripherals" canBeEmpty="true" > 137 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 138 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 139 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 140 </Parameter> 141 </Constraint> 142 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 143 <Parameter id="DriveModes" severity="WARNING" reason=""> 144 <Choice> 145 <Option value="CY_GPIO_DM_STRONG_IN_OFF"/> 146 <Option value="CY_GPIO_DM_STRONG"/> 147 <Option value="CY_GPIO_DM_OD_DRIVESLOW_IN_OFF"/> 148 <Option value="CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF"/> 149 <Option value="CY_GPIO_DM_OD_DRIVESLOW"/> 150 <Option value="CY_GPIO_DM_OD_DRIVESHIGH"/> 151 <Option value="CY_GPIO_DM_PULLUP_IN_OFF"/> 152 <Option value="CY_GPIO_DM_PULLDOWN_IN_OFF"/> 153 <Option value="CY_GPIO_DM_PULLUP_DOWN_IN_OFF"/> 154 <Option value="CY_GPIO_DM_PULLUP"/> 155 <Option value="CY_GPIO_DM_PULLDOWN"/> 156 <Option value="CY_GPIO_DM_PULLUP_DOWN"/> 157 </Choice> 158 </Parameter> 159 </Constraint> 160 <!--Constraint type="REQUIRE" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 161 <Parameter id="DriveModes" severity="ERROR" reason=""> 162 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 163 </Parameter> 164 </Constraint--> 165 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 166 </ParamSignal> 167 </Parameters> 168 <DRCs> 169 <DRC type="ERROR" text="Source clock for CLK_HF`${clockInst}` is not enabled" condition="`${srcNotUsed}`" > 170 <FixIt action="ENABLE_BLOCK" target="`${sourceClockRsc}`" value="" valid="true" /> 171 </DRC> 172 <DRC type="ERROR" text="CLK_HF0 is slower than legal min 200 kHz." condition="`${!error && ((clockInst == 0) && (sourceFreq < 200000))}`" /> 173 <DRC type="INFO" text="The top-level System Clocks must be enabled to generate the clock initialization code" condition="`${!isBlockUsed("srss[0].clock[0]") && clockInst == 0}`" location="srss[0].clock[0]" > 174 <FixIt action="ENABLE_BLOCK" target="srss[0].clock[0]" value="" valid="true" /> 175 </DRC> 176 <!-- Generate a DRC from HFCLK0 that prevents IMO from being disabled --> 177 <DRC type="ERROR" text="The IMO cannot be disabled." condition="`${(clockInst eq 0) && !isBlockUsed("srss[0].clock[0].imo[0]")}`" location="srss[0].clock[0]"> 178 <FixIt action="ENABLE_BLOCK" target="srss[0].clock[0].imo[0]" value="" valid="true" /> 179 </DRC> 180 <DRC type="ERROR" text="CLK_HF2 should be equal to 48MHz." condition="`${((clockInst == 2) && (frequency ne 48000000) && ("mxs40ssrss" eq getIpBlockName()) && NUM_TOTAL_PLL eq 0)}`" /> 181 <DRC type="ERROR" text="CLK_HF3 should be less than 24MHz." condition="`${((clockInst == 3) && (frequency > 24000000) && ("mxs40ssrss" eq getIpBlockName()))}`" /> 182 <!--DRC type="ERROR" text="Only one connection between the clock system and GPIO pins is possible, either EXTCLK or CLK_HF4." condition="`${hasConnection("root_clk", 0) && isBlockUsed("srss[0].clock[0].ext[0]")}`" /--> 183 </DRCs> 184 <ConfigFirmware> 185 <ConfigInclude value="cy_sysclk.h" include="true" /> 186 <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`_ENABLED" public="false" value="1" include="true" /> 187 <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`_DIVIDER" public="false" value="CY_SYSCLK_CLKHF_`${divider == 1 ? "NO_DIVIDE" : (("DIVIDE_BY_") . divider)}`" include="true" /> 188 <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`" public="true" value="`${clockInst}`UL" include="true" /> 189 <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`_FREQ_MHZ" public="false" value="`${frequency / 1000000}`UL" include="true" /> 190 <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`_CLKPATH" public="false" value="CY_SYSCLK_CLKHF_IN_CLKPATH`${sourceClockNumber}`" include="true" /> 191 <ConfigDefine name="CY_CFG_SYSCLK_CLKHF`${clockInst}`_CLKPATH_NUM" public="true" value="`${sourceClockNumber}`UL" include="true" /> 192 193 <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_ClkHf`${clockInst}`Init()" body=" Cy_SysClk_ClkHfSetSource(`${clockInst}`U, CY_CFG_SYSCLK_CLKHF`${clockInst}`_CLKPATH);
 Cy_SysClk_ClkHfSetDivider(`${clockInst}`U, CY_SYSCLK_CLKHF_`${divider == 1 ? "NO_DIVIDE" : (("DIVIDE_BY_") . divider)}`);
 Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF`${clockInst}`, false);" public="false" include="`${(is40srss_ver3Available) && (clockInst eq 0)}`" /> 194 195 <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_ClkHf`${clockInst}`Init()" body=" Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF`${clockInst}`, CY_CFG_SYSCLK_CLKHF`${clockInst}`_CLKPATH);
 Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF`${clockInst}`, CY_SYSCLK_CLKHF_`${divider == 1 ? "NO_DIVIDE" : (("DIVIDE_BY_") . divider)}`);
 Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF`${clockInst}`, false);
 Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF`${clockInst}`);" public="false" include="`${(is40srss_ver3Available) && (clockInst gt 0)}`" /> 196 197 <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_ClkHf`${clockInst}`Init()" body=" Cy_SysClk_ClkHfSetSource(`${clockInst}`U, CY_CFG_SYSCLK_CLKHF`${clockInst}`_CLKPATH);
 Cy_SysClk_ClkHfSetDivider(`${clockInst}`U, CY_SYSCLK_CLKHF_`${divider == 1 ? "NO_DIVIDE" : (("DIVIDE_BY_") . divider)}`);" public="false" include="`${!(is40srss_ver3Available) && (clockInst eq 0)}`" guard="(!defined(CY_DEVICE_SECURE))"/> 198 199 <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_ClkHf`${clockInst}`Init()" body=" Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF`${clockInst}`, CY_CFG_SYSCLK_CLKHF`${clockInst}`_CLKPATH);
 Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF`${clockInst}`, CY_SYSCLK_CLKHF_`${divider == 1 ? "NO_DIVIDE" : (("DIVIDE_BY_") . divider)}`);
 Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF`${clockInst}`);" public="false" include="`${!(is40srss_ver3Available) && (clockInst gt 0)}`" guard="(!defined(CY_DEVICE_SECURE))"/> 200 201 </ConfigFirmware> 202</Personality> 203
