1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file fll.cypersonality 6* \version 4.0 7* 8* \brief 9* FLL personality description file. It Supports CAT1A, CAT1B and CAT1C family of devices. 10* 11******************************************************************************** 12* \copyright 13* Copyright (c) 2022, Cypress Semiconductor Corporation (an Infineon company) or 14* an affiliate of Cypress Semiconductor Corporation. 15* SPDX-License-Identifier: Apache-2.0 16* 17* Licensed under the Apache License, Version 2.0 (the "License"); 18* you may not use this file except in compliance with the License. 19* You may obtain a copy of the License at 20* 21* http://www.apache.org/licenses/LICENSE-2.0 22* 23* Unless required by applicable law or agreed to in writing, software 24* distributed under the License is distributed on an "AS IS" BASIS, 25* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26* See the License for the specific language governing permissions and 27* limitations under the License. 28*****************************************************************************--> 29 30<Personality id="fll" name="FLL" version="4.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 31 <Dependencies> 32 <IpBlock name="mxs40srss,mxs40ssrss,mxs40srss_ver3,mxs40srss_ver2" /> 33 <Resource name="srss\.clock\.fll" /> 34 </Dependencies> 35 <ExposedMembers> 36 <ExposedMember key="frequency" paramId="frequency" /> 37 <ExposedMember key="accuracy" paramId="solvedAccuracy" /> 38 <ExposedMember key="error" paramId="srcError" /> 39 </ExposedMembers> 40 <Parameters> 41 <!-- PDL documentation --> 42 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__sysclk__fll.html" linkText="Open FLL Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 43 44 <!-- For LP mode, Ffll_max = 96 MHz or Fcpu_max (if Fcpu_max < 100 MHz) --> 45 <ParamRange id="fllmax" name="Max FLL Frequency" group="Internal" default="`${("mxs40ssrss" eq getIpBlockName()) ? 96 : 100}`" min="96" max="100" resolution="1" visible="false" editable="false" desc="Max FLL Frequency based on platform." /> 46 <ParamBool id="usingUlp" name="usingUlp" group="Internal" default="`${isBlockUsed("srss[0].power[0]") && getExposedMember("srss[0].power[0]", "usingUlp")}`" visible="false" editable="false" desc="" /> 47 <ParamString id="maxFrequency" name="Max Frequency (MHz)" group="Internal" default="`${getDeviceAttr("CPU_MAX_MHZ") > fllmax ? fllmax : getDeviceAttr("CPU_MAX_MHZ")}`" visible="false" editable="false" desc="The maximum FLL frequency" /> 48 <ParamString id="maxFreqHz" name="Max Frequency (Hz)" group="Internal" default="`${1000000 * maxFrequency}`" visible="false" editable="false" desc="The maximum FLL frequency" /> 49 50 <!-- FLL is on clock path 0 --> 51 <ParamString id="sourceClockRsc" name="Source Clock" group="Internal" default="srss[0].clock[0].pathmux[0]" visible="false" editable="false" desc="" /> 52 <ParamBool id="srcNotUsed" name="Clock Source Enabled" group="Internal" default="`${!isBlockUsed(sourceClockRsc)}`" visible="false" editable="false" desc="" /> 53 <!-- Set an error if the source clock is not enabled or contains an error --> 54 <ParamBool id="srcError" name="Source Error" group="Internal" default="`${srcNotUsed || getExposedMember(sourceClockRsc, "error")}`" visible="false" editable="false" desc="" /> 55 <ParamRange id="sourceFrequency" name="Source Frequency" group="Internal" default="`${!srcError ? getExposedMember(sourceClockRsc, "frequency") : 0}`" min="0" max="100000000" resolution="1" visible="false" editable="false" desc="" /> 56 <ParamString id="sourceAccuracy" name="Source Accuracy" group="Internal" default="`${!srcError ? getExposedMember(sourceClockRsc, "accuracy") : 0}`" visible="false" editable="false" desc="" /> 57 <ParamString id="sourceFrequencyInfo" name="Source Frequency" group="General" default="`${formatFrequency(sourceFrequency,sourceAccuracy)}`" visible="true" editable="false" desc="Source clock frequency" /> 58 <ParamChoice id="configuration" name="Configuration" group="General" default="auto" visible="true" editable="true" desc="Choose the automatic or manual FLL tuning"> 59 <Entry name="Automatic" value="auto" visible="true"/> 60 <Entry name="Manual" value="manual" visible="true"/> 61 </ParamChoice> 62 63 <ParamBool id="manConfig" name="Manual FLL Configuration" group="Internal" default="`${configuration eq manual}`" visible="false" editable="false" desc="" /> 64 65 <ParamRange id="desiredFrequency" name="Desired Frequency (MHz)" group="General" default="`${maxFrequency}`" min="24" max="`${maxFrequency}`" resolution="0.001" visible="`${!manConfig}`" editable="true" desc="" /> 66 67 <!-- Use default values in case of error --> 68 69 <!-- The FLL calculator takes into account whether the WCO is used as the reference clock for the FLL. The FLL resides on clock path 0. --> 70 <ParamString id="path0ClkSource" name="Source Clock for Clock Path 0" group="Internal" default="`${!srcError ? getExposedMember(sourceClockRsc, "sourceClock") : false}`" visible="false" editable="false" desc="" /> 71 72 <ParamString id="callSolverAuto" name="callSolver" group="Internal" default="`${manConfig ? "" : runTcl("fll_solver-2.0.tcl", "auto", sourceFrequency / 1000000.0, desiredFrequency, path0ClkSource eq "wco", sourceAccuracy)}`" visible="false" editable="false" desc="FLL clock solver" /> 73 74 <!-- Use min value in case of error --> 75 <ParamRange id="multiplier" name="Multiplier (1-262143)" group="General" default="`${getTclVar("fllMult", callSolverAuto)}`" min="`${srcNotUsed ? 0 : 1}`" max="262143" resolution="1" visible="true" editable="`${manConfig}`" desc="The feedback clock divider" /> 76 <ParamRange id="reference" name="Reference (1-8191)" group="General" default="`${getTclVar("refDiv", callSolverAuto)}`" min="`${srcNotUsed ? 0 : 1}`" max="8191" resolution="1" visible="true" editable="`${manConfig}`" desc="The reference clock divider" /> 77 <ParamRange id="tolerance" name="Lock Tolerance (0-511)" group="General" default="`${getTclVar("lockTolerance", callSolverAuto)}`" min="0" max="511" resolution="1" visible="true" editable="`${manConfig}`" desc="Lock tolerance sets the error threshold for when the FLL output is considered locked to the reference input. A high tolerance can be used to lock more quickly or to track a less accurate source. The tolerance should be set so that the FLL does not unlock under normal conditions. The tolerance is the allowed difference between the count value for the ideal formula and the measured value" /> 78 <ParamBool id="enableOutputDivider" name="Enable FLL output Divider" group="General" default="false" visible="`${manConfig ? "true" : "false"}`" editable="true" desc="Enable FLL output Divider" /> 79 <ParamString id="callSolver" name="callSolver" group="Internal" default="`${manConfig ? runTcl("fll_solver-2.0.tcl" , "manual", sourceFrequency / 1000000.0, multiplier, reference, tolerance, enableOutputDivider, path0ClkSource eq "wco", sourceAccuracy) : callSolverAuto}`" visible="false" editable="false" desc="FLL clock solver" /> 80 81 <ParamRange id="frequency" name="Frequency" group="Internal" default="`${sourceFrequency * multiplier / (srcNotUsed ? 1 : reference) / (getTclVar("enableOutputDiv", callSolver) ? 2 : 1)}`" min="`${srcNotUsed ? 0 : 24000000}`" max="`${maxFreqHz}`" resolution="200000" visible="false" editable="false" desc="" /> 82 <ParamString id="solvedAccuracy" name="accuracy" group="Internal" default="`${getTclVar("accuracy", callSolver)}`" visible="false" editable="false" desc="" /> 83 <ParamString id="frequencyInfo" name="Actual Frequency" group="General" default="`${srcError ? formatFrequency(0,0) : formatFrequency(frequency,solvedAccuracy)}`" visible="true" editable="false" desc="The calculated resulting FLL output frequency" /> 84 </Parameters> 85 <DRCs> 86 <DRC type="ERROR" text="Source clock for FLL is not enabled" condition="`${srcNotUsed}`" > 87 <FixIt action="ENABLE_BLOCK" target="`${sourceClockRsc}`" value="" valid="true" /> 88 </DRC> 89 <DRC type="ERROR" text="Source clock for FLL is outside the valid range of 1 kHz - 100 MHz" condition="`${!srcError && (sourceFrequency < 1000) || (sourceFrequency > 100000000)}`" /> 90 <DRC type="ERROR" text="The desired FLL frequency `${desiredFrequency}` MHz is higher than the maximum operating frequency `${maxFrequency}` MHz of the device" condition="`${!usingUlp && desiredFrequency > maxFrequency}`" paramId="desiredFrequency" /> 91 <DRC type="ERROR" text="The desired FLL frequency `${desiredFrequency}` MHz exceeds the maximum of 50 MHz when the ULP mode is used" condition="`${usingUlp && desiredFrequency > 50}`" paramId="desiredFrequency" /> 92 </DRCs> 93 <ConfigFirmware> 94 <ConfigInclude value="cy_sysclk.h" include="true" /> 95 <ConfigDefine name="CY_CFG_SYSCLK_FLL_ENABLED" value="1" public="false" include="true" /> 96 <ConfigDefine name="CY_CFG_SYSCLK_FLL_MULT" value="`${multiplier}`U" public="false" include="true" /> 97 <ConfigDefine name="CY_CFG_SYSCLK_FLL_REFDIV" value="`${reference}`U" public="false" include="true" /> 98 <ConfigDefine name="CY_CFG_SYSCLK_FLL_CCO_RANGE" value="`${getTclVar("ccoRange", callSolver)}`" public="false" include="true" /> 99 <ConfigDefine name="CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV" value="`${getTclVar("enableOutputDiv", callSolver)}`" public="false" include="true" /> 100 <ConfigDefine name="CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE" value="`${tolerance}`U" public="false" include="true" /> 101 <ConfigDefine name="CY_CFG_SYSCLK_FLL_IGAIN" value="`${getTclVar("igain", callSolver)}`U" public="false" include="true" /> 102 <ConfigDefine name="CY_CFG_SYSCLK_FLL_PGAIN" value="`${getTclVar("pgain", callSolver)}`U" public="false" include="true" /> 103 <ConfigDefine name="CY_CFG_SYSCLK_FLL_SETTLING_COUNT" value="`${getTclVar("settlingCount", callSolver)}`U" public="false" include="true" /> 104 <ConfigDefine name="CY_CFG_SYSCLK_FLL_OUTPUT_MODE" value="`${getTclVar("outputMode", callSolver)}`" public="false" include="true" /> 105 <ConfigDefine name="CY_CFG_SYSCLK_FLL_CCO_FREQ" value="`${getTclVar("cco_Freq", callSolver)}`U" public="false" include="true" /> 106 <ConfigDefine name="CY_CFG_SYSCLK_FLL_OUT_FREQ" value="`${frequency}`" public="false" include="true" /> 107 <ConfigStruct name="`${INST_NAME . "_fllConfig"}`" type="cy_stc_fll_manual_config_t" const="true" public="false" include="true" guard="(!defined(CY_DEVICE_SECURE))"> 108 <Member name="fllMult" value="`${multiplier}`U" /> 109 <Member name="refDiv" value="`${reference}`U" /> 110 <Member name="ccoRange" value="`${getTclVar("ccoRange", callSolver)}`" /> 111 <Member name="enableOutputDiv" value="`${manConfig ? (enableOutputDivider ? "true" : "false") : getTclVar("enableOutputDiv", callSolver)}`" /> 112 <Member name="lockTolerance" value="`${tolerance}`U" /> 113 <Member name="igain" value="`${getTclVar("igain", callSolver)}`U" /> 114 <Member name="pgain" value="`${getTclVar("pgain", callSolver)}`U" /> 115 <Member name="settlingCount" value="`${getTclVar("settlingCount", callSolver)}`U" /> 116 <Member name="outputMode" value="`${getTclVar("outputMode", callSolver)}`" /> 117 <Member name="cco_Freq" value="`${getTclVar("cco_Freq", callSolver)}`U" /> 118 </ConfigStruct> 119 <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_FllInit()" body=" if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&`${INST_NAME}`_fllConfig))
 {
 cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
 }
 if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
 {
 cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
 }" public="false" include="true" guard="(!defined(CY_DEVICE_SECURE))"/> 120 <ConfigInstruction value="CY_UNUSED_PARAM(srss_0_clock_0_fll_0_fllConfig);" include="`${("mxs40ssrss" eq getIpBlockName())}`" guard="(!defined(CY_DEVICE_SECURE))"/> 121 </ConfigFirmware> 122</Personality> 123
