1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file extclk.cypersonality 6* \version 3.0 7* 8* \brief 9* EXTCLK personality description file. It Supports CAT1A, CAT1B and CAT1C family of devices. 10* 11******************************************************************************** 12* \copyright 13* Copyright (c) 2022, Cypress Semiconductor Corporation (an Infineon company) or 14* an affiliate of Cypress Semiconductor Corporation. 15* SPDX-License-Identifier: Apache-2.0 16* 17* Licensed under the Apache License, Version 2.0 (the "License"); 18* you may not use this file except in compliance with the License. 19* You may obtain a copy of the License at 20* 21* http://www.apache.org/licenses/LICENSE-2.0 22* 23* Unless required by applicable law or agreed to in writing, software 24* distributed under the License is distributed on an "AS IS" BASIS, 25* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26* See the License for the specific language governing permissions and 27* limitations under the License. 28*****************************************************************************--> 29 30<Personality id="extclk" name="EXTCLK" version="3.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 31 <Dependencies> 32 <IpBlock name="mxs40srss,mxs40ssrss,mxs40srss_ver2,mxs40srss_ver3,mxs22srss" /> 33 <IpBlock name="mxs40ioss,mxs40sioss,mxs22ioss" /> 34 <Resource name="srss\.clock\.ext" /> 35 </Dependencies> 36 <ExposedMembers> 37 <ExposedMember key="frequency" paramId="frequency" /> 38 <ExposedMember key="accuracy" paramId="accuracyPct" /> 39 <ExposedMember key="suppressCodeGen" paramId="suppressWcoCodeGen" /> 40 </ExposedMembers> 41 <Parameters> 42 <!-- PDL documentation --> 43 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__sysclk.html" linkText="Open System Clock Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 44 <ParamBool id="is40ssrssAvailable" name="is40ssrssAvailable" group="" default="`${("mxs40ssrss" eq getIpBlockName())}`" visible="false" editable="false" desc="" /> 45 <ParamBool id="is40srss_ver2or3Available" name="is40srss_ver2or3Available" group="" default="`${("mxs40srss_ver2" eq getIpBlockName()) || ("mxs40srss_ver3" eq getIpBlockName())}`" visible="false" editable="false" desc="" /> 46 <ParamBool id="is22srssAvailable" name="is22srssAvailable" group="" default="`${("mxs22srss" eq getIpBlockName())}`" visible="false" editable="false" desc="" /> 47 <ParamBool id="is40srssAvailable" name="is40srssAvailable" group="" default="`${("mxs40srss" eq getIpBlockName())}`" visible="false" editable="false" desc="" /> 48 49 <ParamBool id="usingUlp" name="usingUlp" group="Internal" default="`${isBlockUsed("srss[0].power[0]") && getExposedMember("srss[0].power[0]", "usingUlp")}`" visible="false" editable="false" desc="" /> 50 <ParamString id="maxFrequency" name="Max Frequency (MHz)" group="Internal" default="`${getDeviceAttr("CPU_MAX_MHZ") > 100 ? 100 : getDeviceAttr("CPU_MAX_MHZ")}`" visible="false" editable="false" desc="The maximum EXTCLK frequency" /> 51 52 <ParamRange id="extFrequencyMin" name="Min Ext Frequency" group="General" default="0.001" min="0.001" max="1" resolution="0.001" visible="false" editable="false" desc="Max FLL Frequency based on platform." /> 53 <ParamRange id="frequencyMin" name="Min Frequency" group="General" default="1000" min="1000" max="1000000" resolution="1" visible="false" editable="false" desc="Max FLL Frequency based on platform." /> 54 55 <ParamRange id="extFrequency" name="Frequency (MHz)" group="General" default="24.000" min="`${extFrequencyMin}`" max="`${maxFrequency}`" resolution="0.001" visible="true" editable="true" desc="" /> 56 <ParamRange id="frequency" name="Frequency" group="Internal" default="`${extFrequency * 1000000}`" visible="false" editable="false" min="`${frequencyMin}`" max="100000000" resolution="1" desc="" /> 57 <ParamRange id="accuracyPpm" name="Accuracy (±ppm)" group="General" default="0" min="0" max="1000000" resolution="1" visible="true" editable="true" desc="Clock accuracy in ppm" /> 58 <ParamString id="accuracyPct" name="Accuracy (±%)" group="General" default="`${accuracyPpm/10000.0}`" visible="true" editable="false" desc="Clock accuracy in %" /> 59 60 <ParamSignal port="ext_clk[0]" name="Pin" group="Connections" visible="true" desc="The input terminal to connect the external clock signal" canBeEmpty="false" /> 61 62 <ParamString id="gpio_port" name="gpio_port" group="Internal" default="`${getInstFromLocation(getParamValue("ext_clk[0]"), "port")}`" visible="false" editable="false" desc="" /> 63 <ParamString id="gpio_pin" name="gpio_pin" group="Internal" default="`${getInstFromLocation(getParamValue("ext_clk[0]"), "pin")}`" visible="false" editable="false" desc="" /> 64 <ParamBool id="suppressWcoCodeGen" name="Suppress WCO PIN Configuration Code Generation" group="Internal" default="true" 65 visible="false" editable="false" desc="Prevents pins connected to this personality to generate configuration code" /> 66 </Parameters> 67 <DRCs> 68 <!-- For ULP mode, Fextclk_max = 50 MHz. For LP mode, Fextclk_max = 100 MHz or Fcpu_max (if Fcpu_max < 100 MHz) --> 69 <DRC type="ERROR" text="The EXTCLK frequency `${extFrequency}` MHz is higher than the maximum operating frequency `${maxFrequency}` MHz of the device" condition="`${!usingUlp && extFrequency > maxFrequency}`" paramId="extFrequency" /> 70 <DRC type="ERROR" text="The EXTCLK frequency `${extFrequency}` MHz exceeds the maximum of 50 MHz when the ULP mode is used" condition="`${usingUlp && extFrequency > 50}`" paramId="extFrequency" /> 71 </DRCs> 72 <ConfigFirmware> 73 <ConfigInclude value="cy_gpio.h" include="true" /> 74 <ConfigDefine name="CY_CFG_SYSCLK_EXTCLK_ENABLED" value="1" public="false" include="true" /> 75 <ConfigDefine name="CY_CFG_SYSCLK_EXTCLK_FREQ" value="`${frequency}`UL" public="false" include="true" /> 76 <ConfigDefine name="CY_CFG_SYSCLK_EXTCLK_GPIO_PRT" value="GPIO_PRT`${gpio_port}`" public="false" include="true" /> 77 <ConfigDefine name="CY_CFG_SYSCLK_EXTCLK_GPIO_PIN" value="`${gpio_pin}`" public="false" include="true" /> 78 <ConfigDefine name="CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM" value="P`${gpio_port}`_`${gpio_pin}`_SRSS_EXT_CLK" public="false" include="true" /> 79 <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_ExtClkInit()" body=" (void)Cy_GPIO_Pin_FastInit(GPIO_PRT`${gpio_port}`, `${gpio_pin}`, CY_GPIO_DM_HIGHZ, 0UL, P`${gpio_port}`_`${gpio_pin}`_SRSS_EXT_CLK);
 Cy_SysClk_ExtClkSetFrequency(CY_CFG_SYSCLK_EXTCLK_FREQ);" public="false" include="`${(is40srssAvailable || is40ssrssAvailable || is40srss_ver2or3Available)}`" guard="((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))" /> 80 <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_ExtClkInit()" body=" (void)Cy_GPIO_Pin_SecFastInit(GPIO_PRT`${gpio_port}`, `${gpio_pin}`, CY_GPIO_DM_HIGHZ, 0UL, P`${gpio_port}`_`${gpio_pin}`_SRSS_EXT_CLK);
" public="false" include="`${(is22srssAvailable)}`" guard="defined(CORE_NAME_CM33_0) && defined(CY_PDL_TZ_ENABLED)" /> 81 </ConfigFirmware> 82</Personality> 83
