1<?xml version="1.0" encoding="utf-8"?>
2
3
4<!--****************************************************************************
5* \file slowclk.cypersonality
6* \version 2.0
7*
8* \brief
9* CLK_SLOW personality description file.
10* This supports CAT1A and CAT1C devices.
11*
12********************************************************************************
13* \copyright
14* Copyright 2018-2022 Cypress Semiconductor Corporation
15* SPDX-License-Identifier: Apache-2.0
16*
17* Licensed under the Apache License, Version 2.0 (the "License");
18* you may not use this file except in compliance with the License.
19* You may obtain a copy of the License at
20*
21*     http://www.apache.org/licenses/LICENSE-2.0
22*
23* Unless required by applicable law or agreed to in writing, software
24* distributed under the License is distributed on an "AS IS" BASIS,
25* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
26* See the License for the specific language governing permissions and
27* limitations under the License.
28*****************************************************************************-->
29
30<Personality id="slowclk" name="CLK_SLOW" version="2.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v7">
31  <Dependencies>
32    <IpBlock name="mxs40srss,mxs40srss_ver3" />
33    <Resource name="srss\.clock\.slowclk" />
34  </Dependencies>
35  <ExposedMembers>
36    <ExposedMember key="frequency" paramId="frequency" />
37    <ExposedMember key="accuracy"  paramId="accuracy" />
38  </ExposedMembers>
39  <Parameters>
40    <!-- PDL documentation -->
41    <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__sysclk__clk__slow.html" linkText="Open Slow Clock Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" />
42
43    <!-- Source clock -->
44    <ParamString id="sourceClockRsc" name="Source Clock" group="Internal" default="`${&quot;mxs40srss&quot; eq getIpBlockName() ? &quot;srss[0].clock[0].periclk[0]&quot; : &quot;srss[0].clock[0].memclk[0]&quot;}`" visible="false" editable="false" desc="" />
45    <!-- Set an error if the source clock is not enabled -->
46    <ParamBool id="srcNotUsed" name="Clock Source Enabled" group="Internal" default="`${!isBlockUsed(sourceClockRsc)}`" visible="false" editable="false" desc="" />
47    <ParamBool id="clockError" name="Clock Error" group="Internal" default="`${&quot;mxs40srss&quot; eq getIpBlockName() ? getExposedMember(sourceClockRsc, &quot;error&quot;) : 0}`" visible="false" editable="false" desc="" />
48    <ParamBool id="error" name="Clock Error" group="Internal" default="`${srcNotUsed || clockError}`" visible="false" editable="false" desc="" />
49    <ParamRange  id="sourceFreq" name="sourceFrequency" group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, &quot;frequency&quot;) : 0}`" min="0" max="400000000" resolution="1" visible="false" editable="false" desc="" />
50    <ParamString id="accuracy"  name="Accuracy"  group="Internal" default="`${!error ? getExposedMember(sourceClockRsc, &quot;accuracy&quot;) : 0}`" visible="false" editable="false" desc="" />
51    <ParamString id="sourceFrequencyInfo" name="Source Clock" group="General" default="`${formatFrequency(sourceFreq,accuracy)}`" visible="true" editable="false" desc="Source clock frequency" />
52
53    <!-- Resulted clock -->
54    <ParamRange id="divider" name="Divider" group="General" default="1" min="1" max="256" resolution="1" visible="true" editable="true" desc="" />
55    <ParamRange id="frequency" name="Frequency" group="Internal" default="`${sourceFreq / divider}`" min="0" max="400000000" resolution="1" visible="false" editable="false" desc="" />
56
57    <!-- If the frequency is less than one MHz, display its value in kHz -->
58    <ParamString id="frequencyInfo" name="Frequency" group="General" default="`${formatFrequency(frequency,accuracy)}`" visible="true" editable="false" desc="The resulting CLK_SLOW output clock frequency" />
59  </Parameters>
60  <DRCs>
61    <DRC type="ERROR" text="Source clock for CLK_SLOW is not enabled" condition="`${srcNotUsed}`" >
62      <FixIt action="ENABLE_BLOCK" target="`${sourceClockRsc}`" value="" valid="true" />
63    </DRC>
64  </DRCs>
65  <ConfigFirmware>
66    <ConfigInclude value="cy_sysclk.h" include="true" />
67    <ConfigDefine name="CY_CFG_SYSCLK_CLKSLOW_ENABLED" value="1" public="false" include="true" />
68    <ConfigDefine name="CY_CFG_SYSCLK_CLKSLOW_DIVIDER" value="`${divider - 1}`"  public="false" include="true" />
69    <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_ClkSlowInit()" body="    Cy_SysClk_ClkSlowSetDivider(`${divider - 1}`U);" public="false" include="true" guard="(!defined(CY_DEVICE_SECURE))" />
70  </ConfigFirmware>
71</Personality>
72