1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file debug.cypersonality 6* \version 2.0 7* 8* \brief 9* Debug Access personality description file. 10* Supports CAT1A, CAT1B and CAT1C Device Families. 11* 12******************************************************************************** 13* \copyright 14* Copyright 2018-2022 Cypress Semiconductor Corporation 15* SPDX-License-Identifier: Apache-2.0 16* 17* Licensed under the Apache License, Version 2.0 (the "License"); 18* you may not use this file except in compliance with the License. 19* You may obtain a copy of the License at 20* 21* http://www.apache.org/licenses/LICENSE-2.0 22* 23* Unless required by applicable law or agreed to in writing, software 24* distributed under the License is distributed on an "AS IS" BASIS, 25* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26* See the License for the specific language governing permissions and 27* limitations under the License. 28*****************************************************************************--> 29 30<Personality id="dap" name="Debug Access" version="2.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 31 <Dependencies> 32 <IpBlock name="m4cpuss,m4cpuss_ver2,m33syscpuss,m7cpuss" /> 33 <Resource name="cpuss\.dap" /> 34 </Dependencies> 35 36 <ExposedMembers /> 37 38 <Parameters> 39 <ParamDoc id="pdlDoc" name="Application Notes" group="Overview" default="https://www.infineon.com/AN235279" linkText="Performing ETM and ITM Trace on PSoC 6 MCU" visible="`${hasMatch(getIpBlockName(), "m4cpuss.*")}`" desc="Opens the application note for Debug module." /> 40 <ParamChoice id="dbgMode" name="Debug Mode" group="General" default="SWD" visible="true" editable="true" desc="Controls what pins need to be reserved for debugging."> 41 <Entry name="Disabled" value="NONE" visible="true" /> 42 <Entry name="SWD" value="SWD" visible="true" /> 43 <Entry name="JTAG" value="JTAG" visible="true" /> 44 </ParamChoice> 45 <ParamBool id="traceClockExists" name="traceClock" group="General" default="`${hasVisibleOption("trace_clock[0]")}`" visible="false" editable="false" desc="" /> 46 <ParamChoice id="traceModeParallel" name="Trace Mode - Parallel" group="General" default="0" visible="true" editable="true" desc="Number of parallel pins used in trace."> 47 <Entry name="Disabled" value="0" visible="true" /> 48 <Entry name="1-bit Parallel Trace" value="1" visible="`${traceClockExists}`" /> 49 <Entry name="2-bit Parallel Trace" value="2" visible="`${traceClockExists}`" /> 50 <Entry name="4-bit Parallel Trace" value="4" visible="`${traceClockExists}`" /> 51 </ParamChoice> 52 <ParamBool id="traceModeSerial" name="Trace Mode - Serial" group="General" default="false" visible="`${dbgMode ne JTAG}`" editable="true" desc="Enables Serial Trace Mode." /> 53 <ParamString id="dbgGroup" name="dbgGroup" group="Internal" default="`${dbgMode eq SWD ? "SWD" : "JTAG"}` Pins" visible="false" editable="false" desc="" /> 54 <ParamSignal port="clock_trace_in[0]" name="Clock" group="Trace Clock" visible="`${hasVisibleOption("clock_trace_in[0]") && (traceModeSerial || traceModeParallel)}`" desc="Clock that operates this block." canBeEmpty="`${!traceModeSerial && !traceModeParallel}`" > 55 <Constraint type="ACCEPT" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_.*" valid="true" > 56 <Parameter id="intDivider" severity="INFO" reason="Clock Divider must be set to 1."> 57 <Fixed value="1" /> 58 </Parameter> 59 <Parameter id="fracDivider" severity="INFO" reason="Fractional Clock Divider must be set to 0."> 60 <Fixed value="0" /> 61 </Parameter> 62 </Constraint> 63 </ParamSignal> 64 <ParamSignal port="clock_trace_in_pos_en[0]" name="Clock" group="Trace Clock" visible="`${hasVisibleOption("clock_trace_in_pos_en[0]") && (traceModeSerial || traceModeParallel)}`" desc="Clock that operates this block." canBeEmpty="`${!traceModeSerial && !traceModeParallel}`" > 65 <Constraint type="ACCEPT" targetLocation="peri\[\d+\](\.group\[\d+\])?\.div_.*" valid="true" > 66 <Parameter id="intDivider" severity="INFO" reason="Clock Divider must be set to 1."> 67 <Fixed value="1" /> 68 </Parameter> 69 <Parameter id="fracDivider" severity="INFO" reason="Fractional Clock Divider must be set to 0."> 70 <Fixed value="0" /> 71 </Parameter> 72 </Constraint> 73 </ParamSignal> 74 <!-- Peripheral clock divider connection --> 75 <ParamString id="sourceClock" name="sourceClock" group="Internal" default="`${(hasVisibleOption("clock_trace_in[0]")) ? (getBlockFromSignal("clock_trace_in[0]")) : (getBlockFromSignal("clock_trace_in_pos_en[0]"))}`" visible="false" editable="false" desc="Source Clock Resource" /> 76 <ParamBool id="pclkOk" name="PCLK Valid" group="Internal" default="`${(hasVisibleOption("clock_trace_in[0]")) ? (hasConnection("clock_trace_in", 0) && isBlockUsed(sourceClock)) : (hasConnection("clock_trace_in_pos_en", 0) && isBlockUsed(sourceClock)) }`" visible="false" editable="false" desc="Checks whether there is a PCLK connected and enabled." /> 77 78 79 <ParamSignal port="swj_swdio_tms[0]" name="`${dbgMode eq SWD ? "SWDIO" : "TMS"}`" group="`${dbgGroup}`" visible="`${dbgMode ne NONE}`" desc="Reserve the pin for `${dbgMode eq SWD ? "Single Wire Data In/Out" : "Test Mode Select"}`" canBeEmpty="`${dbgMode eq NONE}`"> 80 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 81 <Parameter id="DriveModes" severity="ERROR" reason="Drive Mode must be set to 'Resistive Pull-Up. Input buffer on'."> 82 <Fixed value="CY_GPIO_DM_PULLUP" /> 83 </Parameter> 84 </Constraint> 85 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 86 </ParamSignal> 87 <ParamSignal port="swj_swclk_tclk[0]" name="`${dbgMode eq SWD ? "SWCLK" : "TCLK"}`" group="`${dbgGroup}`" visible="`${dbgMode ne NONE}`" desc="Reserve the pin for `${dbgMode eq SWD ? "Single Wire Clock" : "Test Clock"}`" canBeEmpty="`${dbgMode eq NONE}`"> 88 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 89 <Parameter id="DriveModes" severity="ERROR" reason="Drive Mode must be set to 'Resistive Pull-Down. Input buffer on'."> 90 <Fixed value="CY_GPIO_DM_PULLDOWN" /> 91 </Parameter> 92 </Constraint> 93 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 94 </ParamSignal> 95 <ParamSignal port="swj_swo_tdo[0]" name="`${dbgMode eq SWD ? "SWO" : "TDO"}`" group="`${dbgMode eq SWD ? "Trace Pins" : dbgGroup}`" visible="`${(dbgMode eq JTAG) || ((dbgMode eq SWD) && traceModeSerial)}`" desc="Reserve the pin for `${dbgMode eq SWD ? "Single Wire Output" : "Test Data Output"}`" canBeEmpty="`${!((dbgMode eq JTAG) || ((dbgMode eq SWD) && traceModeSerial))}`"> 96 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 97 <Parameter id="DriveModes" severity="ERROR" reason="Drive Mode must be set to 'Strong Drive. Input buffer off'."> 98 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 99 </Parameter> 100 <Parameter id="initialState" severity="ERROR" reason="Initial State must be set to High (1)."> 101 <Fixed value="1" /> 102 </Parameter> 103 <Parameter id="driveStrength" severity="ERROR" reason="Drive Strength must be set to 1 / 2."> 104 <Fixed value="CY_GPIO_DRIVE_1_2" /> 105 </Parameter> 106 <Parameter id="slewRate" severity="ERROR" reason="Slew Rate must be set to Fast."> 107 <Fixed value="CY_GPIO_SLEW_FAST" /> 108 </Parameter> 109 <Parameter id="isrTrigger" severity="ERROR" reason="Interrupt Trigger Type must be set to None."> 110 <Fixed value="CY_GPIO_INTR_DISABLE" /> 111 </Parameter> 112 <Parameter id="vtrip" severity="ERROR" reason="Threshold must be set to CMOS."> 113 <Fixed value="CY_GPIO_VTRIP_CMOS" /> 114 </Parameter> 115 </Constraint> 116 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 117 </ParamSignal> 118 <ParamSignal port="swj_swdoe_tdi[0]" name="TDI" group="`${dbgGroup}`" visible="`${dbgMode eq JTAG}`" desc="Reserve pin for Test Data Input" canBeEmpty="`${dbgMode ne JTAG}`"> 119 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 120 <Parameter id="DriveModes" severity="ERROR" reason="Drive Mode must be set to 'Strong Drive. Input buffer off'."> 121 <Fixed value="CY_GPIO_DM_PULLUP" /> 122 </Parameter> 123 </Constraint> 124 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 125 </ParamSignal> 126 <ParamSignal port="swj_trstn[0]" name="TRSTn" group="`${dbgGroup}`" visible="`${dbgMode eq JTAG}`" desc="Reserve pin for Test Reset" canBeEmpty="true"> 127 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 128 <Parameter id="DriveModes" severity="ERROR" reason="Drive Mode must be set to 'Resistive Pull-Up. Input buffer on'."> 129 <Fixed value="CY_GPIO_DM_PULLUP" /> 130 </Parameter> 131 </Constraint> 132 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 133 </ParamSignal> 134 135 <ParamSignal port="trace_clock[0]" name="CLK" group="Trace Pins" visible="`${traceModeParallel && traceClockExists}`" desc="Clock pin for the Cortex ETM Trace." canBeEmpty="`${!(traceModeParallel && traceClockExists)}`"> 136 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 137 <Parameter id="DriveModes" severity="ERROR" reason="Drive Mode must be set to 'Strong Drive. Input buffer off'."> 138 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 139 </Parameter> 140 <Parameter id="initialState" severity="ERROR" reason="Initial State must be set to High (1)."> 141 <Fixed value="1" /> 142 </Parameter> 143 <Parameter id="driveStrength" severity="ERROR" reason="Drive Strength must be set to 1 / 2."> 144 <Fixed value="CY_GPIO_DRIVE_1_2" /> 145 </Parameter> 146 <Parameter id="slewRate" severity="ERROR" reason="Slew Rate must be set to Fast."> 147 <Fixed value="CY_GPIO_SLEW_FAST" /> 148 </Parameter> 149 <Parameter id="isrTrigger" severity="ERROR" reason="Interrupt Trigger Type must be set to None."> 150 <Fixed value="CY_GPIO_INTR_DISABLE" /> 151 </Parameter> 152 <Parameter id="vtrip" severity="ERROR" reason="Threshold must be set to CMOS."> 153 <Fixed value="CY_GPIO_VTRIP_CMOS" /> 154 </Parameter> 155 </Constraint> 156 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 157 </ParamSignal> 158 <Repeat count="64"> 159 <ParamSignal port="trace_data[$idx]" name="Data[$idx]" group="Trace Pins" visible="`${$idx < traceModeParallel}`" desc="Data[$idx] pin for the Cortex ETM Trace." canBeEmpty="`${!($idx < traceModeParallel)}`"> 160 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 161 <Parameter id="DriveModes" severity="ERROR" reason="Drive Mode must be set to 'Strong Drive. Input buffer off'."> 162 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 163 </Parameter> 164 <Parameter id="initialState" severity="ERROR" reason="Initial State must be set to High (1)."> 165 <Fixed value="1" /> 166 </Parameter> 167 <Parameter id="driveStrength" severity="ERROR" reason="Drive Strength must be set to 1 / 2."> 168 <Fixed value="CY_GPIO_DRIVE_1_2" /> 169 </Parameter> 170 <Parameter id="slewRate" severity="ERROR" reason="Slew Rate must be set to Fast."> 171 <Fixed value="CY_GPIO_SLEW_FAST" /> 172 </Parameter> 173 <Parameter id="isrTrigger" severity="ERROR" reason="Interrupt Trigger Type must be set to None."> 174 <Fixed value="CY_GPIO_INTR_DISABLE" /> 175 </Parameter> 176 <Parameter id="vtrip" severity="ERROR" reason="Threshold must be set to CMOS."> 177 <Fixed value="CY_GPIO_VTRIP_CMOS" /> 178 </Parameter> 179 </Constraint> 180 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 181 </ParamSignal> 182 </Repeat> 183 <ParamString id="pclkTraceClockString" name="PCLK Destination Clock" group="Internal" default="PCLK_CPUSS_CLOCK_TRACE_IN" visible="false" editable="false" desc="String variable used for PCLK_SCB_CLOCK." /> 184 <ParamString id="pclkTraceClockENString" name="PCLK Destination Clock" group="Internal" default="PCLK_CPUSS_CLOCK_TRACE_IN_POS_EN" visible="false" editable="false" desc="String variable used only for PCLK_SCB_CLOCK_SCB_EN." /> 185 186 <ParamString id="pclkDst" name="PCLK Destination" group="Internal" default="`${(hasMatch(getIpBlockName(), "m33syscpuss.*")) ? pclkTraceClockENString : pclkTraceClockString }`" visible="false" editable="false" desc="Generates PCLK connection define." /> 187 188 </Parameters> 189 190 <DRCs> 191 </DRCs> 192 193 <ConfigFirmware> 194 <ConfigInstruction value="Cy_SysClk_PeriPclkAssignDivider(`${pclkDst}`, `${getExposedMember(sourceClock, "clockSel")}`);" include="`${((!(hasMatch(getIpBlockName(), "m4cpuss.*"))) && pclkOk)}`" /> 195 <ConfigInstruction value="Cy_SysClk_PeriphAssignDivider(`${pclkDst}`, `${getExposedMember(sourceClock, "clockSel")}`);" include="`${(hasMatch(getIpBlockName(), "m4cpuss.*") && pclkOk)}`" /> 196 </ConfigFirmware> 197</Personality> 198
