1<?xml version="1.0" encoding="utf-8"?> 2 3<!--**************************************************************************** 4* \file sysanalog.cypersonality 5* \version 1.0 6* 7* \brief 8* SysAnalog personality description file. 9* 10******************************************************************************** 11* \copyright 12* Copyright 2018-2022 Cypress Semiconductor Corporation 13* SPDX-License-Identifier: Apache-2.0 14* 15* Licensed under the Apache License, Version 2.0 (the "License"); 16* you may not use this file except in compliance with the License. 17* You may obtain a copy of the License at 18* 19* http://www.apache.org/licenses/LICENSE-2.0 20* 21* Unless required by applicable law or agreed to in writing, software 22* distributed under the License is distributed on an "AS IS" BASIS, 23* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24* See the License for the specific language governing permissions and 25* limitations under the License. 26*****************************************************************************--> 27 28<Personality id="mxs40sysanalog" name="Programmable Analog" version="1.0" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 29 <Dependencies> 30 <IpBlock name="mxs40pass,mxs40pass_ver2" /> 31 <Resource name="pass" /> 32 <DependentResource name="pass.ctb.oa" /> 33 </Dependencies> 34 <ExposedMembers> 35 <ExposedMember key="iptat_level" paramId="iptat_level" /> 36 <ExposedMember key="ctb0_deep_sleep" paramId="ctb0_deep_sleep" /> 37 <ExposedMember key="ctb1_deep_sleep" paramId="ctb1_deep_sleep" /> 38 <ExposedMember key="ctb2_deep_sleep" paramId="ctb2_deep_sleep" /> 39 <ExposedMember key="ctb3_deep_sleep" paramId="ctb3_deep_sleep" /> 40 <ExposedMember key="frequency" paramId="frequency" /> 41 </ExposedMembers> 42 <Parameters> 43 <!-- PDL documentation --> 44 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__ctb.html" linkText="Open CTB Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation" /> 45 46 <!--Internal--> 47 <ParamBool id="isClkPumpEnabled" name="Is Pump Clock Enabled" group="Internal" default="`${isBlockUsed("srss[0].clock[0].pumpclk[0]")}`" visible="false" editable="false" desc="Pump clock enabling state" /> 48 <ParamBool id="hasCTB" name="hasCTB" group="Internal" default="`${hasBlock("pass[0].ctb[0].oa[0]")}`" visible="false" editable="false" desc="Check whether device has CTBs" /> 49 <ParamBool id="isArefEnabled" name="Is Aref Enabled" group="Internal" default="`${isBlockUsed("pass[0].aref[0]")}`" visible="false" editable="false" desc="" /> 50 51 <ParamString id="version" name="version number" group="Internal" default="`${getVersion()}`" visible="false" editable="false" desc="" /> 52 <ParamBool id="ver1" name="ver1" desc="" group="Internal" default="`${version eq 1}`" visible="false" editable="false" /> 53 <!--Internal--> 54 55 <ParamChoice id="iptat_level" name="Opamp Reference Current" group="Global Opamp Settings" default="CY_CTB_IPTAT_NORMAL" visible="`${hasCTB}`" editable="true" desc="Select the level for the opamp current output." > 56 <Entry name="1 uA" value="CY_CTB_IPTAT_NORMAL" visible="true" /> 57 <Entry name="100 nA" value="CY_CTB_IPTAT_LOW" visible="true" /> 58 </ParamChoice> 59 60 <ParamChoice id="pump_clock_source" name="Opamp Pump Clock Source" group="Global Opamp Settings" default="CY_CTB_CLK_PUMP_SRSS" visible="`${hasCTB && ver1}`" editable="true" desc="Select the clock source for the opamp pump clock." > 61 <Entry name="SRSS" value="CY_CTB_CLK_PUMP_SRSS" visible="true" /> 62 <Entry name="Peri Clock Divider" value="CY_CTB_CLK_PUMP_PERI" visible="true" /> 63 </ParamChoice> 64 65 <ParamSignal name="Peri Clock" port="clock_pump_peri[0]" group="Global Opamp Settings" visible="`${pump_clock_source eq CY_CTB_CLK_PUMP_PERI}`" desc="Peri divider clock for the pump clock." canBeEmpty="`${pump_clock_source ne CY_CTB_CLK_PUMP_PERI}`" /> 66 <ParamString id="peri_source_clock" name="Pump Clock Peri Source Resource" group="Global Opamp Settings" default="`${getBlockFromSignal("clock_pump_peri[0]")}`" visible="false" editable="false" desc="Pump Clock Peri Source Resource" /> 67 <ParamRange id="frequency" name="Frequency" group="Internal" default="`${(pump_clock_source eq CY_CTB_CLK_PUMP_SRSS) ? (isClkPumpEnabled ? getExposedMember("srss[0].clock[0].pumpclk[0]", "frequency") : 0) : ((peri_source_clock ne "") ? getExposedMember(peri_source_clock, "frequency") : 0)}`" min="0" max="1000000000" resolution="1" visible="false" editable="false" desc=""/> 68 <ParamString id="pump_clk_freq" name="Opamp Pump Clock Frequency" group="Global Opamp Settings" default="`${frequency < 1000000 ? frequency / 1000.0 . " kHz" : frequency / 1000000.0 . " MHz"}`" visible="`${hasCTB && ver1}`" editable="false" desc="Frequency of the Analog Pump Clock" /> 69 70 <ParamBool id="ctb0_deep_sleep" name="Deep Sleep Enable" group="CTB0" default="false" visible="`${hasCTB && (NR_CTBS > 0)}`" editable="true" desc="Maintain the opamp output during Deep Sleep for CTB0. Enabling Deep Sleep will reduce the output range of the opamp." /> 71 <ParamBool id="ctb1_deep_sleep" name="Deep Sleep Enable" group="CTB1" default="false" visible="`${hasCTB && (NR_CTBS > 1)}`" editable="true" desc="Maintain the opamp output during Deep Sleep for CTB1. Enabling Deep Sleep will reduce the output range of the opamp." /> 72 <ParamBool id="ctb2_deep_sleep" name="Deep Sleep Enable" group="CTB2" default="false" visible="`${hasCTB && (NR_CTBS > 2)}`" editable="true" desc="Maintain the opamp output during Deep Sleep for CTB2. Enabling Deep Sleep will reduce the output range of the opamp." /> 73 <ParamBool id="ctb3_deep_sleep" name="Deep Sleep Enable" group="CTB3" default="false" visible="`${hasCTB && (NR_CTBS > 3)}`" editable="true" desc="Maintain the opamp output during Deep Sleep for CTB3. Enabling Deep Sleep will reduce the output range of the opamp." /> 74 75 <!-- Peripheral clock divider connection --> 76 <ParamString id="pclk" name="PCLK" group="Internal" default="`${getBlockFromSignal("clock_pump_peri[0]")}`" visible="false" editable="false" desc="Connected peripheral clock divider (PCLK)." /> 77 <ParamBool id="pclkOk" name="PCLK Valid" group="Internal" default="`${hasConnection("clock_pump_peri", 0) && isBlockUsed(pclk)}`" visible="false" editable="false" desc="Checks whether there is a PCLK connected and enabled." /> 78 <ParamString id="pclkDst" name="PCLK Destination" group="Internal" default="PCLK_PASS_CLOCK_PUMP_PERI" visible="false" editable="false" desc="Generates PCLK connection define." /> 79 80 <!--Advanced--> 81 <ParamBool id="inFlash" name="Store Config in Flash" group="Advanced" default="true" visible="`${!ver1}`" editable="true" desc="Controls whether the configuration structure is stored in flash (const, true) or SRAM (not const, false)." /> 82 </Parameters> 83 84 <DRCs> 85 <DRC type="ERROR" text="Pump clock (CLK_PUMP) resource must be enabled when the Opamp Pump Clock Source is set to SRSS." condition="`${hasCTB && !isClkPumpEnabled && pump_clock_source eq CY_CTB_CLK_PUMP_SRSS && ver1}`" location="srss[0].clock[0].pumpclk[0]"> 86 <FixIt action="ENABLE_BLOCK" target="srss[0].clock[0].pumpclk[0]" value="pumpclk-3.0" valid="true" /> 87 </DRC> 88 </DRCs> 89 90 <ConfigFirmware> 91 <ConfigInclude value="cy_ctb.h" include="`${iptat_level eq CY_CTB_IPTAT_LOW}`" /> 92 <ConfigInclude value="cy_sysclk.h" include="`${pclkOk && ver1}`" /> 93 <ConfigInclude value="cy_sysanalog.h" include="`${!ver1}`" /> 94 <ConfigInstruction value="Cy_CTB_SetIptatLevel(`${iptat_level}`);" include="`${iptat_level eq CY_CTB_IPTAT_LOW}`" /> 95 <ConfigInstruction value="Cy_SysClk_PeriphAssignDivider(`${pclkDst}`, `${getExposedMember(pclk, "clockSel")}`);" include="`${pump_clock_source eq CY_CTB_CLK_PUMP_PERI && pclkOk && ver1}`" /> 96 <ConfigInstruction value="Cy_CTB_SetDeepSleepMode(CTBM0, `${ctb0_deep_sleep ? "CY_CTB_DEEPSLEEP_ENABLE" : "CY_CTB_DEEPSLEEP_DISABLE"}`);" include="`${isBlockUsed("pass[0].ctb[0].oa[0]") || isBlockUsed("pass[0].ctb[0].oa[1]")}`" /> 97 <ConfigInstruction value="Cy_CTB_SetDeepSleepMode(CTBM1, `${ctb1_deep_sleep ? "CY_CTB_DEEPSLEEP_ENABLE" : "CY_CTB_DEEPSLEEP_DISABLE"}`);" include="`${isBlockUsed("pass[0].ctb[1].oa[0]") || isBlockUsed("pass[0].ctb[1].oa[1]")}`" /> 98 <ConfigInstruction value="Cy_CTB_SetDeepSleepMode(CTBM2, `${ctb2_deep_sleep ? "CY_CTB_DEEPSLEEP_ENABLE" : "CY_CTB_DEEPSLEEP_DISABLE"}`);" include="`${isBlockUsed("pass[0].ctb[2].oa[0]") || isBlockUsed("pass[0].ctb[2].oa[1]")}`" /> 99 <ConfigInstruction value="Cy_CTB_SetDeepSleepMode(CTBM3, `${ctb3_deep_sleep ? "CY_CTB_DEEPSLEEP_ENABLE" : "CY_CTB_DEEPSLEEP_DISABLE"}`);" include="`${isBlockUsed("pass[0].ctb[3].oa[0]") || isBlockUsed("pass[0].ctb[3].oa[1]")}`" /> 100 </ConfigFirmware> 101</Personality> 102
