1<?xml version="1.0" encoding="utf-8"?> 2 3 4<!--**************************************************************************** 5* \file pdm_pcm.cypersonality 6* \version 1.1 7* 8* \brief 9* PDM-PCM personality description file. Supports CAT1A family of devices 10* 11******************************************************************************** 12* \copyright 13* Copyright (c) (2022), Cypress Semiconductor Corporation (an Infineon company) or 14* an affiliate of Cypress Semiconductor Corporation. 15* SPDX-License-Identifier: Apache-2.0 16* 17* Licensed under the Apache License, Version 2.0 (the "License"); 18* you may not use this file except in compliance with the License. 19* You may obtain a copy of the License at 20* 21* http://www.apache.org/licenses/LICENSE-2.0 22* 23* Unless required by applicable law or agreed to in writing, software 24* distributed under the License is distributed on an "AS IS" BASIS, 25* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26* See the License for the specific language governing permissions and 27* limitations under the License. 28*****************************************************************************--> 29 30<Personality id="mxaudioss_pdm" name="PDM-PCM" version="1.1" xmlns="http://cypress.com/xsd/cyhwpersonality_v7"> 31 <Dependencies> 32 <IpBlock name="mxaudioss" /> 33 <Resource name="audioss\.pdm" /> 34 </Dependencies> 35 <ExposedMembers /> 36 <Parameters> 37 <!-- PDL documentation --> 38 <ParamDoc id="pdlDoc" name="Configuration Help" group="Overview" default="file:///`${cy_libs_path()}`/docs/pdl_api_reference_manual/html/group__group__pdm__pcm.html" linkText="Open PDM_PCM Documentation" visible="true" desc="Opens the Peripheral Driver Library Documentation." /> 39 40 <!-- Channels --> 41 <ParamBool id="chanSwap" name="Channel Recording Swap" group="Channels" default="false" visible="true" editable="true" desc="Right-left channel recording swap." /> 42 <ParamChoice id="gainLeft" name="Left Channel Gain" group="Channels" default="CY_PDM_PCM_BYPASS" visible="true" editable="true" desc="Left channel gain."> 43 <Entry name="-12dB" value="CY_PDM_PCM_ATTN_12_DB" visible="true" /> 44 <Entry name="-10.5dB" value="CY_PDM_PCM_ATTN_10_5_DB" visible="true" /> 45 <Entry name="-9dB" value="CY_PDM_PCM_ATTN_9_DB" visible="true" /> 46 <Entry name="-7.5dB" value="CY_PDM_PCM_ATTN_7_5_DB" visible="true" /> 47 <Entry name="-6dB" value="CY_PDM_PCM_ATTN_6_DB" visible="true" /> 48 <Entry name="-4.5dB" value="CY_PDM_PCM_ATTN_4_5_DB" visible="true" /> 49 <Entry name="-3dB" value="CY_PDM_PCM_ATTN_3_DB" visible="true" /> 50 <Entry name="-1.5dB" value="CY_PDM_PCM_ATTN_1_5_DB" visible="true" /> 51 <Entry name="0dB" value="CY_PDM_PCM_BYPASS" visible="true" /> 52 <Entry name="+1.5dB" value="CY_PDM_PCM_GAIN_1_5_DB" visible="true" /> 53 <Entry name="+3dB" value="CY_PDM_PCM_GAIN_3_DB" visible="true" /> 54 <Entry name="+4.5dB" value="CY_PDM_PCM_GAIN_4_5_DB" visible="true" /> 55 <Entry name="+6dB" value="CY_PDM_PCM_GAIN_6_DB" visible="true" /> 56 <Entry name="+7.5dB" value="CY_PDM_PCM_GAIN_7_5_DB" visible="true" /> 57 <Entry name="+9dB" value="CY_PDM_PCM_GAIN_9_DB" visible="true" /> 58 <Entry name="+10.5dB" value="CY_PDM_PCM_GAIN_10_5_DB" visible="true" /> 59 </ParamChoice> 60 <ParamChoice id="gainRight" name="Right Channel Gain" group="Channels" default="CY_PDM_PCM_BYPASS" visible="true" editable="true" desc="Right channel gain."> 61 <Entry name="-12dB" value="CY_PDM_PCM_ATTN_12_DB" visible="true" /> 62 <Entry name="-10.5dB" value="CY_PDM_PCM_ATTN_10_5_DB" visible="true" /> 63 <Entry name="-9dB" value="CY_PDM_PCM_ATTN_9_DB" visible="true" /> 64 <Entry name="-7.5dB" value="CY_PDM_PCM_ATTN_7_5_DB" visible="true" /> 65 <Entry name="-6dB" value="CY_PDM_PCM_ATTN_6_DB" visible="true" /> 66 <Entry name="-4.5dB" value="CY_PDM_PCM_ATTN_4_5_DB" visible="true" /> 67 <Entry name="-3dB" value="CY_PDM_PCM_ATTN_3_DB" visible="true" /> 68 <Entry name="-1.5dB" value="CY_PDM_PCM_ATTN_1_5_DB" visible="true" /> 69 <Entry name="0dB" value="CY_PDM_PCM_BYPASS" visible="true" /> 70 <Entry name="+1.5dB" value="CY_PDM_PCM_GAIN_1_5_DB" visible="true" /> 71 <Entry name="+3dB" value="CY_PDM_PCM_GAIN_3_DB" visible="true" /> 72 <Entry name="+4.5dB" value="CY_PDM_PCM_GAIN_4_5_DB" visible="true" /> 73 <Entry name="+6dB" value="CY_PDM_PCM_GAIN_6_DB" visible="true" /> 74 <Entry name="+7.5dB" value="CY_PDM_PCM_GAIN_7_5_DB" visible="true" /> 75 <Entry name="+9dB" value="CY_PDM_PCM_GAIN_9_DB" visible="true" /> 76 <Entry name="+10.5dB" value="CY_PDM_PCM_GAIN_10_5_DB" visible="true" /> 77 </ParamChoice> 78 <ParamChoice id="chanSelect" name="Stereo / Mono Mode Select" group="Channels" default="CY_PDM_PCM_OUT_STEREO" visible="true" editable="true" desc="Stereo / mono mode select."> 79 <Entry name="Mono L" value="CY_PDM_PCM_OUT_CHAN_LEFT" visible="true" /> 80 <Entry name="Mono R" value="CY_PDM_PCM_OUT_CHAN_RIGHT" visible="true" /> 81 <Entry name="Stereo" value="CY_PDM_PCM_OUT_STEREO" visible="true" /> 82 </ParamChoice> 83 84 <!-- Filter --> 85 <ParamBool id="highPassDisable" name="Disable High Pass Filter" group="Filter" default="false" visible="true" editable="true" desc="Disables high pass filter." /> 86 <ParamRange id="highPassFilterGain" name="High Pass Filter Gain" group="Filter" default="8" min="0" max="15" resolution="1" visible="true" editable="true" desc="High pass filter gain: H(Z) = (1 - Z^-1) / (1 - (1 - 2^(-HighPassFilterCoeff)) * Z^-1)." /> 87 88 <!-- Interrupts --> 89 <ParamBool id="rxNotEmpty" name="Not Empty" group="Interrupts" default="false" visible="true" editable="true" desc="RX FIFO is not empty interrupt." /> 90 <ParamBool id="rxOverflow" name="Overflow" group="Interrupts" default="false" visible="true" editable="true" desc="Attempt to write to a full RX FIFO." /> 91 <ParamBool id="rxTrig" name="Trigger" group="Interrupts" default="false" visible="true" editable="true" desc="More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTL." /> 92 <ParamBool id="rxUnderflow" name="Underflow" group="Interrupts" default="false" visible="true" editable="true" desc="Attempt to read from an empty RX FIFO." /> 93 <ParamString id="interruptMask" name="InterruptMask" group="Interrupts" default="`${((rxTrig || rxNotEmpty || rxOverflow || rxUnderflow) ? "" : "0UL") . (rxTrig ? "CY_PDM_PCM_INTR_RX_TRIGGER" : "") . ((rxTrig && (rxNotEmpty || rxOverflow || rxUnderflow)) ? " | " : "") . (rxNotEmpty ? "CY_PDM_PCM_INTR_RX_NOT_EMPTY" : "") . ((rxNotEmpty && (rxOverflow || rxUnderflow)) ? " | " : "") . (rxOverflow ? "CY_PDM_PCM_INTR_RX_OVERFLOW" : "") . ((rxOverflow && rxUnderflow) ? " | " : "") . (rxUnderflow ? "CY_PDM_PCM_INTR_RX_UNDERFLOW" : "")}`" visible="false" editable="false" desc="" /> 94 95 <!-- Output Data --> 96 <ParamBool id="signExtension" name="Output Data Sign Extension" group="Output Data" default="false" visible="true" editable="true" desc="When enabled - all the MSB of RX_FIFO_RD beyond the "word length" are filled by the sign bit value. Otherwise (when disabled) - all the MSBa are filled by 0." /> 97 <ParamChoice id="wordLength" name="Output Data Word Length, in Bits" group="Output Data" default="CY_PDM_PCM_WLEN_16_BIT" visible="true" editable="true" desc="PCM Word Length in number of bits."> 98 <Entry name="16" value="CY_PDM_PCM_WLEN_16_BIT" visible="true" /> 99 <Entry name="18" value="CY_PDM_PCM_WLEN_18_BIT" visible="true" /> 100 <Entry name="20" value="CY_PDM_PCM_WLEN_20_BIT" visible="true" /> 101 <Entry name="24" value="CY_PDM_PCM_WLEN_24_BIT" visible="true" /> 102 </ParamChoice> 103 104 <!-- Output FIFO --> 105 <ParamBool id="rxFifoDmaEnable" name="DMA Trigger Enable" group="Output FIFO" default="false" visible="true" editable="true" desc="Trigger event from output RX FIFO." /> 106 <ParamRange id="rxFifoTriggerLevel" name="Output FIFO Trigger Level" group="Output FIFO" default="0" min="0" max="`${((chanSelect eq CY_PDM_PCM_OUT_STEREO) ? 253 : 254)}`" resolution="1" visible="true" editable="true" desc="Trigger level. When the RX FIFO has more entries than the number of this field, a receiver trigger event is generated." /> 107 108 <!-- Soft Mute --> 109 <ParamBool id="softMuteEnable" name="Enable Soft Mute" group="Soft Mute" default="false" visible="true" editable="true" desc="Soft Mute Enable." /> 110 <ParamChoice id="softMuteFineGain" name="Select Soft Mute Fine Gain" group="Soft Mute" default="1" visible="true" editable="true" desc="Select fine gain step for smooth PGA or Soft-Mute attenuation transition."> 111 <Entry name="0.13dB" value="0" visible="true" /> 112 <Entry name="0.26dB" value="1" visible="true" /> 113 </ParamChoice> 114 <ParamChoice id="softMuteCycles" name="Soft Mute Cycles" group="Soft Mute" default="CY_PDM_PCM_SOFT_MUTE_CYCLES_96" visible="true" editable="true" desc="Set time step for gain change during PGA or soft mute operation in number of 1/a sampling rate."> 115 <Entry name="64" value="CY_PDM_PCM_SOFT_MUTE_CYCLES_64" visible="true" /> 116 <Entry name="96" value="CY_PDM_PCM_SOFT_MUTE_CYCLES_96" visible="true" /> 117 <Entry name="128" value="CY_PDM_PCM_SOFT_MUTE_CYCLES_128" visible="true" /> 118 <Entry name="160" value="CY_PDM_PCM_SOFT_MUTE_CYCLES_160" visible="true" /> 119 <Entry name="192" value="CY_PDM_PCM_SOFT_MUTE_CYCLES_192" visible="true" /> 120 <Entry name="256" value="CY_PDM_PCM_SOFT_MUTE_CYCLES_256" visible="true" /> 121 <Entry name="384" value="CY_PDM_PCM_SOFT_MUTE_CYCLES_384" visible="true" /> 122 <Entry name="512" value="CY_PDM_PCM_SOFT_MUTE_CYCLES_512" visible="true" /> 123 </ParamChoice> 124 125 <!-- Timing --> 126 <ParamSignal port="clock[0]" name="Clock" group="Timing" visible="true" desc="Input clock source." canBeEmpty="false" /> 127 <ParamChoice id="clkDiv" name="1st Clock Divisor" group="Timing" default="CY_PDM_PCM_CLK_DIV_BYPASS" visible="true" editable="true" desc="PDM CLK (FPDM_CLK) (1st divider). This configures a frequency of PDM CLK. The configured frequency is used to operate PDM core. I.e. the frequency is input to MCLKQ_CLOCK_DIV register. Note: configure a frequency of PDM CLK as lower than or equal 50MHz with this divider."> 128 <Entry name="1/1" value="CY_PDM_PCM_CLK_DIV_BYPASS" visible="true" /> 129 <Entry name="1/2" value="CY_PDM_PCM_CLK_DIV_1_2" visible="true" /> 130 <Entry name="1/3" value="CY_PDM_PCM_CLK_DIV_1_3" visible="true" /> 131 <Entry name="1/4" value="CY_PDM_PCM_CLK_DIV_1_4" visible="true" /> 132 </ParamChoice> 133 <ParamChoice id="mClkDiv" name="2nd Clock Divisor" group="Timing" default="CY_PDM_PCM_CLK_DIV_BYPASS" visible="true" editable="true" desc="MCLKQ divider (2nd divider)."> 134 <Entry name="1/1" value="CY_PDM_PCM_CLK_DIV_BYPASS" visible="true" /> 135 <Entry name="1/2" value="CY_PDM_PCM_CLK_DIV_1_2" visible="true" /> 136 <Entry name="1/3" value="CY_PDM_PCM_CLK_DIV_1_3" visible="true" /> 137 <Entry name="1/4" value="CY_PDM_PCM_CLK_DIV_1_4" visible="true" /> 138 </ParamChoice> 139 <ParamRange id="ckoDiv" name="3rd Clock Divisor" group="Timing" default="3" min="1" max="15" resolution="1" visible="true" editable="true" desc="PDM CKO (FPDM_CKO) clock divider (3rd divider): FPDM_CKO = MCLKQ / (CKO_CLOCK_DIV + 1)." /> 140 <ParamRange id="ckoDelay" name="Number of PDM_CLK Periods" group="Timing" default="0" min="0" max="7" resolution="1" visible="true" editable="true" desc="Phase difference from the rising edge of internal sampler clock (CLK_IS) to that of PDM_CKO clock." /> 141 <ParamRange id="sincDecRate" name="Sinc Decimation Rate" group="Timing" default="32" min="0" max="127" resolution="1" visible="true" editable="true" desc="SINC Decimation Rate. Oversampling Ratio = Decimation Rate = 2 X SINC_RATE." /> 142 <ParamBool id="extClock" name="Clock from terminal" group="Timing" default="false" visible="false" editable="true" desc="Clock from terminal." /> 143 144 <!-- Connections --> 145 <ParamSignal port="pdm_data[0]" name="PDM Data" group="Inputs" visible="true" desc="PDM input signal from PDM device for conversion. Can be connected to digital input pin." canBeEmpty="true" > 146 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 147 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 148 <Fixed value="CY_GPIO_DM_HIGHZ" /> 149 </Parameter> 150 </Constraint> 151 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 152 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 153 <Fixed value="CY_GPIO_DM_HIGHZ" /> 154 </Parameter> 155 </Constraint> 156 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 157 </ParamSignal> 158 <ParamSignal port="pdm_clk[0]" name="PDM Clock" group="Outputs" visible="true" desc="Clock output signal for PDM sampling. Can be connected to digital output pin." canBeEmpty="true" > 159 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 160 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 161 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 162 </Parameter> 163 </Constraint> 164 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 165 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 166 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 167 </Parameter> 168 </Constraint> 169 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 170 </ParamSignal> 171 <ParamSignal port="tr_pdm_rx_req[0]" name="DMA" group="Outputs" visible="`${rxFifoDmaEnable}`" desc="DMA transfer request signal. Visible when the DMA Trigger Enable is selected." canBeEmpty="true" > 172 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 173 <Parameter id="DriveModes" severity="DEFAULT" reason=""> 174 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 175 </Parameter> 176 </Constraint> 177 <Constraint type="ACCEPT" targetLocation="ioss\[\d+\]\.port\[\d+\]\.pin.*" valid="true" > 178 <Parameter id="DriveModes" severity="INFO" reason="The pin Drive Mode parameter does not match expected."> 179 <Fixed value="CY_GPIO_DM_STRONG_IN_OFF" /> 180 </Parameter> 181 </Constraint> 182 <Constraint type="ACCEPT" targetLocation=".*" valid="true" /> 183 </ParamSignal> 184 185 <ParamBool id="inFlash" name="Store Config in Flash" group="Advanced" default="true" visible="true" editable="true" desc="Controls whether the configuration structure is stored in flash (const, true) or SRAM (not const, false)." /> 186 187 <!-- PDM instance number --> 188 <ParamString id="InstNumber" name="Instance Number" group="Internal" default="`${getInstNumber("audioss")}`" visible="false" editable="false" desc="PDM Instance number." /> 189 <ParamBool id="hasAudioss1" name="hasAudioss1" group="Internal" default="`${hasBlock("audioss[1]")}`" visible="false" editable="false" desc="Check whether device has more than one audioss" /> 190 191 </Parameters> 192 <DRCs /> 193 <ConfigFirmware> 194 <ConfigInclude value="cy_pdm_pcm.h" include="true" /> 195 <ConfigInclude value="cyhal_hwmgr.h" include="true" guard="defined (CY_USING_HAL)" /> 196 197 <ConfigDefine name="`${INST_NAME}`_HW" value="PDM`${hasAudioss1 ? InstNumber : ""}`" public="true" include="true" /> 198 <ConfigDefine name="`${INST_NAME}`_IRQ" value="audioss_`${hasAudioss1 ? InstNumber . "_" : ""}`interrupt_pdm_IRQn" public="true" include="true" /> 199 200 <ConfigStruct name="`${INST_NAME . "_config"}`" type="cy_stc_pdm_pcm_config_t" const="`${inFlash}`" public="true" include="true" > 201 <Member name="clkDiv" value="`${clkDiv}`" /> 202 <Member name="mclkDiv" value="`${mClkDiv}`" /> 203 <Member name="ckoDiv" value="`${ckoDiv}`U" /> 204 <Member name="ckoDelay" value="`${ckoDelay}`U" /> 205 <Member name="sincDecRate" value="`${sincDecRate}`U" /> 206 <Member name="chanSelect" value="`${chanSelect}`" /> 207 <Member name="chanSwapEnable" value="`${chanSwap}`" /> 208 <Member name="highPassFilterGain" value="`${highPassFilterGain}`U" /> 209 <Member name="highPassDisable" value="`${highPassDisable}`" /> 210 <Member name="softMuteCycles" value="`${softMuteCycles}`" /> 211 <Member name="softMuteFineGain" value="`${softMuteFineGain}`UL" /> 212 <Member name="softMuteEnable" value="`${softMuteEnable}`" /> 213 <Member name="wordLen" value="`${wordLength}`" /> 214 <Member name="signExtension" value="`${signExtension}`" /> 215 <Member name="gainLeft" value="`${gainLeft}`" /> 216 <Member name="gainRight" value="`${gainRight}`" /> 217 <Member name="rxFifoTriggerLevel" value="`${rxFifoTriggerLevel}`U" /> 218 <Member name="dmaTriggerEnable" value="`${rxFifoDmaEnable}`" /> 219 <Member name="interruptMask" value="`${interruptMask}`" /> 220 </ConfigStruct> 221 222 <ConfigStruct name="`${INST_NAME}`_obj" type="cyhal_resource_inst_t" const="true" public="true" include="true" guard="defined (CY_USING_HAL)"> 223 <Member name="type" value="CYHAL_RSC_PDM" /> 224 <Member name="block_num" value="`${InstNumber}`U" /> 225 <Member name="channel_num" value="0U" /> 226 </ConfigStruct> 227 228 <ConfigInstruction value="cyhal_hwmgr_reserve(&`${INST_NAME}`_obj);" include="true" guard="defined (CY_USING_HAL)" /> 229 </ConfigFirmware> 230</Personality> 231
