1 /***************************************************************************//** 2 * \file cyhal_dma_impl.h 3 * 4 * \brief 5 * Implementation details of Infineon Datawire/DMAC DMA. 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #pragma once 28 29 #if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) || defined(CY_IP_M7CPUSS_DMAC) || defined(CY_IP_M7CPUSS_DMA) || defined(CY_IP_M0S8CPUSSV3_DMAC) || defined(CY_IP_MXAHBDMAC) || defined(CY_IP_MXDW) || defined(CY_IP_MXSAXIDMAC) 30 31 #if defined(__cplusplus) 32 extern "C" { 33 #endif 34 35 /** \addtogroup group_hal_impl_dma DMA (Direct Memory Access) 36 * \ingroup group_hal_impl 37 * \{ 38 * DW (DataWire) is one of two DMA hardware implementations for CAT1 (PSoC™ 6). 39 * DW is designed for low latency memory to peripheral or peripheral to memory 40 * transfers but can also perform memory to memory transfers and peripheral to 41 * peripheral transfers. 42 * 43 * DMAC (Direct Memory Access Controller) is the second of two DMA hardware 44 * implementations for CAT1 (PSoC™ 6). It is also the implementation that is 45 * found on CAT2 (PMG/PSoC™ 4) devices. DMAC is designed with high memory 46 * bandwidth for large memory to memory transfers but can perform peripheral 47 * to memory, memory to peripheral, and peripheral to peripheral transfers. 48 * 49 * Which DMA type is used is dependent on the exact hardware and number of DMA 50 * channels already in use. This implementation will attempt to use DMAC first 51 * for memory to memory transfers and Datawire otherwise but either type may be 52 * used. 53 * 54 * \section group_hal_impl_dma_interconnect Interconnect 55 * For both DW and DMAC each channel has a single input and a single output 56 * trigger available. The input, when triggered, initiates a DMA transfer of 57 * the configured type (note that this also affects the type transferred by the 58 * SW triggering). For output, a trigger is generated when a DMA transfer of 59 * the configured type is completed. For DW and DMAC neither input nor output 60 * triggers can be disabled completely but the signals do not, of course, have 61 * to be connected through the interconnect. 62 * 63 * */ 64 65 /** Default DMA channel priority */ 66 #define CYHAL_DMA_PRIORITY_DEFAULT CYHAL_DMA_PRIORITY_LOW 67 /** High DMA channel priority */ 68 #define CYHAL_DMA_PRIORITY_HIGH 0 69 /** Medium DMA channel priority */ 70 #define CYHAL_DMA_PRIORITY_MEDIUM 1 71 /** Low DMA channel priority */ 72 #define CYHAL_DMA_PRIORITY_LOW 3 73 74 /** \cond INTERNAL */ 75 /** Hal-Triggers uses bit 8 to denote a one to one trigger, whereas, the PDL 76 * SwTrigger function uses bit 5 to denote a one to one trigger. */ 77 #define _CYHAL_DMA_TRIGGERS_1TO1_MASK (0x80) 78 #define _CYHAL_DMA_PDL_TRIGGERS_1TO1_MASK (0x10) 79 /** \endcond */ 80 81 /** \} group_hal_impl_dma */ 82 83 #if defined(__cplusplus) 84 } 85 #endif 86 87 #endif /* defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) || defined(CY_IP_M7CPUSS_DMAC) || defined(CY_IP_M7CPUSS_DMA) || defined(CY_IP_M0S8CPUSSV3_DMAC) || defined(CY_IP_MXAHBDMAC) || defined(CY_IP_MXDW) */ 88
