1 /***************************************************************************//** 2 * \file cyhal_uart.h 3 * 4 * \brief 5 * Provides a high level interface for interacting with the Infineon UART. 6 * This interface abstracts out the chip specific details. If any chip specific 7 * functionality is necessary, or performance is critical the low level functions 8 * can be used directly. 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or 13 * an affiliate of Cypress Semiconductor Corporation 14 * 15 * SPDX-License-Identifier: Apache-2.0 16 * 17 * Licensed under the Apache License, Version 2.0 (the "License"); 18 * you may not use this file except in compliance with the License. 19 * You may obtain a copy of the License at 20 * 21 * http://www.apache.org/licenses/LICENSE-2.0 22 * 23 * Unless required by applicable law or agreed to in writing, software 24 * distributed under the License is distributed on an "AS IS" BASIS, 25 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 26 * See the License for the specific language governing permissions and 27 * limitations under the License. 28 *******************************************************************************/ 29 30 /** 31 * \addtogroup group_hal_uart UART (Universal Asynchronous Receiver-Transmitter) 32 * \ingroup group_hal 33 * \{ 34 * High level interface for interacting with the Universal Asynchronous Receiver-Transmitter (UART). 35 * 36 * The Universal Asynchronous Receiver/Transmitter (UART) protocol is an 37 * asynchronous serial interface protocol. UART communication is typically 38 * point-to-point. The UART interface consists of two signals: 39 * * TX: Transmitter output 40 * * RX: Receiver input 41 * 42 * Additionally, two side-band signals are used to implement flow control in 43 * UART. Note that the flow control applies only to TX functionality. 44 * * Clear to Send (CTS): This is an input signal to the transmitter. 45 * When active, it indicates that the slave is ready for the master to 46 * transmit data. 47 * * Ready to Send (RTS): This is an output signal from the receiver. When 48 * active, it indicates that the receiver is ready to receive data 49 * 50 * Flow control can be configured by providing cts / rts pins to cyhal_uart_init() and this will activate the feature in 51 * driver. In case flow control enablement status needs to be changed, cyhal_uart_enable_flow_control() function 52 * can be used. 53 * 54 * The data frame size, STOP bits and parity can be configured via \ref cyhal_uart_cfg_t. 55 * The UART contains dedicated hardware buffers for transmit and receive. Optionally, 56 * either of these can be augmented with a software buffer. This is done in scope of \ref cyhal_uart_init (if appropriate 57 * configuration was selected) and \ref cyhal_uart_config_software_buffer functions. 58 * 59 * \note For applications that require printing messages on a UART terminal using printf(), 60 * the <a href="https://github.com/infineon/retarget-io">retarget-io</a> utility library can be used directly. 61 * 62 * \section subsection_uart_features Features 63 * * Configurable UART baud rate - \ref cyhal_uart_set_baud 64 * * Configurable data frame size, STOP bits and parity - \ref cyhal_uart_cfg_t 65 * * Configurable interrupts and callback on UART events - \ref cyhal_uart_event_t 66 * \section subsection_uart_interrupts Interrupts and callbacks 67 * Interrupts are handled by callbacks based on events \ref cyhal_uart_event_t 68 * If an event is disabled, the underlying interrupt is still enabled. Enabling or disabling 69 * an event only enables or disables the callback. 70 * \note Care must be exercised when using the \ref CYHAL_UART_IRQ_RX_NOT_EMPTY event. 71 * The callback must read all available received data or the interrupt will not be cleared 72 * leading to the callback being immediately retriggered. 73 * \section subsection_uart_quickstart Quick Start 74 * \ref cyhal_uart_init is used for UART initialization 75 * 76 * \section subsection_uart_sample_snippets Code Snippets 77 * 78 * \subsection subsection_uart_snippet_1 Snippet 1: Initialization and Configuration 79 * The following snippet initializes the UART block and assigns the **tx**, **rx** pins and sets the baudrate. 80 * 81 * The snippet also shows how to use \ref cyhal_uart_write, \ref cyhal_uart_putc, \ref cyhal_uart_read API. 82 * 83 * \snippet hal_uart.c snippet_cyhal_uart_init 84 * 85 * \subsection subsection_uart_snippet_2 Snippet 2: Interrupts on UART events 86 * 87 * In the following snippet, UART events are handled in a callback function. 88 * The callback function has to be registered and then the events have to be enabled. 89 * 90 * \snippet hal_uart.c snippet_cyhal_uart_event 91 * 92 */ 93 94 #pragma once 95 96 #include <stdint.h> 97 #include <stdbool.h> 98 #include "cy_result.h" 99 #include "cyhal_hw_types.h" 100 101 #if defined(__cplusplus) 102 extern "C" { 103 #endif 104 105 /**************************************************************** 106 * Defines 107 *****************************************************************/ 108 109 /** \addtogroup group_hal_results_uart UART HAL Results 110 * UART specific return codes 111 * \ingroup group_hal_results 112 * \{ *//** 113 */ 114 /** The requested resource type is invalid */ 115 #define CYHAL_UART_RSLT_ERR_INVALID_PIN \ 116 (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_HAL, CYHAL_RSLT_MODULE_UART, 0)) 117 /** Failed to configure power management callback */ 118 #define CYHAL_UART_RSLT_ERR_PM_CALLBACK \ 119 (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_HAL, CYHAL_RSLT_MODULE_UART, 1)) 120 /** The getc call timed out with no received data */ 121 #define CY_RSLT_ERR_CSP_UART_GETC_TIMEOUT \ 122 (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_HAL, CYHAL_RSLT_MODULE_UART, 2)) 123 /** The actual baud rate is greater than 10% off the requested baud rate */ 124 #define CY_RSLT_WRN_CSP_UART_BAUD_TOLERANCE \ 125 (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_WARNING, CY_RSLT_MODULE_ABSTRACTION_HAL, CYHAL_RSLT_MODULE_UART, 3)) 126 /** The requested configuration is not supported on the current hardware */ 127 #define CYHAL_UART_RSLT_ERR_UNSUPPORTED_CONFIG \ 128 (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_HAL, CYHAL_RSLT_MODULE_UART, 4)) 129 /** The requested operation is not supported on the current hardware */ 130 #define CYHAL_UART_RSLT_ERR_UNSUPPORTED_OPERATION \ 131 (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_HAL, CYHAL_RSLT_MODULE_UART, 5)) 132 /** Can't make changes in user-provided clock */ 133 #define CYHAL_UART_RSLT_CLOCK_ERROR \ 134 (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_HAL, CYHAL_RSLT_MODULE_UART, 6)) 135 136 /** 137 * \} 138 */ 139 140 /** The baud rate to set to if no clock is specified in the init function */ 141 #define CYHAL_UART_DEFAULT_BAUD 115200 142 /** The maximum allowable difference between baud requested and actual baud **/ 143 #define CYHAL_UART_MAX_BAUD_PERCENT_DIFFERENCE 10 144 145 146 /**************************************************************** 147 * Enumerations 148 *****************************************************************/ 149 150 151 /** UART Parity */ 152 typedef enum 153 { 154 CYHAL_UART_PARITY_NONE, /**< UART has no parity check */ 155 CYHAL_UART_PARITY_EVEN, /**< UART has even parity check */ 156 CYHAL_UART_PARITY_ODD, /**< UART has odd parity check */ 157 } cyhal_uart_parity_t; 158 159 /** Enum to enable/disable/report interrupt cause flags. */ 160 typedef enum 161 { 162 CYHAL_UART_IRQ_NONE = 0, //!< No interrupt 163 CYHAL_UART_IRQ_TX_TRANSMIT_IN_FIFO = 1 << 1, //!< All TX data from transmit has been moved to the HW TX FIFO buffer 164 CYHAL_UART_IRQ_TX_DONE = 1 << 2, //!< All TX data has been transmitted (applicable only for cyhal_uart_write_async) 165 CYHAL_UART_IRQ_TX_ERROR = 1 << 3, //!< An error occurred during TX 166 CYHAL_UART_IRQ_RX_FULL = 1 << 4, //!< The SW RX buffer (if used) is full. Additional data will be stored in the HW RX FIFO buffer 167 CYHAL_UART_IRQ_RX_DONE = 1 << 5, //!< All RX data has been received (applicable only for cyhal_uart_read_async) 168 CYHAL_UART_IRQ_RX_ERROR = 1 << 6, //!< An error occurred during RX 169 CYHAL_UART_IRQ_RX_NOT_EMPTY = 1 << 7, //!< The HW RX FIFO buffer is not empty 170 CYHAL_UART_IRQ_TX_EMPTY = 1 << 8, //!< The HW TX FIFO buffer is empty 171 CYHAL_UART_IRQ_TX_FIFO = 1 << 9, //!< Number of entries in the HW TX FIFO is less than the TX FIFO trigger level 172 CYHAL_UART_IRQ_RX_FIFO = 1 << 10, //!< Number of entries in the HW RX FIFO is more than the RX FIFO trigger level 173 } cyhal_uart_event_t; 174 175 /** UART FIFO type */ 176 typedef enum 177 { 178 CYHAL_UART_FIFO_RX, //!< Set RX FIFO level 179 CYHAL_UART_FIFO_TX, //!< Set TX FIFO level 180 } cyhal_uart_fifo_type_t; 181 182 /** Enum of possible output signals from a UART */ 183 typedef enum 184 { 185 CYHAL_UART_OUTPUT_TRIGGER_RX_FIFO_LEVEL_REACHED, //!< Output the RX FIFO signal which is triggered when the receive FIFO has more entries than the configured level. 186 CYHAL_UART_OUTPUT_TRIGGER_TX_FIFO_LEVEL_REACHED, //!< Output the TX FIFO signal which is triggered when the transmit FIFO has less entries than the configured level. 187 } cyhal_uart_output_t; 188 189 /**************************************************************** 190 * Typedef 191 *****************************************************************/ 192 193 /** @brief Initial UART configuration */ 194 195 typedef struct 196 { 197 uint32_t data_bits; //!< The number of data bits (generally 8 or 9) 198 uint32_t stop_bits; //!< The number of stop bits (generally 0 or 1) 199 cyhal_uart_parity_t parity; //!< The parity 200 uint8_t *rx_buffer; //!< The rx software buffer pointer, if NULL, no rx software buffer will be used 201 uint32_t rx_buffer_size; //!< The number of bytes in the rx software buffer 202 } cyhal_uart_cfg_t; 203 204 205 /** UART callback function type */ 206 typedef void (*cyhal_uart_event_callback_t)(void *callback_arg, cyhal_uart_event_t event); 207 208 /******************************************************************************* 209 * Functions 210 *******************************************************************************/ 211 212 /** Initialize the UART peripheral. 213 * 214 * \note This will set the baud rate to a default of \ref CYHAL_UART_DEFAULT_BAUD. This can 215 * be changed by calling \ref cyhal_uart_set_baud. 216 * \note Function activates the flow control feature if CTS / RTS pins are provided. 217 * 218 * @param[out] obj Pointer to a UART object. The caller must allocate the memory 219 * for this object but the init function will initialize its contents. 220 * @param[in] tx The TX pin name, if no TX pin use NC 221 * @param[in] rx The RX pin name, if no RX pin use NC 222 * @param[in] cts The CTS pin name, if no CTS pin use NC 223 * @param[in] rts The RTS pin name, if no RTS pin use NC 224 * @param[in] clk The clock to use can be shared. If not provided, a new clock will be 225 * allocated and the default baud rate will be set 226 * @param[in] cfg The UART configuration data for data bits, stop bits and parity. 227 * If not provided, default values of (8, 1, none) will be used 228 * @return The status of the init request 229 */ 230 cy_rslt_t cyhal_uart_init(cyhal_uart_t *obj, cyhal_gpio_t tx, cyhal_gpio_t rx, cyhal_gpio_t cts, cyhal_gpio_t rts, const cyhal_clock_t *clk, const cyhal_uart_cfg_t *cfg); 231 232 /** Release the UART peripheral. 233 * 234 * @param[in,out] obj The UART object 235 */ 236 void cyhal_uart_free(cyhal_uart_t *obj); 237 238 /** Configure the baud rate 239 * 240 * @note This function should only be called if a shared clock divider is not used i.e. the clock 241 * parameter is set to NULL when calling \ref cyhal_uart_init. 242 * 243 * @param[in,out] obj The UART object 244 * @param[in] baudrate The baud rate to be configured 245 * @param[out] actualbaud The actual baud rate achieved by the HAL 246 * Specify NULL if you do not want this information. 247 * @return The status of the set_baud request 248 */ 249 cy_rslt_t cyhal_uart_set_baud(cyhal_uart_t *obj, uint32_t baudrate, uint32_t *actualbaud); 250 251 /** Configure the data bits, stop bits, and parity 252 * 253 * @param[in,out] obj The UART object 254 * @param[in] cfg The UART configuration data for data bits, stop bits and parity. 255 * rx_buffer and rx_buffer_size are ignored. 256 * @return The status of the configure request 257 */ 258 cy_rslt_t cyhal_uart_configure(cyhal_uart_t *obj, const cyhal_uart_cfg_t *cfg); 259 260 /** Get a character. This is a blocking call which waits till a character is received. 261 * 262 * @param[in] obj The UART object 263 * @param[out] value The value read from the serial port 264 * @param[in] timeout The time in ms to spend attempting to receive from serial port. 265 * Zero is wait forever 266 * @return The status of the getc request 267 */ 268 cy_rslt_t cyhal_uart_getc(cyhal_uart_t *obj, uint8_t *value, uint32_t timeout); 269 270 /** Send a character. This is a blocking call which waits till the character is sent out from the UART completely. 271 * 272 * @param[in] obj The UART object 273 * @param[in] value The character to be sent 274 * @return The status of the putc request 275 */ 276 cy_rslt_t cyhal_uart_putc(cyhal_uart_t *obj, uint32_t value); 277 278 /** Check the number of bytes available to read from the receive buffers 279 * 280 * @param[in] obj The UART object 281 * @return The number of readable bytes 282 */ 283 uint32_t cyhal_uart_readable(cyhal_uart_t *obj); 284 285 /** Check the number of bytes than can be written to the transmit buffer 286 * 287 * @param[in] obj The UART object 288 * @return The number of bytes that can be written 289 */ 290 uint32_t cyhal_uart_writable(cyhal_uart_t *obj); 291 292 /** Clear the UART buffers 293 * 294 * @param[in] obj The UART object 295 * @return The status of the clear request 296 */ 297 cy_rslt_t cyhal_uart_clear(cyhal_uart_t *obj); 298 299 /** Configure the UART for flow control. It sets flow control in the hardware 300 * if a UART peripheral supports it, otherwise software emulation is used. 301 * 302 * @param[in,out] obj The UART object 303 * @param[in] enable_cts Enable or disable CTS functionality 304 * @param[in] enable_rts Enable or disable RTS functionality 305 * @return The status of the enable_flow_control request 306 */ 307 cy_rslt_t cyhal_uart_enable_flow_control(cyhal_uart_t *obj, bool enable_cts, bool enable_rts); 308 309 /** Begin synchronous TX transfer. 310 * 311 * This will write either `length` bytes or until the write buffer is full, whichever is less, 312 * then return. The value pointed to by `length` will be updated to reflect the number of bytes 313 * that was actually written. 314 * 315 * @param[in] obj The UART object 316 * @param[in] tx The transmit buffer 317 * @param[in,out] tx_length [in] The number of bytes to transmit, [out] number actually transmitted 318 * @return The status of the tx request 319 */ 320 cy_rslt_t cyhal_uart_write(cyhal_uart_t *obj, void *tx, size_t *tx_length); 321 322 /** Begin synchronous RX transfer (enable interrupt for data collecting) 323 * 324 * This will read either `length` bytes or the number of bytes that are currently available in the 325 * receive buffer, whichever is less, then return. The value pointed to by `length` will be updated 326 * to reflect the number of bytes that was actually read. 327 * 328 * @param[in] obj The UART object 329 * @param[in] rx The receive buffer 330 * @param[in,out] rx_length [in] The number of bytes to receive, [out] number actually received 331 * @return The status of the rx request 332 */ 333 cy_rslt_t cyhal_uart_read(cyhal_uart_t *obj, void *rx, size_t *rx_length); 334 335 /** Set the mechanism that is used to perform UART asynchronous transfers. The default is SW. 336 * @warning The effect of calling this function while an async transfer is pending is undefined. 337 * 338 * @param[in] obj The UART object 339 * @param[in] mode The transfer mode 340 * @param[in] dma_priority The priority, if DMA is used. Valid values are the same as for @ref cyhal_dma_init. 341 * If DMA is not selected, the only valid value is CYHAL_DMA_PRIORITY_DEFAULT, and no 342 guarantees are made about prioritization. 343 * @return The status of the set mode request 344 */ 345 cy_rslt_t cyhal_uart_set_async_mode(cyhal_uart_t *obj, cyhal_async_mode_t mode, uint8_t dma_priority); 346 347 /** Begin asynchronous TX transfer. 348 * 349 * This will transfer `length` bytes into the buffer pointed to by `tx` in the background. When the 350 * requested quantity of data has been transferred, the @ref CYHAL_UART_IRQ_TX_TRANSMIT_IN_FIFO event will 351 * be raised. The transmit buffer is a user defined buffer that will be sent on the UART. The user 352 * must register a callback with \ref cyhal_uart_register_callback. If desired, TX callback 353 * events can be enabled using \ref cyhal_uart_enable_event with the appropriate events. 354 * 355 * If D-cache is enabled and data Cache line is 32 bytes, 356 * the user needs to make sure that the tx pointer passed to the cyhal_uart_write_async 357 * function points to a 32 byte aligned array of words that contains the buffer data. 358 * The size of buffer data must be a multiple of 32 bytes to ensure cache coherency. 359 * CY_ALIGN(__SCB_DCACHE_LINE_SIZE) macro can be used for 32 byte alignment. 360 * 361 * Refer to \ref DCACHE_Management for more information. 362 * 363 * @param[in] obj The UART object 364 * @param[in] tx The transmit buffer 365 * @param[in] length The number of bytes to transmit 366 * @return The status of the tx_async request 367 */ 368 cy_rslt_t cyhal_uart_write_async(cyhal_uart_t *obj, void *tx, size_t length); 369 370 /** Begin asynchronous RX transfer. 371 * 372 * This will transfer `length` bytes into the buffer pointed to by `rx` in the background. When the 373 * requested quantity of data has been transferred, the @ref CYHAL_UART_IRQ_RX_DONE event will be raised. 374 * Received data is placed in the user specified buffer. The user must register a callback with 375 * \ref cyhal_uart_register_callback. RX callback events can be enabled using \ref 376 * cyhal_uart_enable_event with the appropriate events. 377 * 378 * If D-cache is enabled and data Cache line is 32 bytes, 379 * the user needs to make sure that the tx pointer passed to the cyhal_uart_read_async 380 * function points to a 32 byte aligned array of words that contains the buffer data. 381 * The size of buffer data must be a multiple of 32 bytes to ensure cache coherency. 382 * CY_ALIGN(__SCB_DCACHE_LINE_SIZE) macro can be used for 32 byte alignment. 383 * 384 * Refer to \ref DCACHE_Management for more information. 385 * 386 * @param[in] obj The UART object 387 * @param[out] rx The user specified receive buffer 388 * @param[in] length The number of bytes to receive 389 * @return The status of the rx_async request 390 */ 391 cy_rslt_t cyhal_uart_read_async(cyhal_uart_t *obj, void *rx, size_t length); 392 393 /** Determines if the UART peripheral is currently in use for TX 394 * 395 * @param[in] obj The UART object 396 * @return TX channel active status (active=true) 397 */ 398 bool cyhal_uart_is_tx_active(cyhal_uart_t *obj); 399 400 /** Determines if the UART peripheral is currently in use for RX 401 * 402 * @param[in] obj The UART object 403 * @return RX channel active status (active=true) 404 */ 405 bool cyhal_uart_is_rx_active(cyhal_uart_t *obj); 406 407 /** Abort the ongoing TX transaction. 408 * 409 * Disables the TX interrupt and flushes the TX hardware buffer if TX FIFO is used. 410 * 411 * @param[in] obj The UART object 412 * @return The status of the tx_abort request 413 */ 414 cy_rslt_t cyhal_uart_write_abort(cyhal_uart_t *obj); 415 416 /** Abort the ongoing read transaction. 417 * 418 * Disables the RX interrupt and flushes the RX hardware buffer if RX FIFO is used. 419 * 420 * @param[in] obj The UART object 421 * @return The status of the read_abort request 422 */ 423 cy_rslt_t cyhal_uart_read_abort(cyhal_uart_t *obj); 424 425 /** Register a uart callback handler 426 * 427 * This function will be called when one of the events enabled by \ref cyhal_uart_enable_event occurs. 428 * 429 * @param[in] obj The UART object 430 * @param[in] callback The callback handler which will be invoked when the interrupt fires 431 * @param[in] callback_arg Generic argument that will be provided to the callback when called 432 */ 433 void cyhal_uart_register_callback(cyhal_uart_t *obj, cyhal_uart_event_callback_t callback, void *callback_arg); 434 435 /** Enable or disable specified UART events. 436 * 437 * When an enabled event occurs, the function specified by \ref cyhal_uart_register_callback will be called. 438 * 439 * @param[in] obj The UART object 440 * @param[in] event The uart event type, this argument supports the bitwise-or of multiple enum flag values 441 * @param[in] intr_priority The priority for NVIC interrupt events 442 * @param[in] enable True to turn on interrupts, False to turn off 443 */ 444 void cyhal_uart_enable_event(cyhal_uart_t *obj, cyhal_uart_event_t event, uint8_t intr_priority, bool enable); 445 446 /** Sets a threshold level for a FIFO that will generate an interrupt and a 447 * trigger output. 448 * 449 * The RX FIFO interrupt and trigger will be activated when 450 * the receive FIFO has more entries than the threshold. The TX FIFO interrupt 451 * and trigger will be activated when the transmit FIFO has less entries than 452 * the threshold. 453 * 454 * @param[in] obj The UART object 455 * @param[in] type FIFO type to set level for 456 * @param[in] level Level threshold to set 457 * @return The status of the level set 458 * */ 459 cy_rslt_t cyhal_uart_set_fifo_level(cyhal_uart_t *obj, cyhal_uart_fifo_type_t type, uint16_t level); 460 461 /** Enables the specified output signal from a UART. 462 * 463 * @param[in] obj The UART object 464 * @param[in] output Which output signal to enable 465 * @param[out] source Pointer to user-allocated source signal object 466 * which will be initialized by enable_output. \p source should be passed to 467 * (dis)connect_digital functions to (dis)connect the associated endpoints. 468 * @return The status of the output enable 469 * */ 470 cy_rslt_t cyhal_uart_enable_output(cyhal_uart_t *obj, cyhal_uart_output_t output, cyhal_source_t *source); 471 472 /** Disables the specified output signal from a UART 473 * 474 * @param[in] obj The UART object 475 * @param[in] output Which output signal to disable 476 * @return The status of the output disable 477 * */ 478 cy_rslt_t cyhal_uart_disable_output(cyhal_uart_t *obj, cyhal_uart_output_t output); 479 480 /** Initialize the UART peripheral using a configurator generated configuration struct. 481 * 482 * @param[in] obj The UART peripheral to configure 483 * @param[in] cfg Configuration structure generated by a configurator. 484 * @return The status of the operation 485 */ 486 cy_rslt_t cyhal_uart_init_cfg(cyhal_uart_t *obj, const cyhal_uart_configurator_t *cfg); 487 488 /** Configure UART RX software buffer, which will extend the hardware RX FIFO buffer only 489 * for SW async mode. \ref cyhal_uart_init function does 490 * not require this function call if a non-null value was provided for `rx_buffer`. 491 * 492 * @param[in] obj The UART peripheral to configure 493 * @param[in] rx_buffer The RX software buffer pointer 494 * @param[in] rx_buffer_size The number of bytes in the RX software buffer 495 * @return The status of the operation 496 */ 497 cy_rslt_t cyhal_uart_config_software_buffer(cyhal_uart_t *obj, uint8_t *rx_buffer, uint32_t rx_buffer_size); 498 499 #if defined(__cplusplus) 500 } 501 #endif 502 503 #ifdef CYHAL_UART_IMPL_HEADER 504 #include CYHAL_UART_IMPL_HEADER 505 #endif /* CYHAL_UART_IMPL_HEADER */ 506 507 /** \} group_hal_uart */ 508
