1 /***************************************************************************//** 2 * \file cyhal_xmc7200_176_teqfp.c 3 * 4 * \brief 5 * XMC7200 device GPIO HAL header for 176-TEQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_XMC7200_176_TEQFP_H_) 31 #include "pin_packages/cyhal_xmc7200_176_teqfp.h" 32 33 /* Pin connections */ 34 /* Connections for: audioss_clk_i2s_if */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[3] = { 36 {0u, 0u, P12_1, P12_1_AUDIOSS0_CLK_I2S_IF}, 37 {1u, 0u, P13_4, P13_4_AUDIOSS1_CLK_I2S_IF}, 38 {2u, 0u, P15_0, P15_0_AUDIOSS2_CLK_I2S_IF}, 39 }; 40 41 /* Connections for: audioss_mclk */ 42 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_mclk[3] = { 43 {0u, 0u, P11_0, P11_0_AUDIOSS0_MCLK}, 44 {1u, 0u, P13_0, P13_0_AUDIOSS1_MCLK}, 45 {2u, 0u, P14_0, P14_0_AUDIOSS2_MCLK}, 46 }; 47 48 /* Connections for: audioss_rx_sck */ 49 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[3] = { 50 {0u, 0u, P12_2, P12_2_AUDIOSS0_RX_SCK}, 51 {1u, 0u, P13_5, P13_5_AUDIOSS1_RX_SCK}, 52 {2u, 0u, P15_1, P15_1_AUDIOSS2_RX_SCK}, 53 }; 54 55 /* Connections for: audioss_rx_sdi */ 56 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[3] = { 57 {0u, 0u, P12_4, P12_4_AUDIOSS0_RX_SDI}, 58 {1u, 0u, P13_7, P13_7_AUDIOSS1_RX_SDI}, 59 {2u, 0u, P15_3, P15_3_AUDIOSS2_RX_SDI}, 60 }; 61 62 /* Connections for: audioss_rx_ws */ 63 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[3] = { 64 {0u, 0u, P12_3, P12_3_AUDIOSS0_RX_WS}, 65 {1u, 0u, P13_6, P13_6_AUDIOSS1_RX_WS}, 66 {2u, 0u, P15_2, P15_2_AUDIOSS2_RX_WS}, 67 }; 68 69 /* Connections for: audioss_tx_sck */ 70 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3] = { 71 {0u, 0u, P11_1, P11_1_AUDIOSS0_TX_SCK}, 72 {1u, 0u, P13_1, P13_1_AUDIOSS1_TX_SCK}, 73 {2u, 0u, P14_1, P14_1_AUDIOSS2_TX_SCK}, 74 }; 75 76 /* Connections for: audioss_tx_sdo */ 77 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[3] = { 78 {0u, 0u, P12_0, P12_0_AUDIOSS0_TX_SDO}, 79 {1u, 0u, P13_3, P13_3_AUDIOSS1_TX_SDO}, 80 {2u, 0u, P14_5, P14_5_AUDIOSS2_TX_SDO}, 81 }; 82 83 /* Connections for: audioss_tx_ws */ 84 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[3] = { 85 {0u, 0u, P11_2, P11_2_AUDIOSS0_TX_WS}, 86 {1u, 0u, P13_2, P13_2_AUDIOSS1_TX_WS}, 87 {2u, 0u, P14_4, P14_4_AUDIOSS2_TX_WS}, 88 }; 89 90 /* Connections for: canfd_ttcan_rx */ 91 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[18] = { 92 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1}, 93 {0u, 0u, P2_1, P2_1_CANFD0_TTCAN_RX0}, 94 {0u, 3u, P3_1, P3_1_CANFD0_TTCAN_RX3}, 95 {0u, 1u, P4_4, P4_4_CANFD0_TTCAN_RX1}, 96 {0u, 2u, P6_3, P6_3_CANFD0_TTCAN_RX2}, 97 {0u, 4u, P7_4, P7_4_CANFD0_TTCAN_RX4}, 98 {0u, 0u, P8_1, P8_1_CANFD0_TTCAN_RX0}, 99 {0u, 2u, P12_1, P12_1_CANFD0_TTCAN_RX2}, 100 {1u, 1u, P12_5, P12_5_CANFD1_TTCAN_RX1}, 101 {1u, 0u, P14_1, P14_1_CANFD1_TTCAN_RX0}, 102 {1u, 3u, P15_1, P15_1_CANFD1_TTCAN_RX3}, 103 {1u, 1u, P17_1, P17_1_CANFD1_TTCAN_RX1}, 104 {1u, 2u, P18_7, P18_7_CANFD1_TTCAN_RX2}, 105 {1u, 3u, P19_1, P19_1_CANFD1_TTCAN_RX3}, 106 {1u, 2u, P20_4, P20_4_CANFD1_TTCAN_RX2}, 107 {1u, 4u, P20_7, P20_7_CANFD1_TTCAN_RX4}, 108 {1u, 1u, P22_1, P22_1_CANFD1_TTCAN_RX1}, 109 {1u, 0u, P23_1, P23_1_CANFD1_TTCAN_RX0}, 110 }; 111 112 /* Connections for: canfd_ttcan_tx */ 113 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[18] = { 114 {0u, 1u, P0_2, P0_2_CANFD0_TTCAN_TX1}, 115 {0u, 0u, P2_0, P2_0_CANFD0_TTCAN_TX0}, 116 {0u, 3u, P3_0, P3_0_CANFD0_TTCAN_TX3}, 117 {0u, 1u, P4_3, P4_3_CANFD0_TTCAN_TX1}, 118 {0u, 2u, P6_2, P6_2_CANFD0_TTCAN_TX2}, 119 {0u, 4u, P7_3, P7_3_CANFD0_TTCAN_TX4}, 120 {0u, 0u, P8_0, P8_0_CANFD0_TTCAN_TX0}, 121 {0u, 2u, P12_0, P12_0_CANFD0_TTCAN_TX2}, 122 {1u, 1u, P12_4, P12_4_CANFD1_TTCAN_TX1}, 123 {1u, 0u, P14_0, P14_0_CANFD1_TTCAN_TX0}, 124 {1u, 3u, P15_0, P15_0_CANFD1_TTCAN_TX3}, 125 {1u, 1u, P17_0, P17_0_CANFD1_TTCAN_TX1}, 126 {1u, 2u, P18_6, P18_6_CANFD1_TTCAN_TX2}, 127 {1u, 3u, P19_0, P19_0_CANFD1_TTCAN_TX3}, 128 {1u, 2u, P20_3, P20_3_CANFD1_TTCAN_TX2}, 129 {1u, 4u, P20_6, P20_6_CANFD1_TTCAN_TX4}, 130 {1u, 1u, P21_5, P21_5_CANFD1_TTCAN_TX1}, 131 {1u, 0u, P23_0, P23_0_CANFD1_TTCAN_TX0}, 132 }; 133 134 /* Connections for: cpuss_cal_sup_nz */ 135 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[3] = { 136 {0u, 0u, P6_3, P6_3_CPUSS_CAL_SUP_NZ}, 137 {0u, 0u, P21_7, P21_7_CPUSS_CAL_SUP_NZ}, 138 {0u, 0u, P23_7, P23_7_CPUSS_CAL_SUP_NZ}, 139 }; 140 141 /* Connections for: cpuss_clk_fm_pump */ 142 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 143 {0u, 0u, P21_6, P21_6_CPUSS_CLK_FM_PUMP}, 144 }; 145 146 /* Connections for: cpuss_fault_out */ 147 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[8] = { 148 {0u, 0u, P18_0, P18_0_CPUSS_FAULT_OUT0}, 149 {0u, 1u, P18_1, P18_1_CPUSS_FAULT_OUT1}, 150 {0u, 2u, P19_0, P19_0_CPUSS_FAULT_OUT2}, 151 {0u, 3u, P19_1, P19_1_CPUSS_FAULT_OUT3}, 152 {0u, 0u, P23_0, P23_0_CPUSS_FAULT_OUT0}, 153 {0u, 1u, P23_1, P23_1_CPUSS_FAULT_OUT1}, 154 {0u, 2u, P23_2, P23_2_CPUSS_FAULT_OUT2}, 155 {0u, 3u, P23_3, P23_3_CPUSS_FAULT_OUT3}, 156 }; 157 158 /* Connections for: cpuss_swj_swclk_tclk */ 159 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1] = { 160 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK}, 161 }; 162 163 /* Connections for: cpuss_swj_swdio_tms */ 164 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 165 {0u, 0u, P23_6, P23_6_CPUSS_SWJ_SWDIO_TMS}, 166 }; 167 168 /* Connections for: cpuss_swj_swdoe_tdi */ 169 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 170 {0u, 0u, P23_7, P23_7_CPUSS_SWJ_SWDOE_TDI}, 171 }; 172 173 /* Connections for: cpuss_swj_swo_tdo */ 174 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 175 {0u, 0u, P23_4, P23_4_CPUSS_SWJ_SWO_TDO}, 176 }; 177 178 /* Connections for: cpuss_swj_trstn */ 179 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1] = { 180 {0u, 0u, P2_0, P2_0_CPUSS_SWJ_TRSTN}, 181 }; 182 183 /* Connections for: cpuss_trace_clock */ 184 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2] = { 185 {0u, 0u, P18_3, P18_3_CPUSS_TRACE_CLOCK}, 186 {0u, 0u, P22_4, P22_4_CPUSS_TRACE_CLOCK}, 187 }; 188 189 /* Connections for: cpuss_trace_data */ 190 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8] = { 191 {0u, 0u, P18_4, P18_4_CPUSS_TRACE_DATA0}, 192 {0u, 1u, P18_5, P18_5_CPUSS_TRACE_DATA1}, 193 {0u, 2u, P18_6, P18_6_CPUSS_TRACE_DATA2}, 194 {0u, 3u, P18_7, P18_7_CPUSS_TRACE_DATA3}, 195 {0u, 0u, P21_5, P21_5_CPUSS_TRACE_DATA0}, 196 {0u, 1u, P22_1, P22_1_CPUSS_TRACE_DATA1}, 197 {0u, 2u, P22_2, P22_2_CPUSS_TRACE_DATA2}, 198 {0u, 3u, P22_3, P22_3_CPUSS_TRACE_DATA3}, 199 }; 200 201 /* Connections for: eth_eth_tsu_timer_cmp_val */ 202 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_eth_tsu_timer_cmp_val[1] = { 203 {0u, 0u, P2_3, P2_3_ETH0_ETH_TSU_TIMER_CMP_VAL}, 204 }; 205 206 /* Connections for: eth_mdc */ 207 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdc[1] = { 208 {0u, 0u, P3_1, P3_1_ETH0_MDC}, 209 }; 210 211 /* Connections for: eth_mdio */ 212 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdio[1] = { 213 {0u, 0u, P3_0, P3_0_ETH0_MDIO}, 214 }; 215 216 /* Connections for: eth_ref_clk */ 217 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_ref_clk[1] = { 218 {0u, 0u, P18_0, P18_0_ETH0_REF_CLK}, 219 }; 220 221 /* Connections for: eth_rx_clk */ 222 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_clk[1] = { 223 {0u, 0u, P23_3, P23_3_ETH0_RX_CLK}, 224 }; 225 226 /* Connections for: eth_rx_ctl */ 227 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_ctl[1] = { 228 {0u, 0u, P21_5, P21_5_ETH0_RX_CTL}, 229 }; 230 231 /* Connections for: eth_rx_er */ 232 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_er[1] = { 233 {0u, 0u, P2_2, P2_2_ETH0_RX_ER}, 234 }; 235 236 /* Connections for: eth_rxd */ 237 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rxd[4] = { 238 {0u, 0u, P19_0, P19_0_ETH0_RXD0}, 239 {0u, 1u, P19_1, P19_1_ETH0_RXD1}, 240 {0u, 2u, P19_2, P19_2_ETH0_RXD2}, 241 {0u, 3u, P19_3, P19_3_ETH0_RXD3}, 242 }; 243 244 /* Connections for: eth_tx_clk */ 245 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_clk[1] = { 246 {0u, 0u, P18_3, P18_3_ETH0_TX_CLK}, 247 }; 248 249 /* Connections for: eth_tx_ctl */ 250 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_ctl[1] = { 251 {0u, 0u, P18_1, P18_1_ETH0_TX_CTL}, 252 }; 253 254 /* Connections for: eth_tx_er */ 255 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_er[1] = { 256 {0u, 0u, P18_2, P18_2_ETH0_TX_ER}, 257 }; 258 259 /* Connections for: eth_txd */ 260 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_txd[4] = { 261 {0u, 0u, P18_4, P18_4_ETH0_TXD0}, 262 {0u, 1u, P18_5, P18_5_ETH0_TXD1}, 263 {0u, 2u, P18_6, P18_6_ETH0_TXD2}, 264 {0u, 3u, P18_7, P18_7_ETH0_TXD3}, 265 }; 266 267 /* Connections for: flexray_rxda */ 268 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_rxda[1] = { 269 {0u, 0u, P10_2, P10_2_FLEXRAY0_RXDA}, 270 }; 271 272 /* Connections for: flexray_rxdb */ 273 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_rxdb[1] = { 274 {0u, 0u, P10_5, P10_5_FLEXRAY0_RXDB}, 275 }; 276 277 /* Connections for: flexray_txda */ 278 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txda[1] = { 279 {0u, 0u, P10_3, P10_3_FLEXRAY0_TXDA}, 280 }; 281 282 /* Connections for: flexray_txdb */ 283 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txdb[1] = { 284 {0u, 0u, P10_6, P10_6_FLEXRAY0_TXDB}, 285 }; 286 287 /* Connections for: flexray_txena_n */ 288 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txena_n[1] = { 289 {0u, 0u, P10_4, P10_4_FLEXRAY0_TXENA_N}, 290 }; 291 292 /* Connections for: flexray_txenb_n */ 293 const cyhal_resource_pin_mapping_t cyhal_pin_map_flexray_txenb_n[1] = { 294 {0u, 0u, P10_7, P10_7_FLEXRAY0_TXENB_N}, 295 }; 296 297 /* Connections for: lin_lin_en */ 298 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[27] = { 299 {0u, 1u, P0_2, P0_2_LIN0_LIN_EN1}, 300 {0u, 0u, P2_2, P2_2_LIN0_LIN_EN0}, 301 {0u, 5u, P2_5, P2_5_LIN0_LIN_EN5}, 302 {0u, 1u, P4_2, P4_2_LIN0_LIN_EN1}, 303 {0u, 7u, P5_2, P5_2_LIN0_LIN_EN7}, 304 {0u, 2u, P5_5, P5_5_LIN0_LIN_EN2}, 305 {0u, 9u, P6_0, P6_0_LIN0_LIN_EN9}, 306 {0u, 3u, P6_2, P6_2_LIN0_LIN_EN3}, 307 {0u, 4u, P6_5, P6_5_LIN0_LIN_EN4}, 308 {0u, 4u, P7_2, P7_2_LIN0_LIN_EN4}, 309 {0u, 10u, P7_7, P7_7_LIN0_LIN_EN10}, 310 {0u, 2u, P8_2, P8_2_LIN0_LIN_EN2}, 311 {0u, 16u, P9_0, P9_0_LIN0_LIN_EN16}, 312 {0u, 12u, P9_3, P9_3_LIN0_LIN_EN12}, 313 {0u, 8u, P10_4, P10_4_LIN0_LIN_EN8}, 314 {0u, 13u, P10_7, P10_7_LIN0_LIN_EN13}, 315 {0u, 6u, P12_1, P12_1_LIN0_LIN_EN6}, 316 {0u, 3u, P13_2, P13_2_LIN0_LIN_EN3}, 317 {0u, 8u, P13_6, P13_6_LIN0_LIN_EN8}, 318 {0u, 6u, P14_4, P14_4_LIN0_LIN_EN6}, 319 {0u, 14u, P14_7, P14_7_LIN0_LIN_EN14}, 320 {0u, 11u, P17_2, P17_2_LIN0_LIN_EN11}, 321 {0u, 15u, P17_7, P17_7_LIN0_LIN_EN15}, 322 {0u, 5u, P20_2, P20_2_LIN0_LIN_EN5}, 323 {0u, 0u, P21_7, P21_7_LIN0_LIN_EN0}, 324 {0u, 7u, P22_7, P22_7_LIN0_LIN_EN7}, 325 {0u, 9u, P23_7, P23_7_LIN0_LIN_EN9}, 326 }; 327 328 /* Connections for: lin_lin_rx */ 329 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[37] = { 330 {0u, 1u, P0_0, P0_0_LIN0_LIN_RX1}, 331 {0u, 0u, P1_2, P1_2_LIN0_LIN_RX0}, 332 {0u, 0u, P2_0, P2_0_LIN0_LIN_RX0}, 333 {0u, 5u, P2_3, P2_3_LIN0_LIN_RX5}, 334 {0u, 1u, P3_4, P3_4_LIN0_LIN_RX1}, 335 {0u, 1u, P4_0, P4_0_LIN0_LIN_RX1}, 336 {0u, 15u, P4_4, P4_4_LIN0_LIN_RX15}, 337 {0u, 7u, P5_0, P5_0_LIN0_LIN_RX7}, 338 {0u, 10u, P5_2, P5_2_LIN0_LIN_RX10}, 339 {0u, 2u, P5_3, P5_3_LIN0_LIN_RX2}, 340 {0u, 9u, P5_4, P5_4_LIN0_LIN_RX9}, 341 {0u, 3u, P6_0, P6_0_LIN0_LIN_RX3}, 342 {0u, 4u, P6_3, P6_3_LIN0_LIN_RX4}, 343 {0u, 4u, P7_0, P7_0_LIN0_LIN_RX4}, 344 {0u, 10u, P7_5, P7_5_LIN0_LIN_RX10}, 345 {0u, 2u, P8_0, P8_0_LIN0_LIN_RX2}, 346 {0u, 16u, P8_3, P8_3_LIN0_LIN_RX16}, 347 {0u, 12u, P9_1, P9_1_LIN0_LIN_RX12}, 348 {0u, 7u, P10_0, P10_0_LIN0_LIN_RX7}, 349 {0u, 8u, P10_2, P10_2_LIN0_LIN_RX8}, 350 {0u, 13u, P10_5, P10_5_LIN0_LIN_RX13}, 351 {0u, 6u, P12_2, P12_2_LIN0_LIN_RX6}, 352 {0u, 3u, P13_0, P13_0_LIN0_LIN_RX3}, 353 {0u, 2u, P13_3, P13_3_LIN0_LIN_RX2}, 354 {0u, 8u, P13_4, P13_4_LIN0_LIN_RX8}, 355 {0u, 6u, P14_2, P14_2_LIN0_LIN_RX6}, 356 {0u, 14u, P14_5, P14_5_LIN0_LIN_RX14}, 357 {0u, 11u, P17_0, P17_0_LIN0_LIN_RX11}, 358 {0u, 15u, P17_5, P17_5_LIN0_LIN_RX15}, 359 {0u, 12u, P17_7, P17_7_LIN0_LIN_RX12}, 360 {0u, 5u, P20_0, P20_0_LIN0_LIN_RX5}, 361 {0u, 0u, P21_5, P21_5_LIN0_LIN_RX0}, 362 {0u, 13u, P21_6, P21_6_LIN0_LIN_RX13}, 363 {0u, 7u, P22_5, P22_5_LIN0_LIN_RX7}, 364 {0u, 14u, P22_7, P22_7_LIN0_LIN_RX14}, 365 {0u, 6u, P23_2, P23_2_LIN0_LIN_RX6}, 366 {0u, 9u, P23_5, P23_5_LIN0_LIN_RX9}, 367 }; 368 369 /* Connections for: lin_lin_tx */ 370 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[37] = { 371 {0u, 1u, P0_1, P0_1_LIN0_LIN_TX1}, 372 {0u, 0u, P1_3, P1_3_LIN0_LIN_TX0}, 373 {0u, 0u, P2_1, P2_1_LIN0_LIN_TX0}, 374 {0u, 5u, P2_4, P2_4_LIN0_LIN_TX5}, 375 {0u, 1u, P3_5, P3_5_LIN0_LIN_TX1}, 376 {0u, 1u, P4_1, P4_1_LIN0_LIN_TX1}, 377 {0u, 15u, P5_0, P5_0_LIN0_LIN_TX15}, 378 {0u, 7u, P5_1, P5_1_LIN0_LIN_TX7}, 379 {0u, 10u, P5_3, P5_3_LIN0_LIN_TX10}, 380 {0u, 2u, P5_4, P5_4_LIN0_LIN_TX2}, 381 {0u, 9u, P5_5, P5_5_LIN0_LIN_TX9}, 382 {0u, 3u, P6_1, P6_1_LIN0_LIN_TX3}, 383 {0u, 4u, P6_4, P6_4_LIN0_LIN_TX4}, 384 {0u, 4u, P7_1, P7_1_LIN0_LIN_TX4}, 385 {0u, 10u, P7_6, P7_6_LIN0_LIN_TX10}, 386 {0u, 2u, P8_1, P8_1_LIN0_LIN_TX2}, 387 {0u, 16u, P8_4, P8_4_LIN0_LIN_TX16}, 388 {0u, 12u, P9_2, P9_2_LIN0_LIN_TX12}, 389 {0u, 7u, P10_1, P10_1_LIN0_LIN_TX7}, 390 {0u, 8u, P10_3, P10_3_LIN0_LIN_TX8}, 391 {0u, 13u, P10_6, P10_6_LIN0_LIN_TX13}, 392 {0u, 6u, P12_3, P12_3_LIN0_LIN_TX6}, 393 {0u, 3u, P13_1, P13_1_LIN0_LIN_TX3}, 394 {0u, 2u, P13_4, P13_4_LIN0_LIN_TX2}, 395 {0u, 8u, P13_5, P13_5_LIN0_LIN_TX8}, 396 {0u, 6u, P14_3, P14_3_LIN0_LIN_TX6}, 397 {0u, 14u, P14_6, P14_6_LIN0_LIN_TX14}, 398 {0u, 11u, P17_1, P17_1_LIN0_LIN_TX11}, 399 {0u, 15u, P17_6, P17_6_LIN0_LIN_TX15}, 400 {0u, 12u, P18_0, P18_0_LIN0_LIN_TX12}, 401 {0u, 5u, P20_1, P20_1_LIN0_LIN_TX5}, 402 {0u, 0u, P21_6, P21_6_LIN0_LIN_TX0}, 403 {0u, 13u, P21_7, P21_7_LIN0_LIN_TX13}, 404 {0u, 7u, P22_6, P22_6_LIN0_LIN_TX7}, 405 {0u, 14u, P23_0, P23_0_LIN0_LIN_TX14}, 406 {0u, 6u, P23_3, P23_3_LIN0_LIN_TX6}, 407 {0u, 9u, P23_6, P23_6_LIN0_LIN_TX9}, 408 }; 409 410 /* Connections for: pass_sar_ext_mux_en */ 411 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[3] = { 412 {0u, 0u, P4_3, P4_3_PASS0_SAR_EXT_MUX_EN0}, 413 {0u, 1u, P12_2, P12_2_PASS0_SAR_EXT_MUX_EN1}, 414 {0u, 2u, P13_3, P13_3_PASS0_SAR_EXT_MUX_EN2}, 415 }; 416 417 /* Connections for: pass_sar_ext_mux_sel */ 418 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[9] = { 419 {0u, 0u, P4_0, P4_0_PASS0_SAR_EXT_MUX_SEL0}, 420 {0u, 1u, P4_1, P4_1_PASS0_SAR_EXT_MUX_SEL1}, 421 {0u, 2u, P4_2, P4_2_PASS0_SAR_EXT_MUX_SEL2}, 422 {0u, 3u, P12_3, P12_3_PASS0_SAR_EXT_MUX_SEL3}, 423 {0u, 4u, P12_4, P12_4_PASS0_SAR_EXT_MUX_SEL4}, 424 {0u, 5u, P12_5, P12_5_PASS0_SAR_EXT_MUX_SEL5}, 425 {0u, 6u, P13_0, P13_0_PASS0_SAR_EXT_MUX_SEL6}, 426 {0u, 7u, P13_1, P13_1_PASS0_SAR_EXT_MUX_SEL7}, 427 {0u, 8u, P13_2, P13_2_PASS0_SAR_EXT_MUX_SEL8}, 428 }; 429 430 /* Connections for: pass_sarmux_pads */ 431 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[81] = { 432 {0u, 0u, P6_0, HSIOM_SEL_GPIO}, 433 {0u, 1u, P6_1, HSIOM_SEL_GPIO}, 434 {0u, 2u, P6_2, HSIOM_SEL_GPIO}, 435 {0u, 3u, P6_3, HSIOM_SEL_GPIO}, 436 {0u, 4u, P6_4, HSIOM_SEL_GPIO}, 437 {0u, 5u, P6_5, HSIOM_SEL_GPIO}, 438 {0u, 6u, P6_6, HSIOM_SEL_GPIO}, 439 {0u, 7u, P6_7, HSIOM_SEL_GPIO}, 440 {0u, 16u, P7_0, HSIOM_SEL_GPIO}, 441 {0u, 17u, P7_1, HSIOM_SEL_GPIO}, 442 {0u, 18u, P7_2, HSIOM_SEL_GPIO}, 443 {0u, 19u, P7_3, HSIOM_SEL_GPIO}, 444 {0u, 20u, P7_4, HSIOM_SEL_GPIO}, 445 {0u, 21u, P7_5, HSIOM_SEL_GPIO}, 446 {0u, 22u, P7_6, HSIOM_SEL_GPIO}, 447 {0u, 23u, P7_7, HSIOM_SEL_GPIO}, 448 {0u, 24u, P8_1, HSIOM_SEL_GPIO}, 449 {0u, 25u, P8_2, HSIOM_SEL_GPIO}, 450 {0u, 26u, P8_3, HSIOM_SEL_GPIO}, 451 {0u, 27u, P8_4, HSIOM_SEL_GPIO}, 452 {0u, 28u, P9_0, HSIOM_SEL_GPIO}, 453 {0u, 29u, P9_1, HSIOM_SEL_GPIO}, 454 {0u, 30u, P9_2, HSIOM_SEL_GPIO}, 455 {0u, 31u, P9_3, HSIOM_SEL_GPIO}, 456 {1u, 0u, P10_4, HSIOM_SEL_GPIO}, 457 {1u, 1u, P10_5, HSIOM_SEL_GPIO}, 458 {1u, 2u, P10_6, HSIOM_SEL_GPIO}, 459 {1u, 3u, P10_7, HSIOM_SEL_GPIO}, 460 {1u, 4u, P12_0, HSIOM_SEL_GPIO}, 461 {1u, 5u, P12_1, HSIOM_SEL_GPIO}, 462 {1u, 6u, P12_2, HSIOM_SEL_GPIO}, 463 {1u, 7u, P12_3, HSIOM_SEL_GPIO}, 464 {1u, 8u, P12_4, HSIOM_SEL_GPIO}, 465 {1u, 9u, P12_5, HSIOM_SEL_GPIO}, 466 {1u, 10u, P12_6, HSIOM_SEL_GPIO}, 467 {1u, 11u, P12_7, HSIOM_SEL_GPIO}, 468 {1u, 12u, P13_0, HSIOM_SEL_GPIO}, 469 {1u, 13u, P13_1, HSIOM_SEL_GPIO}, 470 {1u, 14u, P13_2, HSIOM_SEL_GPIO}, 471 {1u, 15u, P13_3, HSIOM_SEL_GPIO}, 472 {1u, 16u, P13_4, HSIOM_SEL_GPIO}, 473 {1u, 17u, P13_5, HSIOM_SEL_GPIO}, 474 {1u, 18u, P13_6, HSIOM_SEL_GPIO}, 475 {1u, 19u, P13_7, HSIOM_SEL_GPIO}, 476 {1u, 20u, P14_0, HSIOM_SEL_GPIO}, 477 {1u, 21u, P14_1, HSIOM_SEL_GPIO}, 478 {1u, 22u, P14_2, HSIOM_SEL_GPIO}, 479 {1u, 23u, P14_3, HSIOM_SEL_GPIO}, 480 {1u, 24u, P14_4, HSIOM_SEL_GPIO}, 481 {1u, 25u, P14_5, HSIOM_SEL_GPIO}, 482 {1u, 26u, P14_6, HSIOM_SEL_GPIO}, 483 {1u, 27u, P14_7, HSIOM_SEL_GPIO}, 484 {1u, 28u, P15_0, HSIOM_SEL_GPIO}, 485 {1u, 29u, P15_1, HSIOM_SEL_GPIO}, 486 {1u, 30u, P15_2, HSIOM_SEL_GPIO}, 487 {1u, 31u, P15_3, HSIOM_SEL_GPIO}, 488 {2u, 3u, P16_3, HSIOM_SEL_GPIO}, 489 {2u, 8u, P17_0, HSIOM_SEL_GPIO}, 490 {2u, 9u, P17_1, HSIOM_SEL_GPIO}, 491 {2u, 10u, P17_2, HSIOM_SEL_GPIO}, 492 {2u, 11u, P17_3, HSIOM_SEL_GPIO}, 493 {2u, 12u, P17_4, HSIOM_SEL_GPIO}, 494 {2u, 13u, P17_5, HSIOM_SEL_GPIO}, 495 {2u, 14u, P17_6, HSIOM_SEL_GPIO}, 496 {2u, 15u, P17_7, HSIOM_SEL_GPIO}, 497 {2u, 16u, P18_0, HSIOM_SEL_GPIO}, 498 {2u, 17u, P18_1, HSIOM_SEL_GPIO}, 499 {2u, 18u, P18_2, HSIOM_SEL_GPIO}, 500 {2u, 19u, P18_3, HSIOM_SEL_GPIO}, 501 {2u, 20u, P18_4, HSIOM_SEL_GPIO}, 502 {2u, 21u, P18_5, HSIOM_SEL_GPIO}, 503 {2u, 22u, P18_6, HSIOM_SEL_GPIO}, 504 {2u, 23u, P18_7, HSIOM_SEL_GPIO}, 505 {2u, 24u, P19_0, HSIOM_SEL_GPIO}, 506 {2u, 25u, P19_1, HSIOM_SEL_GPIO}, 507 {2u, 26u, P19_2, HSIOM_SEL_GPIO}, 508 {2u, 27u, P19_3, HSIOM_SEL_GPIO}, 509 {2u, 28u, P19_4, HSIOM_SEL_GPIO}, 510 {2u, 29u, P20_0, HSIOM_SEL_GPIO}, 511 {2u, 30u, P20_1, HSIOM_SEL_GPIO}, 512 {2u, 31u, P20_2, HSIOM_SEL_GPIO}, 513 }; 514 515 /* Connections for: peri_tr_io_input */ 516 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 517 to know the index of the input or output trigger line. Store that in the channel_num field 518 instead. */ 519 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[34] = { 520 {0u, 0u, P1_2, P1_2_PERI_TR_IO_INPUT0}, 521 {0u, 1u, P1_3, P1_3_PERI_TR_IO_INPUT1}, 522 {0u, 2u, P2_0, P2_0_PERI_TR_IO_INPUT2}, 523 {0u, 3u, P2_1, P2_1_PERI_TR_IO_INPUT3}, 524 {0u, 4u, P2_2, P2_2_PERI_TR_IO_INPUT4}, 525 {0u, 5u, P2_3, P2_3_PERI_TR_IO_INPUT5}, 526 {0u, 6u, P2_4, P2_4_PERI_TR_IO_INPUT6}, 527 {0u, 7u, P2_5, P2_5_PERI_TR_IO_INPUT7}, 528 {0u, 10u, P4_0, P4_0_PERI_TR_IO_INPUT10}, 529 {0u, 11u, P4_1, P4_1_PERI_TR_IO_INPUT11}, 530 {0u, 12u, P4_2, P4_2_PERI_TR_IO_INPUT12}, 531 {0u, 13u, P4_3, P4_3_PERI_TR_IO_INPUT13}, 532 {0u, 38u, P5_0, P5_0_PERI_TR_IO_INPUT38}, 533 {0u, 39u, P5_1, P5_1_PERI_TR_IO_INPUT39}, 534 {0u, 8u, P6_6, P6_6_PERI_TR_IO_INPUT8}, 535 {0u, 9u, P6_7, P6_7_PERI_TR_IO_INPUT9}, 536 {0u, 16u, P7_6, P7_6_PERI_TR_IO_INPUT16}, 537 {0u, 17u, P7_7, P7_7_PERI_TR_IO_INPUT17}, 538 {0u, 14u, P8_1, P8_1_PERI_TR_IO_INPUT14}, 539 {0u, 15u, P8_2, P8_2_PERI_TR_IO_INPUT15}, 540 {0u, 18u, P10_0, P10_0_PERI_TR_IO_INPUT18}, 541 {0u, 19u, P10_1, P10_1_PERI_TR_IO_INPUT19}, 542 {0u, 20u, P12_0, P12_0_PERI_TR_IO_INPUT20}, 543 {0u, 21u, P12_1, P12_1_PERI_TR_IO_INPUT21}, 544 {0u, 22u, P13_6, P13_6_PERI_TR_IO_INPUT22}, 545 {0u, 23u, P13_7, P13_7_PERI_TR_IO_INPUT23}, 546 {0u, 24u, P14_6, P14_6_PERI_TR_IO_INPUT24}, 547 {0u, 25u, P14_7, P14_7_PERI_TR_IO_INPUT25}, 548 {0u, 26u, P17_3, P17_3_PERI_TR_IO_INPUT26}, 549 {0u, 27u, P17_4, P17_4_PERI_TR_IO_INPUT27}, 550 {0u, 28u, P19_2, P19_2_PERI_TR_IO_INPUT28}, 551 {0u, 29u, P19_3, P19_3_PERI_TR_IO_INPUT29}, 552 {0u, 30u, P23_3, P23_3_PERI_TR_IO_INPUT30}, 553 {0u, 31u, P23_4, P23_4_PERI_TR_IO_INPUT31}, 554 }; 555 556 /* Connections for: peri_tr_io_output */ 557 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 558 to know the index of the input or output trigger line. Store that in the channel_num field 559 instead. */ 560 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6] = { 561 {0u, 0u, P3_0, P3_0_PERI_TR_IO_OUTPUT0}, 562 {0u, 1u, P3_1, P3_1_PERI_TR_IO_OUTPUT1}, 563 {0u, 0u, P8_3, P8_3_PERI_TR_IO_OUTPUT0}, 564 {0u, 1u, P8_4, P8_4_PERI_TR_IO_OUTPUT1}, 565 {0u, 1u, P21_2, P21_2_PERI_TR_IO_OUTPUT1}, 566 {0u, 0u, P23_4, P23_4_PERI_TR_IO_OUTPUT0}, 567 }; 568 569 /* Connections for: scb_i2c_scl */ 570 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[19] = { 571 {7u, 0u, P0_1, P0_1_SCB7_I2C_SCL}, 572 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 573 {0u, 0u, P1_0, P1_0_SCB0_I2C_SCL}, 574 {7u, 0u, P2_2, P2_2_SCB7_I2C_SCL}, 575 {6u, 0u, P3_2, P3_2_SCB6_I2C_SCL}, 576 {5u, 0u, P4_2, P4_2_SCB5_I2C_SCL}, 577 {4u, 0u, P6_2, P6_2_SCB4_I2C_SCL}, 578 {5u, 0u, P7_2, P7_2_SCB5_I2C_SCL}, 579 {4u, 0u, P10_2, P10_2_SCB4_I2C_SCL}, 580 {8u, 0u, P12_2, P12_2_SCB8_I2C_SCL}, 581 {3u, 0u, P13_2, P13_2_SCB3_I2C_SCL}, 582 {2u, 0u, P14_2, P14_2_SCB2_I2C_SCL}, 583 {9u, 0u, P15_2, P15_2_SCB9_I2C_SCL}, 584 {3u, 0u, P17_3, P17_3_SCB3_I2C_SCL}, 585 {1u, 0u, P18_2, P18_2_SCB1_I2C_SCL}, 586 {2u, 0u, P19_2, P19_2_SCB2_I2C_SCL}, 587 {1u, 0u, P20_5, P20_5_SCB1_I2C_SCL}, 588 {6u, 0u, P22_2, P22_2_SCB6_I2C_SCL}, 589 {7u, 0u, P23_2, P23_2_SCB7_I2C_SCL}, 590 }; 591 592 /* Connections for: scb_i2c_sda */ 593 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[19] = { 594 {7u, 0u, P0_0, P0_0_SCB7_I2C_SDA}, 595 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 596 {0u, 0u, P1_1, P1_1_SCB0_I2C_SDA}, 597 {7u, 0u, P2_1, P2_1_SCB7_I2C_SDA}, 598 {6u, 0u, P3_1, P3_1_SCB6_I2C_SDA}, 599 {5u, 0u, P4_1, P4_1_SCB5_I2C_SDA}, 600 {4u, 0u, P6_1, P6_1_SCB4_I2C_SDA}, 601 {5u, 0u, P7_1, P7_1_SCB5_I2C_SDA}, 602 {4u, 0u, P10_1, P10_1_SCB4_I2C_SDA}, 603 {8u, 0u, P12_1, P12_1_SCB8_I2C_SDA}, 604 {3u, 0u, P13_1, P13_1_SCB3_I2C_SDA}, 605 {2u, 0u, P14_1, P14_1_SCB2_I2C_SDA}, 606 {9u, 0u, P15_1, P15_1_SCB9_I2C_SDA}, 607 {3u, 0u, P17_2, P17_2_SCB3_I2C_SDA}, 608 {1u, 0u, P18_1, P18_1_SCB1_I2C_SDA}, 609 {2u, 0u, P19_1, P19_1_SCB2_I2C_SDA}, 610 {1u, 0u, P20_4, P20_4_SCB1_I2C_SDA}, 611 {6u, 0u, P22_1, P22_1_SCB6_I2C_SDA}, 612 {7u, 0u, P23_1, P23_1_SCB7_I2C_SDA}, 613 }; 614 615 /* Connections for: scb_spi_m_clk */ 616 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[21] = { 617 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 618 {4u, 0u, P1_0, P1_0_SCB4_SPI_CLK}, 619 {0u, 0u, P1_2, P1_2_SCB0_SPI_CLK}, 620 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 621 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 622 {5u, 0u, P4_2, P4_2_SCB5_SPI_CLK}, 623 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 624 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 625 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 626 {8u, 0u, P12_2, P12_2_SCB8_SPI_CLK}, 627 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 628 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 629 {9u, 0u, P15_2, P15_2_SCB9_SPI_CLK}, 630 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 631 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 632 {3u, 0u, P18_3, P18_3_SCB3_SPI_CLK}, 633 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 634 {1u, 0u, P20_5, P20_5_SCB1_SPI_CLK}, 635 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 636 {7u, 0u, P23_2, P23_2_SCB7_SPI_CLK}, 637 {2u, 0u, P23_6, P23_6_SCB2_SPI_CLK}, 638 }; 639 640 /* Connections for: scb_spi_m_miso */ 641 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[20] = { 642 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 643 {4u, 0u, P0_2, P0_2_SCB4_SPI_MISO}, 644 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 645 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 646 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 647 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 648 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 649 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 650 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 651 {8u, 0u, P12_0, P12_0_SCB8_SPI_MISO}, 652 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 653 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 654 {9u, 0u, P15_0, P15_0_SCB9_SPI_MISO}, 655 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 656 {3u, 0u, P18_1, P18_1_SCB3_SPI_MISO}, 657 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 658 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 659 {6u, 0u, P21_7, P21_7_SCB6_SPI_MISO}, 660 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 661 {2u, 0u, P23_4, P23_4_SCB2_SPI_MISO}, 662 }; 663 664 /* Connections for: scb_spi_m_mosi */ 665 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[20] = { 666 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 667 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI}, 668 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 669 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 670 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 671 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 672 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 673 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 674 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 675 {8u, 0u, P12_1, P12_1_SCB8_SPI_MOSI}, 676 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 677 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 678 {9u, 0u, P15_1, P15_1_SCB9_SPI_MOSI}, 679 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 680 {3u, 0u, P18_2, P18_2_SCB3_SPI_MOSI}, 681 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 682 {1u, 0u, P20_4, P20_4_SCB1_SPI_MOSI}, 683 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 684 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 685 {2u, 0u, P23_5, P23_5_SCB2_SPI_MOSI}, 686 }; 687 688 /* Connections for: scb_spi_m_select0 */ 689 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[21] = { 690 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 691 {4u, 0u, P1_1, P1_1_SCB4_SPI_SELECT0}, 692 {0u, 0u, P1_3, P1_3_SCB0_SPI_SELECT0}, 693 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 694 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 695 {5u, 0u, P4_3, P4_3_SCB5_SPI_SELECT0}, 696 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 697 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 698 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 699 {8u, 0u, P12_3, P12_3_SCB8_SPI_SELECT0}, 700 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 701 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 702 {9u, 0u, P15_3, P15_3_SCB9_SPI_SELECT0}, 703 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 704 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 705 {3u, 0u, P18_4, P18_4_SCB3_SPI_SELECT0}, 706 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 707 {1u, 0u, P20_6, P20_6_SCB1_SPI_SELECT0}, 708 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 709 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 710 {2u, 0u, P23_7, P23_7_SCB2_SPI_SELECT0}, 711 }; 712 713 /* Connections for: scb_spi_m_select1 */ 714 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[16] = { 715 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 716 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 717 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 718 {5u, 0u, P4_4, P4_4_SCB5_SPI_SELECT1}, 719 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 720 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 721 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 722 {8u, 0u, P12_4, P12_4_SCB8_SPI_SELECT1}, 723 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 724 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 725 {3u, 0u, P17_5, P17_5_SCB3_SPI_SELECT1}, 726 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 727 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 728 {1u, 0u, P20_7, P20_7_SCB1_SPI_SELECT1}, 729 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 730 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 731 }; 732 733 /* Connections for: scb_spi_m_select2 */ 734 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[15] = { 735 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 736 {7u, 0u, P2_5, P2_5_SCB7_SPI_SELECT2}, 737 {6u, 0u, P3_5, P3_5_SCB6_SPI_SELECT2}, 738 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 739 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 740 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 741 {4u, 0u, P10_5, P10_5_SCB4_SPI_SELECT2}, 742 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 743 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 744 {3u, 0u, P17_6, P17_6_SCB3_SPI_SELECT2}, 745 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 746 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 747 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 748 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 749 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 750 }; 751 752 /* Connections for: scb_spi_m_select3 */ 753 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[5] = { 754 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 755 {9u, 0u, P5_1, P5_1_SCB9_SPI_SELECT3}, 756 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 757 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 758 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 759 }; 760 761 /* Connections for: scb_spi_s_clk */ 762 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[21] = { 763 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 764 {4u, 0u, P1_0, P1_0_SCB4_SPI_CLK}, 765 {0u, 0u, P1_2, P1_2_SCB0_SPI_CLK}, 766 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 767 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 768 {5u, 0u, P4_2, P4_2_SCB5_SPI_CLK}, 769 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 770 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 771 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 772 {8u, 0u, P12_2, P12_2_SCB8_SPI_CLK}, 773 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 774 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 775 {9u, 0u, P15_2, P15_2_SCB9_SPI_CLK}, 776 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 777 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 778 {3u, 0u, P18_3, P18_3_SCB3_SPI_CLK}, 779 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 780 {1u, 0u, P20_5, P20_5_SCB1_SPI_CLK}, 781 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 782 {7u, 0u, P23_2, P23_2_SCB7_SPI_CLK}, 783 {2u, 0u, P23_6, P23_6_SCB2_SPI_CLK}, 784 }; 785 786 /* Connections for: scb_spi_s_miso */ 787 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[20] = { 788 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 789 {4u, 0u, P0_2, P0_2_SCB4_SPI_MISO}, 790 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 791 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 792 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 793 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 794 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 795 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 796 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 797 {8u, 0u, P12_0, P12_0_SCB8_SPI_MISO}, 798 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 799 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 800 {9u, 0u, P15_0, P15_0_SCB9_SPI_MISO}, 801 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 802 {3u, 0u, P18_1, P18_1_SCB3_SPI_MISO}, 803 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 804 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 805 {6u, 0u, P21_7, P21_7_SCB6_SPI_MISO}, 806 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 807 {2u, 0u, P23_4, P23_4_SCB2_SPI_MISO}, 808 }; 809 810 /* Connections for: scb_spi_s_mosi */ 811 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[20] = { 812 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 813 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI}, 814 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 815 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 816 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 817 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 818 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 819 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 820 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 821 {8u, 0u, P12_1, P12_1_SCB8_SPI_MOSI}, 822 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 823 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 824 {9u, 0u, P15_1, P15_1_SCB9_SPI_MOSI}, 825 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 826 {3u, 0u, P18_2, P18_2_SCB3_SPI_MOSI}, 827 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 828 {1u, 0u, P20_4, P20_4_SCB1_SPI_MOSI}, 829 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 830 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 831 {2u, 0u, P23_5, P23_5_SCB2_SPI_MOSI}, 832 }; 833 834 /* Connections for: scb_spi_s_select0 */ 835 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[21] = { 836 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 837 {4u, 0u, P1_1, P1_1_SCB4_SPI_SELECT0}, 838 {0u, 0u, P1_3, P1_3_SCB0_SPI_SELECT0}, 839 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 840 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 841 {5u, 0u, P4_3, P4_3_SCB5_SPI_SELECT0}, 842 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 843 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 844 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 845 {8u, 0u, P12_3, P12_3_SCB8_SPI_SELECT0}, 846 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 847 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 848 {9u, 0u, P15_3, P15_3_SCB9_SPI_SELECT0}, 849 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 850 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 851 {3u, 0u, P18_4, P18_4_SCB3_SPI_SELECT0}, 852 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 853 {1u, 0u, P20_6, P20_6_SCB1_SPI_SELECT0}, 854 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 855 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 856 {2u, 0u, P23_7, P23_7_SCB2_SPI_SELECT0}, 857 }; 858 859 /* Connections for: scb_spi_s_select1 */ 860 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[16] = { 861 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 862 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 863 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 864 {5u, 0u, P4_4, P4_4_SCB5_SPI_SELECT1}, 865 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 866 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 867 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 868 {8u, 0u, P12_4, P12_4_SCB8_SPI_SELECT1}, 869 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 870 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 871 {3u, 0u, P17_5, P17_5_SCB3_SPI_SELECT1}, 872 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 873 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 874 {1u, 0u, P20_7, P20_7_SCB1_SPI_SELECT1}, 875 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 876 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 877 }; 878 879 /* Connections for: scb_spi_s_select2 */ 880 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[15] = { 881 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 882 {7u, 0u, P2_5, P2_5_SCB7_SPI_SELECT2}, 883 {6u, 0u, P3_5, P3_5_SCB6_SPI_SELECT2}, 884 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 885 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 886 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 887 {4u, 0u, P10_5, P10_5_SCB4_SPI_SELECT2}, 888 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 889 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 890 {3u, 0u, P17_6, P17_6_SCB3_SPI_SELECT2}, 891 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 892 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 893 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 894 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 895 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 896 }; 897 898 /* Connections for: scb_spi_s_select3 */ 899 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[5] = { 900 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 901 {9u, 0u, P5_1, P5_1_SCB9_SPI_SELECT3}, 902 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 903 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 904 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 905 }; 906 907 /* Connections for: scb_uart_cts */ 908 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[17] = { 909 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS}, 910 {7u, 0u, P2_3, P2_3_SCB7_UART_CTS}, 911 {6u, 0u, P3_3, P3_3_SCB6_UART_CTS}, 912 {5u, 0u, P4_3, P4_3_SCB5_UART_CTS}, 913 {4u, 0u, P6_3, P6_3_SCB4_UART_CTS}, 914 {5u, 0u, P7_3, P7_3_SCB5_UART_CTS}, 915 {4u, 0u, P10_3, P10_3_SCB4_UART_CTS}, 916 {8u, 0u, P12_3, P12_3_SCB8_UART_CTS}, 917 {3u, 0u, P13_3, P13_3_SCB3_UART_CTS}, 918 {2u, 0u, P14_3, P14_3_SCB2_UART_CTS}, 919 {9u, 0u, P15_3, P15_3_SCB9_UART_CTS}, 920 {3u, 0u, P17_4, P17_4_SCB3_UART_CTS}, 921 {1u, 0u, P18_3, P18_3_SCB1_UART_CTS}, 922 {2u, 0u, P19_3, P19_3_SCB2_UART_CTS}, 923 {1u, 0u, P20_6, P20_6_SCB1_UART_CTS}, 924 {6u, 0u, P22_3, P22_3_SCB6_UART_CTS}, 925 {7u, 0u, P23_3, P23_3_SCB7_UART_CTS}, 926 }; 927 928 /* Connections for: scb_uart_rts */ 929 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[17] = { 930 {0u, 0u, P0_2, P0_2_SCB0_UART_RTS}, 931 {7u, 0u, P2_2, P2_2_SCB7_UART_RTS}, 932 {6u, 0u, P3_2, P3_2_SCB6_UART_RTS}, 933 {5u, 0u, P4_2, P4_2_SCB5_UART_RTS}, 934 {4u, 0u, P6_2, P6_2_SCB4_UART_RTS}, 935 {5u, 0u, P7_2, P7_2_SCB5_UART_RTS}, 936 {4u, 0u, P10_2, P10_2_SCB4_UART_RTS}, 937 {8u, 0u, P12_2, P12_2_SCB8_UART_RTS}, 938 {3u, 0u, P13_2, P13_2_SCB3_UART_RTS}, 939 {2u, 0u, P14_2, P14_2_SCB2_UART_RTS}, 940 {9u, 0u, P15_2, P15_2_SCB9_UART_RTS}, 941 {3u, 0u, P17_3, P17_3_SCB3_UART_RTS}, 942 {1u, 0u, P18_2, P18_2_SCB1_UART_RTS}, 943 {2u, 0u, P19_2, P19_2_SCB2_UART_RTS}, 944 {1u, 0u, P20_5, P20_5_SCB1_UART_RTS}, 945 {6u, 0u, P22_2, P22_2_SCB6_UART_RTS}, 946 {7u, 0u, P23_2, P23_2_SCB7_UART_RTS}, 947 }; 948 949 /* Connections for: scb_uart_rx */ 950 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[17] = { 951 {0u, 0u, P0_0, P0_0_SCB0_UART_RX}, 952 {7u, 0u, P2_0, P2_0_SCB7_UART_RX}, 953 {6u, 0u, P3_0, P3_0_SCB6_UART_RX}, 954 {5u, 0u, P4_0, P4_0_SCB5_UART_RX}, 955 {4u, 0u, P6_0, P6_0_SCB4_UART_RX}, 956 {5u, 0u, P7_0, P7_0_SCB5_UART_RX}, 957 {4u, 0u, P10_0, P10_0_SCB4_UART_RX}, 958 {8u, 0u, P12_0, P12_0_SCB8_UART_RX}, 959 {3u, 0u, P13_0, P13_0_SCB3_UART_RX}, 960 {2u, 0u, P14_0, P14_0_SCB2_UART_RX}, 961 {9u, 0u, P15_0, P15_0_SCB9_UART_RX}, 962 {3u, 0u, P17_1, P17_1_SCB3_UART_RX}, 963 {1u, 0u, P18_0, P18_0_SCB1_UART_RX}, 964 {2u, 0u, P19_0, P19_0_SCB2_UART_RX}, 965 {1u, 0u, P20_3, P20_3_SCB1_UART_RX}, 966 {6u, 0u, P21_7, P21_7_SCB6_UART_RX}, 967 {7u, 0u, P23_0, P23_0_SCB7_UART_RX}, 968 }; 969 970 /* Connections for: scb_uart_tx */ 971 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[17] = { 972 {0u, 0u, P0_1, P0_1_SCB0_UART_TX}, 973 {7u, 0u, P2_1, P2_1_SCB7_UART_TX}, 974 {6u, 0u, P3_1, P3_1_SCB6_UART_TX}, 975 {5u, 0u, P4_1, P4_1_SCB5_UART_TX}, 976 {4u, 0u, P6_1, P6_1_SCB4_UART_TX}, 977 {5u, 0u, P7_1, P7_1_SCB5_UART_TX}, 978 {4u, 0u, P10_1, P10_1_SCB4_UART_TX}, 979 {8u, 0u, P12_1, P12_1_SCB8_UART_TX}, 980 {3u, 0u, P13_1, P13_1_SCB3_UART_TX}, 981 {2u, 0u, P14_1, P14_1_SCB2_UART_TX}, 982 {9u, 0u, P15_1, P15_1_SCB9_UART_TX}, 983 {3u, 0u, P17_2, P17_2_SCB3_UART_TX}, 984 {1u, 0u, P18_1, P18_1_SCB1_UART_TX}, 985 {2u, 0u, P19_1, P19_1_SCB2_UART_TX}, 986 {1u, 0u, P20_4, P20_4_SCB1_UART_TX}, 987 {6u, 0u, P22_1, P22_1_SCB6_UART_TX}, 988 {7u, 0u, P23_1, P23_1_SCB7_UART_TX}, 989 }; 990 991 /* Connections for: sdhc_card_cmd */ 992 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1] = { 993 {0u, 0u, P6_3, P6_3_SDHC0_CARD_CMD}, 994 }; 995 996 /* Connections for: sdhc_card_dat_3to0 */ 997 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4] = { 998 {0u, 0u, P7_1, P7_1_SDHC0_CARD_DAT_3TO00}, 999 {0u, 1u, P7_2, P7_2_SDHC0_CARD_DAT_3TO01}, 1000 {0u, 2u, P7_3, P7_3_SDHC0_CARD_DAT_3TO02}, 1001 {0u, 3u, P7_4, P7_4_SDHC0_CARD_DAT_3TO03}, 1002 }; 1003 1004 /* Connections for: sdhc_card_dat_7to4 */ 1005 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4] = { 1006 {0u, 0u, P7_5, P7_5_SDHC0_CARD_DAT_7TO40}, 1007 {0u, 1u, P8_0, P8_0_SDHC0_CARD_DAT_7TO41}, 1008 {0u, 2u, P8_1, P8_1_SDHC0_CARD_DAT_7TO42}, 1009 {0u, 3u, P8_2, P8_2_SDHC0_CARD_DAT_7TO43}, 1010 }; 1011 1012 /* Connections for: sdhc_card_detect_n */ 1013 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1] = { 1014 {0u, 0u, P6_5, P6_5_SDHC0_CARD_DETECT_N}, 1015 }; 1016 1017 /* Connections for: sdhc_card_if_pwr_en */ 1018 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1] = { 1019 {0u, 0u, P7_0, P7_0_SDHC0_CARD_IF_PWR_EN}, 1020 }; 1021 1022 /* Connections for: sdhc_card_mech_write_prot */ 1023 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1] = { 1024 {0u, 0u, P6_2, P6_2_SDHC0_CARD_MECH_WRITE_PROT}, 1025 }; 1026 1027 /* Connections for: sdhc_clk_card */ 1028 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1] = { 1029 {0u, 0u, P6_4, P6_4_SDHC0_CLK_CARD}, 1030 }; 1031 1032 /* Connections for: smif_spi_clk */ 1033 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = { 1034 {0u, 0u, P6_3, P6_3_SMIF0_SPIHB_CLK}, 1035 }; 1036 1037 /* Connections for: smif_spi_data0 */ 1038 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = { 1039 {0u, 0u, P7_1, P7_1_SMIF0_SPIHB_DATA0}, 1040 }; 1041 1042 /* Connections for: smif_spi_data1 */ 1043 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = { 1044 {0u, 0u, P7_2, P7_2_SMIF0_SPIHB_DATA1}, 1045 }; 1046 1047 /* Connections for: smif_spi_data2 */ 1048 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = { 1049 {0u, 0u, P7_3, P7_3_SMIF0_SPIHB_DATA2}, 1050 }; 1051 1052 /* Connections for: smif_spi_data3 */ 1053 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = { 1054 {0u, 0u, P7_4, P7_4_SMIF0_SPIHB_DATA3}, 1055 }; 1056 1057 /* Connections for: smif_spi_data4 */ 1058 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1] = { 1059 {0u, 0u, P7_5, P7_5_SMIF0_SPIHB_DATA4}, 1060 }; 1061 1062 /* Connections for: smif_spi_data5 */ 1063 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1] = { 1064 {0u, 0u, P8_0, P8_0_SMIF0_SPIHB_DATA5}, 1065 }; 1066 1067 /* Connections for: smif_spi_data6 */ 1068 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1] = { 1069 {0u, 0u, P8_1, P8_1_SMIF0_SPIHB_DATA6}, 1070 }; 1071 1072 /* Connections for: smif_spi_data7 */ 1073 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1] = { 1074 {0u, 0u, P8_2, P8_2_SMIF0_SPIHB_DATA7}, 1075 }; 1076 1077 /* Connections for: smif_spi_rwds */ 1078 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_rwds[1] = { 1079 {0u, 0u, P6_4, P6_4_SMIF0_SPIHB_RWDS}, 1080 }; 1081 1082 /* Connections for: smif_spi_select0 */ 1083 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = { 1084 {0u, 0u, P6_5, P6_5_SMIF0_SPIHB_SELECT0}, 1085 }; 1086 1087 /* Connections for: smif_spi_select1 */ 1088 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = { 1089 {0u, 0u, P7_0, P7_0_SMIF0_SPIHB_SELECT1}, 1090 }; 1091 1092 /* Connections for: tcpwm_line */ 1093 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[181] = { 1094 {2u, 0u, P0_0, P0_0_TCPWM0_LINE512}, 1095 {4u, 18u, P0_0, P0_0_TCPWM1_LINE18}, 1096 {4u, 17u, P0_1, P0_1_TCPWM1_LINE17}, 1097 {4u, 14u, P0_2, P0_2_TCPWM1_LINE14}, 1098 {4u, 13u, P0_3, P0_3_TCPWM1_LINE13}, 1099 {4u, 12u, P1_0, P1_0_TCPWM1_LINE12}, 1100 {6u, 4u, P1_0, P1_0_TCPWM1_LINE516}, 1101 {4u, 11u, P1_1, P1_1_TCPWM1_LINE11}, 1102 {6u, 5u, P1_1, P1_1_TCPWM1_LINE517}, 1103 {4u, 10u, P1_2, P1_2_TCPWM1_LINE10}, 1104 {6u, 6u, P1_2, P1_2_TCPWM1_LINE518}, 1105 {4u, 8u, P1_3, P1_3_TCPWM1_LINE8}, 1106 {6u, 7u, P1_3, P1_3_TCPWM1_LINE519}, 1107 {4u, 7u, P2_0, P2_0_TCPWM1_LINE7}, 1108 {4u, 6u, P2_1, P2_1_TCPWM1_LINE6}, 1109 {4u, 5u, P2_2, P2_2_TCPWM1_LINE5}, 1110 {4u, 4u, P2_3, P2_3_TCPWM1_LINE4}, 1111 {4u, 3u, P2_4, P2_4_TCPWM1_LINE3}, 1112 {4u, 2u, P2_5, P2_5_TCPWM1_LINE2}, 1113 {4u, 1u, P3_0, P3_0_TCPWM1_LINE1}, 1114 {4u, 0u, P3_1, P3_1_TCPWM1_LINE0}, 1115 {5u, 3u, P3_2, P3_2_TCPWM1_LINE259}, 1116 {5u, 2u, P3_3, P3_3_TCPWM1_LINE258}, 1117 {5u, 1u, P3_4, P3_4_TCPWM1_LINE257}, 1118 {5u, 0u, P3_5, P3_5_TCPWM1_LINE256}, 1119 {4u, 4u, P4_0, P4_0_TCPWM1_LINE4}, 1120 {4u, 5u, P4_1, P4_1_TCPWM1_LINE5}, 1121 {4u, 6u, P4_2, P4_2_TCPWM1_LINE6}, 1122 {4u, 7u, P4_3, P4_3_TCPWM1_LINE7}, 1123 {4u, 8u, P4_4, P4_4_TCPWM1_LINE8}, 1124 {1u, 0u, P5_0, P5_0_TCPWM0_LINE256}, 1125 {4u, 9u, P5_0, P5_0_TCPWM1_LINE9}, 1126 {6u, 10u, P5_0, P5_0_TCPWM1_LINE522}, 1127 {4u, 10u, P5_1, P5_1_TCPWM1_LINE10}, 1128 {4u, 11u, P5_2, P5_2_TCPWM1_LINE11}, 1129 {4u, 12u, P5_3, P5_3_TCPWM1_LINE12}, 1130 {4u, 13u, P5_4, P5_4_TCPWM1_LINE13}, 1131 {6u, 11u, P5_4, P5_4_TCPWM1_LINE523}, 1132 {4u, 14u, P5_5, P5_5_TCPWM1_LINE14}, 1133 {0u, 0u, P6_0, P6_0_TCPWM0_LINE0}, 1134 {5u, 0u, P6_0, P6_0_TCPWM1_LINE256}, 1135 {4u, 0u, P6_1, P6_1_TCPWM1_LINE0}, 1136 {5u, 1u, P6_2, P6_2_TCPWM1_LINE257}, 1137 {6u, 12u, P6_2, P6_2_TCPWM1_LINE524}, 1138 {4u, 1u, P6_3, P6_3_TCPWM1_LINE1}, 1139 {5u, 2u, P6_4, P6_4_TCPWM1_LINE258}, 1140 {4u, 2u, P6_5, P6_5_TCPWM1_LINE2}, 1141 {5u, 3u, P6_6, P6_6_TCPWM1_LINE259}, 1142 {4u, 3u, P6_7, P6_7_TCPWM1_LINE3}, 1143 {0u, 1u, P7_0, P7_0_TCPWM0_LINE1}, 1144 {5u, 4u, P7_0, P7_0_TCPWM1_LINE260}, 1145 {4u, 15u, P7_1, P7_1_TCPWM1_LINE15}, 1146 {5u, 5u, P7_2, P7_2_TCPWM1_LINE261}, 1147 {4u, 16u, P7_3, P7_3_TCPWM1_LINE16}, 1148 {5u, 6u, P7_4, P7_4_TCPWM1_LINE262}, 1149 {2u, 2u, P7_5, P7_5_TCPWM0_LINE514}, 1150 {4u, 17u, P7_5, P7_5_TCPWM1_LINE17}, 1151 {5u, 7u, P7_6, P7_6_TCPWM1_LINE263}, 1152 {4u, 18u, P7_7, P7_7_TCPWM1_LINE18}, 1153 {4u, 19u, P8_0, P8_0_TCPWM1_LINE19}, 1154 {6u, 8u, P8_0, P8_0_TCPWM1_LINE520}, 1155 {4u, 20u, P8_1, P8_1_TCPWM1_LINE20}, 1156 {4u, 21u, P8_2, P8_2_TCPWM1_LINE21}, 1157 {4u, 22u, P8_3, P8_3_TCPWM1_LINE22}, 1158 {4u, 23u, P8_4, P8_4_TCPWM1_LINE23}, 1159 {4u, 24u, P9_0, P9_0_TCPWM1_LINE24}, 1160 {6u, 9u, P9_0, P9_0_TCPWM1_LINE521}, 1161 {4u, 25u, P9_1, P9_1_TCPWM1_LINE25}, 1162 {4u, 26u, P9_2, P9_2_TCPWM1_LINE26}, 1163 {4u, 27u, P9_3, P9_3_TCPWM1_LINE27}, 1164 {4u, 28u, P10_0, P10_0_TCPWM1_LINE28}, 1165 {6u, 10u, P10_0, P10_0_TCPWM1_LINE522}, 1166 {4u, 29u, P10_1, P10_1_TCPWM1_LINE29}, 1167 {4u, 30u, P10_2, P10_2_TCPWM1_LINE30}, 1168 {4u, 31u, P10_3, P10_3_TCPWM1_LINE31}, 1169 {4u, 32u, P10_4, P10_4_TCPWM1_LINE32}, 1170 {6u, 11u, P10_4, P10_4_TCPWM1_LINE523}, 1171 {4u, 33u, P10_5, P10_5_TCPWM1_LINE33}, 1172 {4u, 34u, P10_6, P10_6_TCPWM1_LINE34}, 1173 {4u, 35u, P10_7, P10_7_TCPWM1_LINE35}, 1174 {4u, 61u, P11_0, P11_0_TCPWM1_LINE61}, 1175 {4u, 60u, P11_1, P11_1_TCPWM1_LINE60}, 1176 {4u, 59u, P11_2, P11_2_TCPWM1_LINE59}, 1177 {2u, 1u, P12_0, P12_0_TCPWM0_LINE513}, 1178 {4u, 36u, P12_0, P12_0_TCPWM1_LINE36}, 1179 {4u, 37u, P12_1, P12_1_TCPWM1_LINE37}, 1180 {4u, 38u, P12_2, P12_2_TCPWM1_LINE38}, 1181 {4u, 39u, P12_3, P12_3_TCPWM1_LINE39}, 1182 {4u, 40u, P12_4, P12_4_TCPWM1_LINE40}, 1183 {4u, 41u, P12_5, P12_5_TCPWM1_LINE41}, 1184 {4u, 42u, P12_6, P12_6_TCPWM1_LINE42}, 1185 {4u, 43u, P12_7, P12_7_TCPWM1_LINE43}, 1186 {5u, 8u, P13_0, P13_0_TCPWM1_LINE264}, 1187 {4u, 44u, P13_1, P13_1_TCPWM1_LINE44}, 1188 {0u, 2u, P13_2, P13_2_TCPWM0_LINE2}, 1189 {5u, 9u, P13_2, P13_2_TCPWM1_LINE265}, 1190 {4u, 45u, P13_3, P13_3_TCPWM1_LINE45}, 1191 {5u, 10u, P13_4, P13_4_TCPWM1_LINE266}, 1192 {6u, 4u, P13_4, P13_4_TCPWM1_LINE516}, 1193 {4u, 46u, P13_5, P13_5_TCPWM1_LINE46}, 1194 {5u, 11u, P13_6, P13_6_TCPWM1_LINE267}, 1195 {6u, 5u, P13_6, P13_6_TCPWM1_LINE517}, 1196 {4u, 47u, P13_7, P13_7_TCPWM1_LINE47}, 1197 {1u, 1u, P14_0, P14_0_TCPWM0_LINE257}, 1198 {4u, 48u, P14_0, P14_0_TCPWM1_LINE48}, 1199 {6u, 6u, P14_0, P14_0_TCPWM1_LINE518}, 1200 {4u, 49u, P14_1, P14_1_TCPWM1_LINE49}, 1201 {4u, 50u, P14_2, P14_2_TCPWM1_LINE50}, 1202 {6u, 7u, P14_2, P14_2_TCPWM1_LINE519}, 1203 {4u, 51u, P14_3, P14_3_TCPWM1_LINE51}, 1204 {4u, 52u, P14_4, P14_4_TCPWM1_LINE52}, 1205 {4u, 53u, P14_5, P14_5_TCPWM1_LINE53}, 1206 {4u, 54u, P14_6, P14_6_TCPWM1_LINE54}, 1207 {4u, 55u, P14_7, P14_7_TCPWM1_LINE55}, 1208 {4u, 56u, P15_0, P15_0_TCPWM1_LINE56}, 1209 {4u, 57u, P15_1, P15_1_TCPWM1_LINE57}, 1210 {4u, 58u, P15_2, P15_2_TCPWM1_LINE58}, 1211 {4u, 59u, P15_3, P15_3_TCPWM1_LINE59}, 1212 {4u, 62u, P16_3, P16_3_TCPWM1_LINE62}, 1213 {4u, 61u, P17_0, P17_0_TCPWM1_LINE61}, 1214 {4u, 60u, P17_1, P17_1_TCPWM1_LINE60}, 1215 {4u, 59u, P17_2, P17_2_TCPWM1_LINE59}, 1216 {4u, 58u, P17_3, P17_3_TCPWM1_LINE58}, 1217 {6u, 3u, P17_3, P17_3_TCPWM1_LINE515}, 1218 {4u, 57u, P17_4, P17_4_TCPWM1_LINE57}, 1219 {4u, 56u, P17_5, P17_5_TCPWM1_LINE56}, 1220 {6u, 2u, P17_5, P17_5_TCPWM1_LINE514}, 1221 {5u, 4u, P17_6, P17_6_TCPWM1_LINE260}, 1222 {5u, 5u, P17_7, P17_7_TCPWM1_LINE261}, 1223 {5u, 6u, P18_0, P18_0_TCPWM1_LINE262}, 1224 {6u, 0u, P18_0, P18_0_TCPWM1_LINE512}, 1225 {5u, 7u, P18_1, P18_1_TCPWM1_LINE263}, 1226 {4u, 55u, P18_2, P18_2_TCPWM1_LINE55}, 1227 {6u, 1u, P18_2, P18_2_TCPWM1_LINE513}, 1228 {4u, 54u, P18_3, P18_3_TCPWM1_LINE54}, 1229 {1u, 2u, P18_4, P18_4_TCPWM0_LINE258}, 1230 {4u, 53u, P18_4, P18_4_TCPWM1_LINE53}, 1231 {6u, 2u, P18_4, P18_4_TCPWM1_LINE514}, 1232 {4u, 52u, P18_5, P18_5_TCPWM1_LINE52}, 1233 {4u, 51u, P18_6, P18_6_TCPWM1_LINE51}, 1234 {6u, 3u, P18_6, P18_6_TCPWM1_LINE515}, 1235 {4u, 50u, P18_7, P18_7_TCPWM1_LINE50}, 1236 {5u, 3u, P19_0, P19_0_TCPWM1_LINE259}, 1237 {4u, 26u, P19_1, P19_1_TCPWM1_LINE26}, 1238 {4u, 27u, P19_2, P19_2_TCPWM1_LINE27}, 1239 {4u, 28u, P19_3, P19_3_TCPWM1_LINE28}, 1240 {4u, 29u, P19_4, P19_4_TCPWM1_LINE29}, 1241 {4u, 30u, P20_0, P20_0_TCPWM1_LINE30}, 1242 {4u, 49u, P20_1, P20_1_TCPWM1_LINE49}, 1243 {4u, 48u, P20_2, P20_2_TCPWM1_LINE48}, 1244 {4u, 47u, P20_3, P20_3_TCPWM1_LINE47}, 1245 {4u, 46u, P20_4, P20_4_TCPWM1_LINE46}, 1246 {4u, 45u, P20_5, P20_5_TCPWM1_LINE45}, 1247 {4u, 44u, P20_6, P20_6_TCPWM1_LINE44}, 1248 {4u, 43u, P20_7, P20_7_TCPWM1_LINE43}, 1249 {4u, 42u, P21_0, P21_0_TCPWM1_LINE42}, 1250 {4u, 41u, P21_1, P21_1_TCPWM1_LINE41}, 1251 {4u, 40u, P21_2, P21_2_TCPWM1_LINE40}, 1252 {4u, 39u, P21_3, P21_3_TCPWM1_LINE39}, 1253 {4u, 38u, P21_4, P21_4_TCPWM1_LINE38}, 1254 {4u, 34u, P21_5, P21_5_TCPWM1_LINE34}, 1255 {4u, 37u, P21_5, P21_5_TCPWM1_LINE37}, 1256 {4u, 36u, P21_6, P21_6_TCPWM1_LINE36}, 1257 {4u, 35u, P21_7, P21_7_TCPWM1_LINE35}, 1258 {4u, 33u, P22_1, P22_1_TCPWM1_LINE33}, 1259 {4u, 32u, P22_2, P22_2_TCPWM1_LINE32}, 1260 {4u, 31u, P22_3, P22_3_TCPWM1_LINE31}, 1261 {4u, 30u, P22_4, P22_4_TCPWM1_LINE30}, 1262 {4u, 29u, P22_5, P22_5_TCPWM1_LINE29}, 1263 {6u, 8u, P22_5, P22_5_TCPWM1_LINE520}, 1264 {4u, 28u, P22_6, P22_6_TCPWM1_LINE28}, 1265 {4u, 27u, P22_7, P22_7_TCPWM1_LINE27}, 1266 {5u, 8u, P23_0, P23_0_TCPWM1_LINE264}, 1267 {5u, 9u, P23_1, P23_1_TCPWM1_LINE265}, 1268 {5u, 10u, P23_2, P23_2_TCPWM1_LINE266}, 1269 {5u, 11u, P23_3, P23_3_TCPWM1_LINE267}, 1270 {4u, 25u, P23_4, P23_4_TCPWM1_LINE25}, 1271 {6u, 9u, P23_4, P23_4_TCPWM1_LINE521}, 1272 {4u, 24u, P23_5, P23_5_TCPWM1_LINE24}, 1273 {4u, 23u, P23_6, P23_6_TCPWM1_LINE23}, 1274 {4u, 22u, P23_7, P23_7_TCPWM1_LINE22}, 1275 }; 1276 1277 /* Connections for: tcpwm_line_compl */ 1278 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[182] = { 1279 {4u, 22u, P0_0, P0_0_TCPWM1_LINE_COMPL22}, 1280 {2u, 0u, P0_1, P0_1_TCPWM0_LINE_COMPL512}, 1281 {4u, 18u, P0_1, P0_1_TCPWM1_LINE_COMPL18}, 1282 {4u, 17u, P0_2, P0_2_TCPWM1_LINE_COMPL17}, 1283 {4u, 14u, P0_3, P0_3_TCPWM1_LINE_COMPL14}, 1284 {4u, 13u, P1_0, P1_0_TCPWM1_LINE_COMPL13}, 1285 {4u, 12u, P1_1, P1_1_TCPWM1_LINE_COMPL12}, 1286 {4u, 11u, P1_2, P1_2_TCPWM1_LINE_COMPL11}, 1287 {4u, 10u, P1_3, P1_3_TCPWM1_LINE_COMPL10}, 1288 {4u, 8u, P2_0, P2_0_TCPWM1_LINE_COMPL8}, 1289 {4u, 7u, P2_1, P2_1_TCPWM1_LINE_COMPL7}, 1290 {4u, 6u, P2_2, P2_2_TCPWM1_LINE_COMPL6}, 1291 {4u, 5u, P2_3, P2_3_TCPWM1_LINE_COMPL5}, 1292 {4u, 4u, P2_4, P2_4_TCPWM1_LINE_COMPL4}, 1293 {6u, 4u, P2_4, P2_4_TCPWM1_LINE_COMPL516}, 1294 {4u, 3u, P2_5, P2_5_TCPWM1_LINE_COMPL3}, 1295 {6u, 5u, P2_5, P2_5_TCPWM1_LINE_COMPL517}, 1296 {4u, 2u, P3_0, P3_0_TCPWM1_LINE_COMPL2}, 1297 {6u, 6u, P3_0, P3_0_TCPWM1_LINE_COMPL518}, 1298 {4u, 1u, P3_1, P3_1_TCPWM1_LINE_COMPL1}, 1299 {6u, 7u, P3_1, P3_1_TCPWM1_LINE_COMPL519}, 1300 {4u, 0u, P3_2, P3_2_TCPWM1_LINE_COMPL0}, 1301 {5u, 3u, P3_3, P3_3_TCPWM1_LINE_COMPL259}, 1302 {5u, 2u, P3_4, P3_4_TCPWM1_LINE_COMPL258}, 1303 {5u, 1u, P3_5, P3_5_TCPWM1_LINE_COMPL257}, 1304 {5u, 0u, P4_0, P4_0_TCPWM1_LINE_COMPL256}, 1305 {4u, 4u, P4_1, P4_1_TCPWM1_LINE_COMPL4}, 1306 {4u, 5u, P4_2, P4_2_TCPWM1_LINE_COMPL5}, 1307 {4u, 6u, P4_3, P4_3_TCPWM1_LINE_COMPL6}, 1308 {4u, 7u, P4_4, P4_4_TCPWM1_LINE_COMPL7}, 1309 {4u, 8u, P5_0, P5_0_TCPWM1_LINE_COMPL8}, 1310 {1u, 0u, P5_1, P5_1_TCPWM0_LINE_COMPL256}, 1311 {4u, 9u, P5_1, P5_1_TCPWM1_LINE_COMPL9}, 1312 {6u, 10u, P5_1, P5_1_TCPWM1_LINE_COMPL522}, 1313 {4u, 10u, P5_2, P5_2_TCPWM1_LINE_COMPL10}, 1314 {4u, 11u, P5_3, P5_3_TCPWM1_LINE_COMPL11}, 1315 {4u, 12u, P5_4, P5_4_TCPWM1_LINE_COMPL12}, 1316 {4u, 13u, P5_5, P5_5_TCPWM1_LINE_COMPL13}, 1317 {6u, 11u, P5_5, P5_5_TCPWM1_LINE_COMPL523}, 1318 {4u, 14u, P6_0, P6_0_TCPWM1_LINE_COMPL14}, 1319 {5u, 0u, P6_1, P6_1_TCPWM1_LINE_COMPL256}, 1320 {0u, 0u, P6_2, P6_2_TCPWM0_LINE_COMPL0}, 1321 {4u, 0u, P6_2, P6_2_TCPWM1_LINE_COMPL0}, 1322 {5u, 1u, P6_3, P6_3_TCPWM1_LINE_COMPL257}, 1323 {6u, 12u, P6_3, P6_3_TCPWM1_LINE_COMPL524}, 1324 {4u, 1u, P6_4, P6_4_TCPWM1_LINE_COMPL1}, 1325 {5u, 2u, P6_5, P6_5_TCPWM1_LINE_COMPL258}, 1326 {4u, 2u, P6_6, P6_6_TCPWM1_LINE_COMPL2}, 1327 {5u, 3u, P6_7, P6_7_TCPWM1_LINE_COMPL259}, 1328 {4u, 3u, P7_0, P7_0_TCPWM1_LINE_COMPL3}, 1329 {5u, 4u, P7_1, P7_1_TCPWM1_LINE_COMPL260}, 1330 {0u, 1u, P7_2, P7_2_TCPWM0_LINE_COMPL1}, 1331 {4u, 15u, P7_2, P7_2_TCPWM1_LINE_COMPL15}, 1332 {5u, 5u, P7_3, P7_3_TCPWM1_LINE_COMPL261}, 1333 {4u, 16u, P7_4, P7_4_TCPWM1_LINE_COMPL16}, 1334 {5u, 6u, P7_5, P7_5_TCPWM1_LINE_COMPL262}, 1335 {4u, 17u, P7_6, P7_6_TCPWM1_LINE_COMPL17}, 1336 {5u, 7u, P7_7, P7_7_TCPWM1_LINE_COMPL263}, 1337 {2u, 2u, P8_0, P8_0_TCPWM0_LINE_COMPL514}, 1338 {4u, 18u, P8_0, P8_0_TCPWM1_LINE_COMPL18}, 1339 {4u, 19u, P8_1, P8_1_TCPWM1_LINE_COMPL19}, 1340 {6u, 8u, P8_1, P8_1_TCPWM1_LINE_COMPL520}, 1341 {4u, 20u, P8_2, P8_2_TCPWM1_LINE_COMPL20}, 1342 {4u, 21u, P8_3, P8_3_TCPWM1_LINE_COMPL21}, 1343 {4u, 22u, P8_4, P8_4_TCPWM1_LINE_COMPL22}, 1344 {4u, 23u, P9_0, P9_0_TCPWM1_LINE_COMPL23}, 1345 {4u, 24u, P9_1, P9_1_TCPWM1_LINE_COMPL24}, 1346 {6u, 9u, P9_1, P9_1_TCPWM1_LINE_COMPL521}, 1347 {4u, 25u, P9_2, P9_2_TCPWM1_LINE_COMPL25}, 1348 {4u, 26u, P9_3, P9_3_TCPWM1_LINE_COMPL26}, 1349 {4u, 27u, P10_0, P10_0_TCPWM1_LINE_COMPL27}, 1350 {4u, 28u, P10_1, P10_1_TCPWM1_LINE_COMPL28}, 1351 {6u, 10u, P10_1, P10_1_TCPWM1_LINE_COMPL522}, 1352 {4u, 29u, P10_2, P10_2_TCPWM1_LINE_COMPL29}, 1353 {4u, 30u, P10_3, P10_3_TCPWM1_LINE_COMPL30}, 1354 {4u, 31u, P10_4, P10_4_TCPWM1_LINE_COMPL31}, 1355 {4u, 32u, P10_5, P10_5_TCPWM1_LINE_COMPL32}, 1356 {6u, 11u, P10_5, P10_5_TCPWM1_LINE_COMPL523}, 1357 {4u, 33u, P10_6, P10_6_TCPWM1_LINE_COMPL33}, 1358 {4u, 34u, P10_7, P10_7_TCPWM1_LINE_COMPL34}, 1359 {4u, 62u, P11_0, P11_0_TCPWM1_LINE_COMPL62}, 1360 {4u, 61u, P11_1, P11_1_TCPWM1_LINE_COMPL61}, 1361 {4u, 60u, P11_2, P11_2_TCPWM1_LINE_COMPL60}, 1362 {4u, 35u, P12_0, P12_0_TCPWM1_LINE_COMPL35}, 1363 {2u, 1u, P12_1, P12_1_TCPWM0_LINE_COMPL513}, 1364 {4u, 36u, P12_1, P12_1_TCPWM1_LINE_COMPL36}, 1365 {4u, 37u, P12_2, P12_2_TCPWM1_LINE_COMPL37}, 1366 {4u, 38u, P12_3, P12_3_TCPWM1_LINE_COMPL38}, 1367 {4u, 39u, P12_4, P12_4_TCPWM1_LINE_COMPL39}, 1368 {4u, 40u, P12_5, P12_5_TCPWM1_LINE_COMPL40}, 1369 {4u, 41u, P12_6, P12_6_TCPWM1_LINE_COMPL41}, 1370 {4u, 42u, P12_7, P12_7_TCPWM1_LINE_COMPL42}, 1371 {4u, 43u, P13_0, P13_0_TCPWM1_LINE_COMPL43}, 1372 {0u, 2u, P13_1, P13_1_TCPWM0_LINE_COMPL2}, 1373 {5u, 8u, P13_1, P13_1_TCPWM1_LINE_COMPL264}, 1374 {4u, 44u, P13_2, P13_2_TCPWM1_LINE_COMPL44}, 1375 {5u, 9u, P13_3, P13_3_TCPWM1_LINE_COMPL265}, 1376 {4u, 45u, P13_4, P13_4_TCPWM1_LINE_COMPL45}, 1377 {5u, 10u, P13_5, P13_5_TCPWM1_LINE_COMPL266}, 1378 {6u, 4u, P13_5, P13_5_TCPWM1_LINE_COMPL516}, 1379 {4u, 46u, P13_6, P13_6_TCPWM1_LINE_COMPL46}, 1380 {5u, 11u, P13_7, P13_7_TCPWM1_LINE_COMPL267}, 1381 {6u, 5u, P13_7, P13_7_TCPWM1_LINE_COMPL517}, 1382 {4u, 47u, P14_0, P14_0_TCPWM1_LINE_COMPL47}, 1383 {1u, 1u, P14_1, P14_1_TCPWM0_LINE_COMPL257}, 1384 {4u, 48u, P14_1, P14_1_TCPWM1_LINE_COMPL48}, 1385 {6u, 6u, P14_1, P14_1_TCPWM1_LINE_COMPL518}, 1386 {4u, 49u, P14_2, P14_2_TCPWM1_LINE_COMPL49}, 1387 {4u, 50u, P14_3, P14_3_TCPWM1_LINE_COMPL50}, 1388 {6u, 7u, P14_3, P14_3_TCPWM1_LINE_COMPL519}, 1389 {4u, 51u, P14_4, P14_4_TCPWM1_LINE_COMPL51}, 1390 {4u, 52u, P14_5, P14_5_TCPWM1_LINE_COMPL52}, 1391 {4u, 53u, P14_6, P14_6_TCPWM1_LINE_COMPL53}, 1392 {4u, 54u, P14_7, P14_7_TCPWM1_LINE_COMPL54}, 1393 {4u, 55u, P15_0, P15_0_TCPWM1_LINE_COMPL55}, 1394 {4u, 56u, P15_1, P15_1_TCPWM1_LINE_COMPL56}, 1395 {4u, 57u, P15_2, P15_2_TCPWM1_LINE_COMPL57}, 1396 {4u, 58u, P15_3, P15_3_TCPWM1_LINE_COMPL58}, 1397 {4u, 62u, P16_3, P16_3_TCPWM1_LINE_COMPL62}, 1398 {6u, 1u, P16_3, P16_3_TCPWM1_LINE_COMPL513}, 1399 {4u, 62u, P17_0, P17_0_TCPWM1_LINE_COMPL62}, 1400 {4u, 61u, P17_1, P17_1_TCPWM1_LINE_COMPL61}, 1401 {4u, 60u, P17_2, P17_2_TCPWM1_LINE_COMPL60}, 1402 {4u, 59u, P17_3, P17_3_TCPWM1_LINE_COMPL59}, 1403 {4u, 58u, P17_4, P17_4_TCPWM1_LINE_COMPL58}, 1404 {6u, 3u, P17_4, P17_4_TCPWM1_LINE_COMPL515}, 1405 {4u, 57u, P17_5, P17_5_TCPWM1_LINE_COMPL57}, 1406 {4u, 56u, P17_6, P17_6_TCPWM1_LINE_COMPL56}, 1407 {6u, 2u, P17_6, P17_6_TCPWM1_LINE_COMPL514}, 1408 {5u, 4u, P17_7, P17_7_TCPWM1_LINE_COMPL260}, 1409 {5u, 5u, P18_0, P18_0_TCPWM1_LINE_COMPL261}, 1410 {5u, 6u, P18_1, P18_1_TCPWM1_LINE_COMPL262}, 1411 {6u, 0u, P18_1, P18_1_TCPWM1_LINE_COMPL512}, 1412 {5u, 7u, P18_2, P18_2_TCPWM1_LINE_COMPL263}, 1413 {4u, 55u, P18_3, P18_3_TCPWM1_LINE_COMPL55}, 1414 {6u, 1u, P18_3, P18_3_TCPWM1_LINE_COMPL513}, 1415 {4u, 54u, P18_4, P18_4_TCPWM1_LINE_COMPL54}, 1416 {1u, 2u, P18_5, P18_5_TCPWM0_LINE_COMPL258}, 1417 {4u, 53u, P18_5, P18_5_TCPWM1_LINE_COMPL53}, 1418 {6u, 2u, P18_5, P18_5_TCPWM1_LINE_COMPL514}, 1419 {4u, 52u, P18_6, P18_6_TCPWM1_LINE_COMPL52}, 1420 {4u, 51u, P18_7, P18_7_TCPWM1_LINE_COMPL51}, 1421 {6u, 3u, P18_7, P18_7_TCPWM1_LINE_COMPL515}, 1422 {4u, 50u, P19_0, P19_0_TCPWM1_LINE_COMPL50}, 1423 {5u, 3u, P19_1, P19_1_TCPWM1_LINE_COMPL259}, 1424 {4u, 26u, P19_2, P19_2_TCPWM1_LINE_COMPL26}, 1425 {4u, 27u, P19_3, P19_3_TCPWM1_LINE_COMPL27}, 1426 {4u, 28u, P19_4, P19_4_TCPWM1_LINE_COMPL28}, 1427 {4u, 29u, P20_0, P20_0_TCPWM1_LINE_COMPL29}, 1428 {4u, 30u, P20_1, P20_1_TCPWM1_LINE_COMPL30}, 1429 {4u, 49u, P20_2, P20_2_TCPWM1_LINE_COMPL49}, 1430 {4u, 48u, P20_3, P20_3_TCPWM1_LINE_COMPL48}, 1431 {4u, 47u, P20_4, P20_4_TCPWM1_LINE_COMPL47}, 1432 {4u, 46u, P20_5, P20_5_TCPWM1_LINE_COMPL46}, 1433 {4u, 45u, P20_6, P20_6_TCPWM1_LINE_COMPL45}, 1434 {4u, 44u, P20_7, P20_7_TCPWM1_LINE_COMPL44}, 1435 {4u, 43u, P21_0, P21_0_TCPWM1_LINE_COMPL43}, 1436 {4u, 42u, P21_1, P21_1_TCPWM1_LINE_COMPL42}, 1437 {4u, 41u, P21_2, P21_2_TCPWM1_LINE_COMPL41}, 1438 {4u, 40u, P21_3, P21_3_TCPWM1_LINE_COMPL40}, 1439 {4u, 39u, P21_4, P21_4_TCPWM1_LINE_COMPL39}, 1440 {4u, 35u, P21_5, P21_5_TCPWM1_LINE_COMPL35}, 1441 {4u, 38u, P21_5, P21_5_TCPWM1_LINE_COMPL38}, 1442 {4u, 37u, P21_6, P21_6_TCPWM1_LINE_COMPL37}, 1443 {4u, 36u, P21_7, P21_7_TCPWM1_LINE_COMPL36}, 1444 {4u, 34u, P22_1, P22_1_TCPWM1_LINE_COMPL34}, 1445 {4u, 33u, P22_2, P22_2_TCPWM1_LINE_COMPL33}, 1446 {4u, 32u, P22_3, P22_3_TCPWM1_LINE_COMPL32}, 1447 {4u, 31u, P22_4, P22_4_TCPWM1_LINE_COMPL31}, 1448 {4u, 30u, P22_5, P22_5_TCPWM1_LINE_COMPL30}, 1449 {4u, 29u, P22_6, P22_6_TCPWM1_LINE_COMPL29}, 1450 {6u, 8u, P22_6, P22_6_TCPWM1_LINE_COMPL520}, 1451 {4u, 28u, P22_7, P22_7_TCPWM1_LINE_COMPL28}, 1452 {4u, 27u, P23_0, P23_0_TCPWM1_LINE_COMPL27}, 1453 {5u, 8u, P23_1, P23_1_TCPWM1_LINE_COMPL264}, 1454 {5u, 9u, P23_2, P23_2_TCPWM1_LINE_COMPL265}, 1455 {5u, 10u, P23_3, P23_3_TCPWM1_LINE_COMPL266}, 1456 {5u, 11u, P23_4, P23_4_TCPWM1_LINE_COMPL267}, 1457 {4u, 25u, P23_5, P23_5_TCPWM1_LINE_COMPL25}, 1458 {6u, 9u, P23_5, P23_5_TCPWM1_LINE_COMPL521}, 1459 {4u, 24u, P23_6, P23_6_TCPWM1_LINE_COMPL24}, 1460 {4u, 23u, P23_7, P23_7_TCPWM1_LINE_COMPL23}, 1461 }; 1462 1463 /* Connections for: tcpwm_tr_one_cnt_in */ 1464 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[358] = { 1465 {4u, 54u, P0_0, P0_0_TCPWM1_TR_ONE_CNT_IN54}, 1466 {4u, 67u, P0_0, P0_0_TCPWM1_TR_ONE_CNT_IN67}, 1467 {4u, 51u, P0_1, P0_1_TCPWM1_TR_ONE_CNT_IN51}, 1468 {4u, 55u, P0_1, P0_1_TCPWM1_TR_ONE_CNT_IN55}, 1469 {4u, 42u, P0_2, P0_2_TCPWM1_TR_ONE_CNT_IN42}, 1470 {4u, 52u, P0_2, P0_2_TCPWM1_TR_ONE_CNT_IN52}, 1471 {6u, 0u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN1536}, 1472 {4u, 39u, P0_3, P0_3_TCPWM1_TR_ONE_CNT_IN39}, 1473 {4u, 43u, P0_3, P0_3_TCPWM1_TR_ONE_CNT_IN43}, 1474 {6u, 1u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN1537}, 1475 {4u, 36u, P1_0, P1_0_TCPWM1_TR_ONE_CNT_IN36}, 1476 {4u, 40u, P1_0, P1_0_TCPWM1_TR_ONE_CNT_IN40}, 1477 {4u, 33u, P1_1, P1_1_TCPWM1_TR_ONE_CNT_IN33}, 1478 {4u, 37u, P1_1, P1_1_TCPWM1_TR_ONE_CNT_IN37}, 1479 {4u, 30u, P1_2, P1_2_TCPWM1_TR_ONE_CNT_IN30}, 1480 {4u, 34u, P1_2, P1_2_TCPWM1_TR_ONE_CNT_IN34}, 1481 {4u, 24u, P1_3, P1_3_TCPWM1_TR_ONE_CNT_IN24}, 1482 {4u, 31u, P1_3, P1_3_TCPWM1_TR_ONE_CNT_IN31}, 1483 {4u, 21u, P2_0, P2_0_TCPWM1_TR_ONE_CNT_IN21}, 1484 {4u, 25u, P2_0, P2_0_TCPWM1_TR_ONE_CNT_IN25}, 1485 {10u, 12u, P2_0, P2_0_TCPWM1_TR_ONE_CNT_IN1548}, 1486 {4u, 18u, P2_1, P2_1_TCPWM1_TR_ONE_CNT_IN18}, 1487 {4u, 22u, P2_1, P2_1_TCPWM1_TR_ONE_CNT_IN22}, 1488 {10u, 15u, P2_1, P2_1_TCPWM1_TR_ONE_CNT_IN1551}, 1489 {4u, 15u, P2_2, P2_2_TCPWM1_TR_ONE_CNT_IN15}, 1490 {4u, 19u, P2_2, P2_2_TCPWM1_TR_ONE_CNT_IN19}, 1491 {10u, 18u, P2_2, P2_2_TCPWM1_TR_ONE_CNT_IN1554}, 1492 {4u, 12u, P2_3, P2_3_TCPWM1_TR_ONE_CNT_IN12}, 1493 {4u, 16u, P2_3, P2_3_TCPWM1_TR_ONE_CNT_IN16}, 1494 {10u, 21u, P2_3, P2_3_TCPWM1_TR_ONE_CNT_IN1557}, 1495 {4u, 9u, P2_4, P2_4_TCPWM1_TR_ONE_CNT_IN9}, 1496 {4u, 13u, P2_4, P2_4_TCPWM1_TR_ONE_CNT_IN13}, 1497 {4u, 6u, P2_5, P2_5_TCPWM1_TR_ONE_CNT_IN6}, 1498 {4u, 10u, P2_5, P2_5_TCPWM1_TR_ONE_CNT_IN10}, 1499 {4u, 3u, P3_0, P3_0_TCPWM1_TR_ONE_CNT_IN3}, 1500 {4u, 7u, P3_0, P3_0_TCPWM1_TR_ONE_CNT_IN7}, 1501 {4u, 0u, P3_1, P3_1_TCPWM1_TR_ONE_CNT_IN0}, 1502 {4u, 4u, P3_1, P3_1_TCPWM1_TR_ONE_CNT_IN4}, 1503 {4u, 1u, P3_2, P3_2_TCPWM1_TR_ONE_CNT_IN1}, 1504 {7u, 9u, P3_2, P3_2_TCPWM1_TR_ONE_CNT_IN777}, 1505 {10u, 13u, P3_2, P3_2_TCPWM1_TR_ONE_CNT_IN1549}, 1506 {7u, 6u, P3_3, P3_3_TCPWM1_TR_ONE_CNT_IN774}, 1507 {7u, 10u, P3_3, P3_3_TCPWM1_TR_ONE_CNT_IN778}, 1508 {10u, 16u, P3_3, P3_3_TCPWM1_TR_ONE_CNT_IN1552}, 1509 {7u, 3u, P3_4, P3_4_TCPWM1_TR_ONE_CNT_IN771}, 1510 {7u, 7u, P3_4, P3_4_TCPWM1_TR_ONE_CNT_IN775}, 1511 {10u, 19u, P3_4, P3_4_TCPWM1_TR_ONE_CNT_IN1555}, 1512 {7u, 0u, P3_5, P3_5_TCPWM1_TR_ONE_CNT_IN768}, 1513 {7u, 4u, P3_5, P3_5_TCPWM1_TR_ONE_CNT_IN772}, 1514 {10u, 22u, P3_5, P3_5_TCPWM1_TR_ONE_CNT_IN1558}, 1515 {4u, 12u, P4_0, P4_0_TCPWM1_TR_ONE_CNT_IN12}, 1516 {7u, 1u, P4_0, P4_0_TCPWM1_TR_ONE_CNT_IN769}, 1517 {4u, 13u, P4_1, P4_1_TCPWM1_TR_ONE_CNT_IN13}, 1518 {4u, 15u, P4_1, P4_1_TCPWM1_TR_ONE_CNT_IN15}, 1519 {4u, 16u, P4_2, P4_2_TCPWM1_TR_ONE_CNT_IN16}, 1520 {4u, 18u, P4_2, P4_2_TCPWM1_TR_ONE_CNT_IN18}, 1521 {4u, 19u, P4_3, P4_3_TCPWM1_TR_ONE_CNT_IN19}, 1522 {4u, 21u, P4_3, P4_3_TCPWM1_TR_ONE_CNT_IN21}, 1523 {4u, 22u, P4_4, P4_4_TCPWM1_TR_ONE_CNT_IN22}, 1524 {4u, 24u, P4_4, P4_4_TCPWM1_TR_ONE_CNT_IN24}, 1525 {4u, 25u, P5_0, P5_0_TCPWM1_TR_ONE_CNT_IN25}, 1526 {4u, 27u, P5_0, P5_0_TCPWM1_TR_ONE_CNT_IN27}, 1527 {4u, 28u, P5_1, P5_1_TCPWM1_TR_ONE_CNT_IN28}, 1528 {4u, 30u, P5_1, P5_1_TCPWM1_TR_ONE_CNT_IN30}, 1529 {3u, 0u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN768}, 1530 {4u, 31u, P5_2, P5_2_TCPWM1_TR_ONE_CNT_IN31}, 1531 {4u, 33u, P5_2, P5_2_TCPWM1_TR_ONE_CNT_IN33}, 1532 {10u, 30u, P5_2, P5_2_TCPWM1_TR_ONE_CNT_IN1566}, 1533 {3u, 1u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN769}, 1534 {4u, 34u, P5_3, P5_3_TCPWM1_TR_ONE_CNT_IN34}, 1535 {4u, 36u, P5_3, P5_3_TCPWM1_TR_ONE_CNT_IN36}, 1536 {10u, 31u, P5_3, P5_3_TCPWM1_TR_ONE_CNT_IN1567}, 1537 {4u, 37u, P5_4, P5_4_TCPWM1_TR_ONE_CNT_IN37}, 1538 {4u, 39u, P5_4, P5_4_TCPWM1_TR_ONE_CNT_IN39}, 1539 {4u, 40u, P5_5, P5_5_TCPWM1_TR_ONE_CNT_IN40}, 1540 {4u, 42u, P5_5, P5_5_TCPWM1_TR_ONE_CNT_IN42}, 1541 {4u, 43u, P6_0, P6_0_TCPWM1_TR_ONE_CNT_IN43}, 1542 {7u, 0u, P6_0, P6_0_TCPWM1_TR_ONE_CNT_IN768}, 1543 {10u, 33u, P6_0, P6_0_TCPWM1_TR_ONE_CNT_IN1569}, 1544 {4u, 0u, P6_1, P6_1_TCPWM1_TR_ONE_CNT_IN0}, 1545 {7u, 1u, P6_1, P6_1_TCPWM1_TR_ONE_CNT_IN769}, 1546 {10u, 34u, P6_1, P6_1_TCPWM1_TR_ONE_CNT_IN1570}, 1547 {4u, 1u, P6_2, P6_2_TCPWM1_TR_ONE_CNT_IN1}, 1548 {7u, 3u, P6_2, P6_2_TCPWM1_TR_ONE_CNT_IN771}, 1549 {4u, 3u, P6_3, P6_3_TCPWM1_TR_ONE_CNT_IN3}, 1550 {7u, 4u, P6_3, P6_3_TCPWM1_TR_ONE_CNT_IN772}, 1551 {0u, 0u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN0}, 1552 {4u, 4u, P6_4, P6_4_TCPWM1_TR_ONE_CNT_IN4}, 1553 {7u, 6u, P6_4, P6_4_TCPWM1_TR_ONE_CNT_IN774}, 1554 {10u, 36u, P6_4, P6_4_TCPWM1_TR_ONE_CNT_IN1572}, 1555 {0u, 1u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN1}, 1556 {4u, 6u, P6_5, P6_5_TCPWM1_TR_ONE_CNT_IN6}, 1557 {7u, 7u, P6_5, P6_5_TCPWM1_TR_ONE_CNT_IN775}, 1558 {10u, 37u, P6_5, P6_5_TCPWM1_TR_ONE_CNT_IN1573}, 1559 {4u, 7u, P6_6, P6_6_TCPWM1_TR_ONE_CNT_IN7}, 1560 {7u, 9u, P6_6, P6_6_TCPWM1_TR_ONE_CNT_IN777}, 1561 {4u, 9u, P6_7, P6_7_TCPWM1_TR_ONE_CNT_IN9}, 1562 {7u, 10u, P6_7, P6_7_TCPWM1_TR_ONE_CNT_IN778}, 1563 {4u, 10u, P7_0, P7_0_TCPWM1_TR_ONE_CNT_IN10}, 1564 {7u, 12u, P7_0, P7_0_TCPWM1_TR_ONE_CNT_IN780}, 1565 {4u, 45u, P7_1, P7_1_TCPWM1_TR_ONE_CNT_IN45}, 1566 {7u, 13u, P7_1, P7_1_TCPWM1_TR_ONE_CNT_IN781}, 1567 {4u, 46u, P7_2, P7_2_TCPWM1_TR_ONE_CNT_IN46}, 1568 {7u, 15u, P7_2, P7_2_TCPWM1_TR_ONE_CNT_IN783}, 1569 {0u, 3u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN3}, 1570 {4u, 48u, P7_3, P7_3_TCPWM1_TR_ONE_CNT_IN48}, 1571 {7u, 16u, P7_3, P7_3_TCPWM1_TR_ONE_CNT_IN784}, 1572 {0u, 4u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN4}, 1573 {4u, 49u, P7_4, P7_4_TCPWM1_TR_ONE_CNT_IN49}, 1574 {7u, 18u, P7_4, P7_4_TCPWM1_TR_ONE_CNT_IN786}, 1575 {4u, 51u, P7_5, P7_5_TCPWM1_TR_ONE_CNT_IN51}, 1576 {7u, 19u, P7_5, P7_5_TCPWM1_TR_ONE_CNT_IN787}, 1577 {4u, 52u, P7_6, P7_6_TCPWM1_TR_ONE_CNT_IN52}, 1578 {7u, 21u, P7_6, P7_6_TCPWM1_TR_ONE_CNT_IN789}, 1579 {4u, 54u, P7_7, P7_7_TCPWM1_TR_ONE_CNT_IN54}, 1580 {7u, 22u, P7_7, P7_7_TCPWM1_TR_ONE_CNT_IN790}, 1581 {4u, 55u, P8_0, P8_0_TCPWM1_TR_ONE_CNT_IN55}, 1582 {4u, 57u, P8_0, P8_0_TCPWM1_TR_ONE_CNT_IN57}, 1583 {4u, 58u, P8_1, P8_1_TCPWM1_TR_ONE_CNT_IN58}, 1584 {4u, 60u, P8_1, P8_1_TCPWM1_TR_ONE_CNT_IN60}, 1585 {6u, 6u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN1542}, 1586 {4u, 61u, P8_2, P8_2_TCPWM1_TR_ONE_CNT_IN61}, 1587 {4u, 63u, P8_2, P8_2_TCPWM1_TR_ONE_CNT_IN63}, 1588 {6u, 7u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN1543}, 1589 {10u, 24u, P8_2, P8_2_TCPWM1_TR_ONE_CNT_IN1560}, 1590 {4u, 64u, P8_3, P8_3_TCPWM1_TR_ONE_CNT_IN64}, 1591 {4u, 66u, P8_3, P8_3_TCPWM1_TR_ONE_CNT_IN66}, 1592 {10u, 25u, P8_3, P8_3_TCPWM1_TR_ONE_CNT_IN1561}, 1593 {4u, 67u, P8_4, P8_4_TCPWM1_TR_ONE_CNT_IN67}, 1594 {4u, 69u, P8_4, P8_4_TCPWM1_TR_ONE_CNT_IN69}, 1595 {4u, 70u, P9_0, P9_0_TCPWM1_TR_ONE_CNT_IN70}, 1596 {4u, 72u, P9_0, P9_0_TCPWM1_TR_ONE_CNT_IN72}, 1597 {4u, 73u, P9_1, P9_1_TCPWM1_TR_ONE_CNT_IN73}, 1598 {4u, 75u, P9_1, P9_1_TCPWM1_TR_ONE_CNT_IN75}, 1599 {4u, 76u, P9_2, P9_2_TCPWM1_TR_ONE_CNT_IN76}, 1600 {4u, 78u, P9_2, P9_2_TCPWM1_TR_ONE_CNT_IN78}, 1601 {10u, 27u, P9_2, P9_2_TCPWM1_TR_ONE_CNT_IN1563}, 1602 {4u, 79u, P9_3, P9_3_TCPWM1_TR_ONE_CNT_IN79}, 1603 {4u, 81u, P9_3, P9_3_TCPWM1_TR_ONE_CNT_IN81}, 1604 {10u, 28u, P9_3, P9_3_TCPWM1_TR_ONE_CNT_IN1564}, 1605 {4u, 82u, P10_0, P10_0_TCPWM1_TR_ONE_CNT_IN82}, 1606 {4u, 84u, P10_0, P10_0_TCPWM1_TR_ONE_CNT_IN84}, 1607 {4u, 85u, P10_1, P10_1_TCPWM1_TR_ONE_CNT_IN85}, 1608 {4u, 87u, P10_1, P10_1_TCPWM1_TR_ONE_CNT_IN87}, 1609 {4u, 88u, P10_2, P10_2_TCPWM1_TR_ONE_CNT_IN88}, 1610 {4u, 90u, P10_2, P10_2_TCPWM1_TR_ONE_CNT_IN90}, 1611 {10u, 30u, P10_2, P10_2_TCPWM1_TR_ONE_CNT_IN1566}, 1612 {4u, 91u, P10_3, P10_3_TCPWM1_TR_ONE_CNT_IN91}, 1613 {4u, 93u, P10_3, P10_3_TCPWM1_TR_ONE_CNT_IN93}, 1614 {10u, 31u, P10_3, P10_3_TCPWM1_TR_ONE_CNT_IN1567}, 1615 {4u, 94u, P10_4, P10_4_TCPWM1_TR_ONE_CNT_IN94}, 1616 {4u, 96u, P10_4, P10_4_TCPWM1_TR_ONE_CNT_IN96}, 1617 {4u, 97u, P10_5, P10_5_TCPWM1_TR_ONE_CNT_IN97}, 1618 {4u, 99u, P10_5, P10_5_TCPWM1_TR_ONE_CNT_IN99}, 1619 {4u, 100u, P10_6, P10_6_TCPWM1_TR_ONE_CNT_IN100}, 1620 {4u, 102u, P10_6, P10_6_TCPWM1_TR_ONE_CNT_IN102}, 1621 {10u, 33u, P10_6, P10_6_TCPWM1_TR_ONE_CNT_IN1569}, 1622 {4u, 103u, P10_7, P10_7_TCPWM1_TR_ONE_CNT_IN103}, 1623 {4u, 105u, P10_7, P10_7_TCPWM1_TR_ONE_CNT_IN105}, 1624 {10u, 34u, P10_7, P10_7_TCPWM1_TR_ONE_CNT_IN1570}, 1625 {4u, 183u, P11_0, P11_0_TCPWM1_TR_ONE_CNT_IN183}, 1626 {4u, 187u, P11_0, P11_0_TCPWM1_TR_ONE_CNT_IN187}, 1627 {4u, 180u, P11_1, P11_1_TCPWM1_TR_ONE_CNT_IN180}, 1628 {4u, 184u, P11_1, P11_1_TCPWM1_TR_ONE_CNT_IN184}, 1629 {4u, 177u, P11_2, P11_2_TCPWM1_TR_ONE_CNT_IN177}, 1630 {4u, 181u, P11_2, P11_2_TCPWM1_TR_ONE_CNT_IN181}, 1631 {4u, 106u, P12_0, P12_0_TCPWM1_TR_ONE_CNT_IN106}, 1632 {4u, 108u, P12_0, P12_0_TCPWM1_TR_ONE_CNT_IN108}, 1633 {4u, 109u, P12_1, P12_1_TCPWM1_TR_ONE_CNT_IN109}, 1634 {4u, 111u, P12_1, P12_1_TCPWM1_TR_ONE_CNT_IN111}, 1635 {4u, 112u, P12_2, P12_2_TCPWM1_TR_ONE_CNT_IN112}, 1636 {4u, 114u, P12_2, P12_2_TCPWM1_TR_ONE_CNT_IN114}, 1637 {6u, 3u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN1539}, 1638 {4u, 115u, P12_3, P12_3_TCPWM1_TR_ONE_CNT_IN115}, 1639 {4u, 117u, P12_3, P12_3_TCPWM1_TR_ONE_CNT_IN117}, 1640 {6u, 4u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN1540}, 1641 {0u, 7u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN7}, 1642 {4u, 118u, P12_4, P12_4_TCPWM1_TR_ONE_CNT_IN118}, 1643 {4u, 120u, P12_4, P12_4_TCPWM1_TR_ONE_CNT_IN120}, 1644 {4u, 121u, P12_5, P12_5_TCPWM1_TR_ONE_CNT_IN121}, 1645 {4u, 123u, P12_5, P12_5_TCPWM1_TR_ONE_CNT_IN123}, 1646 {4u, 124u, P12_6, P12_6_TCPWM1_TR_ONE_CNT_IN124}, 1647 {4u, 126u, P12_6, P12_6_TCPWM1_TR_ONE_CNT_IN126}, 1648 {4u, 127u, P12_7, P12_7_TCPWM1_TR_ONE_CNT_IN127}, 1649 {4u, 129u, P12_7, P12_7_TCPWM1_TR_ONE_CNT_IN129}, 1650 {0u, 6u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN6}, 1651 {4u, 130u, P13_0, P13_0_TCPWM1_TR_ONE_CNT_IN130}, 1652 {7u, 24u, P13_0, P13_0_TCPWM1_TR_ONE_CNT_IN792}, 1653 {4u, 132u, P13_1, P13_1_TCPWM1_TR_ONE_CNT_IN132}, 1654 {7u, 25u, P13_1, P13_1_TCPWM1_TR_ONE_CNT_IN793}, 1655 {4u, 133u, P13_2, P13_2_TCPWM1_TR_ONE_CNT_IN133}, 1656 {7u, 27u, P13_2, P13_2_TCPWM1_TR_ONE_CNT_IN795}, 1657 {4u, 135u, P13_3, P13_3_TCPWM1_TR_ONE_CNT_IN135}, 1658 {7u, 28u, P13_3, P13_3_TCPWM1_TR_ONE_CNT_IN796}, 1659 {4u, 136u, P13_4, P13_4_TCPWM1_TR_ONE_CNT_IN136}, 1660 {7u, 30u, P13_4, P13_4_TCPWM1_TR_ONE_CNT_IN798}, 1661 {4u, 138u, P13_5, P13_5_TCPWM1_TR_ONE_CNT_IN138}, 1662 {7u, 31u, P13_5, P13_5_TCPWM1_TR_ONE_CNT_IN799}, 1663 {4u, 139u, P13_6, P13_6_TCPWM1_TR_ONE_CNT_IN139}, 1664 {7u, 33u, P13_6, P13_6_TCPWM1_TR_ONE_CNT_IN801}, 1665 {4u, 141u, P13_7, P13_7_TCPWM1_TR_ONE_CNT_IN141}, 1666 {7u, 34u, P13_7, P13_7_TCPWM1_TR_ONE_CNT_IN802}, 1667 {4u, 142u, P14_0, P14_0_TCPWM1_TR_ONE_CNT_IN142}, 1668 {4u, 144u, P14_0, P14_0_TCPWM1_TR_ONE_CNT_IN144}, 1669 {4u, 145u, P14_1, P14_1_TCPWM1_TR_ONE_CNT_IN145}, 1670 {4u, 147u, P14_1, P14_1_TCPWM1_TR_ONE_CNT_IN147}, 1671 {3u, 3u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN771}, 1672 {4u, 148u, P14_2, P14_2_TCPWM1_TR_ONE_CNT_IN148}, 1673 {4u, 150u, P14_2, P14_2_TCPWM1_TR_ONE_CNT_IN150}, 1674 {3u, 4u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN772}, 1675 {4u, 151u, P14_3, P14_3_TCPWM1_TR_ONE_CNT_IN151}, 1676 {4u, 153u, P14_3, P14_3_TCPWM1_TR_ONE_CNT_IN153}, 1677 {4u, 154u, P14_4, P14_4_TCPWM1_TR_ONE_CNT_IN154}, 1678 {4u, 156u, P14_4, P14_4_TCPWM1_TR_ONE_CNT_IN156}, 1679 {10u, 12u, P14_4, P14_4_TCPWM1_TR_ONE_CNT_IN1548}, 1680 {4u, 157u, P14_5, P14_5_TCPWM1_TR_ONE_CNT_IN157}, 1681 {4u, 159u, P14_5, P14_5_TCPWM1_TR_ONE_CNT_IN159}, 1682 {10u, 13u, P14_5, P14_5_TCPWM1_TR_ONE_CNT_IN1549}, 1683 {4u, 160u, P14_6, P14_6_TCPWM1_TR_ONE_CNT_IN160}, 1684 {4u, 162u, P14_6, P14_6_TCPWM1_TR_ONE_CNT_IN162}, 1685 {10u, 15u, P14_6, P14_6_TCPWM1_TR_ONE_CNT_IN1551}, 1686 {4u, 163u, P14_7, P14_7_TCPWM1_TR_ONE_CNT_IN163}, 1687 {4u, 165u, P14_7, P14_7_TCPWM1_TR_ONE_CNT_IN165}, 1688 {10u, 16u, P14_7, P14_7_TCPWM1_TR_ONE_CNT_IN1552}, 1689 {4u, 166u, P15_0, P15_0_TCPWM1_TR_ONE_CNT_IN166}, 1690 {4u, 168u, P15_0, P15_0_TCPWM1_TR_ONE_CNT_IN168}, 1691 {10u, 18u, P15_0, P15_0_TCPWM1_TR_ONE_CNT_IN1554}, 1692 {4u, 169u, P15_1, P15_1_TCPWM1_TR_ONE_CNT_IN169}, 1693 {4u, 171u, P15_1, P15_1_TCPWM1_TR_ONE_CNT_IN171}, 1694 {10u, 19u, P15_1, P15_1_TCPWM1_TR_ONE_CNT_IN1555}, 1695 {4u, 172u, P15_2, P15_2_TCPWM1_TR_ONE_CNT_IN172}, 1696 {4u, 174u, P15_2, P15_2_TCPWM1_TR_ONE_CNT_IN174}, 1697 {10u, 21u, P15_2, P15_2_TCPWM1_TR_ONE_CNT_IN1557}, 1698 {4u, 175u, P15_3, P15_3_TCPWM1_TR_ONE_CNT_IN175}, 1699 {4u, 177u, P15_3, P15_3_TCPWM1_TR_ONE_CNT_IN177}, 1700 {10u, 22u, P15_3, P15_3_TCPWM1_TR_ONE_CNT_IN1558}, 1701 {4u, 186u, P16_3, P16_3_TCPWM1_TR_ONE_CNT_IN186}, 1702 {4u, 187u, P16_3, P16_3_TCPWM1_TR_ONE_CNT_IN187}, 1703 {4u, 183u, P17_0, P17_0_TCPWM1_TR_ONE_CNT_IN183}, 1704 {4u, 187u, P17_0, P17_0_TCPWM1_TR_ONE_CNT_IN187}, 1705 {4u, 180u, P17_1, P17_1_TCPWM1_TR_ONE_CNT_IN180}, 1706 {4u, 184u, P17_1, P17_1_TCPWM1_TR_ONE_CNT_IN184}, 1707 {4u, 177u, P17_2, P17_2_TCPWM1_TR_ONE_CNT_IN177}, 1708 {4u, 181u, P17_2, P17_2_TCPWM1_TR_ONE_CNT_IN181}, 1709 {4u, 174u, P17_3, P17_3_TCPWM1_TR_ONE_CNT_IN174}, 1710 {4u, 178u, P17_3, P17_3_TCPWM1_TR_ONE_CNT_IN178}, 1711 {4u, 171u, P17_4, P17_4_TCPWM1_TR_ONE_CNT_IN171}, 1712 {4u, 175u, P17_4, P17_4_TCPWM1_TR_ONE_CNT_IN175}, 1713 {4u, 168u, P17_5, P17_5_TCPWM1_TR_ONE_CNT_IN168}, 1714 {4u, 172u, P17_5, P17_5_TCPWM1_TR_ONE_CNT_IN172}, 1715 {4u, 169u, P17_6, P17_6_TCPWM1_TR_ONE_CNT_IN169}, 1716 {7u, 12u, P17_6, P17_6_TCPWM1_TR_ONE_CNT_IN780}, 1717 {7u, 13u, P17_7, P17_7_TCPWM1_TR_ONE_CNT_IN781}, 1718 {7u, 15u, P17_7, P17_7_TCPWM1_TR_ONE_CNT_IN783}, 1719 {7u, 16u, P18_0, P18_0_TCPWM1_TR_ONE_CNT_IN784}, 1720 {7u, 18u, P18_0, P18_0_TCPWM1_TR_ONE_CNT_IN786}, 1721 {7u, 19u, P18_1, P18_1_TCPWM1_TR_ONE_CNT_IN787}, 1722 {7u, 21u, P18_1, P18_1_TCPWM1_TR_ONE_CNT_IN789}, 1723 {4u, 165u, P18_2, P18_2_TCPWM1_TR_ONE_CNT_IN165}, 1724 {7u, 22u, P18_2, P18_2_TCPWM1_TR_ONE_CNT_IN790}, 1725 {4u, 162u, P18_3, P18_3_TCPWM1_TR_ONE_CNT_IN162}, 1726 {4u, 166u, P18_3, P18_3_TCPWM1_TR_ONE_CNT_IN166}, 1727 {4u, 159u, P18_4, P18_4_TCPWM1_TR_ONE_CNT_IN159}, 1728 {4u, 163u, P18_4, P18_4_TCPWM1_TR_ONE_CNT_IN163}, 1729 {4u, 156u, P18_5, P18_5_TCPWM1_TR_ONE_CNT_IN156}, 1730 {4u, 160u, P18_5, P18_5_TCPWM1_TR_ONE_CNT_IN160}, 1731 {3u, 6u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN774}, 1732 {4u, 153u, P18_6, P18_6_TCPWM1_TR_ONE_CNT_IN153}, 1733 {4u, 157u, P18_6, P18_6_TCPWM1_TR_ONE_CNT_IN157}, 1734 {3u, 7u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN775}, 1735 {4u, 150u, P18_7, P18_7_TCPWM1_TR_ONE_CNT_IN150}, 1736 {4u, 154u, P18_7, P18_7_TCPWM1_TR_ONE_CNT_IN154}, 1737 {4u, 151u, P19_0, P19_0_TCPWM1_TR_ONE_CNT_IN151}, 1738 {7u, 9u, P19_0, P19_0_TCPWM1_TR_ONE_CNT_IN777}, 1739 {10u, 0u, P19_0, P19_0_TCPWM1_TR_ONE_CNT_IN1536}, 1740 {4u, 78u, P19_1, P19_1_TCPWM1_TR_ONE_CNT_IN78}, 1741 {7u, 10u, P19_1, P19_1_TCPWM1_TR_ONE_CNT_IN778}, 1742 {10u, 1u, P19_1, P19_1_TCPWM1_TR_ONE_CNT_IN1537}, 1743 {4u, 79u, P19_2, P19_2_TCPWM1_TR_ONE_CNT_IN79}, 1744 {4u, 81u, P19_2, P19_2_TCPWM1_TR_ONE_CNT_IN81}, 1745 {10u, 3u, P19_2, P19_2_TCPWM1_TR_ONE_CNT_IN1539}, 1746 {4u, 82u, P19_3, P19_3_TCPWM1_TR_ONE_CNT_IN82}, 1747 {4u, 84u, P19_3, P19_3_TCPWM1_TR_ONE_CNT_IN84}, 1748 {10u, 4u, P19_3, P19_3_TCPWM1_TR_ONE_CNT_IN1540}, 1749 {4u, 85u, P19_4, P19_4_TCPWM1_TR_ONE_CNT_IN85}, 1750 {4u, 87u, P19_4, P19_4_TCPWM1_TR_ONE_CNT_IN87}, 1751 {10u, 6u, P19_4, P19_4_TCPWM1_TR_ONE_CNT_IN1542}, 1752 {4u, 88u, P20_0, P20_0_TCPWM1_TR_ONE_CNT_IN88}, 1753 {4u, 90u, P20_0, P20_0_TCPWM1_TR_ONE_CNT_IN90}, 1754 {10u, 7u, P20_0, P20_0_TCPWM1_TR_ONE_CNT_IN1543}, 1755 {4u, 91u, P20_1, P20_1_TCPWM1_TR_ONE_CNT_IN91}, 1756 {4u, 147u, P20_1, P20_1_TCPWM1_TR_ONE_CNT_IN147}, 1757 {10u, 9u, P20_1, P20_1_TCPWM1_TR_ONE_CNT_IN1545}, 1758 {4u, 144u, P20_2, P20_2_TCPWM1_TR_ONE_CNT_IN144}, 1759 {4u, 148u, P20_2, P20_2_TCPWM1_TR_ONE_CNT_IN148}, 1760 {10u, 10u, P20_2, P20_2_TCPWM1_TR_ONE_CNT_IN1546}, 1761 {4u, 141u, P20_3, P20_3_TCPWM1_TR_ONE_CNT_IN141}, 1762 {4u, 145u, P20_3, P20_3_TCPWM1_TR_ONE_CNT_IN145}, 1763 {4u, 138u, P20_4, P20_4_TCPWM1_TR_ONE_CNT_IN138}, 1764 {4u, 142u, P20_4, P20_4_TCPWM1_TR_ONE_CNT_IN142}, 1765 {4u, 135u, P20_5, P20_5_TCPWM1_TR_ONE_CNT_IN135}, 1766 {4u, 139u, P20_5, P20_5_TCPWM1_TR_ONE_CNT_IN139}, 1767 {4u, 132u, P20_6, P20_6_TCPWM1_TR_ONE_CNT_IN132}, 1768 {4u, 136u, P20_6, P20_6_TCPWM1_TR_ONE_CNT_IN136}, 1769 {4u, 129u, P20_7, P20_7_TCPWM1_TR_ONE_CNT_IN129}, 1770 {4u, 133u, P20_7, P20_7_TCPWM1_TR_ONE_CNT_IN133}, 1771 {4u, 126u, P21_0, P21_0_TCPWM1_TR_ONE_CNT_IN126}, 1772 {4u, 130u, P21_0, P21_0_TCPWM1_TR_ONE_CNT_IN130}, 1773 {4u, 123u, P21_1, P21_1_TCPWM1_TR_ONE_CNT_IN123}, 1774 {4u, 127u, P21_1, P21_1_TCPWM1_TR_ONE_CNT_IN127}, 1775 {4u, 120u, P21_2, P21_2_TCPWM1_TR_ONE_CNT_IN120}, 1776 {4u, 124u, P21_2, P21_2_TCPWM1_TR_ONE_CNT_IN124}, 1777 {4u, 117u, P21_3, P21_3_TCPWM1_TR_ONE_CNT_IN117}, 1778 {4u, 121u, P21_3, P21_3_TCPWM1_TR_ONE_CNT_IN121}, 1779 {4u, 114u, P21_4, P21_4_TCPWM1_TR_ONE_CNT_IN114}, 1780 {4u, 118u, P21_4, P21_4_TCPWM1_TR_ONE_CNT_IN118}, 1781 {4u, 102u, P21_5, P21_5_TCPWM1_TR_ONE_CNT_IN102}, 1782 {4u, 106u, P21_5, P21_5_TCPWM1_TR_ONE_CNT_IN106}, 1783 {4u, 111u, P21_5, P21_5_TCPWM1_TR_ONE_CNT_IN111}, 1784 {4u, 115u, P21_5, P21_5_TCPWM1_TR_ONE_CNT_IN115}, 1785 {4u, 108u, P21_6, P21_6_TCPWM1_TR_ONE_CNT_IN108}, 1786 {4u, 112u, P21_6, P21_6_TCPWM1_TR_ONE_CNT_IN112}, 1787 {4u, 105u, P21_7, P21_7_TCPWM1_TR_ONE_CNT_IN105}, 1788 {4u, 109u, P21_7, P21_7_TCPWM1_TR_ONE_CNT_IN109}, 1789 {4u, 99u, P22_1, P22_1_TCPWM1_TR_ONE_CNT_IN99}, 1790 {4u, 103u, P22_1, P22_1_TCPWM1_TR_ONE_CNT_IN103}, 1791 {4u, 96u, P22_2, P22_2_TCPWM1_TR_ONE_CNT_IN96}, 1792 {4u, 100u, P22_2, P22_2_TCPWM1_TR_ONE_CNT_IN100}, 1793 {4u, 93u, P22_3, P22_3_TCPWM1_TR_ONE_CNT_IN93}, 1794 {4u, 97u, P22_3, P22_3_TCPWM1_TR_ONE_CNT_IN97}, 1795 {4u, 90u, P22_4, P22_4_TCPWM1_TR_ONE_CNT_IN90}, 1796 {4u, 94u, P22_4, P22_4_TCPWM1_TR_ONE_CNT_IN94}, 1797 {4u, 87u, P22_5, P22_5_TCPWM1_TR_ONE_CNT_IN87}, 1798 {4u, 91u, P22_5, P22_5_TCPWM1_TR_ONE_CNT_IN91}, 1799 {4u, 84u, P22_6, P22_6_TCPWM1_TR_ONE_CNT_IN84}, 1800 {4u, 88u, P22_6, P22_6_TCPWM1_TR_ONE_CNT_IN88}, 1801 {4u, 81u, P22_7, P22_7_TCPWM1_TR_ONE_CNT_IN81}, 1802 {4u, 85u, P22_7, P22_7_TCPWM1_TR_ONE_CNT_IN85}, 1803 {10u, 24u, P22_7, P22_7_TCPWM1_TR_ONE_CNT_IN1560}, 1804 {4u, 82u, P23_0, P23_0_TCPWM1_TR_ONE_CNT_IN82}, 1805 {7u, 24u, P23_0, P23_0_TCPWM1_TR_ONE_CNT_IN792}, 1806 {10u, 25u, P23_0, P23_0_TCPWM1_TR_ONE_CNT_IN1561}, 1807 {7u, 25u, P23_1, P23_1_TCPWM1_TR_ONE_CNT_IN793}, 1808 {7u, 27u, P23_1, P23_1_TCPWM1_TR_ONE_CNT_IN795}, 1809 {7u, 28u, P23_2, P23_2_TCPWM1_TR_ONE_CNT_IN796}, 1810 {7u, 30u, P23_2, P23_2_TCPWM1_TR_ONE_CNT_IN798}, 1811 {7u, 31u, P23_3, P23_3_TCPWM1_TR_ONE_CNT_IN799}, 1812 {7u, 33u, P23_3, P23_3_TCPWM1_TR_ONE_CNT_IN801}, 1813 {4u, 75u, P23_4, P23_4_TCPWM1_TR_ONE_CNT_IN75}, 1814 {7u, 34u, P23_4, P23_4_TCPWM1_TR_ONE_CNT_IN802}, 1815 {4u, 72u, P23_5, P23_5_TCPWM1_TR_ONE_CNT_IN72}, 1816 {4u, 76u, P23_5, P23_5_TCPWM1_TR_ONE_CNT_IN76}, 1817 {4u, 69u, P23_6, P23_6_TCPWM1_TR_ONE_CNT_IN69}, 1818 {4u, 73u, P23_6, P23_6_TCPWM1_TR_ONE_CNT_IN73}, 1819 {10u, 27u, P23_6, P23_6_TCPWM1_TR_ONE_CNT_IN1563}, 1820 {4u, 66u, P23_7, P23_7_TCPWM1_TR_ONE_CNT_IN66}, 1821 {4u, 70u, P23_7, P23_7_TCPWM1_TR_ONE_CNT_IN70}, 1822 {10u, 28u, P23_7, P23_7_TCPWM1_TR_ONE_CNT_IN1564}, 1823 }; 1824 1825 #endif 1826
