1 /***************************************************************************//** 2 * \file cyhal_xmc7100_272_bga.c 3 * 4 * \brief 5 * XMC7100 device GPIO HAL header for 272-BGA package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_XMC7100_272_BGA_H_) 31 #include "pin_packages/cyhal_xmc7100_272_bga.h" 32 33 /* Pin connections */ 34 /* Connections for: audioss_clk_i2s_if */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[3] = { 36 {0u, 0u, P12_1, P12_1_AUDIOSS0_CLK_I2S_IF}, 37 {1u, 0u, P13_4, P13_4_AUDIOSS1_CLK_I2S_IF}, 38 {2u, 0u, P15_0, P15_0_AUDIOSS2_CLK_I2S_IF}, 39 }; 40 41 /* Connections for: audioss_mclk */ 42 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_mclk[3] = { 43 {0u, 0u, P11_0, P11_0_AUDIOSS0_MCLK}, 44 {1u, 0u, P13_0, P13_0_AUDIOSS1_MCLK}, 45 {2u, 0u, P14_0, P14_0_AUDIOSS2_MCLK}, 46 }; 47 48 /* Connections for: audioss_rx_sck */ 49 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[3] = { 50 {0u, 0u, P12_2, P12_2_AUDIOSS0_RX_SCK}, 51 {1u, 0u, P13_5, P13_5_AUDIOSS1_RX_SCK}, 52 {2u, 0u, P15_1, P15_1_AUDIOSS2_RX_SCK}, 53 }; 54 55 /* Connections for: audioss_rx_sdi */ 56 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[3] = { 57 {0u, 0u, P12_4, P12_4_AUDIOSS0_RX_SDI}, 58 {1u, 0u, P13_7, P13_7_AUDIOSS1_RX_SDI}, 59 {2u, 0u, P15_3, P15_3_AUDIOSS2_RX_SDI}, 60 }; 61 62 /* Connections for: audioss_rx_ws */ 63 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[3] = { 64 {0u, 0u, P12_3, P12_3_AUDIOSS0_RX_WS}, 65 {1u, 0u, P13_6, P13_6_AUDIOSS1_RX_WS}, 66 {2u, 0u, P15_2, P15_2_AUDIOSS2_RX_WS}, 67 }; 68 69 /* Connections for: audioss_tx_sck */ 70 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3] = { 71 {0u, 0u, P11_1, P11_1_AUDIOSS0_TX_SCK}, 72 {1u, 0u, P13_1, P13_1_AUDIOSS1_TX_SCK}, 73 {2u, 0u, P14_1, P14_1_AUDIOSS2_TX_SCK}, 74 }; 75 76 /* Connections for: audioss_tx_sdo */ 77 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[3] = { 78 {0u, 0u, P12_0, P12_0_AUDIOSS0_TX_SDO}, 79 {1u, 0u, P13_3, P13_3_AUDIOSS1_TX_SDO}, 80 {2u, 0u, P14_5, P14_5_AUDIOSS2_TX_SDO}, 81 }; 82 83 /* Connections for: audioss_tx_ws */ 84 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[3] = { 85 {0u, 0u, P11_2, P11_2_AUDIOSS0_TX_WS}, 86 {1u, 0u, P13_2, P13_2_AUDIOSS1_TX_WS}, 87 {2u, 0u, P14_4, P14_4_AUDIOSS2_TX_WS}, 88 }; 89 90 /* Connections for: canfd_ttcan_rx */ 91 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[18] = { 92 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1}, 93 {0u, 0u, P2_1, P2_1_CANFD0_TTCAN_RX0}, 94 {0u, 3u, P3_1, P3_1_CANFD0_TTCAN_RX3}, 95 {1u, 2u, P3_7, P3_7_CANFD1_TTCAN_RX2}, 96 {0u, 1u, P4_4, P4_4_CANFD0_TTCAN_RX1}, 97 {0u, 2u, P6_3, P6_3_CANFD0_TTCAN_RX2}, 98 {0u, 0u, P8_1, P8_1_CANFD0_TTCAN_RX0}, 99 {0u, 2u, P12_1, P12_1_CANFD0_TTCAN_RX2}, 100 {1u, 1u, P12_5, P12_5_CANFD1_TTCAN_RX1}, 101 {1u, 0u, P14_1, P14_1_CANFD1_TTCAN_RX0}, 102 {1u, 3u, P15_1, P15_1_CANFD1_TTCAN_RX3}, 103 {1u, 1u, P17_1, P17_1_CANFD1_TTCAN_RX1}, 104 {1u, 2u, P18_7, P18_7_CANFD1_TTCAN_RX2}, 105 {1u, 3u, P19_1, P19_1_CANFD1_TTCAN_RX3}, 106 {1u, 2u, P20_4, P20_4_CANFD1_TTCAN_RX2}, 107 {1u, 1u, P22_1, P22_1_CANFD1_TTCAN_RX1}, 108 {1u, 0u, P23_1, P23_1_CANFD1_TTCAN_RX0}, 109 {1u, 3u, P30_3, P30_3_CANFD1_TTCAN_RX3}, 110 }; 111 112 /* Connections for: canfd_ttcan_tx */ 113 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[18] = { 114 {0u, 1u, P0_2, P0_2_CANFD0_TTCAN_TX1}, 115 {0u, 0u, P2_0, P2_0_CANFD0_TTCAN_TX0}, 116 {0u, 3u, P3_0, P3_0_CANFD0_TTCAN_TX3}, 117 {1u, 2u, P3_6, P3_6_CANFD1_TTCAN_TX2}, 118 {0u, 1u, P4_3, P4_3_CANFD0_TTCAN_TX1}, 119 {0u, 2u, P6_2, P6_2_CANFD0_TTCAN_TX2}, 120 {0u, 0u, P8_0, P8_0_CANFD0_TTCAN_TX0}, 121 {0u, 2u, P12_0, P12_0_CANFD0_TTCAN_TX2}, 122 {1u, 1u, P12_4, P12_4_CANFD1_TTCAN_TX1}, 123 {1u, 0u, P14_0, P14_0_CANFD1_TTCAN_TX0}, 124 {1u, 3u, P15_0, P15_0_CANFD1_TTCAN_TX3}, 125 {1u, 1u, P17_0, P17_0_CANFD1_TTCAN_TX1}, 126 {1u, 2u, P18_6, P18_6_CANFD1_TTCAN_TX2}, 127 {1u, 3u, P19_0, P19_0_CANFD1_TTCAN_TX3}, 128 {1u, 2u, P20_3, P20_3_CANFD1_TTCAN_TX2}, 129 {1u, 1u, P21_5, P21_5_CANFD1_TTCAN_TX1}, 130 {1u, 0u, P23_0, P23_0_CANFD1_TTCAN_TX0}, 131 {1u, 3u, P30_2, P30_2_CANFD1_TTCAN_TX3}, 132 }; 133 134 /* Connections for: cpuss_cal_sup_nz */ 135 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[3] = { 136 {0u, 0u, P6_3, P6_3_CPUSS_CAL_SUP_NZ}, 137 {0u, 0u, P21_7, P21_7_CPUSS_CAL_SUP_NZ}, 138 {0u, 0u, P23_7, P23_7_CPUSS_CAL_SUP_NZ}, 139 }; 140 141 /* Connections for: cpuss_clk_fm_pump */ 142 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 143 {0u, 0u, P21_6, P21_6_CPUSS_CLK_FM_PUMP}, 144 }; 145 146 /* Connections for: cpuss_fault_out */ 147 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[8] = { 148 {0u, 0u, P18_0, P18_0_CPUSS_FAULT_OUT0}, 149 {0u, 1u, P18_1, P18_1_CPUSS_FAULT_OUT1}, 150 {0u, 2u, P19_0, P19_0_CPUSS_FAULT_OUT2}, 151 {0u, 3u, P19_1, P19_1_CPUSS_FAULT_OUT3}, 152 {0u, 0u, P23_0, P23_0_CPUSS_FAULT_OUT0}, 153 {0u, 1u, P23_1, P23_1_CPUSS_FAULT_OUT1}, 154 {0u, 2u, P23_2, P23_2_CPUSS_FAULT_OUT2}, 155 {0u, 3u, P23_3, P23_3_CPUSS_FAULT_OUT3}, 156 }; 157 158 /* Connections for: cpuss_swj_swclk_tclk */ 159 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1] = { 160 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK}, 161 }; 162 163 /* Connections for: cpuss_swj_swdio_tms */ 164 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 165 {0u, 0u, P23_6, P23_6_CPUSS_SWJ_SWDIO_TMS}, 166 }; 167 168 /* Connections for: cpuss_swj_swdoe_tdi */ 169 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 170 {0u, 0u, P23_7, P23_7_CPUSS_SWJ_SWDOE_TDI}, 171 }; 172 173 /* Connections for: cpuss_swj_swo_tdo */ 174 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 175 {0u, 0u, P23_4, P23_4_CPUSS_SWJ_SWO_TDO}, 176 }; 177 178 /* Connections for: cpuss_swj_trstn */ 179 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1] = { 180 {0u, 0u, P2_0, P2_0_CPUSS_SWJ_TRSTN}, 181 }; 182 183 /* Connections for: cpuss_trace_clock */ 184 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2] = { 185 {0u, 0u, P18_3, P18_3_CPUSS_TRACE_CLOCK}, 186 {0u, 0u, P22_4, P22_4_CPUSS_TRACE_CLOCK}, 187 }; 188 189 /* Connections for: cpuss_trace_data */ 190 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8] = { 191 {0u, 0u, P18_4, P18_4_CPUSS_TRACE_DATA0}, 192 {0u, 1u, P18_5, P18_5_CPUSS_TRACE_DATA1}, 193 {0u, 2u, P18_6, P18_6_CPUSS_TRACE_DATA2}, 194 {0u, 3u, P18_7, P18_7_CPUSS_TRACE_DATA3}, 195 {0u, 0u, P21_5, P21_5_CPUSS_TRACE_DATA0}, 196 {0u, 1u, P22_1, P22_1_CPUSS_TRACE_DATA1}, 197 {0u, 2u, P22_2, P22_2_CPUSS_TRACE_DATA2}, 198 {0u, 3u, P22_3, P22_3_CPUSS_TRACE_DATA3}, 199 }; 200 201 /* Connections for: eth_eth_tsu_timer_cmp_val */ 202 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_eth_tsu_timer_cmp_val[1] = { 203 {0u, 0u, P2_3, P2_3_ETH0_ETH_TSU_TIMER_CMP_VAL}, 204 }; 205 206 /* Connections for: eth_mdc */ 207 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdc[1] = { 208 {0u, 0u, P3_1, P3_1_ETH0_MDC}, 209 }; 210 211 /* Connections for: eth_mdio */ 212 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdio[1] = { 213 {0u, 0u, P3_0, P3_0_ETH0_MDIO}, 214 }; 215 216 /* Connections for: eth_ref_clk */ 217 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_ref_clk[1] = { 218 {0u, 0u, P18_0, P18_0_ETH0_REF_CLK}, 219 }; 220 221 /* Connections for: eth_rx_clk */ 222 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_clk[1] = { 223 {0u, 0u, P23_3, P23_3_ETH0_RX_CLK}, 224 }; 225 226 /* Connections for: eth_rx_ctl */ 227 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_ctl[1] = { 228 {0u, 0u, P21_5, P21_5_ETH0_RX_CTL}, 229 }; 230 231 /* Connections for: eth_rx_er */ 232 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_er[1] = { 233 {0u, 0u, P2_2, P2_2_ETH0_RX_ER}, 234 }; 235 236 /* Connections for: eth_rxd */ 237 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rxd[4] = { 238 {0u, 0u, P19_0, P19_0_ETH0_RXD0}, 239 {0u, 1u, P19_1, P19_1_ETH0_RXD1}, 240 {0u, 2u, P19_2, P19_2_ETH0_RXD2}, 241 {0u, 3u, P19_3, P19_3_ETH0_RXD3}, 242 }; 243 244 /* Connections for: eth_tx_clk */ 245 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_clk[1] = { 246 {0u, 0u, P18_3, P18_3_ETH0_TX_CLK}, 247 }; 248 249 /* Connections for: eth_tx_ctl */ 250 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_ctl[1] = { 251 {0u, 0u, P18_1, P18_1_ETH0_TX_CTL}, 252 }; 253 254 /* Connections for: eth_tx_er */ 255 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_er[1] = { 256 {0u, 0u, P18_2, P18_2_ETH0_TX_ER}, 257 }; 258 259 /* Connections for: eth_txd */ 260 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_txd[4] = { 261 {0u, 0u, P18_4, P18_4_ETH0_TXD0}, 262 {0u, 1u, P18_5, P18_5_ETH0_TXD1}, 263 {0u, 2u, P18_6, P18_6_ETH0_TXD2}, 264 {0u, 3u, P18_7, P18_7_ETH0_TXD3}, 265 }; 266 267 /* Connections for: lin_lin_en */ 268 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[29] = { 269 {0u, 1u, P0_2, P0_2_LIN0_LIN_EN1}, 270 {0u, 0u, P2_2, P2_2_LIN0_LIN_EN0}, 271 {0u, 5u, P2_5, P2_5_LIN0_LIN_EN5}, 272 {0u, 11u, P3_7, P3_7_LIN0_LIN_EN11}, 273 {0u, 1u, P4_2, P4_2_LIN0_LIN_EN1}, 274 {0u, 7u, P5_2, P5_2_LIN0_LIN_EN7}, 275 {0u, 2u, P5_5, P5_5_LIN0_LIN_EN2}, 276 {0u, 9u, P6_0, P6_0_LIN0_LIN_EN9}, 277 {0u, 3u, P6_2, P6_2_LIN0_LIN_EN3}, 278 {0u, 4u, P6_5, P6_5_LIN0_LIN_EN4}, 279 {0u, 4u, P7_2, P7_2_LIN0_LIN_EN4}, 280 {0u, 10u, P7_7, P7_7_LIN0_LIN_EN10}, 281 {0u, 2u, P8_2, P8_2_LIN0_LIN_EN2}, 282 {0u, 12u, P9_3, P9_3_LIN0_LIN_EN12}, 283 {0u, 8u, P10_4, P10_4_LIN0_LIN_EN8}, 284 {0u, 13u, P10_7, P10_7_LIN0_LIN_EN13}, 285 {0u, 6u, P12_1, P12_1_LIN0_LIN_EN6}, 286 {0u, 3u, P13_2, P13_2_LIN0_LIN_EN3}, 287 {0u, 8u, P13_6, P13_6_LIN0_LIN_EN8}, 288 {0u, 6u, P14_4, P14_4_LIN0_LIN_EN6}, 289 {0u, 14u, P14_7, P14_7_LIN0_LIN_EN14}, 290 {0u, 11u, P16_2, P16_2_LIN0_LIN_EN11}, 291 {0u, 11u, P17_2, P17_2_LIN0_LIN_EN11}, 292 {0u, 15u, P17_7, P17_7_LIN0_LIN_EN15}, 293 {0u, 5u, P20_2, P20_2_LIN0_LIN_EN5}, 294 {0u, 0u, P21_7, P21_7_LIN0_LIN_EN0}, 295 {0u, 7u, P22_7, P22_7_LIN0_LIN_EN7}, 296 {0u, 9u, P23_7, P23_7_LIN0_LIN_EN9}, 297 {0u, 10u, P32_6, P32_6_LIN0_LIN_EN10}, 298 }; 299 300 /* Connections for: lin_lin_rx */ 301 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[40] = { 302 {0u, 1u, P0_0, P0_0_LIN0_LIN_RX1}, 303 {0u, 0u, P1_2, P1_2_LIN0_LIN_RX0}, 304 {0u, 8u, P1_4, P1_4_LIN0_LIN_RX8}, 305 {0u, 0u, P2_0, P2_0_LIN0_LIN_RX0}, 306 {0u, 5u, P2_3, P2_3_LIN0_LIN_RX5}, 307 {0u, 11u, P2_7, P2_7_LIN0_LIN_RX11}, 308 {0u, 1u, P3_4, P3_4_LIN0_LIN_RX1}, 309 {0u, 1u, P4_0, P4_0_LIN0_LIN_RX1}, 310 {0u, 15u, P4_4, P4_4_LIN0_LIN_RX15}, 311 {0u, 7u, P5_0, P5_0_LIN0_LIN_RX7}, 312 {0u, 10u, P5_2, P5_2_LIN0_LIN_RX10}, 313 {0u, 2u, P5_3, P5_3_LIN0_LIN_RX2}, 314 {0u, 9u, P5_4, P5_4_LIN0_LIN_RX9}, 315 {0u, 3u, P6_0, P6_0_LIN0_LIN_RX3}, 316 {0u, 4u, P6_3, P6_3_LIN0_LIN_RX4}, 317 {0u, 4u, P7_0, P7_0_LIN0_LIN_RX4}, 318 {0u, 10u, P7_5, P7_5_LIN0_LIN_RX10}, 319 {0u, 2u, P8_0, P8_0_LIN0_LIN_RX2}, 320 {0u, 12u, P9_1, P9_1_LIN0_LIN_RX12}, 321 {0u, 7u, P10_0, P10_0_LIN0_LIN_RX7}, 322 {0u, 8u, P10_2, P10_2_LIN0_LIN_RX8}, 323 {0u, 13u, P10_5, P10_5_LIN0_LIN_RX13}, 324 {0u, 6u, P12_2, P12_2_LIN0_LIN_RX6}, 325 {0u, 3u, P13_0, P13_0_LIN0_LIN_RX3}, 326 {0u, 2u, P13_3, P13_3_LIN0_LIN_RX2}, 327 {0u, 8u, P13_4, P13_4_LIN0_LIN_RX8}, 328 {0u, 6u, P14_2, P14_2_LIN0_LIN_RX6}, 329 {0u, 14u, P14_5, P14_5_LIN0_LIN_RX14}, 330 {0u, 11u, P16_0, P16_0_LIN0_LIN_RX11}, 331 {0u, 11u, P17_0, P17_0_LIN0_LIN_RX11}, 332 {0u, 15u, P17_5, P17_5_LIN0_LIN_RX15}, 333 {0u, 12u, P17_7, P17_7_LIN0_LIN_RX12}, 334 {0u, 5u, P20_0, P20_0_LIN0_LIN_RX5}, 335 {0u, 0u, P21_5, P21_5_LIN0_LIN_RX0}, 336 {0u, 13u, P21_6, P21_6_LIN0_LIN_RX13}, 337 {0u, 7u, P22_5, P22_5_LIN0_LIN_RX7}, 338 {0u, 14u, P22_7, P22_7_LIN0_LIN_RX14}, 339 {0u, 6u, P23_2, P23_2_LIN0_LIN_RX6}, 340 {0u, 9u, P23_5, P23_5_LIN0_LIN_RX9}, 341 {0u, 10u, P32_4, P32_4_LIN0_LIN_RX10}, 342 }; 343 344 /* Connections for: lin_lin_tx */ 345 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[39] = { 346 {0u, 1u, P0_1, P0_1_LIN0_LIN_TX1}, 347 {0u, 0u, P1_3, P1_3_LIN0_LIN_TX0}, 348 {0u, 0u, P2_1, P2_1_LIN0_LIN_TX0}, 349 {0u, 5u, P2_4, P2_4_LIN0_LIN_TX5}, 350 {0u, 1u, P3_5, P3_5_LIN0_LIN_TX1}, 351 {0u, 11u, P3_6, P3_6_LIN0_LIN_TX11}, 352 {0u, 1u, P4_1, P4_1_LIN0_LIN_TX1}, 353 {0u, 15u, P5_0, P5_0_LIN0_LIN_TX15}, 354 {0u, 7u, P5_1, P5_1_LIN0_LIN_TX7}, 355 {0u, 10u, P5_3, P5_3_LIN0_LIN_TX10}, 356 {0u, 2u, P5_4, P5_4_LIN0_LIN_TX2}, 357 {0u, 9u, P5_5, P5_5_LIN0_LIN_TX9}, 358 {0u, 3u, P6_1, P6_1_LIN0_LIN_TX3}, 359 {0u, 4u, P6_4, P6_4_LIN0_LIN_TX4}, 360 {0u, 4u, P7_1, P7_1_LIN0_LIN_TX4}, 361 {0u, 10u, P7_6, P7_6_LIN0_LIN_TX10}, 362 {0u, 2u, P8_1, P8_1_LIN0_LIN_TX2}, 363 {0u, 12u, P9_2, P9_2_LIN0_LIN_TX12}, 364 {0u, 7u, P10_1, P10_1_LIN0_LIN_TX7}, 365 {0u, 8u, P10_3, P10_3_LIN0_LIN_TX8}, 366 {0u, 13u, P10_6, P10_6_LIN0_LIN_TX13}, 367 {0u, 6u, P12_3, P12_3_LIN0_LIN_TX6}, 368 {0u, 3u, P13_1, P13_1_LIN0_LIN_TX3}, 369 {0u, 2u, P13_4, P13_4_LIN0_LIN_TX2}, 370 {0u, 8u, P13_5, P13_5_LIN0_LIN_TX8}, 371 {0u, 6u, P14_3, P14_3_LIN0_LIN_TX6}, 372 {0u, 14u, P14_6, P14_6_LIN0_LIN_TX14}, 373 {0u, 11u, P16_1, P16_1_LIN0_LIN_TX11}, 374 {0u, 11u, P17_1, P17_1_LIN0_LIN_TX11}, 375 {0u, 15u, P17_6, P17_6_LIN0_LIN_TX15}, 376 {0u, 12u, P18_0, P18_0_LIN0_LIN_TX12}, 377 {0u, 5u, P20_1, P20_1_LIN0_LIN_TX5}, 378 {0u, 0u, P21_6, P21_6_LIN0_LIN_TX0}, 379 {0u, 13u, P21_7, P21_7_LIN0_LIN_TX13}, 380 {0u, 7u, P22_6, P22_6_LIN0_LIN_TX7}, 381 {0u, 14u, P23_0, P23_0_LIN0_LIN_TX14}, 382 {0u, 6u, P23_3, P23_3_LIN0_LIN_TX6}, 383 {0u, 9u, P23_6, P23_6_LIN0_LIN_TX9}, 384 {0u, 10u, P32_5, P32_5_LIN0_LIN_TX10}, 385 }; 386 387 /* Connections for: pass_sar_ext_mux_en */ 388 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[3] = { 389 {0u, 0u, P4_3, P4_3_PASS0_SAR_EXT_MUX_EN0}, 390 {0u, 1u, P12_2, P12_2_PASS0_SAR_EXT_MUX_EN1}, 391 {0u, 2u, P13_3, P13_3_PASS0_SAR_EXT_MUX_EN2}, 392 }; 393 394 /* Connections for: pass_sar_ext_mux_sel */ 395 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[9] = { 396 {0u, 0u, P4_0, P4_0_PASS0_SAR_EXT_MUX_SEL0}, 397 {0u, 1u, P4_1, P4_1_PASS0_SAR_EXT_MUX_SEL1}, 398 {0u, 2u, P4_2, P4_2_PASS0_SAR_EXT_MUX_SEL2}, 399 {0u, 3u, P12_3, P12_3_PASS0_SAR_EXT_MUX_SEL3}, 400 {0u, 4u, P12_4, P12_4_PASS0_SAR_EXT_MUX_SEL4}, 401 {0u, 5u, P12_5, P12_5_PASS0_SAR_EXT_MUX_SEL5}, 402 {0u, 6u, P13_0, P13_0_PASS0_SAR_EXT_MUX_SEL6}, 403 {0u, 7u, P13_1, P13_1_PASS0_SAR_EXT_MUX_SEL7}, 404 {0u, 8u, P13_2, P13_2_PASS0_SAR_EXT_MUX_SEL8}, 405 }; 406 407 /* Connections for: pass_sarmux_pads */ 408 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[72] = { 409 {0u, 0u, P6_0, HSIOM_SEL_GPIO}, 410 {0u, 1u, P6_1, HSIOM_SEL_GPIO}, 411 {0u, 2u, P6_2, HSIOM_SEL_GPIO}, 412 {0u, 3u, P6_3, HSIOM_SEL_GPIO}, 413 {0u, 4u, P6_4, HSIOM_SEL_GPIO}, 414 {0u, 5u, P6_5, HSIOM_SEL_GPIO}, 415 {0u, 6u, P6_6, HSIOM_SEL_GPIO}, 416 {0u, 7u, P6_7, HSIOM_SEL_GPIO}, 417 {0u, 16u, P7_0, HSIOM_SEL_GPIO}, 418 {0u, 17u, P7_1, HSIOM_SEL_GPIO}, 419 {0u, 18u, P7_2, HSIOM_SEL_GPIO}, 420 {0u, 19u, P7_3, HSIOM_SEL_GPIO}, 421 {0u, 20u, P7_4, HSIOM_SEL_GPIO}, 422 {0u, 21u, P7_5, HSIOM_SEL_GPIO}, 423 {0u, 22u, P7_6, HSIOM_SEL_GPIO}, 424 {0u, 23u, P7_7, HSIOM_SEL_GPIO}, 425 {0u, 24u, P8_1, HSIOM_SEL_GPIO}, 426 {0u, 25u, P8_2, HSIOM_SEL_GPIO}, 427 {0u, 26u, P8_3, HSIOM_SEL_GPIO}, 428 {0u, 27u, P8_4, HSIOM_SEL_GPIO}, 429 {0u, 28u, P9_0, HSIOM_SEL_GPIO}, 430 {0u, 29u, P9_1, HSIOM_SEL_GPIO}, 431 {0u, 30u, P9_2, HSIOM_SEL_GPIO}, 432 {0u, 31u, P9_3, HSIOM_SEL_GPIO}, 433 {1u, 0u, P10_4, HSIOM_SEL_GPIO}, 434 {1u, 1u, P10_5, HSIOM_SEL_GPIO}, 435 {1u, 2u, P10_6, HSIOM_SEL_GPIO}, 436 {1u, 3u, P10_7, HSIOM_SEL_GPIO}, 437 {1u, 4u, P12_0, HSIOM_SEL_GPIO}, 438 {1u, 5u, P12_1, HSIOM_SEL_GPIO}, 439 {1u, 6u, P12_2, HSIOM_SEL_GPIO}, 440 {1u, 7u, P12_3, HSIOM_SEL_GPIO}, 441 {1u, 8u, P12_4, HSIOM_SEL_GPIO}, 442 {1u, 9u, P12_5, HSIOM_SEL_GPIO}, 443 {1u, 10u, P12_6, HSIOM_SEL_GPIO}, 444 {1u, 11u, P12_7, HSIOM_SEL_GPIO}, 445 {1u, 12u, P13_0, HSIOM_SEL_GPIO}, 446 {1u, 13u, P13_1, HSIOM_SEL_GPIO}, 447 {1u, 14u, P13_2, HSIOM_SEL_GPIO}, 448 {1u, 15u, P13_3, HSIOM_SEL_GPIO}, 449 {1u, 16u, P13_4, HSIOM_SEL_GPIO}, 450 {1u, 17u, P13_5, HSIOM_SEL_GPIO}, 451 {1u, 18u, P13_6, HSIOM_SEL_GPIO}, 452 {1u, 19u, P13_7, HSIOM_SEL_GPIO}, 453 {1u, 20u, P14_0, HSIOM_SEL_GPIO}, 454 {1u, 21u, P14_1, HSIOM_SEL_GPIO}, 455 {1u, 22u, P14_2, HSIOM_SEL_GPIO}, 456 {1u, 23u, P14_3, HSIOM_SEL_GPIO}, 457 {1u, 24u, P14_4, HSIOM_SEL_GPIO}, 458 {1u, 25u, P14_5, HSIOM_SEL_GPIO}, 459 {1u, 26u, P14_6, HSIOM_SEL_GPIO}, 460 {1u, 27u, P14_7, HSIOM_SEL_GPIO}, 461 {1u, 28u, P15_0, HSIOM_SEL_GPIO}, 462 {1u, 29u, P15_1, HSIOM_SEL_GPIO}, 463 {1u, 30u, P15_2, HSIOM_SEL_GPIO}, 464 {1u, 31u, P15_3, HSIOM_SEL_GPIO}, 465 {2u, 0u, P18_0, HSIOM_SEL_GPIO}, 466 {2u, 1u, P18_1, HSIOM_SEL_GPIO}, 467 {2u, 2u, P18_2, HSIOM_SEL_GPIO}, 468 {2u, 3u, P18_3, HSIOM_SEL_GPIO}, 469 {2u, 4u, P18_4, HSIOM_SEL_GPIO}, 470 {2u, 5u, P18_5, HSIOM_SEL_GPIO}, 471 {2u, 6u, P18_6, HSIOM_SEL_GPIO}, 472 {2u, 7u, P18_7, HSIOM_SEL_GPIO}, 473 {0u, 8u, P32_0, HSIOM_SEL_GPIO}, 474 {0u, 9u, P32_1, HSIOM_SEL_GPIO}, 475 {0u, 10u, P32_2, HSIOM_SEL_GPIO}, 476 {0u, 11u, P32_3, HSIOM_SEL_GPIO}, 477 {0u, 12u, P32_4, HSIOM_SEL_GPIO}, 478 {0u, 13u, P32_5, HSIOM_SEL_GPIO}, 479 {0u, 14u, P32_6, HSIOM_SEL_GPIO}, 480 {0u, 15u, P32_7, HSIOM_SEL_GPIO}, 481 }; 482 483 /* Connections for: peri_tr_io_input */ 484 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 485 to know the index of the input or output trigger line. Store that in the channel_num field 486 instead. */ 487 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[32] = { 488 {0u, 0u, P1_2, P1_2_PERI_TR_IO_INPUT0}, 489 {0u, 1u, P1_3, P1_3_PERI_TR_IO_INPUT1}, 490 {0u, 2u, P2_0, P2_0_PERI_TR_IO_INPUT2}, 491 {0u, 3u, P2_1, P2_1_PERI_TR_IO_INPUT3}, 492 {0u, 4u, P2_2, P2_2_PERI_TR_IO_INPUT4}, 493 {0u, 5u, P2_3, P2_3_PERI_TR_IO_INPUT5}, 494 {0u, 6u, P2_4, P2_4_PERI_TR_IO_INPUT6}, 495 {0u, 7u, P2_5, P2_5_PERI_TR_IO_INPUT7}, 496 {0u, 10u, P4_0, P4_0_PERI_TR_IO_INPUT10}, 497 {0u, 11u, P4_1, P4_1_PERI_TR_IO_INPUT11}, 498 {0u, 12u, P4_2, P4_2_PERI_TR_IO_INPUT12}, 499 {0u, 13u, P4_3, P4_3_PERI_TR_IO_INPUT13}, 500 {0u, 8u, P6_6, P6_6_PERI_TR_IO_INPUT8}, 501 {0u, 9u, P6_7, P6_7_PERI_TR_IO_INPUT9}, 502 {0u, 16u, P7_6, P7_6_PERI_TR_IO_INPUT16}, 503 {0u, 17u, P7_7, P7_7_PERI_TR_IO_INPUT17}, 504 {0u, 14u, P8_1, P8_1_PERI_TR_IO_INPUT14}, 505 {0u, 15u, P8_2, P8_2_PERI_TR_IO_INPUT15}, 506 {0u, 18u, P10_0, P10_0_PERI_TR_IO_INPUT18}, 507 {0u, 19u, P10_1, P10_1_PERI_TR_IO_INPUT19}, 508 {0u, 20u, P12_0, P12_0_PERI_TR_IO_INPUT20}, 509 {0u, 21u, P12_1, P12_1_PERI_TR_IO_INPUT21}, 510 {0u, 22u, P13_6, P13_6_PERI_TR_IO_INPUT22}, 511 {0u, 23u, P13_7, P13_7_PERI_TR_IO_INPUT23}, 512 {0u, 24u, P14_6, P14_6_PERI_TR_IO_INPUT24}, 513 {0u, 25u, P14_7, P14_7_PERI_TR_IO_INPUT25}, 514 {0u, 26u, P17_3, P17_3_PERI_TR_IO_INPUT26}, 515 {0u, 27u, P17_4, P17_4_PERI_TR_IO_INPUT27}, 516 {0u, 28u, P19_2, P19_2_PERI_TR_IO_INPUT28}, 517 {0u, 29u, P19_3, P19_3_PERI_TR_IO_INPUT29}, 518 {0u, 30u, P23_3, P23_3_PERI_TR_IO_INPUT30}, 519 {0u, 31u, P23_4, P23_4_PERI_TR_IO_INPUT31}, 520 }; 521 522 /* Connections for: peri_tr_io_output */ 523 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 524 to know the index of the input or output trigger line. Store that in the channel_num field 525 instead. */ 526 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6] = { 527 {0u, 0u, P3_0, P3_0_PERI_TR_IO_OUTPUT0}, 528 {0u, 1u, P3_1, P3_1_PERI_TR_IO_OUTPUT1}, 529 {0u, 0u, P8_3, P8_3_PERI_TR_IO_OUTPUT0}, 530 {0u, 1u, P8_4, P8_4_PERI_TR_IO_OUTPUT1}, 531 {0u, 1u, P21_2, P21_2_PERI_TR_IO_OUTPUT1}, 532 {0u, 0u, P23_4, P23_4_PERI_TR_IO_OUTPUT0}, 533 }; 534 535 /* Connections for: scb_i2c_scl */ 536 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[21] = { 537 {7u, 0u, P0_1, P0_1_SCB7_I2C_SCL}, 538 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 539 {0u, 0u, P1_0, P1_0_SCB0_I2C_SCL}, 540 {7u, 0u, P2_2, P2_2_SCB7_I2C_SCL}, 541 {6u, 0u, P3_2, P3_2_SCB6_I2C_SCL}, 542 {5u, 0u, P4_2, P4_2_SCB5_I2C_SCL}, 543 {4u, 0u, P6_2, P6_2_SCB4_I2C_SCL}, 544 {5u, 0u, P7_2, P7_2_SCB5_I2C_SCL}, 545 {4u, 0u, P10_2, P10_2_SCB4_I2C_SCL}, 546 {8u, 0u, P12_2, P12_2_SCB8_I2C_SCL}, 547 {3u, 0u, P13_2, P13_2_SCB3_I2C_SCL}, 548 {2u, 0u, P14_2, P14_2_SCB2_I2C_SCL}, 549 {9u, 0u, P15_2, P15_2_SCB9_I2C_SCL}, 550 {3u, 0u, P17_3, P17_3_SCB3_I2C_SCL}, 551 {1u, 0u, P18_2, P18_2_SCB1_I2C_SCL}, 552 {2u, 0u, P19_2, P19_2_SCB2_I2C_SCL}, 553 {1u, 0u, P20_5, P20_5_SCB1_I2C_SCL}, 554 {6u, 0u, P22_2, P22_2_SCB6_I2C_SCL}, 555 {7u, 0u, P23_2, P23_2_SCB7_I2C_SCL}, 556 {10u, 0u, P28_2, P28_2_SCB10_I2C_SCL}, 557 {10u, 0u, P32_2, P32_2_SCB10_I2C_SCL}, 558 }; 559 560 /* Connections for: scb_i2c_sda */ 561 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[21] = { 562 {7u, 0u, P0_0, P0_0_SCB7_I2C_SDA}, 563 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 564 {0u, 0u, P1_1, P1_1_SCB0_I2C_SDA}, 565 {7u, 0u, P2_1, P2_1_SCB7_I2C_SDA}, 566 {6u, 0u, P3_1, P3_1_SCB6_I2C_SDA}, 567 {5u, 0u, P4_1, P4_1_SCB5_I2C_SDA}, 568 {4u, 0u, P6_1, P6_1_SCB4_I2C_SDA}, 569 {5u, 0u, P7_1, P7_1_SCB5_I2C_SDA}, 570 {4u, 0u, P10_1, P10_1_SCB4_I2C_SDA}, 571 {8u, 0u, P12_1, P12_1_SCB8_I2C_SDA}, 572 {3u, 0u, P13_1, P13_1_SCB3_I2C_SDA}, 573 {2u, 0u, P14_1, P14_1_SCB2_I2C_SDA}, 574 {9u, 0u, P15_1, P15_1_SCB9_I2C_SDA}, 575 {3u, 0u, P17_2, P17_2_SCB3_I2C_SDA}, 576 {1u, 0u, P18_1, P18_1_SCB1_I2C_SDA}, 577 {2u, 0u, P19_1, P19_1_SCB2_I2C_SDA}, 578 {1u, 0u, P20_4, P20_4_SCB1_I2C_SDA}, 579 {6u, 0u, P22_1, P22_1_SCB6_I2C_SDA}, 580 {7u, 0u, P23_1, P23_1_SCB7_I2C_SDA}, 581 {10u, 0u, P28_1, P28_1_SCB10_I2C_SDA}, 582 {10u, 0u, P32_1, P32_1_SCB10_I2C_SDA}, 583 }; 584 585 /* Connections for: scb_spi_m_clk */ 586 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[24] = { 587 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 588 {4u, 0u, P1_0, P1_0_SCB4_SPI_CLK}, 589 {0u, 0u, P1_2, P1_2_SCB0_SPI_CLK}, 590 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 591 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 592 {5u, 0u, P4_2, P4_2_SCB5_SPI_CLK}, 593 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 594 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 595 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 596 {8u, 0u, P12_2, P12_2_SCB8_SPI_CLK}, 597 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 598 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 599 {9u, 0u, P15_2, P15_2_SCB9_SPI_CLK}, 600 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 601 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 602 {3u, 0u, P18_3, P18_3_SCB3_SPI_CLK}, 603 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 604 {1u, 0u, P20_5, P20_5_SCB1_SPI_CLK}, 605 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 606 {7u, 0u, P23_2, P23_2_SCB7_SPI_CLK}, 607 {2u, 0u, P23_6, P23_6_SCB2_SPI_CLK}, 608 {10u, 0u, P28_2, P28_2_SCB10_SPI_CLK}, 609 {9u, 0u, P30_0, P30_0_SCB9_SPI_CLK}, 610 {10u, 0u, P32_2, P32_2_SCB10_SPI_CLK}, 611 }; 612 613 /* Connections for: scb_spi_m_miso */ 614 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[23] = { 615 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 616 {4u, 0u, P0_2, P0_2_SCB4_SPI_MISO}, 617 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 618 {8u, 0u, P1_4, P1_4_SCB8_SPI_MISO}, 619 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 620 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 621 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 622 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 623 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 624 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 625 {8u, 0u, P12_0, P12_0_SCB8_SPI_MISO}, 626 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 627 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 628 {9u, 0u, P15_0, P15_0_SCB9_SPI_MISO}, 629 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 630 {3u, 0u, P18_1, P18_1_SCB3_SPI_MISO}, 631 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 632 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 633 {6u, 0u, P21_7, P21_7_SCB6_SPI_MISO}, 634 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 635 {2u, 0u, P23_4, P23_4_SCB2_SPI_MISO}, 636 {10u, 0u, P28_0, P28_0_SCB10_SPI_MISO}, 637 {10u, 0u, P32_0, P32_0_SCB10_SPI_MISO}, 638 }; 639 640 /* Connections for: scb_spi_m_mosi */ 641 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[22] = { 642 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 643 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI}, 644 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 645 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 646 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 647 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 648 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 649 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 650 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 651 {8u, 0u, P12_1, P12_1_SCB8_SPI_MOSI}, 652 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 653 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 654 {9u, 0u, P15_1, P15_1_SCB9_SPI_MOSI}, 655 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 656 {3u, 0u, P18_2, P18_2_SCB3_SPI_MOSI}, 657 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 658 {1u, 0u, P20_4, P20_4_SCB1_SPI_MOSI}, 659 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 660 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 661 {2u, 0u, P23_5, P23_5_SCB2_SPI_MOSI}, 662 {10u, 0u, P28_1, P28_1_SCB10_SPI_MOSI}, 663 {10u, 0u, P32_1, P32_1_SCB10_SPI_MOSI}, 664 }; 665 666 /* Connections for: scb_spi_m_select0 */ 667 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[25] = { 668 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 669 {4u, 0u, P1_1, P1_1_SCB4_SPI_SELECT0}, 670 {0u, 0u, P1_3, P1_3_SCB0_SPI_SELECT0}, 671 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 672 {8u, 0u, P2_6, P2_6_SCB8_SPI_SELECT0}, 673 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 674 {5u, 0u, P4_3, P4_3_SCB5_SPI_SELECT0}, 675 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 676 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 677 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 678 {8u, 0u, P12_3, P12_3_SCB8_SPI_SELECT0}, 679 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 680 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 681 {9u, 0u, P15_3, P15_3_SCB9_SPI_SELECT0}, 682 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 683 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 684 {3u, 0u, P18_4, P18_4_SCB3_SPI_SELECT0}, 685 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 686 {1u, 0u, P20_6, P20_6_SCB1_SPI_SELECT0}, 687 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 688 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 689 {2u, 0u, P23_7, P23_7_SCB2_SPI_SELECT0}, 690 {10u, 0u, P28_3, P28_3_SCB10_SPI_SELECT0}, 691 {9u, 0u, P30_1, P30_1_SCB9_SPI_SELECT0}, 692 {10u, 0u, P32_3, P32_3_SCB10_SPI_SELECT0}, 693 }; 694 695 /* Connections for: scb_spi_m_select1 */ 696 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[21] = { 697 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 698 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 699 {8u, 0u, P2_7, P2_7_SCB8_SPI_SELECT1}, 700 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 701 {5u, 0u, P4_4, P4_4_SCB5_SPI_SELECT1}, 702 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 703 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 704 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 705 {8u, 0u, P12_4, P12_4_SCB8_SPI_SELECT1}, 706 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 707 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 708 {9u, 0u, P16_0, P16_0_SCB9_SPI_SELECT1}, 709 {3u, 0u, P17_5, P17_5_SCB3_SPI_SELECT1}, 710 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 711 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 712 {1u, 0u, P20_7, P20_7_SCB1_SPI_SELECT1}, 713 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 714 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 715 {10u, 0u, P28_4, P28_4_SCB10_SPI_SELECT1}, 716 {9u, 0u, P30_2, P30_2_SCB9_SPI_SELECT1}, 717 {10u, 0u, P32_4, P32_4_SCB10_SPI_SELECT1}, 718 }; 719 720 /* Connections for: scb_spi_m_select2 */ 721 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[20] = { 722 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 723 {7u, 0u, P2_5, P2_5_SCB7_SPI_SELECT2}, 724 {6u, 0u, P3_5, P3_5_SCB6_SPI_SELECT2}, 725 {8u, 0u, P3_6, P3_6_SCB8_SPI_SELECT2}, 726 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 727 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 728 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 729 {4u, 0u, P10_5, P10_5_SCB4_SPI_SELECT2}, 730 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 731 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 732 {9u, 0u, P16_1, P16_1_SCB9_SPI_SELECT2}, 733 {3u, 0u, P17_6, P17_6_SCB3_SPI_SELECT2}, 734 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 735 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 736 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 737 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 738 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 739 {10u, 0u, P28_5, P28_5_SCB10_SPI_SELECT2}, 740 {9u, 0u, P30_3, P30_3_SCB9_SPI_SELECT2}, 741 {10u, 0u, P32_5, P32_5_SCB10_SPI_SELECT2}, 742 }; 743 744 /* Connections for: scb_spi_m_select3 */ 745 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8] = { 746 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 747 {9u, 0u, P5_1, P5_1_SCB9_SPI_SELECT3}, 748 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 749 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 750 {9u, 0u, P16_2, P16_2_SCB9_SPI_SELECT3}, 751 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 752 {10u, 0u, P28_6, P28_6_SCB10_SPI_SELECT3}, 753 {10u, 0u, P32_6, P32_6_SCB10_SPI_SELECT3}, 754 }; 755 756 /* Connections for: scb_spi_s_clk */ 757 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[24] = { 758 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 759 {4u, 0u, P1_0, P1_0_SCB4_SPI_CLK}, 760 {0u, 0u, P1_2, P1_2_SCB0_SPI_CLK}, 761 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 762 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 763 {5u, 0u, P4_2, P4_2_SCB5_SPI_CLK}, 764 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 765 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 766 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 767 {8u, 0u, P12_2, P12_2_SCB8_SPI_CLK}, 768 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 769 {2u, 0u, P14_2, P14_2_SCB2_SPI_CLK}, 770 {9u, 0u, P15_2, P15_2_SCB9_SPI_CLK}, 771 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 772 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 773 {3u, 0u, P18_3, P18_3_SCB3_SPI_CLK}, 774 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 775 {1u, 0u, P20_5, P20_5_SCB1_SPI_CLK}, 776 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 777 {7u, 0u, P23_2, P23_2_SCB7_SPI_CLK}, 778 {2u, 0u, P23_6, P23_6_SCB2_SPI_CLK}, 779 {10u, 0u, P28_2, P28_2_SCB10_SPI_CLK}, 780 {9u, 0u, P30_0, P30_0_SCB9_SPI_CLK}, 781 {10u, 0u, P32_2, P32_2_SCB10_SPI_CLK}, 782 }; 783 784 /* Connections for: scb_spi_s_miso */ 785 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[23] = { 786 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 787 {4u, 0u, P0_2, P0_2_SCB4_SPI_MISO}, 788 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 789 {8u, 0u, P1_4, P1_4_SCB8_SPI_MISO}, 790 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 791 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 792 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 793 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 794 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 795 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 796 {8u, 0u, P12_0, P12_0_SCB8_SPI_MISO}, 797 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 798 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 799 {9u, 0u, P15_0, P15_0_SCB9_SPI_MISO}, 800 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 801 {3u, 0u, P18_1, P18_1_SCB3_SPI_MISO}, 802 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 803 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 804 {6u, 0u, P21_7, P21_7_SCB6_SPI_MISO}, 805 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 806 {2u, 0u, P23_4, P23_4_SCB2_SPI_MISO}, 807 {10u, 0u, P28_0, P28_0_SCB10_SPI_MISO}, 808 {10u, 0u, P32_0, P32_0_SCB10_SPI_MISO}, 809 }; 810 811 /* Connections for: scb_spi_s_mosi */ 812 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[22] = { 813 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 814 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI}, 815 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 816 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 817 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 818 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 819 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 820 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 821 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 822 {8u, 0u, P12_1, P12_1_SCB8_SPI_MOSI}, 823 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 824 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 825 {9u, 0u, P15_1, P15_1_SCB9_SPI_MOSI}, 826 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 827 {3u, 0u, P18_2, P18_2_SCB3_SPI_MOSI}, 828 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 829 {1u, 0u, P20_4, P20_4_SCB1_SPI_MOSI}, 830 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 831 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 832 {2u, 0u, P23_5, P23_5_SCB2_SPI_MOSI}, 833 {10u, 0u, P28_1, P28_1_SCB10_SPI_MOSI}, 834 {10u, 0u, P32_1, P32_1_SCB10_SPI_MOSI}, 835 }; 836 837 /* Connections for: scb_spi_s_select0 */ 838 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[25] = { 839 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 840 {4u, 0u, P1_1, P1_1_SCB4_SPI_SELECT0}, 841 {0u, 0u, P1_3, P1_3_SCB0_SPI_SELECT0}, 842 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 843 {8u, 0u, P2_6, P2_6_SCB8_SPI_SELECT0}, 844 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 845 {5u, 0u, P4_3, P4_3_SCB5_SPI_SELECT0}, 846 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 847 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 848 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 849 {8u, 0u, P12_3, P12_3_SCB8_SPI_SELECT0}, 850 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 851 {2u, 0u, P14_3, P14_3_SCB2_SPI_SELECT0}, 852 {9u, 0u, P15_3, P15_3_SCB9_SPI_SELECT0}, 853 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 854 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 855 {3u, 0u, P18_4, P18_4_SCB3_SPI_SELECT0}, 856 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 857 {1u, 0u, P20_6, P20_6_SCB1_SPI_SELECT0}, 858 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 859 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 860 {2u, 0u, P23_7, P23_7_SCB2_SPI_SELECT0}, 861 {10u, 0u, P28_3, P28_3_SCB10_SPI_SELECT0}, 862 {9u, 0u, P30_1, P30_1_SCB9_SPI_SELECT0}, 863 {10u, 0u, P32_3, P32_3_SCB10_SPI_SELECT0}, 864 }; 865 866 /* Connections for: scb_spi_s_select1 */ 867 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[21] = { 868 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 869 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 870 {8u, 0u, P2_7, P2_7_SCB8_SPI_SELECT1}, 871 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 872 {5u, 0u, P4_4, P4_4_SCB5_SPI_SELECT1}, 873 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 874 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 875 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 876 {8u, 0u, P12_4, P12_4_SCB8_SPI_SELECT1}, 877 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 878 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 879 {9u, 0u, P16_0, P16_0_SCB9_SPI_SELECT1}, 880 {3u, 0u, P17_5, P17_5_SCB3_SPI_SELECT1}, 881 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 882 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 883 {1u, 0u, P20_7, P20_7_SCB1_SPI_SELECT1}, 884 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 885 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 886 {10u, 0u, P28_4, P28_4_SCB10_SPI_SELECT1}, 887 {9u, 0u, P30_2, P30_2_SCB9_SPI_SELECT1}, 888 {10u, 0u, P32_4, P32_4_SCB10_SPI_SELECT1}, 889 }; 890 891 /* Connections for: scb_spi_s_select2 */ 892 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[20] = { 893 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 894 {7u, 0u, P2_5, P2_5_SCB7_SPI_SELECT2}, 895 {6u, 0u, P3_5, P3_5_SCB6_SPI_SELECT2}, 896 {8u, 0u, P3_6, P3_6_SCB8_SPI_SELECT2}, 897 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 898 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 899 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 900 {4u, 0u, P10_5, P10_5_SCB4_SPI_SELECT2}, 901 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 902 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 903 {9u, 0u, P16_1, P16_1_SCB9_SPI_SELECT2}, 904 {3u, 0u, P17_6, P17_6_SCB3_SPI_SELECT2}, 905 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 906 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 907 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 908 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 909 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 910 {10u, 0u, P28_5, P28_5_SCB10_SPI_SELECT2}, 911 {9u, 0u, P30_3, P30_3_SCB9_SPI_SELECT2}, 912 {10u, 0u, P32_5, P32_5_SCB10_SPI_SELECT2}, 913 }; 914 915 /* Connections for: scb_spi_s_select3 */ 916 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8] = { 917 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 918 {9u, 0u, P5_1, P5_1_SCB9_SPI_SELECT3}, 919 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 920 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 921 {9u, 0u, P16_2, P16_2_SCB9_SPI_SELECT3}, 922 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 923 {10u, 0u, P28_6, P28_6_SCB10_SPI_SELECT3}, 924 {10u, 0u, P32_6, P32_6_SCB10_SPI_SELECT3}, 925 }; 926 927 /* Connections for: scb_uart_cts */ 928 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[21] = { 929 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS}, 930 {7u, 0u, P2_3, P2_3_SCB7_UART_CTS}, 931 {8u, 0u, P2_6, P2_6_SCB8_UART_CTS}, 932 {6u, 0u, P3_3, P3_3_SCB6_UART_CTS}, 933 {5u, 0u, P4_3, P4_3_SCB5_UART_CTS}, 934 {4u, 0u, P6_3, P6_3_SCB4_UART_CTS}, 935 {5u, 0u, P7_3, P7_3_SCB5_UART_CTS}, 936 {4u, 0u, P10_3, P10_3_SCB4_UART_CTS}, 937 {8u, 0u, P12_3, P12_3_SCB8_UART_CTS}, 938 {3u, 0u, P13_3, P13_3_SCB3_UART_CTS}, 939 {2u, 0u, P14_3, P14_3_SCB2_UART_CTS}, 940 {9u, 0u, P15_3, P15_3_SCB9_UART_CTS}, 941 {3u, 0u, P17_4, P17_4_SCB3_UART_CTS}, 942 {1u, 0u, P18_3, P18_3_SCB1_UART_CTS}, 943 {2u, 0u, P19_3, P19_3_SCB2_UART_CTS}, 944 {1u, 0u, P20_6, P20_6_SCB1_UART_CTS}, 945 {6u, 0u, P22_3, P22_3_SCB6_UART_CTS}, 946 {7u, 0u, P23_3, P23_3_SCB7_UART_CTS}, 947 {10u, 0u, P28_3, P28_3_SCB10_UART_CTS}, 948 {9u, 0u, P30_1, P30_1_SCB9_UART_CTS}, 949 {10u, 0u, P32_3, P32_3_SCB10_UART_CTS}, 950 }; 951 952 /* Connections for: scb_uart_rts */ 953 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[20] = { 954 {0u, 0u, P0_2, P0_2_SCB0_UART_RTS}, 955 {7u, 0u, P2_2, P2_2_SCB7_UART_RTS}, 956 {6u, 0u, P3_2, P3_2_SCB6_UART_RTS}, 957 {5u, 0u, P4_2, P4_2_SCB5_UART_RTS}, 958 {4u, 0u, P6_2, P6_2_SCB4_UART_RTS}, 959 {5u, 0u, P7_2, P7_2_SCB5_UART_RTS}, 960 {4u, 0u, P10_2, P10_2_SCB4_UART_RTS}, 961 {8u, 0u, P12_2, P12_2_SCB8_UART_RTS}, 962 {3u, 0u, P13_2, P13_2_SCB3_UART_RTS}, 963 {2u, 0u, P14_2, P14_2_SCB2_UART_RTS}, 964 {9u, 0u, P15_2, P15_2_SCB9_UART_RTS}, 965 {3u, 0u, P17_3, P17_3_SCB3_UART_RTS}, 966 {1u, 0u, P18_2, P18_2_SCB1_UART_RTS}, 967 {2u, 0u, P19_2, P19_2_SCB2_UART_RTS}, 968 {1u, 0u, P20_5, P20_5_SCB1_UART_RTS}, 969 {6u, 0u, P22_2, P22_2_SCB6_UART_RTS}, 970 {7u, 0u, P23_2, P23_2_SCB7_UART_RTS}, 971 {10u, 0u, P28_2, P28_2_SCB10_UART_RTS}, 972 {9u, 0u, P30_0, P30_0_SCB9_UART_RTS}, 973 {10u, 0u, P32_2, P32_2_SCB10_UART_RTS}, 974 }; 975 976 /* Connections for: scb_uart_rx */ 977 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[20] = { 978 {0u, 0u, P0_0, P0_0_SCB0_UART_RX}, 979 {8u, 0u, P1_4, P1_4_SCB8_UART_RX}, 980 {7u, 0u, P2_0, P2_0_SCB7_UART_RX}, 981 {6u, 0u, P3_0, P3_0_SCB6_UART_RX}, 982 {5u, 0u, P4_0, P4_0_SCB5_UART_RX}, 983 {4u, 0u, P6_0, P6_0_SCB4_UART_RX}, 984 {5u, 0u, P7_0, P7_0_SCB5_UART_RX}, 985 {4u, 0u, P10_0, P10_0_SCB4_UART_RX}, 986 {8u, 0u, P12_0, P12_0_SCB8_UART_RX}, 987 {3u, 0u, P13_0, P13_0_SCB3_UART_RX}, 988 {2u, 0u, P14_0, P14_0_SCB2_UART_RX}, 989 {9u, 0u, P15_0, P15_0_SCB9_UART_RX}, 990 {3u, 0u, P17_1, P17_1_SCB3_UART_RX}, 991 {1u, 0u, P18_0, P18_0_SCB1_UART_RX}, 992 {2u, 0u, P19_0, P19_0_SCB2_UART_RX}, 993 {1u, 0u, P20_3, P20_3_SCB1_UART_RX}, 994 {6u, 0u, P21_7, P21_7_SCB6_UART_RX}, 995 {7u, 0u, P23_0, P23_0_SCB7_UART_RX}, 996 {10u, 0u, P28_0, P28_0_SCB10_UART_RX}, 997 {10u, 0u, P32_0, P32_0_SCB10_UART_RX}, 998 }; 999 1000 /* Connections for: scb_uart_tx */ 1001 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[19] = { 1002 {0u, 0u, P0_1, P0_1_SCB0_UART_TX}, 1003 {7u, 0u, P2_1, P2_1_SCB7_UART_TX}, 1004 {6u, 0u, P3_1, P3_1_SCB6_UART_TX}, 1005 {5u, 0u, P4_1, P4_1_SCB5_UART_TX}, 1006 {4u, 0u, P6_1, P6_1_SCB4_UART_TX}, 1007 {5u, 0u, P7_1, P7_1_SCB5_UART_TX}, 1008 {4u, 0u, P10_1, P10_1_SCB4_UART_TX}, 1009 {8u, 0u, P12_1, P12_1_SCB8_UART_TX}, 1010 {3u, 0u, P13_1, P13_1_SCB3_UART_TX}, 1011 {2u, 0u, P14_1, P14_1_SCB2_UART_TX}, 1012 {9u, 0u, P15_1, P15_1_SCB9_UART_TX}, 1013 {3u, 0u, P17_2, P17_2_SCB3_UART_TX}, 1014 {1u, 0u, P18_1, P18_1_SCB1_UART_TX}, 1015 {2u, 0u, P19_1, P19_1_SCB2_UART_TX}, 1016 {1u, 0u, P20_4, P20_4_SCB1_UART_TX}, 1017 {6u, 0u, P22_1, P22_1_SCB6_UART_TX}, 1018 {7u, 0u, P23_1, P23_1_SCB7_UART_TX}, 1019 {10u, 0u, P28_1, P28_1_SCB10_UART_TX}, 1020 {10u, 0u, P32_1, P32_1_SCB10_UART_TX}, 1021 }; 1022 1023 /* Connections for: sdhc_card_cmd */ 1024 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2] = { 1025 {0u, 0u, P6_3, P6_3_SDHC0_CARD_CMD}, 1026 {0u, 0u, P24_3, P24_3_SDHC0_CARD_CMD}, 1027 }; 1028 1029 /* Connections for: sdhc_card_dat_3to0 */ 1030 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8] = { 1031 {0u, 0u, P7_1, P7_1_SDHC0_CARD_DAT_3TO00}, 1032 {0u, 1u, P7_2, P7_2_SDHC0_CARD_DAT_3TO01}, 1033 {0u, 2u, P7_3, P7_3_SDHC0_CARD_DAT_3TO02}, 1034 {0u, 3u, P7_4, P7_4_SDHC0_CARD_DAT_3TO03}, 1035 {0u, 0u, P25_0, P25_0_SDHC0_CARD_DAT_3TO00}, 1036 {0u, 1u, P25_1, P25_1_SDHC0_CARD_DAT_3TO01}, 1037 {0u, 2u, P25_2, P25_2_SDHC0_CARD_DAT_3TO02}, 1038 {0u, 3u, P25_3, P25_3_SDHC0_CARD_DAT_3TO03}, 1039 }; 1040 1041 /* Connections for: sdhc_card_dat_7to4 */ 1042 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[8] = { 1043 {0u, 0u, P7_5, P7_5_SDHC0_CARD_DAT_7TO40}, 1044 {0u, 1u, P8_0, P8_0_SDHC0_CARD_DAT_7TO41}, 1045 {0u, 2u, P8_1, P8_1_SDHC0_CARD_DAT_7TO42}, 1046 {0u, 3u, P8_2, P8_2_SDHC0_CARD_DAT_7TO43}, 1047 {0u, 0u, P25_4, P25_4_SDHC0_CARD_DAT_7TO40}, 1048 {0u, 1u, P25_5, P25_5_SDHC0_CARD_DAT_7TO41}, 1049 {0u, 2u, P25_6, P25_6_SDHC0_CARD_DAT_7TO42}, 1050 {0u, 3u, P25_7, P25_7_SDHC0_CARD_DAT_7TO43}, 1051 }; 1052 1053 /* Connections for: sdhc_card_detect_n */ 1054 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2] = { 1055 {0u, 0u, P6_5, P6_5_SDHC0_CARD_DETECT_N}, 1056 {0u, 0u, P24_0, P24_0_SDHC0_CARD_DETECT_N}, 1057 }; 1058 1059 /* Connections for: sdhc_card_if_pwr_en */ 1060 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2] = { 1061 {0u, 0u, P7_0, P7_0_SDHC0_CARD_IF_PWR_EN}, 1062 {0u, 0u, P24_4, P24_4_SDHC0_CARD_IF_PWR_EN}, 1063 }; 1064 1065 /* Connections for: sdhc_card_mech_write_prot */ 1066 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2] = { 1067 {0u, 0u, P6_2, P6_2_SDHC0_CARD_MECH_WRITE_PROT}, 1068 {0u, 0u, P24_1, P24_1_SDHC0_CARD_MECH_WRITE_PROT}, 1069 }; 1070 1071 /* Connections for: sdhc_clk_card */ 1072 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2] = { 1073 {0u, 0u, P6_4, P6_4_SDHC0_CLK_CARD}, 1074 {0u, 0u, P24_2, P24_2_SDHC0_CLK_CARD}, 1075 }; 1076 1077 /* Connections for: smif_spi_clk */ 1078 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[2] = { 1079 {0u, 0u, P6_3, P6_3_SMIF0_SPIHB_CLK}, 1080 {0u, 0u, P24_1, P24_1_SMIF0_SPIHB_CLK}, 1081 }; 1082 1083 /* Connections for: smif_spi_data0 */ 1084 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[2] = { 1085 {0u, 0u, P7_1, P7_1_SMIF0_SPIHB_DATA0}, 1086 {0u, 0u, P25_0, P25_0_SMIF0_SPIHB_DATA0}, 1087 }; 1088 1089 /* Connections for: smif_spi_data1 */ 1090 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[2] = { 1091 {0u, 0u, P7_2, P7_2_SMIF0_SPIHB_DATA1}, 1092 {0u, 0u, P25_1, P25_1_SMIF0_SPIHB_DATA1}, 1093 }; 1094 1095 /* Connections for: smif_spi_data2 */ 1096 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[2] = { 1097 {0u, 0u, P7_3, P7_3_SMIF0_SPIHB_DATA2}, 1098 {0u, 0u, P25_2, P25_2_SMIF0_SPIHB_DATA2}, 1099 }; 1100 1101 /* Connections for: smif_spi_data3 */ 1102 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[2] = { 1103 {0u, 0u, P7_4, P7_4_SMIF0_SPIHB_DATA3}, 1104 {0u, 0u, P25_3, P25_3_SMIF0_SPIHB_DATA3}, 1105 }; 1106 1107 /* Connections for: smif_spi_data4 */ 1108 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[2] = { 1109 {0u, 0u, P7_5, P7_5_SMIF0_SPIHB_DATA4}, 1110 {0u, 0u, P25_4, P25_4_SMIF0_SPIHB_DATA4}, 1111 }; 1112 1113 /* Connections for: smif_spi_data5 */ 1114 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[2] = { 1115 {0u, 0u, P8_0, P8_0_SMIF0_SPIHB_DATA5}, 1116 {0u, 0u, P25_5, P25_5_SMIF0_SPIHB_DATA5}, 1117 }; 1118 1119 /* Connections for: smif_spi_data6 */ 1120 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[2] = { 1121 {0u, 0u, P8_1, P8_1_SMIF0_SPIHB_DATA6}, 1122 {0u, 0u, P25_6, P25_6_SMIF0_SPIHB_DATA6}, 1123 }; 1124 1125 /* Connections for: smif_spi_data7 */ 1126 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[2] = { 1127 {0u, 0u, P8_2, P8_2_SMIF0_SPIHB_DATA7}, 1128 {0u, 0u, P25_7, P25_7_SMIF0_SPIHB_DATA7}, 1129 }; 1130 1131 /* Connections for: smif_spi_rwds */ 1132 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_rwds[2] = { 1133 {0u, 0u, P6_4, P6_4_SMIF0_SPIHB_RWDS}, 1134 {0u, 0u, P24_2, P24_2_SMIF0_SPIHB_RWDS}, 1135 }; 1136 1137 /* Connections for: smif_spi_select0 */ 1138 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[2] = { 1139 {0u, 0u, P6_5, P6_5_SMIF0_SPIHB_SELECT0}, 1140 {0u, 0u, P24_3, P24_3_SMIF0_SPIHB_SELECT0}, 1141 }; 1142 1143 /* Connections for: smif_spi_select1 */ 1144 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[2] = { 1145 {0u, 0u, P7_0, P7_0_SMIF0_SPIHB_SELECT1}, 1146 {0u, 0u, P24_4, P24_4_SMIF0_SPIHB_SELECT1}, 1147 }; 1148 1149 /* Connections for: tcpwm_line */ 1150 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[168] = { 1151 {0u, 18u, P0_0, P0_0_TCPWM0_LINE18}, 1152 {0u, 17u, P0_1, P0_1_TCPWM0_LINE17}, 1153 {0u, 14u, P0_2, P0_2_TCPWM0_LINE14}, 1154 {0u, 13u, P0_3, P0_3_TCPWM0_LINE13}, 1155 {0u, 12u, P1_0, P1_0_TCPWM0_LINE12}, 1156 {2u, 4u, P1_0, P1_0_TCPWM0_LINE516}, 1157 {0u, 11u, P1_1, P1_1_TCPWM0_LINE11}, 1158 {2u, 5u, P1_1, P1_1_TCPWM0_LINE517}, 1159 {0u, 10u, P1_2, P1_2_TCPWM0_LINE10}, 1160 {2u, 6u, P1_2, P1_2_TCPWM0_LINE518}, 1161 {0u, 8u, P1_3, P1_3_TCPWM0_LINE8}, 1162 {2u, 7u, P1_3, P1_3_TCPWM0_LINE519}, 1163 {0u, 7u, P2_0, P2_0_TCPWM0_LINE7}, 1164 {0u, 6u, P2_1, P2_1_TCPWM0_LINE6}, 1165 {0u, 5u, P2_2, P2_2_TCPWM0_LINE5}, 1166 {0u, 4u, P2_3, P2_3_TCPWM0_LINE4}, 1167 {0u, 3u, P2_4, P2_4_TCPWM0_LINE3}, 1168 {0u, 2u, P2_5, P2_5_TCPWM0_LINE2}, 1169 {0u, 1u, P3_0, P3_0_TCPWM0_LINE1}, 1170 {0u, 0u, P3_1, P3_1_TCPWM0_LINE0}, 1171 {1u, 3u, P3_2, P3_2_TCPWM0_LINE259}, 1172 {1u, 2u, P3_3, P3_3_TCPWM0_LINE258}, 1173 {1u, 1u, P3_4, P3_4_TCPWM0_LINE257}, 1174 {1u, 0u, P3_5, P3_5_TCPWM0_LINE256}, 1175 {0u, 4u, P4_0, P4_0_TCPWM0_LINE4}, 1176 {0u, 5u, P4_1, P4_1_TCPWM0_LINE5}, 1177 {0u, 6u, P4_2, P4_2_TCPWM0_LINE6}, 1178 {0u, 7u, P4_3, P4_3_TCPWM0_LINE7}, 1179 {0u, 8u, P4_4, P4_4_TCPWM0_LINE8}, 1180 {0u, 9u, P5_0, P5_0_TCPWM0_LINE9}, 1181 {0u, 10u, P5_1, P5_1_TCPWM0_LINE10}, 1182 {0u, 11u, P5_2, P5_2_TCPWM0_LINE11}, 1183 {0u, 12u, P5_3, P5_3_TCPWM0_LINE12}, 1184 {0u, 13u, P5_4, P5_4_TCPWM0_LINE13}, 1185 {0u, 14u, P5_5, P5_5_TCPWM0_LINE14}, 1186 {1u, 0u, P6_0, P6_0_TCPWM0_LINE256}, 1187 {0u, 0u, P6_1, P6_1_TCPWM0_LINE0}, 1188 {1u, 1u, P6_2, P6_2_TCPWM0_LINE257}, 1189 {0u, 1u, P6_3, P6_3_TCPWM0_LINE1}, 1190 {1u, 2u, P6_4, P6_4_TCPWM0_LINE258}, 1191 {0u, 2u, P6_5, P6_5_TCPWM0_LINE2}, 1192 {1u, 3u, P6_6, P6_6_TCPWM0_LINE259}, 1193 {0u, 3u, P6_7, P6_7_TCPWM0_LINE3}, 1194 {1u, 4u, P7_0, P7_0_TCPWM0_LINE260}, 1195 {0u, 15u, P7_1, P7_1_TCPWM0_LINE15}, 1196 {1u, 5u, P7_2, P7_2_TCPWM0_LINE261}, 1197 {0u, 16u, P7_3, P7_3_TCPWM0_LINE16}, 1198 {1u, 6u, P7_4, P7_4_TCPWM0_LINE262}, 1199 {0u, 17u, P7_5, P7_5_TCPWM0_LINE17}, 1200 {1u, 7u, P7_6, P7_6_TCPWM0_LINE263}, 1201 {0u, 18u, P7_7, P7_7_TCPWM0_LINE18}, 1202 {0u, 19u, P8_0, P8_0_TCPWM0_LINE19}, 1203 {0u, 20u, P8_1, P8_1_TCPWM0_LINE20}, 1204 {0u, 21u, P8_2, P8_2_TCPWM0_LINE21}, 1205 {0u, 22u, P8_3, P8_3_TCPWM0_LINE22}, 1206 {0u, 23u, P8_4, P8_4_TCPWM0_LINE23}, 1207 {0u, 24u, P9_0, P9_0_TCPWM0_LINE24}, 1208 {0u, 25u, P9_1, P9_1_TCPWM0_LINE25}, 1209 {0u, 26u, P9_2, P9_2_TCPWM0_LINE26}, 1210 {0u, 27u, P9_3, P9_3_TCPWM0_LINE27}, 1211 {0u, 28u, P10_0, P10_0_TCPWM0_LINE28}, 1212 {0u, 29u, P10_1, P10_1_TCPWM0_LINE29}, 1213 {0u, 30u, P10_2, P10_2_TCPWM0_LINE30}, 1214 {0u, 31u, P10_3, P10_3_TCPWM0_LINE31}, 1215 {0u, 32u, P10_4, P10_4_TCPWM0_LINE32}, 1216 {0u, 33u, P10_5, P10_5_TCPWM0_LINE33}, 1217 {0u, 34u, P10_6, P10_6_TCPWM0_LINE34}, 1218 {0u, 35u, P10_7, P10_7_TCPWM0_LINE35}, 1219 {0u, 61u, P11_0, P11_0_TCPWM0_LINE61}, 1220 {0u, 60u, P11_1, P11_1_TCPWM0_LINE60}, 1221 {0u, 59u, P11_2, P11_2_TCPWM0_LINE59}, 1222 {0u, 36u, P12_0, P12_0_TCPWM0_LINE36}, 1223 {0u, 37u, P12_1, P12_1_TCPWM0_LINE37}, 1224 {0u, 38u, P12_2, P12_2_TCPWM0_LINE38}, 1225 {0u, 39u, P12_3, P12_3_TCPWM0_LINE39}, 1226 {0u, 40u, P12_4, P12_4_TCPWM0_LINE40}, 1227 {0u, 41u, P12_5, P12_5_TCPWM0_LINE41}, 1228 {0u, 42u, P12_6, P12_6_TCPWM0_LINE42}, 1229 {0u, 43u, P12_7, P12_7_TCPWM0_LINE43}, 1230 {1u, 8u, P13_0, P13_0_TCPWM0_LINE264}, 1231 {0u, 44u, P13_1, P13_1_TCPWM0_LINE44}, 1232 {1u, 9u, P13_2, P13_2_TCPWM0_LINE265}, 1233 {0u, 45u, P13_3, P13_3_TCPWM0_LINE45}, 1234 {1u, 10u, P13_4, P13_4_TCPWM0_LINE266}, 1235 {2u, 4u, P13_4, P13_4_TCPWM0_LINE516}, 1236 {0u, 46u, P13_5, P13_5_TCPWM0_LINE46}, 1237 {1u, 11u, P13_6, P13_6_TCPWM0_LINE267}, 1238 {2u, 5u, P13_6, P13_6_TCPWM0_LINE517}, 1239 {0u, 47u, P13_7, P13_7_TCPWM0_LINE47}, 1240 {0u, 48u, P14_0, P14_0_TCPWM0_LINE48}, 1241 {2u, 6u, P14_0, P14_0_TCPWM0_LINE518}, 1242 {0u, 49u, P14_1, P14_1_TCPWM0_LINE49}, 1243 {0u, 50u, P14_2, P14_2_TCPWM0_LINE50}, 1244 {2u, 7u, P14_2, P14_2_TCPWM0_LINE519}, 1245 {0u, 51u, P14_3, P14_3_TCPWM0_LINE51}, 1246 {0u, 52u, P14_4, P14_4_TCPWM0_LINE52}, 1247 {0u, 53u, P14_5, P14_5_TCPWM0_LINE53}, 1248 {0u, 54u, P14_6, P14_6_TCPWM0_LINE54}, 1249 {0u, 55u, P14_7, P14_7_TCPWM0_LINE55}, 1250 {0u, 56u, P15_0, P15_0_TCPWM0_LINE56}, 1251 {0u, 57u, P15_1, P15_1_TCPWM0_LINE57}, 1252 {0u, 58u, P15_2, P15_2_TCPWM0_LINE58}, 1253 {0u, 59u, P15_3, P15_3_TCPWM0_LINE59}, 1254 {0u, 60u, P16_0, P16_0_TCPWM0_LINE60}, 1255 {2u, 0u, P16_0, P16_0_TCPWM0_LINE512}, 1256 {0u, 61u, P16_1, P16_1_TCPWM0_LINE61}, 1257 {0u, 62u, P16_2, P16_2_TCPWM0_LINE62}, 1258 {2u, 1u, P16_2, P16_2_TCPWM0_LINE513}, 1259 {0u, 62u, P16_3, P16_3_TCPWM0_LINE62}, 1260 {0u, 61u, P17_0, P17_0_TCPWM0_LINE61}, 1261 {0u, 60u, P17_1, P17_1_TCPWM0_LINE60}, 1262 {0u, 59u, P17_2, P17_2_TCPWM0_LINE59}, 1263 {0u, 58u, P17_3, P17_3_TCPWM0_LINE58}, 1264 {2u, 3u, P17_3, P17_3_TCPWM0_LINE515}, 1265 {0u, 57u, P17_4, P17_4_TCPWM0_LINE57}, 1266 {0u, 56u, P17_5, P17_5_TCPWM0_LINE56}, 1267 {2u, 2u, P17_5, P17_5_TCPWM0_LINE514}, 1268 {1u, 4u, P17_6, P17_6_TCPWM0_LINE260}, 1269 {1u, 5u, P17_7, P17_7_TCPWM0_LINE261}, 1270 {1u, 6u, P18_0, P18_0_TCPWM0_LINE262}, 1271 {2u, 0u, P18_0, P18_0_TCPWM0_LINE512}, 1272 {1u, 7u, P18_1, P18_1_TCPWM0_LINE263}, 1273 {0u, 55u, P18_2, P18_2_TCPWM0_LINE55}, 1274 {2u, 1u, P18_2, P18_2_TCPWM0_LINE513}, 1275 {0u, 54u, P18_3, P18_3_TCPWM0_LINE54}, 1276 {0u, 53u, P18_4, P18_4_TCPWM0_LINE53}, 1277 {2u, 2u, P18_4, P18_4_TCPWM0_LINE514}, 1278 {0u, 52u, P18_5, P18_5_TCPWM0_LINE52}, 1279 {0u, 51u, P18_6, P18_6_TCPWM0_LINE51}, 1280 {2u, 3u, P18_6, P18_6_TCPWM0_LINE515}, 1281 {0u, 50u, P18_7, P18_7_TCPWM0_LINE50}, 1282 {1u, 3u, P19_0, P19_0_TCPWM0_LINE259}, 1283 {0u, 26u, P19_1, P19_1_TCPWM0_LINE26}, 1284 {0u, 27u, P19_2, P19_2_TCPWM0_LINE27}, 1285 {0u, 28u, P19_3, P19_3_TCPWM0_LINE28}, 1286 {0u, 29u, P19_4, P19_4_TCPWM0_LINE29}, 1287 {0u, 30u, P20_0, P20_0_TCPWM0_LINE30}, 1288 {0u, 49u, P20_1, P20_1_TCPWM0_LINE49}, 1289 {0u, 48u, P20_2, P20_2_TCPWM0_LINE48}, 1290 {0u, 47u, P20_3, P20_3_TCPWM0_LINE47}, 1291 {0u, 46u, P20_4, P20_4_TCPWM0_LINE46}, 1292 {0u, 45u, P20_5, P20_5_TCPWM0_LINE45}, 1293 {0u, 44u, P20_6, P20_6_TCPWM0_LINE44}, 1294 {0u, 43u, P20_7, P20_7_TCPWM0_LINE43}, 1295 {0u, 42u, P21_0, P21_0_TCPWM0_LINE42}, 1296 {0u, 41u, P21_1, P21_1_TCPWM0_LINE41}, 1297 {0u, 40u, P21_2, P21_2_TCPWM0_LINE40}, 1298 {0u, 39u, P21_3, P21_3_TCPWM0_LINE39}, 1299 {0u, 38u, P21_4, P21_4_TCPWM0_LINE38}, 1300 {0u, 34u, P21_5, P21_5_TCPWM0_LINE34}, 1301 {0u, 37u, P21_5, P21_5_TCPWM0_LINE37}, 1302 {0u, 36u, P21_6, P21_6_TCPWM0_LINE36}, 1303 {0u, 35u, P21_7, P21_7_TCPWM0_LINE35}, 1304 {0u, 33u, P22_1, P22_1_TCPWM0_LINE33}, 1305 {0u, 32u, P22_2, P22_2_TCPWM0_LINE32}, 1306 {0u, 31u, P22_3, P22_3_TCPWM0_LINE31}, 1307 {0u, 30u, P22_4, P22_4_TCPWM0_LINE30}, 1308 {0u, 29u, P22_5, P22_5_TCPWM0_LINE29}, 1309 {0u, 28u, P22_6, P22_6_TCPWM0_LINE28}, 1310 {0u, 27u, P22_7, P22_7_TCPWM0_LINE27}, 1311 {1u, 8u, P23_0, P23_0_TCPWM0_LINE264}, 1312 {1u, 9u, P23_1, P23_1_TCPWM0_LINE265}, 1313 {1u, 10u, P23_2, P23_2_TCPWM0_LINE266}, 1314 {1u, 11u, P23_3, P23_3_TCPWM0_LINE267}, 1315 {0u, 25u, P23_4, P23_4_TCPWM0_LINE25}, 1316 {0u, 24u, P23_5, P23_5_TCPWM0_LINE24}, 1317 {0u, 23u, P23_6, P23_6_TCPWM0_LINE23}, 1318 {0u, 22u, P23_7, P23_7_TCPWM0_LINE22}, 1319 }; 1320 1321 /* Connections for: tcpwm_line_compl */ 1322 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[168] = { 1323 {0u, 22u, P0_0, P0_0_TCPWM0_LINE_COMPL22}, 1324 {0u, 18u, P0_1, P0_1_TCPWM0_LINE_COMPL18}, 1325 {0u, 17u, P0_2, P0_2_TCPWM0_LINE_COMPL17}, 1326 {0u, 14u, P0_3, P0_3_TCPWM0_LINE_COMPL14}, 1327 {0u, 13u, P1_0, P1_0_TCPWM0_LINE_COMPL13}, 1328 {0u, 12u, P1_1, P1_1_TCPWM0_LINE_COMPL12}, 1329 {0u, 11u, P1_2, P1_2_TCPWM0_LINE_COMPL11}, 1330 {0u, 10u, P1_3, P1_3_TCPWM0_LINE_COMPL10}, 1331 {0u, 8u, P2_0, P2_0_TCPWM0_LINE_COMPL8}, 1332 {0u, 7u, P2_1, P2_1_TCPWM0_LINE_COMPL7}, 1333 {0u, 6u, P2_2, P2_2_TCPWM0_LINE_COMPL6}, 1334 {0u, 5u, P2_3, P2_3_TCPWM0_LINE_COMPL5}, 1335 {0u, 4u, P2_4, P2_4_TCPWM0_LINE_COMPL4}, 1336 {2u, 4u, P2_4, P2_4_TCPWM0_LINE_COMPL516}, 1337 {0u, 3u, P2_5, P2_5_TCPWM0_LINE_COMPL3}, 1338 {2u, 5u, P2_5, P2_5_TCPWM0_LINE_COMPL517}, 1339 {0u, 2u, P3_0, P3_0_TCPWM0_LINE_COMPL2}, 1340 {2u, 6u, P3_0, P3_0_TCPWM0_LINE_COMPL518}, 1341 {0u, 1u, P3_1, P3_1_TCPWM0_LINE_COMPL1}, 1342 {2u, 7u, P3_1, P3_1_TCPWM0_LINE_COMPL519}, 1343 {0u, 0u, P3_2, P3_2_TCPWM0_LINE_COMPL0}, 1344 {1u, 3u, P3_3, P3_3_TCPWM0_LINE_COMPL259}, 1345 {1u, 2u, P3_4, P3_4_TCPWM0_LINE_COMPL258}, 1346 {1u, 1u, P3_5, P3_5_TCPWM0_LINE_COMPL257}, 1347 {1u, 0u, P4_0, P4_0_TCPWM0_LINE_COMPL256}, 1348 {0u, 4u, P4_1, P4_1_TCPWM0_LINE_COMPL4}, 1349 {0u, 5u, P4_2, P4_2_TCPWM0_LINE_COMPL5}, 1350 {0u, 6u, P4_3, P4_3_TCPWM0_LINE_COMPL6}, 1351 {0u, 7u, P4_4, P4_4_TCPWM0_LINE_COMPL7}, 1352 {0u, 8u, P5_0, P5_0_TCPWM0_LINE_COMPL8}, 1353 {0u, 9u, P5_1, P5_1_TCPWM0_LINE_COMPL9}, 1354 {0u, 10u, P5_2, P5_2_TCPWM0_LINE_COMPL10}, 1355 {0u, 11u, P5_3, P5_3_TCPWM0_LINE_COMPL11}, 1356 {0u, 12u, P5_4, P5_4_TCPWM0_LINE_COMPL12}, 1357 {0u, 13u, P5_5, P5_5_TCPWM0_LINE_COMPL13}, 1358 {0u, 14u, P6_0, P6_0_TCPWM0_LINE_COMPL14}, 1359 {1u, 0u, P6_1, P6_1_TCPWM0_LINE_COMPL256}, 1360 {0u, 0u, P6_2, P6_2_TCPWM0_LINE_COMPL0}, 1361 {1u, 1u, P6_3, P6_3_TCPWM0_LINE_COMPL257}, 1362 {0u, 1u, P6_4, P6_4_TCPWM0_LINE_COMPL1}, 1363 {1u, 2u, P6_5, P6_5_TCPWM0_LINE_COMPL258}, 1364 {0u, 2u, P6_6, P6_6_TCPWM0_LINE_COMPL2}, 1365 {1u, 3u, P6_7, P6_7_TCPWM0_LINE_COMPL259}, 1366 {0u, 3u, P7_0, P7_0_TCPWM0_LINE_COMPL3}, 1367 {1u, 4u, P7_1, P7_1_TCPWM0_LINE_COMPL260}, 1368 {0u, 15u, P7_2, P7_2_TCPWM0_LINE_COMPL15}, 1369 {1u, 5u, P7_3, P7_3_TCPWM0_LINE_COMPL261}, 1370 {0u, 16u, P7_4, P7_4_TCPWM0_LINE_COMPL16}, 1371 {1u, 6u, P7_5, P7_5_TCPWM0_LINE_COMPL262}, 1372 {0u, 17u, P7_6, P7_6_TCPWM0_LINE_COMPL17}, 1373 {1u, 7u, P7_7, P7_7_TCPWM0_LINE_COMPL263}, 1374 {0u, 18u, P8_0, P8_0_TCPWM0_LINE_COMPL18}, 1375 {0u, 19u, P8_1, P8_1_TCPWM0_LINE_COMPL19}, 1376 {0u, 20u, P8_2, P8_2_TCPWM0_LINE_COMPL20}, 1377 {0u, 21u, P8_3, P8_3_TCPWM0_LINE_COMPL21}, 1378 {0u, 22u, P8_4, P8_4_TCPWM0_LINE_COMPL22}, 1379 {0u, 23u, P9_0, P9_0_TCPWM0_LINE_COMPL23}, 1380 {0u, 24u, P9_1, P9_1_TCPWM0_LINE_COMPL24}, 1381 {0u, 25u, P9_2, P9_2_TCPWM0_LINE_COMPL25}, 1382 {0u, 26u, P9_3, P9_3_TCPWM0_LINE_COMPL26}, 1383 {0u, 27u, P10_0, P10_0_TCPWM0_LINE_COMPL27}, 1384 {0u, 28u, P10_1, P10_1_TCPWM0_LINE_COMPL28}, 1385 {0u, 29u, P10_2, P10_2_TCPWM0_LINE_COMPL29}, 1386 {0u, 30u, P10_3, P10_3_TCPWM0_LINE_COMPL30}, 1387 {0u, 31u, P10_4, P10_4_TCPWM0_LINE_COMPL31}, 1388 {0u, 32u, P10_5, P10_5_TCPWM0_LINE_COMPL32}, 1389 {0u, 33u, P10_6, P10_6_TCPWM0_LINE_COMPL33}, 1390 {0u, 34u, P10_7, P10_7_TCPWM0_LINE_COMPL34}, 1391 {0u, 62u, P11_0, P11_0_TCPWM0_LINE_COMPL62}, 1392 {0u, 61u, P11_1, P11_1_TCPWM0_LINE_COMPL61}, 1393 {0u, 60u, P11_2, P11_2_TCPWM0_LINE_COMPL60}, 1394 {0u, 35u, P12_0, P12_0_TCPWM0_LINE_COMPL35}, 1395 {0u, 36u, P12_1, P12_1_TCPWM0_LINE_COMPL36}, 1396 {0u, 37u, P12_2, P12_2_TCPWM0_LINE_COMPL37}, 1397 {0u, 38u, P12_3, P12_3_TCPWM0_LINE_COMPL38}, 1398 {0u, 39u, P12_4, P12_4_TCPWM0_LINE_COMPL39}, 1399 {0u, 40u, P12_5, P12_5_TCPWM0_LINE_COMPL40}, 1400 {0u, 41u, P12_6, P12_6_TCPWM0_LINE_COMPL41}, 1401 {0u, 42u, P12_7, P12_7_TCPWM0_LINE_COMPL42}, 1402 {0u, 43u, P13_0, P13_0_TCPWM0_LINE_COMPL43}, 1403 {1u, 8u, P13_1, P13_1_TCPWM0_LINE_COMPL264}, 1404 {0u, 44u, P13_2, P13_2_TCPWM0_LINE_COMPL44}, 1405 {1u, 9u, P13_3, P13_3_TCPWM0_LINE_COMPL265}, 1406 {0u, 45u, P13_4, P13_4_TCPWM0_LINE_COMPL45}, 1407 {1u, 10u, P13_5, P13_5_TCPWM0_LINE_COMPL266}, 1408 {2u, 4u, P13_5, P13_5_TCPWM0_LINE_COMPL516}, 1409 {0u, 46u, P13_6, P13_6_TCPWM0_LINE_COMPL46}, 1410 {1u, 11u, P13_7, P13_7_TCPWM0_LINE_COMPL267}, 1411 {2u, 5u, P13_7, P13_7_TCPWM0_LINE_COMPL517}, 1412 {0u, 47u, P14_0, P14_0_TCPWM0_LINE_COMPL47}, 1413 {0u, 48u, P14_1, P14_1_TCPWM0_LINE_COMPL48}, 1414 {2u, 6u, P14_1, P14_1_TCPWM0_LINE_COMPL518}, 1415 {0u, 49u, P14_2, P14_2_TCPWM0_LINE_COMPL49}, 1416 {0u, 50u, P14_3, P14_3_TCPWM0_LINE_COMPL50}, 1417 {2u, 7u, P14_3, P14_3_TCPWM0_LINE_COMPL519}, 1418 {0u, 51u, P14_4, P14_4_TCPWM0_LINE_COMPL51}, 1419 {0u, 52u, P14_5, P14_5_TCPWM0_LINE_COMPL52}, 1420 {0u, 53u, P14_6, P14_6_TCPWM0_LINE_COMPL53}, 1421 {0u, 54u, P14_7, P14_7_TCPWM0_LINE_COMPL54}, 1422 {0u, 55u, P15_0, P15_0_TCPWM0_LINE_COMPL55}, 1423 {0u, 56u, P15_1, P15_1_TCPWM0_LINE_COMPL56}, 1424 {0u, 57u, P15_2, P15_2_TCPWM0_LINE_COMPL57}, 1425 {0u, 58u, P15_3, P15_3_TCPWM0_LINE_COMPL58}, 1426 {0u, 59u, P16_0, P16_0_TCPWM0_LINE_COMPL59}, 1427 {0u, 60u, P16_1, P16_1_TCPWM0_LINE_COMPL60}, 1428 {2u, 0u, P16_1, P16_1_TCPWM0_LINE_COMPL512}, 1429 {0u, 61u, P16_2, P16_2_TCPWM0_LINE_COMPL61}, 1430 {0u, 62u, P16_3, P16_3_TCPWM0_LINE_COMPL62}, 1431 {2u, 1u, P16_3, P16_3_TCPWM0_LINE_COMPL513}, 1432 {0u, 62u, P17_0, P17_0_TCPWM0_LINE_COMPL62}, 1433 {0u, 61u, P17_1, P17_1_TCPWM0_LINE_COMPL61}, 1434 {0u, 60u, P17_2, P17_2_TCPWM0_LINE_COMPL60}, 1435 {0u, 59u, P17_3, P17_3_TCPWM0_LINE_COMPL59}, 1436 {0u, 58u, P17_4, P17_4_TCPWM0_LINE_COMPL58}, 1437 {2u, 3u, P17_4, P17_4_TCPWM0_LINE_COMPL515}, 1438 {0u, 57u, P17_5, P17_5_TCPWM0_LINE_COMPL57}, 1439 {0u, 56u, P17_6, P17_6_TCPWM0_LINE_COMPL56}, 1440 {2u, 2u, P17_6, P17_6_TCPWM0_LINE_COMPL514}, 1441 {1u, 4u, P17_7, P17_7_TCPWM0_LINE_COMPL260}, 1442 {1u, 5u, P18_0, P18_0_TCPWM0_LINE_COMPL261}, 1443 {1u, 6u, P18_1, P18_1_TCPWM0_LINE_COMPL262}, 1444 {2u, 0u, P18_1, P18_1_TCPWM0_LINE_COMPL512}, 1445 {1u, 7u, P18_2, P18_2_TCPWM0_LINE_COMPL263}, 1446 {0u, 55u, P18_3, P18_3_TCPWM0_LINE_COMPL55}, 1447 {2u, 1u, P18_3, P18_3_TCPWM0_LINE_COMPL513}, 1448 {0u, 54u, P18_4, P18_4_TCPWM0_LINE_COMPL54}, 1449 {0u, 53u, P18_5, P18_5_TCPWM0_LINE_COMPL53}, 1450 {2u, 2u, P18_5, P18_5_TCPWM0_LINE_COMPL514}, 1451 {0u, 52u, P18_6, P18_6_TCPWM0_LINE_COMPL52}, 1452 {0u, 51u, P18_7, P18_7_TCPWM0_LINE_COMPL51}, 1453 {2u, 3u, P18_7, P18_7_TCPWM0_LINE_COMPL515}, 1454 {0u, 50u, P19_0, P19_0_TCPWM0_LINE_COMPL50}, 1455 {1u, 3u, P19_1, P19_1_TCPWM0_LINE_COMPL259}, 1456 {0u, 26u, P19_2, P19_2_TCPWM0_LINE_COMPL26}, 1457 {0u, 27u, P19_3, P19_3_TCPWM0_LINE_COMPL27}, 1458 {0u, 28u, P19_4, P19_4_TCPWM0_LINE_COMPL28}, 1459 {0u, 29u, P20_0, P20_0_TCPWM0_LINE_COMPL29}, 1460 {0u, 30u, P20_1, P20_1_TCPWM0_LINE_COMPL30}, 1461 {0u, 49u, P20_2, P20_2_TCPWM0_LINE_COMPL49}, 1462 {0u, 48u, P20_3, P20_3_TCPWM0_LINE_COMPL48}, 1463 {0u, 47u, P20_4, P20_4_TCPWM0_LINE_COMPL47}, 1464 {0u, 46u, P20_5, P20_5_TCPWM0_LINE_COMPL46}, 1465 {0u, 45u, P20_6, P20_6_TCPWM0_LINE_COMPL45}, 1466 {0u, 44u, P20_7, P20_7_TCPWM0_LINE_COMPL44}, 1467 {0u, 43u, P21_0, P21_0_TCPWM0_LINE_COMPL43}, 1468 {0u, 42u, P21_1, P21_1_TCPWM0_LINE_COMPL42}, 1469 {0u, 41u, P21_2, P21_2_TCPWM0_LINE_COMPL41}, 1470 {0u, 40u, P21_3, P21_3_TCPWM0_LINE_COMPL40}, 1471 {0u, 39u, P21_4, P21_4_TCPWM0_LINE_COMPL39}, 1472 {0u, 35u, P21_5, P21_5_TCPWM0_LINE_COMPL35}, 1473 {0u, 38u, P21_5, P21_5_TCPWM0_LINE_COMPL38}, 1474 {0u, 37u, P21_6, P21_6_TCPWM0_LINE_COMPL37}, 1475 {0u, 36u, P21_7, P21_7_TCPWM0_LINE_COMPL36}, 1476 {0u, 34u, P22_1, P22_1_TCPWM0_LINE_COMPL34}, 1477 {0u, 33u, P22_2, P22_2_TCPWM0_LINE_COMPL33}, 1478 {0u, 32u, P22_3, P22_3_TCPWM0_LINE_COMPL32}, 1479 {0u, 31u, P22_4, P22_4_TCPWM0_LINE_COMPL31}, 1480 {0u, 30u, P22_5, P22_5_TCPWM0_LINE_COMPL30}, 1481 {0u, 29u, P22_6, P22_6_TCPWM0_LINE_COMPL29}, 1482 {0u, 28u, P22_7, P22_7_TCPWM0_LINE_COMPL28}, 1483 {0u, 27u, P23_0, P23_0_TCPWM0_LINE_COMPL27}, 1484 {1u, 8u, P23_1, P23_1_TCPWM0_LINE_COMPL264}, 1485 {1u, 9u, P23_2, P23_2_TCPWM0_LINE_COMPL265}, 1486 {1u, 10u, P23_3, P23_3_TCPWM0_LINE_COMPL266}, 1487 {1u, 11u, P23_4, P23_4_TCPWM0_LINE_COMPL267}, 1488 {0u, 25u, P23_5, P23_5_TCPWM0_LINE_COMPL25}, 1489 {0u, 24u, P23_6, P23_6_TCPWM0_LINE_COMPL24}, 1490 {0u, 23u, P23_7, P23_7_TCPWM0_LINE_COMPL23}, 1491 }; 1492 1493 /* Connections for: tcpwm_tr_one_cnt_in */ 1494 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[328] = { 1495 {0u, 54u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN54}, 1496 {0u, 67u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN67}, 1497 {0u, 51u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN51}, 1498 {0u, 55u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN55}, 1499 {0u, 42u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN42}, 1500 {0u, 52u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN52}, 1501 {0u, 39u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN39}, 1502 {0u, 43u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN43}, 1503 {0u, 36u, P1_0, P1_0_TCPWM0_TR_ONE_CNT_IN36}, 1504 {0u, 40u, P1_0, P1_0_TCPWM0_TR_ONE_CNT_IN40}, 1505 {0u, 33u, P1_1, P1_1_TCPWM0_TR_ONE_CNT_IN33}, 1506 {0u, 37u, P1_1, P1_1_TCPWM0_TR_ONE_CNT_IN37}, 1507 {0u, 30u, P1_2, P1_2_TCPWM0_TR_ONE_CNT_IN30}, 1508 {0u, 34u, P1_2, P1_2_TCPWM0_TR_ONE_CNT_IN34}, 1509 {0u, 24u, P1_3, P1_3_TCPWM0_TR_ONE_CNT_IN24}, 1510 {0u, 31u, P1_3, P1_3_TCPWM0_TR_ONE_CNT_IN31}, 1511 {0u, 21u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN21}, 1512 {0u, 25u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN25}, 1513 {6u, 12u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN1548}, 1514 {0u, 18u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN18}, 1515 {0u, 22u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN22}, 1516 {6u, 15u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN1551}, 1517 {0u, 15u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN15}, 1518 {0u, 19u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN19}, 1519 {6u, 18u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN1554}, 1520 {0u, 12u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN12}, 1521 {0u, 16u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN16}, 1522 {6u, 21u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN1557}, 1523 {0u, 9u, P2_4, P2_4_TCPWM0_TR_ONE_CNT_IN9}, 1524 {0u, 13u, P2_4, P2_4_TCPWM0_TR_ONE_CNT_IN13}, 1525 {0u, 6u, P2_5, P2_5_TCPWM0_TR_ONE_CNT_IN6}, 1526 {0u, 10u, P2_5, P2_5_TCPWM0_TR_ONE_CNT_IN10}, 1527 {0u, 3u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN3}, 1528 {0u, 7u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN7}, 1529 {0u, 0u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN0}, 1530 {0u, 4u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN4}, 1531 {0u, 1u, P3_2, P3_2_TCPWM0_TR_ONE_CNT_IN1}, 1532 {3u, 9u, P3_2, P3_2_TCPWM0_TR_ONE_CNT_IN777}, 1533 {6u, 13u, P3_2, P3_2_TCPWM0_TR_ONE_CNT_IN1549}, 1534 {3u, 6u, P3_3, P3_3_TCPWM0_TR_ONE_CNT_IN774}, 1535 {3u, 10u, P3_3, P3_3_TCPWM0_TR_ONE_CNT_IN778}, 1536 {6u, 16u, P3_3, P3_3_TCPWM0_TR_ONE_CNT_IN1552}, 1537 {3u, 3u, P3_4, P3_4_TCPWM0_TR_ONE_CNT_IN771}, 1538 {3u, 7u, P3_4, P3_4_TCPWM0_TR_ONE_CNT_IN775}, 1539 {6u, 19u, P3_4, P3_4_TCPWM0_TR_ONE_CNT_IN1555}, 1540 {3u, 0u, P3_5, P3_5_TCPWM0_TR_ONE_CNT_IN768}, 1541 {3u, 4u, P3_5, P3_5_TCPWM0_TR_ONE_CNT_IN772}, 1542 {6u, 22u, P3_5, P3_5_TCPWM0_TR_ONE_CNT_IN1558}, 1543 {0u, 12u, P4_0, P4_0_TCPWM0_TR_ONE_CNT_IN12}, 1544 {3u, 1u, P4_0, P4_0_TCPWM0_TR_ONE_CNT_IN769}, 1545 {0u, 13u, P4_1, P4_1_TCPWM0_TR_ONE_CNT_IN13}, 1546 {0u, 15u, P4_1, P4_1_TCPWM0_TR_ONE_CNT_IN15}, 1547 {0u, 16u, P4_2, P4_2_TCPWM0_TR_ONE_CNT_IN16}, 1548 {0u, 18u, P4_2, P4_2_TCPWM0_TR_ONE_CNT_IN18}, 1549 {0u, 19u, P4_3, P4_3_TCPWM0_TR_ONE_CNT_IN19}, 1550 {0u, 21u, P4_3, P4_3_TCPWM0_TR_ONE_CNT_IN21}, 1551 {0u, 22u, P4_4, P4_4_TCPWM0_TR_ONE_CNT_IN22}, 1552 {0u, 24u, P4_4, P4_4_TCPWM0_TR_ONE_CNT_IN24}, 1553 {0u, 25u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN25}, 1554 {0u, 27u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN27}, 1555 {0u, 28u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN28}, 1556 {0u, 30u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN30}, 1557 {0u, 31u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN31}, 1558 {0u, 33u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN33}, 1559 {0u, 34u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN34}, 1560 {0u, 36u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN36}, 1561 {0u, 37u, P5_4, P5_4_TCPWM0_TR_ONE_CNT_IN37}, 1562 {0u, 39u, P5_4, P5_4_TCPWM0_TR_ONE_CNT_IN39}, 1563 {0u, 40u, P5_5, P5_5_TCPWM0_TR_ONE_CNT_IN40}, 1564 {0u, 42u, P5_5, P5_5_TCPWM0_TR_ONE_CNT_IN42}, 1565 {0u, 43u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN43}, 1566 {3u, 0u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN768}, 1567 {0u, 0u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN0}, 1568 {3u, 1u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN769}, 1569 {0u, 1u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN1}, 1570 {3u, 3u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN771}, 1571 {0u, 3u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN3}, 1572 {3u, 4u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN772}, 1573 {0u, 4u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN4}, 1574 {3u, 6u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN774}, 1575 {0u, 6u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN6}, 1576 {3u, 7u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN775}, 1577 {0u, 7u, P6_6, P6_6_TCPWM0_TR_ONE_CNT_IN7}, 1578 {3u, 9u, P6_6, P6_6_TCPWM0_TR_ONE_CNT_IN777}, 1579 {0u, 9u, P6_7, P6_7_TCPWM0_TR_ONE_CNT_IN9}, 1580 {3u, 10u, P6_7, P6_7_TCPWM0_TR_ONE_CNT_IN778}, 1581 {0u, 10u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN10}, 1582 {3u, 12u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN780}, 1583 {0u, 45u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN45}, 1584 {3u, 13u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN781}, 1585 {0u, 46u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN46}, 1586 {3u, 15u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN783}, 1587 {0u, 48u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN48}, 1588 {3u, 16u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN784}, 1589 {0u, 49u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN49}, 1590 {3u, 18u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN786}, 1591 {0u, 51u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN51}, 1592 {3u, 19u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN787}, 1593 {0u, 52u, P7_6, P7_6_TCPWM0_TR_ONE_CNT_IN52}, 1594 {3u, 21u, P7_6, P7_6_TCPWM0_TR_ONE_CNT_IN789}, 1595 {0u, 54u, P7_7, P7_7_TCPWM0_TR_ONE_CNT_IN54}, 1596 {3u, 22u, P7_7, P7_7_TCPWM0_TR_ONE_CNT_IN790}, 1597 {0u, 55u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN55}, 1598 {0u, 57u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN57}, 1599 {0u, 58u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN58}, 1600 {0u, 60u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN60}, 1601 {0u, 61u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN61}, 1602 {0u, 63u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN63}, 1603 {0u, 64u, P8_3, P8_3_TCPWM0_TR_ONE_CNT_IN64}, 1604 {0u, 66u, P8_3, P8_3_TCPWM0_TR_ONE_CNT_IN66}, 1605 {0u, 67u, P8_4, P8_4_TCPWM0_TR_ONE_CNT_IN67}, 1606 {0u, 69u, P8_4, P8_4_TCPWM0_TR_ONE_CNT_IN69}, 1607 {0u, 70u, P9_0, P9_0_TCPWM0_TR_ONE_CNT_IN70}, 1608 {0u, 72u, P9_0, P9_0_TCPWM0_TR_ONE_CNT_IN72}, 1609 {0u, 73u, P9_1, P9_1_TCPWM0_TR_ONE_CNT_IN73}, 1610 {0u, 75u, P9_1, P9_1_TCPWM0_TR_ONE_CNT_IN75}, 1611 {0u, 76u, P9_2, P9_2_TCPWM0_TR_ONE_CNT_IN76}, 1612 {0u, 78u, P9_2, P9_2_TCPWM0_TR_ONE_CNT_IN78}, 1613 {0u, 79u, P9_3, P9_3_TCPWM0_TR_ONE_CNT_IN79}, 1614 {0u, 81u, P9_3, P9_3_TCPWM0_TR_ONE_CNT_IN81}, 1615 {0u, 82u, P10_0, P10_0_TCPWM0_TR_ONE_CNT_IN82}, 1616 {0u, 84u, P10_0, P10_0_TCPWM0_TR_ONE_CNT_IN84}, 1617 {0u, 85u, P10_1, P10_1_TCPWM0_TR_ONE_CNT_IN85}, 1618 {0u, 87u, P10_1, P10_1_TCPWM0_TR_ONE_CNT_IN87}, 1619 {0u, 88u, P10_2, P10_2_TCPWM0_TR_ONE_CNT_IN88}, 1620 {0u, 90u, P10_2, P10_2_TCPWM0_TR_ONE_CNT_IN90}, 1621 {0u, 91u, P10_3, P10_3_TCPWM0_TR_ONE_CNT_IN91}, 1622 {0u, 93u, P10_3, P10_3_TCPWM0_TR_ONE_CNT_IN93}, 1623 {0u, 94u, P10_4, P10_4_TCPWM0_TR_ONE_CNT_IN94}, 1624 {0u, 96u, P10_4, P10_4_TCPWM0_TR_ONE_CNT_IN96}, 1625 {0u, 97u, P10_5, P10_5_TCPWM0_TR_ONE_CNT_IN97}, 1626 {0u, 99u, P10_5, P10_5_TCPWM0_TR_ONE_CNT_IN99}, 1627 {0u, 100u, P10_6, P10_6_TCPWM0_TR_ONE_CNT_IN100}, 1628 {0u, 102u, P10_6, P10_6_TCPWM0_TR_ONE_CNT_IN102}, 1629 {0u, 103u, P10_7, P10_7_TCPWM0_TR_ONE_CNT_IN103}, 1630 {0u, 105u, P10_7, P10_7_TCPWM0_TR_ONE_CNT_IN105}, 1631 {0u, 183u, P11_0, P11_0_TCPWM0_TR_ONE_CNT_IN183}, 1632 {0u, 187u, P11_0, P11_0_TCPWM0_TR_ONE_CNT_IN187}, 1633 {0u, 180u, P11_1, P11_1_TCPWM0_TR_ONE_CNT_IN180}, 1634 {0u, 184u, P11_1, P11_1_TCPWM0_TR_ONE_CNT_IN184}, 1635 {0u, 177u, P11_2, P11_2_TCPWM0_TR_ONE_CNT_IN177}, 1636 {0u, 181u, P11_2, P11_2_TCPWM0_TR_ONE_CNT_IN181}, 1637 {0u, 106u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN106}, 1638 {0u, 108u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN108}, 1639 {0u, 109u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN109}, 1640 {0u, 111u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN111}, 1641 {0u, 112u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN112}, 1642 {0u, 114u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN114}, 1643 {0u, 115u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN115}, 1644 {0u, 117u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN117}, 1645 {0u, 118u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN118}, 1646 {0u, 120u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN120}, 1647 {0u, 121u, P12_5, P12_5_TCPWM0_TR_ONE_CNT_IN121}, 1648 {0u, 123u, P12_5, P12_5_TCPWM0_TR_ONE_CNT_IN123}, 1649 {0u, 124u, P12_6, P12_6_TCPWM0_TR_ONE_CNT_IN124}, 1650 {0u, 126u, P12_6, P12_6_TCPWM0_TR_ONE_CNT_IN126}, 1651 {0u, 127u, P12_7, P12_7_TCPWM0_TR_ONE_CNT_IN127}, 1652 {0u, 129u, P12_7, P12_7_TCPWM0_TR_ONE_CNT_IN129}, 1653 {0u, 130u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN130}, 1654 {3u, 24u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN792}, 1655 {0u, 132u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN132}, 1656 {3u, 25u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN793}, 1657 {0u, 133u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN133}, 1658 {3u, 27u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN795}, 1659 {0u, 135u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN135}, 1660 {3u, 28u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN796}, 1661 {0u, 136u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN136}, 1662 {3u, 30u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN798}, 1663 {0u, 138u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN138}, 1664 {3u, 31u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN799}, 1665 {0u, 139u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN139}, 1666 {3u, 33u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN801}, 1667 {0u, 141u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN141}, 1668 {3u, 34u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN802}, 1669 {0u, 142u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN142}, 1670 {0u, 144u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN144}, 1671 {0u, 145u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN145}, 1672 {0u, 147u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN147}, 1673 {0u, 148u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN148}, 1674 {0u, 150u, P14_2, P14_2_TCPWM0_TR_ONE_CNT_IN150}, 1675 {0u, 151u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN151}, 1676 {0u, 153u, P14_3, P14_3_TCPWM0_TR_ONE_CNT_IN153}, 1677 {0u, 154u, P14_4, P14_4_TCPWM0_TR_ONE_CNT_IN154}, 1678 {0u, 156u, P14_4, P14_4_TCPWM0_TR_ONE_CNT_IN156}, 1679 {6u, 12u, P14_4, P14_4_TCPWM0_TR_ONE_CNT_IN1548}, 1680 {0u, 157u, P14_5, P14_5_TCPWM0_TR_ONE_CNT_IN157}, 1681 {0u, 159u, P14_5, P14_5_TCPWM0_TR_ONE_CNT_IN159}, 1682 {6u, 13u, P14_5, P14_5_TCPWM0_TR_ONE_CNT_IN1549}, 1683 {0u, 160u, P14_6, P14_6_TCPWM0_TR_ONE_CNT_IN160}, 1684 {0u, 162u, P14_6, P14_6_TCPWM0_TR_ONE_CNT_IN162}, 1685 {6u, 15u, P14_6, P14_6_TCPWM0_TR_ONE_CNT_IN1551}, 1686 {0u, 163u, P14_7, P14_7_TCPWM0_TR_ONE_CNT_IN163}, 1687 {0u, 165u, P14_7, P14_7_TCPWM0_TR_ONE_CNT_IN165}, 1688 {6u, 16u, P14_7, P14_7_TCPWM0_TR_ONE_CNT_IN1552}, 1689 {0u, 166u, P15_0, P15_0_TCPWM0_TR_ONE_CNT_IN166}, 1690 {0u, 168u, P15_0, P15_0_TCPWM0_TR_ONE_CNT_IN168}, 1691 {6u, 18u, P15_0, P15_0_TCPWM0_TR_ONE_CNT_IN1554}, 1692 {0u, 169u, P15_1, P15_1_TCPWM0_TR_ONE_CNT_IN169}, 1693 {0u, 171u, P15_1, P15_1_TCPWM0_TR_ONE_CNT_IN171}, 1694 {6u, 19u, P15_1, P15_1_TCPWM0_TR_ONE_CNT_IN1555}, 1695 {0u, 172u, P15_2, P15_2_TCPWM0_TR_ONE_CNT_IN172}, 1696 {0u, 174u, P15_2, P15_2_TCPWM0_TR_ONE_CNT_IN174}, 1697 {6u, 21u, P15_2, P15_2_TCPWM0_TR_ONE_CNT_IN1557}, 1698 {0u, 175u, P15_3, P15_3_TCPWM0_TR_ONE_CNT_IN175}, 1699 {0u, 177u, P15_3, P15_3_TCPWM0_TR_ONE_CNT_IN177}, 1700 {6u, 22u, P15_3, P15_3_TCPWM0_TR_ONE_CNT_IN1558}, 1701 {0u, 178u, P16_0, P16_0_TCPWM0_TR_ONE_CNT_IN178}, 1702 {0u, 180u, P16_0, P16_0_TCPWM0_TR_ONE_CNT_IN180}, 1703 {0u, 181u, P16_1, P16_1_TCPWM0_TR_ONE_CNT_IN181}, 1704 {0u, 183u, P16_1, P16_1_TCPWM0_TR_ONE_CNT_IN183}, 1705 {0u, 184u, P16_2, P16_2_TCPWM0_TR_ONE_CNT_IN184}, 1706 {0u, 186u, P16_2, P16_2_TCPWM0_TR_ONE_CNT_IN186}, 1707 {0u, 186u, P16_3, P16_3_TCPWM0_TR_ONE_CNT_IN186}, 1708 {0u, 187u, P16_3, P16_3_TCPWM0_TR_ONE_CNT_IN187}, 1709 {0u, 183u, P17_0, P17_0_TCPWM0_TR_ONE_CNT_IN183}, 1710 {0u, 187u, P17_0, P17_0_TCPWM0_TR_ONE_CNT_IN187}, 1711 {0u, 180u, P17_1, P17_1_TCPWM0_TR_ONE_CNT_IN180}, 1712 {0u, 184u, P17_1, P17_1_TCPWM0_TR_ONE_CNT_IN184}, 1713 {0u, 177u, P17_2, P17_2_TCPWM0_TR_ONE_CNT_IN177}, 1714 {0u, 181u, P17_2, P17_2_TCPWM0_TR_ONE_CNT_IN181}, 1715 {0u, 174u, P17_3, P17_3_TCPWM0_TR_ONE_CNT_IN174}, 1716 {0u, 178u, P17_3, P17_3_TCPWM0_TR_ONE_CNT_IN178}, 1717 {0u, 171u, P17_4, P17_4_TCPWM0_TR_ONE_CNT_IN171}, 1718 {0u, 175u, P17_4, P17_4_TCPWM0_TR_ONE_CNT_IN175}, 1719 {0u, 168u, P17_5, P17_5_TCPWM0_TR_ONE_CNT_IN168}, 1720 {0u, 172u, P17_5, P17_5_TCPWM0_TR_ONE_CNT_IN172}, 1721 {0u, 169u, P17_6, P17_6_TCPWM0_TR_ONE_CNT_IN169}, 1722 {3u, 12u, P17_6, P17_6_TCPWM0_TR_ONE_CNT_IN780}, 1723 {3u, 13u, P17_7, P17_7_TCPWM0_TR_ONE_CNT_IN781}, 1724 {3u, 15u, P17_7, P17_7_TCPWM0_TR_ONE_CNT_IN783}, 1725 {3u, 16u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN784}, 1726 {3u, 18u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN786}, 1727 {3u, 19u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN787}, 1728 {3u, 21u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN789}, 1729 {0u, 165u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN165}, 1730 {3u, 22u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN790}, 1731 {0u, 162u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN162}, 1732 {0u, 166u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN166}, 1733 {0u, 159u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN159}, 1734 {0u, 163u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN163}, 1735 {0u, 156u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN156}, 1736 {0u, 160u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN160}, 1737 {0u, 153u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN153}, 1738 {0u, 157u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN157}, 1739 {0u, 150u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN150}, 1740 {0u, 154u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN154}, 1741 {0u, 151u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN151}, 1742 {3u, 9u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN777}, 1743 {6u, 0u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN1536}, 1744 {0u, 78u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN78}, 1745 {3u, 10u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN778}, 1746 {6u, 1u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN1537}, 1747 {0u, 79u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN79}, 1748 {0u, 81u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN81}, 1749 {6u, 3u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN1539}, 1750 {0u, 82u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN82}, 1751 {0u, 84u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN84}, 1752 {6u, 4u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN1540}, 1753 {0u, 85u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN85}, 1754 {0u, 87u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN87}, 1755 {6u, 6u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN1542}, 1756 {0u, 88u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN88}, 1757 {0u, 90u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN90}, 1758 {6u, 7u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN1543}, 1759 {0u, 91u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN91}, 1760 {0u, 147u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN147}, 1761 {6u, 9u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN1545}, 1762 {0u, 144u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN144}, 1763 {0u, 148u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN148}, 1764 {6u, 10u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN1546}, 1765 {0u, 141u, P20_3, P20_3_TCPWM0_TR_ONE_CNT_IN141}, 1766 {0u, 145u, P20_3, P20_3_TCPWM0_TR_ONE_CNT_IN145}, 1767 {0u, 138u, P20_4, P20_4_TCPWM0_TR_ONE_CNT_IN138}, 1768 {0u, 142u, P20_4, P20_4_TCPWM0_TR_ONE_CNT_IN142}, 1769 {0u, 135u, P20_5, P20_5_TCPWM0_TR_ONE_CNT_IN135}, 1770 {0u, 139u, P20_5, P20_5_TCPWM0_TR_ONE_CNT_IN139}, 1771 {0u, 132u, P20_6, P20_6_TCPWM0_TR_ONE_CNT_IN132}, 1772 {0u, 136u, P20_6, P20_6_TCPWM0_TR_ONE_CNT_IN136}, 1773 {0u, 129u, P20_7, P20_7_TCPWM0_TR_ONE_CNT_IN129}, 1774 {0u, 133u, P20_7, P20_7_TCPWM0_TR_ONE_CNT_IN133}, 1775 {0u, 126u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN126}, 1776 {0u, 130u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN130}, 1777 {0u, 123u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN123}, 1778 {0u, 127u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN127}, 1779 {0u, 120u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN120}, 1780 {0u, 124u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN124}, 1781 {0u, 117u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN117}, 1782 {0u, 121u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN121}, 1783 {0u, 114u, P21_4, P21_4_TCPWM0_TR_ONE_CNT_IN114}, 1784 {0u, 118u, P21_4, P21_4_TCPWM0_TR_ONE_CNT_IN118}, 1785 {0u, 102u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN102}, 1786 {0u, 106u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN106}, 1787 {0u, 111u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN111}, 1788 {0u, 115u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN115}, 1789 {0u, 108u, P21_6, P21_6_TCPWM0_TR_ONE_CNT_IN108}, 1790 {0u, 112u, P21_6, P21_6_TCPWM0_TR_ONE_CNT_IN112}, 1791 {0u, 105u, P21_7, P21_7_TCPWM0_TR_ONE_CNT_IN105}, 1792 {0u, 109u, P21_7, P21_7_TCPWM0_TR_ONE_CNT_IN109}, 1793 {0u, 99u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN99}, 1794 {0u, 103u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN103}, 1795 {0u, 96u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN96}, 1796 {0u, 100u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN100}, 1797 {0u, 93u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN93}, 1798 {0u, 97u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN97}, 1799 {0u, 90u, P22_4, P22_4_TCPWM0_TR_ONE_CNT_IN90}, 1800 {0u, 94u, P22_4, P22_4_TCPWM0_TR_ONE_CNT_IN94}, 1801 {0u, 87u, P22_5, P22_5_TCPWM0_TR_ONE_CNT_IN87}, 1802 {0u, 91u, P22_5, P22_5_TCPWM0_TR_ONE_CNT_IN91}, 1803 {0u, 84u, P22_6, P22_6_TCPWM0_TR_ONE_CNT_IN84}, 1804 {0u, 88u, P22_6, P22_6_TCPWM0_TR_ONE_CNT_IN88}, 1805 {0u, 81u, P22_7, P22_7_TCPWM0_TR_ONE_CNT_IN81}, 1806 {0u, 85u, P22_7, P22_7_TCPWM0_TR_ONE_CNT_IN85}, 1807 {0u, 82u, P23_0, P23_0_TCPWM0_TR_ONE_CNT_IN82}, 1808 {3u, 24u, P23_0, P23_0_TCPWM0_TR_ONE_CNT_IN792}, 1809 {3u, 25u, P23_1, P23_1_TCPWM0_TR_ONE_CNT_IN793}, 1810 {3u, 27u, P23_1, P23_1_TCPWM0_TR_ONE_CNT_IN795}, 1811 {3u, 28u, P23_2, P23_2_TCPWM0_TR_ONE_CNT_IN796}, 1812 {3u, 30u, P23_2, P23_2_TCPWM0_TR_ONE_CNT_IN798}, 1813 {3u, 31u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN799}, 1814 {3u, 33u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN801}, 1815 {0u, 75u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN75}, 1816 {3u, 34u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN802}, 1817 {0u, 72u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN72}, 1818 {0u, 76u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN76}, 1819 {0u, 69u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN69}, 1820 {0u, 73u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN73}, 1821 {0u, 66u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN66}, 1822 {0u, 70u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN70}, 1823 }; 1824 1825 #endif 1826
