1 /***************************************************************************//** 2 * \file cyhal_xmc7100_144_teqfp.c 3 * 4 * \brief 5 * XMC7100 device GPIO HAL header for 144-TEQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_XMC7100_144_TEQFP_H_) 31 #include "pin_packages/cyhal_xmc7100_144_teqfp.h" 32 33 /* Pin connections */ 34 /* Connections for: audioss_clk_i2s_if */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[3] = { 36 {0u, 0u, P12_1, P12_1_AUDIOSS0_CLK_I2S_IF}, 37 {1u, 0u, P13_4, P13_4_AUDIOSS1_CLK_I2S_IF}, 38 {2u, 0u, P15_0, P15_0_AUDIOSS2_CLK_I2S_IF}, 39 }; 40 41 /* Connections for: audioss_mclk */ 42 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_mclk[3] = { 43 {0u, 0u, P11_0, P11_0_AUDIOSS0_MCLK}, 44 {1u, 0u, P13_0, P13_0_AUDIOSS1_MCLK}, 45 {2u, 0u, P14_0, P14_0_AUDIOSS2_MCLK}, 46 }; 47 48 /* Connections for: audioss_rx_sck */ 49 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[3] = { 50 {0u, 0u, P12_2, P12_2_AUDIOSS0_RX_SCK}, 51 {1u, 0u, P13_5, P13_5_AUDIOSS1_RX_SCK}, 52 {2u, 0u, P15_1, P15_1_AUDIOSS2_RX_SCK}, 53 }; 54 55 /* Connections for: audioss_rx_sdi */ 56 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[3] = { 57 {0u, 0u, P12_4, P12_4_AUDIOSS0_RX_SDI}, 58 {1u, 0u, P13_7, P13_7_AUDIOSS1_RX_SDI}, 59 {2u, 0u, P15_3, P15_3_AUDIOSS2_RX_SDI}, 60 }; 61 62 /* Connections for: audioss_rx_ws */ 63 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[3] = { 64 {0u, 0u, P12_3, P12_3_AUDIOSS0_RX_WS}, 65 {1u, 0u, P13_6, P13_6_AUDIOSS1_RX_WS}, 66 {2u, 0u, P15_2, P15_2_AUDIOSS2_RX_WS}, 67 }; 68 69 /* Connections for: audioss_tx_sck */ 70 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3] = { 71 {0u, 0u, P11_1, P11_1_AUDIOSS0_TX_SCK}, 72 {1u, 0u, P13_1, P13_1_AUDIOSS1_TX_SCK}, 73 {2u, 0u, P14_1, P14_1_AUDIOSS2_TX_SCK}, 74 }; 75 76 /* Connections for: audioss_tx_sdo */ 77 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[3] = { 78 {0u, 0u, P12_0, P12_0_AUDIOSS0_TX_SDO}, 79 {1u, 0u, P13_3, P13_3_AUDIOSS1_TX_SDO}, 80 {2u, 0u, P14_5, P14_5_AUDIOSS2_TX_SDO}, 81 }; 82 83 /* Connections for: audioss_tx_ws */ 84 const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[3] = { 85 {0u, 0u, P11_2, P11_2_AUDIOSS0_TX_WS}, 86 {1u, 0u, P13_2, P13_2_AUDIOSS1_TX_WS}, 87 {2u, 0u, P14_4, P14_4_AUDIOSS2_TX_WS}, 88 }; 89 90 /* Connections for: canfd_ttcan_rx */ 91 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[14] = { 92 {0u, 1u, P0_3, P0_3_CANFD0_TTCAN_RX1}, 93 {0u, 0u, P2_1, P2_1_CANFD0_TTCAN_RX0}, 94 {0u, 3u, P3_1, P3_1_CANFD0_TTCAN_RX3}, 95 {0u, 2u, P6_3, P6_3_CANFD0_TTCAN_RX2}, 96 {0u, 0u, P8_1, P8_1_CANFD0_TTCAN_RX0}, 97 {0u, 2u, P12_1, P12_1_CANFD0_TTCAN_RX2}, 98 {1u, 1u, P12_5, P12_5_CANFD1_TTCAN_RX1}, 99 {1u, 0u, P14_1, P14_1_CANFD1_TTCAN_RX0}, 100 {1u, 3u, P15_1, P15_1_CANFD1_TTCAN_RX3}, 101 {1u, 1u, P17_1, P17_1_CANFD1_TTCAN_RX1}, 102 {1u, 2u, P18_7, P18_7_CANFD1_TTCAN_RX2}, 103 {1u, 3u, P19_1, P19_1_CANFD1_TTCAN_RX3}, 104 {1u, 1u, P22_1, P22_1_CANFD1_TTCAN_RX1}, 105 {1u, 0u, P23_1, P23_1_CANFD1_TTCAN_RX0}, 106 }; 107 108 /* Connections for: canfd_ttcan_tx */ 109 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[15] = { 110 {0u, 1u, P0_2, P0_2_CANFD0_TTCAN_TX1}, 111 {0u, 0u, P2_0, P2_0_CANFD0_TTCAN_TX0}, 112 {0u, 3u, P3_0, P3_0_CANFD0_TTCAN_TX3}, 113 {0u, 2u, P6_2, P6_2_CANFD0_TTCAN_TX2}, 114 {0u, 0u, P8_0, P8_0_CANFD0_TTCAN_TX0}, 115 {0u, 2u, P12_0, P12_0_CANFD0_TTCAN_TX2}, 116 {1u, 1u, P12_4, P12_4_CANFD1_TTCAN_TX1}, 117 {1u, 0u, P14_0, P14_0_CANFD1_TTCAN_TX0}, 118 {1u, 3u, P15_0, P15_0_CANFD1_TTCAN_TX3}, 119 {1u, 1u, P17_0, P17_0_CANFD1_TTCAN_TX1}, 120 {1u, 2u, P18_6, P18_6_CANFD1_TTCAN_TX2}, 121 {1u, 3u, P19_0, P19_0_CANFD1_TTCAN_TX3}, 122 {1u, 2u, P20_3, P20_3_CANFD1_TTCAN_TX2}, 123 {1u, 1u, P21_5, P21_5_CANFD1_TTCAN_TX1}, 124 {1u, 0u, P23_0, P23_0_CANFD1_TTCAN_TX0}, 125 }; 126 127 /* Connections for: cpuss_cal_sup_nz */ 128 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_cal_sup_nz[2] = { 129 {0u, 0u, P6_3, P6_3_CPUSS_CAL_SUP_NZ}, 130 {0u, 0u, P23_7, P23_7_CPUSS_CAL_SUP_NZ}, 131 }; 132 133 /* Connections for: cpuss_clk_fm_pump */ 134 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 135 {0u, 0u, P21_6, P21_6_CPUSS_CLK_FM_PUMP}, 136 }; 137 138 /* Connections for: cpuss_fault_out */ 139 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault_out[7] = { 140 {0u, 0u, P18_0, P18_0_CPUSS_FAULT_OUT0}, 141 {0u, 1u, P18_1, P18_1_CPUSS_FAULT_OUT1}, 142 {0u, 2u, P19_0, P19_0_CPUSS_FAULT_OUT2}, 143 {0u, 3u, P19_1, P19_1_CPUSS_FAULT_OUT3}, 144 {0u, 0u, P23_0, P23_0_CPUSS_FAULT_OUT0}, 145 {0u, 1u, P23_1, P23_1_CPUSS_FAULT_OUT1}, 146 {0u, 3u, P23_3, P23_3_CPUSS_FAULT_OUT3}, 147 }; 148 149 /* Connections for: cpuss_swj_swclk_tclk */ 150 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swclk_tclk[1] = { 151 {0u, 0u, P23_5, P23_5_CPUSS_SWJ_SWCLK_TCLK}, 152 }; 153 154 /* Connections for: cpuss_swj_swdio_tms */ 155 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 156 {0u, 0u, P23_6, P23_6_CPUSS_SWJ_SWDIO_TMS}, 157 }; 158 159 /* Connections for: cpuss_swj_swdoe_tdi */ 160 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 161 {0u, 0u, P23_7, P23_7_CPUSS_SWJ_SWDOE_TDI}, 162 }; 163 164 /* Connections for: cpuss_swj_swo_tdo */ 165 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 166 {0u, 0u, P23_4, P23_4_CPUSS_SWJ_SWO_TDO}, 167 }; 168 169 /* Connections for: cpuss_swj_trstn */ 170 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_trstn[1] = { 171 {0u, 0u, P2_0, P2_0_CPUSS_SWJ_TRSTN}, 172 }; 173 174 /* Connections for: cpuss_trace_clock */ 175 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2] = { 176 {0u, 0u, P18_3, P18_3_CPUSS_TRACE_CLOCK}, 177 {0u, 0u, P22_4, P22_4_CPUSS_TRACE_CLOCK}, 178 }; 179 180 /* Connections for: cpuss_trace_data */ 181 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8] = { 182 {0u, 0u, P18_4, P18_4_CPUSS_TRACE_DATA0}, 183 {0u, 1u, P18_5, P18_5_CPUSS_TRACE_DATA1}, 184 {0u, 2u, P18_6, P18_6_CPUSS_TRACE_DATA2}, 185 {0u, 3u, P18_7, P18_7_CPUSS_TRACE_DATA3}, 186 {0u, 0u, P21_5, P21_5_CPUSS_TRACE_DATA0}, 187 {0u, 1u, P22_1, P22_1_CPUSS_TRACE_DATA1}, 188 {0u, 2u, P22_2, P22_2_CPUSS_TRACE_DATA2}, 189 {0u, 3u, P22_3, P22_3_CPUSS_TRACE_DATA3}, 190 }; 191 192 /* Connections for: eth_eth_tsu_timer_cmp_val */ 193 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_eth_tsu_timer_cmp_val[1] = { 194 {0u, 0u, P2_3, P2_3_ETH0_ETH_TSU_TIMER_CMP_VAL}, 195 }; 196 197 /* Connections for: eth_mdc */ 198 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdc[1] = { 199 {0u, 0u, P3_1, P3_1_ETH0_MDC}, 200 }; 201 202 /* Connections for: eth_mdio */ 203 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_mdio[1] = { 204 {0u, 0u, P3_0, P3_0_ETH0_MDIO}, 205 }; 206 207 /* Connections for: eth_ref_clk */ 208 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_ref_clk[1] = { 209 {0u, 0u, P18_0, P18_0_ETH0_REF_CLK}, 210 }; 211 212 /* Connections for: eth_rx_clk */ 213 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_clk[1] = { 214 {0u, 0u, P23_3, P23_3_ETH0_RX_CLK}, 215 }; 216 217 /* Connections for: eth_rx_ctl */ 218 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_ctl[1] = { 219 {0u, 0u, P21_5, P21_5_ETH0_RX_CTL}, 220 }; 221 222 /* Connections for: eth_rx_er */ 223 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rx_er[1] = { 224 {0u, 0u, P2_2, P2_2_ETH0_RX_ER}, 225 }; 226 227 /* Connections for: eth_rxd */ 228 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_rxd[4] = { 229 {0u, 0u, P19_0, P19_0_ETH0_RXD0}, 230 {0u, 1u, P19_1, P19_1_ETH0_RXD1}, 231 {0u, 2u, P19_2, P19_2_ETH0_RXD2}, 232 {0u, 3u, P19_3, P19_3_ETH0_RXD3}, 233 }; 234 235 /* Connections for: eth_tx_clk */ 236 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_clk[1] = { 237 {0u, 0u, P18_3, P18_3_ETH0_TX_CLK}, 238 }; 239 240 /* Connections for: eth_tx_ctl */ 241 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_ctl[1] = { 242 {0u, 0u, P18_1, P18_1_ETH0_TX_CTL}, 243 }; 244 245 /* Connections for: eth_tx_er */ 246 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_tx_er[1] = { 247 {0u, 0u, P18_2, P18_2_ETH0_TX_ER}, 248 }; 249 250 /* Connections for: eth_txd */ 251 const cyhal_resource_pin_mapping_t cyhal_pin_map_eth_txd[4] = { 252 {0u, 0u, P18_4, P18_4_ETH0_TXD0}, 253 {0u, 1u, P18_5, P18_5_ETH0_TXD1}, 254 {0u, 2u, P18_6, P18_6_ETH0_TXD2}, 255 {0u, 3u, P18_7, P18_7_ETH0_TXD3}, 256 }; 257 258 /* Connections for: lin_lin_en */ 259 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[17] = { 260 {0u, 1u, P0_2, P0_2_LIN0_LIN_EN1}, 261 {0u, 0u, P2_2, P2_2_LIN0_LIN_EN0}, 262 {0u, 7u, P5_2, P5_2_LIN0_LIN_EN7}, 263 {0u, 9u, P6_0, P6_0_LIN0_LIN_EN9}, 264 {0u, 3u, P6_2, P6_2_LIN0_LIN_EN3}, 265 {0u, 4u, P6_5, P6_5_LIN0_LIN_EN4}, 266 {0u, 4u, P7_2, P7_2_LIN0_LIN_EN4}, 267 {0u, 10u, P7_7, P7_7_LIN0_LIN_EN10}, 268 {0u, 2u, P8_2, P8_2_LIN0_LIN_EN2}, 269 {0u, 8u, P10_4, P10_4_LIN0_LIN_EN8}, 270 {0u, 6u, P12_1, P12_1_LIN0_LIN_EN6}, 271 {0u, 3u, P13_2, P13_2_LIN0_LIN_EN3}, 272 {0u, 8u, P13_6, P13_6_LIN0_LIN_EN8}, 273 {0u, 6u, P14_4, P14_4_LIN0_LIN_EN6}, 274 {0u, 11u, P17_2, P17_2_LIN0_LIN_EN11}, 275 {0u, 5u, P20_2, P20_2_LIN0_LIN_EN5}, 276 {0u, 9u, P23_7, P23_7_LIN0_LIN_EN9}, 277 }; 278 279 /* Connections for: lin_lin_rx */ 280 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[28] = { 281 {0u, 1u, P0_0, P0_0_LIN0_LIN_RX1}, 282 {0u, 0u, P2_0, P2_0_LIN0_LIN_RX0}, 283 {0u, 5u, P2_3, P2_3_LIN0_LIN_RX5}, 284 {0u, 1u, P3_4, P3_4_LIN0_LIN_RX1}, 285 {0u, 1u, P4_0, P4_0_LIN0_LIN_RX1}, 286 {0u, 7u, P5_0, P5_0_LIN0_LIN_RX7}, 287 {0u, 10u, P5_2, P5_2_LIN0_LIN_RX10}, 288 {0u, 2u, P5_3, P5_3_LIN0_LIN_RX2}, 289 {0u, 9u, P5_4, P5_4_LIN0_LIN_RX9}, 290 {0u, 3u, P6_0, P6_0_LIN0_LIN_RX3}, 291 {0u, 4u, P6_3, P6_3_LIN0_LIN_RX4}, 292 {0u, 4u, P7_0, P7_0_LIN0_LIN_RX4}, 293 {0u, 10u, P7_5, P7_5_LIN0_LIN_RX10}, 294 {0u, 2u, P8_0, P8_0_LIN0_LIN_RX2}, 295 {0u, 12u, P9_1, P9_1_LIN0_LIN_RX12}, 296 {0u, 7u, P10_0, P10_0_LIN0_LIN_RX7}, 297 {0u, 8u, P10_2, P10_2_LIN0_LIN_RX8}, 298 {0u, 6u, P12_2, P12_2_LIN0_LIN_RX6}, 299 {0u, 3u, P13_0, P13_0_LIN0_LIN_RX3}, 300 {0u, 2u, P13_3, P13_3_LIN0_LIN_RX2}, 301 {0u, 8u, P13_4, P13_4_LIN0_LIN_RX8}, 302 {0u, 14u, P14_5, P14_5_LIN0_LIN_RX14}, 303 {0u, 11u, P17_0, P17_0_LIN0_LIN_RX11}, 304 {0u, 5u, P20_0, P20_0_LIN0_LIN_RX5}, 305 {0u, 0u, P21_5, P21_5_LIN0_LIN_RX0}, 306 {0u, 13u, P21_6, P21_6_LIN0_LIN_RX13}, 307 {0u, 7u, P22_5, P22_5_LIN0_LIN_RX7}, 308 {0u, 9u, P23_5, P23_5_LIN0_LIN_RX9}, 309 }; 310 311 /* Connections for: lin_lin_tx */ 312 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[27] = { 313 {0u, 1u, P0_1, P0_1_LIN0_LIN_TX1}, 314 {0u, 0u, P2_1, P2_1_LIN0_LIN_TX0}, 315 {0u, 5u, P2_4, P2_4_LIN0_LIN_TX5}, 316 {0u, 1u, P4_1, P4_1_LIN0_LIN_TX1}, 317 {0u, 15u, P5_0, P5_0_LIN0_LIN_TX15}, 318 {0u, 7u, P5_1, P5_1_LIN0_LIN_TX7}, 319 {0u, 10u, P5_3, P5_3_LIN0_LIN_TX10}, 320 {0u, 2u, P5_4, P5_4_LIN0_LIN_TX2}, 321 {0u, 3u, P6_1, P6_1_LIN0_LIN_TX3}, 322 {0u, 4u, P6_4, P6_4_LIN0_LIN_TX4}, 323 {0u, 4u, P7_1, P7_1_LIN0_LIN_TX4}, 324 {0u, 10u, P7_6, P7_6_LIN0_LIN_TX10}, 325 {0u, 2u, P8_1, P8_1_LIN0_LIN_TX2}, 326 {0u, 7u, P10_1, P10_1_LIN0_LIN_TX7}, 327 {0u, 8u, P10_3, P10_3_LIN0_LIN_TX8}, 328 {0u, 6u, P12_3, P12_3_LIN0_LIN_TX6}, 329 {0u, 3u, P13_1, P13_1_LIN0_LIN_TX3}, 330 {0u, 2u, P13_4, P13_4_LIN0_LIN_TX2}, 331 {0u, 8u, P13_5, P13_5_LIN0_LIN_TX8}, 332 {0u, 11u, P17_1, P17_1_LIN0_LIN_TX11}, 333 {0u, 12u, P18_0, P18_0_LIN0_LIN_TX12}, 334 {0u, 5u, P20_1, P20_1_LIN0_LIN_TX5}, 335 {0u, 0u, P21_6, P21_6_LIN0_LIN_TX0}, 336 {0u, 7u, P22_6, P22_6_LIN0_LIN_TX7}, 337 {0u, 14u, P23_0, P23_0_LIN0_LIN_TX14}, 338 {0u, 6u, P23_3, P23_3_LIN0_LIN_TX6}, 339 {0u, 9u, P23_6, P23_6_LIN0_LIN_TX9}, 340 }; 341 342 /* Connections for: pass_sar_ext_mux_en */ 343 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_en[2] = { 344 {0u, 1u, P12_2, P12_2_PASS0_SAR_EXT_MUX_EN1}, 345 {0u, 2u, P13_3, P13_3_PASS0_SAR_EXT_MUX_EN2}, 346 }; 347 348 /* Connections for: pass_sar_ext_mux_sel */ 349 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sar_ext_mux_sel[8] = { 350 {0u, 0u, P4_0, P4_0_PASS0_SAR_EXT_MUX_SEL0}, 351 {0u, 1u, P4_1, P4_1_PASS0_SAR_EXT_MUX_SEL1}, 352 {0u, 3u, P12_3, P12_3_PASS0_SAR_EXT_MUX_SEL3}, 353 {0u, 4u, P12_4, P12_4_PASS0_SAR_EXT_MUX_SEL4}, 354 {0u, 5u, P12_5, P12_5_PASS0_SAR_EXT_MUX_SEL5}, 355 {0u, 6u, P13_0, P13_0_PASS0_SAR_EXT_MUX_SEL6}, 356 {0u, 7u, P13_1, P13_1_PASS0_SAR_EXT_MUX_SEL7}, 357 {0u, 8u, P13_2, P13_2_PASS0_SAR_EXT_MUX_SEL8}, 358 }; 359 360 /* Connections for: pass_sarmux_pads */ 361 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[52] = { 362 {0u, 0u, P6_0, HSIOM_SEL_GPIO}, 363 {0u, 1u, P6_1, HSIOM_SEL_GPIO}, 364 {0u, 2u, P6_2, HSIOM_SEL_GPIO}, 365 {0u, 3u, P6_3, HSIOM_SEL_GPIO}, 366 {0u, 4u, P6_4, HSIOM_SEL_GPIO}, 367 {0u, 5u, P6_5, HSIOM_SEL_GPIO}, 368 {0u, 6u, P6_6, HSIOM_SEL_GPIO}, 369 {0u, 7u, P6_7, HSIOM_SEL_GPIO}, 370 {0u, 16u, P7_0, HSIOM_SEL_GPIO}, 371 {0u, 17u, P7_1, HSIOM_SEL_GPIO}, 372 {0u, 18u, P7_2, HSIOM_SEL_GPIO}, 373 {0u, 19u, P7_3, HSIOM_SEL_GPIO}, 374 {0u, 20u, P7_4, HSIOM_SEL_GPIO}, 375 {0u, 21u, P7_5, HSIOM_SEL_GPIO}, 376 {0u, 22u, P7_6, HSIOM_SEL_GPIO}, 377 {0u, 23u, P7_7, HSIOM_SEL_GPIO}, 378 {0u, 24u, P8_1, HSIOM_SEL_GPIO}, 379 {0u, 25u, P8_2, HSIOM_SEL_GPIO}, 380 {0u, 26u, P8_3, HSIOM_SEL_GPIO}, 381 {0u, 28u, P9_0, HSIOM_SEL_GPIO}, 382 {0u, 29u, P9_1, HSIOM_SEL_GPIO}, 383 {1u, 0u, P10_4, HSIOM_SEL_GPIO}, 384 {1u, 4u, P12_0, HSIOM_SEL_GPIO}, 385 {1u, 5u, P12_1, HSIOM_SEL_GPIO}, 386 {1u, 6u, P12_2, HSIOM_SEL_GPIO}, 387 {1u, 7u, P12_3, HSIOM_SEL_GPIO}, 388 {1u, 8u, P12_4, HSIOM_SEL_GPIO}, 389 {1u, 9u, P12_5, HSIOM_SEL_GPIO}, 390 {1u, 12u, P13_0, HSIOM_SEL_GPIO}, 391 {1u, 13u, P13_1, HSIOM_SEL_GPIO}, 392 {1u, 14u, P13_2, HSIOM_SEL_GPIO}, 393 {1u, 15u, P13_3, HSIOM_SEL_GPIO}, 394 {1u, 16u, P13_4, HSIOM_SEL_GPIO}, 395 {1u, 17u, P13_5, HSIOM_SEL_GPIO}, 396 {1u, 18u, P13_6, HSIOM_SEL_GPIO}, 397 {1u, 19u, P13_7, HSIOM_SEL_GPIO}, 398 {1u, 20u, P14_0, HSIOM_SEL_GPIO}, 399 {1u, 21u, P14_1, HSIOM_SEL_GPIO}, 400 {1u, 24u, P14_4, HSIOM_SEL_GPIO}, 401 {1u, 25u, P14_5, HSIOM_SEL_GPIO}, 402 {1u, 28u, P15_0, HSIOM_SEL_GPIO}, 403 {1u, 29u, P15_1, HSIOM_SEL_GPIO}, 404 {1u, 30u, P15_2, HSIOM_SEL_GPIO}, 405 {1u, 31u, P15_3, HSIOM_SEL_GPIO}, 406 {2u, 0u, P18_0, HSIOM_SEL_GPIO}, 407 {2u, 1u, P18_1, HSIOM_SEL_GPIO}, 408 {2u, 2u, P18_2, HSIOM_SEL_GPIO}, 409 {2u, 3u, P18_3, HSIOM_SEL_GPIO}, 410 {2u, 4u, P18_4, HSIOM_SEL_GPIO}, 411 {2u, 5u, P18_5, HSIOM_SEL_GPIO}, 412 {2u, 6u, P18_6, HSIOM_SEL_GPIO}, 413 {2u, 7u, P18_7, HSIOM_SEL_GPIO}, 414 }; 415 416 /* Connections for: peri_tr_io_input */ 417 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 418 to know the index of the input or output trigger line. Store that in the channel_num field 419 instead. */ 420 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[25] = { 421 {0u, 2u, P2_0, P2_0_PERI_TR_IO_INPUT2}, 422 {0u, 3u, P2_1, P2_1_PERI_TR_IO_INPUT3}, 423 {0u, 4u, P2_2, P2_2_PERI_TR_IO_INPUT4}, 424 {0u, 5u, P2_3, P2_3_PERI_TR_IO_INPUT5}, 425 {0u, 6u, P2_4, P2_4_PERI_TR_IO_INPUT6}, 426 {0u, 10u, P4_0, P4_0_PERI_TR_IO_INPUT10}, 427 {0u, 11u, P4_1, P4_1_PERI_TR_IO_INPUT11}, 428 {0u, 8u, P6_6, P6_6_PERI_TR_IO_INPUT8}, 429 {0u, 9u, P6_7, P6_7_PERI_TR_IO_INPUT9}, 430 {0u, 16u, P7_6, P7_6_PERI_TR_IO_INPUT16}, 431 {0u, 17u, P7_7, P7_7_PERI_TR_IO_INPUT17}, 432 {0u, 14u, P8_1, P8_1_PERI_TR_IO_INPUT14}, 433 {0u, 15u, P8_2, P8_2_PERI_TR_IO_INPUT15}, 434 {0u, 18u, P10_0, P10_0_PERI_TR_IO_INPUT18}, 435 {0u, 19u, P10_1, P10_1_PERI_TR_IO_INPUT19}, 436 {0u, 20u, P12_0, P12_0_PERI_TR_IO_INPUT20}, 437 {0u, 21u, P12_1, P12_1_PERI_TR_IO_INPUT21}, 438 {0u, 22u, P13_6, P13_6_PERI_TR_IO_INPUT22}, 439 {0u, 23u, P13_7, P13_7_PERI_TR_IO_INPUT23}, 440 {0u, 26u, P17_3, P17_3_PERI_TR_IO_INPUT26}, 441 {0u, 27u, P17_4, P17_4_PERI_TR_IO_INPUT27}, 442 {0u, 28u, P19_2, P19_2_PERI_TR_IO_INPUT28}, 443 {0u, 29u, P19_3, P19_3_PERI_TR_IO_INPUT29}, 444 {0u, 30u, P23_3, P23_3_PERI_TR_IO_INPUT30}, 445 {0u, 31u, P23_4, P23_4_PERI_TR_IO_INPUT31}, 446 }; 447 448 /* Connections for: peri_tr_io_output */ 449 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 450 to know the index of the input or output trigger line. Store that in the channel_num field 451 instead. */ 452 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[5] = { 453 {0u, 0u, P3_0, P3_0_PERI_TR_IO_OUTPUT0}, 454 {0u, 1u, P3_1, P3_1_PERI_TR_IO_OUTPUT1}, 455 {0u, 0u, P8_3, P8_3_PERI_TR_IO_OUTPUT0}, 456 {0u, 1u, P21_2, P21_2_PERI_TR_IO_OUTPUT1}, 457 {0u, 0u, P23_4, P23_4_PERI_TR_IO_OUTPUT0}, 458 }; 459 460 /* Connections for: scb_i2c_scl */ 461 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[15] = { 462 {7u, 0u, P0_1, P0_1_SCB7_I2C_SCL}, 463 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 464 {0u, 0u, P1_0, P1_0_SCB0_I2C_SCL}, 465 {7u, 0u, P2_2, P2_2_SCB7_I2C_SCL}, 466 {6u, 0u, P3_2, P3_2_SCB6_I2C_SCL}, 467 {4u, 0u, P6_2, P6_2_SCB4_I2C_SCL}, 468 {5u, 0u, P7_2, P7_2_SCB5_I2C_SCL}, 469 {4u, 0u, P10_2, P10_2_SCB4_I2C_SCL}, 470 {8u, 0u, P12_2, P12_2_SCB8_I2C_SCL}, 471 {3u, 0u, P13_2, P13_2_SCB3_I2C_SCL}, 472 {9u, 0u, P15_2, P15_2_SCB9_I2C_SCL}, 473 {3u, 0u, P17_3, P17_3_SCB3_I2C_SCL}, 474 {1u, 0u, P18_2, P18_2_SCB1_I2C_SCL}, 475 {2u, 0u, P19_2, P19_2_SCB2_I2C_SCL}, 476 {6u, 0u, P22_2, P22_2_SCB6_I2C_SCL}, 477 }; 478 479 /* Connections for: scb_i2c_sda */ 480 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[18] = { 481 {7u, 0u, P0_0, P0_0_SCB7_I2C_SDA}, 482 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 483 {0u, 0u, P1_1, P1_1_SCB0_I2C_SDA}, 484 {7u, 0u, P2_1, P2_1_SCB7_I2C_SDA}, 485 {6u, 0u, P3_1, P3_1_SCB6_I2C_SDA}, 486 {5u, 0u, P4_1, P4_1_SCB5_I2C_SDA}, 487 {4u, 0u, P6_1, P6_1_SCB4_I2C_SDA}, 488 {5u, 0u, P7_1, P7_1_SCB5_I2C_SDA}, 489 {4u, 0u, P10_1, P10_1_SCB4_I2C_SDA}, 490 {8u, 0u, P12_1, P12_1_SCB8_I2C_SDA}, 491 {3u, 0u, P13_1, P13_1_SCB3_I2C_SDA}, 492 {2u, 0u, P14_1, P14_1_SCB2_I2C_SDA}, 493 {9u, 0u, P15_1, P15_1_SCB9_I2C_SDA}, 494 {3u, 0u, P17_2, P17_2_SCB3_I2C_SDA}, 495 {1u, 0u, P18_1, P18_1_SCB1_I2C_SDA}, 496 {2u, 0u, P19_1, P19_1_SCB2_I2C_SDA}, 497 {6u, 0u, P22_1, P22_1_SCB6_I2C_SDA}, 498 {7u, 0u, P23_1, P23_1_SCB7_I2C_SDA}, 499 }; 500 501 /* Connections for: scb_spi_m_clk */ 502 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[16] = { 503 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 504 {4u, 0u, P1_0, P1_0_SCB4_SPI_CLK}, 505 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 506 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 507 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 508 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 509 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 510 {8u, 0u, P12_2, P12_2_SCB8_SPI_CLK}, 511 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 512 {9u, 0u, P15_2, P15_2_SCB9_SPI_CLK}, 513 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 514 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 515 {3u, 0u, P18_3, P18_3_SCB3_SPI_CLK}, 516 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 517 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 518 {2u, 0u, P23_6, P23_6_SCB2_SPI_CLK}, 519 }; 520 521 /* Connections for: scb_spi_m_miso */ 522 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[19] = { 523 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 524 {4u, 0u, P0_2, P0_2_SCB4_SPI_MISO}, 525 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 526 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 527 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 528 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 529 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 530 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 531 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 532 {8u, 0u, P12_0, P12_0_SCB8_SPI_MISO}, 533 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 534 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 535 {9u, 0u, P15_0, P15_0_SCB9_SPI_MISO}, 536 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 537 {3u, 0u, P18_1, P18_1_SCB3_SPI_MISO}, 538 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 539 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 540 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 541 {2u, 0u, P23_4, P23_4_SCB2_SPI_MISO}, 542 }; 543 544 /* Connections for: scb_spi_m_mosi */ 545 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[19] = { 546 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 547 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI}, 548 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 549 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 550 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 551 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 552 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 553 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 554 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 555 {8u, 0u, P12_1, P12_1_SCB8_SPI_MOSI}, 556 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 557 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 558 {9u, 0u, P15_1, P15_1_SCB9_SPI_MOSI}, 559 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 560 {3u, 0u, P18_2, P18_2_SCB3_SPI_MOSI}, 561 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 562 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 563 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 564 {2u, 0u, P23_5, P23_5_SCB2_SPI_MOSI}, 565 }; 566 567 /* Connections for: scb_spi_m_select0 */ 568 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[17] = { 569 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 570 {4u, 0u, P1_1, P1_1_SCB4_SPI_SELECT0}, 571 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 572 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 573 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 574 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 575 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 576 {8u, 0u, P12_3, P12_3_SCB8_SPI_SELECT0}, 577 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 578 {9u, 0u, P15_3, P15_3_SCB9_SPI_SELECT0}, 579 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 580 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 581 {3u, 0u, P18_4, P18_4_SCB3_SPI_SELECT0}, 582 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 583 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 584 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 585 {2u, 0u, P23_7, P23_7_SCB2_SPI_SELECT0}, 586 }; 587 588 /* Connections for: scb_spi_m_select1 */ 589 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[13] = { 590 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 591 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 592 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 593 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 594 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 595 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 596 {8u, 0u, P12_4, P12_4_SCB8_SPI_SELECT1}, 597 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 598 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 599 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 600 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 601 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 602 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 603 }; 604 605 /* Connections for: scb_spi_m_select2 */ 606 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[11] = { 607 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 608 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 609 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 610 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 611 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 612 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 613 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 614 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 615 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 616 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 617 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 618 }; 619 620 /* Connections for: scb_spi_m_select3 */ 621 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[5] = { 622 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 623 {9u, 0u, P5_1, P5_1_SCB9_SPI_SELECT3}, 624 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 625 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 626 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 627 }; 628 629 /* Connections for: scb_spi_s_clk */ 630 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[16] = { 631 {0u, 0u, P0_2, P0_2_SCB0_SPI_CLK}, 632 {4u, 0u, P1_0, P1_0_SCB4_SPI_CLK}, 633 {7u, 0u, P2_2, P2_2_SCB7_SPI_CLK}, 634 {6u, 0u, P3_2, P3_2_SCB6_SPI_CLK}, 635 {4u, 0u, P6_2, P6_2_SCB4_SPI_CLK}, 636 {5u, 0u, P7_2, P7_2_SCB5_SPI_CLK}, 637 {4u, 0u, P10_2, P10_2_SCB4_SPI_CLK}, 638 {8u, 0u, P12_2, P12_2_SCB8_SPI_CLK}, 639 {3u, 0u, P13_2, P13_2_SCB3_SPI_CLK}, 640 {9u, 0u, P15_2, P15_2_SCB9_SPI_CLK}, 641 {3u, 0u, P17_3, P17_3_SCB3_SPI_CLK}, 642 {1u, 0u, P18_2, P18_2_SCB1_SPI_CLK}, 643 {3u, 0u, P18_3, P18_3_SCB3_SPI_CLK}, 644 {2u, 0u, P19_2, P19_2_SCB2_SPI_CLK}, 645 {6u, 0u, P22_2, P22_2_SCB6_SPI_CLK}, 646 {2u, 0u, P23_6, P23_6_SCB2_SPI_CLK}, 647 }; 648 649 /* Connections for: scb_spi_s_miso */ 650 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[19] = { 651 {0u, 0u, P0_0, P0_0_SCB0_SPI_MISO}, 652 {4u, 0u, P0_2, P0_2_SCB4_SPI_MISO}, 653 {0u, 0u, P1_0, P1_0_SCB0_SPI_MISO}, 654 {7u, 0u, P2_0, P2_0_SCB7_SPI_MISO}, 655 {6u, 0u, P3_0, P3_0_SCB6_SPI_MISO}, 656 {5u, 0u, P4_0, P4_0_SCB5_SPI_MISO}, 657 {4u, 0u, P6_0, P6_0_SCB4_SPI_MISO}, 658 {5u, 0u, P7_0, P7_0_SCB5_SPI_MISO}, 659 {4u, 0u, P10_0, P10_0_SCB4_SPI_MISO}, 660 {8u, 0u, P12_0, P12_0_SCB8_SPI_MISO}, 661 {3u, 0u, P13_0, P13_0_SCB3_SPI_MISO}, 662 {2u, 0u, P14_0, P14_0_SCB2_SPI_MISO}, 663 {9u, 0u, P15_0, P15_0_SCB9_SPI_MISO}, 664 {1u, 0u, P18_0, P18_0_SCB1_SPI_MISO}, 665 {3u, 0u, P18_1, P18_1_SCB3_SPI_MISO}, 666 {2u, 0u, P19_0, P19_0_SCB2_SPI_MISO}, 667 {1u, 0u, P20_3, P20_3_SCB1_SPI_MISO}, 668 {7u, 0u, P23_0, P23_0_SCB7_SPI_MISO}, 669 {2u, 0u, P23_4, P23_4_SCB2_SPI_MISO}, 670 }; 671 672 /* Connections for: scb_spi_s_mosi */ 673 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[19] = { 674 {0u, 0u, P0_1, P0_1_SCB0_SPI_MOSI}, 675 {4u, 0u, P0_3, P0_3_SCB4_SPI_MOSI}, 676 {0u, 0u, P1_1, P1_1_SCB0_SPI_MOSI}, 677 {7u, 0u, P2_1, P2_1_SCB7_SPI_MOSI}, 678 {6u, 0u, P3_1, P3_1_SCB6_SPI_MOSI}, 679 {5u, 0u, P4_1, P4_1_SCB5_SPI_MOSI}, 680 {4u, 0u, P6_1, P6_1_SCB4_SPI_MOSI}, 681 {5u, 0u, P7_1, P7_1_SCB5_SPI_MOSI}, 682 {4u, 0u, P10_1, P10_1_SCB4_SPI_MOSI}, 683 {8u, 0u, P12_1, P12_1_SCB8_SPI_MOSI}, 684 {3u, 0u, P13_1, P13_1_SCB3_SPI_MOSI}, 685 {2u, 0u, P14_1, P14_1_SCB2_SPI_MOSI}, 686 {9u, 0u, P15_1, P15_1_SCB9_SPI_MOSI}, 687 {1u, 0u, P18_1, P18_1_SCB1_SPI_MOSI}, 688 {3u, 0u, P18_2, P18_2_SCB3_SPI_MOSI}, 689 {2u, 0u, P19_1, P19_1_SCB2_SPI_MOSI}, 690 {6u, 0u, P22_1, P22_1_SCB6_SPI_MOSI}, 691 {7u, 0u, P23_1, P23_1_SCB7_SPI_MOSI}, 692 {2u, 0u, P23_5, P23_5_SCB2_SPI_MOSI}, 693 }; 694 695 /* Connections for: scb_spi_s_select0 */ 696 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[17] = { 697 {0u, 0u, P0_3, P0_3_SCB0_SPI_SELECT0}, 698 {4u, 0u, P1_1, P1_1_SCB4_SPI_SELECT0}, 699 {7u, 0u, P2_3, P2_3_SCB7_SPI_SELECT0}, 700 {6u, 0u, P3_3, P3_3_SCB6_SPI_SELECT0}, 701 {4u, 0u, P6_3, P6_3_SCB4_SPI_SELECT0}, 702 {5u, 0u, P7_3, P7_3_SCB5_SPI_SELECT0}, 703 {4u, 0u, P10_3, P10_3_SCB4_SPI_SELECT0}, 704 {8u, 0u, P12_3, P12_3_SCB8_SPI_SELECT0}, 705 {3u, 0u, P13_3, P13_3_SCB3_SPI_SELECT0}, 706 {9u, 0u, P15_3, P15_3_SCB9_SPI_SELECT0}, 707 {3u, 0u, P17_4, P17_4_SCB3_SPI_SELECT0}, 708 {1u, 0u, P18_3, P18_3_SCB1_SPI_SELECT0}, 709 {3u, 0u, P18_4, P18_4_SCB3_SPI_SELECT0}, 710 {2u, 0u, P19_3, P19_3_SCB2_SPI_SELECT0}, 711 {6u, 0u, P22_3, P22_3_SCB6_SPI_SELECT0}, 712 {7u, 0u, P23_3, P23_3_SCB7_SPI_SELECT0}, 713 {2u, 0u, P23_7, P23_7_SCB2_SPI_SELECT0}, 714 }; 715 716 /* Connections for: scb_spi_s_select1 */ 717 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[13] = { 718 {0u, 0u, P2_0, P2_0_SCB0_SPI_SELECT1}, 719 {7u, 0u, P2_4, P2_4_SCB7_SPI_SELECT1}, 720 {6u, 0u, P3_4, P3_4_SCB6_SPI_SELECT1}, 721 {4u, 0u, P6_4, P6_4_SCB4_SPI_SELECT1}, 722 {5u, 0u, P7_4, P7_4_SCB5_SPI_SELECT1}, 723 {4u, 0u, P10_4, P10_4_SCB4_SPI_SELECT1}, 724 {8u, 0u, P12_4, P12_4_SCB8_SPI_SELECT1}, 725 {3u, 0u, P13_4, P13_4_SCB3_SPI_SELECT1}, 726 {2u, 0u, P14_4, P14_4_SCB2_SPI_SELECT1}, 727 {1u, 0u, P18_4, P18_4_SCB1_SPI_SELECT1}, 728 {2u, 0u, P19_4, P19_4_SCB2_SPI_SELECT1}, 729 {6u, 0u, P22_4, P22_4_SCB6_SPI_SELECT1}, 730 {7u, 0u, P23_4, P23_4_SCB7_SPI_SELECT1}, 731 }; 732 733 /* Connections for: scb_spi_s_select2 */ 734 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[11] = { 735 {0u, 0u, P2_1, P2_1_SCB0_SPI_SELECT2}, 736 {5u, 0u, P5_0, P5_0_SCB5_SPI_SELECT2}, 737 {4u, 0u, P6_5, P6_5_SCB4_SPI_SELECT2}, 738 {5u, 0u, P7_5, P7_5_SCB5_SPI_SELECT2}, 739 {3u, 0u, P13_5, P13_5_SCB3_SPI_SELECT2}, 740 {2u, 0u, P14_5, P14_5_SCB2_SPI_SELECT2}, 741 {1u, 0u, P18_5, P18_5_SCB1_SPI_SELECT2}, 742 {2u, 0u, P20_0, P20_0_SCB2_SPI_SELECT2}, 743 {1u, 0u, P21_0, P21_0_SCB1_SPI_SELECT2}, 744 {6u, 0u, P22_5, P22_5_SCB6_SPI_SELECT2}, 745 {7u, 0u, P23_5, P23_5_SCB7_SPI_SELECT2}, 746 }; 747 748 /* Connections for: scb_spi_s_select3 */ 749 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[5] = { 750 {0u, 0u, P2_2, P2_2_SCB0_SPI_SELECT3}, 751 {9u, 0u, P5_1, P5_1_SCB9_SPI_SELECT3}, 752 {4u, 0u, P6_6, P6_6_SCB4_SPI_SELECT3}, 753 {3u, 0u, P13_6, P13_6_SCB3_SPI_SELECT3}, 754 {1u, 0u, P18_6, P18_6_SCB1_SPI_SELECT3}, 755 }; 756 757 /* Connections for: scb_uart_cts */ 758 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[14] = { 759 {0u, 0u, P0_3, P0_3_SCB0_UART_CTS}, 760 {7u, 0u, P2_3, P2_3_SCB7_UART_CTS}, 761 {6u, 0u, P3_3, P3_3_SCB6_UART_CTS}, 762 {4u, 0u, P6_3, P6_3_SCB4_UART_CTS}, 763 {5u, 0u, P7_3, P7_3_SCB5_UART_CTS}, 764 {4u, 0u, P10_3, P10_3_SCB4_UART_CTS}, 765 {8u, 0u, P12_3, P12_3_SCB8_UART_CTS}, 766 {3u, 0u, P13_3, P13_3_SCB3_UART_CTS}, 767 {9u, 0u, P15_3, P15_3_SCB9_UART_CTS}, 768 {3u, 0u, P17_4, P17_4_SCB3_UART_CTS}, 769 {1u, 0u, P18_3, P18_3_SCB1_UART_CTS}, 770 {2u, 0u, P19_3, P19_3_SCB2_UART_CTS}, 771 {6u, 0u, P22_3, P22_3_SCB6_UART_CTS}, 772 {7u, 0u, P23_3, P23_3_SCB7_UART_CTS}, 773 }; 774 775 /* Connections for: scb_uart_rts */ 776 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[13] = { 777 {0u, 0u, P0_2, P0_2_SCB0_UART_RTS}, 778 {7u, 0u, P2_2, P2_2_SCB7_UART_RTS}, 779 {6u, 0u, P3_2, P3_2_SCB6_UART_RTS}, 780 {4u, 0u, P6_2, P6_2_SCB4_UART_RTS}, 781 {5u, 0u, P7_2, P7_2_SCB5_UART_RTS}, 782 {4u, 0u, P10_2, P10_2_SCB4_UART_RTS}, 783 {8u, 0u, P12_2, P12_2_SCB8_UART_RTS}, 784 {3u, 0u, P13_2, P13_2_SCB3_UART_RTS}, 785 {9u, 0u, P15_2, P15_2_SCB9_UART_RTS}, 786 {3u, 0u, P17_3, P17_3_SCB3_UART_RTS}, 787 {1u, 0u, P18_2, P18_2_SCB1_UART_RTS}, 788 {2u, 0u, P19_2, P19_2_SCB2_UART_RTS}, 789 {6u, 0u, P22_2, P22_2_SCB6_UART_RTS}, 790 }; 791 792 /* Connections for: scb_uart_rx */ 793 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[16] = { 794 {0u, 0u, P0_0, P0_0_SCB0_UART_RX}, 795 {7u, 0u, P2_0, P2_0_SCB7_UART_RX}, 796 {6u, 0u, P3_0, P3_0_SCB6_UART_RX}, 797 {5u, 0u, P4_0, P4_0_SCB5_UART_RX}, 798 {4u, 0u, P6_0, P6_0_SCB4_UART_RX}, 799 {5u, 0u, P7_0, P7_0_SCB5_UART_RX}, 800 {4u, 0u, P10_0, P10_0_SCB4_UART_RX}, 801 {8u, 0u, P12_0, P12_0_SCB8_UART_RX}, 802 {3u, 0u, P13_0, P13_0_SCB3_UART_RX}, 803 {2u, 0u, P14_0, P14_0_SCB2_UART_RX}, 804 {9u, 0u, P15_0, P15_0_SCB9_UART_RX}, 805 {3u, 0u, P17_1, P17_1_SCB3_UART_RX}, 806 {1u, 0u, P18_0, P18_0_SCB1_UART_RX}, 807 {2u, 0u, P19_0, P19_0_SCB2_UART_RX}, 808 {1u, 0u, P20_3, P20_3_SCB1_UART_RX}, 809 {7u, 0u, P23_0, P23_0_SCB7_UART_RX}, 810 }; 811 812 /* Connections for: scb_uart_tx */ 813 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[16] = { 814 {0u, 0u, P0_1, P0_1_SCB0_UART_TX}, 815 {7u, 0u, P2_1, P2_1_SCB7_UART_TX}, 816 {6u, 0u, P3_1, P3_1_SCB6_UART_TX}, 817 {5u, 0u, P4_1, P4_1_SCB5_UART_TX}, 818 {4u, 0u, P6_1, P6_1_SCB4_UART_TX}, 819 {5u, 0u, P7_1, P7_1_SCB5_UART_TX}, 820 {4u, 0u, P10_1, P10_1_SCB4_UART_TX}, 821 {8u, 0u, P12_1, P12_1_SCB8_UART_TX}, 822 {3u, 0u, P13_1, P13_1_SCB3_UART_TX}, 823 {2u, 0u, P14_1, P14_1_SCB2_UART_TX}, 824 {9u, 0u, P15_1, P15_1_SCB9_UART_TX}, 825 {3u, 0u, P17_2, P17_2_SCB3_UART_TX}, 826 {1u, 0u, P18_1, P18_1_SCB1_UART_TX}, 827 {2u, 0u, P19_1, P19_1_SCB2_UART_TX}, 828 {6u, 0u, P22_1, P22_1_SCB6_UART_TX}, 829 {7u, 0u, P23_1, P23_1_SCB7_UART_TX}, 830 }; 831 832 /* Connections for: sdhc_card_cmd */ 833 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1] = { 834 {0u, 0u, P6_3, P6_3_SDHC0_CARD_CMD}, 835 }; 836 837 /* Connections for: sdhc_card_dat_3to0 */ 838 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4] = { 839 {0u, 0u, P7_1, P7_1_SDHC0_CARD_DAT_3TO00}, 840 {0u, 1u, P7_2, P7_2_SDHC0_CARD_DAT_3TO01}, 841 {0u, 2u, P7_3, P7_3_SDHC0_CARD_DAT_3TO02}, 842 {0u, 3u, P7_4, P7_4_SDHC0_CARD_DAT_3TO03}, 843 }; 844 845 /* Connections for: sdhc_card_dat_7to4 */ 846 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4] = { 847 {0u, 0u, P7_5, P7_5_SDHC0_CARD_DAT_7TO40}, 848 {0u, 1u, P8_0, P8_0_SDHC0_CARD_DAT_7TO41}, 849 {0u, 2u, P8_1, P8_1_SDHC0_CARD_DAT_7TO42}, 850 {0u, 3u, P8_2, P8_2_SDHC0_CARD_DAT_7TO43}, 851 }; 852 853 /* Connections for: sdhc_card_detect_n */ 854 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1] = { 855 {0u, 0u, P6_5, P6_5_SDHC0_CARD_DETECT_N}, 856 }; 857 858 /* Connections for: sdhc_card_if_pwr_en */ 859 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1] = { 860 {0u, 0u, P7_0, P7_0_SDHC0_CARD_IF_PWR_EN}, 861 }; 862 863 /* Connections for: sdhc_card_mech_write_prot */ 864 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1] = { 865 {0u, 0u, P6_2, P6_2_SDHC0_CARD_MECH_WRITE_PROT}, 866 }; 867 868 /* Connections for: sdhc_clk_card */ 869 const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1] = { 870 {0u, 0u, P6_4, P6_4_SDHC0_CLK_CARD}, 871 }; 872 873 /* Connections for: smif_spi_clk */ 874 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = { 875 {0u, 0u, P6_3, P6_3_SMIF0_SPIHB_CLK}, 876 }; 877 878 /* Connections for: smif_spi_data0 */ 879 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = { 880 {0u, 0u, P7_1, P7_1_SMIF0_SPIHB_DATA0}, 881 }; 882 883 /* Connections for: smif_spi_data1 */ 884 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = { 885 {0u, 0u, P7_2, P7_2_SMIF0_SPIHB_DATA1}, 886 }; 887 888 /* Connections for: smif_spi_data2 */ 889 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = { 890 {0u, 0u, P7_3, P7_3_SMIF0_SPIHB_DATA2}, 891 }; 892 893 /* Connections for: smif_spi_data3 */ 894 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = { 895 {0u, 0u, P7_4, P7_4_SMIF0_SPIHB_DATA3}, 896 }; 897 898 /* Connections for: smif_spi_data4 */ 899 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1] = { 900 {0u, 0u, P7_5, P7_5_SMIF0_SPIHB_DATA4}, 901 }; 902 903 /* Connections for: smif_spi_data5 */ 904 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1] = { 905 {0u, 0u, P8_0, P8_0_SMIF0_SPIHB_DATA5}, 906 }; 907 908 /* Connections for: smif_spi_data6 */ 909 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1] = { 910 {0u, 0u, P8_1, P8_1_SMIF0_SPIHB_DATA6}, 911 }; 912 913 /* Connections for: smif_spi_data7 */ 914 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1] = { 915 {0u, 0u, P8_2, P8_2_SMIF0_SPIHB_DATA7}, 916 }; 917 918 /* Connections for: smif_spi_rwds */ 919 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_rwds[1] = { 920 {0u, 0u, P6_4, P6_4_SMIF0_SPIHB_RWDS}, 921 }; 922 923 /* Connections for: smif_spi_select0 */ 924 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = { 925 {0u, 0u, P6_5, P6_5_SMIF0_SPIHB_SELECT0}, 926 }; 927 928 /* Connections for: smif_spi_select1 */ 929 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = { 930 {0u, 0u, P7_0, P7_0_SMIF0_SPIHB_SELECT1}, 931 }; 932 933 /* Connections for: tcpwm_line */ 934 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[127] = { 935 {0u, 18u, P0_0, P0_0_TCPWM0_LINE18}, 936 {0u, 17u, P0_1, P0_1_TCPWM0_LINE17}, 937 {0u, 14u, P0_2, P0_2_TCPWM0_LINE14}, 938 {0u, 13u, P0_3, P0_3_TCPWM0_LINE13}, 939 {0u, 12u, P1_0, P1_0_TCPWM0_LINE12}, 940 {2u, 4u, P1_0, P1_0_TCPWM0_LINE516}, 941 {0u, 11u, P1_1, P1_1_TCPWM0_LINE11}, 942 {2u, 5u, P1_1, P1_1_TCPWM0_LINE517}, 943 {0u, 7u, P2_0, P2_0_TCPWM0_LINE7}, 944 {0u, 6u, P2_1, P2_1_TCPWM0_LINE6}, 945 {0u, 5u, P2_2, P2_2_TCPWM0_LINE5}, 946 {0u, 4u, P2_3, P2_3_TCPWM0_LINE4}, 947 {0u, 3u, P2_4, P2_4_TCPWM0_LINE3}, 948 {0u, 1u, P3_0, P3_0_TCPWM0_LINE1}, 949 {0u, 0u, P3_1, P3_1_TCPWM0_LINE0}, 950 {1u, 3u, P3_2, P3_2_TCPWM0_LINE259}, 951 {1u, 2u, P3_3, P3_3_TCPWM0_LINE258}, 952 {1u, 1u, P3_4, P3_4_TCPWM0_LINE257}, 953 {0u, 4u, P4_0, P4_0_TCPWM0_LINE4}, 954 {0u, 5u, P4_1, P4_1_TCPWM0_LINE5}, 955 {0u, 9u, P5_0, P5_0_TCPWM0_LINE9}, 956 {0u, 10u, P5_1, P5_1_TCPWM0_LINE10}, 957 {0u, 11u, P5_2, P5_2_TCPWM0_LINE11}, 958 {0u, 12u, P5_3, P5_3_TCPWM0_LINE12}, 959 {0u, 13u, P5_4, P5_4_TCPWM0_LINE13}, 960 {1u, 0u, P6_0, P6_0_TCPWM0_LINE256}, 961 {0u, 0u, P6_1, P6_1_TCPWM0_LINE0}, 962 {1u, 1u, P6_2, P6_2_TCPWM0_LINE257}, 963 {0u, 1u, P6_3, P6_3_TCPWM0_LINE1}, 964 {1u, 2u, P6_4, P6_4_TCPWM0_LINE258}, 965 {0u, 2u, P6_5, P6_5_TCPWM0_LINE2}, 966 {1u, 3u, P6_6, P6_6_TCPWM0_LINE259}, 967 {0u, 3u, P6_7, P6_7_TCPWM0_LINE3}, 968 {1u, 4u, P7_0, P7_0_TCPWM0_LINE260}, 969 {0u, 15u, P7_1, P7_1_TCPWM0_LINE15}, 970 {1u, 5u, P7_2, P7_2_TCPWM0_LINE261}, 971 {0u, 16u, P7_3, P7_3_TCPWM0_LINE16}, 972 {1u, 6u, P7_4, P7_4_TCPWM0_LINE262}, 973 {0u, 17u, P7_5, P7_5_TCPWM0_LINE17}, 974 {1u, 7u, P7_6, P7_6_TCPWM0_LINE263}, 975 {0u, 18u, P7_7, P7_7_TCPWM0_LINE18}, 976 {0u, 19u, P8_0, P8_0_TCPWM0_LINE19}, 977 {0u, 20u, P8_1, P8_1_TCPWM0_LINE20}, 978 {0u, 21u, P8_2, P8_2_TCPWM0_LINE21}, 979 {0u, 22u, P8_3, P8_3_TCPWM0_LINE22}, 980 {0u, 24u, P9_0, P9_0_TCPWM0_LINE24}, 981 {0u, 25u, P9_1, P9_1_TCPWM0_LINE25}, 982 {0u, 28u, P10_0, P10_0_TCPWM0_LINE28}, 983 {0u, 29u, P10_1, P10_1_TCPWM0_LINE29}, 984 {0u, 30u, P10_2, P10_2_TCPWM0_LINE30}, 985 {0u, 31u, P10_3, P10_3_TCPWM0_LINE31}, 986 {0u, 32u, P10_4, P10_4_TCPWM0_LINE32}, 987 {0u, 61u, P11_0, P11_0_TCPWM0_LINE61}, 988 {0u, 60u, P11_1, P11_1_TCPWM0_LINE60}, 989 {0u, 59u, P11_2, P11_2_TCPWM0_LINE59}, 990 {0u, 36u, P12_0, P12_0_TCPWM0_LINE36}, 991 {0u, 37u, P12_1, P12_1_TCPWM0_LINE37}, 992 {0u, 38u, P12_2, P12_2_TCPWM0_LINE38}, 993 {0u, 39u, P12_3, P12_3_TCPWM0_LINE39}, 994 {0u, 40u, P12_4, P12_4_TCPWM0_LINE40}, 995 {0u, 41u, P12_5, P12_5_TCPWM0_LINE41}, 996 {1u, 8u, P13_0, P13_0_TCPWM0_LINE264}, 997 {0u, 44u, P13_1, P13_1_TCPWM0_LINE44}, 998 {1u, 9u, P13_2, P13_2_TCPWM0_LINE265}, 999 {0u, 45u, P13_3, P13_3_TCPWM0_LINE45}, 1000 {1u, 10u, P13_4, P13_4_TCPWM0_LINE266}, 1001 {2u, 4u, P13_4, P13_4_TCPWM0_LINE516}, 1002 {0u, 46u, P13_5, P13_5_TCPWM0_LINE46}, 1003 {1u, 11u, P13_6, P13_6_TCPWM0_LINE267}, 1004 {2u, 5u, P13_6, P13_6_TCPWM0_LINE517}, 1005 {0u, 47u, P13_7, P13_7_TCPWM0_LINE47}, 1006 {0u, 48u, P14_0, P14_0_TCPWM0_LINE48}, 1007 {2u, 6u, P14_0, P14_0_TCPWM0_LINE518}, 1008 {0u, 49u, P14_1, P14_1_TCPWM0_LINE49}, 1009 {0u, 52u, P14_4, P14_4_TCPWM0_LINE52}, 1010 {0u, 53u, P14_5, P14_5_TCPWM0_LINE53}, 1011 {0u, 56u, P15_0, P15_0_TCPWM0_LINE56}, 1012 {0u, 57u, P15_1, P15_1_TCPWM0_LINE57}, 1013 {0u, 58u, P15_2, P15_2_TCPWM0_LINE58}, 1014 {0u, 59u, P15_3, P15_3_TCPWM0_LINE59}, 1015 {0u, 61u, P17_0, P17_0_TCPWM0_LINE61}, 1016 {0u, 60u, P17_1, P17_1_TCPWM0_LINE60}, 1017 {0u, 59u, P17_2, P17_2_TCPWM0_LINE59}, 1018 {0u, 58u, P17_3, P17_3_TCPWM0_LINE58}, 1019 {2u, 3u, P17_3, P17_3_TCPWM0_LINE515}, 1020 {0u, 57u, P17_4, P17_4_TCPWM0_LINE57}, 1021 {1u, 6u, P18_0, P18_0_TCPWM0_LINE262}, 1022 {2u, 0u, P18_0, P18_0_TCPWM0_LINE512}, 1023 {1u, 7u, P18_1, P18_1_TCPWM0_LINE263}, 1024 {0u, 55u, P18_2, P18_2_TCPWM0_LINE55}, 1025 {2u, 1u, P18_2, P18_2_TCPWM0_LINE513}, 1026 {0u, 54u, P18_3, P18_3_TCPWM0_LINE54}, 1027 {0u, 53u, P18_4, P18_4_TCPWM0_LINE53}, 1028 {2u, 2u, P18_4, P18_4_TCPWM0_LINE514}, 1029 {0u, 52u, P18_5, P18_5_TCPWM0_LINE52}, 1030 {0u, 51u, P18_6, P18_6_TCPWM0_LINE51}, 1031 {2u, 3u, P18_6, P18_6_TCPWM0_LINE515}, 1032 {0u, 50u, P18_7, P18_7_TCPWM0_LINE50}, 1033 {1u, 3u, P19_0, P19_0_TCPWM0_LINE259}, 1034 {0u, 26u, P19_1, P19_1_TCPWM0_LINE26}, 1035 {0u, 27u, P19_2, P19_2_TCPWM0_LINE27}, 1036 {0u, 28u, P19_3, P19_3_TCPWM0_LINE28}, 1037 {0u, 29u, P19_4, P19_4_TCPWM0_LINE29}, 1038 {0u, 30u, P20_0, P20_0_TCPWM0_LINE30}, 1039 {0u, 49u, P20_1, P20_1_TCPWM0_LINE49}, 1040 {0u, 48u, P20_2, P20_2_TCPWM0_LINE48}, 1041 {0u, 47u, P20_3, P20_3_TCPWM0_LINE47}, 1042 {0u, 42u, P21_0, P21_0_TCPWM0_LINE42}, 1043 {0u, 41u, P21_1, P21_1_TCPWM0_LINE41}, 1044 {0u, 40u, P21_2, P21_2_TCPWM0_LINE40}, 1045 {0u, 39u, P21_3, P21_3_TCPWM0_LINE39}, 1046 {0u, 34u, P21_5, P21_5_TCPWM0_LINE34}, 1047 {0u, 37u, P21_5, P21_5_TCPWM0_LINE37}, 1048 {0u, 36u, P21_6, P21_6_TCPWM0_LINE36}, 1049 {0u, 33u, P22_1, P22_1_TCPWM0_LINE33}, 1050 {0u, 32u, P22_2, P22_2_TCPWM0_LINE32}, 1051 {0u, 31u, P22_3, P22_3_TCPWM0_LINE31}, 1052 {0u, 30u, P22_4, P22_4_TCPWM0_LINE30}, 1053 {0u, 29u, P22_5, P22_5_TCPWM0_LINE29}, 1054 {0u, 28u, P22_6, P22_6_TCPWM0_LINE28}, 1055 {1u, 8u, P23_0, P23_0_TCPWM0_LINE264}, 1056 {1u, 9u, P23_1, P23_1_TCPWM0_LINE265}, 1057 {1u, 11u, P23_3, P23_3_TCPWM0_LINE267}, 1058 {0u, 25u, P23_4, P23_4_TCPWM0_LINE25}, 1059 {0u, 24u, P23_5, P23_5_TCPWM0_LINE24}, 1060 {0u, 23u, P23_6, P23_6_TCPWM0_LINE23}, 1061 {0u, 22u, P23_7, P23_7_TCPWM0_LINE22}, 1062 }; 1063 1064 /* Connections for: tcpwm_line_compl */ 1065 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[128] = { 1066 {0u, 22u, P0_0, P0_0_TCPWM0_LINE_COMPL22}, 1067 {0u, 18u, P0_1, P0_1_TCPWM0_LINE_COMPL18}, 1068 {0u, 17u, P0_2, P0_2_TCPWM0_LINE_COMPL17}, 1069 {0u, 14u, P0_3, P0_3_TCPWM0_LINE_COMPL14}, 1070 {0u, 13u, P1_0, P1_0_TCPWM0_LINE_COMPL13}, 1071 {0u, 12u, P1_1, P1_1_TCPWM0_LINE_COMPL12}, 1072 {0u, 8u, P2_0, P2_0_TCPWM0_LINE_COMPL8}, 1073 {0u, 7u, P2_1, P2_1_TCPWM0_LINE_COMPL7}, 1074 {0u, 6u, P2_2, P2_2_TCPWM0_LINE_COMPL6}, 1075 {0u, 5u, P2_3, P2_3_TCPWM0_LINE_COMPL5}, 1076 {0u, 4u, P2_4, P2_4_TCPWM0_LINE_COMPL4}, 1077 {2u, 4u, P2_4, P2_4_TCPWM0_LINE_COMPL516}, 1078 {0u, 2u, P3_0, P3_0_TCPWM0_LINE_COMPL2}, 1079 {2u, 6u, P3_0, P3_0_TCPWM0_LINE_COMPL518}, 1080 {0u, 1u, P3_1, P3_1_TCPWM0_LINE_COMPL1}, 1081 {2u, 7u, P3_1, P3_1_TCPWM0_LINE_COMPL519}, 1082 {0u, 0u, P3_2, P3_2_TCPWM0_LINE_COMPL0}, 1083 {1u, 3u, P3_3, P3_3_TCPWM0_LINE_COMPL259}, 1084 {1u, 2u, P3_4, P3_4_TCPWM0_LINE_COMPL258}, 1085 {1u, 0u, P4_0, P4_0_TCPWM0_LINE_COMPL256}, 1086 {0u, 4u, P4_1, P4_1_TCPWM0_LINE_COMPL4}, 1087 {0u, 8u, P5_0, P5_0_TCPWM0_LINE_COMPL8}, 1088 {0u, 9u, P5_1, P5_1_TCPWM0_LINE_COMPL9}, 1089 {0u, 10u, P5_2, P5_2_TCPWM0_LINE_COMPL10}, 1090 {0u, 11u, P5_3, P5_3_TCPWM0_LINE_COMPL11}, 1091 {0u, 12u, P5_4, P5_4_TCPWM0_LINE_COMPL12}, 1092 {0u, 14u, P6_0, P6_0_TCPWM0_LINE_COMPL14}, 1093 {1u, 0u, P6_1, P6_1_TCPWM0_LINE_COMPL256}, 1094 {0u, 0u, P6_2, P6_2_TCPWM0_LINE_COMPL0}, 1095 {1u, 1u, P6_3, P6_3_TCPWM0_LINE_COMPL257}, 1096 {0u, 1u, P6_4, P6_4_TCPWM0_LINE_COMPL1}, 1097 {1u, 2u, P6_5, P6_5_TCPWM0_LINE_COMPL258}, 1098 {0u, 2u, P6_6, P6_6_TCPWM0_LINE_COMPL2}, 1099 {1u, 3u, P6_7, P6_7_TCPWM0_LINE_COMPL259}, 1100 {0u, 3u, P7_0, P7_0_TCPWM0_LINE_COMPL3}, 1101 {1u, 4u, P7_1, P7_1_TCPWM0_LINE_COMPL260}, 1102 {0u, 15u, P7_2, P7_2_TCPWM0_LINE_COMPL15}, 1103 {1u, 5u, P7_3, P7_3_TCPWM0_LINE_COMPL261}, 1104 {0u, 16u, P7_4, P7_4_TCPWM0_LINE_COMPL16}, 1105 {1u, 6u, P7_5, P7_5_TCPWM0_LINE_COMPL262}, 1106 {0u, 17u, P7_6, P7_6_TCPWM0_LINE_COMPL17}, 1107 {1u, 7u, P7_7, P7_7_TCPWM0_LINE_COMPL263}, 1108 {0u, 18u, P8_0, P8_0_TCPWM0_LINE_COMPL18}, 1109 {0u, 19u, P8_1, P8_1_TCPWM0_LINE_COMPL19}, 1110 {0u, 20u, P8_2, P8_2_TCPWM0_LINE_COMPL20}, 1111 {0u, 21u, P8_3, P8_3_TCPWM0_LINE_COMPL21}, 1112 {0u, 23u, P9_0, P9_0_TCPWM0_LINE_COMPL23}, 1113 {0u, 24u, P9_1, P9_1_TCPWM0_LINE_COMPL24}, 1114 {0u, 27u, P10_0, P10_0_TCPWM0_LINE_COMPL27}, 1115 {0u, 28u, P10_1, P10_1_TCPWM0_LINE_COMPL28}, 1116 {0u, 29u, P10_2, P10_2_TCPWM0_LINE_COMPL29}, 1117 {0u, 30u, P10_3, P10_3_TCPWM0_LINE_COMPL30}, 1118 {0u, 31u, P10_4, P10_4_TCPWM0_LINE_COMPL31}, 1119 {0u, 62u, P11_0, P11_0_TCPWM0_LINE_COMPL62}, 1120 {0u, 61u, P11_1, P11_1_TCPWM0_LINE_COMPL61}, 1121 {0u, 60u, P11_2, P11_2_TCPWM0_LINE_COMPL60}, 1122 {0u, 35u, P12_0, P12_0_TCPWM0_LINE_COMPL35}, 1123 {0u, 36u, P12_1, P12_1_TCPWM0_LINE_COMPL36}, 1124 {0u, 37u, P12_2, P12_2_TCPWM0_LINE_COMPL37}, 1125 {0u, 38u, P12_3, P12_3_TCPWM0_LINE_COMPL38}, 1126 {0u, 39u, P12_4, P12_4_TCPWM0_LINE_COMPL39}, 1127 {0u, 40u, P12_5, P12_5_TCPWM0_LINE_COMPL40}, 1128 {0u, 43u, P13_0, P13_0_TCPWM0_LINE_COMPL43}, 1129 {1u, 8u, P13_1, P13_1_TCPWM0_LINE_COMPL264}, 1130 {0u, 44u, P13_2, P13_2_TCPWM0_LINE_COMPL44}, 1131 {1u, 9u, P13_3, P13_3_TCPWM0_LINE_COMPL265}, 1132 {0u, 45u, P13_4, P13_4_TCPWM0_LINE_COMPL45}, 1133 {1u, 10u, P13_5, P13_5_TCPWM0_LINE_COMPL266}, 1134 {2u, 4u, P13_5, P13_5_TCPWM0_LINE_COMPL516}, 1135 {0u, 46u, P13_6, P13_6_TCPWM0_LINE_COMPL46}, 1136 {1u, 11u, P13_7, P13_7_TCPWM0_LINE_COMPL267}, 1137 {2u, 5u, P13_7, P13_7_TCPWM0_LINE_COMPL517}, 1138 {0u, 47u, P14_0, P14_0_TCPWM0_LINE_COMPL47}, 1139 {0u, 48u, P14_1, P14_1_TCPWM0_LINE_COMPL48}, 1140 {2u, 6u, P14_1, P14_1_TCPWM0_LINE_COMPL518}, 1141 {0u, 51u, P14_4, P14_4_TCPWM0_LINE_COMPL51}, 1142 {0u, 52u, P14_5, P14_5_TCPWM0_LINE_COMPL52}, 1143 {0u, 55u, P15_0, P15_0_TCPWM0_LINE_COMPL55}, 1144 {0u, 56u, P15_1, P15_1_TCPWM0_LINE_COMPL56}, 1145 {0u, 57u, P15_2, P15_2_TCPWM0_LINE_COMPL57}, 1146 {0u, 58u, P15_3, P15_3_TCPWM0_LINE_COMPL58}, 1147 {0u, 62u, P17_0, P17_0_TCPWM0_LINE_COMPL62}, 1148 {0u, 61u, P17_1, P17_1_TCPWM0_LINE_COMPL61}, 1149 {0u, 60u, P17_2, P17_2_TCPWM0_LINE_COMPL60}, 1150 {0u, 59u, P17_3, P17_3_TCPWM0_LINE_COMPL59}, 1151 {0u, 58u, P17_4, P17_4_TCPWM0_LINE_COMPL58}, 1152 {2u, 3u, P17_4, P17_4_TCPWM0_LINE_COMPL515}, 1153 {1u, 5u, P18_0, P18_0_TCPWM0_LINE_COMPL261}, 1154 {1u, 6u, P18_1, P18_1_TCPWM0_LINE_COMPL262}, 1155 {2u, 0u, P18_1, P18_1_TCPWM0_LINE_COMPL512}, 1156 {1u, 7u, P18_2, P18_2_TCPWM0_LINE_COMPL263}, 1157 {0u, 55u, P18_3, P18_3_TCPWM0_LINE_COMPL55}, 1158 {2u, 1u, P18_3, P18_3_TCPWM0_LINE_COMPL513}, 1159 {0u, 54u, P18_4, P18_4_TCPWM0_LINE_COMPL54}, 1160 {0u, 53u, P18_5, P18_5_TCPWM0_LINE_COMPL53}, 1161 {2u, 2u, P18_5, P18_5_TCPWM0_LINE_COMPL514}, 1162 {0u, 52u, P18_6, P18_6_TCPWM0_LINE_COMPL52}, 1163 {0u, 51u, P18_7, P18_7_TCPWM0_LINE_COMPL51}, 1164 {2u, 3u, P18_7, P18_7_TCPWM0_LINE_COMPL515}, 1165 {0u, 50u, P19_0, P19_0_TCPWM0_LINE_COMPL50}, 1166 {1u, 3u, P19_1, P19_1_TCPWM0_LINE_COMPL259}, 1167 {0u, 26u, P19_2, P19_2_TCPWM0_LINE_COMPL26}, 1168 {0u, 27u, P19_3, P19_3_TCPWM0_LINE_COMPL27}, 1169 {0u, 28u, P19_4, P19_4_TCPWM0_LINE_COMPL28}, 1170 {0u, 29u, P20_0, P20_0_TCPWM0_LINE_COMPL29}, 1171 {0u, 30u, P20_1, P20_1_TCPWM0_LINE_COMPL30}, 1172 {0u, 49u, P20_2, P20_2_TCPWM0_LINE_COMPL49}, 1173 {0u, 48u, P20_3, P20_3_TCPWM0_LINE_COMPL48}, 1174 {0u, 43u, P21_0, P21_0_TCPWM0_LINE_COMPL43}, 1175 {0u, 42u, P21_1, P21_1_TCPWM0_LINE_COMPL42}, 1176 {0u, 41u, P21_2, P21_2_TCPWM0_LINE_COMPL41}, 1177 {0u, 40u, P21_3, P21_3_TCPWM0_LINE_COMPL40}, 1178 {0u, 35u, P21_5, P21_5_TCPWM0_LINE_COMPL35}, 1179 {0u, 38u, P21_5, P21_5_TCPWM0_LINE_COMPL38}, 1180 {0u, 37u, P21_6, P21_6_TCPWM0_LINE_COMPL37}, 1181 {0u, 34u, P22_1, P22_1_TCPWM0_LINE_COMPL34}, 1182 {0u, 33u, P22_2, P22_2_TCPWM0_LINE_COMPL33}, 1183 {0u, 32u, P22_3, P22_3_TCPWM0_LINE_COMPL32}, 1184 {0u, 31u, P22_4, P22_4_TCPWM0_LINE_COMPL31}, 1185 {0u, 30u, P22_5, P22_5_TCPWM0_LINE_COMPL30}, 1186 {0u, 29u, P22_6, P22_6_TCPWM0_LINE_COMPL29}, 1187 {0u, 27u, P23_0, P23_0_TCPWM0_LINE_COMPL27}, 1188 {1u, 8u, P23_1, P23_1_TCPWM0_LINE_COMPL264}, 1189 {1u, 10u, P23_3, P23_3_TCPWM0_LINE_COMPL266}, 1190 {1u, 11u, P23_4, P23_4_TCPWM0_LINE_COMPL267}, 1191 {0u, 25u, P23_5, P23_5_TCPWM0_LINE_COMPL25}, 1192 {0u, 24u, P23_6, P23_6_TCPWM0_LINE_COMPL24}, 1193 {0u, 23u, P23_7, P23_7_TCPWM0_LINE_COMPL23}, 1194 }; 1195 1196 /* Connections for: tcpwm_tr_one_cnt_in */ 1197 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_tr_one_cnt_in[255] = { 1198 {0u, 54u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN54}, 1199 {0u, 67u, P0_0, P0_0_TCPWM0_TR_ONE_CNT_IN67}, 1200 {0u, 51u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN51}, 1201 {0u, 55u, P0_1, P0_1_TCPWM0_TR_ONE_CNT_IN55}, 1202 {0u, 42u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN42}, 1203 {0u, 52u, P0_2, P0_2_TCPWM0_TR_ONE_CNT_IN52}, 1204 {0u, 39u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN39}, 1205 {0u, 43u, P0_3, P0_3_TCPWM0_TR_ONE_CNT_IN43}, 1206 {0u, 36u, P1_0, P1_0_TCPWM0_TR_ONE_CNT_IN36}, 1207 {0u, 40u, P1_0, P1_0_TCPWM0_TR_ONE_CNT_IN40}, 1208 {0u, 33u, P1_1, P1_1_TCPWM0_TR_ONE_CNT_IN33}, 1209 {0u, 37u, P1_1, P1_1_TCPWM0_TR_ONE_CNT_IN37}, 1210 {0u, 21u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN21}, 1211 {0u, 25u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN25}, 1212 {6u, 12u, P2_0, P2_0_TCPWM0_TR_ONE_CNT_IN1548}, 1213 {0u, 18u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN18}, 1214 {0u, 22u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN22}, 1215 {6u, 15u, P2_1, P2_1_TCPWM0_TR_ONE_CNT_IN1551}, 1216 {0u, 15u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN15}, 1217 {0u, 19u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN19}, 1218 {6u, 18u, P2_2, P2_2_TCPWM0_TR_ONE_CNT_IN1554}, 1219 {0u, 12u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN12}, 1220 {0u, 16u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN16}, 1221 {6u, 21u, P2_3, P2_3_TCPWM0_TR_ONE_CNT_IN1557}, 1222 {0u, 9u, P2_4, P2_4_TCPWM0_TR_ONE_CNT_IN9}, 1223 {0u, 13u, P2_4, P2_4_TCPWM0_TR_ONE_CNT_IN13}, 1224 {0u, 3u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN3}, 1225 {0u, 7u, P3_0, P3_0_TCPWM0_TR_ONE_CNT_IN7}, 1226 {0u, 0u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN0}, 1227 {0u, 4u, P3_1, P3_1_TCPWM0_TR_ONE_CNT_IN4}, 1228 {0u, 1u, P3_2, P3_2_TCPWM0_TR_ONE_CNT_IN1}, 1229 {3u, 9u, P3_2, P3_2_TCPWM0_TR_ONE_CNT_IN777}, 1230 {6u, 13u, P3_2, P3_2_TCPWM0_TR_ONE_CNT_IN1549}, 1231 {3u, 6u, P3_3, P3_3_TCPWM0_TR_ONE_CNT_IN774}, 1232 {3u, 10u, P3_3, P3_3_TCPWM0_TR_ONE_CNT_IN778}, 1233 {6u, 16u, P3_3, P3_3_TCPWM0_TR_ONE_CNT_IN1552}, 1234 {3u, 3u, P3_4, P3_4_TCPWM0_TR_ONE_CNT_IN771}, 1235 {3u, 7u, P3_4, P3_4_TCPWM0_TR_ONE_CNT_IN775}, 1236 {6u, 19u, P3_4, P3_4_TCPWM0_TR_ONE_CNT_IN1555}, 1237 {0u, 12u, P4_0, P4_0_TCPWM0_TR_ONE_CNT_IN12}, 1238 {3u, 1u, P4_0, P4_0_TCPWM0_TR_ONE_CNT_IN769}, 1239 {0u, 13u, P4_1, P4_1_TCPWM0_TR_ONE_CNT_IN13}, 1240 {0u, 15u, P4_1, P4_1_TCPWM0_TR_ONE_CNT_IN15}, 1241 {0u, 25u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN25}, 1242 {0u, 27u, P5_0, P5_0_TCPWM0_TR_ONE_CNT_IN27}, 1243 {0u, 28u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN28}, 1244 {0u, 30u, P5_1, P5_1_TCPWM0_TR_ONE_CNT_IN30}, 1245 {0u, 31u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN31}, 1246 {0u, 33u, P5_2, P5_2_TCPWM0_TR_ONE_CNT_IN33}, 1247 {0u, 34u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN34}, 1248 {0u, 36u, P5_3, P5_3_TCPWM0_TR_ONE_CNT_IN36}, 1249 {0u, 37u, P5_4, P5_4_TCPWM0_TR_ONE_CNT_IN37}, 1250 {0u, 39u, P5_4, P5_4_TCPWM0_TR_ONE_CNT_IN39}, 1251 {0u, 43u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN43}, 1252 {3u, 0u, P6_0, P6_0_TCPWM0_TR_ONE_CNT_IN768}, 1253 {0u, 0u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN0}, 1254 {3u, 1u, P6_1, P6_1_TCPWM0_TR_ONE_CNT_IN769}, 1255 {0u, 1u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN1}, 1256 {3u, 3u, P6_2, P6_2_TCPWM0_TR_ONE_CNT_IN771}, 1257 {0u, 3u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN3}, 1258 {3u, 4u, P6_3, P6_3_TCPWM0_TR_ONE_CNT_IN772}, 1259 {0u, 4u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN4}, 1260 {3u, 6u, P6_4, P6_4_TCPWM0_TR_ONE_CNT_IN774}, 1261 {0u, 6u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN6}, 1262 {3u, 7u, P6_5, P6_5_TCPWM0_TR_ONE_CNT_IN775}, 1263 {0u, 7u, P6_6, P6_6_TCPWM0_TR_ONE_CNT_IN7}, 1264 {3u, 9u, P6_6, P6_6_TCPWM0_TR_ONE_CNT_IN777}, 1265 {0u, 9u, P6_7, P6_7_TCPWM0_TR_ONE_CNT_IN9}, 1266 {3u, 10u, P6_7, P6_7_TCPWM0_TR_ONE_CNT_IN778}, 1267 {0u, 10u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN10}, 1268 {3u, 12u, P7_0, P7_0_TCPWM0_TR_ONE_CNT_IN780}, 1269 {0u, 45u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN45}, 1270 {3u, 13u, P7_1, P7_1_TCPWM0_TR_ONE_CNT_IN781}, 1271 {0u, 46u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN46}, 1272 {3u, 15u, P7_2, P7_2_TCPWM0_TR_ONE_CNT_IN783}, 1273 {0u, 48u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN48}, 1274 {3u, 16u, P7_3, P7_3_TCPWM0_TR_ONE_CNT_IN784}, 1275 {0u, 49u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN49}, 1276 {3u, 18u, P7_4, P7_4_TCPWM0_TR_ONE_CNT_IN786}, 1277 {0u, 51u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN51}, 1278 {3u, 19u, P7_5, P7_5_TCPWM0_TR_ONE_CNT_IN787}, 1279 {0u, 52u, P7_6, P7_6_TCPWM0_TR_ONE_CNT_IN52}, 1280 {3u, 21u, P7_6, P7_6_TCPWM0_TR_ONE_CNT_IN789}, 1281 {0u, 54u, P7_7, P7_7_TCPWM0_TR_ONE_CNT_IN54}, 1282 {3u, 22u, P7_7, P7_7_TCPWM0_TR_ONE_CNT_IN790}, 1283 {0u, 55u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN55}, 1284 {0u, 57u, P8_0, P8_0_TCPWM0_TR_ONE_CNT_IN57}, 1285 {0u, 58u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN58}, 1286 {0u, 60u, P8_1, P8_1_TCPWM0_TR_ONE_CNT_IN60}, 1287 {0u, 61u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN61}, 1288 {0u, 63u, P8_2, P8_2_TCPWM0_TR_ONE_CNT_IN63}, 1289 {0u, 64u, P8_3, P8_3_TCPWM0_TR_ONE_CNT_IN64}, 1290 {0u, 66u, P8_3, P8_3_TCPWM0_TR_ONE_CNT_IN66}, 1291 {0u, 70u, P9_0, P9_0_TCPWM0_TR_ONE_CNT_IN70}, 1292 {0u, 72u, P9_0, P9_0_TCPWM0_TR_ONE_CNT_IN72}, 1293 {0u, 73u, P9_1, P9_1_TCPWM0_TR_ONE_CNT_IN73}, 1294 {0u, 75u, P9_1, P9_1_TCPWM0_TR_ONE_CNT_IN75}, 1295 {0u, 82u, P10_0, P10_0_TCPWM0_TR_ONE_CNT_IN82}, 1296 {0u, 84u, P10_0, P10_0_TCPWM0_TR_ONE_CNT_IN84}, 1297 {0u, 85u, P10_1, P10_1_TCPWM0_TR_ONE_CNT_IN85}, 1298 {0u, 87u, P10_1, P10_1_TCPWM0_TR_ONE_CNT_IN87}, 1299 {0u, 88u, P10_2, P10_2_TCPWM0_TR_ONE_CNT_IN88}, 1300 {0u, 90u, P10_2, P10_2_TCPWM0_TR_ONE_CNT_IN90}, 1301 {0u, 91u, P10_3, P10_3_TCPWM0_TR_ONE_CNT_IN91}, 1302 {0u, 93u, P10_3, P10_3_TCPWM0_TR_ONE_CNT_IN93}, 1303 {0u, 94u, P10_4, P10_4_TCPWM0_TR_ONE_CNT_IN94}, 1304 {0u, 96u, P10_4, P10_4_TCPWM0_TR_ONE_CNT_IN96}, 1305 {0u, 183u, P11_0, P11_0_TCPWM0_TR_ONE_CNT_IN183}, 1306 {0u, 187u, P11_0, P11_0_TCPWM0_TR_ONE_CNT_IN187}, 1307 {0u, 180u, P11_1, P11_1_TCPWM0_TR_ONE_CNT_IN180}, 1308 {0u, 184u, P11_1, P11_1_TCPWM0_TR_ONE_CNT_IN184}, 1309 {0u, 177u, P11_2, P11_2_TCPWM0_TR_ONE_CNT_IN177}, 1310 {0u, 181u, P11_2, P11_2_TCPWM0_TR_ONE_CNT_IN181}, 1311 {0u, 106u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN106}, 1312 {0u, 108u, P12_0, P12_0_TCPWM0_TR_ONE_CNT_IN108}, 1313 {0u, 109u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN109}, 1314 {0u, 111u, P12_1, P12_1_TCPWM0_TR_ONE_CNT_IN111}, 1315 {0u, 112u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN112}, 1316 {0u, 114u, P12_2, P12_2_TCPWM0_TR_ONE_CNT_IN114}, 1317 {0u, 115u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN115}, 1318 {0u, 117u, P12_3, P12_3_TCPWM0_TR_ONE_CNT_IN117}, 1319 {0u, 118u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN118}, 1320 {0u, 120u, P12_4, P12_4_TCPWM0_TR_ONE_CNT_IN120}, 1321 {0u, 121u, P12_5, P12_5_TCPWM0_TR_ONE_CNT_IN121}, 1322 {0u, 123u, P12_5, P12_5_TCPWM0_TR_ONE_CNT_IN123}, 1323 {0u, 130u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN130}, 1324 {3u, 24u, P13_0, P13_0_TCPWM0_TR_ONE_CNT_IN792}, 1325 {0u, 132u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN132}, 1326 {3u, 25u, P13_1, P13_1_TCPWM0_TR_ONE_CNT_IN793}, 1327 {0u, 133u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN133}, 1328 {3u, 27u, P13_2, P13_2_TCPWM0_TR_ONE_CNT_IN795}, 1329 {0u, 135u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN135}, 1330 {3u, 28u, P13_3, P13_3_TCPWM0_TR_ONE_CNT_IN796}, 1331 {0u, 136u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN136}, 1332 {3u, 30u, P13_4, P13_4_TCPWM0_TR_ONE_CNT_IN798}, 1333 {0u, 138u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN138}, 1334 {3u, 31u, P13_5, P13_5_TCPWM0_TR_ONE_CNT_IN799}, 1335 {0u, 139u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN139}, 1336 {3u, 33u, P13_6, P13_6_TCPWM0_TR_ONE_CNT_IN801}, 1337 {0u, 141u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN141}, 1338 {3u, 34u, P13_7, P13_7_TCPWM0_TR_ONE_CNT_IN802}, 1339 {0u, 142u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN142}, 1340 {0u, 144u, P14_0, P14_0_TCPWM0_TR_ONE_CNT_IN144}, 1341 {0u, 145u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN145}, 1342 {0u, 147u, P14_1, P14_1_TCPWM0_TR_ONE_CNT_IN147}, 1343 {0u, 154u, P14_4, P14_4_TCPWM0_TR_ONE_CNT_IN154}, 1344 {0u, 156u, P14_4, P14_4_TCPWM0_TR_ONE_CNT_IN156}, 1345 {6u, 12u, P14_4, P14_4_TCPWM0_TR_ONE_CNT_IN1548}, 1346 {0u, 157u, P14_5, P14_5_TCPWM0_TR_ONE_CNT_IN157}, 1347 {0u, 159u, P14_5, P14_5_TCPWM0_TR_ONE_CNT_IN159}, 1348 {6u, 13u, P14_5, P14_5_TCPWM0_TR_ONE_CNT_IN1549}, 1349 {0u, 166u, P15_0, P15_0_TCPWM0_TR_ONE_CNT_IN166}, 1350 {0u, 168u, P15_0, P15_0_TCPWM0_TR_ONE_CNT_IN168}, 1351 {6u, 18u, P15_0, P15_0_TCPWM0_TR_ONE_CNT_IN1554}, 1352 {0u, 169u, P15_1, P15_1_TCPWM0_TR_ONE_CNT_IN169}, 1353 {0u, 171u, P15_1, P15_1_TCPWM0_TR_ONE_CNT_IN171}, 1354 {6u, 19u, P15_1, P15_1_TCPWM0_TR_ONE_CNT_IN1555}, 1355 {0u, 172u, P15_2, P15_2_TCPWM0_TR_ONE_CNT_IN172}, 1356 {0u, 174u, P15_2, P15_2_TCPWM0_TR_ONE_CNT_IN174}, 1357 {6u, 21u, P15_2, P15_2_TCPWM0_TR_ONE_CNT_IN1557}, 1358 {0u, 175u, P15_3, P15_3_TCPWM0_TR_ONE_CNT_IN175}, 1359 {0u, 177u, P15_3, P15_3_TCPWM0_TR_ONE_CNT_IN177}, 1360 {6u, 22u, P15_3, P15_3_TCPWM0_TR_ONE_CNT_IN1558}, 1361 {0u, 183u, P17_0, P17_0_TCPWM0_TR_ONE_CNT_IN183}, 1362 {0u, 187u, P17_0, P17_0_TCPWM0_TR_ONE_CNT_IN187}, 1363 {0u, 180u, P17_1, P17_1_TCPWM0_TR_ONE_CNT_IN180}, 1364 {0u, 184u, P17_1, P17_1_TCPWM0_TR_ONE_CNT_IN184}, 1365 {0u, 177u, P17_2, P17_2_TCPWM0_TR_ONE_CNT_IN177}, 1366 {0u, 181u, P17_2, P17_2_TCPWM0_TR_ONE_CNT_IN181}, 1367 {0u, 174u, P17_3, P17_3_TCPWM0_TR_ONE_CNT_IN174}, 1368 {0u, 178u, P17_3, P17_3_TCPWM0_TR_ONE_CNT_IN178}, 1369 {0u, 171u, P17_4, P17_4_TCPWM0_TR_ONE_CNT_IN171}, 1370 {0u, 175u, P17_4, P17_4_TCPWM0_TR_ONE_CNT_IN175}, 1371 {3u, 16u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN784}, 1372 {3u, 18u, P18_0, P18_0_TCPWM0_TR_ONE_CNT_IN786}, 1373 {3u, 19u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN787}, 1374 {3u, 21u, P18_1, P18_1_TCPWM0_TR_ONE_CNT_IN789}, 1375 {0u, 165u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN165}, 1376 {3u, 22u, P18_2, P18_2_TCPWM0_TR_ONE_CNT_IN790}, 1377 {0u, 162u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN162}, 1378 {0u, 166u, P18_3, P18_3_TCPWM0_TR_ONE_CNT_IN166}, 1379 {0u, 159u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN159}, 1380 {0u, 163u, P18_4, P18_4_TCPWM0_TR_ONE_CNT_IN163}, 1381 {0u, 156u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN156}, 1382 {0u, 160u, P18_5, P18_5_TCPWM0_TR_ONE_CNT_IN160}, 1383 {0u, 153u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN153}, 1384 {0u, 157u, P18_6, P18_6_TCPWM0_TR_ONE_CNT_IN157}, 1385 {0u, 150u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN150}, 1386 {0u, 154u, P18_7, P18_7_TCPWM0_TR_ONE_CNT_IN154}, 1387 {0u, 151u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN151}, 1388 {3u, 9u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN777}, 1389 {6u, 0u, P19_0, P19_0_TCPWM0_TR_ONE_CNT_IN1536}, 1390 {0u, 78u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN78}, 1391 {3u, 10u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN778}, 1392 {6u, 1u, P19_1, P19_1_TCPWM0_TR_ONE_CNT_IN1537}, 1393 {0u, 79u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN79}, 1394 {0u, 81u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN81}, 1395 {6u, 3u, P19_2, P19_2_TCPWM0_TR_ONE_CNT_IN1539}, 1396 {0u, 82u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN82}, 1397 {0u, 84u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN84}, 1398 {6u, 4u, P19_3, P19_3_TCPWM0_TR_ONE_CNT_IN1540}, 1399 {0u, 85u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN85}, 1400 {0u, 87u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN87}, 1401 {6u, 6u, P19_4, P19_4_TCPWM0_TR_ONE_CNT_IN1542}, 1402 {0u, 88u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN88}, 1403 {0u, 90u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN90}, 1404 {6u, 7u, P20_0, P20_0_TCPWM0_TR_ONE_CNT_IN1543}, 1405 {0u, 91u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN91}, 1406 {0u, 147u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN147}, 1407 {6u, 9u, P20_1, P20_1_TCPWM0_TR_ONE_CNT_IN1545}, 1408 {0u, 144u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN144}, 1409 {0u, 148u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN148}, 1410 {6u, 10u, P20_2, P20_2_TCPWM0_TR_ONE_CNT_IN1546}, 1411 {0u, 141u, P20_3, P20_3_TCPWM0_TR_ONE_CNT_IN141}, 1412 {0u, 145u, P20_3, P20_3_TCPWM0_TR_ONE_CNT_IN145}, 1413 {0u, 126u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN126}, 1414 {0u, 130u, P21_0, P21_0_TCPWM0_TR_ONE_CNT_IN130}, 1415 {0u, 123u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN123}, 1416 {0u, 127u, P21_1, P21_1_TCPWM0_TR_ONE_CNT_IN127}, 1417 {0u, 120u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN120}, 1418 {0u, 124u, P21_2, P21_2_TCPWM0_TR_ONE_CNT_IN124}, 1419 {0u, 117u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN117}, 1420 {0u, 121u, P21_3, P21_3_TCPWM0_TR_ONE_CNT_IN121}, 1421 {0u, 102u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN102}, 1422 {0u, 106u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN106}, 1423 {0u, 111u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN111}, 1424 {0u, 115u, P21_5, P21_5_TCPWM0_TR_ONE_CNT_IN115}, 1425 {0u, 108u, P21_6, P21_6_TCPWM0_TR_ONE_CNT_IN108}, 1426 {0u, 112u, P21_6, P21_6_TCPWM0_TR_ONE_CNT_IN112}, 1427 {0u, 99u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN99}, 1428 {0u, 103u, P22_1, P22_1_TCPWM0_TR_ONE_CNT_IN103}, 1429 {0u, 96u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN96}, 1430 {0u, 100u, P22_2, P22_2_TCPWM0_TR_ONE_CNT_IN100}, 1431 {0u, 93u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN93}, 1432 {0u, 97u, P22_3, P22_3_TCPWM0_TR_ONE_CNT_IN97}, 1433 {0u, 90u, P22_4, P22_4_TCPWM0_TR_ONE_CNT_IN90}, 1434 {0u, 94u, P22_4, P22_4_TCPWM0_TR_ONE_CNT_IN94}, 1435 {0u, 87u, P22_5, P22_5_TCPWM0_TR_ONE_CNT_IN87}, 1436 {0u, 91u, P22_5, P22_5_TCPWM0_TR_ONE_CNT_IN91}, 1437 {0u, 84u, P22_6, P22_6_TCPWM0_TR_ONE_CNT_IN84}, 1438 {0u, 88u, P22_6, P22_6_TCPWM0_TR_ONE_CNT_IN88}, 1439 {0u, 82u, P23_0, P23_0_TCPWM0_TR_ONE_CNT_IN82}, 1440 {3u, 24u, P23_0, P23_0_TCPWM0_TR_ONE_CNT_IN792}, 1441 {3u, 25u, P23_1, P23_1_TCPWM0_TR_ONE_CNT_IN793}, 1442 {3u, 27u, P23_1, P23_1_TCPWM0_TR_ONE_CNT_IN795}, 1443 {3u, 31u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN799}, 1444 {3u, 33u, P23_3, P23_3_TCPWM0_TR_ONE_CNT_IN801}, 1445 {0u, 75u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN75}, 1446 {3u, 34u, P23_4, P23_4_TCPWM0_TR_ONE_CNT_IN802}, 1447 {0u, 72u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN72}, 1448 {0u, 76u, P23_5, P23_5_TCPWM0_TR_ONE_CNT_IN76}, 1449 {0u, 69u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN69}, 1450 {0u, 73u, P23_6, P23_6_TCPWM0_TR_ONE_CNT_IN73}, 1451 {0u, 66u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN66}, 1452 {0u, 70u, P23_7, P23_7_TCPWM0_TR_ONE_CNT_IN70}, 1453 }; 1454 1455 #endif 1456
