1 /***************************************************************************//** 2 * \file cyhal_triggers_cyw20829a0.c 3 * 4 * \brief 5 * CYW20829A0 family HAL triggers header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(CY_DEVICE_CYW20829) && (CY_SYSLIB_GET_SILICON_REV_ID == CY_SYSLIB_20829A0_SILICON_REV) 31 #include "triggers/cyhal_triggers_cyw20829a0.h" 32 33 const uint16_t cyhal_sources_per_mux[15] = 34 { 35 25, 54, 54, 46, 64, 3, 19, 2, 3, 3, 4, 5, 1, 1, 2, 36 }; 37 38 const bool cyhal_is_mux_1to1[15] = 39 { 40 false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, 41 }; 42 43 const _cyhal_trigger_source_cyw20829_t cyhal_mux0_sources[25] = 44 { 45 _CYHAL_TRIGGER_CPUSS_ZERO, 46 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, 47 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, 48 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, 49 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, 50 _CYHAL_TRIGGER_TCPWM0_TR_OUT00, 51 _CYHAL_TRIGGER_TCPWM0_TR_OUT10, 52 _CYHAL_TRIGGER_TCPWM0_TR_OUT01, 53 _CYHAL_TRIGGER_TCPWM0_TR_OUT11, 54 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0, 55 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1, 56 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2, 57 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3, 58 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4, 59 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5, 60 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6, 61 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7, 62 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, 63 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, 64 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DC, 65 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DATA, 66 _CYHAL_TRIGGER_TDM_TR_TX_REQ0, 67 _CYHAL_TRIGGER_TDM_TR_RX_REQ0, 68 _CYHAL_TRIGGER_PDM_TR_RX_REQ0, 69 _CYHAL_TRIGGER_PDM_TR_RX_REQ1, 70 }; 71 72 const _cyhal_trigger_source_cyw20829_t cyhal_mux1_sources[54] = 73 { 74 _CYHAL_TRIGGER_CPUSS_ZERO, 75 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, 76 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, 77 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, 78 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, 79 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, 80 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, 81 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, 82 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, 83 _CYHAL_TRIGGER_TCPWM0_TR_OUT00, 84 _CYHAL_TRIGGER_TCPWM0_TR_OUT10, 85 _CYHAL_TRIGGER_TCPWM0_TR_OUT01, 86 _CYHAL_TRIGGER_TCPWM0_TR_OUT11, 87 _CYHAL_TRIGGER_TCPWM0_TR_OUT0256, 88 _CYHAL_TRIGGER_TCPWM0_TR_OUT1256, 89 _CYHAL_TRIGGER_TCPWM0_TR_OUT0257, 90 _CYHAL_TRIGGER_TCPWM0_TR_OUT1257, 91 _CYHAL_TRIGGER_TCPWM0_TR_OUT0258, 92 _CYHAL_TRIGGER_TCPWM0_TR_OUT1258, 93 _CYHAL_TRIGGER_TCPWM0_TR_OUT0259, 94 _CYHAL_TRIGGER_TCPWM0_TR_OUT1259, 95 _CYHAL_TRIGGER_TCPWM0_TR_OUT0260, 96 _CYHAL_TRIGGER_TCPWM0_TR_OUT1260, 97 _CYHAL_TRIGGER_TCPWM0_TR_OUT0261, 98 _CYHAL_TRIGGER_TCPWM0_TR_OUT1261, 99 _CYHAL_TRIGGER_TCPWM0_TR_OUT0262, 100 _CYHAL_TRIGGER_TCPWM0_TR_OUT1262, 101 _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, 102 _CYHAL_TRIGGER_SCB0_TR_TX_REQ, 103 _CYHAL_TRIGGER_SCB0_TR_RX_REQ, 104 _CYHAL_TRIGGER_CPUSS_ZERO, 105 _CYHAL_TRIGGER_SCB1_TR_TX_REQ, 106 _CYHAL_TRIGGER_SCB1_TR_RX_REQ, 107 _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, 108 _CYHAL_TRIGGER_SCB2_TR_TX_REQ, 109 _CYHAL_TRIGGER_SCB2_TR_RX_REQ, 110 _CYHAL_TRIGGER_SMIF_TR_TX_REQ, 111 _CYHAL_TRIGGER_SMIF_TR_RX_REQ, 112 _CYHAL_TRIGGER_TDM_TR_TX_REQ0, 113 _CYHAL_TRIGGER_TDM_TR_RX_REQ0, 114 _CYHAL_TRIGGER_PDM_TR_RX_REQ0, 115 _CYHAL_TRIGGER_PDM_TR_RX_REQ1, 116 _CYHAL_TRIGGER_PDM_TR_RX_REQ_ALL, 117 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0, 118 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1, 119 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2, 120 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3, 121 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, 122 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, 123 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DC, 124 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DATA, 125 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, 126 _CYHAL_TRIGGER_BTSS_TR_TX_START, 127 _CYHAL_TRIGGER_BTSS_TR_RX_PACKET_SYNC, 128 }; 129 130 const _cyhal_trigger_source_cyw20829_t cyhal_mux2_sources[54] = 131 { 132 _CYHAL_TRIGGER_CPUSS_ZERO, 133 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, 134 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, 135 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, 136 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, 137 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, 138 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, 139 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, 140 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, 141 _CYHAL_TRIGGER_TCPWM0_TR_OUT00, 142 _CYHAL_TRIGGER_TCPWM0_TR_OUT10, 143 _CYHAL_TRIGGER_TCPWM0_TR_OUT01, 144 _CYHAL_TRIGGER_TCPWM0_TR_OUT11, 145 _CYHAL_TRIGGER_TCPWM0_TR_OUT0256, 146 _CYHAL_TRIGGER_TCPWM0_TR_OUT1256, 147 _CYHAL_TRIGGER_TCPWM0_TR_OUT0257, 148 _CYHAL_TRIGGER_TCPWM0_TR_OUT1257, 149 _CYHAL_TRIGGER_TCPWM0_TR_OUT0258, 150 _CYHAL_TRIGGER_TCPWM0_TR_OUT1258, 151 _CYHAL_TRIGGER_TCPWM0_TR_OUT0259, 152 _CYHAL_TRIGGER_TCPWM0_TR_OUT1259, 153 _CYHAL_TRIGGER_TCPWM0_TR_OUT0260, 154 _CYHAL_TRIGGER_TCPWM0_TR_OUT1260, 155 _CYHAL_TRIGGER_TCPWM0_TR_OUT0261, 156 _CYHAL_TRIGGER_TCPWM0_TR_OUT1261, 157 _CYHAL_TRIGGER_TCPWM0_TR_OUT0262, 158 _CYHAL_TRIGGER_TCPWM0_TR_OUT1262, 159 _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, 160 _CYHAL_TRIGGER_SCB0_TR_TX_REQ, 161 _CYHAL_TRIGGER_SCB0_TR_RX_REQ, 162 _CYHAL_TRIGGER_CPUSS_ZERO, 163 _CYHAL_TRIGGER_SCB1_TR_TX_REQ, 164 _CYHAL_TRIGGER_SCB1_TR_RX_REQ, 165 _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, 166 _CYHAL_TRIGGER_SCB2_TR_TX_REQ, 167 _CYHAL_TRIGGER_SCB2_TR_RX_REQ, 168 _CYHAL_TRIGGER_SMIF_TR_TX_REQ, 169 _CYHAL_TRIGGER_SMIF_TR_RX_REQ, 170 _CYHAL_TRIGGER_TDM_TR_TX_REQ0, 171 _CYHAL_TRIGGER_TDM_TR_RX_REQ0, 172 _CYHAL_TRIGGER_PDM_TR_RX_REQ0, 173 _CYHAL_TRIGGER_PDM_TR_RX_REQ1, 174 _CYHAL_TRIGGER_PDM_TR_RX_REQ_ALL, 175 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4, 176 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5, 177 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6, 178 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7, 179 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, 180 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, 181 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DC, 182 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DATA, 183 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, 184 _CYHAL_TRIGGER_BTSS_TR_TX_START, 185 _CYHAL_TRIGGER_BTSS_TR_RX_PACKET_SYNC, 186 }; 187 188 const _cyhal_trigger_source_cyw20829_t cyhal_mux3_sources[46] = 189 { 190 _CYHAL_TRIGGER_CPUSS_ZERO, 191 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, 192 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, 193 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, 194 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, 195 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, 196 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, 197 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, 198 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, 199 _CYHAL_TRIGGER_TCPWM0_TR_OUT00, 200 _CYHAL_TRIGGER_TCPWM0_TR_OUT10, 201 _CYHAL_TRIGGER_TCPWM0_TR_OUT01, 202 _CYHAL_TRIGGER_TCPWM0_TR_OUT11, 203 _CYHAL_TRIGGER_TCPWM0_TR_OUT0256, 204 _CYHAL_TRIGGER_TCPWM0_TR_OUT1256, 205 _CYHAL_TRIGGER_TCPWM0_TR_OUT0257, 206 _CYHAL_TRIGGER_TCPWM0_TR_OUT1257, 207 _CYHAL_TRIGGER_TCPWM0_TR_OUT0258, 208 _CYHAL_TRIGGER_TCPWM0_TR_OUT1258, 209 _CYHAL_TRIGGER_TCPWM0_TR_OUT0259, 210 _CYHAL_TRIGGER_TCPWM0_TR_OUT1259, 211 _CYHAL_TRIGGER_TCPWM0_TR_OUT0260, 212 _CYHAL_TRIGGER_TCPWM0_TR_OUT1260, 213 _CYHAL_TRIGGER_TCPWM0_TR_OUT0261, 214 _CYHAL_TRIGGER_TCPWM0_TR_OUT1261, 215 _CYHAL_TRIGGER_TCPWM0_TR_OUT0262, 216 _CYHAL_TRIGGER_TCPWM0_TR_OUT1262, 217 _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, 218 _CYHAL_TRIGGER_SCB0_TR_TX_REQ, 219 _CYHAL_TRIGGER_SCB0_TR_RX_REQ, 220 _CYHAL_TRIGGER_CPUSS_ZERO, 221 _CYHAL_TRIGGER_SCB1_TR_TX_REQ, 222 _CYHAL_TRIGGER_SCB1_TR_RX_REQ, 223 _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, 224 _CYHAL_TRIGGER_SCB2_TR_TX_REQ, 225 _CYHAL_TRIGGER_SCB2_TR_RX_REQ, 226 _CYHAL_TRIGGER_TDM_TR_TX_REQ0, 227 _CYHAL_TRIGGER_TDM_TR_RX_REQ0, 228 _CYHAL_TRIGGER_PDM_TR_RX_REQ0, 229 _CYHAL_TRIGGER_PDM_TR_RX_REQ1, 230 _CYHAL_TRIGGER_PDM_TR_RX_REQ_ALL, 231 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, 232 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, 233 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DC, 234 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DATA, 235 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, 236 }; 237 238 const _cyhal_trigger_source_cyw20829_t cyhal_mux4_sources[64] = 239 { 240 _CYHAL_TRIGGER_CPUSS_ZERO, 241 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, 242 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, 243 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, 244 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, 245 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, 246 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, 247 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, 248 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, 249 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, 250 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, 251 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, 252 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, 253 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, 254 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, 255 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, 256 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, 257 _CYHAL_TRIGGER_TCPWM0_TR_OUT00, 258 _CYHAL_TRIGGER_TCPWM0_TR_OUT10, 259 _CYHAL_TRIGGER_TCPWM0_TR_OUT01, 260 _CYHAL_TRIGGER_TCPWM0_TR_OUT11, 261 _CYHAL_TRIGGER_TCPWM0_TR_OUT0256, 262 _CYHAL_TRIGGER_TCPWM0_TR_OUT1256, 263 _CYHAL_TRIGGER_TCPWM0_TR_OUT0257, 264 _CYHAL_TRIGGER_TCPWM0_TR_OUT1257, 265 _CYHAL_TRIGGER_TCPWM0_TR_OUT0258, 266 _CYHAL_TRIGGER_TCPWM0_TR_OUT1258, 267 _CYHAL_TRIGGER_TCPWM0_TR_OUT0259, 268 _CYHAL_TRIGGER_TCPWM0_TR_OUT1259, 269 _CYHAL_TRIGGER_TCPWM0_TR_OUT0260, 270 _CYHAL_TRIGGER_TCPWM0_TR_OUT1260, 271 _CYHAL_TRIGGER_TCPWM0_TR_OUT0261, 272 _CYHAL_TRIGGER_TCPWM0_TR_OUT1261, 273 _CYHAL_TRIGGER_TCPWM0_TR_OUT0262, 274 _CYHAL_TRIGGER_TCPWM0_TR_OUT1262, 275 _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, 276 _CYHAL_TRIGGER_SCB0_TR_TX_REQ, 277 _CYHAL_TRIGGER_SCB0_TR_RX_REQ, 278 _CYHAL_TRIGGER_CPUSS_ZERO, 279 _CYHAL_TRIGGER_SCB1_TR_TX_REQ, 280 _CYHAL_TRIGGER_SCB1_TR_RX_REQ, 281 _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, 282 _CYHAL_TRIGGER_SCB2_TR_TX_REQ, 283 _CYHAL_TRIGGER_SCB2_TR_RX_REQ, 284 _CYHAL_TRIGGER_SMIF_TR_TX_REQ, 285 _CYHAL_TRIGGER_SMIF_TR_RX_REQ, 286 _CYHAL_TRIGGER_TDM_TR_TX_REQ0, 287 _CYHAL_TRIGGER_TDM_TR_RX_REQ0, 288 _CYHAL_TRIGGER_PDM_TR_RX_REQ0, 289 _CYHAL_TRIGGER_PDM_TR_RX_REQ1, 290 _CYHAL_TRIGGER_PDM_TR_RX_REQ_ALL, 291 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0, 292 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1, 293 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2, 294 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3, 295 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4, 296 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5, 297 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6, 298 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7, 299 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, 300 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, 301 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DC, 302 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DATA, 303 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, 304 }; 305 306 const _cyhal_trigger_source_cyw20829_t cyhal_mux5_sources[3] = 307 { 308 _CYHAL_TRIGGER_CPUSS_ZERO, 309 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, 310 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, 311 }; 312 313 const _cyhal_trigger_source_cyw20829_t cyhal_mux6_sources[19] = 314 { 315 _CYHAL_TRIGGER_CPUSS_ZERO, 316 _CYHAL_TRIGGER_TCPWM0_TR_OUT00, 317 _CYHAL_TRIGGER_TCPWM0_TR_OUT10, 318 _CYHAL_TRIGGER_TCPWM0_TR_OUT01, 319 _CYHAL_TRIGGER_TCPWM0_TR_OUT11, 320 _CYHAL_TRIGGER_TCPWM0_TR_OUT0256, 321 _CYHAL_TRIGGER_TCPWM0_TR_OUT1256, 322 _CYHAL_TRIGGER_TCPWM0_TR_OUT0257, 323 _CYHAL_TRIGGER_TCPWM0_TR_OUT1257, 324 _CYHAL_TRIGGER_TCPWM0_TR_OUT0258, 325 _CYHAL_TRIGGER_TCPWM0_TR_OUT1258, 326 _CYHAL_TRIGGER_TCPWM0_TR_OUT0259, 327 _CYHAL_TRIGGER_TCPWM0_TR_OUT1259, 328 _CYHAL_TRIGGER_TCPWM0_TR_OUT0260, 329 _CYHAL_TRIGGER_TCPWM0_TR_OUT1260, 330 _CYHAL_TRIGGER_TCPWM0_TR_OUT0261, 331 _CYHAL_TRIGGER_TCPWM0_TR_OUT1261, 332 _CYHAL_TRIGGER_TCPWM0_TR_OUT0262, 333 _CYHAL_TRIGGER_TCPWM0_TR_OUT1262, 334 }; 335 336 const _cyhal_trigger_source_cyw20829_t cyhal_mux7_sources[2] = 337 { 338 _CYHAL_TRIGGER_CPUSS_ZERO, 339 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, 340 }; 341 342 const _cyhal_trigger_source_cyw20829_t cyhal_mux8_sources[3] = 343 { 344 _CYHAL_TRIGGER_CPUSS_ZERO, 345 _CYHAL_TRIGGER_SCB0_TR_TX_REQ, 346 _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0, 347 }; 348 349 const _cyhal_trigger_source_cyw20829_t cyhal_mux9_sources[3] = 350 { 351 _CYHAL_TRIGGER_CPUSS_ZERO, 352 _CYHAL_TRIGGER_SCB0_TR_RX_REQ, 353 _CYHAL_TRIGGER_CANFD0_TR_FIFO00, 354 }; 355 356 const _cyhal_trigger_source_cyw20829_t cyhal_mux10_sources[4] = 357 { 358 _CYHAL_TRIGGER_SCB1_TR_TX_REQ, 359 _CYHAL_TRIGGER_SCB1_TR_RX_REQ, 360 _CYHAL_TRIGGER_SCB2_TR_TX_REQ, 361 _CYHAL_TRIGGER_SCB2_TR_RX_REQ, 362 }; 363 364 const _cyhal_trigger_source_cyw20829_t cyhal_mux11_sources[5] = 365 { 366 _CYHAL_TRIGGER_TDM_TR_TX_REQ0, 367 _CYHAL_TRIGGER_TDM_TR_RX_REQ0, 368 _CYHAL_TRIGGER_PDM_TR_RX_REQ0, 369 _CYHAL_TRIGGER_PDM_TR_RX_REQ1, 370 _CYHAL_TRIGGER_PDM_TR_RX_REQ_ALL, 371 }; 372 373 const _cyhal_trigger_source_cyw20829_t cyhal_mux12_sources[1] = 374 { 375 _CYHAL_TRIGGER_CANFD0_TR_FIFO10, 376 }; 377 378 const _cyhal_trigger_source_cyw20829_t cyhal_mux13_sources[1] = 379 { 380 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, 381 }; 382 383 const _cyhal_trigger_source_cyw20829_t cyhal_mux14_sources[2] = 384 { 385 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, 386 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, 387 }; 388 389 const _cyhal_trigger_source_cyw20829_t* cyhal_mux_to_sources[15] = 390 { 391 cyhal_mux0_sources, 392 cyhal_mux1_sources, 393 cyhal_mux2_sources, 394 cyhal_mux3_sources, 395 cyhal_mux4_sources, 396 cyhal_mux5_sources, 397 cyhal_mux6_sources, 398 cyhal_mux7_sources, 399 cyhal_mux8_sources, 400 cyhal_mux9_sources, 401 cyhal_mux10_sources, 402 cyhal_mux11_sources, 403 cyhal_mux12_sources, 404 cyhal_mux13_sources, 405 cyhal_mux14_sources, 406 }; 407 408 const uint8_t cyhal_dest_to_mux[59] = 409 { 410 131, /* CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0 */ 411 7, /* CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0 */ 412 4, /* CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 */ 413 4, /* CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 */ 414 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 */ 415 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 */ 416 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 */ 417 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 */ 418 8, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 */ 419 9, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 */ 420 128, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 */ 421 128, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 */ 422 128, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 */ 423 128, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 */ 424 129, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 */ 425 129, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 */ 426 129, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 */ 427 129, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 */ 428 129, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 */ 429 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 */ 430 3, /* CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT0 */ 431 3, /* CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT1 */ 432 132, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER0 */ 433 132, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER1 */ 434 6, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE0 */ 435 6, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE1 */ 436 5, /* CYHAL_TRIGGER_PDM_TR_DBG_FREEZE */ 437 5, /* CYHAL_TRIGGER_PERI_TR_DBG_FREEZE */ 438 4, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 */ 439 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 */ 440 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 */ 441 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 */ 442 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 */ 443 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 */ 444 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 */ 445 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 */ 446 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 */ 447 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 */ 448 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 */ 449 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 */ 450 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 */ 451 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 */ 452 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 */ 453 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 */ 454 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 */ 455 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 */ 456 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 */ 457 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 */ 458 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 */ 459 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 */ 460 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 */ 461 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 */ 462 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 */ 463 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 */ 464 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 */ 465 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 */ 466 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN27 */ 467 5, /* CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE */ 468 5, /* CYHAL_TRIGGER_TDM_TR_DBG_FREEZE */ 469 }; 470 471 const uint8_t cyhal_mux_dest_index[59] = 472 { 473 0, /* CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0 */ 474 0, /* CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0 */ 475 0, /* CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 */ 476 1, /* CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 */ 477 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 */ 478 1, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 */ 479 2, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 */ 480 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 */ 481 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 */ 482 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 */ 483 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 */ 484 1, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 */ 485 2, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 */ 486 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 */ 487 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 */ 488 1, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 */ 489 2, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 */ 490 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 */ 491 4, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 */ 492 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 */ 493 0, /* CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT0 */ 494 1, /* CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT1 */ 495 0, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER0 */ 496 1, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER1 */ 497 0, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE0 */ 498 1, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE1 */ 499 1, /* CYHAL_TRIGGER_PDM_TR_DBG_FREEZE */ 500 0, /* CYHAL_TRIGGER_PERI_TR_DBG_FREEZE */ 501 3, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 */ 502 0, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 */ 503 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 */ 504 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 */ 505 3, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 */ 506 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 */ 507 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 */ 508 6, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 */ 509 7, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 */ 510 8, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 */ 511 9, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 */ 512 10, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 */ 513 11, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 */ 514 12, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 */ 515 13, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 */ 516 0, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 */ 517 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 */ 518 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 */ 519 3, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 */ 520 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 */ 521 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 */ 522 6, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 */ 523 7, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 */ 524 8, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 */ 525 9, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 */ 526 10, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 */ 527 11, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 */ 528 12, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 */ 529 13, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN27 */ 530 3, /* CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE */ 531 2, /* CYHAL_TRIGGER_TDM_TR_DBG_FREEZE */ 532 }; 533 534 #endif /* CY_DEVICE_CYW20829 */ 535
