1 /***************************************************************************//** 2 * \file cyhal_psc3_vqfn_64.c 3 * 4 * \brief 5 * PSC3 device GPIO HAL header for VQFN-64 package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_PSC3_VQFN_64_H_) 31 #include "pin_packages/cyhal_psc3_vqfn_64.h" 32 33 /* Pin connections */ 34 /* Connections for: canfd_ttcan_rx */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[4] = { 36 {0u, 1u, P5_2, P5_2_CANFD0_TTCAN_RX1}, 37 {0u, 1u, P6_2, P6_2_CANFD0_TTCAN_RX1}, 38 {0u, 0u, P8_2, P8_2_CANFD0_TTCAN_RX0}, 39 {0u, 0u, P9_2, P9_2_CANFD0_TTCAN_RX0}, 40 }; 41 42 /* Connections for: canfd_ttcan_tx */ 43 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[4] = { 44 {0u, 1u, P5_3, P5_3_CANFD0_TTCAN_TX1}, 45 {0u, 1u, P6_3, P6_3_CANFD0_TTCAN_TX1}, 46 {0u, 0u, P8_3, P8_3_CANFD0_TTCAN_TX0}, 47 {0u, 0u, P9_3, P9_3_CANFD0_TTCAN_TX0}, 48 }; 49 50 /* Connections for: cpuss_clk_fm_pump */ 51 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 52 {0u, 0u, P9_3, P9_3_CPUSS_CLK_FM_PUMP}, 53 }; 54 55 /* Connections for: cpuss_fault */ 56 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault[2] = { 57 {0u, 0u, P6_3, P6_3_CPUSS_FAULT0}, 58 {0u, 0u, P9_3, P9_3_CPUSS_FAULT0}, 59 }; 60 61 /* Connections for: debug600_clk_swj_swclk_tclk */ 62 const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_clk_swj_swclk_tclk[1] = { 63 {0u, 0u, P1_2, P1_2_DEBUG600_CLK_SWJ_SWCLK_TCLK}, 64 }; 65 66 /* Connections for: debug600_rst_swj_trstn */ 67 const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_rst_swj_trstn[1] = { 68 {0u, 0u, P8_0, P8_0_DEBUG600_RST_SWJ_TRSTN}, 69 }; 70 71 /* Connections for: debug600_swj_swdio_tms */ 72 const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swdio_tms[1] = { 73 {0u, 0u, P1_3, P1_3_DEBUG600_SWJ_SWDIO_TMS}, 74 }; 75 76 /* Connections for: debug600_swj_swdoe_tdi */ 77 const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swdoe_tdi[1] = { 78 {0u, 0u, P2_0, P2_0_DEBUG600_SWJ_SWDOE_TDI}, 79 }; 80 81 /* Connections for: debug600_swj_swo_tdo */ 82 const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swo_tdo[1] = { 83 {0u, 0u, P2_1, P2_1_DEBUG600_SWJ_SWO_TDO}, 84 }; 85 86 /* Connections for: debug600_trace_clock */ 87 const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_trace_clock[2] = { 88 {0u, 0u, P7_4, P7_4_DEBUG600_TRACE_CLOCK}, 89 {0u, 0u, P9_2, P9_2_DEBUG600_TRACE_CLOCK}, 90 }; 91 92 /* Connections for: debug600_trace_data */ 93 const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_trace_data[8] = { 94 {0u, 0u, P7_0, P7_0_DEBUG600_TRACE_DATA0}, 95 {0u, 1u, P7_1, P7_1_DEBUG600_TRACE_DATA1}, 96 {0u, 2u, P7_2, P7_2_DEBUG600_TRACE_DATA2}, 97 {0u, 3u, P7_3, P7_3_DEBUG600_TRACE_DATA3}, 98 {0u, 0u, P8_0, P8_0_DEBUG600_TRACE_DATA0}, 99 {0u, 1u, P8_1, P8_1_DEBUG600_TRACE_DATA1}, 100 {0u, 2u, P8_2, P8_2_DEBUG600_TRACE_DATA2}, 101 {0u, 3u, P8_3, P8_3_DEBUG600_TRACE_DATA3}, 102 }; 103 104 /* Connections for: lpcomp_inn_comp */ 105 const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[2] = { 106 {0u, 0u, P8_1, HSIOM_SEL_GPIO}, 107 {0u, 1u, P8_3, HSIOM_SEL_GPIO}, 108 }; 109 110 /* Connections for: lpcomp_inp_comp */ 111 const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2] = { 112 {0u, 0u, P8_0, HSIOM_SEL_GPIO}, 113 {0u, 1u, P8_2, HSIOM_SEL_GPIO}, 114 }; 115 116 /* Connections for: pass_an_a_pad_aio */ 117 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_an_a_pad_aio[8] = { 118 {0u, 0u, AN_A0, HSIOM_SEL_GPIO}, 119 {0u, 1u, AN_A1, HSIOM_SEL_GPIO}, 120 {0u, 2u, AN_A2, HSIOM_SEL_GPIO}, 121 {0u, 3u, AN_A3, HSIOM_SEL_GPIO}, 122 {0u, 4u, AN_A4, HSIOM_SEL_GPIO}, 123 {0u, 5u, AN_A5, HSIOM_SEL_GPIO}, 124 {0u, 6u, AN_A6, HSIOM_SEL_GPIO}, 125 {0u, 7u, AN_A7, HSIOM_SEL_GPIO}, 126 }; 127 128 /* Connections for: pass_an_b_pad_aio */ 129 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_an_b_pad_aio[8] = { 130 {0u, 8u, AN_B0, HSIOM_SEL_GPIO}, 131 {0u, 9u, AN_B1, HSIOM_SEL_GPIO}, 132 {0u, 10u, AN_B2, HSIOM_SEL_GPIO}, 133 {0u, 11u, AN_B3, HSIOM_SEL_GPIO}, 134 {0u, 12u, AN_B4, HSIOM_SEL_GPIO}, 135 {0u, 13u, AN_B5, HSIOM_SEL_GPIO}, 136 {0u, 14u, AN_B6, HSIOM_SEL_GPIO}, 137 {0u, 15u, AN_B7, HSIOM_SEL_GPIO}, 138 }; 139 140 /* Connections for: pass_gpio_00_aio */ 141 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_gpio_00_aio[1] = { 142 {0u, 0u, P8_0, HSIOM_SEL_GPIO}, 143 }; 144 145 /* Connections for: pass_gpio_01_aio */ 146 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_gpio_01_aio[1] = { 147 {0u, 0u, P8_2, HSIOM_SEL_GPIO}, 148 }; 149 150 /* Connections for: pass_mcpass_dclk */ 151 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_mcpass_dclk[2] = { 152 {0u, 0u, P7_4, P7_4_PASS_MCPASS_DCLK}, 153 {0u, 0u, P9_2, P9_2_PASS_MCPASS_DCLK}, 154 }; 155 156 /* Connections for: pass_mcpass_dout */ 157 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_mcpass_dout[8] = { 158 {0u, 0u, P7_0, P7_0_PASS_MCPASS_DOUT0}, 159 {0u, 1u, P7_1, P7_1_PASS_MCPASS_DOUT1}, 160 {0u, 2u, P7_2, P7_2_PASS_MCPASS_DOUT2}, 161 {0u, 3u, P7_3, P7_3_PASS_MCPASS_DOUT3}, 162 {0u, 0u, P8_0, P8_0_PASS_MCPASS_DOUT0}, 163 {0u, 1u, P8_1, P8_1_PASS_MCPASS_DOUT1}, 164 {0u, 2u, P8_2, P8_2_PASS_MCPASS_DOUT2}, 165 {0u, 3u, P8_3, P8_3_PASS_MCPASS_DOUT3}, 166 }; 167 168 /* Connections for: peri_tr_io_input */ 169 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 170 to know the index of the input or output trigger line. Store that in the channel_num field 171 instead. */ 172 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[39] = { 173 {0u, 0u, P0_0, P0_0_PERI_TR_IO_INPUT0}, 174 {0u, 1u, P0_1, P0_1_PERI_TR_IO_INPUT1}, 175 {0u, 2u, P1_0, P1_0_PERI_TR_IO_INPUT2}, 176 {0u, 3u, P1_1, P1_1_PERI_TR_IO_INPUT3}, 177 {0u, 4u, P1_2, P1_2_PERI_TR_IO_INPUT4}, 178 {0u, 5u, P1_3, P1_3_PERI_TR_IO_INPUT5}, 179 {0u, 6u, P2_0, P2_0_PERI_TR_IO_INPUT6}, 180 {0u, 7u, P2_1, P2_1_PERI_TR_IO_INPUT7}, 181 {0u, 8u, P2_2, P2_2_PERI_TR_IO_INPUT8}, 182 {0u, 9u, P2_3, P2_3_PERI_TR_IO_INPUT9}, 183 {0u, 14u, P4_0, P4_0_PERI_TR_IO_INPUT14}, 184 {0u, 15u, P4_1, P4_1_PERI_TR_IO_INPUT15}, 185 {0u, 16u, P4_2, P4_2_PERI_TR_IO_INPUT16}, 186 {0u, 17u, P4_3, P4_3_PERI_TR_IO_INPUT17}, 187 {0u, 18u, P4_4, P4_4_PERI_TR_IO_INPUT18}, 188 {0u, 19u, P4_5, P4_5_PERI_TR_IO_INPUT19}, 189 {0u, 20u, P4_6, P4_6_PERI_TR_IO_INPUT20}, 190 {0u, 21u, P4_7, P4_7_PERI_TR_IO_INPUT21}, 191 {0u, 22u, P5_0, P5_0_PERI_TR_IO_INPUT22}, 192 {0u, 23u, P5_1, P5_1_PERI_TR_IO_INPUT23}, 193 {0u, 24u, P5_2, P5_2_PERI_TR_IO_INPUT24}, 194 {0u, 25u, P5_3, P5_3_PERI_TR_IO_INPUT25}, 195 {0u, 26u, P6_0, P6_0_PERI_TR_IO_INPUT26}, 196 {0u, 27u, P6_1, P6_1_PERI_TR_IO_INPUT27}, 197 {0u, 28u, P6_2, P6_2_PERI_TR_IO_INPUT28}, 198 {0u, 29u, P6_3, P6_3_PERI_TR_IO_INPUT29}, 199 {0u, 30u, P7_0, P7_0_PERI_TR_IO_INPUT30}, 200 {0u, 31u, P7_1, P7_1_PERI_TR_IO_INPUT31}, 201 {0u, 32u, P7_2, P7_2_PERI_TR_IO_INPUT32}, 202 {0u, 33u, P7_3, P7_3_PERI_TR_IO_INPUT33}, 203 {0u, 34u, P7_4, P7_4_PERI_TR_IO_INPUT34}, 204 {0u, 38u, P8_0, P8_0_PERI_TR_IO_INPUT38}, 205 {0u, 39u, P8_1, P8_1_PERI_TR_IO_INPUT39}, 206 {0u, 40u, P8_2, P8_2_PERI_TR_IO_INPUT40}, 207 {0u, 41u, P8_3, P8_3_PERI_TR_IO_INPUT41}, 208 {0u, 44u, P9_0, P9_0_PERI_TR_IO_INPUT44}, 209 {0u, 45u, P9_1, P9_1_PERI_TR_IO_INPUT45}, 210 {0u, 46u, P9_2, P9_2_PERI_TR_IO_INPUT46}, 211 {0u, 47u, P9_3, P9_3_PERI_TR_IO_INPUT47}, 212 }; 213 214 /* Connections for: peri_tr_io_output */ 215 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 216 to know the index of the input or output trigger line. Store that in the channel_num field 217 instead. */ 218 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[80] = { 219 {0u, 0u, P0_0, P0_0_PERI_TR_IO_OUTPUT0}, 220 {0u, 1u, P0_1, P0_1_PERI_TR_IO_OUTPUT1}, 221 {0u, 2u, P1_0, P1_0_PERI_TR_IO_OUTPUT2}, 222 {0u, 58u, P1_0, P1_0_PERI_TR_IO_OUTPUT58}, 223 {0u, 70u, P1_0, P1_0_PERI_TR_IO_OUTPUT70}, 224 {0u, 3u, P1_1, P1_1_PERI_TR_IO_OUTPUT3}, 225 {0u, 59u, P1_1, P1_1_PERI_TR_IO_OUTPUT59}, 226 {0u, 71u, P1_1, P1_1_PERI_TR_IO_OUTPUT71}, 227 {0u, 4u, P1_2, P1_2_PERI_TR_IO_OUTPUT4}, 228 {0u, 60u, P1_2, P1_2_PERI_TR_IO_OUTPUT60}, 229 {0u, 72u, P1_2, P1_2_PERI_TR_IO_OUTPUT72}, 230 {0u, 5u, P1_3, P1_3_PERI_TR_IO_OUTPUT5}, 231 {0u, 61u, P1_3, P1_3_PERI_TR_IO_OUTPUT61}, 232 {0u, 73u, P1_3, P1_3_PERI_TR_IO_OUTPUT73}, 233 {0u, 6u, P2_0, P2_0_PERI_TR_IO_OUTPUT6}, 234 {0u, 58u, P2_0, P2_0_PERI_TR_IO_OUTPUT58}, 235 {0u, 7u, P2_1, P2_1_PERI_TR_IO_OUTPUT7}, 236 {0u, 59u, P2_1, P2_1_PERI_TR_IO_OUTPUT59}, 237 {0u, 8u, P2_2, P2_2_PERI_TR_IO_OUTPUT8}, 238 {0u, 60u, P2_2, P2_2_PERI_TR_IO_OUTPUT60}, 239 {0u, 9u, P2_3, P2_3_PERI_TR_IO_OUTPUT9}, 240 {0u, 61u, P2_3, P2_3_PERI_TR_IO_OUTPUT61}, 241 {0u, 14u, P4_0, P4_0_PERI_TR_IO_OUTPUT14}, 242 {0u, 50u, P4_0, P4_0_PERI_TR_IO_OUTPUT50}, 243 {0u, 15u, P4_1, P4_1_PERI_TR_IO_OUTPUT15}, 244 {0u, 51u, P4_1, P4_1_PERI_TR_IO_OUTPUT51}, 245 {0u, 16u, P4_2, P4_2_PERI_TR_IO_OUTPUT16}, 246 {0u, 52u, P4_2, P4_2_PERI_TR_IO_OUTPUT52}, 247 {0u, 17u, P4_3, P4_3_PERI_TR_IO_OUTPUT17}, 248 {0u, 53u, P4_3, P4_3_PERI_TR_IO_OUTPUT53}, 249 {0u, 18u, P4_4, P4_4_PERI_TR_IO_OUTPUT18}, 250 {0u, 54u, P4_4, P4_4_PERI_TR_IO_OUTPUT54}, 251 {0u, 19u, P4_5, P4_5_PERI_TR_IO_OUTPUT19}, 252 {0u, 55u, P4_5, P4_5_PERI_TR_IO_OUTPUT55}, 253 {0u, 20u, P4_6, P4_6_PERI_TR_IO_OUTPUT20}, 254 {0u, 56u, P4_6, P4_6_PERI_TR_IO_OUTPUT56}, 255 {0u, 21u, P4_7, P4_7_PERI_TR_IO_OUTPUT21}, 256 {0u, 57u, P4_7, P4_7_PERI_TR_IO_OUTPUT57}, 257 {0u, 22u, P5_0, P5_0_PERI_TR_IO_OUTPUT22}, 258 {0u, 62u, P5_0, P5_0_PERI_TR_IO_OUTPUT62}, 259 {0u, 23u, P5_1, P5_1_PERI_TR_IO_OUTPUT23}, 260 {0u, 63u, P5_1, P5_1_PERI_TR_IO_OUTPUT63}, 261 {0u, 24u, P5_2, P5_2_PERI_TR_IO_OUTPUT24}, 262 {0u, 64u, P5_2, P5_2_PERI_TR_IO_OUTPUT64}, 263 {0u, 25u, P5_3, P5_3_PERI_TR_IO_OUTPUT25}, 264 {0u, 65u, P5_3, P5_3_PERI_TR_IO_OUTPUT65}, 265 {0u, 26u, P6_0, P6_0_PERI_TR_IO_OUTPUT26}, 266 {0u, 66u, P6_0, P6_0_PERI_TR_IO_OUTPUT66}, 267 {0u, 27u, P6_1, P6_1_PERI_TR_IO_OUTPUT27}, 268 {0u, 67u, P6_1, P6_1_PERI_TR_IO_OUTPUT67}, 269 {0u, 28u, P6_2, P6_2_PERI_TR_IO_OUTPUT28}, 270 {0u, 68u, P6_2, P6_2_PERI_TR_IO_OUTPUT68}, 271 {0u, 29u, P6_3, P6_3_PERI_TR_IO_OUTPUT29}, 272 {0u, 69u, P6_3, P6_3_PERI_TR_IO_OUTPUT69}, 273 {0u, 30u, P7_0, P7_0_PERI_TR_IO_OUTPUT30}, 274 {0u, 50u, P7_0, P7_0_PERI_TR_IO_OUTPUT50}, 275 {0u, 70u, P7_0, P7_0_PERI_TR_IO_OUTPUT70}, 276 {0u, 31u, P7_1, P7_1_PERI_TR_IO_OUTPUT31}, 277 {0u, 51u, P7_1, P7_1_PERI_TR_IO_OUTPUT51}, 278 {0u, 71u, P7_1, P7_1_PERI_TR_IO_OUTPUT71}, 279 {0u, 32u, P7_2, P7_2_PERI_TR_IO_OUTPUT32}, 280 {0u, 52u, P7_2, P7_2_PERI_TR_IO_OUTPUT52}, 281 {0u, 72u, P7_2, P7_2_PERI_TR_IO_OUTPUT72}, 282 {0u, 33u, P7_3, P7_3_PERI_TR_IO_OUTPUT33}, 283 {0u, 53u, P7_3, P7_3_PERI_TR_IO_OUTPUT53}, 284 {0u, 73u, P7_3, P7_3_PERI_TR_IO_OUTPUT73}, 285 {0u, 34u, P7_4, P7_4_PERI_TR_IO_OUTPUT34}, 286 {0u, 54u, P7_4, P7_4_PERI_TR_IO_OUTPUT54}, 287 {0u, 38u, P8_0, P8_0_PERI_TR_IO_OUTPUT38}, 288 {0u, 62u, P8_0, P8_0_PERI_TR_IO_OUTPUT62}, 289 {0u, 39u, P8_1, P8_1_PERI_TR_IO_OUTPUT39}, 290 {0u, 63u, P8_1, P8_1_PERI_TR_IO_OUTPUT63}, 291 {0u, 40u, P8_2, P8_2_PERI_TR_IO_OUTPUT40}, 292 {0u, 64u, P8_2, P8_2_PERI_TR_IO_OUTPUT64}, 293 {0u, 41u, P8_3, P8_3_PERI_TR_IO_OUTPUT41}, 294 {0u, 65u, P8_3, P8_3_PERI_TR_IO_OUTPUT65}, 295 {0u, 44u, P9_0, P9_0_PERI_TR_IO_OUTPUT44}, 296 {0u, 45u, P9_1, P9_1_PERI_TR_IO_OUTPUT45}, 297 {0u, 46u, P9_2, P9_2_PERI_TR_IO_OUTPUT46}, 298 {0u, 47u, P9_3, P9_3_PERI_TR_IO_OUTPUT47}, 299 }; 300 301 /* Connections for: scb_i2c_scl */ 302 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[8] = { 303 {1u, 0u, P1_3, P1_3_SCB1_I2C_SCL}, 304 {1u, 0u, P2_1, P2_1_SCB1_I2C_SCL}, 305 {4u, 0u, P4_2, P4_2_SCB4_I2C_SCL}, 306 {3u, 0u, P5_1, P5_1_SCB3_I2C_SCL}, 307 {3u, 0u, P6_1, P6_1_SCB3_I2C_SCL}, 308 {2u, 0u, P7_0, P7_0_SCB2_I2C_SCL}, 309 {5u, 0u, P8_1, P8_1_SCB5_I2C_SCL}, 310 {0u, 0u, P9_0, P9_0_SCB0_I2C_SCL}, 311 }; 312 313 /* Connections for: scb_i2c_sda */ 314 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[8] = { 315 {1u, 0u, P1_2, P1_2_SCB1_I2C_SDA}, 316 {1u, 0u, P2_2, P2_2_SCB1_I2C_SDA}, 317 {4u, 0u, P4_1, P4_1_SCB4_I2C_SDA}, 318 {3u, 0u, P5_0, P5_0_SCB3_I2C_SDA}, 319 {3u, 0u, P6_0, P6_0_SCB3_I2C_SDA}, 320 {2u, 0u, P7_1, P7_1_SCB2_I2C_SDA}, 321 {5u, 0u, P8_3, P8_3_SCB5_I2C_SDA}, 322 {0u, 0u, P9_2, P9_2_SCB0_I2C_SDA}, 323 }; 324 325 /* Connections for: scb_spi_m_clk */ 326 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[8] = { 327 {1u, 0u, P1_1, P1_1_SCB1_SPI_CLK}, 328 {1u, 0u, P2_1, P2_1_SCB1_SPI_CLK}, 329 {4u, 0u, P4_2, P4_2_SCB4_SPI_CLK}, 330 {3u, 0u, P5_2, P5_2_SCB3_SPI_CLK}, 331 {3u, 0u, P6_2, P6_2_SCB3_SPI_CLK}, 332 {2u, 0u, P7_0, P7_0_SCB2_SPI_CLK}, 333 {5u, 0u, P8_3, P8_3_SCB5_SPI_CLK}, 334 {0u, 0u, P9_0, P9_0_SCB0_SPI_CLK}, 335 }; 336 337 /* Connections for: scb_spi_m_miso */ 338 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[8] = { 339 {1u, 0u, P1_3, P1_3_SCB1_SPI_MISO}, 340 {1u, 0u, P2_3, P2_3_SCB1_SPI_MISO}, 341 {4u, 0u, P4_1, P4_1_SCB4_SPI_MISO}, 342 {3u, 0u, P5_1, P5_1_SCB3_SPI_MISO}, 343 {3u, 0u, P6_1, P6_1_SCB3_SPI_MISO}, 344 {2u, 0u, P7_2, P7_2_SCB2_SPI_MISO}, 345 {5u, 0u, P8_2, P8_2_SCB5_SPI_MISO}, 346 {0u, 0u, P9_3, P9_3_SCB0_SPI_MISO}, 347 }; 348 349 /* Connections for: scb_spi_m_mosi */ 350 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[8] = { 351 {1u, 0u, P1_2, P1_2_SCB1_SPI_MOSI}, 352 {1u, 0u, P2_2, P2_2_SCB1_SPI_MOSI}, 353 {4u, 0u, P4_0, P4_0_SCB4_SPI_MOSI}, 354 {3u, 0u, P5_0, P5_0_SCB3_SPI_MOSI}, 355 {3u, 0u, P6_0, P6_0_SCB3_SPI_MOSI}, 356 {2u, 0u, P7_1, P7_1_SCB2_SPI_MOSI}, 357 {5u, 0u, P8_1, P8_1_SCB5_SPI_MOSI}, 358 {0u, 0u, P9_2, P9_2_SCB0_SPI_MOSI}, 359 }; 360 361 /* Connections for: scb_spi_m_select0 */ 362 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8] = { 363 {1u, 0u, P1_0, P1_0_SCB1_SPI_SELECT0}, 364 {1u, 0u, P2_0, P2_0_SCB1_SPI_SELECT0}, 365 {4u, 0u, P4_3, P4_3_SCB4_SPI_SELECT0}, 366 {3u, 0u, P5_3, P5_3_SCB3_SPI_SELECT0}, 367 {3u, 0u, P6_3, P6_3_SCB3_SPI_SELECT0}, 368 {2u, 0u, P7_3, P7_3_SCB2_SPI_SELECT0}, 369 {5u, 0u, P8_0, P8_0_SCB5_SPI_SELECT0}, 370 {0u, 0u, P9_1, P9_1_SCB0_SPI_SELECT0}, 371 }; 372 373 /* Connections for: scb_spi_m_select1 */ 374 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[1] = { 375 {2u, 0u, P7_4, P7_4_SCB2_SPI_SELECT1}, 376 }; 377 378 /* Connections for: scb_spi_m_select2 */ 379 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[1] = { 380 {0u, 0u, NC, HSIOM_SEL_GPIO}, 381 }; 382 383 /* Connections for: scb_spi_s_clk */ 384 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[8] = { 385 {1u, 0u, P1_1, P1_1_SCB1_SPI_CLK}, 386 {1u, 0u, P2_1, P2_1_SCB1_SPI_CLK}, 387 {4u, 0u, P4_2, P4_2_SCB4_SPI_CLK}, 388 {3u, 0u, P5_2, P5_2_SCB3_SPI_CLK}, 389 {3u, 0u, P6_2, P6_2_SCB3_SPI_CLK}, 390 {2u, 0u, P7_0, P7_0_SCB2_SPI_CLK}, 391 {5u, 0u, P8_3, P8_3_SCB5_SPI_CLK}, 392 {0u, 0u, P9_0, P9_0_SCB0_SPI_CLK}, 393 }; 394 395 /* Connections for: scb_spi_s_miso */ 396 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[8] = { 397 {1u, 0u, P1_3, P1_3_SCB1_SPI_MISO}, 398 {1u, 0u, P2_3, P2_3_SCB1_SPI_MISO}, 399 {4u, 0u, P4_1, P4_1_SCB4_SPI_MISO}, 400 {3u, 0u, P5_1, P5_1_SCB3_SPI_MISO}, 401 {3u, 0u, P6_1, P6_1_SCB3_SPI_MISO}, 402 {2u, 0u, P7_2, P7_2_SCB2_SPI_MISO}, 403 {5u, 0u, P8_2, P8_2_SCB5_SPI_MISO}, 404 {0u, 0u, P9_3, P9_3_SCB0_SPI_MISO}, 405 }; 406 407 /* Connections for: scb_spi_s_mosi */ 408 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[8] = { 409 {1u, 0u, P1_2, P1_2_SCB1_SPI_MOSI}, 410 {1u, 0u, P2_2, P2_2_SCB1_SPI_MOSI}, 411 {4u, 0u, P4_0, P4_0_SCB4_SPI_MOSI}, 412 {3u, 0u, P5_0, P5_0_SCB3_SPI_MOSI}, 413 {3u, 0u, P6_0, P6_0_SCB3_SPI_MOSI}, 414 {2u, 0u, P7_1, P7_1_SCB2_SPI_MOSI}, 415 {5u, 0u, P8_1, P8_1_SCB5_SPI_MOSI}, 416 {0u, 0u, P9_2, P9_2_SCB0_SPI_MOSI}, 417 }; 418 419 /* Connections for: scb_spi_s_select0 */ 420 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8] = { 421 {1u, 0u, P1_0, P1_0_SCB1_SPI_SELECT0}, 422 {1u, 0u, P2_0, P2_0_SCB1_SPI_SELECT0}, 423 {4u, 0u, P4_3, P4_3_SCB4_SPI_SELECT0}, 424 {3u, 0u, P5_3, P5_3_SCB3_SPI_SELECT0}, 425 {3u, 0u, P6_3, P6_3_SCB3_SPI_SELECT0}, 426 {2u, 0u, P7_3, P7_3_SCB2_SPI_SELECT0}, 427 {5u, 0u, P8_0, P8_0_SCB5_SPI_SELECT0}, 428 {0u, 0u, P9_1, P9_1_SCB0_SPI_SELECT0}, 429 }; 430 431 /* Connections for: scb_spi_s_select1 */ 432 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[1] = { 433 {2u, 0u, P7_4, P7_4_SCB2_SPI_SELECT1}, 434 }; 435 436 /* Connections for: scb_spi_s_select2 */ 437 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[1] = { 438 {0u, 0u, NC, HSIOM_SEL_GPIO}, 439 }; 440 441 /* Connections for: scb_uart_cts */ 442 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[8] = { 443 {1u, 0u, P1_0, P1_0_SCB1_UART_CTS}, 444 {1u, 0u, P2_0, P2_0_SCB1_UART_CTS}, 445 {4u, 0u, P4_0, P4_0_SCB4_UART_CTS}, 446 {3u, 0u, P5_0, P5_0_SCB3_UART_CTS}, 447 {3u, 0u, P6_0, P6_0_SCB3_UART_CTS}, 448 {2u, 0u, P7_0, P7_0_SCB2_UART_CTS}, 449 {5u, 0u, P8_0, P8_0_SCB5_UART_CTS}, 450 {0u, 0u, P9_0, P9_0_SCB0_UART_CTS}, 451 }; 452 453 /* Connections for: scb_uart_rts */ 454 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[8] = { 455 {1u, 0u, P1_1, P1_1_SCB1_UART_RTS}, 456 {1u, 0u, P2_1, P2_1_SCB1_UART_RTS}, 457 {4u, 0u, P4_1, P4_1_SCB4_UART_RTS}, 458 {3u, 0u, P5_1, P5_1_SCB3_UART_RTS}, 459 {3u, 0u, P6_1, P6_1_SCB3_UART_RTS}, 460 {2u, 0u, P7_3, P7_3_SCB2_UART_RTS}, 461 {5u, 0u, P8_2, P8_2_SCB5_UART_RTS}, 462 {0u, 0u, P9_1, P9_1_SCB0_UART_RTS}, 463 }; 464 465 /* Connections for: scb_uart_rx */ 466 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[8] = { 467 {1u, 0u, P1_2, P1_2_SCB1_UART_RX}, 468 {1u, 0u, P2_2, P2_2_SCB1_UART_RX}, 469 {4u, 0u, P4_2, P4_2_SCB4_UART_RX}, 470 {3u, 0u, P5_2, P5_2_SCB3_UART_RX}, 471 {3u, 0u, P6_2, P6_2_SCB3_UART_RX}, 472 {2u, 0u, P7_2, P7_2_SCB2_UART_RX}, 473 {5u, 0u, P8_1, P8_1_SCB5_UART_RX}, 474 {0u, 0u, P9_2, P9_2_SCB0_UART_RX}, 475 }; 476 477 /* Connections for: scb_uart_tx */ 478 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[8] = { 479 {1u, 0u, P1_3, P1_3_SCB1_UART_TX}, 480 {1u, 0u, P2_3, P2_3_SCB1_UART_TX}, 481 {4u, 0u, P4_3, P4_3_SCB4_UART_TX}, 482 {3u, 0u, P5_3, P5_3_SCB3_UART_TX}, 483 {3u, 0u, P6_3, P6_3_SCB3_UART_TX}, 484 {2u, 0u, P7_1, P7_1_SCB2_UART_TX}, 485 {5u, 0u, P8_3, P8_3_SCB5_UART_TX}, 486 {0u, 0u, P9_3, P9_3_SCB0_UART_TX}, 487 }; 488 489 /* Connections for: tcpwm_line */ 490 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[14] = { 491 {2u, 6u, P2_0, P2_0_TCPWM0_LINE518}, 492 {2u, 7u, P2_2, P2_2_TCPWM0_LINE519}, 493 {1u, 4u, P4_0, P4_0_TCPWM0_LINE260}, 494 {1u, 5u, P4_2, P4_2_TCPWM0_LINE261}, 495 {1u, 6u, P4_4, P4_4_TCPWM0_LINE262}, 496 {1u, 7u, P4_6, P4_6_TCPWM0_LINE263}, 497 {1u, 4u, P6_0, P6_0_TCPWM0_LINE260}, 498 {1u, 5u, P6_2, P6_2_TCPWM0_LINE261}, 499 {1u, 6u, P7_0, P7_0_TCPWM0_LINE262}, 500 {1u, 7u, P7_2, P7_2_TCPWM0_LINE263}, 501 {2u, 4u, P8_0, P8_0_TCPWM0_LINE516}, 502 {2u, 5u, P8_2, P8_2_TCPWM0_LINE517}, 503 {2u, 6u, P9_0, P9_0_TCPWM0_LINE518}, 504 {2u, 7u, P9_2, P9_2_TCPWM0_LINE519}, 505 }; 506 507 /* Connections for: tcpwm_line_compl */ 508 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[14] = { 509 {2u, 6u, P2_1, P2_1_TCPWM0_LINE_COMPL518}, 510 {2u, 7u, P2_3, P2_3_TCPWM0_LINE_COMPL519}, 511 {1u, 4u, P4_1, P4_1_TCPWM0_LINE_COMPL260}, 512 {1u, 5u, P4_3, P4_3_TCPWM0_LINE_COMPL261}, 513 {1u, 6u, P4_5, P4_5_TCPWM0_LINE_COMPL262}, 514 {1u, 7u, P4_7, P4_7_TCPWM0_LINE_COMPL263}, 515 {1u, 4u, P6_1, P6_1_TCPWM0_LINE_COMPL260}, 516 {1u, 5u, P6_3, P6_3_TCPWM0_LINE_COMPL261}, 517 {1u, 6u, P7_1, P7_1_TCPWM0_LINE_COMPL262}, 518 {1u, 7u, P7_3, P7_3_TCPWM0_LINE_COMPL263}, 519 {2u, 4u, P8_1, P8_1_TCPWM0_LINE_COMPL516}, 520 {2u, 5u, P8_3, P8_3_TCPWM0_LINE_COMPL517}, 521 {2u, 6u, P9_1, P9_1_TCPWM0_LINE_COMPL518}, 522 {2u, 7u, P9_3, P9_3_TCPWM0_LINE_COMPL519}, 523 }; 524 525 #endif 526
