1 /***************************************************************************//** 2 * \file cyhal_psc3_vqfn_48.c 3 * 4 * \brief 5 * PSC3 device GPIO HAL header for VQFN-48 package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_PSC3_VQFN_48_H_) 31 #include "pin_packages/cyhal_psc3_vqfn_48.h" 32 33 /* Pin connections */ 34 /* Connections for: canfd_ttcan_rx */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[3] = { 36 {0u, 1u, P6_2, P6_2_CANFD0_TTCAN_RX1}, 37 {0u, 0u, P8_2, P8_2_CANFD0_TTCAN_RX0}, 38 {0u, 0u, P9_2, P9_2_CANFD0_TTCAN_RX0}, 39 }; 40 41 /* Connections for: canfd_ttcan_tx */ 42 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[3] = { 43 {0u, 1u, P6_3, P6_3_CANFD0_TTCAN_TX1}, 44 {0u, 0u, P8_3, P8_3_CANFD0_TTCAN_TX0}, 45 {0u, 0u, P9_3, P9_3_CANFD0_TTCAN_TX0}, 46 }; 47 48 /* Connections for: cpuss_clk_fm_pump */ 49 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_fm_pump[1] = { 50 {0u, 0u, P9_3, P9_3_CPUSS_CLK_FM_PUMP}, 51 }; 52 53 /* Connections for: cpuss_fault */ 54 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_fault[2] = { 55 {0u, 0u, P6_3, P6_3_CPUSS_FAULT0}, 56 {0u, 0u, P9_3, P9_3_CPUSS_FAULT0}, 57 }; 58 59 /* Connections for: debug600_clk_swj_swclk_tclk */ 60 const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_clk_swj_swclk_tclk[1] = { 61 {0u, 0u, P1_2, P1_2_DEBUG600_CLK_SWJ_SWCLK_TCLK}, 62 }; 63 64 /* Connections for: debug600_rst_swj_trstn */ 65 const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_rst_swj_trstn[1] = { 66 {0u, 0u, P8_0, P8_0_DEBUG600_RST_SWJ_TRSTN}, 67 }; 68 69 /* Connections for: debug600_swj_swdio_tms */ 70 const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swdio_tms[1] = { 71 {0u, 0u, P1_3, P1_3_DEBUG600_SWJ_SWDIO_TMS}, 72 }; 73 74 /* Connections for: debug600_swj_swdoe_tdi */ 75 const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swdoe_tdi[1] = { 76 {0u, 0u, P2_0, P2_0_DEBUG600_SWJ_SWDOE_TDI}, 77 }; 78 79 /* Connections for: debug600_swj_swo_tdo */ 80 const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_swj_swo_tdo[1] = { 81 {0u, 0u, P2_1, P2_1_DEBUG600_SWJ_SWO_TDO}, 82 }; 83 84 /* Connections for: debug600_trace_clock */ 85 const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_trace_clock[1] = { 86 {0u, 0u, P9_2, P9_2_DEBUG600_TRACE_CLOCK}, 87 }; 88 89 /* Connections for: debug600_trace_data */ 90 const cyhal_resource_pin_mapping_t cyhal_pin_map_debug600_trace_data[7] = { 91 {0u, 0u, P7_0, P7_0_DEBUG600_TRACE_DATA0}, 92 {0u, 1u, P7_1, P7_1_DEBUG600_TRACE_DATA1}, 93 {0u, 2u, P7_2, P7_2_DEBUG600_TRACE_DATA2}, 94 {0u, 0u, P8_0, P8_0_DEBUG600_TRACE_DATA0}, 95 {0u, 1u, P8_1, P8_1_DEBUG600_TRACE_DATA1}, 96 {0u, 2u, P8_2, P8_2_DEBUG600_TRACE_DATA2}, 97 {0u, 3u, P8_3, P8_3_DEBUG600_TRACE_DATA3}, 98 }; 99 100 /* Connections for: lpcomp_inn_comp */ 101 const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp[2] = { 102 {0u, 0u, P8_1, HSIOM_SEL_GPIO}, 103 {0u, 1u, P8_3, HSIOM_SEL_GPIO}, 104 }; 105 106 /* Connections for: lpcomp_inp_comp */ 107 const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2] = { 108 {0u, 0u, P8_0, HSIOM_SEL_GPIO}, 109 {0u, 1u, P8_2, HSIOM_SEL_GPIO}, 110 }; 111 112 /* Connections for: pass_an_a_pad_aio */ 113 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_an_a_pad_aio[6] = { 114 {0u, 0u, AN_A0, HSIOM_SEL_GPIO}, 115 {0u, 1u, AN_A1, HSIOM_SEL_GPIO}, 116 {0u, 2u, AN_A2, HSIOM_SEL_GPIO}, 117 {0u, 3u, AN_A3, HSIOM_SEL_GPIO}, 118 {0u, 4u, AN_A4, HSIOM_SEL_GPIO}, 119 {0u, 5u, AN_A5, HSIOM_SEL_GPIO}, 120 }; 121 122 /* Connections for: pass_an_b_pad_aio */ 123 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_an_b_pad_aio[4] = { 124 {0u, 9u, AN_B1, HSIOM_SEL_GPIO}, 125 {0u, 10u, AN_B2, HSIOM_SEL_GPIO}, 126 {0u, 11u, AN_B3, HSIOM_SEL_GPIO}, 127 {0u, 12u, AN_B4, HSIOM_SEL_GPIO}, 128 }; 129 130 /* Connections for: pass_gpio_00_aio */ 131 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_gpio_00_aio[1] = { 132 {0u, 0u, P8_0, HSIOM_SEL_GPIO}, 133 }; 134 135 /* Connections for: pass_gpio_01_aio */ 136 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_gpio_01_aio[1] = { 137 {0u, 0u, P8_2, HSIOM_SEL_GPIO}, 138 }; 139 140 /* Connections for: pass_mcpass_dclk */ 141 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_mcpass_dclk[1] = { 142 {0u, 0u, P9_2, P9_2_PASS_MCPASS_DCLK}, 143 }; 144 145 /* Connections for: pass_mcpass_dout */ 146 const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_mcpass_dout[7] = { 147 {0u, 0u, P7_0, P7_0_PASS_MCPASS_DOUT0}, 148 {0u, 1u, P7_1, P7_1_PASS_MCPASS_DOUT1}, 149 {0u, 2u, P7_2, P7_2_PASS_MCPASS_DOUT2}, 150 {0u, 0u, P8_0, P8_0_PASS_MCPASS_DOUT0}, 151 {0u, 1u, P8_1, P8_1_PASS_MCPASS_DOUT1}, 152 {0u, 2u, P8_2, P8_2_PASS_MCPASS_DOUT2}, 153 {0u, 3u, P8_3, P8_3_PASS_MCPASS_DOUT3}, 154 }; 155 156 /* Connections for: peri_tr_io_input */ 157 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 158 to know the index of the input or output trigger line. Store that in the channel_num field 159 instead. */ 160 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[29] = { 161 {0u, 0u, P0_0, P0_0_PERI_TR_IO_INPUT0}, 162 {0u, 4u, P1_2, P1_2_PERI_TR_IO_INPUT4}, 163 {0u, 5u, P1_3, P1_3_PERI_TR_IO_INPUT5}, 164 {0u, 6u, P2_0, P2_0_PERI_TR_IO_INPUT6}, 165 {0u, 7u, P2_1, P2_1_PERI_TR_IO_INPUT7}, 166 {0u, 8u, P2_2, P2_2_PERI_TR_IO_INPUT8}, 167 {0u, 9u, P2_3, P2_3_PERI_TR_IO_INPUT9}, 168 {0u, 14u, P4_0, P4_0_PERI_TR_IO_INPUT14}, 169 {0u, 15u, P4_1, P4_1_PERI_TR_IO_INPUT15}, 170 {0u, 16u, P4_2, P4_2_PERI_TR_IO_INPUT16}, 171 {0u, 17u, P4_3, P4_3_PERI_TR_IO_INPUT17}, 172 {0u, 18u, P4_4, P4_4_PERI_TR_IO_INPUT18}, 173 {0u, 19u, P4_5, P4_5_PERI_TR_IO_INPUT19}, 174 {0u, 20u, P4_6, P4_6_PERI_TR_IO_INPUT20}, 175 {0u, 21u, P4_7, P4_7_PERI_TR_IO_INPUT21}, 176 {0u, 26u, P6_0, P6_0_PERI_TR_IO_INPUT26}, 177 {0u, 27u, P6_1, P6_1_PERI_TR_IO_INPUT27}, 178 {0u, 28u, P6_2, P6_2_PERI_TR_IO_INPUT28}, 179 {0u, 29u, P6_3, P6_3_PERI_TR_IO_INPUT29}, 180 {0u, 30u, P7_0, P7_0_PERI_TR_IO_INPUT30}, 181 {0u, 31u, P7_1, P7_1_PERI_TR_IO_INPUT31}, 182 {0u, 32u, P7_2, P7_2_PERI_TR_IO_INPUT32}, 183 {0u, 38u, P8_0, P8_0_PERI_TR_IO_INPUT38}, 184 {0u, 39u, P8_1, P8_1_PERI_TR_IO_INPUT39}, 185 {0u, 40u, P8_2, P8_2_PERI_TR_IO_INPUT40}, 186 {0u, 41u, P8_3, P8_3_PERI_TR_IO_INPUT41}, 187 {0u, 44u, P9_0, P9_0_PERI_TR_IO_INPUT44}, 188 {0u, 46u, P9_2, P9_2_PERI_TR_IO_INPUT46}, 189 {0u, 47u, P9_3, P9_3_PERI_TR_IO_INPUT47}, 190 }; 191 192 /* Connections for: peri_tr_io_output */ 193 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 194 to know the index of the input or output trigger line. Store that in the channel_num field 195 instead. */ 196 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[59] = { 197 {0u, 0u, P0_0, P0_0_PERI_TR_IO_OUTPUT0}, 198 {0u, 4u, P1_2, P1_2_PERI_TR_IO_OUTPUT4}, 199 {0u, 60u, P1_2, P1_2_PERI_TR_IO_OUTPUT60}, 200 {0u, 72u, P1_2, P1_2_PERI_TR_IO_OUTPUT72}, 201 {0u, 5u, P1_3, P1_3_PERI_TR_IO_OUTPUT5}, 202 {0u, 61u, P1_3, P1_3_PERI_TR_IO_OUTPUT61}, 203 {0u, 73u, P1_3, P1_3_PERI_TR_IO_OUTPUT73}, 204 {0u, 6u, P2_0, P2_0_PERI_TR_IO_OUTPUT6}, 205 {0u, 58u, P2_0, P2_0_PERI_TR_IO_OUTPUT58}, 206 {0u, 7u, P2_1, P2_1_PERI_TR_IO_OUTPUT7}, 207 {0u, 59u, P2_1, P2_1_PERI_TR_IO_OUTPUT59}, 208 {0u, 8u, P2_2, P2_2_PERI_TR_IO_OUTPUT8}, 209 {0u, 60u, P2_2, P2_2_PERI_TR_IO_OUTPUT60}, 210 {0u, 9u, P2_3, P2_3_PERI_TR_IO_OUTPUT9}, 211 {0u, 61u, P2_3, P2_3_PERI_TR_IO_OUTPUT61}, 212 {0u, 14u, P4_0, P4_0_PERI_TR_IO_OUTPUT14}, 213 {0u, 50u, P4_0, P4_0_PERI_TR_IO_OUTPUT50}, 214 {0u, 15u, P4_1, P4_1_PERI_TR_IO_OUTPUT15}, 215 {0u, 51u, P4_1, P4_1_PERI_TR_IO_OUTPUT51}, 216 {0u, 16u, P4_2, P4_2_PERI_TR_IO_OUTPUT16}, 217 {0u, 52u, P4_2, P4_2_PERI_TR_IO_OUTPUT52}, 218 {0u, 17u, P4_3, P4_3_PERI_TR_IO_OUTPUT17}, 219 {0u, 53u, P4_3, P4_3_PERI_TR_IO_OUTPUT53}, 220 {0u, 18u, P4_4, P4_4_PERI_TR_IO_OUTPUT18}, 221 {0u, 54u, P4_4, P4_4_PERI_TR_IO_OUTPUT54}, 222 {0u, 19u, P4_5, P4_5_PERI_TR_IO_OUTPUT19}, 223 {0u, 55u, P4_5, P4_5_PERI_TR_IO_OUTPUT55}, 224 {0u, 20u, P4_6, P4_6_PERI_TR_IO_OUTPUT20}, 225 {0u, 56u, P4_6, P4_6_PERI_TR_IO_OUTPUT56}, 226 {0u, 21u, P4_7, P4_7_PERI_TR_IO_OUTPUT21}, 227 {0u, 57u, P4_7, P4_7_PERI_TR_IO_OUTPUT57}, 228 {0u, 26u, P6_0, P6_0_PERI_TR_IO_OUTPUT26}, 229 {0u, 66u, P6_0, P6_0_PERI_TR_IO_OUTPUT66}, 230 {0u, 27u, P6_1, P6_1_PERI_TR_IO_OUTPUT27}, 231 {0u, 67u, P6_1, P6_1_PERI_TR_IO_OUTPUT67}, 232 {0u, 28u, P6_2, P6_2_PERI_TR_IO_OUTPUT28}, 233 {0u, 68u, P6_2, P6_2_PERI_TR_IO_OUTPUT68}, 234 {0u, 29u, P6_3, P6_3_PERI_TR_IO_OUTPUT29}, 235 {0u, 69u, P6_3, P6_3_PERI_TR_IO_OUTPUT69}, 236 {0u, 30u, P7_0, P7_0_PERI_TR_IO_OUTPUT30}, 237 {0u, 50u, P7_0, P7_0_PERI_TR_IO_OUTPUT50}, 238 {0u, 70u, P7_0, P7_0_PERI_TR_IO_OUTPUT70}, 239 {0u, 31u, P7_1, P7_1_PERI_TR_IO_OUTPUT31}, 240 {0u, 51u, P7_1, P7_1_PERI_TR_IO_OUTPUT51}, 241 {0u, 71u, P7_1, P7_1_PERI_TR_IO_OUTPUT71}, 242 {0u, 32u, P7_2, P7_2_PERI_TR_IO_OUTPUT32}, 243 {0u, 52u, P7_2, P7_2_PERI_TR_IO_OUTPUT52}, 244 {0u, 72u, P7_2, P7_2_PERI_TR_IO_OUTPUT72}, 245 {0u, 38u, P8_0, P8_0_PERI_TR_IO_OUTPUT38}, 246 {0u, 62u, P8_0, P8_0_PERI_TR_IO_OUTPUT62}, 247 {0u, 39u, P8_1, P8_1_PERI_TR_IO_OUTPUT39}, 248 {0u, 63u, P8_1, P8_1_PERI_TR_IO_OUTPUT63}, 249 {0u, 40u, P8_2, P8_2_PERI_TR_IO_OUTPUT40}, 250 {0u, 64u, P8_2, P8_2_PERI_TR_IO_OUTPUT64}, 251 {0u, 41u, P8_3, P8_3_PERI_TR_IO_OUTPUT41}, 252 {0u, 65u, P8_3, P8_3_PERI_TR_IO_OUTPUT65}, 253 {0u, 44u, P9_0, P9_0_PERI_TR_IO_OUTPUT44}, 254 {0u, 46u, P9_2, P9_2_PERI_TR_IO_OUTPUT46}, 255 {0u, 47u, P9_3, P9_3_PERI_TR_IO_OUTPUT47}, 256 }; 257 258 /* Connections for: scb_i2c_scl */ 259 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[7] = { 260 {1u, 0u, P1_3, P1_3_SCB1_I2C_SCL}, 261 {1u, 0u, P2_1, P2_1_SCB1_I2C_SCL}, 262 {4u, 0u, P4_2, P4_2_SCB4_I2C_SCL}, 263 {3u, 0u, P6_1, P6_1_SCB3_I2C_SCL}, 264 {2u, 0u, P7_0, P7_0_SCB2_I2C_SCL}, 265 {5u, 0u, P8_1, P8_1_SCB5_I2C_SCL}, 266 {0u, 0u, P9_0, P9_0_SCB0_I2C_SCL}, 267 }; 268 269 /* Connections for: scb_i2c_sda */ 270 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[7] = { 271 {1u, 0u, P1_2, P1_2_SCB1_I2C_SDA}, 272 {1u, 0u, P2_2, P2_2_SCB1_I2C_SDA}, 273 {4u, 0u, P4_1, P4_1_SCB4_I2C_SDA}, 274 {3u, 0u, P6_0, P6_0_SCB3_I2C_SDA}, 275 {2u, 0u, P7_1, P7_1_SCB2_I2C_SDA}, 276 {5u, 0u, P8_3, P8_3_SCB5_I2C_SDA}, 277 {0u, 0u, P9_2, P9_2_SCB0_I2C_SDA}, 278 }; 279 280 /* Connections for: scb_spi_m_clk */ 281 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[6] = { 282 {1u, 0u, P2_1, P2_1_SCB1_SPI_CLK}, 283 {4u, 0u, P4_2, P4_2_SCB4_SPI_CLK}, 284 {3u, 0u, P6_2, P6_2_SCB3_SPI_CLK}, 285 {2u, 0u, P7_0, P7_0_SCB2_SPI_CLK}, 286 {5u, 0u, P8_3, P8_3_SCB5_SPI_CLK}, 287 {0u, 0u, P9_0, P9_0_SCB0_SPI_CLK}, 288 }; 289 290 /* Connections for: scb_spi_m_miso */ 291 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[7] = { 292 {1u, 0u, P1_3, P1_3_SCB1_SPI_MISO}, 293 {1u, 0u, P2_3, P2_3_SCB1_SPI_MISO}, 294 {4u, 0u, P4_1, P4_1_SCB4_SPI_MISO}, 295 {3u, 0u, P6_1, P6_1_SCB3_SPI_MISO}, 296 {2u, 0u, P7_2, P7_2_SCB2_SPI_MISO}, 297 {5u, 0u, P8_2, P8_2_SCB5_SPI_MISO}, 298 {0u, 0u, P9_3, P9_3_SCB0_SPI_MISO}, 299 }; 300 301 /* Connections for: scb_spi_m_mosi */ 302 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[7] = { 303 {1u, 0u, P1_2, P1_2_SCB1_SPI_MOSI}, 304 {1u, 0u, P2_2, P2_2_SCB1_SPI_MOSI}, 305 {4u, 0u, P4_0, P4_0_SCB4_SPI_MOSI}, 306 {3u, 0u, P6_0, P6_0_SCB3_SPI_MOSI}, 307 {2u, 0u, P7_1, P7_1_SCB2_SPI_MOSI}, 308 {5u, 0u, P8_1, P8_1_SCB5_SPI_MOSI}, 309 {0u, 0u, P9_2, P9_2_SCB0_SPI_MOSI}, 310 }; 311 312 /* Connections for: scb_spi_m_select0 */ 313 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[4] = { 314 {1u, 0u, P2_0, P2_0_SCB1_SPI_SELECT0}, 315 {4u, 0u, P4_3, P4_3_SCB4_SPI_SELECT0}, 316 {3u, 0u, P6_3, P6_3_SCB3_SPI_SELECT0}, 317 {5u, 0u, P8_0, P8_0_SCB5_SPI_SELECT0}, 318 }; 319 320 /* Connections for: scb_spi_m_select1 */ 321 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[1] = { 322 {0u, 0u, NC, HSIOM_SEL_GPIO}, 323 }; 324 325 /* Connections for: scb_spi_m_select2 */ 326 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[1] = { 327 {0u, 0u, NC, HSIOM_SEL_GPIO}, 328 }; 329 330 /* Connections for: scb_spi_s_clk */ 331 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[6] = { 332 {1u, 0u, P2_1, P2_1_SCB1_SPI_CLK}, 333 {4u, 0u, P4_2, P4_2_SCB4_SPI_CLK}, 334 {3u, 0u, P6_2, P6_2_SCB3_SPI_CLK}, 335 {2u, 0u, P7_0, P7_0_SCB2_SPI_CLK}, 336 {5u, 0u, P8_3, P8_3_SCB5_SPI_CLK}, 337 {0u, 0u, P9_0, P9_0_SCB0_SPI_CLK}, 338 }; 339 340 /* Connections for: scb_spi_s_miso */ 341 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[7] = { 342 {1u, 0u, P1_3, P1_3_SCB1_SPI_MISO}, 343 {1u, 0u, P2_3, P2_3_SCB1_SPI_MISO}, 344 {4u, 0u, P4_1, P4_1_SCB4_SPI_MISO}, 345 {3u, 0u, P6_1, P6_1_SCB3_SPI_MISO}, 346 {2u, 0u, P7_2, P7_2_SCB2_SPI_MISO}, 347 {5u, 0u, P8_2, P8_2_SCB5_SPI_MISO}, 348 {0u, 0u, P9_3, P9_3_SCB0_SPI_MISO}, 349 }; 350 351 /* Connections for: scb_spi_s_mosi */ 352 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[7] = { 353 {1u, 0u, P1_2, P1_2_SCB1_SPI_MOSI}, 354 {1u, 0u, P2_2, P2_2_SCB1_SPI_MOSI}, 355 {4u, 0u, P4_0, P4_0_SCB4_SPI_MOSI}, 356 {3u, 0u, P6_0, P6_0_SCB3_SPI_MOSI}, 357 {2u, 0u, P7_1, P7_1_SCB2_SPI_MOSI}, 358 {5u, 0u, P8_1, P8_1_SCB5_SPI_MOSI}, 359 {0u, 0u, P9_2, P9_2_SCB0_SPI_MOSI}, 360 }; 361 362 /* Connections for: scb_spi_s_select0 */ 363 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[4] = { 364 {1u, 0u, P2_0, P2_0_SCB1_SPI_SELECT0}, 365 {4u, 0u, P4_3, P4_3_SCB4_SPI_SELECT0}, 366 {3u, 0u, P6_3, P6_3_SCB3_SPI_SELECT0}, 367 {5u, 0u, P8_0, P8_0_SCB5_SPI_SELECT0}, 368 }; 369 370 /* Connections for: scb_spi_s_select1 */ 371 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[1] = { 372 {0u, 0u, NC, HSIOM_SEL_GPIO}, 373 }; 374 375 /* Connections for: scb_spi_s_select2 */ 376 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[1] = { 377 {0u, 0u, NC, HSIOM_SEL_GPIO}, 378 }; 379 380 /* Connections for: scb_uart_cts */ 381 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6] = { 382 {1u, 0u, P2_0, P2_0_SCB1_UART_CTS}, 383 {4u, 0u, P4_0, P4_0_SCB4_UART_CTS}, 384 {3u, 0u, P6_0, P6_0_SCB3_UART_CTS}, 385 {2u, 0u, P7_0, P7_0_SCB2_UART_CTS}, 386 {5u, 0u, P8_0, P8_0_SCB5_UART_CTS}, 387 {0u, 0u, P9_0, P9_0_SCB0_UART_CTS}, 388 }; 389 390 /* Connections for: scb_uart_rts */ 391 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[4] = { 392 {1u, 0u, P2_1, P2_1_SCB1_UART_RTS}, 393 {4u, 0u, P4_1, P4_1_SCB4_UART_RTS}, 394 {3u, 0u, P6_1, P6_1_SCB3_UART_RTS}, 395 {5u, 0u, P8_2, P8_2_SCB5_UART_RTS}, 396 }; 397 398 /* Connections for: scb_uart_rx */ 399 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[7] = { 400 {1u, 0u, P1_2, P1_2_SCB1_UART_RX}, 401 {1u, 0u, P2_2, P2_2_SCB1_UART_RX}, 402 {4u, 0u, P4_2, P4_2_SCB4_UART_RX}, 403 {3u, 0u, P6_2, P6_2_SCB3_UART_RX}, 404 {2u, 0u, P7_2, P7_2_SCB2_UART_RX}, 405 {5u, 0u, P8_1, P8_1_SCB5_UART_RX}, 406 {0u, 0u, P9_2, P9_2_SCB0_UART_RX}, 407 }; 408 409 /* Connections for: scb_uart_tx */ 410 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[7] = { 411 {1u, 0u, P1_3, P1_3_SCB1_UART_TX}, 412 {1u, 0u, P2_3, P2_3_SCB1_UART_TX}, 413 {4u, 0u, P4_3, P4_3_SCB4_UART_TX}, 414 {3u, 0u, P6_3, P6_3_SCB3_UART_TX}, 415 {2u, 0u, P7_1, P7_1_SCB2_UART_TX}, 416 {5u, 0u, P8_3, P8_3_SCB5_UART_TX}, 417 {0u, 0u, P9_3, P9_3_SCB0_UART_TX}, 418 }; 419 420 /* Connections for: tcpwm_line */ 421 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[14] = { 422 {2u, 6u, P2_0, P2_0_TCPWM0_LINE518}, 423 {2u, 7u, P2_2, P2_2_TCPWM0_LINE519}, 424 {1u, 4u, P4_0, P4_0_TCPWM0_LINE260}, 425 {1u, 5u, P4_2, P4_2_TCPWM0_LINE261}, 426 {1u, 6u, P4_4, P4_4_TCPWM0_LINE262}, 427 {1u, 7u, P4_6, P4_6_TCPWM0_LINE263}, 428 {1u, 4u, P6_0, P6_0_TCPWM0_LINE260}, 429 {1u, 5u, P6_2, P6_2_TCPWM0_LINE261}, 430 {1u, 6u, P7_0, P7_0_TCPWM0_LINE262}, 431 {1u, 7u, P7_2, P7_2_TCPWM0_LINE263}, 432 {2u, 4u, P8_0, P8_0_TCPWM0_LINE516}, 433 {2u, 5u, P8_2, P8_2_TCPWM0_LINE517}, 434 {2u, 6u, P9_0, P9_0_TCPWM0_LINE518}, 435 {2u, 7u, P9_2, P9_2_TCPWM0_LINE519}, 436 }; 437 438 /* Connections for: tcpwm_line_compl */ 439 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[12] = { 440 {2u, 6u, P2_1, P2_1_TCPWM0_LINE_COMPL518}, 441 {2u, 7u, P2_3, P2_3_TCPWM0_LINE_COMPL519}, 442 {1u, 4u, P4_1, P4_1_TCPWM0_LINE_COMPL260}, 443 {1u, 5u, P4_3, P4_3_TCPWM0_LINE_COMPL261}, 444 {1u, 6u, P4_5, P4_5_TCPWM0_LINE_COMPL262}, 445 {1u, 7u, P4_7, P4_7_TCPWM0_LINE_COMPL263}, 446 {1u, 4u, P6_1, P6_1_TCPWM0_LINE_COMPL260}, 447 {1u, 5u, P6_3, P6_3_TCPWM0_LINE_COMPL261}, 448 {1u, 6u, P7_1, P7_1_TCPWM0_LINE_COMPL262}, 449 {2u, 4u, P8_1, P8_1_TCPWM0_LINE_COMPL516}, 450 {2u, 5u, P8_3, P8_3_TCPWM0_LINE_COMPL517}, 451 {2u, 7u, P9_3, P9_3_TCPWM0_LINE_COMPL519}, 452 }; 453 454 #endif 455
