1 /***************************************************************************//** 2 * \file cyhal_cyw20829a0_56_qfn.c 3 * 4 * \brief 5 * CYW20829 device GPIO HAL header for 56-QFN package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_CYW20829A0_56_QFN_H_) 31 #include "pin_packages/cyhal_cyw20829a0_56_qfn.h" 32 33 /* Pin connections */ 34 /* Connections for: adcmic_clk_pdm */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_clk_pdm[2] = { 36 {0u, 0u, P3_2, P3_2_ADCMIC_CLK_PDM}, 37 {0u, 0u, P5_0, P5_0_ADCMIC_CLK_PDM}, 38 }; 39 40 /* Connections for: adcmic_gpio_adc_in */ 41 /* The actual channel_num will always be 0 for the ADCMIC. However, the ADC driver does need to 42 know the bit index on the analog_in signal. So store that in the channel_num field instead. */ 43 const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_gpio_adc_in[8] = { 44 {0u, 0u, P3_0, HSIOM_SEL_GPIO}, 45 {0u, 1u, P3_1, HSIOM_SEL_GPIO}, 46 {0u, 2u, P3_2, HSIOM_SEL_GPIO}, 47 {0u, 3u, P3_3, HSIOM_SEL_GPIO}, 48 {0u, 4u, P3_4, HSIOM_SEL_GPIO}, 49 {0u, 5u, P3_5, HSIOM_SEL_GPIO}, 50 {0u, 6u, P3_6, HSIOM_SEL_GPIO}, 51 {0u, 7u, P3_7, HSIOM_SEL_GPIO}, 52 }; 53 54 /* Connections for: adcmic_pdm_data */ 55 const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_pdm_data[2] = { 56 {0u, 0u, P3_3, P3_3_ADCMIC_PDM_DATA}, 57 {0u, 0u, P5_1, P5_1_ADCMIC_PDM_DATA}, 58 }; 59 60 /* Connections for: canfd_ttcan_rx */ 61 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1] = { 62 {0u, 0u, P3_2, P3_2_CANFD0_TTCAN_RX0}, 63 }; 64 65 /* Connections for: canfd_ttcan_tx */ 66 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1] = { 67 {0u, 0u, P3_3, P3_3_CANFD0_TTCAN_TX0}, 68 }; 69 70 /* Connections for: cpuss_clk_swj_swclk_tclk */ 71 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_swj_swclk_tclk[1] = { 72 {0u, 0u, P1_3, P1_3_CPUSS_CLK_SWJ_SWCLK_TCLK}, 73 }; 74 75 /* Connections for: cpuss_rst_swj_trstn */ 76 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_rst_swj_trstn[1] = { 77 {0u, 0u, P3_1, P3_1_CPUSS_RST_SWJ_TRSTN}, 78 }; 79 80 /* Connections for: cpuss_swj_swdio_tms */ 81 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 82 {0u, 0u, P1_2, P1_2_CPUSS_SWJ_SWDIO_TMS}, 83 }; 84 85 /* Connections for: cpuss_swj_swdoe_tdi */ 86 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 87 {0u, 0u, P1_1, P1_1_CPUSS_SWJ_SWDOE_TDI}, 88 }; 89 90 /* Connections for: cpuss_swj_swo_tdo */ 91 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 92 {0u, 0u, P1_0, P1_0_CPUSS_SWJ_SWO_TDO}, 93 }; 94 95 /* Connections for: cpuss_trace_clock */ 96 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[2] = { 97 {0u, 0u, P1_2, P1_2_CPUSS_TRACE_CLOCK}, 98 {0u, 0u, P3_4, P3_4_CPUSS_TRACE_CLOCK}, 99 }; 100 101 /* Connections for: cpuss_trace_data */ 102 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[8] = { 103 {0u, 3u, P0_4, P0_4_CPUSS_TRACE_DATA3}, 104 {0u, 2u, P0_5, P0_5_CPUSS_TRACE_DATA2}, 105 {0u, 1u, P1_0, P1_0_CPUSS_TRACE_DATA1}, 106 {0u, 0u, P1_1, P1_1_CPUSS_TRACE_DATA0}, 107 {0u, 3u, P3_0, P3_0_CPUSS_TRACE_DATA3}, 108 {0u, 2u, P3_1, P3_1_CPUSS_TRACE_DATA2}, 109 {0u, 1u, P3_2, P3_2_CPUSS_TRACE_DATA1}, 110 {0u, 0u, P3_3, P3_3_CPUSS_TRACE_DATA0}, 111 }; 112 113 /* Connections for: keyscan_ks_col */ 114 /* The actual channel_num will always be 0 for the KeyScan. However, the driver does need to know 115 the bit index on the row/column signal in order to check that the indices are contiguous and 116 start at 0. Store that in the channel_num field instead. */ 117 const cyhal_resource_pin_mapping_t cyhal_pin_map_keyscan_ks_col[20] = { 118 {0u, 3u, P0_0, P0_0_KEYSCAN_KS_COL3}, 119 {0u, 4u, P0_1, P0_1_KEYSCAN_KS_COL4}, 120 {0u, 11u, P0_2, P0_2_KEYSCAN_KS_COL11}, 121 {0u, 12u, P0_3, P0_3_KEYSCAN_KS_COL12}, 122 {0u, 17u, P1_2, P1_2_KEYSCAN_KS_COL17}, 123 {0u, 16u, P1_3, P1_3_KEYSCAN_KS_COL16}, 124 {0u, 15u, P1_4, P1_4_KEYSCAN_KS_COL15}, 125 {0u, 16u, P1_4, P1_4_KEYSCAN_KS_COL16}, 126 {0u, 5u, P1_5, P1_5_KEYSCAN_KS_COL5}, 127 {0u, 6u, P1_6, P1_6_KEYSCAN_KS_COL6}, 128 {0u, 13u, P3_2, P3_2_KEYSCAN_KS_COL13}, 129 {0u, 14u, P3_3, P3_3_KEYSCAN_KS_COL14}, 130 {0u, 17u, P3_3, P3_3_KEYSCAN_KS_COL17}, 131 {0u, 7u, P3_4, P3_4_KEYSCAN_KS_COL7}, 132 {0u, 8u, P3_5, P3_5_KEYSCAN_KS_COL8}, 133 {0u, 9u, P3_6, P3_6_KEYSCAN_KS_COL9}, 134 {0u, 10u, P3_7, P3_7_KEYSCAN_KS_COL10}, 135 {0u, 0u, P5_0, P5_0_KEYSCAN_KS_COL0}, 136 {0u, 1u, P5_1, P5_1_KEYSCAN_KS_COL1}, 137 {0u, 2u, P5_2, P5_2_KEYSCAN_KS_COL2}, 138 }; 139 140 /* Connections for: keyscan_ks_row */ 141 /* The actual channel_num will always be 0 for the KeyScan. However, the driver does need to know 142 the bit index on the row/column signal in order to check that the indices are contiguous and 143 start at 0. Store that in the channel_num field instead. */ 144 const cyhal_resource_pin_mapping_t cyhal_pin_map_keyscan_ks_row[8] = { 145 {0u, 0u, P0_4, P0_4_KEYSCAN_KS_ROW0}, 146 {0u, 1u, P0_5, P0_5_KEYSCAN_KS_ROW1}, 147 {0u, 5u, P1_0, P1_0_KEYSCAN_KS_ROW5}, 148 {0u, 6u, P1_1, P1_1_KEYSCAN_KS_ROW6}, 149 {0u, 7u, P3_0, P3_0_KEYSCAN_KS_ROW7}, 150 {0u, 4u, P3_1, P3_1_KEYSCAN_KS_ROW4}, 151 {0u, 2u, P4_0, P4_0_KEYSCAN_KS_ROW2}, 152 {0u, 3u, P4_1, P4_1_KEYSCAN_KS_ROW3}, 153 }; 154 155 /* Connections for: lin_lin_en */ 156 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[2] = { 157 {0u, 1u, P1_4, P1_4_LIN0_LIN_EN1}, 158 {0u, 0u, P3_1, P3_1_LIN0_LIN_EN0}, 159 }; 160 161 /* Connections for: lin_lin_rx */ 162 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[2] = { 163 {0u, 1u, P1_5, P1_5_LIN0_LIN_RX1}, 164 {0u, 0u, P3_2, P3_2_LIN0_LIN_RX0}, 165 }; 166 167 /* Connections for: lin_lin_tx */ 168 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[2] = { 169 {0u, 1u, P1_6, P1_6_LIN0_LIN_TX1}, 170 {0u, 0u, P3_3, P3_3_LIN0_LIN_TX0}, 171 }; 172 173 /* Connections for: pdm_pdm_clk */ 174 const cyhal_resource_pin_mapping_t cyhal_pin_map_pdm_pdm_clk[3] = { 175 {0u, 1u, P0_0, P0_0_PDM_PDM_CLK1}, 176 {0u, 0u, P3_2, P3_2_PDM_PDM_CLK0}, 177 {0u, 0u, P5_0, P5_0_PDM_PDM_CLK0}, 178 }; 179 180 /* Connections for: pdm_pdm_data */ 181 const cyhal_resource_pin_mapping_t cyhal_pin_map_pdm_pdm_data[3] = { 182 {0u, 1u, P0_1, P0_1_PDM_PDM_DATA1}, 183 {0u, 0u, P3_3, P3_3_PDM_PDM_DATA0}, 184 {0u, 0u, P5_1, P5_1_PDM_PDM_DATA0}, 185 }; 186 187 /* Connections for: peri_tr_io_input */ 188 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 189 to know the index of the input or output trigger line. Store that in the channel_num field 190 instead. */ 191 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[8] = { 192 {0u, 4u, P0_2, P0_2_PERI_TR_IO_INPUT4}, 193 {0u, 5u, P0_3, P0_3_PERI_TR_IO_INPUT5}, 194 {0u, 0u, P0_4, P0_4_PERI_TR_IO_INPUT0}, 195 {0u, 1u, P0_5, P0_5_PERI_TR_IO_INPUT1}, 196 {0u, 2u, P1_2, P1_2_PERI_TR_IO_INPUT2}, 197 {0u, 3u, P1_3, P1_3_PERI_TR_IO_INPUT3}, 198 {0u, 6u, P3_2, P3_2_PERI_TR_IO_INPUT6}, 199 {0u, 7u, P3_3, P3_3_PERI_TR_IO_INPUT7}, 200 }; 201 202 /* Connections for: peri_tr_io_output */ 203 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 204 to know the index of the input or output trigger line. Store that in the channel_num field 205 instead. */ 206 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[2] = { 207 {0u, 0u, P1_0, P1_0_PERI_TR_IO_OUTPUT0}, 208 {0u, 1u, P1_1, P1_1_PERI_TR_IO_OUTPUT1}, 209 }; 210 211 /* Connections for: scb_i2c_scl */ 212 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[4] = { 213 {0u, 0u, P0_2, P0_2_SCB0_I2C_SCL}, 214 {2u, 0u, P1_2, P1_2_SCB2_I2C_SCL}, 215 {2u, 0u, P3_2, P3_2_SCB2_I2C_SCL}, 216 {0u, 0u, P4_0, P4_0_SCB0_I2C_SCL}, 217 }; 218 219 /* Connections for: scb_i2c_sda */ 220 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[4] = { 221 {0u, 0u, P0_3, P0_3_SCB0_I2C_SDA}, 222 {2u, 0u, P1_3, P1_3_SCB2_I2C_SDA}, 223 {2u, 0u, P3_3, P3_3_SCB2_I2C_SDA}, 224 {0u, 0u, P4_1, P4_1_SCB0_I2C_SDA}, 225 }; 226 227 /* Connections for: scb_spi_m_clk */ 228 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[3] = { 229 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK}, 230 {1u, 0u, P1_1, P1_1_SCB1_SPI_CLK}, 231 {1u, 0u, P3_1, P3_1_SCB1_SPI_CLK}, 232 }; 233 234 /* Connections for: scb_spi_m_miso */ 235 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[4] = { 236 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO}, 237 {1u, 0u, P1_3, P1_3_SCB1_SPI_MISO}, 238 {1u, 0u, P3_3, P3_3_SCB1_SPI_MISO}, 239 {0u, 0u, P4_1, P4_1_SCB0_SPI_MISO}, 240 }; 241 242 /* Connections for: scb_spi_m_mosi */ 243 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[4] = { 244 {0u, 0u, P0_2, P0_2_SCB0_SPI_MOSI}, 245 {1u, 0u, P1_2, P1_2_SCB1_SPI_MOSI}, 246 {1u, 0u, P3_2, P3_2_SCB1_SPI_MOSI}, 247 {0u, 0u, P4_0, P4_0_SCB0_SPI_MOSI}, 248 }; 249 250 /* Connections for: scb_spi_m_select0 */ 251 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[4] = { 252 {1u, 0u, P1_0, P1_0_SCB1_SPI_SELECT0}, 253 {1u, 0u, P3_0, P3_0_SCB1_SPI_SELECT0}, 254 {1u, 0u, P5_0, P5_0_SCB1_SPI_SELECT0}, 255 {0u, 0u, P5_1, P5_1_SCB0_SPI_SELECT0}, 256 }; 257 258 /* Connections for: scb_spi_m_select1 */ 259 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[3] = { 260 {0u, 0u, P0_0, P0_0_SCB0_SPI_SELECT1}, 261 {1u, 0u, P0_5, P0_5_SCB1_SPI_SELECT1}, 262 {1u, 0u, P3_6, P3_6_SCB1_SPI_SELECT1}, 263 }; 264 265 /* Connections for: scb_spi_m_select2 */ 266 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[3] = { 267 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2}, 268 {1u, 0u, P0_4, P0_4_SCB1_SPI_SELECT2}, 269 {1u, 0u, P3_5, P3_5_SCB1_SPI_SELECT2}, 270 }; 271 272 /* Connections for: scb_spi_m_select3 */ 273 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[2] = { 274 {1u, 0u, P0_3, P0_3_SCB1_SPI_SELECT3}, 275 {1u, 0u, P3_4, P3_4_SCB1_SPI_SELECT3}, 276 }; 277 278 /* Connections for: scb_spi_s_clk */ 279 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[3] = { 280 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK}, 281 {1u, 0u, P1_1, P1_1_SCB1_SPI_CLK}, 282 {1u, 0u, P3_1, P3_1_SCB1_SPI_CLK}, 283 }; 284 285 /* Connections for: scb_spi_s_miso */ 286 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[4] = { 287 {0u, 0u, P0_3, P0_3_SCB0_SPI_MISO}, 288 {1u, 0u, P1_3, P1_3_SCB1_SPI_MISO}, 289 {1u, 0u, P3_3, P3_3_SCB1_SPI_MISO}, 290 {0u, 0u, P4_1, P4_1_SCB0_SPI_MISO}, 291 }; 292 293 /* Connections for: scb_spi_s_mosi */ 294 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[4] = { 295 {0u, 0u, P0_2, P0_2_SCB0_SPI_MOSI}, 296 {1u, 0u, P1_2, P1_2_SCB1_SPI_MOSI}, 297 {1u, 0u, P3_2, P3_2_SCB1_SPI_MOSI}, 298 {0u, 0u, P4_0, P4_0_SCB0_SPI_MOSI}, 299 }; 300 301 /* Connections for: scb_spi_s_select0 */ 302 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[4] = { 303 {1u, 0u, P1_0, P1_0_SCB1_SPI_SELECT0}, 304 {1u, 0u, P3_0, P3_0_SCB1_SPI_SELECT0}, 305 {1u, 0u, P5_0, P5_0_SCB1_SPI_SELECT0}, 306 {0u, 0u, P5_1, P5_1_SCB0_SPI_SELECT0}, 307 }; 308 309 /* Connections for: scb_spi_s_select1 */ 310 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[3] = { 311 {0u, 0u, P0_0, P0_0_SCB0_SPI_SELECT1}, 312 {1u, 0u, P0_5, P0_5_SCB1_SPI_SELECT1}, 313 {1u, 0u, P3_6, P3_6_SCB1_SPI_SELECT1}, 314 }; 315 316 /* Connections for: scb_spi_s_select2 */ 317 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[3] = { 318 {0u, 0u, P0_1, P0_1_SCB0_SPI_SELECT2}, 319 {1u, 0u, P0_4, P0_4_SCB1_SPI_SELECT2}, 320 {1u, 0u, P3_5, P3_5_SCB1_SPI_SELECT2}, 321 }; 322 323 /* Connections for: scb_spi_s_select3 */ 324 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[2] = { 325 {1u, 0u, P0_3, P0_3_SCB1_SPI_SELECT3}, 326 {1u, 0u, P3_4, P3_4_SCB1_SPI_SELECT3}, 327 }; 328 329 /* Connections for: scb_uart_cts */ 330 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[4] = { 331 {1u, 0u, P1_0, P1_0_SCB1_UART_CTS}, 332 {2u, 0u, P3_0, P3_0_SCB2_UART_CTS}, 333 {2u, 0u, P4_0, P4_0_SCB2_UART_CTS}, 334 {2u, 0u, P5_0, P5_0_SCB2_UART_CTS}, 335 }; 336 337 /* Connections for: scb_uart_rts */ 338 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[2] = { 339 {1u, 0u, P1_1, P1_1_SCB1_UART_RTS}, 340 {2u, 0u, P3_1, P3_1_SCB2_UART_RTS}, 341 }; 342 343 /* Connections for: scb_uart_rx */ 344 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[2] = { 345 {1u, 0u, P1_2, P1_2_SCB1_UART_RX}, 346 {2u, 0u, P3_2, P3_2_SCB2_UART_RX}, 347 }; 348 349 /* Connections for: scb_uart_tx */ 350 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[2] = { 351 {1u, 0u, P1_3, P1_3_SCB1_UART_TX}, 352 {2u, 0u, P3_3, P3_3_SCB2_UART_TX}, 353 }; 354 355 /* Connections for: smif_spi_clk */ 356 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = { 357 {0u, 0u, P2_5, P2_5_SMIF_SPIHB_CLK}, 358 }; 359 360 /* Connections for: smif_spi_data0 */ 361 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = { 362 {0u, 0u, P2_4, P2_4_SMIF_SPIHB_DATA0}, 363 }; 364 365 /* Connections for: smif_spi_data1 */ 366 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = { 367 {0u, 0u, P2_3, P2_3_SMIF_SPIHB_DATA1}, 368 }; 369 370 /* Connections for: smif_spi_data2 */ 371 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = { 372 {0u, 0u, P2_2, P2_2_SMIF_SPIHB_DATA2}, 373 }; 374 375 /* Connections for: smif_spi_data3 */ 376 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = { 377 {0u, 0u, P2_1, P2_1_SMIF_SPIHB_DATA3}, 378 }; 379 380 /* Connections for: smif_spi_select0 */ 381 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = { 382 {0u, 0u, P2_0, P2_0_SMIF_SPIHB_SELECT0}, 383 }; 384 385 /* Connections for: smif_spi_select1 */ 386 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = { 387 {0u, 0u, P0_5, P0_5_SMIF_SPIHB_SELECT1}, 388 }; 389 390 /* Connections for: tcpwm_line */ 391 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[26] = { 392 {0u, 1u, P0_1, P0_1_TCPWM0_LINE1}, 393 {1u, 0u, P0_1, P0_1_TCPWM0_LINE256}, 394 {0u, 0u, P0_3, P0_3_TCPWM0_LINE0}, 395 {1u, 1u, P0_3, P0_3_TCPWM0_LINE257}, 396 {0u, 1u, P0_5, P0_5_TCPWM0_LINE1}, 397 {1u, 2u, P0_5, P0_5_TCPWM0_LINE258}, 398 {0u, 0u, P1_1, P1_1_TCPWM0_LINE0}, 399 {1u, 3u, P1_1, P1_1_TCPWM0_LINE259}, 400 {0u, 1u, P1_3, P1_3_TCPWM0_LINE1}, 401 {1u, 4u, P1_3, P1_3_TCPWM0_LINE260}, 402 {0u, 0u, P1_5, P1_5_TCPWM0_LINE0}, 403 {1u, 5u, P1_5, P1_5_TCPWM0_LINE261}, 404 {0u, 0u, P3_0, P3_0_TCPWM0_LINE0}, 405 {1u, 0u, P3_0, P3_0_TCPWM0_LINE256}, 406 {0u, 1u, P3_2, P3_2_TCPWM0_LINE1}, 407 {1u, 1u, P3_2, P3_2_TCPWM0_LINE257}, 408 {0u, 0u, P3_4, P3_4_TCPWM0_LINE0}, 409 {1u, 2u, P3_4, P3_4_TCPWM0_LINE258}, 410 {0u, 1u, P3_6, P3_6_TCPWM0_LINE1}, 411 {1u, 3u, P3_6, P3_6_TCPWM0_LINE259}, 412 {0u, 0u, P4_1, P4_1_TCPWM0_LINE0}, 413 {1u, 6u, P4_1, P4_1_TCPWM0_LINE262}, 414 {0u, 0u, P5_0, P5_0_TCPWM0_LINE0}, 415 {1u, 4u, P5_0, P5_0_TCPWM0_LINE260}, 416 {0u, 1u, P5_2, P5_2_TCPWM0_LINE1}, 417 {1u, 5u, P5_2, P5_2_TCPWM0_LINE261}, 418 }; 419 420 /* Connections for: tcpwm_line_compl */ 421 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[26] = { 422 {0u, 0u, P0_0, P0_0_TCPWM0_LINE_COMPL0}, 423 {1u, 6u, P0_0, P0_0_TCPWM0_LINE_COMPL262}, 424 {0u, 1u, P0_2, P0_2_TCPWM0_LINE_COMPL1}, 425 {1u, 0u, P0_2, P0_2_TCPWM0_LINE_COMPL256}, 426 {0u, 0u, P0_4, P0_4_TCPWM0_LINE_COMPL0}, 427 {1u, 1u, P0_4, P0_4_TCPWM0_LINE_COMPL257}, 428 {0u, 1u, P1_0, P1_0_TCPWM0_LINE_COMPL1}, 429 {1u, 2u, P1_0, P1_0_TCPWM0_LINE_COMPL258}, 430 {0u, 0u, P1_2, P1_2_TCPWM0_LINE_COMPL0}, 431 {1u, 3u, P1_2, P1_2_TCPWM0_LINE_COMPL259}, 432 {0u, 1u, P1_4, P1_4_TCPWM0_LINE_COMPL1}, 433 {1u, 4u, P1_4, P1_4_TCPWM0_LINE_COMPL260}, 434 {0u, 0u, P1_6, P1_6_TCPWM0_LINE_COMPL0}, 435 {1u, 5u, P1_6, P1_6_TCPWM0_LINE_COMPL261}, 436 {0u, 0u, P3_1, P3_1_TCPWM0_LINE_COMPL0}, 437 {1u, 0u, P3_1, P3_1_TCPWM0_LINE_COMPL256}, 438 {0u, 1u, P3_3, P3_3_TCPWM0_LINE_COMPL1}, 439 {1u, 1u, P3_3, P3_3_TCPWM0_LINE_COMPL257}, 440 {0u, 0u, P3_5, P3_5_TCPWM0_LINE_COMPL0}, 441 {1u, 2u, P3_5, P3_5_TCPWM0_LINE_COMPL258}, 442 {0u, 1u, P3_7, P3_7_TCPWM0_LINE_COMPL1}, 443 {1u, 3u, P3_7, P3_7_TCPWM0_LINE_COMPL259}, 444 {0u, 1u, P4_0, P4_0_TCPWM0_LINE_COMPL1}, 445 {1u, 5u, P4_0, P4_0_TCPWM0_LINE_COMPL261}, 446 {0u, 0u, P5_1, P5_1_TCPWM0_LINE_COMPL0}, 447 {1u, 4u, P5_1, P5_1_TCPWM0_LINE_COMPL260}, 448 }; 449 450 /* Connections for: tdm_tdm_rx_fsync */ 451 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_fsync[1] = { 452 {0u, 0u, P0_2, P0_2_TDM_TDM_RX_FSYNC0}, 453 }; 454 455 /* Connections for: tdm_tdm_rx_mck */ 456 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_mck[1] = { 457 {0u, 0u, P0_0, P0_0_TDM_TDM_RX_MCK0}, 458 }; 459 460 /* Connections for: tdm_tdm_rx_sck */ 461 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_sck[1] = { 462 {0u, 0u, P0_1, P0_1_TDM_TDM_RX_SCK0}, 463 }; 464 465 /* Connections for: tdm_tdm_rx_sd */ 466 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_sd[1] = { 467 {0u, 0u, P0_3, P0_3_TDM_TDM_RX_SD0}, 468 }; 469 470 /* Connections for: tdm_tdm_tx_fsync */ 471 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_fsync[1] = { 472 {0u, 0u, P1_0, P1_0_TDM_TDM_TX_FSYNC0}, 473 }; 474 475 /* Connections for: tdm_tdm_tx_mck */ 476 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_mck[1] = { 477 {0u, 0u, P0_4, P0_4_TDM_TDM_TX_MCK0}, 478 }; 479 480 /* Connections for: tdm_tdm_tx_sck */ 481 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_sck[1] = { 482 {0u, 0u, P0_5, P0_5_TDM_TDM_TX_SCK0}, 483 }; 484 485 /* Connections for: tdm_tdm_tx_sd */ 486 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_sd[1] = { 487 {0u, 0u, P1_1, P1_1_TDM_TDM_TX_SD0}, 488 }; 489 490 #endif 491
