1 /***************************************************************************//** 2 * \file cyhal_cyw20829a0_40_qfn.c 3 * 4 * \brief 5 * CYW20829 device GPIO HAL header for 40-QFN package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2022), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if defined(_GPIO_CYW20829A0_40_QFN_H_) 31 #include "pin_packages/cyhal_cyw20829a0_40_qfn.h" 32 33 /* Pin connections */ 34 /* Connections for: adcmic_clk_pdm */ 35 const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_clk_pdm[2] = { 36 {0u, 0u, P3_2, P3_2_ADCMIC_CLK_PDM}, 37 {0u, 0u, P5_0, P5_0_ADCMIC_CLK_PDM}, 38 }; 39 40 /* Connections for: adcmic_gpio_adc_in */ 41 /* The actual channel_num will always be 0 for the ADCMIC. However, the ADC driver does need to 42 know the bit index on the analog_in signal. So store that in the channel_num field instead. */ 43 const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_gpio_adc_in[3] = { 44 {0u, 1u, P3_1, HSIOM_SEL_GPIO}, 45 {0u, 2u, P3_2, HSIOM_SEL_GPIO}, 46 {0u, 3u, P3_3, HSIOM_SEL_GPIO}, 47 }; 48 49 /* Connections for: adcmic_pdm_data */ 50 const cyhal_resource_pin_mapping_t cyhal_pin_map_adcmic_pdm_data[2] = { 51 {0u, 0u, P3_3, P3_3_ADCMIC_PDM_DATA}, 52 {0u, 0u, P5_1, P5_1_ADCMIC_PDM_DATA}, 53 }; 54 55 /* Connections for: canfd_ttcan_rx */ 56 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1] = { 57 {0u, 0u, P3_2, P3_2_CANFD0_TTCAN_RX0}, 58 }; 59 60 /* Connections for: canfd_ttcan_tx */ 61 const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1] = { 62 {0u, 0u, P3_3, P3_3_CANFD0_TTCAN_TX0}, 63 }; 64 65 /* Connections for: cpuss_clk_swj_swclk_tclk */ 66 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_clk_swj_swclk_tclk[1] = { 67 {0u, 0u, P1_3, P1_3_CPUSS_CLK_SWJ_SWCLK_TCLK}, 68 }; 69 70 /* Connections for: cpuss_rst_swj_trstn */ 71 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_rst_swj_trstn[1] = { 72 {0u, 0u, P3_1, P3_1_CPUSS_RST_SWJ_TRSTN}, 73 }; 74 75 /* Connections for: cpuss_swj_swdio_tms */ 76 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdio_tms[1] = { 77 {0u, 0u, P1_2, P1_2_CPUSS_SWJ_SWDIO_TMS}, 78 }; 79 80 /* Connections for: cpuss_swj_swdoe_tdi */ 81 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swdoe_tdi[1] = { 82 {0u, 0u, P1_1, P1_1_CPUSS_SWJ_SWDOE_TDI}, 83 }; 84 85 /* Connections for: cpuss_swj_swo_tdo */ 86 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_swj_swo_tdo[1] = { 87 {0u, 0u, P1_0, P1_0_CPUSS_SWJ_SWO_TDO}, 88 }; 89 90 /* Connections for: cpuss_trace_clock */ 91 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_clock[1] = { 92 {0u, 0u, P1_2, P1_2_CPUSS_TRACE_CLOCK}, 93 }; 94 95 /* Connections for: cpuss_trace_data */ 96 const cyhal_resource_pin_mapping_t cyhal_pin_map_cpuss_trace_data[7] = { 97 {0u, 3u, P0_4, P0_4_CPUSS_TRACE_DATA3}, 98 {0u, 2u, P0_5, P0_5_CPUSS_TRACE_DATA2}, 99 {0u, 1u, P1_0, P1_0_CPUSS_TRACE_DATA1}, 100 {0u, 0u, P1_1, P1_1_CPUSS_TRACE_DATA0}, 101 {0u, 2u, P3_1, P3_1_CPUSS_TRACE_DATA2}, 102 {0u, 1u, P3_2, P3_2_CPUSS_TRACE_DATA1}, 103 {0u, 0u, P3_3, P3_3_CPUSS_TRACE_DATA0}, 104 }; 105 106 /* Connections for: keyscan_ks_col */ 107 /* The actual channel_num will always be 0 for the KeyScan. However, the driver does need to know 108 the bit index on the row/column signal in order to check that the indices are contiguous and 109 start at 0. Store that in the channel_num field instead. */ 110 const cyhal_resource_pin_mapping_t cyhal_pin_map_keyscan_ks_col[2] = { 111 {0u, 0u, P5_0, P5_0_KEYSCAN_KS_COL0}, 112 {0u, 1u, P5_1, P5_1_KEYSCAN_KS_COL1}, 113 }; 114 115 /* Connections for: keyscan_ks_row */ 116 /* The actual channel_num will always be 0 for the KeyScan. However, the driver does need to know 117 the bit index on the row/column signal in order to check that the indices are contiguous and 118 start at 0. Store that in the channel_num field instead. */ 119 const cyhal_resource_pin_mapping_t cyhal_pin_map_keyscan_ks_row[7] = { 120 {0u, 0u, P0_4, P0_4_KEYSCAN_KS_ROW0}, 121 {0u, 1u, P0_5, P0_5_KEYSCAN_KS_ROW1}, 122 {0u, 5u, P1_0, P1_0_KEYSCAN_KS_ROW5}, 123 {0u, 6u, P1_1, P1_1_KEYSCAN_KS_ROW6}, 124 {0u, 4u, P3_1, P3_1_KEYSCAN_KS_ROW4}, 125 {0u, 2u, P4_0, P4_0_KEYSCAN_KS_ROW2}, 126 {0u, 3u, P4_1, P4_1_KEYSCAN_KS_ROW3}, 127 }; 128 129 /* Connections for: lin_lin_en */ 130 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_en[1] = { 131 {0u, 0u, P3_1, P3_1_LIN0_LIN_EN0}, 132 }; 133 134 /* Connections for: lin_lin_rx */ 135 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_rx[1] = { 136 {0u, 0u, P3_2, P3_2_LIN0_LIN_RX0}, 137 }; 138 139 /* Connections for: lin_lin_tx */ 140 const cyhal_resource_pin_mapping_t cyhal_pin_map_lin_lin_tx[1] = { 141 {0u, 0u, P3_3, P3_3_LIN0_LIN_TX0}, 142 }; 143 144 /* Connections for: pdm_pdm_clk */ 145 const cyhal_resource_pin_mapping_t cyhal_pin_map_pdm_pdm_clk[2] = { 146 {0u, 0u, P3_2, P3_2_PDM_PDM_CLK0}, 147 {0u, 0u, P5_0, P5_0_PDM_PDM_CLK0}, 148 }; 149 150 /* Connections for: pdm_pdm_data */ 151 const cyhal_resource_pin_mapping_t cyhal_pin_map_pdm_pdm_data[2] = { 152 {0u, 0u, P3_3, P3_3_PDM_PDM_DATA0}, 153 {0u, 0u, P5_1, P5_1_PDM_PDM_DATA0}, 154 }; 155 156 /* Connections for: peri_tr_io_input */ 157 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 158 to know the index of the input or output trigger line. Store that in the channel_num field 159 instead. */ 160 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[6] = { 161 {0u, 0u, P0_4, P0_4_PERI_TR_IO_INPUT0}, 162 {0u, 1u, P0_5, P0_5_PERI_TR_IO_INPUT1}, 163 {0u, 2u, P1_2, P1_2_PERI_TR_IO_INPUT2}, 164 {0u, 3u, P1_3, P1_3_PERI_TR_IO_INPUT3}, 165 {0u, 6u, P3_2, P3_2_PERI_TR_IO_INPUT6}, 166 {0u, 7u, P3_3, P3_3_PERI_TR_IO_INPUT7}, 167 }; 168 169 /* Connections for: peri_tr_io_output */ 170 /* The actual channel_num has no value to how the connection works. However, the HAL driver needs 171 to know the index of the input or output trigger line. Store that in the channel_num field 172 instead. */ 173 const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[2] = { 174 {0u, 0u, P1_0, P1_0_PERI_TR_IO_OUTPUT0}, 175 {0u, 1u, P1_1, P1_1_PERI_TR_IO_OUTPUT1}, 176 }; 177 178 /* Connections for: scb_i2c_scl */ 179 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[3] = { 180 {2u, 0u, P1_2, P1_2_SCB2_I2C_SCL}, 181 {2u, 0u, P3_2, P3_2_SCB2_I2C_SCL}, 182 {0u, 0u, P4_0, P4_0_SCB0_I2C_SCL}, 183 }; 184 185 /* Connections for: scb_i2c_sda */ 186 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[3] = { 187 {2u, 0u, P1_3, P1_3_SCB2_I2C_SDA}, 188 {2u, 0u, P3_3, P3_3_SCB2_I2C_SDA}, 189 {0u, 0u, P4_1, P4_1_SCB0_I2C_SDA}, 190 }; 191 192 /* Connections for: scb_spi_m_clk */ 193 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[3] = { 194 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK}, 195 {1u, 0u, P1_1, P1_1_SCB1_SPI_CLK}, 196 {1u, 0u, P3_1, P3_1_SCB1_SPI_CLK}, 197 }; 198 199 /* Connections for: scb_spi_m_miso */ 200 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[3] = { 201 {1u, 0u, P1_3, P1_3_SCB1_SPI_MISO}, 202 {1u, 0u, P3_3, P3_3_SCB1_SPI_MISO}, 203 {0u, 0u, P4_1, P4_1_SCB0_SPI_MISO}, 204 }; 205 206 /* Connections for: scb_spi_m_mosi */ 207 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[3] = { 208 {1u, 0u, P1_2, P1_2_SCB1_SPI_MOSI}, 209 {1u, 0u, P3_2, P3_2_SCB1_SPI_MOSI}, 210 {0u, 0u, P4_0, P4_0_SCB0_SPI_MOSI}, 211 }; 212 213 /* Connections for: scb_spi_m_select0 */ 214 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[3] = { 215 {1u, 0u, P1_0, P1_0_SCB1_SPI_SELECT0}, 216 {1u, 0u, P5_0, P5_0_SCB1_SPI_SELECT0}, 217 {0u, 0u, P5_1, P5_1_SCB0_SPI_SELECT0}, 218 }; 219 220 /* Connections for: scb_spi_m_select1 */ 221 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[1] = { 222 {1u, 0u, P0_5, P0_5_SCB1_SPI_SELECT1}, 223 }; 224 225 /* Connections for: scb_spi_m_select2 */ 226 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[1] = { 227 {1u, 0u, P0_4, P0_4_SCB1_SPI_SELECT2}, 228 }; 229 230 /* Connections for: scb_spi_m_select3 */ 231 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[1] = { 232 {0u, 0u, NC, HSIOM_SEL_GPIO}, 233 }; 234 235 /* Connections for: scb_spi_s_clk */ 236 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[3] = { 237 {0u, 0u, P0_4, P0_4_SCB0_SPI_CLK}, 238 {1u, 0u, P1_1, P1_1_SCB1_SPI_CLK}, 239 {1u, 0u, P3_1, P3_1_SCB1_SPI_CLK}, 240 }; 241 242 /* Connections for: scb_spi_s_miso */ 243 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[3] = { 244 {1u, 0u, P1_3, P1_3_SCB1_SPI_MISO}, 245 {1u, 0u, P3_3, P3_3_SCB1_SPI_MISO}, 246 {0u, 0u, P4_1, P4_1_SCB0_SPI_MISO}, 247 }; 248 249 /* Connections for: scb_spi_s_mosi */ 250 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[3] = { 251 {1u, 0u, P1_2, P1_2_SCB1_SPI_MOSI}, 252 {1u, 0u, P3_2, P3_2_SCB1_SPI_MOSI}, 253 {0u, 0u, P4_0, P4_0_SCB0_SPI_MOSI}, 254 }; 255 256 /* Connections for: scb_spi_s_select0 */ 257 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[3] = { 258 {1u, 0u, P1_0, P1_0_SCB1_SPI_SELECT0}, 259 {1u, 0u, P5_0, P5_0_SCB1_SPI_SELECT0}, 260 {0u, 0u, P5_1, P5_1_SCB0_SPI_SELECT0}, 261 }; 262 263 /* Connections for: scb_spi_s_select1 */ 264 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[1] = { 265 {1u, 0u, P0_5, P0_5_SCB1_SPI_SELECT1}, 266 }; 267 268 /* Connections for: scb_spi_s_select2 */ 269 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[1] = { 270 {1u, 0u, P0_4, P0_4_SCB1_SPI_SELECT2}, 271 }; 272 273 /* Connections for: scb_spi_s_select3 */ 274 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[1] = { 275 {0u, 0u, NC, HSIOM_SEL_GPIO}, 276 }; 277 278 /* Connections for: scb_uart_cts */ 279 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[3] = { 280 {1u, 0u, P1_0, P1_0_SCB1_UART_CTS}, 281 {2u, 0u, P4_0, P4_0_SCB2_UART_CTS}, 282 {2u, 0u, P5_0, P5_0_SCB2_UART_CTS}, 283 }; 284 285 /* Connections for: scb_uart_rts */ 286 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[2] = { 287 {1u, 0u, P1_1, P1_1_SCB1_UART_RTS}, 288 {2u, 0u, P3_1, P3_1_SCB2_UART_RTS}, 289 }; 290 291 /* Connections for: scb_uart_rx */ 292 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[2] = { 293 {1u, 0u, P1_2, P1_2_SCB1_UART_RX}, 294 {2u, 0u, P3_2, P3_2_SCB2_UART_RX}, 295 }; 296 297 /* Connections for: scb_uart_tx */ 298 const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[2] = { 299 {1u, 0u, P1_3, P1_3_SCB1_UART_TX}, 300 {2u, 0u, P3_3, P3_3_SCB2_UART_TX}, 301 }; 302 303 /* Connections for: smif_spi_clk */ 304 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = { 305 {0u, 0u, P2_5, P2_5_SMIF_SPIHB_CLK}, 306 }; 307 308 /* Connections for: smif_spi_data0 */ 309 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = { 310 {0u, 0u, P2_4, P2_4_SMIF_SPIHB_DATA0}, 311 }; 312 313 /* Connections for: smif_spi_data1 */ 314 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = { 315 {0u, 0u, P2_3, P2_3_SMIF_SPIHB_DATA1}, 316 }; 317 318 /* Connections for: smif_spi_data2 */ 319 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = { 320 {0u, 0u, P2_2, P2_2_SMIF_SPIHB_DATA2}, 321 }; 322 323 /* Connections for: smif_spi_data3 */ 324 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = { 325 {0u, 0u, P2_1, P2_1_SMIF_SPIHB_DATA3}, 326 }; 327 328 /* Connections for: smif_spi_select0 */ 329 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = { 330 {0u, 0u, P2_0, P2_0_SMIF_SPIHB_SELECT0}, 331 }; 332 333 /* Connections for: smif_spi_select1 */ 334 const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = { 335 {0u, 0u, P0_5, P0_5_SMIF_SPIHB_SELECT1}, 336 }; 337 338 /* Connections for: tcpwm_line */ 339 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[12] = { 340 {0u, 1u, P0_5, P0_5_TCPWM0_LINE1}, 341 {1u, 2u, P0_5, P0_5_TCPWM0_LINE258}, 342 {0u, 0u, P1_1, P1_1_TCPWM0_LINE0}, 343 {1u, 3u, P1_1, P1_1_TCPWM0_LINE259}, 344 {0u, 1u, P1_3, P1_3_TCPWM0_LINE1}, 345 {1u, 4u, P1_3, P1_3_TCPWM0_LINE260}, 346 {0u, 1u, P3_2, P3_2_TCPWM0_LINE1}, 347 {1u, 1u, P3_2, P3_2_TCPWM0_LINE257}, 348 {0u, 0u, P4_1, P4_1_TCPWM0_LINE0}, 349 {1u, 6u, P4_1, P4_1_TCPWM0_LINE262}, 350 {0u, 0u, P5_0, P5_0_TCPWM0_LINE0}, 351 {1u, 4u, P5_0, P5_0_TCPWM0_LINE260}, 352 }; 353 354 /* Connections for: tcpwm_line_compl */ 355 const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[14] = { 356 {0u, 0u, P0_4, P0_4_TCPWM0_LINE_COMPL0}, 357 {1u, 1u, P0_4, P0_4_TCPWM0_LINE_COMPL257}, 358 {0u, 1u, P1_0, P1_0_TCPWM0_LINE_COMPL1}, 359 {1u, 2u, P1_0, P1_0_TCPWM0_LINE_COMPL258}, 360 {0u, 0u, P1_2, P1_2_TCPWM0_LINE_COMPL0}, 361 {1u, 3u, P1_2, P1_2_TCPWM0_LINE_COMPL259}, 362 {0u, 0u, P3_1, P3_1_TCPWM0_LINE_COMPL0}, 363 {1u, 0u, P3_1, P3_1_TCPWM0_LINE_COMPL256}, 364 {0u, 1u, P3_3, P3_3_TCPWM0_LINE_COMPL1}, 365 {1u, 1u, P3_3, P3_3_TCPWM0_LINE_COMPL257}, 366 {0u, 1u, P4_0, P4_0_TCPWM0_LINE_COMPL1}, 367 {1u, 5u, P4_0, P4_0_TCPWM0_LINE_COMPL261}, 368 {0u, 0u, P5_1, P5_1_TCPWM0_LINE_COMPL0}, 369 {1u, 4u, P5_1, P5_1_TCPWM0_LINE_COMPL260}, 370 }; 371 372 /* Connections for: tdm_tdm_rx_fsync */ 373 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_fsync[1] = { 374 {0u, 0u, NC, HSIOM_SEL_GPIO}, 375 }; 376 377 /* Connections for: tdm_tdm_rx_mck */ 378 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_mck[1] = { 379 {0u, 0u, NC, HSIOM_SEL_GPIO}, 380 }; 381 382 /* Connections for: tdm_tdm_rx_sck */ 383 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_sck[1] = { 384 {0u, 0u, NC, HSIOM_SEL_GPIO}, 385 }; 386 387 /* Connections for: tdm_tdm_rx_sd */ 388 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_rx_sd[1] = { 389 {0u, 0u, NC, HSIOM_SEL_GPIO}, 390 }; 391 392 /* Connections for: tdm_tdm_tx_fsync */ 393 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_fsync[1] = { 394 {0u, 0u, P1_0, P1_0_TDM_TDM_TX_FSYNC0}, 395 }; 396 397 /* Connections for: tdm_tdm_tx_mck */ 398 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_mck[1] = { 399 {0u, 0u, P0_4, P0_4_TDM_TDM_TX_MCK0}, 400 }; 401 402 /* Connections for: tdm_tdm_tx_sck */ 403 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_sck[1] = { 404 {0u, 0u, P0_5, P0_5_TDM_TDM_TX_SCK0}, 405 }; 406 407 /* Connections for: tdm_tdm_tx_sd */ 408 const cyhal_resource_pin_mapping_t cyhal_pin_map_tdm_tdm_tx_sd[1] = { 409 {0u, 0u, P1_1, P1_1_TDM_TDM_TX_SD0}, 410 }; 411 412 #endif 413
