1 /***************************************************************************//** 2 * \file cyhal_triggers_psc3.h 3 * 4 * \brief 5 * PSC3 family HAL triggers header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYHAL_TRIGGERS_PSC3_H_ 28 #define _CYHAL_TRIGGERS_PSC3_H_ 29 30 /** 31 * \addtogroup group_hal_impl_triggers_psc3 PSC3 32 * \ingroup group_hal_impl_triggers 33 * \{ 34 * Trigger connections for psc3 35 */ 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif /* __cplusplus */ 40 41 /** \cond INTERNAL */ 42 /** @brief Name of each input trigger. */ 43 typedef enum 44 { 45 _CYHAL_TRIGGER_CPUSS_ZERO = 0, //!< cpuss.zero 46 _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0 = 1, //!< canfd[0].tr_dbg_dma_req[0] 47 _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1 = 2, //!< canfd[0].tr_dbg_dma_req[1] 48 _CYHAL_TRIGGER_CANFD0_TR_FIFO00 = 3, //!< canfd[0].tr_fifo0[0] 49 _CYHAL_TRIGGER_CANFD0_TR_FIFO01 = 4, //!< canfd[0].tr_fifo0[1] 50 _CYHAL_TRIGGER_CANFD0_TR_FIFO10 = 5, //!< canfd[0].tr_fifo1[0] 51 _CYHAL_TRIGGER_CANFD0_TR_FIFO11 = 6, //!< canfd[0].tr_fifo1[1] 52 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0 = 7, //!< canfd[0].tr_tmp_rtp_out[0] 53 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1 = 8, //!< canfd[0].tr_tmp_rtp_out[1] 54 _CYHAL_TRIGGER_CORDIC0_TR_DONE_MXCORDIC = 9, //!< cordic[0].tr_done_mxcordic 55 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = 10, //!< cpuss.dw0_tr_out[0] 56 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = 11, //!< cpuss.dw0_tr_out[1] 57 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = 12, //!< cpuss.dw0_tr_out[2] 58 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = 13, //!< cpuss.dw0_tr_out[3] 59 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = 14, //!< cpuss.dw0_tr_out[4] 60 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = 15, //!< cpuss.dw0_tr_out[5] 61 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = 16, //!< cpuss.dw0_tr_out[6] 62 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = 17, //!< cpuss.dw0_tr_out[7] 63 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = 18, //!< cpuss.dw0_tr_out[8] 64 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = 19, //!< cpuss.dw0_tr_out[9] 65 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = 20, //!< cpuss.dw0_tr_out[10] 66 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = 21, //!< cpuss.dw0_tr_out[11] 67 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = 22, //!< cpuss.dw0_tr_out[12] 68 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = 23, //!< cpuss.dw0_tr_out[13] 69 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = 24, //!< cpuss.dw0_tr_out[14] 70 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = 25, //!< cpuss.dw0_tr_out[15] 71 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = 26, //!< cpuss.dw1_tr_out[0] 72 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = 27, //!< cpuss.dw1_tr_out[1] 73 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = 28, //!< cpuss.dw1_tr_out[2] 74 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = 29, //!< cpuss.dw1_tr_out[3] 75 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = 30, //!< cpuss.dw1_tr_out[4] 76 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = 31, //!< cpuss.dw1_tr_out[5] 77 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = 32, //!< cpuss.dw1_tr_out[6] 78 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = 33, //!< cpuss.dw1_tr_out[7] 79 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = 34, //!< cpuss.dw1_tr_out[8] 80 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = 35, //!< cpuss.dw1_tr_out[9] 81 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = 36, //!< cpuss.dw1_tr_out[10] 82 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = 37, //!< cpuss.dw1_tr_out[11] 83 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = 38, //!< cpuss.dw1_tr_out[12] 84 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = 39, //!< cpuss.dw1_tr_out[13] 85 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = 40, //!< cpuss.dw1_tr_out[14] 86 _CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = 41, //!< cpuss.dw1_tr_out[15] 87 _CYHAL_TRIGGER_CPUSS_TR_FAULT0 = 42, //!< cpuss.tr_fault[0] 88 _CYHAL_TRIGGER_CRYPTOLITE_TR_TRNG_BITSTREAM = 43, //!< cryptolite.tr_trng_bitstream 89 _CYHAL_TRIGGER_DEBUG600_CTI_TR_OUT0 = 44, //!< debug600.cti_tr_out[0] 90 _CYHAL_TRIGGER_DEBUG600_CTI_TR_OUT1 = 45, //!< debug600.cti_tr_out[1] 91 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0 = 46, //!< ioss.peri_tr_io_input_in[0] 92 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1 = 47, //!< ioss.peri_tr_io_input_in[1] 93 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2 = 48, //!< ioss.peri_tr_io_input_in[2] 94 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3 = 49, //!< ioss.peri_tr_io_input_in[3] 95 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4 = 50, //!< ioss.peri_tr_io_input_in[4] 96 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5 = 51, //!< ioss.peri_tr_io_input_in[5] 97 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6 = 52, //!< ioss.peri_tr_io_input_in[6] 98 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7 = 53, //!< ioss.peri_tr_io_input_in[7] 99 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN8 = 54, //!< ioss.peri_tr_io_input_in[8] 100 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN9 = 55, //!< ioss.peri_tr_io_input_in[9] 101 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN10 = 56, //!< ioss.peri_tr_io_input_in[10] 102 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN11 = 57, //!< ioss.peri_tr_io_input_in[11] 103 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN12 = 58, //!< ioss.peri_tr_io_input_in[12] 104 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN13 = 59, //!< ioss.peri_tr_io_input_in[13] 105 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN14 = 60, //!< ioss.peri_tr_io_input_in[14] 106 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN15 = 61, //!< ioss.peri_tr_io_input_in[15] 107 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN16 = 62, //!< ioss.peri_tr_io_input_in[16] 108 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN17 = 63, //!< ioss.peri_tr_io_input_in[17] 109 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN18 = 64, //!< ioss.peri_tr_io_input_in[18] 110 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN19 = 65, //!< ioss.peri_tr_io_input_in[19] 111 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN20 = 66, //!< ioss.peri_tr_io_input_in[20] 112 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN21 = 67, //!< ioss.peri_tr_io_input_in[21] 113 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN22 = 68, //!< ioss.peri_tr_io_input_in[22] 114 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN23 = 69, //!< ioss.peri_tr_io_input_in[23] 115 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN24 = 70, //!< ioss.peri_tr_io_input_in[24] 116 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN25 = 71, //!< ioss.peri_tr_io_input_in[25] 117 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN26 = 72, //!< ioss.peri_tr_io_input_in[26] 118 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN27 = 73, //!< ioss.peri_tr_io_input_in[27] 119 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN28 = 74, //!< ioss.peri_tr_io_input_in[28] 120 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN29 = 75, //!< ioss.peri_tr_io_input_in[29] 121 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN30 = 76, //!< ioss.peri_tr_io_input_in[30] 122 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN31 = 77, //!< ioss.peri_tr_io_input_in[31] 123 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN32 = 78, //!< ioss.peri_tr_io_input_in[32] 124 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN33 = 79, //!< ioss.peri_tr_io_input_in[33] 125 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN34 = 80, //!< ioss.peri_tr_io_input_in[34] 126 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN35 = 81, //!< ioss.peri_tr_io_input_in[35] 127 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN36 = 82, //!< ioss.peri_tr_io_input_in[36] 128 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN37 = 83, //!< ioss.peri_tr_io_input_in[37] 129 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN38 = 84, //!< ioss.peri_tr_io_input_in[38] 130 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN39 = 85, //!< ioss.peri_tr_io_input_in[39] 131 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN40 = 86, //!< ioss.peri_tr_io_input_in[40] 132 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN41 = 87, //!< ioss.peri_tr_io_input_in[41] 133 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN42 = 88, //!< ioss.peri_tr_io_input_in[42] 134 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN43 = 89, //!< ioss.peri_tr_io_input_in[43] 135 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN44 = 90, //!< ioss.peri_tr_io_input_in[44] 136 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN45 = 91, //!< ioss.peri_tr_io_input_in[45] 137 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN46 = 92, //!< ioss.peri_tr_io_input_in[46] 138 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN47 = 93, //!< ioss.peri_tr_io_input_in[47] 139 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN48 = 94, //!< ioss.peri_tr_io_input_in[48] 140 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN49 = 95, //!< ioss.peri_tr_io_input_in[49] 141 _CYHAL_TRIGGER_LPCOMP_DSI_COMP0 = 96, //!< lpcomp.dsi_comp0 142 _CYHAL_TRIGGER_LPCOMP_DSI_COMP1 = 97, //!< lpcomp.dsi_comp1 143 _CYHAL_TRIGGER_PASS_TR_FIFO_LEVEL_OUT0 = 98, //!< pass.tr_fifo_level_out[0] 144 _CYHAL_TRIGGER_PASS_TR_FIFO_LEVEL_OUT1 = 99, //!< pass.tr_fifo_level_out[1] 145 _CYHAL_TRIGGER_PASS_TR_FIFO_LEVEL_OUT2 = 100, //!< pass.tr_fifo_level_out[2] 146 _CYHAL_TRIGGER_PASS_TR_FIFO_LEVEL_OUT3 = 101, //!< pass.tr_fifo_level_out[3] 147 _CYHAL_TRIGGER_PASS_TR_LEVEL_OUT0 = 102, //!< pass.tr_level_out[0] 148 _CYHAL_TRIGGER_PASS_TR_LEVEL_OUT1 = 103, //!< pass.tr_level_out[1] 149 _CYHAL_TRIGGER_PASS_TR_LEVEL_OUT2 = 104, //!< pass.tr_level_out[2] 150 _CYHAL_TRIGGER_PASS_TR_LEVEL_OUT3 = 105, //!< pass.tr_level_out[3] 151 _CYHAL_TRIGGER_PASS_TR_LEVEL_OUT4 = 106, //!< pass.tr_level_out[4] 152 _CYHAL_TRIGGER_PASS_TR_LEVEL_OUT5 = 107, //!< pass.tr_level_out[5] 153 _CYHAL_TRIGGER_PASS_TR_LEVEL_OUT6 = 108, //!< pass.tr_level_out[6] 154 _CYHAL_TRIGGER_PASS_TR_LEVEL_OUT7 = 109, //!< pass.tr_level_out[7] 155 _CYHAL_TRIGGER_PASS_TR_PULSE_OUT0 = 110, //!< pass.tr_pulse_out[0] 156 _CYHAL_TRIGGER_PASS_TR_PULSE_OUT1 = 111, //!< pass.tr_pulse_out[1] 157 _CYHAL_TRIGGER_PASS_TR_PULSE_OUT2 = 112, //!< pass.tr_pulse_out[2] 158 _CYHAL_TRIGGER_PASS_TR_PULSE_OUT3 = 113, //!< pass.tr_pulse_out[3] 159 _CYHAL_TRIGGER_PASS_TR_PULSE_OUT4 = 114, //!< pass.tr_pulse_out[4] 160 _CYHAL_TRIGGER_PASS_TR_PULSE_OUT5 = 115, //!< pass.tr_pulse_out[5] 161 _CYHAL_TRIGGER_PASS_TR_PULSE_OUT6 = 116, //!< pass.tr_pulse_out[6] 162 _CYHAL_TRIGGER_PASS_TR_PULSE_OUT7 = 117, //!< pass.tr_pulse_out[7] 163 _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = 118, //!< scb[0].tr_i2c_scl_filtered 164 _CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = 119, //!< scb[1].tr_i2c_scl_filtered 165 _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = 120, //!< scb[2].tr_i2c_scl_filtered 166 _CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = 121, //!< scb[3].tr_i2c_scl_filtered 167 _CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = 122, //!< scb[4].tr_i2c_scl_filtered 168 _CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = 123, //!< scb[5].tr_i2c_scl_filtered 169 _CYHAL_TRIGGER_SCB0_TR_RX_REQ = 124, //!< scb[0].tr_rx_req 170 _CYHAL_TRIGGER_SCB1_TR_RX_REQ = 125, //!< scb[1].tr_rx_req 171 _CYHAL_TRIGGER_SCB2_TR_RX_REQ = 126, //!< scb[2].tr_rx_req 172 _CYHAL_TRIGGER_SCB3_TR_RX_REQ = 127, //!< scb[3].tr_rx_req 173 _CYHAL_TRIGGER_SCB4_TR_RX_REQ = 128, //!< scb[4].tr_rx_req 174 _CYHAL_TRIGGER_SCB5_TR_RX_REQ = 129, //!< scb[5].tr_rx_req 175 _CYHAL_TRIGGER_SCB0_TR_TX_REQ = 130, //!< scb[0].tr_tx_req 176 _CYHAL_TRIGGER_SCB1_TR_TX_REQ = 131, //!< scb[1].tr_tx_req 177 _CYHAL_TRIGGER_SCB2_TR_TX_REQ = 132, //!< scb[2].tr_tx_req 178 _CYHAL_TRIGGER_SCB3_TR_TX_REQ = 133, //!< scb[3].tr_tx_req 179 _CYHAL_TRIGGER_SCB4_TR_TX_REQ = 134, //!< scb[4].tr_tx_req 180 _CYHAL_TRIGGER_SCB5_TR_TX_REQ = 135, //!< scb[5].tr_tx_req 181 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL0 = 136, //!< tcpwm[0].tr_line_compl[0] 182 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL1 = 137, //!< tcpwm[0].tr_line_compl[1] 183 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL2 = 138, //!< tcpwm[0].tr_line_compl[2] 184 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL3 = 139, //!< tcpwm[0].tr_line_compl[3] 185 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL256 = 140, //!< tcpwm[0].tr_line_compl[256] 186 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL257 = 141, //!< tcpwm[0].tr_line_compl[257] 187 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL258 = 142, //!< tcpwm[0].tr_line_compl[258] 188 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL259 = 143, //!< tcpwm[0].tr_line_compl[259] 189 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL260 = 144, //!< tcpwm[0].tr_line_compl[260] 190 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL261 = 145, //!< tcpwm[0].tr_line_compl[261] 191 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL262 = 146, //!< tcpwm[0].tr_line_compl[262] 192 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL263 = 147, //!< tcpwm[0].tr_line_compl[263] 193 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL512 = 148, //!< tcpwm[0].tr_line_compl[512] 194 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL513 = 149, //!< tcpwm[0].tr_line_compl[513] 195 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL514 = 150, //!< tcpwm[0].tr_line_compl[514] 196 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL515 = 151, //!< tcpwm[0].tr_line_compl[515] 197 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL516 = 152, //!< tcpwm[0].tr_line_compl[516] 198 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL517 = 153, //!< tcpwm[0].tr_line_compl[517] 199 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL518 = 154, //!< tcpwm[0].tr_line_compl[518] 200 _CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL519 = 155, //!< tcpwm[0].tr_line_compl[519] 201 _CYHAL_TRIGGER_TCPWM0_TR_LINE0 = 156, //!< tcpwm[0].tr_line[0] 202 _CYHAL_TRIGGER_TCPWM0_TR_LINE1 = 157, //!< tcpwm[0].tr_line[1] 203 _CYHAL_TRIGGER_TCPWM0_TR_LINE2 = 158, //!< tcpwm[0].tr_line[2] 204 _CYHAL_TRIGGER_TCPWM0_TR_LINE3 = 159, //!< tcpwm[0].tr_line[3] 205 _CYHAL_TRIGGER_TCPWM0_TR_LINE256 = 160, //!< tcpwm[0].tr_line[256] 206 _CYHAL_TRIGGER_TCPWM0_TR_LINE257 = 161, //!< tcpwm[0].tr_line[257] 207 _CYHAL_TRIGGER_TCPWM0_TR_LINE258 = 162, //!< tcpwm[0].tr_line[258] 208 _CYHAL_TRIGGER_TCPWM0_TR_LINE259 = 163, //!< tcpwm[0].tr_line[259] 209 _CYHAL_TRIGGER_TCPWM0_TR_LINE260 = 164, //!< tcpwm[0].tr_line[260] 210 _CYHAL_TRIGGER_TCPWM0_TR_LINE261 = 165, //!< tcpwm[0].tr_line[261] 211 _CYHAL_TRIGGER_TCPWM0_TR_LINE262 = 166, //!< tcpwm[0].tr_line[262] 212 _CYHAL_TRIGGER_TCPWM0_TR_LINE263 = 167, //!< tcpwm[0].tr_line[263] 213 _CYHAL_TRIGGER_TCPWM0_TR_LINE512 = 168, //!< tcpwm[0].tr_line[512] 214 _CYHAL_TRIGGER_TCPWM0_TR_LINE513 = 169, //!< tcpwm[0].tr_line[513] 215 _CYHAL_TRIGGER_TCPWM0_TR_LINE514 = 170, //!< tcpwm[0].tr_line[514] 216 _CYHAL_TRIGGER_TCPWM0_TR_LINE515 = 171, //!< tcpwm[0].tr_line[515] 217 _CYHAL_TRIGGER_TCPWM0_TR_LINE516 = 172, //!< tcpwm[0].tr_line[516] 218 _CYHAL_TRIGGER_TCPWM0_TR_LINE517 = 173, //!< tcpwm[0].tr_line[517] 219 _CYHAL_TRIGGER_TCPWM0_TR_LINE518 = 174, //!< tcpwm[0].tr_line[518] 220 _CYHAL_TRIGGER_TCPWM0_TR_LINE519 = 175, //!< tcpwm[0].tr_line[519] 221 _CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT256 = 176, //!< tcpwm[0].tr_motif_out[256] 222 _CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT257 = 177, //!< tcpwm[0].tr_motif_out[257] 223 _CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT258 = 178, //!< tcpwm[0].tr_motif_out[258] 224 _CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT259 = 179, //!< tcpwm[0].tr_motif_out[259] 225 _CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT260 = 180, //!< tcpwm[0].tr_motif_out[260] 226 _CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT261 = 181, //!< tcpwm[0].tr_motif_out[261] 227 _CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT262 = 182, //!< tcpwm[0].tr_motif_out[262] 228 _CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT263 = 183, //!< tcpwm[0].tr_motif_out[263] 229 _CYHAL_TRIGGER_TCPWM0_TR_OUT00 = 184, //!< tcpwm[0].tr_out0[0] 230 _CYHAL_TRIGGER_TCPWM0_TR_OUT01 = 185, //!< tcpwm[0].tr_out0[1] 231 _CYHAL_TRIGGER_TCPWM0_TR_OUT02 = 186, //!< tcpwm[0].tr_out0[2] 232 _CYHAL_TRIGGER_TCPWM0_TR_OUT03 = 187, //!< tcpwm[0].tr_out0[3] 233 _CYHAL_TRIGGER_TCPWM0_TR_OUT0256 = 188, //!< tcpwm[0].tr_out0[256] 234 _CYHAL_TRIGGER_TCPWM0_TR_OUT0257 = 189, //!< tcpwm[0].tr_out0[257] 235 _CYHAL_TRIGGER_TCPWM0_TR_OUT0258 = 190, //!< tcpwm[0].tr_out0[258] 236 _CYHAL_TRIGGER_TCPWM0_TR_OUT0259 = 191, //!< tcpwm[0].tr_out0[259] 237 _CYHAL_TRIGGER_TCPWM0_TR_OUT0260 = 192, //!< tcpwm[0].tr_out0[260] 238 _CYHAL_TRIGGER_TCPWM0_TR_OUT0261 = 193, //!< tcpwm[0].tr_out0[261] 239 _CYHAL_TRIGGER_TCPWM0_TR_OUT0262 = 194, //!< tcpwm[0].tr_out0[262] 240 _CYHAL_TRIGGER_TCPWM0_TR_OUT0263 = 195, //!< tcpwm[0].tr_out0[263] 241 _CYHAL_TRIGGER_TCPWM0_TR_OUT0512 = 196, //!< tcpwm[0].tr_out0[512] 242 _CYHAL_TRIGGER_TCPWM0_TR_OUT0513 = 197, //!< tcpwm[0].tr_out0[513] 243 _CYHAL_TRIGGER_TCPWM0_TR_OUT0514 = 198, //!< tcpwm[0].tr_out0[514] 244 _CYHAL_TRIGGER_TCPWM0_TR_OUT0515 = 199, //!< tcpwm[0].tr_out0[515] 245 _CYHAL_TRIGGER_TCPWM0_TR_OUT0516 = 200, //!< tcpwm[0].tr_out0[516] 246 _CYHAL_TRIGGER_TCPWM0_TR_OUT0517 = 201, //!< tcpwm[0].tr_out0[517] 247 _CYHAL_TRIGGER_TCPWM0_TR_OUT0518 = 202, //!< tcpwm[0].tr_out0[518] 248 _CYHAL_TRIGGER_TCPWM0_TR_OUT0519 = 203, //!< tcpwm[0].tr_out0[519] 249 _CYHAL_TRIGGER_TCPWM0_TR_OUT10 = 204, //!< tcpwm[0].tr_out1[0] 250 _CYHAL_TRIGGER_TCPWM0_TR_OUT11 = 205, //!< tcpwm[0].tr_out1[1] 251 _CYHAL_TRIGGER_TCPWM0_TR_OUT12 = 206, //!< tcpwm[0].tr_out1[2] 252 _CYHAL_TRIGGER_TCPWM0_TR_OUT13 = 207, //!< tcpwm[0].tr_out1[3] 253 _CYHAL_TRIGGER_TCPWM0_TR_OUT1256 = 208, //!< tcpwm[0].tr_out1[256] 254 _CYHAL_TRIGGER_TCPWM0_TR_OUT1257 = 209, //!< tcpwm[0].tr_out1[257] 255 _CYHAL_TRIGGER_TCPWM0_TR_OUT1258 = 210, //!< tcpwm[0].tr_out1[258] 256 _CYHAL_TRIGGER_TCPWM0_TR_OUT1259 = 211, //!< tcpwm[0].tr_out1[259] 257 _CYHAL_TRIGGER_TCPWM0_TR_OUT1260 = 212, //!< tcpwm[0].tr_out1[260] 258 _CYHAL_TRIGGER_TCPWM0_TR_OUT1261 = 213, //!< tcpwm[0].tr_out1[261] 259 _CYHAL_TRIGGER_TCPWM0_TR_OUT1262 = 214, //!< tcpwm[0].tr_out1[262] 260 _CYHAL_TRIGGER_TCPWM0_TR_OUT1263 = 215, //!< tcpwm[0].tr_out1[263] 261 _CYHAL_TRIGGER_TCPWM0_TR_OUT1512 = 216, //!< tcpwm[0].tr_out1[512] 262 _CYHAL_TRIGGER_TCPWM0_TR_OUT1513 = 217, //!< tcpwm[0].tr_out1[513] 263 _CYHAL_TRIGGER_TCPWM0_TR_OUT1514 = 218, //!< tcpwm[0].tr_out1[514] 264 _CYHAL_TRIGGER_TCPWM0_TR_OUT1515 = 219, //!< tcpwm[0].tr_out1[515] 265 _CYHAL_TRIGGER_TCPWM0_TR_OUT1516 = 220, //!< tcpwm[0].tr_out1[516] 266 _CYHAL_TRIGGER_TCPWM0_TR_OUT1517 = 221, //!< tcpwm[0].tr_out1[517] 267 _CYHAL_TRIGGER_TCPWM0_TR_OUT1518 = 222, //!< tcpwm[0].tr_out1[518] 268 _CYHAL_TRIGGER_TCPWM0_TR_OUT1519 = 223, //!< tcpwm[0].tr_out1[519] 269 } _cyhal_trigger_source_psc3_t; 270 271 /** Typedef for internal device family specific trigger source to generic trigger source */ 272 typedef _cyhal_trigger_source_psc3_t cyhal_internal_source_t; 273 274 /** @brief Get a public source signal type (cyhal_trigger_source_psc3_t) given an internal source signal and signal type */ 275 #define _CYHAL_TRIGGER_CREATE_SOURCE(src, type) ((src) << 1 | (type)) 276 /** @brief Get an internal source signal (_cyhal_trigger_source_psc3_t) given a public source signal. */ 277 #define _CYHAL_TRIGGER_GET_SOURCE_SIGNAL(src) ((cyhal_internal_source_t)((src) >> 1)) 278 /** @brief Get the signal type (cyhal_signal_type_t) given a public source signal. */ 279 #define _CYHAL_TRIGGER_GET_SOURCE_TYPE(src) ((cyhal_signal_type_t)((src) & 1)) 280 /** \endcond */ 281 282 /** @brief Name of each input trigger. */ 283 typedef enum 284 { 285 CYHAL_TRIGGER_CPUSS_ZERO_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.zero 286 CYHAL_TRIGGER_CPUSS_ZERO_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_ZERO, CYHAL_SIGNAL_TYPE_LEVEL), //!< cpuss.zero 287 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[0] 288 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ1, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_dbg_dma_req[1] 289 CYHAL_TRIGGER_CANFD0_TR_FIFO00 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO00, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[0] 290 CYHAL_TRIGGER_CANFD0_TR_FIFO01 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO01, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo0[1] 291 CYHAL_TRIGGER_CANFD0_TR_FIFO10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO10, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[0] 292 CYHAL_TRIGGER_CANFD0_TR_FIFO11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_FIFO11, CYHAL_SIGNAL_TYPE_LEVEL), //!< canfd[0].tr_fifo1[1] 293 CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[0] 294 CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< canfd[0].tr_tmp_rtp_out[1] 295 CYHAL_TRIGGER_CORDIC0_TR_DONE_MXCORDIC = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CORDIC0_TR_DONE_MXCORDIC, CYHAL_SIGNAL_TYPE_LEVEL), //!< cordic[0].tr_done_mxcordic 296 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[0] 297 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[1] 298 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[2] 299 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[3] 300 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[4] 301 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[5] 302 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[6] 303 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[7] 304 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[8] 305 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[9] 306 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[10] 307 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[11] 308 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[12] 309 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[13] 310 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[14] 311 CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw0_tr_out[15] 312 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[0] 313 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[1] 314 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[2] 315 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[3] 316 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[4] 317 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[5] 318 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[6] 319 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[7] 320 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[8] 321 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[9] 322 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[10] 323 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[11] 324 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[12] 325 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[13] 326 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[14] 327 CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.dw1_tr_out[15] 328 CYHAL_TRIGGER_CPUSS_TR_FAULT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT0, CYHAL_SIGNAL_TYPE_EDGE), //!< cpuss.tr_fault[0] 329 CYHAL_TRIGGER_CPUSS_TR_FAULT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CPUSS_TR_FAULT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< cpuss.tr_fault[0] 330 CYHAL_TRIGGER_CRYPTOLITE_TR_TRNG_BITSTREAM = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_CRYPTOLITE_TR_TRNG_BITSTREAM, CYHAL_SIGNAL_TYPE_LEVEL), //!< cryptolite.tr_trng_bitstream 331 CYHAL_TRIGGER_DEBUG600_CTI_TR_OUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_DEBUG600_CTI_TR_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< debug600.cti_tr_out[0] 332 CYHAL_TRIGGER_DEBUG600_CTI_TR_OUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_DEBUG600_CTI_TR_OUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< debug600.cti_tr_out[0] 333 CYHAL_TRIGGER_DEBUG600_CTI_TR_OUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_DEBUG600_CTI_TR_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< debug600.cti_tr_out[1] 334 CYHAL_TRIGGER_DEBUG600_CTI_TR_OUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_DEBUG600_CTI_TR_OUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< debug600.cti_tr_out[1] 335 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[0] 336 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[0] 337 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[1] 338 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[1] 339 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[2] 340 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[2] 341 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[3] 342 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[3] 343 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[4] 344 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[4] 345 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[5] 346 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[5] 347 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[6] 348 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[6] 349 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[7] 350 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[7] 351 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN8_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN8, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[8] 352 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN8_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN8, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[8] 353 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN9_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN9, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[9] 354 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN9_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN9, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[9] 355 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN10, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[10] 356 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN10, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[10] 357 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN11, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[11] 358 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN11, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[11] 359 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN12, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[12] 360 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN12, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[12] 361 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN13, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[13] 362 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN13, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[13] 363 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN14_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN14, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[14] 364 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN14_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN14, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[14] 365 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN15_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN15, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[15] 366 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN15_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN15, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[15] 367 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN16_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN16, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[16] 368 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN16_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN16, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[16] 369 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN17_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN17, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[17] 370 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN17_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN17, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[17] 371 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN18_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN18, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[18] 372 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN18_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN18, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[18] 373 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN19_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN19, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[19] 374 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN19_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN19, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[19] 375 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN20_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN20, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[20] 376 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN20_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN20, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[20] 377 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN21_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN21, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[21] 378 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN21_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN21, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[21] 379 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN22_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN22, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[22] 380 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN22_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN22, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[22] 381 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN23_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN23, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[23] 382 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN23_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN23, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[23] 383 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN24_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN24, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[24] 384 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN24_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN24, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[24] 385 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN25_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN25, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[25] 386 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN25_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN25, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[25] 387 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN26_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN26, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[26] 388 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN26_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN26, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[26] 389 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN27_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN27, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[27] 390 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN27_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN27, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[27] 391 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN28_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN28, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[28] 392 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN28_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN28, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[28] 393 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN29_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN29, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[29] 394 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN29_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN29, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[29] 395 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN30_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN30, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[30] 396 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN30_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN30, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[30] 397 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN31_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN31, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[31] 398 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN31_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN31, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[31] 399 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN32_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN32, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[32] 400 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN32_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN32, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[32] 401 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN33_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN33, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[33] 402 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN33_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN33, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[33] 403 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN34_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN34, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[34] 404 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN34_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN34, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[34] 405 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN35_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN35, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[35] 406 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN35_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN35, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[35] 407 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN36_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN36, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[36] 408 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN36_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN36, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[36] 409 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN37_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN37, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[37] 410 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN37_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN37, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[37] 411 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN38_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN38, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[38] 412 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN38_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN38, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[38] 413 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN39_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN39, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[39] 414 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN39_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN39, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[39] 415 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN40_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN40, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[40] 416 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN40_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN40, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[40] 417 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN41_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN41, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[41] 418 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN41_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN41, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[41] 419 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN42_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN42, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[42] 420 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN42_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN42, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[42] 421 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN43_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN43, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[43] 422 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN43_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN43, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[43] 423 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN44_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN44, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[44] 424 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN44_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN44, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[44] 425 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN45_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN45, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[45] 426 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN45_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN45, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[45] 427 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN46_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN46, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[46] 428 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN46_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN46, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[46] 429 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN47_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN47, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[47] 430 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN47_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN47, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[47] 431 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN48_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN48, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[48] 432 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN48_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN48, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[48] 433 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN49_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN49, CYHAL_SIGNAL_TYPE_EDGE), //!< ioss.peri_tr_io_input_in[49] 434 CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN49_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN49, CYHAL_SIGNAL_TYPE_LEVEL), //!< ioss.peri_tr_io_input_in[49] 435 CYHAL_TRIGGER_LPCOMP_DSI_COMP0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_DSI_COMP0, CYHAL_SIGNAL_TYPE_LEVEL), //!< lpcomp.dsi_comp0 436 CYHAL_TRIGGER_LPCOMP_DSI_COMP1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_LPCOMP_DSI_COMP1, CYHAL_SIGNAL_TYPE_LEVEL), //!< lpcomp.dsi_comp1 437 CYHAL_TRIGGER_PASS_TR_FIFO_LEVEL_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_FIFO_LEVEL_OUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_fifo_level_out[0] 438 CYHAL_TRIGGER_PASS_TR_FIFO_LEVEL_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_FIFO_LEVEL_OUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_fifo_level_out[1] 439 CYHAL_TRIGGER_PASS_TR_FIFO_LEVEL_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_FIFO_LEVEL_OUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_fifo_level_out[2] 440 CYHAL_TRIGGER_PASS_TR_FIFO_LEVEL_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_FIFO_LEVEL_OUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_fifo_level_out[3] 441 CYHAL_TRIGGER_PASS_TR_LEVEL_OUT0 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LEVEL_OUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_level_out[0] 442 CYHAL_TRIGGER_PASS_TR_LEVEL_OUT1 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LEVEL_OUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_level_out[1] 443 CYHAL_TRIGGER_PASS_TR_LEVEL_OUT2 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LEVEL_OUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_level_out[2] 444 CYHAL_TRIGGER_PASS_TR_LEVEL_OUT3 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LEVEL_OUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_level_out[3] 445 CYHAL_TRIGGER_PASS_TR_LEVEL_OUT4 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LEVEL_OUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_level_out[4] 446 CYHAL_TRIGGER_PASS_TR_LEVEL_OUT5 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LEVEL_OUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_level_out[5] 447 CYHAL_TRIGGER_PASS_TR_LEVEL_OUT6 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LEVEL_OUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_level_out[6] 448 CYHAL_TRIGGER_PASS_TR_LEVEL_OUT7 = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_LEVEL_OUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_level_out[7] 449 CYHAL_TRIGGER_PASS_TR_PULSE_OUT0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_PULSE_OUT0, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_pulse_out[0] 450 CYHAL_TRIGGER_PASS_TR_PULSE_OUT0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_PULSE_OUT0, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_pulse_out[0] 451 CYHAL_TRIGGER_PASS_TR_PULSE_OUT1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_PULSE_OUT1, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_pulse_out[1] 452 CYHAL_TRIGGER_PASS_TR_PULSE_OUT1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_PULSE_OUT1, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_pulse_out[1] 453 CYHAL_TRIGGER_PASS_TR_PULSE_OUT2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_PULSE_OUT2, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_pulse_out[2] 454 CYHAL_TRIGGER_PASS_TR_PULSE_OUT2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_PULSE_OUT2, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_pulse_out[2] 455 CYHAL_TRIGGER_PASS_TR_PULSE_OUT3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_PULSE_OUT3, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_pulse_out[3] 456 CYHAL_TRIGGER_PASS_TR_PULSE_OUT3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_PULSE_OUT3, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_pulse_out[3] 457 CYHAL_TRIGGER_PASS_TR_PULSE_OUT4_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_PULSE_OUT4, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_pulse_out[4] 458 CYHAL_TRIGGER_PASS_TR_PULSE_OUT4_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_PULSE_OUT4, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_pulse_out[4] 459 CYHAL_TRIGGER_PASS_TR_PULSE_OUT5_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_PULSE_OUT5, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_pulse_out[5] 460 CYHAL_TRIGGER_PASS_TR_PULSE_OUT5_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_PULSE_OUT5, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_pulse_out[5] 461 CYHAL_TRIGGER_PASS_TR_PULSE_OUT6_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_PULSE_OUT6, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_pulse_out[6] 462 CYHAL_TRIGGER_PASS_TR_PULSE_OUT6_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_PULSE_OUT6, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_pulse_out[6] 463 CYHAL_TRIGGER_PASS_TR_PULSE_OUT7_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_PULSE_OUT7, CYHAL_SIGNAL_TYPE_EDGE), //!< pass.tr_pulse_out[7] 464 CYHAL_TRIGGER_PASS_TR_PULSE_OUT7_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_PASS_TR_PULSE_OUT7, CYHAL_SIGNAL_TYPE_LEVEL), //!< pass.tr_pulse_out[7] 465 CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_i2c_scl_filtered 466 CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_i2c_scl_filtered 467 CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_i2c_scl_filtered 468 CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_i2c_scl_filtered 469 CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_i2c_scl_filtered 470 CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_i2c_scl_filtered 471 CYHAL_TRIGGER_SCB0_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_rx_req 472 CYHAL_TRIGGER_SCB1_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_rx_req 473 CYHAL_TRIGGER_SCB2_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_rx_req 474 CYHAL_TRIGGER_SCB3_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_rx_req 475 CYHAL_TRIGGER_SCB4_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_rx_req 476 CYHAL_TRIGGER_SCB5_TR_RX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_RX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_rx_req 477 CYHAL_TRIGGER_SCB0_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB0_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[0].tr_tx_req 478 CYHAL_TRIGGER_SCB1_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB1_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[1].tr_tx_req 479 CYHAL_TRIGGER_SCB2_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB2_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[2].tr_tx_req 480 CYHAL_TRIGGER_SCB3_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB3_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[3].tr_tx_req 481 CYHAL_TRIGGER_SCB4_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB4_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[4].tr_tx_req 482 CYHAL_TRIGGER_SCB5_TR_TX_REQ = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_SCB5_TR_TX_REQ, CYHAL_SIGNAL_TYPE_LEVEL), //!< scb[5].tr_tx_req 483 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL0, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[0] 484 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[0] 485 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL1, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[1] 486 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[1] 487 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL2, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[2] 488 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[2] 489 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL3, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[3] 490 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[3] 491 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[256] 492 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[256] 493 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[257] 494 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[257] 495 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[258] 496 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[258] 497 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[259] 498 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[259] 499 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[260] 500 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[260] 501 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[261] 502 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[261] 503 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[262] 504 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[262] 505 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[263] 506 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[263] 507 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL512_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL512, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[512] 508 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL512_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL512, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[512] 509 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL513_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL513, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[513] 510 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL513_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL513, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[513] 511 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL514_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL514, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[514] 512 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL514_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL514, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[514] 513 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL515_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL515, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[515] 514 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL515_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL515, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[515] 515 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL516_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL516, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[516] 516 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL516_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL516, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[516] 517 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL517_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL517, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[517] 518 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL517_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL517, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[517] 519 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL518_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL518, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[518] 520 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL518_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL518, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[518] 521 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL519_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL519, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line_compl[519] 522 CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL519_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL519, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line_compl[519] 523 CYHAL_TRIGGER_TCPWM0_TR_LINE0_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE0, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[0] 524 CYHAL_TRIGGER_TCPWM0_TR_LINE0_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE0, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[0] 525 CYHAL_TRIGGER_TCPWM0_TR_LINE1_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE1, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[1] 526 CYHAL_TRIGGER_TCPWM0_TR_LINE1_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE1, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[1] 527 CYHAL_TRIGGER_TCPWM0_TR_LINE2_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE2, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[2] 528 CYHAL_TRIGGER_TCPWM0_TR_LINE2_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE2, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[2] 529 CYHAL_TRIGGER_TCPWM0_TR_LINE3_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE3, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[3] 530 CYHAL_TRIGGER_TCPWM0_TR_LINE3_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE3, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[3] 531 CYHAL_TRIGGER_TCPWM0_TR_LINE256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[256] 532 CYHAL_TRIGGER_TCPWM0_TR_LINE256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[256] 533 CYHAL_TRIGGER_TCPWM0_TR_LINE257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[257] 534 CYHAL_TRIGGER_TCPWM0_TR_LINE257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[257] 535 CYHAL_TRIGGER_TCPWM0_TR_LINE258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[258] 536 CYHAL_TRIGGER_TCPWM0_TR_LINE258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[258] 537 CYHAL_TRIGGER_TCPWM0_TR_LINE259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[259] 538 CYHAL_TRIGGER_TCPWM0_TR_LINE259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[259] 539 CYHAL_TRIGGER_TCPWM0_TR_LINE260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[260] 540 CYHAL_TRIGGER_TCPWM0_TR_LINE260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[260] 541 CYHAL_TRIGGER_TCPWM0_TR_LINE261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[261] 542 CYHAL_TRIGGER_TCPWM0_TR_LINE261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[261] 543 CYHAL_TRIGGER_TCPWM0_TR_LINE262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[262] 544 CYHAL_TRIGGER_TCPWM0_TR_LINE262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[262] 545 CYHAL_TRIGGER_TCPWM0_TR_LINE263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[263] 546 CYHAL_TRIGGER_TCPWM0_TR_LINE263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[263] 547 CYHAL_TRIGGER_TCPWM0_TR_LINE512_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE512, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[512] 548 CYHAL_TRIGGER_TCPWM0_TR_LINE512_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE512, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[512] 549 CYHAL_TRIGGER_TCPWM0_TR_LINE513_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE513, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[513] 550 CYHAL_TRIGGER_TCPWM0_TR_LINE513_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE513, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[513] 551 CYHAL_TRIGGER_TCPWM0_TR_LINE514_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE514, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[514] 552 CYHAL_TRIGGER_TCPWM0_TR_LINE514_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE514, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[514] 553 CYHAL_TRIGGER_TCPWM0_TR_LINE515_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE515, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[515] 554 CYHAL_TRIGGER_TCPWM0_TR_LINE515_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE515, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[515] 555 CYHAL_TRIGGER_TCPWM0_TR_LINE516_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE516, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[516] 556 CYHAL_TRIGGER_TCPWM0_TR_LINE516_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE516, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[516] 557 CYHAL_TRIGGER_TCPWM0_TR_LINE517_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE517, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[517] 558 CYHAL_TRIGGER_TCPWM0_TR_LINE517_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE517, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[517] 559 CYHAL_TRIGGER_TCPWM0_TR_LINE518_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE518, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[518] 560 CYHAL_TRIGGER_TCPWM0_TR_LINE518_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE518, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[518] 561 CYHAL_TRIGGER_TCPWM0_TR_LINE519_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE519, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_line[519] 562 CYHAL_TRIGGER_TCPWM0_TR_LINE519_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_LINE519, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_line[519] 563 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_motif_out[256] 564 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_motif_out[256] 565 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_motif_out[257] 566 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_motif_out[257] 567 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_motif_out[258] 568 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_motif_out[258] 569 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_motif_out[259] 570 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_motif_out[259] 571 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_motif_out[260] 572 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_motif_out[260] 573 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_motif_out[261] 574 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_motif_out[261] 575 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_motif_out[262] 576 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_motif_out[262] 577 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_motif_out[263] 578 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_motif_out[263] 579 CYHAL_TRIGGER_TCPWM0_TR_OUT00_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT00, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[0] 580 CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT00, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[0] 581 CYHAL_TRIGGER_TCPWM0_TR_OUT01_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT01, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[1] 582 CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT01, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[1] 583 CYHAL_TRIGGER_TCPWM0_TR_OUT02_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT02, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[2] 584 CYHAL_TRIGGER_TCPWM0_TR_OUT02_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT02, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[2] 585 CYHAL_TRIGGER_TCPWM0_TR_OUT03_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT03, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[3] 586 CYHAL_TRIGGER_TCPWM0_TR_OUT03_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT03, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[3] 587 CYHAL_TRIGGER_TCPWM0_TR_OUT0256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[256] 588 CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[256] 589 CYHAL_TRIGGER_TCPWM0_TR_OUT0257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[257] 590 CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[257] 591 CYHAL_TRIGGER_TCPWM0_TR_OUT0258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[258] 592 CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[258] 593 CYHAL_TRIGGER_TCPWM0_TR_OUT0259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[259] 594 CYHAL_TRIGGER_TCPWM0_TR_OUT0259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[259] 595 CYHAL_TRIGGER_TCPWM0_TR_OUT0260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[260] 596 CYHAL_TRIGGER_TCPWM0_TR_OUT0260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[260] 597 CYHAL_TRIGGER_TCPWM0_TR_OUT0261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[261] 598 CYHAL_TRIGGER_TCPWM0_TR_OUT0261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[261] 599 CYHAL_TRIGGER_TCPWM0_TR_OUT0262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[262] 600 CYHAL_TRIGGER_TCPWM0_TR_OUT0262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[262] 601 CYHAL_TRIGGER_TCPWM0_TR_OUT0263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[263] 602 CYHAL_TRIGGER_TCPWM0_TR_OUT0263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[263] 603 CYHAL_TRIGGER_TCPWM0_TR_OUT0512_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0512, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[512] 604 CYHAL_TRIGGER_TCPWM0_TR_OUT0512_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0512, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[512] 605 CYHAL_TRIGGER_TCPWM0_TR_OUT0513_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0513, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[513] 606 CYHAL_TRIGGER_TCPWM0_TR_OUT0513_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0513, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[513] 607 CYHAL_TRIGGER_TCPWM0_TR_OUT0514_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0514, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[514] 608 CYHAL_TRIGGER_TCPWM0_TR_OUT0514_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0514, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[514] 609 CYHAL_TRIGGER_TCPWM0_TR_OUT0515_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0515, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[515] 610 CYHAL_TRIGGER_TCPWM0_TR_OUT0515_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0515, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[515] 611 CYHAL_TRIGGER_TCPWM0_TR_OUT0516_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0516, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[516] 612 CYHAL_TRIGGER_TCPWM0_TR_OUT0516_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0516, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[516] 613 CYHAL_TRIGGER_TCPWM0_TR_OUT0517_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0517, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[517] 614 CYHAL_TRIGGER_TCPWM0_TR_OUT0517_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0517, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[517] 615 CYHAL_TRIGGER_TCPWM0_TR_OUT0518_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0518, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[518] 616 CYHAL_TRIGGER_TCPWM0_TR_OUT0518_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0518, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[518] 617 CYHAL_TRIGGER_TCPWM0_TR_OUT0519_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0519, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out0[519] 618 CYHAL_TRIGGER_TCPWM0_TR_OUT0519_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT0519, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out0[519] 619 CYHAL_TRIGGER_TCPWM0_TR_OUT10_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT10, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[0] 620 CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT10, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[0] 621 CYHAL_TRIGGER_TCPWM0_TR_OUT11_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT11, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[1] 622 CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT11, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[1] 623 CYHAL_TRIGGER_TCPWM0_TR_OUT12_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT12, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[2] 624 CYHAL_TRIGGER_TCPWM0_TR_OUT12_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT12, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[2] 625 CYHAL_TRIGGER_TCPWM0_TR_OUT13_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT13, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[3] 626 CYHAL_TRIGGER_TCPWM0_TR_OUT13_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT13, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[3] 627 CYHAL_TRIGGER_TCPWM0_TR_OUT1256_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1256, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[256] 628 CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1256, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[256] 629 CYHAL_TRIGGER_TCPWM0_TR_OUT1257_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1257, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[257] 630 CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1257, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[257] 631 CYHAL_TRIGGER_TCPWM0_TR_OUT1258_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1258, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[258] 632 CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1258, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[258] 633 CYHAL_TRIGGER_TCPWM0_TR_OUT1259_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1259, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[259] 634 CYHAL_TRIGGER_TCPWM0_TR_OUT1259_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1259, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[259] 635 CYHAL_TRIGGER_TCPWM0_TR_OUT1260_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1260, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[260] 636 CYHAL_TRIGGER_TCPWM0_TR_OUT1260_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1260, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[260] 637 CYHAL_TRIGGER_TCPWM0_TR_OUT1261_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1261, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[261] 638 CYHAL_TRIGGER_TCPWM0_TR_OUT1261_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1261, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[261] 639 CYHAL_TRIGGER_TCPWM0_TR_OUT1262_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1262, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[262] 640 CYHAL_TRIGGER_TCPWM0_TR_OUT1262_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1262, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[262] 641 CYHAL_TRIGGER_TCPWM0_TR_OUT1263_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1263, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[263] 642 CYHAL_TRIGGER_TCPWM0_TR_OUT1263_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1263, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[263] 643 CYHAL_TRIGGER_TCPWM0_TR_OUT1512_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1512, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[512] 644 CYHAL_TRIGGER_TCPWM0_TR_OUT1512_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1512, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[512] 645 CYHAL_TRIGGER_TCPWM0_TR_OUT1513_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1513, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[513] 646 CYHAL_TRIGGER_TCPWM0_TR_OUT1513_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1513, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[513] 647 CYHAL_TRIGGER_TCPWM0_TR_OUT1514_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1514, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[514] 648 CYHAL_TRIGGER_TCPWM0_TR_OUT1514_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1514, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[514] 649 CYHAL_TRIGGER_TCPWM0_TR_OUT1515_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1515, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[515] 650 CYHAL_TRIGGER_TCPWM0_TR_OUT1515_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1515, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[515] 651 CYHAL_TRIGGER_TCPWM0_TR_OUT1516_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1516, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[516] 652 CYHAL_TRIGGER_TCPWM0_TR_OUT1516_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1516, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[516] 653 CYHAL_TRIGGER_TCPWM0_TR_OUT1517_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1517, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[517] 654 CYHAL_TRIGGER_TCPWM0_TR_OUT1517_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1517, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[517] 655 CYHAL_TRIGGER_TCPWM0_TR_OUT1518_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1518, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[518] 656 CYHAL_TRIGGER_TCPWM0_TR_OUT1518_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1518, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[518] 657 CYHAL_TRIGGER_TCPWM0_TR_OUT1519_EDGE = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1519, CYHAL_SIGNAL_TYPE_EDGE), //!< tcpwm[0].tr_out1[519] 658 CYHAL_TRIGGER_TCPWM0_TR_OUT1519_LEVEL = _CYHAL_TRIGGER_CREATE_SOURCE(_CYHAL_TRIGGER_TCPWM0_TR_OUT1519, CYHAL_SIGNAL_TYPE_LEVEL), //!< tcpwm[0].tr_out1[519] 659 } cyhal_trigger_source_psc3_t; 660 661 /** Typedef from device family specific trigger source to generic trigger source */ 662 typedef cyhal_trigger_source_psc3_t cyhal_source_t; 663 664 /** Deprecated defines for signals that can be either level or edge. */ 665 #define CYHAL_TRIGGER_CPUSS_ZERO (CYHAL_TRIGGER_CPUSS_ZERO_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 666 #define CYHAL_TRIGGER_CPUSS_TR_FAULT0 (CYHAL_TRIGGER_CPUSS_TR_FAULT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 667 #define CYHAL_TRIGGER_DEBUG600_CTI_TR_OUT0 (CYHAL_TRIGGER_DEBUG600_CTI_TR_OUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 668 #define CYHAL_TRIGGER_DEBUG600_CTI_TR_OUT1 (CYHAL_TRIGGER_DEBUG600_CTI_TR_OUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 669 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 670 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 671 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 672 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 673 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 674 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 675 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 676 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 677 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN8 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN8_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 678 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN9 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN9_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 679 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN10 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 680 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN11 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 681 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN12 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 682 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN13 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 683 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN14 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN14_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 684 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN15 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN15_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 685 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN16 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN16_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 686 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN17 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN17_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 687 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN18 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN18_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 688 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN19 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN19_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 689 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN20 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN20_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 690 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN21 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN21_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 691 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN22 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN22_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 692 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN23 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN23_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 693 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN24 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN24_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 694 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN25 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN25_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 695 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN26 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN26_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 696 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN27 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN27_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 697 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN28 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN28_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 698 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN29 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN29_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 699 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN30 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN30_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 700 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN31 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN31_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 701 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN32 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN32_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 702 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN33 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN33_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 703 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN34 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN34_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 704 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN35 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN35_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 705 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN36 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN36_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 706 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN37 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN37_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 707 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN38 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN38_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 708 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN39 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN39_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 709 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN40 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN40_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 710 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN41 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN41_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 711 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN42 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN42_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 712 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN43 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN43_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 713 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN44 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN44_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 714 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN45 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN45_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 715 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN46 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN46_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 716 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN47 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN47_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 717 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN48 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN48_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 718 #define CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN49 (CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN49_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 719 #define CYHAL_TRIGGER_PASS_TR_PULSE_OUT0 (CYHAL_TRIGGER_PASS_TR_PULSE_OUT0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 720 #define CYHAL_TRIGGER_PASS_TR_PULSE_OUT1 (CYHAL_TRIGGER_PASS_TR_PULSE_OUT1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 721 #define CYHAL_TRIGGER_PASS_TR_PULSE_OUT2 (CYHAL_TRIGGER_PASS_TR_PULSE_OUT2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 722 #define CYHAL_TRIGGER_PASS_TR_PULSE_OUT3 (CYHAL_TRIGGER_PASS_TR_PULSE_OUT3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 723 #define CYHAL_TRIGGER_PASS_TR_PULSE_OUT4 (CYHAL_TRIGGER_PASS_TR_PULSE_OUT4_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 724 #define CYHAL_TRIGGER_PASS_TR_PULSE_OUT5 (CYHAL_TRIGGER_PASS_TR_PULSE_OUT5_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 725 #define CYHAL_TRIGGER_PASS_TR_PULSE_OUT6 (CYHAL_TRIGGER_PASS_TR_PULSE_OUT6_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 726 #define CYHAL_TRIGGER_PASS_TR_PULSE_OUT7 (CYHAL_TRIGGER_PASS_TR_PULSE_OUT7_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 727 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL0 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 728 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL1 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 729 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL2 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 730 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL3 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 731 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL256 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 732 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL257 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 733 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL258 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 734 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL259 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 735 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL260 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 736 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL261 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 737 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL262 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 738 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL263 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 739 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL512 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL512_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 740 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL513 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL513_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 741 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL514 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL514_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 742 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL515 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL515_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 743 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL516 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL516_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 744 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL517 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL517_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 745 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL518 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL518_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 746 #define CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL519 (CYHAL_TRIGGER_TCPWM0_TR_LINE_COMPL519_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 747 #define CYHAL_TRIGGER_TCPWM0_TR_LINE0 (CYHAL_TRIGGER_TCPWM0_TR_LINE0_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 748 #define CYHAL_TRIGGER_TCPWM0_TR_LINE1 (CYHAL_TRIGGER_TCPWM0_TR_LINE1_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 749 #define CYHAL_TRIGGER_TCPWM0_TR_LINE2 (CYHAL_TRIGGER_TCPWM0_TR_LINE2_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 750 #define CYHAL_TRIGGER_TCPWM0_TR_LINE3 (CYHAL_TRIGGER_TCPWM0_TR_LINE3_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 751 #define CYHAL_TRIGGER_TCPWM0_TR_LINE256 (CYHAL_TRIGGER_TCPWM0_TR_LINE256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 752 #define CYHAL_TRIGGER_TCPWM0_TR_LINE257 (CYHAL_TRIGGER_TCPWM0_TR_LINE257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 753 #define CYHAL_TRIGGER_TCPWM0_TR_LINE258 (CYHAL_TRIGGER_TCPWM0_TR_LINE258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 754 #define CYHAL_TRIGGER_TCPWM0_TR_LINE259 (CYHAL_TRIGGER_TCPWM0_TR_LINE259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 755 #define CYHAL_TRIGGER_TCPWM0_TR_LINE260 (CYHAL_TRIGGER_TCPWM0_TR_LINE260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 756 #define CYHAL_TRIGGER_TCPWM0_TR_LINE261 (CYHAL_TRIGGER_TCPWM0_TR_LINE261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 757 #define CYHAL_TRIGGER_TCPWM0_TR_LINE262 (CYHAL_TRIGGER_TCPWM0_TR_LINE262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 758 #define CYHAL_TRIGGER_TCPWM0_TR_LINE263 (CYHAL_TRIGGER_TCPWM0_TR_LINE263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 759 #define CYHAL_TRIGGER_TCPWM0_TR_LINE512 (CYHAL_TRIGGER_TCPWM0_TR_LINE512_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 760 #define CYHAL_TRIGGER_TCPWM0_TR_LINE513 (CYHAL_TRIGGER_TCPWM0_TR_LINE513_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 761 #define CYHAL_TRIGGER_TCPWM0_TR_LINE514 (CYHAL_TRIGGER_TCPWM0_TR_LINE514_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 762 #define CYHAL_TRIGGER_TCPWM0_TR_LINE515 (CYHAL_TRIGGER_TCPWM0_TR_LINE515_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 763 #define CYHAL_TRIGGER_TCPWM0_TR_LINE516 (CYHAL_TRIGGER_TCPWM0_TR_LINE516_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 764 #define CYHAL_TRIGGER_TCPWM0_TR_LINE517 (CYHAL_TRIGGER_TCPWM0_TR_LINE517_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 765 #define CYHAL_TRIGGER_TCPWM0_TR_LINE518 (CYHAL_TRIGGER_TCPWM0_TR_LINE518_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 766 #define CYHAL_TRIGGER_TCPWM0_TR_LINE519 (CYHAL_TRIGGER_TCPWM0_TR_LINE519_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 767 #define CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT256 (CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 768 #define CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT257 (CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 769 #define CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT258 (CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 770 #define CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT259 (CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 771 #define CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT260 (CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 772 #define CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT261 (CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 773 #define CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT262 (CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 774 #define CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT263 (CYHAL_TRIGGER_TCPWM0_TR_MOTIF_OUT263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 775 #define CYHAL_TRIGGER_TCPWM0_TR_OUT00 (CYHAL_TRIGGER_TCPWM0_TR_OUT00_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 776 #define CYHAL_TRIGGER_TCPWM0_TR_OUT01 (CYHAL_TRIGGER_TCPWM0_TR_OUT01_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 777 #define CYHAL_TRIGGER_TCPWM0_TR_OUT02 (CYHAL_TRIGGER_TCPWM0_TR_OUT02_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 778 #define CYHAL_TRIGGER_TCPWM0_TR_OUT03 (CYHAL_TRIGGER_TCPWM0_TR_OUT03_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 779 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0256 (CYHAL_TRIGGER_TCPWM0_TR_OUT0256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 780 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0257 (CYHAL_TRIGGER_TCPWM0_TR_OUT0257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 781 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0258 (CYHAL_TRIGGER_TCPWM0_TR_OUT0258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 782 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0259 (CYHAL_TRIGGER_TCPWM0_TR_OUT0259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 783 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0260 (CYHAL_TRIGGER_TCPWM0_TR_OUT0260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 784 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0261 (CYHAL_TRIGGER_TCPWM0_TR_OUT0261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 785 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0262 (CYHAL_TRIGGER_TCPWM0_TR_OUT0262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 786 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0263 (CYHAL_TRIGGER_TCPWM0_TR_OUT0263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 787 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0512 (CYHAL_TRIGGER_TCPWM0_TR_OUT0512_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 788 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0513 (CYHAL_TRIGGER_TCPWM0_TR_OUT0513_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 789 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0514 (CYHAL_TRIGGER_TCPWM0_TR_OUT0514_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 790 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0515 (CYHAL_TRIGGER_TCPWM0_TR_OUT0515_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 791 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0516 (CYHAL_TRIGGER_TCPWM0_TR_OUT0516_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 792 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0517 (CYHAL_TRIGGER_TCPWM0_TR_OUT0517_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 793 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0518 (CYHAL_TRIGGER_TCPWM0_TR_OUT0518_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 794 #define CYHAL_TRIGGER_TCPWM0_TR_OUT0519 (CYHAL_TRIGGER_TCPWM0_TR_OUT0519_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 795 #define CYHAL_TRIGGER_TCPWM0_TR_OUT10 (CYHAL_TRIGGER_TCPWM0_TR_OUT10_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 796 #define CYHAL_TRIGGER_TCPWM0_TR_OUT11 (CYHAL_TRIGGER_TCPWM0_TR_OUT11_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 797 #define CYHAL_TRIGGER_TCPWM0_TR_OUT12 (CYHAL_TRIGGER_TCPWM0_TR_OUT12_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 798 #define CYHAL_TRIGGER_TCPWM0_TR_OUT13 (CYHAL_TRIGGER_TCPWM0_TR_OUT13_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 799 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1256 (CYHAL_TRIGGER_TCPWM0_TR_OUT1256_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 800 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1257 (CYHAL_TRIGGER_TCPWM0_TR_OUT1257_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 801 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1258 (CYHAL_TRIGGER_TCPWM0_TR_OUT1258_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 802 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1259 (CYHAL_TRIGGER_TCPWM0_TR_OUT1259_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 803 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1260 (CYHAL_TRIGGER_TCPWM0_TR_OUT1260_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 804 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1261 (CYHAL_TRIGGER_TCPWM0_TR_OUT1261_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 805 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1262 (CYHAL_TRIGGER_TCPWM0_TR_OUT1262_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 806 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1263 (CYHAL_TRIGGER_TCPWM0_TR_OUT1263_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 807 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1512 (CYHAL_TRIGGER_TCPWM0_TR_OUT1512_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 808 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1513 (CYHAL_TRIGGER_TCPWM0_TR_OUT1513_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 809 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1514 (CYHAL_TRIGGER_TCPWM0_TR_OUT1514_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 810 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1515 (CYHAL_TRIGGER_TCPWM0_TR_OUT1515_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 811 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1516 (CYHAL_TRIGGER_TCPWM0_TR_OUT1516_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 812 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1517 (CYHAL_TRIGGER_TCPWM0_TR_OUT1517_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 813 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1518 (CYHAL_TRIGGER_TCPWM0_TR_OUT1518_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 814 #define CYHAL_TRIGGER_TCPWM0_TR_OUT1519 (CYHAL_TRIGGER_TCPWM0_TR_OUT1519_LEVEL) //!< Legacy define. Instead, use the explicit _LEVEL or _EDGE version. 815 816 /** @brief Name of each output trigger. */ 817 typedef enum 818 { 819 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0 = 0, //!< CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[0] 820 CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK1 = 1, //!< CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[1] 821 CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0 = 2, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[0] 822 CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN1 = 3, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[1] 823 CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 = 4, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[0] 824 CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 = 5, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[1] 825 CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 = 6, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[2] 826 CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 = 7, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[3] 827 CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 = 8, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[4] 828 CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 = 9, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[5] 829 CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 = 10, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[6] 830 CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 = 11, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[7] 831 CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 = 12, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[8] 832 CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 = 13, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[9] 833 CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 = 14, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[10] 834 CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 = 15, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[11] 835 CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 = 16, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[12] 836 CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 = 17, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[13] 837 CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 = 18, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[14] 838 CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 = 19, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[15] 839 CYHAL_TRIGGER_CPUSS_DW1_TR_IN0 = 20, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[0] 840 CYHAL_TRIGGER_CPUSS_DW1_TR_IN1 = 21, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[1] 841 CYHAL_TRIGGER_CPUSS_DW1_TR_IN2 = 22, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[2] 842 CYHAL_TRIGGER_CPUSS_DW1_TR_IN3 = 23, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[3] 843 CYHAL_TRIGGER_CPUSS_DW1_TR_IN4 = 24, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[4] 844 CYHAL_TRIGGER_CPUSS_DW1_TR_IN5 = 25, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[5] 845 CYHAL_TRIGGER_CPUSS_DW1_TR_IN6 = 26, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[6] 846 CYHAL_TRIGGER_CPUSS_DW1_TR_IN7 = 27, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[7] 847 CYHAL_TRIGGER_CPUSS_DW1_TR_IN8 = 28, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[8] 848 CYHAL_TRIGGER_CPUSS_DW1_TR_IN9 = 29, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[9] 849 CYHAL_TRIGGER_CPUSS_DW1_TR_IN10 = 30, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[10] 850 CYHAL_TRIGGER_CPUSS_DW1_TR_IN11 = 31, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[11] 851 CYHAL_TRIGGER_CPUSS_DW1_TR_IN12 = 32, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[12] 852 CYHAL_TRIGGER_CPUSS_DW1_TR_IN13 = 33, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[13] 853 CYHAL_TRIGGER_CPUSS_DW1_TR_IN14 = 34, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[14] 854 CYHAL_TRIGGER_CPUSS_DW1_TR_IN15 = 35, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[15] 855 CYHAL_TRIGGER_DEBUG600_CTI_TR_IN0 = 36, //!< CPUSS Debug multiplexer - debug600.cti_tr_in[0] 856 CYHAL_TRIGGER_DEBUG600_CTI_TR_IN1 = 37, //!< CPUSS Debug multiplexer - debug600.cti_tr_in[1] 857 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT0 = 38, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[0] 858 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT1 = 39, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[1] 859 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT2 = 40, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[2] 860 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT3 = 41, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[3] 861 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT4 = 42, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[4] 862 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT5 = 43, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[5] 863 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT6 = 44, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[6] 864 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT7 = 45, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[7] 865 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT8 = 46, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[8] 866 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT9 = 47, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[9] 867 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT10 = 48, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[10] 868 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT11 = 49, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[11] 869 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT12 = 50, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[12] 870 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT13 = 51, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[13] 871 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT14 = 52, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[14] 872 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT15 = 53, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[15] 873 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT16 = 54, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[16] 874 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT17 = 55, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[17] 875 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT18 = 56, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[18] 876 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT19 = 57, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[19] 877 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT20 = 58, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[20] 878 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT21 = 59, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[21] 879 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT22 = 60, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[22] 880 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT23 = 61, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[23] 881 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT24 = 62, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[24] 882 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT25 = 63, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[25] 883 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT26 = 64, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[26] 884 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT27 = 65, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[27] 885 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT28 = 66, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[28] 886 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT29 = 67, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[29] 887 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT30 = 68, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[30] 888 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT31 = 69, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[31] 889 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT32 = 70, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[32] 890 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT33 = 71, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[33] 891 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT34 = 72, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[34] 892 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT35 = 73, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[35] 893 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT36 = 74, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[36] 894 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT37 = 75, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[37] 895 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT38 = 76, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[38] 896 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT39 = 77, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[39] 897 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT40 = 78, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[40] 898 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT41 = 79, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[41] 899 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT42 = 80, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[42] 900 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT43 = 81, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[43] 901 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT44 = 82, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[44] 902 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT45 = 83, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[45] 903 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT46 = 84, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[46] 904 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT47 = 85, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[47] 905 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT48 = 86, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[48] 906 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT49 = 87, //!< HSIOM0 trigger multiplexer - ioss.peri_tr_io_output_out[49] 907 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT50 = 88, //!< HSIOM1 trigger multiplexer - ioss.peri_tr_io_output_out[50] 908 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT51 = 89, //!< HSIOM1 trigger multiplexer - ioss.peri_tr_io_output_out[51] 909 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT52 = 90, //!< HSIOM1 trigger multiplexer - ioss.peri_tr_io_output_out[52] 910 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT53 = 91, //!< HSIOM1 trigger multiplexer - ioss.peri_tr_io_output_out[53] 911 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT54 = 92, //!< HSIOM1 trigger multiplexer - ioss.peri_tr_io_output_out[54] 912 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT55 = 93, //!< HSIOM1 trigger multiplexer - ioss.peri_tr_io_output_out[55] 913 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT56 = 94, //!< HSIOM1 trigger multiplexer - ioss.peri_tr_io_output_out[56] 914 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT57 = 95, //!< HSIOM1 trigger multiplexer - ioss.peri_tr_io_output_out[57] 915 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT58 = 96, //!< HSIOM2 trigger multiplexer - ioss.peri_tr_io_output_out[58] 916 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT59 = 97, //!< HSIOM2 trigger multiplexer - ioss.peri_tr_io_output_out[59] 917 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT60 = 98, //!< HSIOM2 trigger multiplexer - ioss.peri_tr_io_output_out[60] 918 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT61 = 99, //!< HSIOM2 trigger multiplexer - ioss.peri_tr_io_output_out[61] 919 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT62 = 100, //!< HSIOM2 trigger multiplexer - ioss.peri_tr_io_output_out[62] 920 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT63 = 101, //!< HSIOM2 trigger multiplexer - ioss.peri_tr_io_output_out[63] 921 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT64 = 102, //!< HSIOM2 trigger multiplexer - ioss.peri_tr_io_output_out[64] 922 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT65 = 103, //!< HSIOM2 trigger multiplexer - ioss.peri_tr_io_output_out[65] 923 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT66 = 104, //!< HSIOM3 trigger multiplexer - ioss.peri_tr_io_output_out[66] 924 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT67 = 105, //!< HSIOM3 trigger multiplexer - ioss.peri_tr_io_output_out[67] 925 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT68 = 106, //!< HSIOM3 trigger multiplexer - ioss.peri_tr_io_output_out[68] 926 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT69 = 107, //!< HSIOM3 trigger multiplexer - ioss.peri_tr_io_output_out[69] 927 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT70 = 108, //!< HSIOM3 trigger multiplexer - ioss.peri_tr_io_output_out[70] 928 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT71 = 109, //!< HSIOM3 trigger multiplexer - ioss.peri_tr_io_output_out[71] 929 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT72 = 110, //!< HSIOM3 trigger multiplexer - ioss.peri_tr_io_output_out[72] 930 CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT73 = 111, //!< HSIOM3 trigger multiplexer - ioss.peri_tr_io_output_out[73] 931 CYHAL_TRIGGER_PASS_TR_A_IN0 = 112, //!< MCPASS trigger multiplexer - pass.tr_a_in[0] 932 CYHAL_TRIGGER_PASS_TR_A_IN1 = 113, //!< MCPASS trigger multiplexer - pass.tr_a_in[1] 933 CYHAL_TRIGGER_PASS_TR_A_IN2 = 114, //!< MCPASS trigger multiplexer - pass.tr_a_in[2] 934 CYHAL_TRIGGER_PASS_TR_A_IN3 = 115, //!< MCPASS trigger multiplexer - pass.tr_a_in[3] 935 CYHAL_TRIGGER_PASS_TR_A_IN4 = 116, //!< MCPASS trigger multiplexer - pass.tr_a_in[4] 936 CYHAL_TRIGGER_PASS_TR_A_IN5 = 117, //!< MCPASS trigger multiplexer - pass.tr_a_in[5] 937 CYHAL_TRIGGER_PASS_TR_A_IN6 = 118, //!< MCPASS trigger multiplexer - pass.tr_a_in[6] 938 CYHAL_TRIGGER_PASS_TR_A_IN7 = 119, //!< MCPASS trigger multiplexer - pass.tr_a_in[7] 939 CYHAL_TRIGGER_PASS_TR_B_IN0 = 120, //!< MCPASS triggers - pass.tr_b_in[0] 940 CYHAL_TRIGGER_PASS_TR_B_IN1 = 121, //!< MCPASS triggers - pass.tr_b_in[1] 941 CYHAL_TRIGGER_PASS_TR_B_IN2 = 122, //!< MCPASS triggers - pass.tr_b_in[2] 942 CYHAL_TRIGGER_PASS_TR_B_IN3 = 123, //!< MCPASS triggers - pass.tr_b_in[3] 943 CYHAL_TRIGGER_PASS_TR_B_IN4 = 124, //!< MCPASS triggers - pass.tr_b_in[4] 944 CYHAL_TRIGGER_PASS_TR_B_IN5 = 125, //!< MCPASS triggers - pass.tr_b_in[5] 945 CYHAL_TRIGGER_PASS_TR_B_IN6 = 126, //!< MCPASS triggers - pass.tr_b_in[6] 946 CYHAL_TRIGGER_PASS_TR_B_IN7 = 127, //!< MCPASS triggers - pass.tr_b_in[7] 947 CYHAL_TRIGGER_PERI_TR_DBG_FREEZE = 128, //!< PERI Freeze trigger multiplexer - peri.tr_dbg_freeze 948 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 = 129, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[0] 949 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 = 130, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[1] 950 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 = 131, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[2] 951 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 = 132, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[3] 952 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 = 133, //!< TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[4] 953 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 = 134, //!< TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[5] 954 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 = 135, //!< TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[6] 955 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 = 136, //!< TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[7] 956 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 = 137, //!< TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[8] 957 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 = 138, //!< TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[9] 958 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 = 139, //!< TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[10] 959 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 = 140, //!< TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[11] 960 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 = 141, //!< TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[12] 961 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 = 142, //!< TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[13] 962 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 = 143, //!< TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[14] 963 CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 = 144, //!< TCPWM1 trigger multiplexer - tcpwm[0].tr_all_cnt_in[15] 964 CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE = 145, //!< PERI Freeze trigger multiplexer - tcpwm[0].tr_debug_freeze 965 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_IN256 = 146, //!< TCPWM MOTIF trigger multiplexer - tcpwm[0].tr_motif_in[256] 966 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_IN257 = 147, //!< TCPWM MOTIF trigger multiplexer - tcpwm[0].tr_motif_in[257] 967 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_IN258 = 148, //!< TCPWM MOTIF trigger multiplexer - tcpwm[0].tr_motif_in[258] 968 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_IN259 = 149, //!< TCPWM MOTIF trigger multiplexer - tcpwm[0].tr_motif_in[259] 969 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_IN260 = 150, //!< TCPWM MOTIF trigger multiplexer - tcpwm[0].tr_motif_in[260] 970 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_IN261 = 151, //!< TCPWM MOTIF trigger multiplexer - tcpwm[0].tr_motif_in[261] 971 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_IN262 = 152, //!< TCPWM MOTIF trigger multiplexer - tcpwm[0].tr_motif_in[262] 972 CYHAL_TRIGGER_TCPWM0_TR_MOTIF_IN263 = 153, //!< TCPWM MOTIF trigger multiplexer - tcpwm[0].tr_motif_in[263] 973 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN0 = 154, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[0] 974 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1 = 155, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1] 975 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN2 = 156, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[2] 976 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN3 = 157, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[3] 977 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN4 = 158, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[4] 978 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN5 = 159, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[5] 979 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN6 = 160, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[6] 980 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN7 = 161, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[7] 981 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN8 = 162, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[8] 982 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN9 = 163, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[9] 983 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN10 = 164, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[10] 984 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN11 = 165, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[11] 985 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1536 = 166, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[1536] 986 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1537 = 167, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1537] 987 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1538 = 168, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1538] 988 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1539 = 169, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[1539] 989 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1540 = 170, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1540] 990 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1541 = 171, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1541] 991 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1542 = 172, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[1542] 992 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1543 = 173, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1543] 993 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1544 = 174, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1544] 994 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1545 = 175, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[1545] 995 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1546 = 176, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1546] 996 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1547 = 177, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1547] 997 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1548 = 178, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[1548] 998 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1549 = 179, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1549] 999 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1550 = 180, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1550] 1000 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1551 = 181, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[1551] 1001 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1552 = 182, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1552] 1002 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1553 = 183, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1553] 1003 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1554 = 184, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[1554] 1004 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1555 = 185, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1555] 1005 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1556 = 186, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1556] 1006 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1557 = 187, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[1557] 1007 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1558 = 188, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1558] 1008 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN1559 = 189, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[1559] 1009 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN768 = 190, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[768] 1010 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN769 = 191, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[769] 1011 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN770 = 192, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[770] 1012 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN771 = 193, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[771] 1013 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN772 = 194, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[772] 1014 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN773 = 195, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[773] 1015 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN774 = 196, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[774] 1016 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN775 = 197, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[775] 1017 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN776 = 198, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[776] 1018 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN777 = 199, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[777] 1019 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN778 = 200, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[778] 1020 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN779 = 201, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[779] 1021 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN780 = 202, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[780] 1022 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN781 = 203, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[781] 1023 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN782 = 204, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[782] 1024 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN783 = 205, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[783] 1025 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN784 = 206, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[784] 1026 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN785 = 207, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[785] 1027 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN786 = 208, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[786] 1028 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN787 = 209, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[787] 1029 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN788 = 210, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[788] 1030 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN789 = 211, //!< MCPASS CSG triggers - tcpwm[0].tr_one_cnt_in[789] 1031 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN790 = 212, //!< TCPWM2 trigger multiplexer - tcpwm[0].tr_one_cnt_in[790] 1032 CYHAL_TRIGGER_TCPWM0_TR_ONE_CNT_IN791 = 213, //!< TCPWM3 trigger multiplexer - tcpwm[0].tr_one_cnt_in[791] 1033 } cyhal_trigger_dest_psc3_t; 1034 1035 /** Typedef from device family specific trigger dest to generic trigger dest */ 1036 typedef cyhal_trigger_dest_psc3_t cyhal_dest_t; 1037 1038 /** \cond INTERNAL */ 1039 /** Table of number of inputs to each mux. */ 1040 extern const uint16_t cyhal_sources_per_mux[18]; 1041 1042 /** Table indicating whether mux is 1to1. */ 1043 extern const bool cyhal_is_mux_1to1[18]; 1044 1045 /** Table pointing to each mux source table. The index of each source in the table is its mux input index. */ 1046 extern const _cyhal_trigger_source_psc3_t* cyhal_mux_to_sources [18]; 1047 1048 /** Maps each cyhal_destination_t to a mux index. 1049 * If bit 8 of the mux index is set, this denotes that the trigger is a 1050 * one to one trigger. 1051 */ 1052 extern const uint8_t cyhal_dest_to_mux[214]; 1053 1054 /* Maps each cyhal_destination_t to a specific output in its mux */ 1055 extern const uint8_t cyhal_mux_dest_index[214]; 1056 /** \endcond */ 1057 1058 #if defined(__cplusplus) 1059 } 1060 #endif /* __cplusplus */ 1061 /** \} group_hal_impl_triggers_psc3 */ 1062 #endif /* _CYHAL_TRIGGERS_PSC3_H_ */ 1063 1064 1065 /* [] END OF FILE */ 1066
