1 2 /** 3 * @file xmc_dma_map.h 4 * @date 2015-05-07 5 * 6 * @cond 7 ********************************************************************************************************************* 8 * XMClib v2.1.24 - XMC Peripheral Driver Library 9 * 10 * Copyright (c) 2015-2019, Infineon Technologies AG 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the 14 * following conditions are met: 15 * 16 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials provided with the distribution. 21 * 22 * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote 23 * products derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 26 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with 34 * Infineon Technologies AG dave@infineon.com). 35 ********************************************************************************************************************* 36 * 37 * Change History 38 * -------------- 39 * 40 * 2015-02-20: 41 * - Initial version 42 * 43 * 2015-05-07: 44 * - Change line numbering for DMA1 <br> 45 * 46 * @endcond 47 */ 48 49 #ifndef XMC_DMA_MAP_H 50 #define XMC_DMA_MAP_H 51 52 #define DMA_PERIPHERAL_REQUEST(line, sel) (uint8_t)(line | (sel << 4U)) 53 54 /* 55 * DMA LINE 0 of DMA0 56 */ 57 58 #define DMA0_PERIPHERAL_REQUEST_ERU0_SR0_0 DMA_PERIPHERAL_REQUEST(0, 0) 59 #define DMA0_PERIPHERAL_REQUEST_VADC_C0SR0_0 DMA_PERIPHERAL_REQUEST(0, 1) 60 #define DMA0_PERIPHERAL_REQUEST_VADC_G0SR3_0 DMA_PERIPHERAL_REQUEST(0, 2) 61 62 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 63 #define DMA0_PERIPHERAL_REQUEST_VADC_G2SR0_0 DMA_PERIPHERAL_REQUEST(0, 3) 64 #define DMA0_PERIPHERAL_REQUEST_VADC_G2SR3_0 DMA_PERIPHERAL_REQUEST(0, 4) 65 #define DMA0_PERIPHERAL_REQUEST_DSD_SRM0_0 DMA_PERIPHERAL_REQUEST(0, 5) 66 #endif 67 68 #define DMA0_PERIPHERAL_REQUEST_CCU40_SR0_0 DMA_PERIPHERAL_REQUEST(0, 6) 69 #define DMA0_PERIPHERAL_REQUEST_CCU80_SR0_0 DMA_PERIPHERAL_REQUEST(0, 7) 70 #define DMA0_PERIPHERAL_REQUEST_CAN_SR0_0 DMA_PERIPHERAL_REQUEST(0, 9) 71 #define DMA0_PERIPHERAL_REQUEST_USIC0_SR0_0 DMA_PERIPHERAL_REQUEST(0, 10) 72 #define DMA0_PERIPHERAL_REQUEST_USIC1_SR0_0 DMA_PERIPHERAL_REQUEST(0, 11) 73 74 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 75 #define DMA0_PERIPHERAL_REQUEST_VADC_G3SR3_0 DMA_PERIPHERAL_REQUEST(0, 13) 76 #define DMA0_PERIPHERAL_REQUEST_CCU42_SR0_0 DMA_PERIPHERAL_REQUEST(0, 14) 77 #endif 78 79 #if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) 80 #define DMA0_PERIPHERAL_REQUEST_HRPWM0_SR0_0 DMA_PERIPHERAL_REQUEST(0, 15) 81 #endif 82 83 /* 84 * DMA LINE 1 of DMA0 85 */ 86 87 #define DMA0_PERIPHERAL_REQUEST_ERU0_SR3_1 DMA_PERIPHERAL_REQUEST(1, 0) 88 #define DMA0_PERIPHERAL_REQUEST_VADC_C0SR1_1 DMA_PERIPHERAL_REQUEST(1, 1) 89 #define DMA0_PERIPHERAL_REQUEST_VADC_G0SR2_1 DMA_PERIPHERAL_REQUEST(1, 2) 90 #define DMA0_PERIPHERAL_REQUEST_VADC_G1SR0_1 DMA_PERIPHERAL_REQUEST(1, 3) 91 92 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 93 #define DMA0_PERIPHERAL_REQUEST_VADC_G2SR2_1 DMA_PERIPHERAL_REQUEST(1, 4) 94 #endif 95 96 #define DMA0_PERIPHERAL_REQUEST_DAC_SR0_1 DMA_PERIPHERAL_REQUEST(1, 5) 97 #define DMA0_PERIPHERAL_REQUEST_CCU40_SR0_1 DMA_PERIPHERAL_REQUEST(1, 6) 98 #define DMA0_PERIPHERAL_REQUEST_CCU80_SR0_1 DMA_PERIPHERAL_REQUEST(1, 7) 99 #define DMA0_PERIPHERAL_REQUEST_CAN_SR0_1 DMA_PERIPHERAL_REQUEST(1, 9) 100 #define DMA0_PERIPHERAL_REQUEST_USIC0_SR0_1 DMA_PERIPHERAL_REQUEST(1, 10) 101 #define DMA0_PERIPHERAL_REQUEST_USIC1_SR0_1 DMA_PERIPHERAL_REQUEST(1, 11) 102 103 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 104 #define DMA0_PERIPHERAL_REQUEST_VADC_G3SR0_1 DMA_PERIPHERAL_REQUEST(1, 13) 105 #define DMA0_PERIPHERAL_REQUEST_CCU42_SR0_1 DMA_PERIPHERAL_REQUEST(1, 14) 106 #endif 107 108 #if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) 109 #define DMA0_PERIPHERAL_REQUEST_HRPWM0_SR1_1 DMA_PERIPHERAL_REQUEST(1, 15) 110 #endif 111 112 /* 113 * DMA LINE 2 of DMA0 114 */ 115 116 #define DMA0_PERIPHERAL_REQUEST_ERU0_SR1_2 DMA_PERIPHERAL_REQUEST(2, 0) 117 #define DMA0_PERIPHERAL_REQUEST_VADC_C0SR2_2 DMA_PERIPHERAL_REQUEST(2, 1) 118 #define DMA0_PERIPHERAL_REQUEST_VADC_C0SR3_2 DMA_PERIPHERAL_REQUEST(2, 2) 119 #define DMA0_PERIPHERAL_REQUEST_VADC_G1SR3_2 DMA_PERIPHERAL_REQUEST(2, 3) 120 121 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 122 #define DMA0_PERIPHERAL_REQUEST_VADC_G2SR1_2 DMA_PERIPHERAL_REQUEST(2, 4) 123 #define DMA0_PERIPHERAL_REQUEST_DSD_SRM1_2 DMA_PERIPHERAL_REQUEST(2, 5) 124 #define DMA0_PERIPHERAL_REQUEST_DSD_SRM3_2 DMA_PERIPHERAL_REQUEST(2, 6) 125 #endif 126 127 #define DMA0_PERIPHERAL_REQUEST_CCU40_SR1_2 DMA_PERIPHERAL_REQUEST(2, 7) 128 #define DMA0_PERIPHERAL_REQUEST_CCU80_SR1_2 DMA_PERIPHERAL_REQUEST(2, 8) 129 #define DMA0_PERIPHERAL_REQUEST_CAN_SR1_2 DMA_PERIPHERAL_REQUEST(2, 10) 130 #define DMA0_PERIPHERAL_REQUEST_USIC0_SR1_2 DMA_PERIPHERAL_REQUEST(2, 11) 131 #define DMA0_PERIPHERAL_REQUEST_USIC1_SR1_2 DMA_PERIPHERAL_REQUEST(2, 12) 132 133 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 134 #define DMA0_PERIPHERAL_REQUEST_VADC_G3SR2_2 DMA_PERIPHERAL_REQUEST(2, 13) 135 #define DMA0_PERIPHERAL_REQUEST_CCU42_SR1_2 DMA_PERIPHERAL_REQUEST(2, 14) 136 #endif 137 138 /* 139 * DMA LINE 3 of DMA0 140 */ 141 142 #define DMA0_PERIPHERAL_REQUEST_ERU0_SR2_3 DMA_PERIPHERAL_REQUEST(3, 0) 143 #define DMA0_PERIPHERAL_REQUEST_VADC_C0SR2_3 DMA_PERIPHERAL_REQUEST(3, 1) 144 #define DMA0_PERIPHERAL_REQUEST_VADC_C0SR3_3 DMA_PERIPHERAL_REQUEST(3, 2) 145 #define DMA0_PERIPHERAL_REQUEST_VADC_G1SR1_3 DMA_PERIPHERAL_REQUEST(3, 3) 146 #define DMA0_PERIPHERAL_REQUEST_VADC_G1SR2_3 DMA_PERIPHERAL_REQUEST(3, 4) 147 148 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 149 #define DMA0_PERIPHERAL_REQUEST_DSD_SRM2_3 DMA_PERIPHERAL_REQUEST(3, 5) 150 #endif 151 152 #define DMA0_PERIPHERAL_REQUEST_DAC_SR1_3 DMA_PERIPHERAL_REQUEST(3, 6) 153 #define DMA0_PERIPHERAL_REQUEST_CCU40_SR1_3 DMA_PERIPHERAL_REQUEST(3, 7) 154 #define DMA0_PERIPHERAL_REQUEST_CCU80_SR1_3 DMA_PERIPHERAL_REQUEST(3, 8) 155 #define DMA0_PERIPHERAL_REQUEST_CAN_SR1_3 DMA_PERIPHERAL_REQUEST(3, 10) 156 #define DMA0_PERIPHERAL_REQUEST_USIC0_SR1_3 DMA_PERIPHERAL_REQUEST(3, 11) 157 #define DMA0_PERIPHERAL_REQUEST_USIC1_SR1_3 DMA_PERIPHERAL_REQUEST(3, 12) 158 159 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 160 #define DMA0_PERIPHERAL_REQUEST_VADC_G3SR1_3 DMA_PERIPHERAL_REQUEST(3, 13) 161 #define DMA0_PERIPHERAL_REQUEST_CCU42_SR1_3 DMA_PERIPHERAL_REQUEST(3, 14) 162 #endif 163 164 /* 165 * DMA LINE 4 of DMA0 166 */ 167 168 #define DMA0_PERIPHERAL_REQUEST_ERU0_SR2_4 DMA_PERIPHERAL_REQUEST(4, 0) 169 #define DMA0_PERIPHERAL_REQUEST_VADC_G0SR0_4 DMA_PERIPHERAL_REQUEST(4, 1) 170 #define DMA0_PERIPHERAL_REQUEST_VADC_G0SR1_4 DMA_PERIPHERAL_REQUEST(4, 2) 171 172 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 173 #define DMA0_PERIPHERAL_REQUEST_VADC_G2SR1_4 DMA_PERIPHERAL_REQUEST(4, 3) 174 #define DMA0_PERIPHERAL_REQUEST_VADC_G2SR2_4 DMA_PERIPHERAL_REQUEST(4, 4) 175 #define DMA0_PERIPHERAL_REQUEST_DSD_SRM2_4 DMA_PERIPHERAL_REQUEST(4, 5) 176 #endif 177 178 #define DMA0_PERIPHERAL_REQUEST_DAC_SR1_4 DMA_PERIPHERAL_REQUEST(4, 6) 179 #define DMA0_PERIPHERAL_REQUEST_CCU41_SR0_4 DMA_PERIPHERAL_REQUEST(4, 7) 180 181 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 182 #define DMA0_PERIPHERAL_REQUEST_CCU81_SR0_4 DMA_PERIPHERAL_REQUEST(4, 8) 183 #endif 184 185 #define DMA0_PERIPHERAL_REQUEST_CAN_SR2_4 DMA_PERIPHERAL_REQUEST(4, 10) 186 #define DMA0_PERIPHERAL_REQUEST_USIC0_SR0_4 DMA_PERIPHERAL_REQUEST(4, 11) 187 #define DMA0_PERIPHERAL_REQUEST_USIC1_SR0_4 DMA_PERIPHERAL_REQUEST(4, 12) 188 189 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 190 #define DMA0_PERIPHERAL_REQUEST_VADC_G3SR1_4 DMA_PERIPHERAL_REQUEST(4, 13) 191 #define DMA0_PERIPHERAL_REQUEST_CCU43_SR0_4 DMA_PERIPHERAL_REQUEST(4, 14) 192 #endif 193 194 /* 195 * DMA LINE 5 of DMA0 196 */ 197 198 #define DMA0_PERIPHERAL_REQUEST_ERU0_SR1_5 DMA_PERIPHERAL_REQUEST(5, 0) 199 #define DMA0_PERIPHERAL_REQUEST_VADC_G0SR0_5 DMA_PERIPHERAL_REQUEST(5, 1) 200 #define DMA0_PERIPHERAL_REQUEST_VADC_G0SR1_5 DMA_PERIPHERAL_REQUEST(5, 2) 201 #define DMA0_PERIPHERAL_REQUEST_VADC_G1SR2_5 DMA_PERIPHERAL_REQUEST(5, 3) 202 203 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 204 #define DMA0_PERIPHERAL_REQUEST_VADC_G2SR0_5 DMA_PERIPHERAL_REQUEST(5, 4) 205 #endif 206 207 #define DMA0_PERIPHERAL_REQUEST_DAC_SR0_5 DMA_PERIPHERAL_REQUEST(5, 5) 208 #define DMA0_PERIPHERAL_REQUEST_CCU41_SR0_5 DMA_PERIPHERAL_REQUEST(5, 6) 209 210 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 211 #define DMA0_PERIPHERAL_REQUEST_CCU81_SR0_5 DMA_PERIPHERAL_REQUEST(5, 7) 212 #endif 213 214 #define DMA0_PERIPHERAL_REQUEST_CAN_SR2_5 DMA_PERIPHERAL_REQUEST(5, 9) 215 #define DMA0_PERIPHERAL_REQUEST_USIC0_SR0_5 DMA_PERIPHERAL_REQUEST(5, 10) 216 #define DMA0_PERIPHERAL_REQUEST_USIC1_SR0_5 DMA_PERIPHERAL_REQUEST(5, 11) 217 218 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 219 #define DMA0_PERIPHERAL_REQUEST_VADC_G3SR2_5 DMA_PERIPHERAL_REQUEST(5, 13) 220 #define DMA0_PERIPHERAL_REQUEST_CCU43_SR0_5 DMA_PERIPHERAL_REQUEST(5, 14) 221 #endif 222 223 #if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) 224 #define DMA0_PERIPHERAL_REQUEST_HRPWM0_SR0_5 DMA_PERIPHERAL_REQUEST(5, 15) 225 #endif 226 227 /* 228 * DMA LINE 6 of DMA0 229 */ 230 231 #define DMA0_PERIPHERAL_REQUEST_ERU0_SR3_6 DMA_PERIPHERAL_REQUEST(6, 0) 232 #define DMA0_PERIPHERAL_REQUEST_VADC_C0SR1_6 DMA_PERIPHERAL_REQUEST(6, 1) 233 #define DMA0_PERIPHERAL_REQUEST_VADC_G0SR2_6 DMA_PERIPHERAL_REQUEST(6, 2) 234 #define DMA0_PERIPHERAL_REQUEST_VADC_G1SR1_6 DMA_PERIPHERAL_REQUEST(6, 3) 235 236 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 237 #define DMA0_PERIPHERAL_REQUEST_VADC_G2SR3_6 DMA_PERIPHERAL_REQUEST(6, 4) 238 #define DMA0_PERIPHERAL_REQUEST_DSD_SRM1_6 DMA_PERIPHERAL_REQUEST(6, 5) 239 #define DMA0_PERIPHERAL_REQUEST_DSD_SRM3_6 DMA_PERIPHERAL_REQUEST(6, 6) 240 #endif 241 242 #define DMA0_PERIPHERAL_REQUEST_CCU41_SR1_6 DMA_PERIPHERAL_REQUEST(6, 7) 243 244 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 245 #define DMA0_PERIPHERAL_REQUEST_CCU81_SR1_6 DMA_PERIPHERAL_REQUEST(6, 8) 246 #endif 247 248 #define DMA0_PERIPHERAL_REQUEST_CAN_SR3_6 DMA_PERIPHERAL_REQUEST(6, 10) 249 #define DMA0_PERIPHERAL_REQUEST_USIC0_SR1_6 DMA_PERIPHERAL_REQUEST(6, 11) 250 #define DMA0_PERIPHERAL_REQUEST_USIC1_SR1_6 DMA_PERIPHERAL_REQUEST(6, 12) 251 252 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 253 #define DMA0_PERIPHERAL_REQUEST_VADC_G3SR0_6 DMA_PERIPHERAL_REQUEST(6, 13) 254 #define DMA0_PERIPHERAL_REQUEST_CCU43_SR1_6 DMA_PERIPHERAL_REQUEST(6, 14) 255 #endif 256 257 /* 258 * DMA LINE 7 of DMA0 259 */ 260 261 #define DMA0_PERIPHERAL_REQUEST_ERU0_SR0_7 DMA_PERIPHERAL_REQUEST(7, 0) 262 #define DMA0_PERIPHERAL_REQUEST_VADC_C0SR0_7 DMA_PERIPHERAL_REQUEST(7, 1) 263 #define DMA0_PERIPHERAL_REQUEST_VADC_G0SR3_7 DMA_PERIPHERAL_REQUEST(7, 2) 264 #define DMA0_PERIPHERAL_REQUEST_VADC_G1SR0_7 DMA_PERIPHERAL_REQUEST(7, 3) 265 #define DMA0_PERIPHERAL_REQUEST_VADC_G1SR3_7 DMA_PERIPHERAL_REQUEST(7, 4) 266 267 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 268 #define DMA0_PERIPHERAL_REQUEST_DSD_SRM0_7 DMA_PERIPHERAL_REQUEST(7, 5) 269 #endif 270 271 #define DMA0_PERIPHERAL_REQUEST_CCU41_SR1_7 DMA_PERIPHERAL_REQUEST(7, 6) 272 273 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 274 #define DMA0_PERIPHERAL_REQUEST_CCU81_SR1_7 DMA_PERIPHERAL_REQUEST(7, 7) 275 #endif 276 277 #define DMA0_PERIPHERAL_REQUEST_CAN_SR3_7 DMA_PERIPHERAL_REQUEST(7, 9) 278 #define DMA0_PERIPHERAL_REQUEST_USIC0_SR1_7 DMA_PERIPHERAL_REQUEST(7, 10) 279 #define DMA0_PERIPHERAL_REQUEST_USIC1_SR1_7 DMA_PERIPHERAL_REQUEST(7, 11) 280 281 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || (UC_SERIES == XMC45) || (UC_SERIES == XMC44)) 282 #define DMA0_PERIPHERAL_REQUEST_VADC_G3SR3_7 DMA_PERIPHERAL_REQUEST(7, 13) 283 #define DMA0_PERIPHERAL_REQUEST_CCU43_SR1_7 DMA_PERIPHERAL_REQUEST(7, 14) 284 #endif 285 286 #if ((UC_SERIES == XMC44) || (UC_SERIES == XMC42) || (UC_SERIES == XMC41)) 287 #define DMA0_PERIPHERAL_REQUEST_HRPWM0_SR1_7 DMA_PERIPHERAL_REQUEST(7, 15) 288 #endif 289 290 #if ((UC_SERIES == XMC48) || (UC_SERIES == XMC47) || UC_SERIES == XMC45) 291 /* 292 * DMA LINE 0 of DMA1 293 */ 294 295 #define DMA1_PERIPHERAL_REQUEST_ERU0_SR0_8 DMA_PERIPHERAL_REQUEST(0, 0) 296 #define DMA1_PERIPHERAL_REQUEST_VADC_C0SR0_8 DMA_PERIPHERAL_REQUEST(0, 1) 297 #define DMA1_PERIPHERAL_REQUEST_VADC_G3SR0_8 DMA_PERIPHERAL_REQUEST(0, 2) 298 #define DMA1_PERIPHERAL_REQUEST_DSD_SRM0_8 DMA_PERIPHERAL_REQUEST(0, 3) 299 #define DMA1_PERIPHERAL_REQUEST_DAC_SR0_8 DMA_PERIPHERAL_REQUEST(0, 4) 300 #define DMA1_PERIPHERAL_REQUEST_CCU42_SR0_8 DMA_PERIPHERAL_REQUEST(0, 5) 301 #define DMA1_PERIPHERAL_REQUEST_USIC2_SR0_8 DMA_PERIPHERAL_REQUEST(0, 6) 302 #define DMA1_PERIPHERAL_REQUEST_USIC2_SR2_8 DMA_PERIPHERAL_REQUEST(0, 7) 303 304 /* 305 * DMA LINE 1 of DMA1 306 */ 307 308 #define DMA1_PERIPHERAL_REQUEST_ERU0_SR1_9 DMA_PERIPHERAL_REQUEST(1, 0) 309 #define DMA1_PERIPHERAL_REQUEST_VADC_C0SR1_9 DMA_PERIPHERAL_REQUEST(1, 1) 310 #define DMA1_PERIPHERAL_REQUEST_VADC_G3SR1_9 DMA_PERIPHERAL_REQUEST(1, 2) 311 #define DMA1_PERIPHERAL_REQUEST_DSD_SRM1_9 DMA_PERIPHERAL_REQUEST(1, 3) 312 #define DMA1_PERIPHERAL_REQUEST_DAC_SR1_9 DMA_PERIPHERAL_REQUEST(1, 4) 313 #define DMA1_PERIPHERAL_REQUEST_CCU42_SR1_9 DMA_PERIPHERAL_REQUEST(1, 5) 314 #define DMA1_PERIPHERAL_REQUEST_USIC2_SR1_9 DMA_PERIPHERAL_REQUEST(1, 6) 315 #define DMA1_PERIPHERAL_REQUEST_USIC2_SR3_9 DMA_PERIPHERAL_REQUEST(1, 7) 316 317 /* 318 * DMA LINE 2 of DMA1 319 */ 320 321 #define DMA1_PERIPHERAL_REQUEST_ERU0_SR2_10 DMA_PERIPHERAL_REQUEST(2, 0) 322 #define DMA1_PERIPHERAL_REQUEST_VADC_C0SR2_10 DMA_PERIPHERAL_REQUEST(2, 1) 323 #define DMA1_PERIPHERAL_REQUEST_VADC_G3SR2_10 DMA_PERIPHERAL_REQUEST(2, 2) 324 #define DMA1_PERIPHERAL_REQUEST_DSD_SRM2_10 DMA_PERIPHERAL_REQUEST(2, 3) 325 #define DMA1_PERIPHERAL_REQUEST_DAC_SR0_10 DMA_PERIPHERAL_REQUEST(2, 4) 326 #define DMA1_PERIPHERAL_REQUEST_CCU43_SR0_10 DMA_PERIPHERAL_REQUEST(2, 5) 327 #define DMA1_PERIPHERAL_REQUEST_USIC2_SR0_10 DMA_PERIPHERAL_REQUEST(2, 6) 328 #define DMA1_PERIPHERAL_REQUEST_USIC2_SR2_10 DMA_PERIPHERAL_REQUEST(2, 7) 329 330 /* 331 * DMA LINE 3 of DMA1 332 */ 333 334 #define DMA1_PERIPHERAL_REQUEST_ERU0_SR3_11 DMA_PERIPHERAL_REQUEST(3, 0) 335 #define DMA1_PERIPHERAL_REQUEST_VADC_C0SR3_11 DMA_PERIPHERAL_REQUEST(3, 1) 336 #define DMA1_PERIPHERAL_REQUEST_VADC_G3SR3_11 DMA_PERIPHERAL_REQUEST(3, 2) 337 #define DMA1_PERIPHERAL_REQUEST_DSD_SRM3_11 DMA_PERIPHERAL_REQUEST(3, 3) 338 #define DMA1_PERIPHERAL_REQUEST_DAC_SR1_11 DMA_PERIPHERAL_REQUEST(3, 4) 339 #define DMA1_PERIPHERAL_REQUEST_CCU43_SR1_11 DMA_PERIPHERAL_REQUEST(3, 5) 340 #define DMA1_PERIPHERAL_REQUEST_USIC2_SR1_11 DMA_PERIPHERAL_REQUEST(3, 6) 341 #define DMA1_PERIPHERAL_REQUEST_USIC2_SR3_11 DMA_PERIPHERAL_REQUEST(3, 7) 342 343 #endif /* (UC_SERIES == XMC45) */ 344 345 #endif /* XMC_DMA_MAP_H */ 346
