1 /***************************************************************************//** 2 * \file cy_ephy.h 3 * \version 1.10 4 * 5 * Provides an API declaration of the Ethernet Generic PHY driver 6 * 7 ******************************************************************************** 8 * \copyright 9 * Copyright 2020 Cypress Semiconductor Corporation 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 *******************************************************************************/ 24 25 /** 26 * \addtogroup group_ephy 27 * \{ 28 * The PHY chip is outside of SoC. It has 15 IEEE specified standard registers. 29 * The EPHY driver implements those standard registers. It provides an API for 30 * PHY management abstraction layer. 31 * 32 * The functions and other declarations used in this driver are in cy_ephy.h. 33 * You can include cy_pdl.h (ModusToolbox only) to get access to all functions 34 * and declarations in the PDL. 35 * 36 * \note Apart from IEEE standard registers, optionally it has some vendor 37 * specific extended registers. The EPHY driver does not implement extended 38 * registers. Any access to PHY registers can be done by using MAC driver APIs, 39 * i.e, \ref Cy_ETHIF_PhyRegRead() and \ref Cy_ETHIF_PhyRegWrite(). 40 * 41 * 42 * \section group_ephy_configuration Configuration Considerations 43 * Code snippet for Initializing DP83867IR PHY chip 44 * 45 * \snippet ethernet/snippet/main.c snippet_Cy_EPHY_DP83867IR_Init 46 * 47 * \section group_ephy_more_information More Information 48 * 49 * Refer to the technical reference manual (TRM) and the device datasheet. 50 * 51 * \section group_ephy_MISRA MISRA-C Compliance 52 * The EPHY driver does not have any specific deviation 53 * 54 * \section group_ephy_Changelog Changelog 55 * <table class="doxtable"> 56 * <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr> 57 * <tr> 58 * <td>1.10</td> 59 * <td>Updated \ref Cy_EPHY_Configure() function and Added new macros for BMSR register.</td> 60 * <td>Bug fixes and support enhancement for 1Gbps configuration.</td> 61 * </tr> 62 * <tr> 63 * <td>1.0</td> 64 * <td>Initial version</td> 65 * <td></td> 66 * </tr> 67 * </table> 68 * 69 * \defgroup group_ephy_macros Macros 70 * \defgroup group_ephy_functions Functions 71 * \defgroup group_ephy_enums Enumerated Types 72 * \defgroup group_ephy_data_structures Data Structures 73 */ 74 75 #if !defined (CY_EPHY_H) 76 #define CY_EPHY_H 77 78 #include "cy_device.h" 79 80 #if defined (CY_IP_MXETH) 81 82 #include <stddef.h> 83 #include "cy_syslib.h" 84 85 #if defined(__cplusplus) 86 extern "C" { 87 #endif 88 89 /** \addtogroup group_ephy_macros 90 * \{ 91 */ 92 93 /** Driver major version */ 94 #define CY_EPHY_DRV_VERSION_MAJOR 1 95 96 /** Driver minor version */ 97 #define CY_EPHY_DRV_VERSION_MINOR 10 98 99 /** EPHY driver ID */ 100 #define CY_EPHY_ID CY_PDL_DRV_ID(0x70U) 101 102 /** \} group_ephy_macros */ 103 104 /*************************************** 105 * Constants 106 ***************************************/ 107 108 /** \cond INTERNAL */ 109 110 #define MIN_PHY_ADDRESS 0 111 #define MAX_PHY_ADDRESS 31 112 113 /** Naming and numbering of basic PHY registers. */ 114 #define PHYREG_00_BMCR (0x00UL) /**< Basic Mode Control Register. */ 115 #define PHYREG_01_BMSR (0x01UL) /**< Basic Mode Status Register. */ 116 #define PHYREG_02_PHYSID1 (0x02UL) /**< PHYS ID 1 */ 117 #define PHYREG_03_PHYSID2 (0x03UL) /**< PHYS ID 2 */ 118 #define PHYREG_04_ANAR (0x04UL) /**< Advertisement control reg */ 119 #define PHYREG_05_ANLPAR (0x05UL) /**< Auto-Negotiation Link Partner Ability Register */ 120 #define PHYREG_10_MSSR (0x0AUL) /**< Master slave status register */ 121 122 /** Bit fields for 'PHYREG_00_BMCR' the 'Basic Mode Control Register'. */ 123 #define PHYBMCR_SPEED_1000_Msk (0x0040UL) /**< Set Network speed. 1:1000Mbps 0:10Mbps */ 124 #define PHYBMCR_SPEED_1000_Pos (6UL) 125 #define PHYBMCR_FULL_DUPLEX_Msk (0x0100UL) /**< Full duplex. */ 126 #define PHYBMCR_FULL_DUPLEX_Pos (8UL) 127 #define PHYBMCR_AN_RESTART_Msk (0x0200UL) /**< Auto negotiation restart. */ 128 #define PHYBMCR_AN_RESTART_Pos (9UL) 129 #define PHYBMCR_ISOLATE_Msk (0x0400UL) /**< 1 = Isolates 0 = Normal operation. */ 130 #define PHYBMCR_ISOLATE_Pos (10UL) 131 #define PHYBMCR_AN_ENABLE_Msk (0x1000UL) /**< Enable auto negotiation. */ 132 #define PHYBMCR_AN_ENABLE_Pos (12UL) 133 #define PHYBMCR_SPEED_100_Msk (0x2000UL) /**< Set Network speed. 1:100Mbps 0:10Mbps */ 134 #define PHYBMCR_SPEED_100_Pos (13UL) 135 #define PHYBMCR_RESET_Msk (0x8000UL) /**< Reset the PHY. */ 136 #define PHYBMCR_RESET_Pos (15UL) 137 138 /** Bit fields for 'BMSR', 'Basic Mode Status Register' */ 139 #define PHYBMSR_EXT_CAPABILITY_Msk (0x0001UL) /**< 1 = Extended register capable */ 140 #define PHYBMSR_EXT_CAPABILITY_Pos (0UL) 141 #define PHYBMSR_JABBER_DETECTED_Msk (0x0002UL) /**< 1 = Jabber condition detected */ 142 #define PHYBMSR_JABBER_DETECTED_Pos (1UL) 143 #define PHYBMSR_LINK_STATUS_Msk (0x0004UL) /**< Link Status. 1=Link was good since last read of this register. (10/100/1000Mbps operation) 0=Link was lost since last read of this register.*/ 144 #define PHYBMSR_LINK_STATUS_Pos (2UL) 145 #define PHYBMSR_AN_ABILITY_Msk (0x0008UL) /**< 1 = Device is able to perform Auto-Negotiation.*/ 146 #define PHYBMSR_AN_ABILITY_Pos (3UL) 147 #define PHYBMSR_REMOTE_FAULT_Msk (0x0010UL) /**< 1 = Remote Fault condition detected. 0 = No remote fault condition detected */ 148 #define PHYBMSR_REMOTE_FAULT_Pos (4UL) 149 #define PHYBMSR_AN_COMPLETE_Msk (0x0020UL) /**< 1 = Auto-Negotiation process completed. 0 = Auto-Negotiation process not complete. */ 150 #define PHYBMSR_AN_COMPLETE_Pos (5UL) 151 #define PHYBMSR_EXT_STATUS_Msk (0x0100UL) /**< 1 = Extended status present in Reg.15 0 = Extended status not present. */ 152 #define PHYBMSR_EXT_STATUS_Pos (8UL) 153 #define PHYBMSR_100BASE_T2_HD_Msk (0x0200UL) /**< 1 = PHY able to perform half duplex 100BASE-T2. 0 = PHY not able to perform half duplex 100BASE-T2. */ 154 #define PHYBMSR_100BASE_T2_HD_Pos (9UL) 155 #define PHYBMSR_100BASE_T2_FD_Msk (0x0400UL) /**< 1 = PHY able to perform full duplex 100BASE-T2. 0 = PHY not able to perform full duplex 100BASE-T2. */ 156 #define PHYBMSR_100BASE_T2_FD_Pos (10UL) 157 #define PHYBMSR_10BASE_T_HD_Msk (0x0800UL) /**< 10BASE-T Half Duplex Capable */ 158 #define PHYBMSR_10BASE_T_HD_Pos (11UL) 159 #define PHYBMSR_10BASE_T_FD_Msk (0x1000UL) /**< 10BASE-T Full Duplex Capable */ 160 #define PHYBMSR_10BASE_T_FD_Pos (12UL) 161 #define PHYBMSR_100BASE_TX_HD_Msk (0x2000UL) /**< 100BASE-TX Half Duplex Capable */ 162 #define PHYBMSR_100BASE_TX_HD_Pos (13UL) 163 #define PHYBMSR_100BASE_TX_FD_Msk (0x4000UL) /**< 100BASE-TX Full Duplex Capable */ 164 #define PHYBMSR_100BASE_TX_FD_Pos (14UL) 165 #define PHYBMSR_100BASE_T4_Msk (0x8000UL) /**< 100BASE-T4 Capable */ 166 #define PHYBMSR_100BASE_T4_Pos (15UL) /**< 100BASE-T4 Capable */ 167 168 /** PHYREG_02_PHYSID1 */ 169 #define PHYID1_OUI_Msk (0xFFFFUL) /**< OUI: 6-21st bits */ 170 #define PHYID1_OUI_Pos (0UL) 171 172 /** PHYREG_03_PHYSID2 */ 173 #define PHYID2_REV_NUM_Msk (0x000FUL) /**< Revision Number */ 174 #define PHYID2_REV_NUM_Pos (0UL) 175 #define PHYID2_MODEL_NUM_Msk (0x03F0UL) /**< Model Number */ 176 #define PHYID2_MODEL_NUM_Pos (4UL) 177 #define PHYID2_OUI_LSB_Msk (0xFC00UL) /**< OUI_LSB: Assign to 0-5th bits of OUI */ 178 #define PHYID2_OUI_LSB_Pos (10UL) 179 180 #define PHYID_ID1_Msk (0xFFFF0000UL) /**< ID1 */ 181 #define PHYID_ID1_Pos (16UL) 182 #define PHYID_ID2_Msk (0xFFFFUL) /**< ID2 */ 183 #define PHYID_ID2_Pos (0UL) 184 185 /* Auto-Negotiation Advertisement Register (ANAR), Address 0x0004 */ 186 /** Description of all capabilities that can be advertised to the peer */ 187 #define PHYANAR_PSB_Msk (0x001FUL) /**< Protocol Selection Bits. <00001> indicates that this device supports IEEE 802.3. */ 188 #define PHYANAR_PSB_Pos (0UL) 189 #define PHYANAR_10BASE_T_Msk (0x0020UL) /**< Try for 10mbps half-duplex. */ 190 #define PHYANAR_10BASE_T_Pos (5UL) 191 #define PHYANAR_10BASE_T_FD_Msk (0x0040UL) /**< Try for 10mbps full-duplex. */ 192 #define PHYANAR_10BASE_T_FD_Pos (6UL) 193 #define PHYANAR_100BASE_TX_Msk (0x0080UL) /**< Try for 100mbps half-duplex. */ 194 #define PHYANAR_100BASE_TX_Pos (7UL) 195 #define PHYANAR_100BASE_TX_FD_Msk (0x0100UL) /**< Try for 100mbps full-duplex. */ 196 #define PHYANAR_100BASE_TX_FD_Pos (8UL) 197 #define PHYANAR_ALL_Msk ( PHYANAR_10BASE_T_Msk | PHYANAR_10BASE_T_FD_Msk | PHYANAR_100BASE_TX_Msk | PHYANAR_100BASE_TX_FD_Msk ) 198 199 /* Auto-Negotiation Link Partner Ability Register (ANLPAR), Address 0x0005 */ 200 #define ANLPAR_10_Msk (0x00000020UL) /**< 10BASE-Te Support */ 201 #define ANLPAR_10_Pos (5UL) /**< 10BASE-Te bit position */ 202 #define ANLPAR_10FD_Msk (0x00000040UL) /**< 10BASE-Te Full Duplex Support */ 203 #define ANLPAR_10FD_Pos (6UL) /**< 10BASE-Te Full Duplex bit position */ 204 205 #define ANLPAR_TX_Msk (0x00000080UL) /**< 100BASE-TX Support */ 206 #define ANLPAR_TX_Pos (7UL) /**< 100BASE-TX bit position */ 207 #define ANLPAR_TXFD_Msk (0x00000100UL) /**< 100BASE-TX Full Duplex Support */ 208 #define ANLPAR_TXFD_Pos (8UL) /**< 100BASE-TX Full Duplex bit position */ 209 #define ANLPAR_T4_Msk (0x00000200UL) /**< 100BASE-T4 Support */ 210 #define ANLPAR_T4_Pos (9UL) /**< 100BASE-T4 bit position */ 211 212 /* MASTER-SLAVE status register (Register 10) */ 213 #define MSSR_1000BASE_T_HALFDUPLEX_Msk (0x00000400UL) /**< 1000BASE-T Half-Duplex Capable */ 214 #define MSSR_1000BASE_T_HALFDUPLEX_Pos (10UL) /**< 1000BASE-T Half-Duplex bit position */ 215 #define MSSR_1000BASE_T_FULLDUPLEX_Msk (0x00000800UL) /**< 1000BASE-T Full-Duplex Capable */ 216 #define MSSR_1000BASE_T_FULLDUPLEX_Pos (11UL) /**< 1000BASE-T Full-Duplex bit position */ 217 218 219 /****************************************************************************** 220 * Global Enumerations definitions 221 ******************************************************************************/ 222 223 /* PHY state machine states */ 224 typedef enum { 225 CY_EPHY_DOWN, /**< PHY device and driver are not ready for anything */ 226 CY_EPHY_READY, /** < PHY is ready to send and receive packets, but the controller is not */ 227 CY_EPHY_UP, /**< The PHY and attached device are ready to do work */ 228 CY_EPHY_AN, /**< The PHY is currently negotiating the link state. Link is therefore down for now */ 229 CY_EPHY_RUNNING, /**< PHY is currently up, running, and possibly sending and/or receiving packets */ 230 } cy_en_ephy_state_t; 231 232 /** \endcond */ 233 234 /** 235 * \addtogroup group_ephy_enums 236 * \{ 237 */ 238 239 /** EPHY Driver error codes */ 240 typedef enum 241 { 242 CY_EPHY_SUCCESS = 0x00U, /**< Returned successful */ 243 CY_EPHY_AN_NOT_SUPPORTED = 0x01U, /**< Auto Negotiation is not supported */ 244 CY_EPHY_INVALID_SPEED = 0x02U, /**< Invalid speed */ 245 CY_EPHY_INVALID_DUPLEX = 0x03U, /**< Invalid duplex */ 246 CY_EPHY_ERROR = CY_EPHY_ID | CY_PDL_STATUS_ERROR | 0x01U, /**< Bad parameter or Generic Error */ 247 } cy_en_ephy_status_t; 248 249 /** PHY Duplex Mode */ 250 typedef enum 251 { 252 CY_EPHY_DUPLEX_HALF, /**< half duplex */ 253 CY_EPHY_DUPLEX_FULL, /**< full duplex */ 254 CY_EPHY_DUPLEX_AUTO /**< both half/full duplex */ 255 } cy_en_ephy_duplex_t; 256 257 /** PHY Speed */ 258 typedef enum 259 { 260 CY_EPHY_SPEED_10, /**< 10Mbps */ 261 CY_EPHY_SPEED_100, /**< 100Mbps */ 262 CY_EPHY_SPEED_1000, /**< 1000Mbps */ 263 CY_EPHY_SPEED_AUTO /**< All 10/100/1000 Mbps */ 264 } cy_en_ephy_speed_t; 265 266 /** \} group_ephy_enums */ 267 268 /****************************************************************************** 269 * Global Data Structure definitions 270 ******************************************************************************/ 271 272 /** 273 * \addtogroup group_ephy_data_structures 274 * \{ 275 */ 276 277 /** PHY read handle to application */ 278 typedef void (*phy_read_handle)(uint32_t phyAddr, uint32_t regAddress, uint32_t *value); 279 280 /** PHY write handle to application */ 281 typedef void (*phy_write_handle)(uint32_t phyAddr, uint32_t regAddress, uint32_t value); 282 283 /** This is the private data structure of EPHY. This has be instantiated by application */ 284 typedef struct cy_stc_ephy 285 { 286 phy_read_handle fnPhyRead; /**< read handle */ 287 phy_write_handle fnPhyWrite; /**< write handle */ 288 uint32_t phyId; /**< phy ID */ 289 cy_en_ephy_state_t state; /**< PHY state */ 290 uint32_t bmcr; /**< store the BMCR value while PHY configuration */ 291 uint32_t anar; /**< store the ANAR value while PHY configuration */ 292 } cy_stc_ephy_t; 293 294 /** EPHY configuration */ 295 typedef struct cy_stc_ephy_config 296 { 297 uint32_t speed; /**< speed */ 298 uint32_t duplex; /**< suplex mode */ 299 } cy_stc_ephy_config_t; 300 301 /** \} group_ephy_data_structures */ 302 303 304 /****************************************************************************** 305 * Global functions * 306 ******************************************************************************/ 307 308 /** 309 * \addtogroup group_ephy_functions 310 * \{ 311 */ 312 313 314 cy_en_ephy_status_t Cy_EPHY_Init(cy_stc_ephy_t *phy, phy_read_handle fnRead, phy_write_handle fnWrite); 315 316 cy_en_ephy_status_t Cy_EPHY_Discover(cy_stc_ephy_t *phy); 317 318 cy_en_ephy_status_t Cy_EPHY_Configure(cy_stc_ephy_t *phy, cy_stc_ephy_config_t *config); 319 320 uint32_t Cy_EPHY_GetLinkStatus(cy_stc_ephy_t *phy); 321 322 cy_en_ephy_status_t Cy_EPHY_Reset(cy_stc_ephy_t *phy); 323 324 uint32_t Cy_EPHY_GetAutoNegotiationStatus(cy_stc_ephy_t *phy); 325 326 cy_en_ephy_status_t Cy_EPHY_getLinkPartnerCapabilities(cy_stc_ephy_t *phy, cy_stc_ephy_config_t *lpConfig); 327 328 329 /** \} group_ephy_functions */ 330 331 332 333 #if defined(__cplusplus) 334 } 335 #endif 336 337 #endif /* CY_IP_MXETH */ 338 339 #endif /* CY_EPHY_H */ 340 341 /** \} group_ephy */ 342 343 /* [] END OF FILE */ 344
