1# CAT1 Hardware Abstraction Layer (HAL) Release Notes 2The CAT1 Hardware Abstraction Layer (HAL) provides an implementation of the Hardware Abstraction Layer for the PSoC™ 6 and XMC7000/T2G-B-H families of chips. This API provides convenience methods for initializing and manipulating different hardware peripherals. Depending on the specific chip being used, not all features may be supported. 3 4On devices which contain multiple cores, this library is supported on all cores. If HAL is used on multiple cores at the same time, the application is responsible for ensuring that each peripheral is only used on one core at a given time. This can be achieved by calling cyhal_hwmgr_reserve() on the core(s) where a particular resource is not expected to be used. This ensures the HAL is aware the resource is in use and does not use it in a conflicting manner. 5 6### What's Included? 7This release of the CAT1 HAL includes support for the following drivers: 8* ADC 9* Clock 10* Comparator 11* CRC 12* DAC 13* DMA 14* EZ-I2C 15* GPIO 16* Hardware Manager 17* KeyScan 18* I2C 19* I2S 20* Interconnect 21* IPC 22* LowPower Timer (LPTimer) 23* NVM (Formerly Flash) 24* OpAmp 25* PDM/PCM 26* Power Management (SysPM) 27* PWM 28* QSPI 29* Quadrature Decoder (QuadDec) 30* RTC 31* SDHC 32* SDIO 33* SPI 34* System 35* TDM 36* Timer 37* True Random Number Generator (TRNG) 38* UART 39* USB Device 40* WDT 41 42### What Changed? 43#### v2.4.1 44* Rename "Flash" driver to "NVM" (Non-Volatile Memory). The existing cyhal_flash APIs are retained as aliases for compatibility purposes. 45* Rename SDIO functions to clarify which apply to host mode only 46* Make GPIO members optional in cyhal_spi_configurator_t 47* Add support for DMA-based asynchronous transfers mode in cyhal_uart 48* Updated pre-production support for CAT1B devices 49#### v2.3.0 50* Add new SPI APIs 51* Fix incorrect base address calculation on some devices in SCB-based drivers (UART, SPI, I2C, EZI2C). 52* Extend documentation on pins and triggers to cover additional devices. 53#### v2.2.0 54* Production support for CAT1C devices 55* Improve interrupt handling when running on on CM0+ core 56* Add new I2C slave APIs 57* Add driver for inter-processor communication (IPC) 58* Add new function `cyhal_system_reset_device` 59NOTE: This version requires udb-sdio-whd 1.2.0 or later 60#### v2.1.0 61* Pre-production support for CAT1B devices 62* Fixed a few bugs in various drivers 63#### v2.0.1 64This patch release addresses issues in several drivers: 65* RTC: 66 1. Do not use RTOS delay even in RTOS-aware mode, to avoid ordering requirements between RTC and RTOS init. 67* PWM: 68 1. Fix incorrect period/duty cycle calculation when a `line_n` (inverted) output pin is used as the sole, 69 non-inverted PWM output. 70* PWM/Timer/QuadDec 71 1. Fix level/edge nature of the source not being honored in `cyhal_*_connect_digital`. 72 2. Add `cyhal_*_connect_digital2` API to allow explicitly specifying edge type (rising/falling/both). This supercedes 73 `cyhal_connect_digital`, which defaults to rising edge when the source is an "edge" signal. 74#### v2.0.0 75This major version update includes changes that break API compatibility with prior releases. Each major or breaking change is described below: 76* Clock: 77 1. Renamed cyhal_resource_inst_t CYHAL_CLOCK_<name> constants with CYHAL_CLOCK_RSC_<name>. Created new CYHAL_CLOCK_<name> constants of type cyhal_clock_t. 78 2. Replaced cyhal_clock_init with cyhal_clock_reserve. 79 3. Removed div_type & div_num from cyhal_clock_t. 80* DMA: 81 1. cyhal_dma_enable must be called after configuring the DMA, but before a trigger will initiate a transfer 82* Flash: 83 1. The data buffer passed to functions must be from SRAM, the driver no longer contains a scratch buffer to copy into. 84* GPIO: 85 1. cyhal_gpio_enable_output updated to require a new argument to specify whether the signal is level or edge based. 86 2. cyhal_gpio_connect_digital no longer takes the signal type parameter. 87 3. cyhal_gpio_register_callback now takes a structure containing details about the callback. 88 4. Removed deprecated functions cyhal_gpio_register_irq & cyhal_gpio_irq_enable 89* I2C: 90 1. Removed deprecated functions cyhal_i2c_register_irq & cyhal_i2c_irq_enable 91* I2S/TDM: 92 1. The mclk GPIO selection is moved into the RX/TX specific pins struct. This allows RX and TX to use separate mclk pins on devices that support this; 93 see the device datasheet for details. For devices which only support a single MCLK pin shared between RX and TX, there is no change in functionality; when 94 calling `cyhal_i2s_init` or `cyhal_tdm_init` the same `cyhal_gpio_t` value should be provided for both RX and TX. 95* PWM: 96 1. cyhal_pwm_connect_digital no longer takes the signal type parameter. 97 2. cyhal_pwm_init will always produce a non-inverted waveform on the specified pin, even if that pin natively produces an inverted 98 output (for example, the `line_compl` pins on PSoC™ devices). This improves consistency with the behavior of cyhal_pwm_init_adv. 99* QSPI: 100 1. cyhal_qspi_init() function got one additional parameter - shared clock (clk), which will allow users to use multiple HAL drivers which depends on same clock source. 101 2. cyhal_qspi_init() now takes io[x] and ssel pins as pointer to cyhal_qspi_slave_pin_config_t structure, that contain mentioned pins. 102 3. cyhal_qspi_slave_select_config function was replaced by cyhal_qspi_slave_configure, which provides possibility to add memory slaves with own data lines (instead of shared data lines and own slave select like it was when cyhal_qspi_slave_select_config has been used). cyhal_qspi_slave_config, as cyhal_qspi_init, takes cyhal_qspi_slave_pin_config_t as parameter. 103 4. cyhal_qspi_command_t structure was updated: address.value field removed, data_rate field was added into all command subsections. 104 5. Added address parameter to all transfer functions (cyhal_qspi_read, cyhal_qspi_read_async, cyhal_qspi_write, cyhal_qspi_write_async anb cyhal_qspi_transfer). 105 6. cyhal_qspi_datarate_t enum was added. Corresponding configuration fields are added into each sub-structure of cyhal_qspi_command_t. 106* SDHC: 107 1. cyhal_sdhc_init() and cyhal_sdhc_init_hw() functions got one additional parameter - shared clock (block_clk), which will allow users to use multiple HAL drivers which depends on same clock source. 108* SDIO: 109 1. Updated the names of enum cyhal_tranfer_t and its types CYHAL_READ and CYHAL_WRITE to cyhal_sdio_transfer_type_t, CYHAL_SDIO_XFER_TYPE_READ, and CYHAL_SDIO_XFER_TYPE_WRITE, respectively. 110 2. Removed deprecated functions cyhal_sdio_register_irq & cyhal_sdio_irq_enable 111* Timer: 112 1. cyhal_timer_connect_digital no longer takes the signal type parameter. 113* UART: 114 1. cyhal_uart_set_flow_control function was replaced by cyhal_uart_enable_flow_control, which only controls the enablement status of flow control. CTS / RTS pins are now provided via cyhal_uart_init() function. 115* I2C: 116 1. The following deprecated functions have been removed: cyhal_i2c_slave_config_write_buff, cyhal_i2c_slave_config_read_buff. 117* Other: 118 1. Removed cyhal_deprecated.h, and all associated code. 119NOTE: This version requires core-lib 1.3.0 or later 120#### v1.6.0 121* Added new TDM driver 122* Added support for 1.8v devices to SDHC/SDIO drivers 123* Extended System driver to support registering for other interrupts 124* Fixed issues with level trigger signals to the DMA driver 125* Fixed a few bugs in various drivers 126#### v1.5.0 127* Added new Quadrature Decoder (QuadDec) driver 128* Added digital hardware connection APIs to drivers 129* Fixed a few bugs in various drivers 130* Updated SDHC and MXSDHC-based SDIO communication functions to use semaphores in RTOS aware environments for improved performance 131* Added optional implementations for SDHC control pin APIs and RTOS aware delay API provided as weak functions in the PDL (Disabled by: DEFINES+=CYHAL_DISABLE_WEAK_FUNC_IMPL) 132#### v1.4.0 133* Renamed library from psoc6hal to mtb-hal-cat1 134* Added support for new PSoC™ 6 S4 devices 135* Extended clock support for QSPI and SDHC drivers 136* Fixed a few bugs in various drivers 137* Minor documentation updates 138#### v1.3.0 139* Added new Analog Comparator driver 140* Added new OpAmp driver 141* Extended ADC driver 142* Extended DAC driver 143* Extended SPI/QSPI drivers to support multiple slave select signals 144* Fixed SDHC based SDIO cyhal_sdio_is_busy() function to return status immediately instead of waiting until the transfer completes 145* Fixed a few bugs in various drivers 146* Minor update for documentation & branding 147#### v1.2.1 148* Added new option for SysPM driver to support tickless sleep in addition to deepsleep 149* Fixed an issue with deep-sleep wake-up in the SDIO and SDHC drivers that could cause intermittent communication failures 150* Minor bug fixes and documentation improvements 151#### v1.2.0 152* Added new Clock driver 153* Added new SysPM Power Management driver 154* Added new I2S driver 155* Added new PDM/PCM driver 156* Reduced flash memory usage for a number of drivers 157* Improved documentation for a number of drivers 158* Fixed a few bugs in various drivers 159NOTE: The new SysPM driver needs to be initialized by calling cyhal_syspm_init(). This is done automatically by Board Support Packages version 1.2.0 and later. 160#### v1.1.1 161* Improved documentation for a number of drivers 162* Fixed duplicate symbol definition with PDL 1.4.1 release 163* Minor bug fixes 164#### v1.1.0 165* Added new DMA driver 166* Added new EZ-I2C driver 167* Extended System driver to allow getting information about reset 168* Extended System driver to provide delay functions 169* Updated PWM driver to provide additional configuration options 170* Updated Timer driver to allow reading the current count 171* Updated RTC driver to support Day Light Savings time 172* Updated LP Timer driver to improve performance 173* Minor updates up avoid potential warnings on some toolchains 174* Multiple bug fixes across drivers 175#### v1.0.0 176* Initial release (ADC, CRC, DAC, Flash, GPIO, Hardware Manager, I2C, LP Timer, PWM, QSPI, RTC, SDHC, SDIO, SPI, System, Timer, TRNG, UART, USB Device, WDT) 177 178### Supported Software and Tools 179This version of the CAT1 Hardware Abstraction Layer was validated for compatibility with the following Software and Tools: 180 181| Software and Tools | Version | 182| :--- | :----: | 183| ModusToolbox™ Software Environment | 3.1.0 | 184| GCC Compiler | 11.3.1 | 185| IAR Compiler | 9.30.1 | 186| ARM Compiler | 6.16 | 187 188Minimum required ModusToolbox™ Software Environment: v2.0 189 190### More information 191Use the following links for more information, as needed: 192* [API Reference Guide](https://infineon.github.io/mtb-hal-cat1/html/modules.html) 193* [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com) 194* [Infineon GitHub](https://github.com/infineon) 195* [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment) 196 197--- 198© Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2023. 199
