1 /***************************************************************************//** 2 * \file cyhal_triggers_cyw20829.c 3 * 4 * \brief 5 * CYW20829 family HAL triggers header 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #include "cy_device_headers.h" 28 #include "cyhal_hw_types.h" 29 30 #if (defined(CY_DEVICE_CYW20829) && (CY_SYSLIB_GET_SILICON_REV_ID == CY_SYSLIB_20829B0_SILICON_REV)) 31 #include "triggers/cyhal_triggers_cyw20829.h" 32 33 const uint16_t cyhal_sources_per_mux[15] = 34 { 35 26, 54, 54, 46, 64, 3, 19, 2, 3, 3, 4, 5, 1, 1, 2, 36 }; 37 38 const bool cyhal_is_mux_1to1[15] = 39 { 40 false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, 41 }; 42 43 const _cyhal_trigger_source_cyw20829_t cyhal_mux0_sources[26] = 44 { 45 _CYHAL_TRIGGER_CPUSS_ZERO, 46 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, 47 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, 48 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, 49 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, 50 _CYHAL_TRIGGER_TCPWM0_TR_OUT00, 51 _CYHAL_TRIGGER_TCPWM0_TR_OUT10, 52 _CYHAL_TRIGGER_TCPWM0_TR_OUT01, 53 _CYHAL_TRIGGER_TCPWM0_TR_OUT11, 54 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0, 55 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1, 56 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2, 57 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3, 58 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4, 59 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5, 60 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6, 61 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7, 62 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, 63 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, 64 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DC, 65 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DATA, 66 _CYHAL_TRIGGER_TDM_TR_TX_REQ0, 67 _CYHAL_TRIGGER_TDM_TR_RX_REQ0, 68 _CYHAL_TRIGGER_PDM_TR_RX_REQ0, 69 _CYHAL_TRIGGER_PDM_TR_RX_REQ1, 70 _CYHAL_TRIGGER_CRYPTO_TR_TRNG_BITSTREAM, 71 }; 72 73 const _cyhal_trigger_source_cyw20829_t cyhal_mux1_sources[54] = 74 { 75 _CYHAL_TRIGGER_CPUSS_ZERO, 76 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, 77 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, 78 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, 79 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, 80 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, 81 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, 82 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, 83 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, 84 _CYHAL_TRIGGER_TCPWM0_TR_OUT00, 85 _CYHAL_TRIGGER_TCPWM0_TR_OUT10, 86 _CYHAL_TRIGGER_TCPWM0_TR_OUT01, 87 _CYHAL_TRIGGER_TCPWM0_TR_OUT11, 88 _CYHAL_TRIGGER_TCPWM0_TR_OUT0256, 89 _CYHAL_TRIGGER_TCPWM0_TR_OUT1256, 90 _CYHAL_TRIGGER_TCPWM0_TR_OUT0257, 91 _CYHAL_TRIGGER_TCPWM0_TR_OUT1257, 92 _CYHAL_TRIGGER_TCPWM0_TR_OUT0258, 93 _CYHAL_TRIGGER_TCPWM0_TR_OUT1258, 94 _CYHAL_TRIGGER_TCPWM0_TR_OUT0259, 95 _CYHAL_TRIGGER_TCPWM0_TR_OUT1259, 96 _CYHAL_TRIGGER_TCPWM0_TR_OUT0260, 97 _CYHAL_TRIGGER_TCPWM0_TR_OUT1260, 98 _CYHAL_TRIGGER_TCPWM0_TR_OUT0261, 99 _CYHAL_TRIGGER_TCPWM0_TR_OUT1261, 100 _CYHAL_TRIGGER_TCPWM0_TR_OUT0262, 101 _CYHAL_TRIGGER_TCPWM0_TR_OUT1262, 102 _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, 103 _CYHAL_TRIGGER_SCB0_TR_TX_REQ, 104 _CYHAL_TRIGGER_SCB0_TR_RX_REQ, 105 _CYHAL_TRIGGER_CRYPTO_TR_TRNG_BITSTREAM, 106 _CYHAL_TRIGGER_SCB1_TR_TX_REQ, 107 _CYHAL_TRIGGER_SCB1_TR_RX_REQ, 108 _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, 109 _CYHAL_TRIGGER_SCB2_TR_TX_REQ, 110 _CYHAL_TRIGGER_SCB2_TR_RX_REQ, 111 _CYHAL_TRIGGER_SMIF_TR_TX_REQ, 112 _CYHAL_TRIGGER_SMIF_TR_RX_REQ, 113 _CYHAL_TRIGGER_TDM_TR_TX_REQ0, 114 _CYHAL_TRIGGER_TDM_TR_RX_REQ0, 115 _CYHAL_TRIGGER_PDM_TR_RX_REQ0, 116 _CYHAL_TRIGGER_PDM_TR_RX_REQ1, 117 _CYHAL_TRIGGER_PDM_TR_RX_REQ_ALL, 118 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0, 119 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1, 120 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2, 121 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3, 122 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, 123 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, 124 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DC, 125 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DATA, 126 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, 127 _CYHAL_TRIGGER_BTSS_TR_TX_START, 128 _CYHAL_TRIGGER_BTSS_TR_RX_PACKET_SYNC, 129 }; 130 131 const _cyhal_trigger_source_cyw20829_t cyhal_mux2_sources[54] = 132 { 133 _CYHAL_TRIGGER_CPUSS_ZERO, 134 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, 135 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, 136 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, 137 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, 138 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, 139 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, 140 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, 141 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, 142 _CYHAL_TRIGGER_TCPWM0_TR_OUT00, 143 _CYHAL_TRIGGER_TCPWM0_TR_OUT10, 144 _CYHAL_TRIGGER_TCPWM0_TR_OUT01, 145 _CYHAL_TRIGGER_TCPWM0_TR_OUT11, 146 _CYHAL_TRIGGER_TCPWM0_TR_OUT0256, 147 _CYHAL_TRIGGER_TCPWM0_TR_OUT1256, 148 _CYHAL_TRIGGER_TCPWM0_TR_OUT0257, 149 _CYHAL_TRIGGER_TCPWM0_TR_OUT1257, 150 _CYHAL_TRIGGER_TCPWM0_TR_OUT0258, 151 _CYHAL_TRIGGER_TCPWM0_TR_OUT1258, 152 _CYHAL_TRIGGER_TCPWM0_TR_OUT0259, 153 _CYHAL_TRIGGER_TCPWM0_TR_OUT1259, 154 _CYHAL_TRIGGER_TCPWM0_TR_OUT0260, 155 _CYHAL_TRIGGER_TCPWM0_TR_OUT1260, 156 _CYHAL_TRIGGER_TCPWM0_TR_OUT0261, 157 _CYHAL_TRIGGER_TCPWM0_TR_OUT1261, 158 _CYHAL_TRIGGER_TCPWM0_TR_OUT0262, 159 _CYHAL_TRIGGER_TCPWM0_TR_OUT1262, 160 _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, 161 _CYHAL_TRIGGER_SCB0_TR_TX_REQ, 162 _CYHAL_TRIGGER_SCB0_TR_RX_REQ, 163 _CYHAL_TRIGGER_CRYPTO_TR_TRNG_BITSTREAM, 164 _CYHAL_TRIGGER_SCB1_TR_TX_REQ, 165 _CYHAL_TRIGGER_SCB1_TR_RX_REQ, 166 _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, 167 _CYHAL_TRIGGER_SCB2_TR_TX_REQ, 168 _CYHAL_TRIGGER_SCB2_TR_RX_REQ, 169 _CYHAL_TRIGGER_SMIF_TR_TX_REQ, 170 _CYHAL_TRIGGER_SMIF_TR_RX_REQ, 171 _CYHAL_TRIGGER_TDM_TR_TX_REQ0, 172 _CYHAL_TRIGGER_TDM_TR_RX_REQ0, 173 _CYHAL_TRIGGER_PDM_TR_RX_REQ0, 174 _CYHAL_TRIGGER_PDM_TR_RX_REQ1, 175 _CYHAL_TRIGGER_PDM_TR_RX_REQ_ALL, 176 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4, 177 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5, 178 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6, 179 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7, 180 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, 181 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, 182 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DC, 183 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DATA, 184 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, 185 _CYHAL_TRIGGER_BTSS_TR_TX_START, 186 _CYHAL_TRIGGER_BTSS_TR_RX_PACKET_SYNC, 187 }; 188 189 const _cyhal_trigger_source_cyw20829_t cyhal_mux3_sources[46] = 190 { 191 _CYHAL_TRIGGER_CPUSS_ZERO, 192 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, 193 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, 194 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, 195 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, 196 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, 197 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, 198 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, 199 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, 200 _CYHAL_TRIGGER_TCPWM0_TR_OUT00, 201 _CYHAL_TRIGGER_TCPWM0_TR_OUT10, 202 _CYHAL_TRIGGER_TCPWM0_TR_OUT01, 203 _CYHAL_TRIGGER_TCPWM0_TR_OUT11, 204 _CYHAL_TRIGGER_TCPWM0_TR_OUT0256, 205 _CYHAL_TRIGGER_TCPWM0_TR_OUT1256, 206 _CYHAL_TRIGGER_TCPWM0_TR_OUT0257, 207 _CYHAL_TRIGGER_TCPWM0_TR_OUT1257, 208 _CYHAL_TRIGGER_TCPWM0_TR_OUT0258, 209 _CYHAL_TRIGGER_TCPWM0_TR_OUT1258, 210 _CYHAL_TRIGGER_TCPWM0_TR_OUT0259, 211 _CYHAL_TRIGGER_TCPWM0_TR_OUT1259, 212 _CYHAL_TRIGGER_TCPWM0_TR_OUT0260, 213 _CYHAL_TRIGGER_TCPWM0_TR_OUT1260, 214 _CYHAL_TRIGGER_TCPWM0_TR_OUT0261, 215 _CYHAL_TRIGGER_TCPWM0_TR_OUT1261, 216 _CYHAL_TRIGGER_TCPWM0_TR_OUT0262, 217 _CYHAL_TRIGGER_TCPWM0_TR_OUT1262, 218 _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, 219 _CYHAL_TRIGGER_SCB0_TR_TX_REQ, 220 _CYHAL_TRIGGER_SCB0_TR_RX_REQ, 221 _CYHAL_TRIGGER_CRYPTO_TR_TRNG_BITSTREAM, 222 _CYHAL_TRIGGER_SCB1_TR_TX_REQ, 223 _CYHAL_TRIGGER_SCB1_TR_RX_REQ, 224 _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, 225 _CYHAL_TRIGGER_SCB2_TR_TX_REQ, 226 _CYHAL_TRIGGER_SCB2_TR_RX_REQ, 227 _CYHAL_TRIGGER_TDM_TR_TX_REQ0, 228 _CYHAL_TRIGGER_TDM_TR_RX_REQ0, 229 _CYHAL_TRIGGER_PDM_TR_RX_REQ0, 230 _CYHAL_TRIGGER_PDM_TR_RX_REQ1, 231 _CYHAL_TRIGGER_PDM_TR_RX_REQ_ALL, 232 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, 233 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, 234 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DC, 235 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DATA, 236 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, 237 }; 238 239 const _cyhal_trigger_source_cyw20829_t cyhal_mux4_sources[64] = 240 { 241 _CYHAL_TRIGGER_CPUSS_ZERO, 242 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0, 243 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1, 244 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2, 245 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3, 246 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4, 247 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5, 248 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6, 249 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7, 250 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, 251 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, 252 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, 253 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11, 254 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12, 255 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13, 256 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14, 257 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15, 258 _CYHAL_TRIGGER_TCPWM0_TR_OUT00, 259 _CYHAL_TRIGGER_TCPWM0_TR_OUT10, 260 _CYHAL_TRIGGER_TCPWM0_TR_OUT01, 261 _CYHAL_TRIGGER_TCPWM0_TR_OUT11, 262 _CYHAL_TRIGGER_TCPWM0_TR_OUT0256, 263 _CYHAL_TRIGGER_TCPWM0_TR_OUT1256, 264 _CYHAL_TRIGGER_TCPWM0_TR_OUT0257, 265 _CYHAL_TRIGGER_TCPWM0_TR_OUT1257, 266 _CYHAL_TRIGGER_TCPWM0_TR_OUT0258, 267 _CYHAL_TRIGGER_TCPWM0_TR_OUT1258, 268 _CYHAL_TRIGGER_TCPWM0_TR_OUT0259, 269 _CYHAL_TRIGGER_TCPWM0_TR_OUT1259, 270 _CYHAL_TRIGGER_TCPWM0_TR_OUT0260, 271 _CYHAL_TRIGGER_TCPWM0_TR_OUT1260, 272 _CYHAL_TRIGGER_TCPWM0_TR_OUT0261, 273 _CYHAL_TRIGGER_TCPWM0_TR_OUT1261, 274 _CYHAL_TRIGGER_TCPWM0_TR_OUT0262, 275 _CYHAL_TRIGGER_TCPWM0_TR_OUT1262, 276 _CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED, 277 _CYHAL_TRIGGER_SCB0_TR_TX_REQ, 278 _CYHAL_TRIGGER_SCB0_TR_RX_REQ, 279 _CYHAL_TRIGGER_CRYPTO_TR_TRNG_BITSTREAM, 280 _CYHAL_TRIGGER_SCB1_TR_TX_REQ, 281 _CYHAL_TRIGGER_SCB1_TR_RX_REQ, 282 _CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED, 283 _CYHAL_TRIGGER_SCB2_TR_TX_REQ, 284 _CYHAL_TRIGGER_SCB2_TR_RX_REQ, 285 _CYHAL_TRIGGER_SMIF_TR_TX_REQ, 286 _CYHAL_TRIGGER_SMIF_TR_RX_REQ, 287 _CYHAL_TRIGGER_TDM_TR_TX_REQ0, 288 _CYHAL_TRIGGER_TDM_TR_RX_REQ0, 289 _CYHAL_TRIGGER_PDM_TR_RX_REQ0, 290 _CYHAL_TRIGGER_PDM_TR_RX_REQ1, 291 _CYHAL_TRIGGER_PDM_TR_RX_REQ_ALL, 292 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN0, 293 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN1, 294 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN2, 295 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN3, 296 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN4, 297 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN5, 298 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN6, 299 _CYHAL_TRIGGER_IOSS_PERI_TR_IO_INPUT_IN7, 300 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, 301 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, 302 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DC, 303 _CYHAL_TRIGGER_ADCMIC_TR_ADCMIC_DATA, 304 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, 305 }; 306 307 const _cyhal_trigger_source_cyw20829_t cyhal_mux5_sources[3] = 308 { 309 _CYHAL_TRIGGER_CPUSS_ZERO, 310 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0, 311 _CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1, 312 }; 313 314 const _cyhal_trigger_source_cyw20829_t cyhal_mux6_sources[19] = 315 { 316 _CYHAL_TRIGGER_CPUSS_ZERO, 317 _CYHAL_TRIGGER_TCPWM0_TR_OUT00, 318 _CYHAL_TRIGGER_TCPWM0_TR_OUT10, 319 _CYHAL_TRIGGER_TCPWM0_TR_OUT01, 320 _CYHAL_TRIGGER_TCPWM0_TR_OUT11, 321 _CYHAL_TRIGGER_TCPWM0_TR_OUT0256, 322 _CYHAL_TRIGGER_TCPWM0_TR_OUT1256, 323 _CYHAL_TRIGGER_TCPWM0_TR_OUT0257, 324 _CYHAL_TRIGGER_TCPWM0_TR_OUT1257, 325 _CYHAL_TRIGGER_TCPWM0_TR_OUT0258, 326 _CYHAL_TRIGGER_TCPWM0_TR_OUT1258, 327 _CYHAL_TRIGGER_TCPWM0_TR_OUT0259, 328 _CYHAL_TRIGGER_TCPWM0_TR_OUT1259, 329 _CYHAL_TRIGGER_TCPWM0_TR_OUT0260, 330 _CYHAL_TRIGGER_TCPWM0_TR_OUT1260, 331 _CYHAL_TRIGGER_TCPWM0_TR_OUT0261, 332 _CYHAL_TRIGGER_TCPWM0_TR_OUT1261, 333 _CYHAL_TRIGGER_TCPWM0_TR_OUT0262, 334 _CYHAL_TRIGGER_TCPWM0_TR_OUT1262, 335 }; 336 337 const _cyhal_trigger_source_cyw20829_t cyhal_mux7_sources[2] = 338 { 339 _CYHAL_TRIGGER_CPUSS_ZERO, 340 _CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0, 341 }; 342 343 const _cyhal_trigger_source_cyw20829_t cyhal_mux8_sources[3] = 344 { 345 _CYHAL_TRIGGER_CPUSS_ZERO, 346 _CYHAL_TRIGGER_SCB0_TR_TX_REQ, 347 _CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0, 348 }; 349 350 const _cyhal_trigger_source_cyw20829_t cyhal_mux9_sources[3] = 351 { 352 _CYHAL_TRIGGER_CPUSS_ZERO, 353 _CYHAL_TRIGGER_SCB0_TR_RX_REQ, 354 _CYHAL_TRIGGER_CANFD0_TR_FIFO00, 355 }; 356 357 const _cyhal_trigger_source_cyw20829_t cyhal_mux10_sources[4] = 358 { 359 _CYHAL_TRIGGER_SCB1_TR_TX_REQ, 360 _CYHAL_TRIGGER_SCB1_TR_RX_REQ, 361 _CYHAL_TRIGGER_SCB2_TR_TX_REQ, 362 _CYHAL_TRIGGER_SCB2_TR_RX_REQ, 363 }; 364 365 const _cyhal_trigger_source_cyw20829_t cyhal_mux11_sources[5] = 366 { 367 _CYHAL_TRIGGER_TDM_TR_TX_REQ0, 368 _CYHAL_TRIGGER_TDM_TR_RX_REQ0, 369 _CYHAL_TRIGGER_PDM_TR_RX_REQ0, 370 _CYHAL_TRIGGER_PDM_TR_RX_REQ1, 371 _CYHAL_TRIGGER_PDM_TR_RX_REQ_ALL, 372 }; 373 374 const _cyhal_trigger_source_cyw20829_t cyhal_mux12_sources[1] = 375 { 376 _CYHAL_TRIGGER_CANFD0_TR_FIFO10, 377 }; 378 379 const _cyhal_trigger_source_cyw20829_t cyhal_mux13_sources[1] = 380 { 381 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8, 382 }; 383 384 const _cyhal_trigger_source_cyw20829_t cyhal_mux14_sources[2] = 385 { 386 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9, 387 _CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10, 388 }; 389 390 const _cyhal_trigger_source_cyw20829_t* cyhal_mux_to_sources[15] = 391 { 392 cyhal_mux0_sources, 393 cyhal_mux1_sources, 394 cyhal_mux2_sources, 395 cyhal_mux3_sources, 396 cyhal_mux4_sources, 397 cyhal_mux5_sources, 398 cyhal_mux6_sources, 399 cyhal_mux7_sources, 400 cyhal_mux8_sources, 401 cyhal_mux9_sources, 402 cyhal_mux10_sources, 403 cyhal_mux11_sources, 404 cyhal_mux12_sources, 405 cyhal_mux13_sources, 406 cyhal_mux14_sources, 407 }; 408 409 const uint8_t cyhal_dest_to_mux[59] = 410 { 411 131, /* CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0 */ 412 7, /* CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0 */ 413 4, /* CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 */ 414 4, /* CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 */ 415 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 */ 416 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 */ 417 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 */ 418 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 */ 419 8, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 */ 420 9, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 */ 421 128, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 */ 422 128, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 */ 423 128, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 */ 424 128, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 */ 425 129, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 */ 426 129, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 */ 427 129, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 */ 428 129, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 */ 429 129, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 */ 430 130, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 */ 431 3, /* CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT0 */ 432 3, /* CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT1 */ 433 132, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER0 */ 434 132, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER1 */ 435 6, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE0 */ 436 6, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE1 */ 437 5, /* CYHAL_TRIGGER_PDM_TR_DBG_FREEZE */ 438 5, /* CYHAL_TRIGGER_PERI_TR_DBG_FREEZE */ 439 4, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 */ 440 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 */ 441 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 */ 442 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 */ 443 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 */ 444 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 */ 445 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 */ 446 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 */ 447 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 */ 448 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 */ 449 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 */ 450 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 */ 451 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 */ 452 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 */ 453 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 */ 454 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 */ 455 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 */ 456 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 */ 457 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 */ 458 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 */ 459 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 */ 460 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 */ 461 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 */ 462 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 */ 463 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 */ 464 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 */ 465 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 */ 466 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 */ 467 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN27 */ 468 5, /* CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE */ 469 5, /* CYHAL_TRIGGER_TDM_TR_DBG_FREEZE */ 470 }; 471 472 const uint8_t cyhal_mux_dest_index[59] = 473 { 474 0, /* CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0 */ 475 0, /* CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0 */ 476 0, /* CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 */ 477 1, /* CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 */ 478 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 */ 479 1, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 */ 480 2, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 */ 481 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 */ 482 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 */ 483 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 */ 484 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 */ 485 1, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 */ 486 2, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 */ 487 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 */ 488 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 */ 489 1, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 */ 490 2, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 */ 491 3, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 */ 492 4, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 */ 493 0, /* CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 */ 494 0, /* CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT0 */ 495 1, /* CYHAL_TRIGGER_IOSS_PERI_TR_IO_OUTPUT_OUT1 */ 496 0, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER0 */ 497 1, /* CYHAL_TRIGGER_LIN0_TR_CMD_TX_HEADER1 */ 498 0, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE0 */ 499 1, /* CYHAL_TRIGGER_PDM_TR_ACTIVATE1 */ 500 1, /* CYHAL_TRIGGER_PDM_TR_DBG_FREEZE */ 501 0, /* CYHAL_TRIGGER_PERI_TR_DBG_FREEZE */ 502 3, /* CYHAL_TRIGGER_SRSS_TR_DEBUG_FREEZE_MCWDT0 */ 503 0, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 */ 504 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 */ 505 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 */ 506 3, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 */ 507 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 */ 508 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 */ 509 6, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 */ 510 7, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 */ 511 8, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 */ 512 9, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 */ 513 10, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 */ 514 11, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 */ 515 12, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 */ 516 13, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 */ 517 0, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 */ 518 1, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 */ 519 2, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 */ 520 3, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 */ 521 4, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 */ 522 5, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 */ 523 6, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 */ 524 7, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 */ 525 8, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 */ 526 9, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 */ 527 10, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 */ 528 11, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 */ 529 12, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 */ 530 13, /* CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN27 */ 531 3, /* CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE */ 532 2, /* CYHAL_TRIGGER_TDM_TR_DBG_FREEZE */ 533 }; 534 535 #endif /* CY_DEVICE_CYW20829 */ 536
