1 2 /** 3 * \cond INTERNAL 4 */ 5 6 #include "cy_device.h" 7 8 //These are all items that should be part of the PDL, but aren't there yet 9 bool Cy_SysClk_PeriPclkGetDividerEnabled(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum); 10 11 #if defined(CY_IP_MXS28SRSS) 12 #define Cy_SysPm_RegisterCallback(handler) (false) 13 #define Cy_SysPm_SystemEnterLp() (CY_RSLT_SUCCESS) 14 #define Cy_SysPm_SystemEnterUlp() (CY_RSLT_SUCCESS) 15 #define Cy_SysPm_IoUnfreeze() 16 #define Cy_SysPm_IoIsFrozen() (false) 17 #else 18 #if !defined(CY_SAR_NUM_CHANNELS) 19 #define CY_SAR_NUM_CHANNELS (16) 20 #define CY_SAR_SEQ_NUM_CHANNELS (16) 21 #define CY_SAR_MAX_NUM_CHANNELS (16) 22 #endif 23 24 #define CY_SAR_INTR_EOS (0) 25 26 #define Cy_SysAnalog_Init(config) (CY_RSLT_SUCCESS) 27 #define Cy_SysAnalog_DeInit(void) 28 #define Cy_SysAnalog_Enable(void) 29 #define Cy_SysAnalog_Disable(void) 30 31 typedef enum 32 { 33 CY_SYSANALOG_STARTUP_NORMAL = 0UL, 34 CY_SYSANALOG_STARTUP_FAST = 1UL, 35 } cy_en_sysanalog_startup_t; 36 typedef enum 37 { 38 CY_SYSANALOG_IZTAT_SOURCE_SRSS = 0UL, 39 CY_SYSANALOG_IZTAT_SOURCE_LOCAL = 1UL 40 } cy_en_sysanalog_iztat_source_t; 41 typedef enum 42 { 43 CY_SYSANALOG_VREF_SOURCE_SRSS = 0UL, 44 CY_SYSANALOG_VREF_SOURCE_LOCAL_1_2V = 1UL, 45 CY_SYSANALOG_VREF_SOURCE_EXTERNAL = 2UL 46 } cy_en_sysanalog_vref_source_t; 47 typedef enum 48 { 49 CY_SYSANALOG_DEEPSLEEP_DISABLE = 0UL, 50 CY_SYSANALOG_DEEPSLEEP_IPTAT_1 = 1UL, 51 CY_SYSANALOG_DEEPSLEEP_IPTAT_2 = 2UL, 52 CY_SYSANALOG_DEEPSLEEP_IPTAT_IZTAT_VREF = 3UL 53 } cy_en_sysanalog_deep_sleep_t; 54 typedef struct 55 { 56 cy_en_sysanalog_startup_t startup; 57 cy_en_sysanalog_iztat_source_t iztat; 58 cy_en_sysanalog_vref_source_t vref; 59 cy_en_sysanalog_deep_sleep_t deepSleep; 60 } cy_stc_sysanalog_config_t; 61 extern const cy_stc_sysanalog_config_t Cy_SysAnalog_Fast_Local; 62 63 typedef enum 64 { 65 CY_SAR_RANGE_LOW_SHIFT, 66 CY_SAR_RANGE_HIGH_SHIFT, 67 } cy_en_sar_range_thres_shift_t; 68 typedef enum 69 { 70 CY_SAR_RANGE_COND_BELOW = 0UL, 71 CY_SAR_RANGE_COND_INSIDE = 1UL, 72 CY_SAR_RANGE_COND_ABOVE = 2UL, 73 CY_SAR_RANGE_COND_OUTSIDE = 3UL, 74 } cy_en_sar_range_detect_condition_t; 75 typedef enum 76 { 77 CY_SAR_CLK_PERI = 0UL, 78 CY_SAR_CLK_DEEPSLEEP = 1UL 79 } cy_en_sar_clock_source_t; 80 typedef struct 81 { 82 bool chanId; 83 bool chainToNext; 84 bool clrTrIntrOnRead; 85 uint32_t level; 86 bool trOut; 87 } cy_stc_sar_fifo_config_t; 88 typedef enum 89 { 90 CY_SAR_MUX_SQ_CTRL_P0 = 0, 91 CY_SAR_MUX_SQ_CTRL_P1 = 1, 92 CY_SAR_MUX_SQ_CTRL_P2 = 2, 93 CY_SAR_MUX_SQ_CTRL_P3 = 3, 94 CY_SAR_MUX_SQ_CTRL_P4 = 4, 95 CY_SAR_MUX_SQ_CTRL_P5 = 5, 96 CY_SAR_MUX_SQ_CTRL_P6 = 6, 97 CY_SAR_MUX_SQ_CTRL_P7 = 7, 98 CY_SAR_MUX_SQ_CTRL_VSSA = 8, 99 CY_SAR_MUX_SQ_CTRL_TEMP = 9, 100 CY_SAR_MUX_SQ_CTRL_AMUXBUSA = 10, 101 CY_SAR_MUX_SQ_CTRL_AMUXBUSB = 11, 102 CY_SAR_MUX_SQ_CTRL_SARBUS0 = 12, 103 CY_SAR_MUX_SQ_CTRL_SARBUS1 = 13, 104 } cy_en_sar_mux_switch_sq_ctrl_t; 105 typedef enum 106 { 107 CY_SAR_MUX_FW_P0_VPLUS = 0, 108 CY_SAR_MUX_FW_P1_VPLUS = 0, 109 CY_SAR_MUX_FW_P2_VPLUS = 0, 110 CY_SAR_MUX_FW_P3_VPLUS = 0, 111 CY_SAR_MUX_FW_P4_VPLUS = 0, 112 CY_SAR_MUX_FW_P5_VPLUS = 0, 113 CY_SAR_MUX_FW_P6_VPLUS = 0, 114 CY_SAR_MUX_FW_P7_VPLUS = 0, 115 CY_SAR_MUX_FW_P0_VMINUS = 0, 116 CY_SAR_MUX_FW_P1_VMINUS = 0, 117 CY_SAR_MUX_FW_P2_VMINUS = 0, 118 CY_SAR_MUX_FW_P3_VMINUS = 0, 119 CY_SAR_MUX_FW_P4_VMINUS = 0, 120 CY_SAR_MUX_FW_P5_VMINUS = 0, 121 CY_SAR_MUX_FW_P6_VMINUS = 0, 122 CY_SAR_MUX_FW_P7_VMINUS = 0, 123 CY_SAR_MUX_FW_VSSA_VMINUS = 0, 124 CY_SAR_MUX_FW_TEMP_VPLUS = 0, 125 CY_SAR_MUX_FW_AMUXBUSA_VPLUS = 0, 126 CY_SAR_MUX_FW_AMUXBUSB_VPLUS = 0, 127 CY_SAR_MUX_FW_AMUXBUSA_VMINUS = 0, 128 CY_SAR_MUX_FW_AMUXBUSB_VMINUS = 0, 129 CY_SAR_MUX_FW_SARBUS0_VPLUS = 0, 130 CY_SAR_MUX_FW_SARBUS1_VPLUS = 0, 131 CY_SAR_MUX_FW_SARBUS0_VMINUS = 0, 132 CY_SAR_MUX_FW_SARBUS1_VMINUS = 0, 133 CY_SAR_MUX_FW_P4_COREIO0 = 0, 134 CY_SAR_MUX_FW_P5_COREIO1 = 0, 135 CY_SAR_MUX_FW_P6_COREIO2 = 0, 136 CY_SAR_MUX_FW_P7_COREIO3 = 0, 137 } cy_en_sar_mux_switch_fw_ctrl_t; 138 typedef enum 139 { 140 CY_SAR_CHAN_POS_PIN_ADDR_0 = 0UL, 141 CY_SAR_CHAN_POS_PIN_ADDR_1 = 1UL, 142 CY_SAR_CHAN_POS_PIN_ADDR_2 = 2UL, 143 CY_SAR_CHAN_POS_PIN_ADDR_3 = 3UL, 144 CY_SAR_CHAN_POS_PIN_ADDR_4 = 4UL, 145 CY_SAR_CHAN_POS_PIN_ADDR_5 = 5UL, 146 CY_SAR_CHAN_POS_PIN_ADDR_6 = 6UL, 147 CY_SAR_CHAN_POS_PIN_ADDR_7 = 7UL, 148 } cy_en_sar_chan_config_pos_pin_addr_t; 149 typedef enum 150 { 151 CY_SAR_CHAN_NEG_PIN_ADDR_0 = 0UL, 152 CY_SAR_CHAN_NEG_PIN_ADDR_1 = 1UL, 153 CY_SAR_CHAN_NEG_PIN_ADDR_2 = 2UL, 154 CY_SAR_CHAN_NEG_PIN_ADDR_3 = 3UL, 155 CY_SAR_CHAN_NEG_PIN_ADDR_4 = 4UL, 156 CY_SAR_CHAN_NEG_PIN_ADDR_5 = 5UL, 157 CY_SAR_CHAN_NEG_PIN_ADDR_6 = 6UL, 158 CY_SAR_CHAN_NEG_PIN_ADDR_7 = 7UL, 159 } cy_en_sar_chan_config_neg_pin_addr_t; 160 typedef enum 161 { 162 CY_SAR_NEG_PORT_ADDR_SARMUX = 0UL, 163 CY_SAR_NEG_PORT_ADDR_AROUTE_VIRT2 = 5UL, 164 CY_SAR_NEG_PORT_ADDR_AROUTE_VIRT1 = 6UL, 165 CY_SAR_NEG_PORT_ADDR_SARMUX_VIRT = 7UL, 166 } cy_en_sar_chan_config_neg_port_addr_t; 167 typedef enum 168 { 169 CY_SAR_POS_PORT_ADDR_SARMUX = 0UL, 170 CY_SAR_POS_PORT_ADDR_CTB0 = 1UL, 171 CY_SAR_POS_PORT_ADDR_CTB1 = 2UL, 172 CY_SAR_POS_PORT_ADDR_CTB2 = 3UL, 173 CY_SAR_POS_PORT_ADDR_CTB3 = 4UL, 174 CY_SAR_POS_PORT_ADDR_AROUTE_VIRT2 = 5UL, 175 CY_SAR_POS_PORT_ADDR_AROUTE_VIRT1 = 6UL, 176 CY_SAR_POS_PORT_ADDR_SARMUX_VIRT = 7UL, 177 } cy_en_sar_chan_config_pos_port_addr_t; 178 typedef enum 179 { 180 CY_SAR_VREF_SEL_BGR = 4UL, 181 CY_SAR_VREF_SEL_EXT = 5UL, 182 CY_SAR_VREF_SEL_VDDA_DIV_2 = 6UL, 183 CY_SAR_VREF_SEL_VDDA = 7UL, 184 } cy_en_sar_ctrl_vref_sel_t; 185 typedef enum 186 { 187 CY_SAR_AVG_CNT_2 = 0UL, 188 CY_SAR_AVG_CNT_4 = 1UL, 189 CY_SAR_AVG_CNT_8 = 2UL, 190 CY_SAR_AVG_CNT_16 = 3UL, 191 CY_SAR_AVG_CNT_32 = 4UL, 192 CY_SAR_AVG_CNT_64 = 5UL, 193 CY_SAR_AVG_CNT_128 = 6UL, 194 CY_SAR_AVG_CNT_256 = 7UL, 195 } cy_en_sar_sample_ctrl_avg_cnt_t; 196 typedef enum 197 { 198 CY_SAR_AVG_MODE_SEQUENTIAL_ACCUM = 0UL, 199 CY_SAR_AVG_MODE_SEQUENTIAL_FIXED = 1UL, 200 CY_SAR_AVG_MODE_INTERLEAVED = 2UL, 201 } cy_en_sar_sample_ctrl_avg_mode_t; 202 typedef enum 203 { 204 CY_SAR_NEG_SEL_VSSA_KELVIN = 0UL, 205 CY_SAR_NEG_SEL_P1 = 2UL, 206 CY_SAR_NEG_SEL_P3 = 3UL, 207 CY_SAR_NEG_SEL_P5 = 4UL, 208 CY_SAR_NEG_SEL_P7 = 5UL, 209 CY_SAR_NEG_SEL_ACORE = 6UL, 210 CY_SAR_NEG_SEL_VREF = 7UL, 211 } cy_en_sar_ctrl_neg_sel_t; 212 typedef enum 213 { 214 CY_SAR_COMP_PWR_100 = 0UL, 215 CY_SAR_COMP_PWR_80 = 1UL, 216 CY_SAR_COMP_PWR_60 = 2UL, 217 CY_SAR_COMP_PWR_50 = 3UL, 218 CY_SAR_COMP_PWR_40 = 4UL, 219 CY_SAR_COMP_PWR_30 = 5UL, 220 CY_SAR_COMP_PWR_20 = 6UL, 221 CY_SAR_COMP_PWR_10 = 7UL, 222 } cy_en_sar_ctrl_comp_pwr_t; 223 typedef enum 224 { 225 CY_SAR_CTRL_NEGVREF_FW_ONLY = 0UL, 226 CY_SAR_CTRL_NEGVREF_HW = 1UL, 227 } cy_en_sar_ctrl_hw_ctrl_negvref_t; 228 typedef enum 229 { 230 CY_SAR_DEEPSLEEP_SARMUX_OFF = 0UL, 231 CY_SAR_DEEPSLEEP_SARMUX_ON = 1UL, 232 } cy_en_sar_ctrl_sarmux_deep_sleep_t; 233 typedef enum 234 { 235 CY_SAR_SARSEQ_SWITCH_ENABLE = 0UL, 236 CY_SAR_SARSEQ_SWITCH_DISABLE = 1UL, 237 } cy_en_sar_ctrl_sarseq_routing_switches_t; 238 typedef enum 239 { 240 CY_SAR_DIFFERENTIAL_UNSIGNED = 0UL, 241 CY_SAR_DIFFERENTIAL_SIGNED = 1UL, 242 } cy_en_sar_sample_ctrl_differential_format_t; 243 typedef enum 244 { 245 CY_SAR_TRIGGER_MODE_FW_ONLY = 0UL, 246 CY_SAR_TRIGGER_MODE_FW_AND_HWEDGE = 1UL, 247 CY_SAR_TRIGGER_MODE_FW_AND_HWLEVEL = 2UL, 248 } cy_en_sar_sample_ctrl_trigger_mode_t; 249 typedef enum 250 { 251 CY_SAR_RIGHT_ALIGN = 0UL, 252 CY_SAR_LEFT_ALIGN = 1UL, 253 } cy_en_sar_sample_ctrl_result_align_t; 254 typedef enum 255 { 256 CY_SAR_SINGLE_ENDED_UNSIGNED = 0UL, 257 CY_SAR_SINGLE_ENDED_SIGNED = 1UL, 258 } cy_en_sar_sample_ctrl_single_ended_format_t; 259 typedef enum 260 { 261 CY_SAR_VREF_PWR_100 = 0UL, 262 CY_SAR_VREF_PWR_80 = 1UL, 263 CY_SAR_VREF_PWR_60 = 2UL, 264 CY_SAR_VREF_PWR_50 = 3UL, 265 CY_SAR_VREF_PWR_40 = 4UL, 266 CY_SAR_VREF_PWR_30 = 5UL, 267 CY_SAR_VREF_PWR_20 = 6UL, 268 CY_SAR_VREF_PWR_10 = 7UL, 269 } cy_en_sar_ctrl_pwr_ctrl_vref_t; 270 typedef enum 271 { 272 CY_SAR_CTRL_COMP_DLY_2P5 = 0UL, 273 CY_SAR_CTRL_COMP_DLY_4 = 1UL, 274 CY_SAR_CTRL_COMP_DLY_10 = 2UL, 275 CY_SAR_CTRL_COMP_DLY_12 = 3UL, 276 } cy_en_sar_ctrl_comp_delay_t; 277 typedef enum 278 { 279 CY_SAR_SWITCH_SEQ_CTRL_DISABLE = 0UL, 280 CY_SAR_SWITCH_SEQ_CTRL_ENABLE = 1UL 281 } cy_en_sar_switch_sar_seq_ctrl_t; 282 typedef enum 283 { 284 CY_SAR_BYPASS_CAP_DISABLE = 0UL, 285 CY_SAR_BYPASS_CAP_ENABLE = 1UL, 286 } cy_en_sar_ctrl_bypass_cap_t; 287 typedef enum 288 { 289 CY_SAR_SWITCH_OPEN = 0UL, 290 CY_SAR_SWITCH_CLOSE = 1UL 291 } cy_en_sar_switch_state_t; 292 typedef enum 293 { 294 CY_SAR_CHAN_SINGLE_ENDED = 0UL, 295 CY_SAR_CHAN_DIFFERENTIAL_PAIRED = 1UL, 296 CY_SAR_CHAN_DIFFERENTIAL_UNPAIRED = 2UL, 297 } cy_en_sar_chan_config_input_mode_t; 298 typedef enum 299 { 300 CY_SAR_MUX_SWITCH0 = 0UL, 301 } cy_en_sar_switch_register_sel_t; 302 typedef struct 303 { 304 uint32_t ctrl; 305 uint32_t sampleCtrl; 306 uint32_t sampleTime01; 307 uint32_t sampleTime23; 308 uint32_t rangeThres; 309 cy_en_sar_range_detect_condition_t rangeCond; 310 uint32_t chanEn; 311 uint32_t chanConfig[CY_SAR_NUM_CHANNELS]; 312 uint32_t intrMask; 313 uint32_t satIntrMask; 314 uint32_t rangeIntrMask; 315 uint32_t muxSwitch; 316 uint32_t muxSwitchSqCtrl; 317 bool configRouting; 318 uint32_t vrefMvValue; 319 cy_en_sar_clock_source_t clock; 320 cy_stc_sar_fifo_config_t const * fifoCfgPtr; 321 bool trTimer; 322 bool scanCnt; 323 bool scanCntIntr; 324 } cy_stc_sar_config_t; 325 326 #define CY_SAR_WRK_MAX_12BIT (0x00001000L) 327 #define SAR_SAMPLE_CTRL(x) (SYSTICK_CTRL) 328 #define SAR_CHAN_EN(x) (0) 329 330 #define Cy_SAR_Init(base, config) (CY_RSLT_SUCCESS) 331 #define Cy_SAR_DeInit(base, deInitRouting) (CY_RSLT_SUCCESS) 332 #define Cy_SAR_Enable(base) 333 #define Cy_SAR_Disable(base) 334 #define Cy_SAR_CountsTo_uVolts(base, chan, adcCounts) (0) 335 #define Cy_SAR_SetVssaSarSeqCtrl(base, ctrl) 336 #define Cy_SAR_ClearInterrupt(base, intrMask) 337 #define Cy_SAR_StartConvert(base, startSelect) 338 #define Cy_SAR_GetResult32(base, chan) (0) 339 #define Cy_SAR_SetInterruptMask(base, intrMask) 340 341 #define Cy_SAR_SetOffset(chan, offset) (CY_RSLT_SUCCESS) 342 #define Cy_SAR_SetVssaVminusSwitch(base, state) 343 #define Cy_SAR_StopConvert(base) 344 #define Cy_SAR_SetAnalogSwitch(base, switchSelect, switchMask, state) 345 #define Cy_SAR_SetChanMask(base, enableMask) 346 #define Cy_SAR_SetConvertMode(base, mode) 347 #define Cy_SAR_SetSwitchSarSeqCtrl(base, switchMask, ctrl) 348 #endif 349 350 /** \endcond */ 351
